1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Linaro Limited 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-sm8450.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/clock/qcom,sm8450-camcc.h> 10#include <dt-bindings/clock/qcom,sm8450-dispcc.h> 11#include <dt-bindings/clock/qcom,sm8450-gpucc.h> 12#include <dt-bindings/clock/qcom,sm8450-videocc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/firmware/qcom,scm.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/phy/phy-qcom-qmp.h> 18#include <dt-bindings/power/qcom,rpmhpd.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/interconnect/qcom,icc.h> 21#include <dt-bindings/interconnect/qcom,sm8450.h> 22#include <dt-bindings/reset/qcom,sm8450-gpucc.h> 23#include <dt-bindings/soc/qcom,gpr.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 26#include <dt-bindings/thermal/thermal.h> 27 28/ { 29 interrupt-parent = <&intc>; 30 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 chosen { }; 35 36 clocks { 37 xo_board: xo-board { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <76800000>; 41 }; 42 43 sleep_clk: sleep-clk { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 clock-frequency = <32000>; 47 }; 48 }; 49 50 cpus { 51 #address-cells = <2>; 52 #size-cells = <0>; 53 54 CPU0: cpu@0 { 55 device_type = "cpu"; 56 compatible = "qcom,kryo780"; 57 reg = <0x0 0x0>; 58 enable-method = "psci"; 59 next-level-cache = <&L2_0>; 60 power-domains = <&CPU_PD0>; 61 power-domain-names = "psci"; 62 qcom,freq-domain = <&cpufreq_hw 0>; 63 #cooling-cells = <2>; 64 clocks = <&cpufreq_hw 0>; 65 L2_0: l2-cache { 66 compatible = "cache"; 67 cache-level = <2>; 68 cache-unified; 69 next-level-cache = <&L3_0>; 70 L3_0: l3-cache { 71 compatible = "cache"; 72 cache-level = <3>; 73 cache-unified; 74 }; 75 }; 76 }; 77 78 CPU1: cpu@100 { 79 device_type = "cpu"; 80 compatible = "qcom,kryo780"; 81 reg = <0x0 0x100>; 82 enable-method = "psci"; 83 next-level-cache = <&L2_100>; 84 power-domains = <&CPU_PD1>; 85 power-domain-names = "psci"; 86 qcom,freq-domain = <&cpufreq_hw 0>; 87 #cooling-cells = <2>; 88 clocks = <&cpufreq_hw 0>; 89 L2_100: l2-cache { 90 compatible = "cache"; 91 cache-level = <2>; 92 cache-unified; 93 next-level-cache = <&L3_0>; 94 }; 95 }; 96 97 CPU2: cpu@200 { 98 device_type = "cpu"; 99 compatible = "qcom,kryo780"; 100 reg = <0x0 0x200>; 101 enable-method = "psci"; 102 next-level-cache = <&L2_200>; 103 power-domains = <&CPU_PD2>; 104 power-domain-names = "psci"; 105 qcom,freq-domain = <&cpufreq_hw 0>; 106 #cooling-cells = <2>; 107 clocks = <&cpufreq_hw 0>; 108 L2_200: l2-cache { 109 compatible = "cache"; 110 cache-level = <2>; 111 cache-unified; 112 next-level-cache = <&L3_0>; 113 }; 114 }; 115 116 CPU3: cpu@300 { 117 device_type = "cpu"; 118 compatible = "qcom,kryo780"; 119 reg = <0x0 0x300>; 120 enable-method = "psci"; 121 next-level-cache = <&L2_300>; 122 power-domains = <&CPU_PD3>; 123 power-domain-names = "psci"; 124 qcom,freq-domain = <&cpufreq_hw 0>; 125 #cooling-cells = <2>; 126 clocks = <&cpufreq_hw 0>; 127 L2_300: l2-cache { 128 compatible = "cache"; 129 cache-level = <2>; 130 cache-unified; 131 next-level-cache = <&L3_0>; 132 }; 133 }; 134 135 CPU4: cpu@400 { 136 device_type = "cpu"; 137 compatible = "qcom,kryo780"; 138 reg = <0x0 0x400>; 139 enable-method = "psci"; 140 next-level-cache = <&L2_400>; 141 power-domains = <&CPU_PD4>; 142 power-domain-names = "psci"; 143 qcom,freq-domain = <&cpufreq_hw 1>; 144 #cooling-cells = <2>; 145 clocks = <&cpufreq_hw 1>; 146 L2_400: l2-cache { 147 compatible = "cache"; 148 cache-level = <2>; 149 cache-unified; 150 next-level-cache = <&L3_0>; 151 }; 152 }; 153 154 CPU5: cpu@500 { 155 device_type = "cpu"; 156 compatible = "qcom,kryo780"; 157 reg = <0x0 0x500>; 158 enable-method = "psci"; 159 next-level-cache = <&L2_500>; 160 power-domains = <&CPU_PD5>; 161 power-domain-names = "psci"; 162 qcom,freq-domain = <&cpufreq_hw 1>; 163 #cooling-cells = <2>; 164 clocks = <&cpufreq_hw 1>; 165 L2_500: l2-cache { 166 compatible = "cache"; 167 cache-level = <2>; 168 cache-unified; 169 next-level-cache = <&L3_0>; 170 }; 171 }; 172 173 CPU6: cpu@600 { 174 device_type = "cpu"; 175 compatible = "qcom,kryo780"; 176 reg = <0x0 0x600>; 177 enable-method = "psci"; 178 next-level-cache = <&L2_600>; 179 power-domains = <&CPU_PD6>; 180 power-domain-names = "psci"; 181 qcom,freq-domain = <&cpufreq_hw 1>; 182 #cooling-cells = <2>; 183 clocks = <&cpufreq_hw 1>; 184 L2_600: l2-cache { 185 compatible = "cache"; 186 cache-level = <2>; 187 cache-unified; 188 next-level-cache = <&L3_0>; 189 }; 190 }; 191 192 CPU7: cpu@700 { 193 device_type = "cpu"; 194 compatible = "qcom,kryo780"; 195 reg = <0x0 0x700>; 196 enable-method = "psci"; 197 next-level-cache = <&L2_700>; 198 power-domains = <&CPU_PD7>; 199 power-domain-names = "psci"; 200 qcom,freq-domain = <&cpufreq_hw 2>; 201 #cooling-cells = <2>; 202 clocks = <&cpufreq_hw 2>; 203 L2_700: l2-cache { 204 compatible = "cache"; 205 cache-level = <2>; 206 cache-unified; 207 next-level-cache = <&L3_0>; 208 }; 209 }; 210 211 cpu-map { 212 cluster0 { 213 core0 { 214 cpu = <&CPU0>; 215 }; 216 217 core1 { 218 cpu = <&CPU1>; 219 }; 220 221 core2 { 222 cpu = <&CPU2>; 223 }; 224 225 core3 { 226 cpu = <&CPU3>; 227 }; 228 229 core4 { 230 cpu = <&CPU4>; 231 }; 232 233 core5 { 234 cpu = <&CPU5>; 235 }; 236 237 core6 { 238 cpu = <&CPU6>; 239 }; 240 241 core7 { 242 cpu = <&CPU7>; 243 }; 244 }; 245 }; 246 247 idle-states { 248 entry-method = "psci"; 249 250 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 251 compatible = "arm,idle-state"; 252 idle-state-name = "silver-rail-power-collapse"; 253 arm,psci-suspend-param = <0x40000004>; 254 entry-latency-us = <800>; 255 exit-latency-us = <750>; 256 min-residency-us = <4090>; 257 local-timer-stop; 258 }; 259 260 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 261 compatible = "arm,idle-state"; 262 idle-state-name = "gold-rail-power-collapse"; 263 arm,psci-suspend-param = <0x40000004>; 264 entry-latency-us = <600>; 265 exit-latency-us = <1550>; 266 min-residency-us = <4791>; 267 local-timer-stop; 268 }; 269 }; 270 271 domain-idle-states { 272 CLUSTER_SLEEP_0: cluster-sleep-0 { 273 compatible = "domain-idle-state"; 274 arm,psci-suspend-param = <0x41000044>; 275 entry-latency-us = <1050>; 276 exit-latency-us = <2500>; 277 min-residency-us = <5309>; 278 }; 279 280 CLUSTER_SLEEP_1: cluster-sleep-1 { 281 compatible = "domain-idle-state"; 282 arm,psci-suspend-param = <0x4100c344>; 283 entry-latency-us = <2700>; 284 exit-latency-us = <3500>; 285 min-residency-us = <13959>; 286 }; 287 }; 288 }; 289 290 firmware { 291 scm: scm { 292 compatible = "qcom,scm-sm8450", "qcom,scm"; 293 qcom,dload-mode = <&tcsr 0x13000>; 294 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 295 #reset-cells = <1>; 296 }; 297 }; 298 299 clk_virt: interconnect-0 { 300 compatible = "qcom,sm8450-clk-virt"; 301 #interconnect-cells = <2>; 302 qcom,bcm-voters = <&apps_bcm_voter>; 303 }; 304 305 mc_virt: interconnect-1 { 306 compatible = "qcom,sm8450-mc-virt"; 307 #interconnect-cells = <2>; 308 qcom,bcm-voters = <&apps_bcm_voter>; 309 }; 310 311 memory@a0000000 { 312 device_type = "memory"; 313 /* We expect the bootloader to fill in the size */ 314 reg = <0x0 0xa0000000 0x0 0x0>; 315 }; 316 317 pmu { 318 compatible = "arm,armv8-pmuv3"; 319 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 320 }; 321 322 psci { 323 compatible = "arm,psci-1.0"; 324 method = "smc"; 325 326 CPU_PD0: power-domain-cpu0 { 327 #power-domain-cells = <0>; 328 power-domains = <&CLUSTER_PD>; 329 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 330 }; 331 332 CPU_PD1: power-domain-cpu1 { 333 #power-domain-cells = <0>; 334 power-domains = <&CLUSTER_PD>; 335 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 336 }; 337 338 CPU_PD2: power-domain-cpu2 { 339 #power-domain-cells = <0>; 340 power-domains = <&CLUSTER_PD>; 341 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 342 }; 343 344 CPU_PD3: power-domain-cpu3 { 345 #power-domain-cells = <0>; 346 power-domains = <&CLUSTER_PD>; 347 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 348 }; 349 350 CPU_PD4: power-domain-cpu4 { 351 #power-domain-cells = <0>; 352 power-domains = <&CLUSTER_PD>; 353 domain-idle-states = <&BIG_CPU_SLEEP_0>; 354 }; 355 356 CPU_PD5: power-domain-cpu5 { 357 #power-domain-cells = <0>; 358 power-domains = <&CLUSTER_PD>; 359 domain-idle-states = <&BIG_CPU_SLEEP_0>; 360 }; 361 362 CPU_PD6: power-domain-cpu6 { 363 #power-domain-cells = <0>; 364 power-domains = <&CLUSTER_PD>; 365 domain-idle-states = <&BIG_CPU_SLEEP_0>; 366 }; 367 368 CPU_PD7: power-domain-cpu7 { 369 #power-domain-cells = <0>; 370 power-domains = <&CLUSTER_PD>; 371 domain-idle-states = <&BIG_CPU_SLEEP_0>; 372 }; 373 374 CLUSTER_PD: power-domain-cpu-cluster0 { 375 #power-domain-cells = <0>; 376 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; 377 }; 378 }; 379 380 qup_opp_table_100mhz: opp-table-qup { 381 compatible = "operating-points-v2"; 382 383 opp-50000000 { 384 opp-hz = /bits/ 64 <50000000>; 385 required-opps = <&rpmhpd_opp_min_svs>; 386 }; 387 388 opp-75000000 { 389 opp-hz = /bits/ 64 <75000000>; 390 required-opps = <&rpmhpd_opp_low_svs>; 391 }; 392 393 opp-100000000 { 394 opp-hz = /bits/ 64 <100000000>; 395 required-opps = <&rpmhpd_opp_svs>; 396 }; 397 }; 398 399 reserved_memory: reserved-memory { 400 #address-cells = <2>; 401 #size-cells = <2>; 402 ranges; 403 404 hyp_mem: memory@80000000 { 405 reg = <0x0 0x80000000 0x0 0x600000>; 406 no-map; 407 }; 408 409 xbl_dt_log_mem: memory@80600000 { 410 reg = <0x0 0x80600000 0x0 0x40000>; 411 no-map; 412 }; 413 414 xbl_ramdump_mem: memory@80640000 { 415 reg = <0x0 0x80640000 0x0 0x180000>; 416 no-map; 417 }; 418 419 xbl_sc_mem: memory@807c0000 { 420 reg = <0x0 0x807c0000 0x0 0x40000>; 421 no-map; 422 }; 423 424 aop_image_mem: memory@80800000 { 425 reg = <0x0 0x80800000 0x0 0x60000>; 426 no-map; 427 }; 428 429 aop_cmd_db_mem: memory@80860000 { 430 compatible = "qcom,cmd-db"; 431 reg = <0x0 0x80860000 0x0 0x20000>; 432 no-map; 433 }; 434 435 aop_config_mem: memory@80880000 { 436 reg = <0x0 0x80880000 0x0 0x20000>; 437 no-map; 438 }; 439 440 tme_crash_dump_mem: memory@808a0000 { 441 reg = <0x0 0x808a0000 0x0 0x40000>; 442 no-map; 443 }; 444 445 tme_log_mem: memory@808e0000 { 446 reg = <0x0 0x808e0000 0x0 0x4000>; 447 no-map; 448 }; 449 450 uefi_log_mem: memory@808e4000 { 451 reg = <0x0 0x808e4000 0x0 0x10000>; 452 no-map; 453 }; 454 455 /* secdata region can be reused by apps */ 456 smem: memory@80900000 { 457 compatible = "qcom,smem"; 458 reg = <0x0 0x80900000 0x0 0x200000>; 459 hwlocks = <&tcsr_mutex 3>; 460 no-map; 461 }; 462 463 cpucp_fw_mem: memory@80b00000 { 464 reg = <0x0 0x80b00000 0x0 0x100000>; 465 no-map; 466 }; 467 468 cdsp_secure_heap: memory@80c00000 { 469 reg = <0x0 0x80c00000 0x0 0x4600000>; 470 no-map; 471 }; 472 473 video_mem: memory@85700000 { 474 reg = <0x0 0x85700000 0x0 0x700000>; 475 no-map; 476 }; 477 478 adsp_mem: memory@85e00000 { 479 reg = <0x0 0x85e00000 0x0 0x2100000>; 480 no-map; 481 }; 482 483 slpi_mem: memory@88000000 { 484 reg = <0x0 0x88000000 0x0 0x1900000>; 485 no-map; 486 }; 487 488 cdsp_mem: memory@89900000 { 489 reg = <0x0 0x89900000 0x0 0x2000000>; 490 no-map; 491 }; 492 493 ipa_fw_mem: memory@8b900000 { 494 reg = <0x0 0x8b900000 0x0 0x10000>; 495 no-map; 496 }; 497 498 ipa_gsi_mem: memory@8b910000 { 499 reg = <0x0 0x8b910000 0x0 0xa000>; 500 no-map; 501 }; 502 503 gpu_micro_code_mem: memory@8b91a000 { 504 reg = <0x0 0x8b91a000 0x0 0x2000>; 505 no-map; 506 }; 507 508 spss_region_mem: memory@8ba00000 { 509 reg = <0x0 0x8ba00000 0x0 0x180000>; 510 no-map; 511 }; 512 513 /* First part of the "SPU secure shared memory" region */ 514 spu_tz_shared_mem: memory@8bb80000 { 515 reg = <0x0 0x8bb80000 0x0 0x60000>; 516 no-map; 517 }; 518 519 /* Second part of the "SPU secure shared memory" region */ 520 spu_modem_shared_mem: memory@8bbe0000 { 521 reg = <0x0 0x8bbe0000 0x0 0x20000>; 522 no-map; 523 }; 524 525 mpss_mem: memory@8bc00000 { 526 reg = <0x0 0x8bc00000 0x0 0x13200000>; 527 no-map; 528 }; 529 530 cvp_mem: memory@9ee00000 { 531 reg = <0x0 0x9ee00000 0x0 0x700000>; 532 no-map; 533 }; 534 535 camera_mem: memory@9f500000 { 536 reg = <0x0 0x9f500000 0x0 0x800000>; 537 no-map; 538 }; 539 540 rmtfs_mem: memory@9fd00000 { 541 compatible = "qcom,rmtfs-mem"; 542 reg = <0x0 0x9fd00000 0x0 0x280000>; 543 no-map; 544 545 qcom,client-id = <1>; 546 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 547 }; 548 549 xbl_sc_mem2: memory@a6e00000 { 550 reg = <0x0 0xa6e00000 0x0 0x40000>; 551 no-map; 552 }; 553 554 global_sync_mem: memory@a6f00000 { 555 reg = <0x0 0xa6f00000 0x0 0x100000>; 556 no-map; 557 }; 558 559 /* uefi region can be reused by APPS */ 560 561 /* Linux kernel image is loaded at 0xa0000000 */ 562 563 oem_vm_mem: memory@bb000000 { 564 reg = <0x0 0xbb000000 0x0 0x5000000>; 565 no-map; 566 }; 567 568 mte_mem: memory@c0000000 { 569 reg = <0x0 0xc0000000 0x0 0x20000000>; 570 no-map; 571 }; 572 573 qheebsp_reserved_mem: memory@e0000000 { 574 reg = <0x0 0xe0000000 0x0 0x600000>; 575 no-map; 576 }; 577 578 cpusys_vm_mem: memory@e0600000 { 579 reg = <0x0 0xe0600000 0x0 0x400000>; 580 no-map; 581 }; 582 583 hyp_reserved_mem: memory@e0a00000 { 584 reg = <0x0 0xe0a00000 0x0 0x100000>; 585 no-map; 586 }; 587 588 trust_ui_vm_mem: memory@e0b00000 { 589 reg = <0x0 0xe0b00000 0x0 0x4af3000>; 590 no-map; 591 }; 592 593 trust_ui_vm_qrtr: memory@e55f3000 { 594 reg = <0x0 0xe55f3000 0x0 0x9000>; 595 no-map; 596 }; 597 598 trust_ui_vm_vblk0_ring: memory@e55fc000 { 599 reg = <0x0 0xe55fc000 0x0 0x4000>; 600 no-map; 601 }; 602 603 trust_ui_vm_swiotlb: memory@e5600000 { 604 reg = <0x0 0xe5600000 0x0 0x100000>; 605 no-map; 606 }; 607 608 tz_stat_mem: memory@e8800000 { 609 reg = <0x0 0xe8800000 0x0 0x100000>; 610 no-map; 611 }; 612 613 tags_mem: memory@e8900000 { 614 reg = <0x0 0xe8900000 0x0 0x1200000>; 615 no-map; 616 }; 617 618 qtee_mem: memory@e9b00000 { 619 reg = <0x0 0xe9b00000 0x0 0x500000>; 620 no-map; 621 }; 622 623 trusted_apps_mem: memory@ea000000 { 624 reg = <0x0 0xea000000 0x0 0x3900000>; 625 no-map; 626 }; 627 628 trusted_apps_ext_mem: memory@ed900000 { 629 reg = <0x0 0xed900000 0x0 0x3b00000>; 630 no-map; 631 }; 632 }; 633 634 smp2p-adsp { 635 compatible = "qcom,smp2p"; 636 qcom,smem = <443>, <429>; 637 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 638 IPCC_MPROC_SIGNAL_SMP2P 639 IRQ_TYPE_EDGE_RISING>; 640 mboxes = <&ipcc IPCC_CLIENT_LPASS 641 IPCC_MPROC_SIGNAL_SMP2P>; 642 643 qcom,local-pid = <0>; 644 qcom,remote-pid = <2>; 645 646 smp2p_adsp_out: master-kernel { 647 qcom,entry-name = "master-kernel"; 648 #qcom,smem-state-cells = <1>; 649 }; 650 651 smp2p_adsp_in: slave-kernel { 652 qcom,entry-name = "slave-kernel"; 653 interrupt-controller; 654 #interrupt-cells = <2>; 655 }; 656 }; 657 658 smp2p-cdsp { 659 compatible = "qcom,smp2p"; 660 qcom,smem = <94>, <432>; 661 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 662 IPCC_MPROC_SIGNAL_SMP2P 663 IRQ_TYPE_EDGE_RISING>; 664 mboxes = <&ipcc IPCC_CLIENT_CDSP 665 IPCC_MPROC_SIGNAL_SMP2P>; 666 667 qcom,local-pid = <0>; 668 qcom,remote-pid = <5>; 669 670 smp2p_cdsp_out: master-kernel { 671 qcom,entry-name = "master-kernel"; 672 #qcom,smem-state-cells = <1>; 673 }; 674 675 smp2p_cdsp_in: slave-kernel { 676 qcom,entry-name = "slave-kernel"; 677 interrupt-controller; 678 #interrupt-cells = <2>; 679 }; 680 }; 681 682 smp2p-modem { 683 compatible = "qcom,smp2p"; 684 qcom,smem = <435>, <428>; 685 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 686 IPCC_MPROC_SIGNAL_SMP2P 687 IRQ_TYPE_EDGE_RISING>; 688 mboxes = <&ipcc IPCC_CLIENT_MPSS 689 IPCC_MPROC_SIGNAL_SMP2P>; 690 691 qcom,local-pid = <0>; 692 qcom,remote-pid = <1>; 693 694 smp2p_modem_out: master-kernel { 695 qcom,entry-name = "master-kernel"; 696 #qcom,smem-state-cells = <1>; 697 }; 698 699 smp2p_modem_in: slave-kernel { 700 qcom,entry-name = "slave-kernel"; 701 interrupt-controller; 702 #interrupt-cells = <2>; 703 }; 704 705 ipa_smp2p_out: ipa-ap-to-modem { 706 qcom,entry-name = "ipa"; 707 #qcom,smem-state-cells = <1>; 708 }; 709 710 ipa_smp2p_in: ipa-modem-to-ap { 711 qcom,entry-name = "ipa"; 712 interrupt-controller; 713 #interrupt-cells = <2>; 714 }; 715 }; 716 717 smp2p-slpi { 718 compatible = "qcom,smp2p"; 719 qcom,smem = <481>, <430>; 720 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 721 IPCC_MPROC_SIGNAL_SMP2P 722 IRQ_TYPE_EDGE_RISING>; 723 mboxes = <&ipcc IPCC_CLIENT_SLPI 724 IPCC_MPROC_SIGNAL_SMP2P>; 725 726 qcom,local-pid = <0>; 727 qcom,remote-pid = <3>; 728 729 smp2p_slpi_out: master-kernel { 730 qcom,entry-name = "master-kernel"; 731 #qcom,smem-state-cells = <1>; 732 }; 733 734 smp2p_slpi_in: slave-kernel { 735 qcom,entry-name = "slave-kernel"; 736 interrupt-controller; 737 #interrupt-cells = <2>; 738 }; 739 }; 740 741 soc: soc@0 { 742 #address-cells = <2>; 743 #size-cells = <2>; 744 ranges = <0 0 0 0 0x10 0>; 745 dma-ranges = <0 0 0 0 0x10 0>; 746 compatible = "simple-bus"; 747 748 gcc: clock-controller@100000 { 749 compatible = "qcom,gcc-sm8450"; 750 reg = <0x0 0x00100000 0x0 0x1f4200>; 751 #clock-cells = <1>; 752 #reset-cells = <1>; 753 #power-domain-cells = <1>; 754 clocks = <&rpmhcc RPMH_CXO_CLK>, 755 <&sleep_clk>, 756 <&pcie0_phy>, 757 <&pcie1_phy>, 758 <0>, 759 <&ufs_mem_phy 0>, 760 <&ufs_mem_phy 1>, 761 <&ufs_mem_phy 2>, 762 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 763 clock-names = "bi_tcxo", 764 "sleep_clk", 765 "pcie_0_pipe_clk", 766 "pcie_1_pipe_clk", 767 "pcie_1_phy_aux_clk", 768 "ufs_phy_rx_symbol_0_clk", 769 "ufs_phy_rx_symbol_1_clk", 770 "ufs_phy_tx_symbol_0_clk", 771 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 772 }; 773 774 gpi_dma2: dma-controller@800000 { 775 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 776 #dma-cells = <3>; 777 reg = <0 0x00800000 0 0x60000>; 778 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 790 dma-channels = <12>; 791 dma-channel-mask = <0x7e>; 792 iommus = <&apps_smmu 0x496 0x0>; 793 status = "disabled"; 794 }; 795 796 qupv3_id_2: geniqup@8c0000 { 797 compatible = "qcom,geni-se-qup"; 798 reg = <0x0 0x008c0000 0x0 0x2000>; 799 clock-names = "m-ahb", "s-ahb"; 800 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 801 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 802 iommus = <&apps_smmu 0x483 0x0>; 803 #address-cells = <2>; 804 #size-cells = <2>; 805 ranges; 806 status = "disabled"; 807 808 i2c15: i2c@880000 { 809 compatible = "qcom,geni-i2c"; 810 reg = <0x0 0x00880000 0x0 0x4000>; 811 clock-names = "se"; 812 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 813 pinctrl-names = "default"; 814 pinctrl-0 = <&qup_i2c15_data_clk>; 815 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 816 #address-cells = <1>; 817 #size-cells = <0>; 818 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 819 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 820 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 821 interconnect-names = "qup-core", "qup-config", "qup-memory"; 822 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 823 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 824 dma-names = "tx", "rx"; 825 status = "disabled"; 826 }; 827 828 spi15: spi@880000 { 829 compatible = "qcom,geni-spi"; 830 reg = <0x0 0x00880000 0x0 0x4000>; 831 clock-names = "se"; 832 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 833 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 834 pinctrl-names = "default"; 835 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 836 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 837 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 838 interconnect-names = "qup-core", "qup-config"; 839 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 840 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 841 dma-names = "tx", "rx"; 842 #address-cells = <1>; 843 #size-cells = <0>; 844 status = "disabled"; 845 }; 846 847 i2c16: i2c@884000 { 848 compatible = "qcom,geni-i2c"; 849 reg = <0x0 0x00884000 0x0 0x4000>; 850 clock-names = "se"; 851 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 852 pinctrl-names = "default"; 853 pinctrl-0 = <&qup_i2c16_data_clk>; 854 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 855 #address-cells = <1>; 856 #size-cells = <0>; 857 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 858 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 859 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 860 interconnect-names = "qup-core", "qup-config", "qup-memory"; 861 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 862 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 863 dma-names = "tx", "rx"; 864 status = "disabled"; 865 }; 866 867 spi16: spi@884000 { 868 compatible = "qcom,geni-spi"; 869 reg = <0x0 0x00884000 0x0 0x4000>; 870 clock-names = "se"; 871 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 872 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 873 pinctrl-names = "default"; 874 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 875 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 876 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 877 interconnect-names = "qup-core", "qup-config"; 878 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 879 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 880 dma-names = "tx", "rx"; 881 #address-cells = <1>; 882 #size-cells = <0>; 883 status = "disabled"; 884 }; 885 886 i2c17: i2c@888000 { 887 compatible = "qcom,geni-i2c"; 888 reg = <0x0 0x00888000 0x0 0x4000>; 889 clock-names = "se"; 890 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 891 pinctrl-names = "default"; 892 pinctrl-0 = <&qup_i2c17_data_clk>; 893 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 894 #address-cells = <1>; 895 #size-cells = <0>; 896 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 897 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 898 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 899 interconnect-names = "qup-core", "qup-config", "qup-memory"; 900 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 901 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 902 dma-names = "tx", "rx"; 903 status = "disabled"; 904 }; 905 906 spi17: spi@888000 { 907 compatible = "qcom,geni-spi"; 908 reg = <0x0 0x00888000 0x0 0x4000>; 909 clock-names = "se"; 910 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 911 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 912 pinctrl-names = "default"; 913 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 914 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 915 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 916 interconnect-names = "qup-core", "qup-config"; 917 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 918 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 919 dma-names = "tx", "rx"; 920 #address-cells = <1>; 921 #size-cells = <0>; 922 status = "disabled"; 923 }; 924 925 i2c18: i2c@88c000 { 926 compatible = "qcom,geni-i2c"; 927 reg = <0x0 0x0088c000 0x0 0x4000>; 928 clock-names = "se"; 929 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 930 pinctrl-names = "default"; 931 pinctrl-0 = <&qup_i2c18_data_clk>; 932 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 933 #address-cells = <1>; 934 #size-cells = <0>; 935 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 936 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 937 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 938 interconnect-names = "qup-core", "qup-config", "qup-memory"; 939 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 940 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 941 dma-names = "tx", "rx"; 942 status = "disabled"; 943 }; 944 945 spi18: spi@88c000 { 946 compatible = "qcom,geni-spi"; 947 reg = <0 0x0088c000 0 0x4000>; 948 clock-names = "se"; 949 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 950 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 951 pinctrl-names = "default"; 952 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 953 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 954 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 955 interconnect-names = "qup-core", "qup-config"; 956 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 957 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 958 dma-names = "tx", "rx"; 959 #address-cells = <1>; 960 #size-cells = <0>; 961 status = "disabled"; 962 }; 963 964 i2c19: i2c@890000 { 965 compatible = "qcom,geni-i2c"; 966 reg = <0x0 0x00890000 0x0 0x4000>; 967 clock-names = "se"; 968 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 969 pinctrl-names = "default"; 970 pinctrl-0 = <&qup_i2c19_data_clk>; 971 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 972 #address-cells = <1>; 973 #size-cells = <0>; 974 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 975 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 976 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 977 interconnect-names = "qup-core", "qup-config", "qup-memory"; 978 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 979 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 980 dma-names = "tx", "rx"; 981 status = "disabled"; 982 }; 983 984 spi19: spi@890000 { 985 compatible = "qcom,geni-spi"; 986 reg = <0 0x00890000 0 0x4000>; 987 clock-names = "se"; 988 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 989 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 990 pinctrl-names = "default"; 991 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 992 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 993 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 994 interconnect-names = "qup-core", "qup-config"; 995 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 996 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 997 dma-names = "tx", "rx"; 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 status = "disabled"; 1001 }; 1002 1003 i2c20: i2c@894000 { 1004 compatible = "qcom,geni-i2c"; 1005 reg = <0x0 0x00894000 0x0 0x4000>; 1006 clock-names = "se"; 1007 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1008 pinctrl-names = "default"; 1009 pinctrl-0 = <&qup_i2c20_data_clk>; 1010 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1011 #address-cells = <1>; 1012 #size-cells = <0>; 1013 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1014 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1015 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1016 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1017 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1018 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1019 dma-names = "tx", "rx"; 1020 status = "disabled"; 1021 }; 1022 1023 uart20: serial@894000 { 1024 compatible = "qcom,geni-uart"; 1025 reg = <0 0x00894000 0 0x4000>; 1026 clock-names = "se"; 1027 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1028 pinctrl-names = "default"; 1029 pinctrl-0 = <&qup_uart20_default>; 1030 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1031 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1032 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1033 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1034 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1035 interconnect-names = "qup-core", 1036 "qup-config"; 1037 status = "disabled"; 1038 }; 1039 1040 spi20: spi@894000 { 1041 compatible = "qcom,geni-spi"; 1042 reg = <0 0x00894000 0 0x4000>; 1043 clock-names = "se"; 1044 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1045 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1046 pinctrl-names = "default"; 1047 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1048 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1049 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1050 interconnect-names = "qup-core", "qup-config"; 1051 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1052 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1053 dma-names = "tx", "rx"; 1054 #address-cells = <1>; 1055 #size-cells = <0>; 1056 status = "disabled"; 1057 }; 1058 1059 i2c21: i2c@898000 { 1060 compatible = "qcom,geni-i2c"; 1061 reg = <0x0 0x00898000 0x0 0x4000>; 1062 clock-names = "se"; 1063 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1064 pinctrl-names = "default"; 1065 pinctrl-0 = <&qup_i2c21_data_clk>; 1066 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1067 #address-cells = <1>; 1068 #size-cells = <0>; 1069 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1070 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1071 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1072 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1073 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1074 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1075 dma-names = "tx", "rx"; 1076 status = "disabled"; 1077 }; 1078 1079 spi21: spi@898000 { 1080 compatible = "qcom,geni-spi"; 1081 reg = <0 0x00898000 0 0x4000>; 1082 clock-names = "se"; 1083 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1084 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1085 pinctrl-names = "default"; 1086 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1087 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1088 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1089 interconnect-names = "qup-core", "qup-config"; 1090 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1091 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1092 dma-names = "tx", "rx"; 1093 #address-cells = <1>; 1094 #size-cells = <0>; 1095 status = "disabled"; 1096 }; 1097 }; 1098 1099 gpi_dma0: dma-controller@900000 { 1100 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1101 #dma-cells = <3>; 1102 reg = <0 0x00900000 0 0x60000>; 1103 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1115 dma-channels = <12>; 1116 dma-channel-mask = <0x7e>; 1117 iommus = <&apps_smmu 0x5b6 0x0>; 1118 status = "disabled"; 1119 }; 1120 1121 qupv3_id_0: geniqup@9c0000 { 1122 compatible = "qcom,geni-se-qup"; 1123 reg = <0x0 0x009c0000 0x0 0x2000>; 1124 clock-names = "m-ahb", "s-ahb"; 1125 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1126 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1127 iommus = <&apps_smmu 0x5a3 0x0>; 1128 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>; 1129 interconnect-names = "qup-core"; 1130 #address-cells = <2>; 1131 #size-cells = <2>; 1132 ranges; 1133 status = "disabled"; 1134 1135 i2c0: i2c@980000 { 1136 compatible = "qcom,geni-i2c"; 1137 reg = <0x0 0x00980000 0x0 0x4000>; 1138 clock-names = "se"; 1139 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1140 pinctrl-names = "default"; 1141 pinctrl-0 = <&qup_i2c0_data_clk>; 1142 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1143 #address-cells = <1>; 1144 #size-cells = <0>; 1145 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1146 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1147 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1148 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1149 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1150 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1151 dma-names = "tx", "rx"; 1152 status = "disabled"; 1153 }; 1154 1155 spi0: spi@980000 { 1156 compatible = "qcom,geni-spi"; 1157 reg = <0x0 0x00980000 0x0 0x4000>; 1158 clock-names = "se"; 1159 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1160 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1161 pinctrl-names = "default"; 1162 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1163 power-domains = <&rpmhpd RPMHPD_CX>; 1164 operating-points-v2 = <&qup_opp_table_100mhz>; 1165 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1166 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1167 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1168 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1169 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1170 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1171 dma-names = "tx", "rx"; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 status = "disabled"; 1175 }; 1176 1177 i2c1: i2c@984000 { 1178 compatible = "qcom,geni-i2c"; 1179 reg = <0x0 0x00984000 0x0 0x4000>; 1180 clock-names = "se"; 1181 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1182 pinctrl-names = "default"; 1183 pinctrl-0 = <&qup_i2c1_data_clk>; 1184 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1185 #address-cells = <1>; 1186 #size-cells = <0>; 1187 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1188 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1189 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1190 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1191 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1192 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1193 dma-names = "tx", "rx"; 1194 status = "disabled"; 1195 }; 1196 1197 spi1: spi@984000 { 1198 compatible = "qcom,geni-spi"; 1199 reg = <0x0 0x00984000 0x0 0x4000>; 1200 clock-names = "se"; 1201 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1202 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1203 pinctrl-names = "default"; 1204 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1205 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1206 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1207 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1208 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1209 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1210 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1211 dma-names = "tx", "rx"; 1212 #address-cells = <1>; 1213 #size-cells = <0>; 1214 status = "disabled"; 1215 }; 1216 1217 i2c2: i2c@988000 { 1218 compatible = "qcom,geni-i2c"; 1219 reg = <0x0 0x00988000 0x0 0x4000>; 1220 clock-names = "se"; 1221 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1222 pinctrl-names = "default"; 1223 pinctrl-0 = <&qup_i2c2_data_clk>; 1224 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1225 #address-cells = <1>; 1226 #size-cells = <0>; 1227 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1228 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1229 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1230 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1231 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1232 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1233 dma-names = "tx", "rx"; 1234 status = "disabled"; 1235 }; 1236 1237 spi2: spi@988000 { 1238 compatible = "qcom,geni-spi"; 1239 reg = <0x0 0x00988000 0x0 0x4000>; 1240 clock-names = "se"; 1241 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1242 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1243 pinctrl-names = "default"; 1244 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1245 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1246 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1247 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1248 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1249 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1250 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1251 dma-names = "tx", "rx"; 1252 #address-cells = <1>; 1253 #size-cells = <0>; 1254 status = "disabled"; 1255 }; 1256 1257 1258 i2c3: i2c@98c000 { 1259 compatible = "qcom,geni-i2c"; 1260 reg = <0x0 0x0098c000 0x0 0x4000>; 1261 clock-names = "se"; 1262 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1263 pinctrl-names = "default"; 1264 pinctrl-0 = <&qup_i2c3_data_clk>; 1265 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1266 #address-cells = <1>; 1267 #size-cells = <0>; 1268 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1269 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1270 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1271 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1272 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1273 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1274 dma-names = "tx", "rx"; 1275 status = "disabled"; 1276 }; 1277 1278 spi3: spi@98c000 { 1279 compatible = "qcom,geni-spi"; 1280 reg = <0x0 0x0098c000 0x0 0x4000>; 1281 clock-names = "se"; 1282 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1283 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1284 pinctrl-names = "default"; 1285 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1286 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1287 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1288 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1289 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1290 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1291 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1292 dma-names = "tx", "rx"; 1293 #address-cells = <1>; 1294 #size-cells = <0>; 1295 status = "disabled"; 1296 }; 1297 1298 i2c4: i2c@990000 { 1299 compatible = "qcom,geni-i2c"; 1300 reg = <0x0 0x00990000 0x0 0x4000>; 1301 clock-names = "se"; 1302 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1303 pinctrl-names = "default"; 1304 pinctrl-0 = <&qup_i2c4_data_clk>; 1305 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1306 #address-cells = <1>; 1307 #size-cells = <0>; 1308 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1309 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1310 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1311 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1312 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1313 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1314 dma-names = "tx", "rx"; 1315 status = "disabled"; 1316 }; 1317 1318 spi4: spi@990000 { 1319 compatible = "qcom,geni-spi"; 1320 reg = <0x0 0x00990000 0x0 0x4000>; 1321 clock-names = "se"; 1322 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1323 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1324 pinctrl-names = "default"; 1325 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1326 power-domains = <&rpmhpd RPMHPD_CX>; 1327 operating-points-v2 = <&qup_opp_table_100mhz>; 1328 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1329 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1330 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1331 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1332 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1333 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1334 dma-names = "tx", "rx"; 1335 #address-cells = <1>; 1336 #size-cells = <0>; 1337 status = "disabled"; 1338 }; 1339 1340 i2c5: i2c@994000 { 1341 compatible = "qcom,geni-i2c"; 1342 reg = <0x0 0x00994000 0x0 0x4000>; 1343 clock-names = "se"; 1344 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1345 pinctrl-names = "default"; 1346 pinctrl-0 = <&qup_i2c5_data_clk>; 1347 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1348 #address-cells = <1>; 1349 #size-cells = <0>; 1350 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1351 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1352 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1353 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1354 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1355 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1356 dma-names = "tx", "rx"; 1357 status = "disabled"; 1358 }; 1359 1360 spi5: spi@994000 { 1361 compatible = "qcom,geni-spi"; 1362 reg = <0x0 0x00994000 0x0 0x4000>; 1363 clock-names = "se"; 1364 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1365 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1366 pinctrl-names = "default"; 1367 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1368 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1369 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1370 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1371 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1372 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1373 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1374 dma-names = "tx", "rx"; 1375 #address-cells = <1>; 1376 #size-cells = <0>; 1377 status = "disabled"; 1378 }; 1379 1380 1381 i2c6: i2c@998000 { 1382 compatible = "qcom,geni-i2c"; 1383 reg = <0x0 0x00998000 0x0 0x4000>; 1384 clock-names = "se"; 1385 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1386 pinctrl-names = "default"; 1387 pinctrl-0 = <&qup_i2c6_data_clk>; 1388 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1389 #address-cells = <1>; 1390 #size-cells = <0>; 1391 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1392 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1393 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1394 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1395 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1396 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1397 dma-names = "tx", "rx"; 1398 status = "disabled"; 1399 }; 1400 1401 spi6: spi@998000 { 1402 compatible = "qcom,geni-spi"; 1403 reg = <0x0 0x00998000 0x0 0x4000>; 1404 clock-names = "se"; 1405 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1406 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1407 pinctrl-names = "default"; 1408 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1409 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1410 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1411 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1412 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1413 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1414 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1415 dma-names = "tx", "rx"; 1416 #address-cells = <1>; 1417 #size-cells = <0>; 1418 status = "disabled"; 1419 }; 1420 1421 uart7: serial@99c000 { 1422 compatible = "qcom,geni-debug-uart"; 1423 reg = <0 0x0099c000 0 0x4000>; 1424 clock-names = "se"; 1425 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1426 pinctrl-names = "default"; 1427 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 1428 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1429 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1430 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1431 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1432 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1433 interconnect-names = "qup-core", 1434 "qup-config"; 1435 status = "disabled"; 1436 }; 1437 }; 1438 1439 gpi_dma1: dma-controller@a00000 { 1440 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1441 #dma-cells = <3>; 1442 reg = <0 0x00a00000 0 0x60000>; 1443 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1455 dma-channels = <12>; 1456 dma-channel-mask = <0x7e>; 1457 iommus = <&apps_smmu 0x56 0x0>; 1458 status = "disabled"; 1459 }; 1460 1461 qupv3_id_1: geniqup@ac0000 { 1462 compatible = "qcom,geni-se-qup"; 1463 reg = <0x0 0x00ac0000 0x0 0x6000>; 1464 clock-names = "m-ahb", "s-ahb"; 1465 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1466 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1467 iommus = <&apps_smmu 0x43 0x0>; 1468 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1469 interconnect-names = "qup-core"; 1470 #address-cells = <2>; 1471 #size-cells = <2>; 1472 ranges; 1473 status = "disabled"; 1474 1475 i2c8: i2c@a80000 { 1476 compatible = "qcom,geni-i2c"; 1477 reg = <0x0 0x00a80000 0x0 0x4000>; 1478 clock-names = "se"; 1479 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1480 pinctrl-names = "default"; 1481 pinctrl-0 = <&qup_i2c8_data_clk>; 1482 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1483 #address-cells = <1>; 1484 #size-cells = <0>; 1485 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1486 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1487 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1488 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1489 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1490 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1491 dma-names = "tx", "rx"; 1492 status = "disabled"; 1493 }; 1494 1495 spi8: spi@a80000 { 1496 compatible = "qcom,geni-spi"; 1497 reg = <0x0 0x00a80000 0x0 0x4000>; 1498 clock-names = "se"; 1499 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1500 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1501 pinctrl-names = "default"; 1502 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1503 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1504 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1505 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1506 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1507 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1508 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1509 dma-names = "tx", "rx"; 1510 #address-cells = <1>; 1511 #size-cells = <0>; 1512 status = "disabled"; 1513 }; 1514 1515 i2c9: i2c@a84000 { 1516 compatible = "qcom,geni-i2c"; 1517 reg = <0x0 0x00a84000 0x0 0x4000>; 1518 clock-names = "se"; 1519 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1520 pinctrl-names = "default"; 1521 pinctrl-0 = <&qup_i2c9_data_clk>; 1522 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1523 #address-cells = <1>; 1524 #size-cells = <0>; 1525 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1526 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1527 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1528 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1529 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1530 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1531 dma-names = "tx", "rx"; 1532 status = "disabled"; 1533 }; 1534 1535 spi9: spi@a84000 { 1536 compatible = "qcom,geni-spi"; 1537 reg = <0x0 0x00a84000 0x0 0x4000>; 1538 clock-names = "se"; 1539 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1540 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1541 pinctrl-names = "default"; 1542 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1543 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1544 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1545 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1546 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1547 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1548 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1549 dma-names = "tx", "rx"; 1550 #address-cells = <1>; 1551 #size-cells = <0>; 1552 status = "disabled"; 1553 }; 1554 1555 i2c10: i2c@a88000 { 1556 compatible = "qcom,geni-i2c"; 1557 reg = <0x0 0x00a88000 0x0 0x4000>; 1558 clock-names = "se"; 1559 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1560 pinctrl-names = "default"; 1561 pinctrl-0 = <&qup_i2c10_data_clk>; 1562 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1563 #address-cells = <1>; 1564 #size-cells = <0>; 1565 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1566 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1567 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1568 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1569 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1570 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1571 dma-names = "tx", "rx"; 1572 status = "disabled"; 1573 }; 1574 1575 spi10: spi@a88000 { 1576 compatible = "qcom,geni-spi"; 1577 reg = <0x0 0x00a88000 0x0 0x4000>; 1578 clock-names = "se"; 1579 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1580 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1581 pinctrl-names = "default"; 1582 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1583 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1584 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1585 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1586 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1587 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1588 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1589 dma-names = "tx", "rx"; 1590 #address-cells = <1>; 1591 #size-cells = <0>; 1592 status = "disabled"; 1593 }; 1594 1595 i2c11: i2c@a8c000 { 1596 compatible = "qcom,geni-i2c"; 1597 reg = <0x0 0x00a8c000 0x0 0x4000>; 1598 clock-names = "se"; 1599 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1600 pinctrl-names = "default"; 1601 pinctrl-0 = <&qup_i2c11_data_clk>; 1602 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1603 #address-cells = <1>; 1604 #size-cells = <0>; 1605 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1606 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1607 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1608 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1609 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1610 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1611 dma-names = "tx", "rx"; 1612 status = "disabled"; 1613 }; 1614 1615 spi11: spi@a8c000 { 1616 compatible = "qcom,geni-spi"; 1617 reg = <0x0 0x00a8c000 0x0 0x4000>; 1618 clock-names = "se"; 1619 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1620 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1621 pinctrl-names = "default"; 1622 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1623 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1624 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1625 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1626 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1627 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1628 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1629 dma-names = "tx", "rx"; 1630 #address-cells = <1>; 1631 #size-cells = <0>; 1632 status = "disabled"; 1633 }; 1634 1635 i2c12: i2c@a90000 { 1636 compatible = "qcom,geni-i2c"; 1637 reg = <0x0 0x00a90000 0x0 0x4000>; 1638 clock-names = "se"; 1639 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1640 pinctrl-names = "default"; 1641 pinctrl-0 = <&qup_i2c12_data_clk>; 1642 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1643 #address-cells = <1>; 1644 #size-cells = <0>; 1645 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1646 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1647 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1648 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1649 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1650 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1651 dma-names = "tx", "rx"; 1652 status = "disabled"; 1653 }; 1654 1655 spi12: spi@a90000 { 1656 compatible = "qcom,geni-spi"; 1657 reg = <0x0 0x00a90000 0x0 0x4000>; 1658 clock-names = "se"; 1659 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1660 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1661 pinctrl-names = "default"; 1662 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1663 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1664 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1665 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1666 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1667 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1668 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1669 dma-names = "tx", "rx"; 1670 #address-cells = <1>; 1671 #size-cells = <0>; 1672 status = "disabled"; 1673 }; 1674 1675 i2c13: i2c@a94000 { 1676 compatible = "qcom,geni-i2c"; 1677 reg = <0 0x00a94000 0 0x4000>; 1678 clock-names = "se"; 1679 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1680 pinctrl-names = "default"; 1681 pinctrl-0 = <&qup_i2c13_data_clk>; 1682 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1683 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1684 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1685 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1686 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1687 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1688 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1689 dma-names = "tx", "rx"; 1690 #address-cells = <1>; 1691 #size-cells = <0>; 1692 status = "disabled"; 1693 }; 1694 1695 spi13: spi@a94000 { 1696 compatible = "qcom,geni-spi"; 1697 reg = <0x0 0x00a94000 0x0 0x4000>; 1698 clock-names = "se"; 1699 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1700 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1701 pinctrl-names = "default"; 1702 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1703 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1704 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1705 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1706 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1707 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1708 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1709 dma-names = "tx", "rx"; 1710 #address-cells = <1>; 1711 #size-cells = <0>; 1712 status = "disabled"; 1713 }; 1714 1715 i2c14: i2c@a98000 { 1716 compatible = "qcom,geni-i2c"; 1717 reg = <0 0x00a98000 0 0x4000>; 1718 clock-names = "se"; 1719 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1720 pinctrl-names = "default"; 1721 pinctrl-0 = <&qup_i2c14_data_clk>; 1722 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1723 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1724 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1725 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1726 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1727 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1728 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1729 dma-names = "tx", "rx"; 1730 #address-cells = <1>; 1731 #size-cells = <0>; 1732 status = "disabled"; 1733 }; 1734 1735 spi14: spi@a98000 { 1736 compatible = "qcom,geni-spi"; 1737 reg = <0x0 0x00a98000 0x0 0x4000>; 1738 clock-names = "se"; 1739 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1740 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1741 pinctrl-names = "default"; 1742 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1743 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1744 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1745 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1746 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1747 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1748 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1749 dma-names = "tx", "rx"; 1750 #address-cells = <1>; 1751 #size-cells = <0>; 1752 status = "disabled"; 1753 }; 1754 }; 1755 1756 rng: rng@10c3000 { 1757 compatible = "qcom,sm8450-trng", "qcom,trng"; 1758 reg = <0 0x010c3000 0 0x1000>; 1759 }; 1760 1761 pcie0: pcie@1c00000 { 1762 compatible = "qcom,pcie-sm8450-pcie0"; 1763 reg = <0 0x01c00000 0 0x3000>, 1764 <0 0x60000000 0 0xf1d>, 1765 <0 0x60000f20 0 0xa8>, 1766 <0 0x60001000 0 0x1000>, 1767 <0 0x60100000 0 0x100000>; 1768 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1769 device_type = "pci"; 1770 linux,pci-domain = <0>; 1771 bus-range = <0x00 0xff>; 1772 num-lanes = <1>; 1773 1774 #address-cells = <3>; 1775 #size-cells = <2>; 1776 1777 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1778 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1779 1780 /* 1781 * MSIs for BDF (1:0.0) only works with Device ID 0x5980. 1782 * Hence, the IDs are swapped. 1783 */ 1784 msi-map = <0x0 &gic_its 0x5981 0x1>, 1785 <0x100 &gic_its 0x5980 0x1>; 1786 msi-map-mask = <0xff00>; 1787 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1789 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1790 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1791 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1792 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1793 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1794 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1795 interrupt-names = "msi0", 1796 "msi1", 1797 "msi2", 1798 "msi3", 1799 "msi4", 1800 "msi5", 1801 "msi6", 1802 "msi7"; 1803 #interrupt-cells = <1>; 1804 interrupt-map-mask = <0 0 0 0x7>; 1805 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1806 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1807 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1808 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1809 1810 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1811 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, 1812 <&pcie0_phy>, 1813 <&rpmhcc RPMH_CXO_CLK>, 1814 <&gcc GCC_PCIE_0_AUX_CLK>, 1815 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1816 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1817 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1818 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1819 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1820 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 1821 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1822 clock-names = "pipe", 1823 "pipe_mux", 1824 "phy_pipe", 1825 "ref", 1826 "aux", 1827 "cfg", 1828 "bus_master", 1829 "bus_slave", 1830 "slave_q2a", 1831 "ddrss_sf_tbu", 1832 "aggre0", 1833 "aggre1"; 1834 1835 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1836 <0x100 &apps_smmu 0x1c01 0x1>; 1837 1838 resets = <&gcc GCC_PCIE_0_BCR>; 1839 reset-names = "pci"; 1840 1841 power-domains = <&gcc PCIE_0_GDSC>; 1842 1843 phys = <&pcie0_phy>; 1844 phy-names = "pciephy"; 1845 1846 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; 1847 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; 1848 1849 pinctrl-names = "default"; 1850 pinctrl-0 = <&pcie0_default_state>; 1851 1852 status = "disabled"; 1853 1854 pcie@0 { 1855 device_type = "pci"; 1856 reg = <0x0 0x0 0x0 0x0 0x0>; 1857 bus-range = <0x01 0xff>; 1858 1859 #address-cells = <3>; 1860 #size-cells = <2>; 1861 ranges; 1862 }; 1863 }; 1864 1865 pcie0_phy: phy@1c06000 { 1866 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; 1867 reg = <0 0x01c06000 0 0x2000>; 1868 1869 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1870 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1871 <&gcc GCC_PCIE_0_CLKREF_EN>, 1872 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 1873 <&gcc GCC_PCIE_0_PIPE_CLK>; 1874 clock-names = "aux", 1875 "cfg_ahb", 1876 "ref", 1877 "rchng", 1878 "pipe"; 1879 1880 clock-output-names = "pcie_0_pipe_clk"; 1881 #clock-cells = <0>; 1882 1883 #phy-cells = <0>; 1884 1885 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1886 reset-names = "phy"; 1887 1888 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1889 assigned-clock-rates = <100000000>; 1890 1891 status = "disabled"; 1892 }; 1893 1894 pcie1: pcie@1c08000 { 1895 compatible = "qcom,pcie-sm8450-pcie1"; 1896 reg = <0 0x01c08000 0 0x3000>, 1897 <0 0x40000000 0 0xf1d>, 1898 <0 0x40000f20 0 0xa8>, 1899 <0 0x40001000 0 0x1000>, 1900 <0 0x40100000 0 0x100000>; 1901 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1902 device_type = "pci"; 1903 linux,pci-domain = <1>; 1904 bus-range = <0x00 0xff>; 1905 num-lanes = <2>; 1906 1907 #address-cells = <3>; 1908 #size-cells = <2>; 1909 1910 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1911 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1912 1913 /* 1914 * MSIs for BDF (1:0.0) only works with Device ID 0x5a00. 1915 * Hence, the IDs are swapped. 1916 */ 1917 msi-map = <0x0 &gic_its 0x5a01 0x1>, 1918 <0x100 &gic_its 0x5a00 0x1>; 1919 msi-map-mask = <0xff00>; 1920 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1921 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1922 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1923 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1924 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1925 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1926 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 1927 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1928 interrupt-names = "msi0", 1929 "msi1", 1930 "msi2", 1931 "msi3", 1932 "msi4", 1933 "msi5", 1934 "msi6", 1935 "msi7"; 1936 #interrupt-cells = <1>; 1937 interrupt-map-mask = <0 0 0 0x7>; 1938 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1939 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1940 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1941 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1942 1943 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1944 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 1945 <&pcie1_phy>, 1946 <&rpmhcc RPMH_CXO_CLK>, 1947 <&gcc GCC_PCIE_1_AUX_CLK>, 1948 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1949 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1950 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1951 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1952 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1953 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1954 clock-names = "pipe", 1955 "pipe_mux", 1956 "phy_pipe", 1957 "ref", 1958 "aux", 1959 "cfg", 1960 "bus_master", 1961 "bus_slave", 1962 "slave_q2a", 1963 "ddrss_sf_tbu", 1964 "aggre1"; 1965 1966 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1967 <0x100 &apps_smmu 0x1c81 0x1>; 1968 1969 resets = <&gcc GCC_PCIE_1_BCR>; 1970 reset-names = "pci"; 1971 1972 power-domains = <&gcc PCIE_1_GDSC>; 1973 1974 phys = <&pcie1_phy>; 1975 phy-names = "pciephy"; 1976 1977 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; 1978 wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; 1979 1980 pinctrl-names = "default"; 1981 pinctrl-0 = <&pcie1_default_state>; 1982 1983 status = "disabled"; 1984 1985 pcie@0 { 1986 device_type = "pci"; 1987 reg = <0x0 0x0 0x0 0x0 0x0>; 1988 bus-range = <0x01 0xff>; 1989 1990 #address-cells = <3>; 1991 #size-cells = <2>; 1992 ranges; 1993 }; 1994 }; 1995 1996 pcie1_phy: phy@1c0e000 { 1997 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy"; 1998 reg = <0 0x01c0e000 0 0x2000>; 1999 2000 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 2001 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2002 <&gcc GCC_PCIE_1_CLKREF_EN>, 2003 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 2004 <&gcc GCC_PCIE_1_PIPE_CLK>; 2005 clock-names = "aux", 2006 "cfg_ahb", 2007 "ref", 2008 "rchng", 2009 "pipe"; 2010 2011 clock-output-names = "pcie_1_pipe_clk"; 2012 #clock-cells = <0>; 2013 2014 #phy-cells = <0>; 2015 2016 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2017 reset-names = "phy"; 2018 2019 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 2020 assigned-clock-rates = <100000000>; 2021 2022 status = "disabled"; 2023 }; 2024 2025 config_noc: interconnect@1500000 { 2026 compatible = "qcom,sm8450-config-noc"; 2027 reg = <0 0x01500000 0 0x1c000>; 2028 #interconnect-cells = <2>; 2029 qcom,bcm-voters = <&apps_bcm_voter>; 2030 }; 2031 2032 system_noc: interconnect@1680000 { 2033 compatible = "qcom,sm8450-system-noc"; 2034 reg = <0 0x01680000 0 0x1e200>; 2035 #interconnect-cells = <2>; 2036 qcom,bcm-voters = <&apps_bcm_voter>; 2037 }; 2038 2039 pcie_noc: interconnect@16c0000 { 2040 compatible = "qcom,sm8450-pcie-anoc"; 2041 reg = <0 0x016c0000 0 0xe280>; 2042 #interconnect-cells = <2>; 2043 qcom,bcm-voters = <&apps_bcm_voter>; 2044 }; 2045 2046 aggre1_noc: interconnect@16e0000 { 2047 compatible = "qcom,sm8450-aggre1-noc"; 2048 reg = <0 0x016e0000 0 0x1c080>; 2049 #interconnect-cells = <2>; 2050 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2051 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 2052 qcom,bcm-voters = <&apps_bcm_voter>; 2053 }; 2054 2055 aggre2_noc: interconnect@1700000 { 2056 compatible = "qcom,sm8450-aggre2-noc"; 2057 reg = <0 0x01700000 0 0x31080>; 2058 #interconnect-cells = <2>; 2059 qcom,bcm-voters = <&apps_bcm_voter>; 2060 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 2061 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 2062 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2063 <&rpmhcc RPMH_IPA_CLK>; 2064 }; 2065 2066 mmss_noc: interconnect@1740000 { 2067 compatible = "qcom,sm8450-mmss-noc"; 2068 reg = <0 0x01740000 0 0x1f080>; 2069 #interconnect-cells = <2>; 2070 qcom,bcm-voters = <&apps_bcm_voter>; 2071 }; 2072 2073 tcsr_mutex: hwlock@1f40000 { 2074 compatible = "qcom,tcsr-mutex"; 2075 reg = <0x0 0x01f40000 0x0 0x40000>; 2076 #hwlock-cells = <1>; 2077 }; 2078 2079 tcsr: syscon@1fc0000 { 2080 compatible = "qcom,sm8450-tcsr", "syscon"; 2081 reg = <0x0 0x1fc0000 0x0 0x30000>; 2082 }; 2083 2084 gpu: gpu@3d00000 { 2085 compatible = "qcom,adreno-730.1", "qcom,adreno"; 2086 reg = <0x0 0x03d00000 0x0 0x40000>, 2087 <0x0 0x03d9e000 0x0 0x1000>, 2088 <0x0 0x03d61000 0x0 0x800>; 2089 reg-names = "kgsl_3d0_reg_memory", 2090 "cx_mem", 2091 "cx_dbgc"; 2092 2093 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2094 2095 iommus = <&adreno_smmu 0 0x400>, 2096 <&adreno_smmu 1 0x400>; 2097 2098 operating-points-v2 = <&gpu_opp_table>; 2099 2100 qcom,gmu = <&gmu>; 2101 #cooling-cells = <2>; 2102 2103 status = "disabled"; 2104 2105 zap-shader { 2106 memory-region = <&gpu_micro_code_mem>; 2107 }; 2108 2109 gpu_opp_table: opp-table { 2110 compatible = "operating-points-v2"; 2111 2112 opp-818000000 { 2113 opp-hz = /bits/ 64 <818000000>; 2114 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2115 }; 2116 2117 opp-791000000 { 2118 opp-hz = /bits/ 64 <791000000>; 2119 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2120 }; 2121 2122 opp-734000000 { 2123 opp-hz = /bits/ 64 <734000000>; 2124 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2125 }; 2126 2127 opp-640000000 { 2128 opp-hz = /bits/ 64 <640000000>; 2129 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2130 }; 2131 2132 opp-599000000 { 2133 opp-hz = /bits/ 64 <599000000>; 2134 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2135 }; 2136 2137 opp-545000000 { 2138 opp-hz = /bits/ 64 <545000000>; 2139 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2140 }; 2141 2142 opp-492000000 { 2143 opp-hz = /bits/ 64 <492000000>; 2144 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2145 }; 2146 2147 opp-421000000 { 2148 opp-hz = /bits/ 64 <421000000>; 2149 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 2150 }; 2151 2152 opp-350000000 { 2153 opp-hz = /bits/ 64 <350000000>; 2154 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2155 }; 2156 2157 opp-317000000 { 2158 opp-hz = /bits/ 64 <317000000>; 2159 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2160 }; 2161 2162 opp-285000000 { 2163 opp-hz = /bits/ 64 <285000000>; 2164 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 2165 }; 2166 2167 opp-220000000 { 2168 opp-hz = /bits/ 64 <220000000>; 2169 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 2170 }; 2171 }; 2172 }; 2173 2174 gmu: gmu@3d6a000 { 2175 compatible = "qcom,adreno-gmu-730.1", "qcom,adreno-gmu"; 2176 reg = <0x0 0x03d6a000 0x0 0x35000>, 2177 <0x0 0x03d50000 0x0 0x10000>, 2178 <0x0 0x0b290000 0x0 0x10000>; 2179 reg-names = "gmu", "rscc", "gmu_pdc"; 2180 2181 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2182 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2183 interrupt-names = "hfi", "gmu"; 2184 2185 clocks = <&gpucc GPU_CC_AHB_CLK>, 2186 <&gpucc GPU_CC_CX_GMU_CLK>, 2187 <&gpucc GPU_CC_CXO_CLK>, 2188 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2189 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2190 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2191 <&gpucc GPU_CC_DEMET_CLK>; 2192 clock-names = "ahb", 2193 "gmu", 2194 "cxo", 2195 "axi", 2196 "memnoc", 2197 "hub", 2198 "demet"; 2199 2200 power-domains = <&gpucc GPU_CX_GDSC>, 2201 <&gpucc GPU_GX_GDSC>; 2202 power-domain-names = "cx", 2203 "gx"; 2204 2205 iommus = <&adreno_smmu 5 0x400>; 2206 2207 qcom,qmp = <&aoss_qmp>; 2208 2209 operating-points-v2 = <&gmu_opp_table>; 2210 2211 gmu_opp_table: opp-table { 2212 compatible = "operating-points-v2"; 2213 2214 opp-500000000 { 2215 opp-hz = /bits/ 64 <500000000>; 2216 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2217 }; 2218 2219 opp-200000000 { 2220 opp-hz = /bits/ 64 <200000000>; 2221 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2222 }; 2223 }; 2224 }; 2225 2226 gpucc: clock-controller@3d90000 { 2227 compatible = "qcom,sm8450-gpucc"; 2228 reg = <0x0 0x03d90000 0x0 0xa000>; 2229 clocks = <&rpmhcc RPMH_CXO_CLK>, 2230 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2231 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2232 #clock-cells = <1>; 2233 #reset-cells = <1>; 2234 #power-domain-cells = <1>; 2235 }; 2236 2237 adreno_smmu: iommu@3da0000 { 2238 compatible = "qcom,sm8450-smmu-500", "qcom,adreno-smmu", 2239 "qcom,smmu-500", "arm,mmu-500"; 2240 reg = <0x0 0x03da0000 0x0 0x40000>; 2241 #iommu-cells = <2>; 2242 #global-interrupts = <1>; 2243 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2244 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2245 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2246 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2247 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2248 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2249 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2250 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2251 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2252 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2253 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2254 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2255 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 2256 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, 2257 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, 2258 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 2259 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, 2260 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>, 2261 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>, 2262 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>, 2263 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 2264 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 2265 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>, 2266 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 2267 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>, 2268 <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>; 2269 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2270 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2271 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2272 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2273 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2274 <&gpucc GPU_CC_AHB_CLK>; 2275 clock-names = "gmu", 2276 "hub", 2277 "hlos", 2278 "bus", 2279 "iface", 2280 "ahb"; 2281 power-domains = <&gpucc GPU_CX_GDSC>; 2282 dma-coherent; 2283 }; 2284 2285 usb_1_hsphy: phy@88e3000 { 2286 compatible = "qcom,sm8450-usb-hs-phy", 2287 "qcom,usb-snps-hs-7nm-phy"; 2288 reg = <0 0x088e3000 0 0x400>; 2289 status = "disabled"; 2290 #phy-cells = <0>; 2291 2292 clocks = <&rpmhcc RPMH_CXO_CLK>; 2293 clock-names = "ref"; 2294 2295 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2296 }; 2297 2298 usb_1_qmpphy: phy@88e8000 { 2299 compatible = "qcom,sm8450-qmp-usb3-dp-phy"; 2300 reg = <0 0x088e8000 0 0x3000>; 2301 2302 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2303 <&rpmhcc RPMH_CXO_CLK>, 2304 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2305 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2306 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2307 2308 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2309 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2310 reset-names = "phy", "common"; 2311 2312 #clock-cells = <1>; 2313 #phy-cells = <1>; 2314 2315 status = "disabled"; 2316 2317 ports { 2318 #address-cells = <1>; 2319 #size-cells = <0>; 2320 2321 port@0 { 2322 reg = <0>; 2323 2324 usb_1_qmpphy_out: endpoint { 2325 }; 2326 }; 2327 2328 port@1 { 2329 reg = <1>; 2330 2331 usb_1_qmpphy_usb_ss_in: endpoint { 2332 }; 2333 }; 2334 2335 port@2 { 2336 reg = <2>; 2337 2338 usb_1_qmpphy_dp_in: endpoint { 2339 }; 2340 }; 2341 }; 2342 }; 2343 2344 remoteproc_slpi: remoteproc@2400000 { 2345 compatible = "qcom,sm8450-slpi-pas"; 2346 reg = <0 0x02400000 0 0x4000>; 2347 2348 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2349 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2350 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2351 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2352 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2353 interrupt-names = "wdog", "fatal", "ready", 2354 "handover", "stop-ack"; 2355 2356 clocks = <&rpmhcc RPMH_CXO_CLK>; 2357 clock-names = "xo"; 2358 2359 power-domains = <&rpmhpd RPMHPD_LCX>, 2360 <&rpmhpd RPMHPD_LMX>; 2361 power-domain-names = "lcx", "lmx"; 2362 2363 memory-region = <&slpi_mem>; 2364 2365 qcom,qmp = <&aoss_qmp>; 2366 2367 qcom,smem-states = <&smp2p_slpi_out 0>; 2368 qcom,smem-state-names = "stop"; 2369 2370 status = "disabled"; 2371 2372 glink-edge { 2373 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2374 IPCC_MPROC_SIGNAL_GLINK_QMP 2375 IRQ_TYPE_EDGE_RISING>; 2376 mboxes = <&ipcc IPCC_CLIENT_SLPI 2377 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2378 2379 label = "slpi"; 2380 qcom,remote-pid = <3>; 2381 2382 fastrpc { 2383 compatible = "qcom,fastrpc"; 2384 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2385 label = "sdsp"; 2386 qcom,non-secure-domain; 2387 #address-cells = <1>; 2388 #size-cells = <0>; 2389 2390 compute-cb@1 { 2391 compatible = "qcom,fastrpc-compute-cb"; 2392 reg = <1>; 2393 iommus = <&apps_smmu 0x0541 0x0>; 2394 }; 2395 2396 compute-cb@2 { 2397 compatible = "qcom,fastrpc-compute-cb"; 2398 reg = <2>; 2399 iommus = <&apps_smmu 0x0542 0x0>; 2400 }; 2401 2402 compute-cb@3 { 2403 compatible = "qcom,fastrpc-compute-cb"; 2404 reg = <3>; 2405 iommus = <&apps_smmu 0x0543 0x0>; 2406 /* note: shared-cb = <4> in downstream */ 2407 }; 2408 }; 2409 }; 2410 }; 2411 2412 wsa2macro: codec@31e0000 { 2413 compatible = "qcom,sm8450-lpass-wsa-macro"; 2414 reg = <0 0x031e0000 0 0x1000>; 2415 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2416 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2417 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2418 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2419 <&vamacro>; 2420 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2421 2422 #clock-cells = <0>; 2423 clock-output-names = "wsa2-mclk"; 2424 #sound-dai-cells = <1>; 2425 }; 2426 2427 swr4: soundwire@31f0000 { 2428 compatible = "qcom,soundwire-v1.7.0"; 2429 reg = <0 0x031f0000 0 0x2000>; 2430 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2431 clocks = <&wsa2macro>; 2432 clock-names = "iface"; 2433 label = "WSA2"; 2434 2435 pinctrl-0 = <&wsa2_swr_active>; 2436 pinctrl-names = "default"; 2437 2438 qcom,din-ports = <2>; 2439 qcom,dout-ports = <6>; 2440 2441 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2442 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2443 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2444 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2445 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2446 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2447 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2448 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2449 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2450 2451 #address-cells = <2>; 2452 #size-cells = <0>; 2453 #sound-dai-cells = <1>; 2454 status = "disabled"; 2455 }; 2456 2457 rxmacro: codec@3200000 { 2458 compatible = "qcom,sm8450-lpass-rx-macro"; 2459 reg = <0 0x03200000 0 0x1000>; 2460 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2461 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2462 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2463 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2464 <&vamacro>; 2465 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2466 2467 #clock-cells = <0>; 2468 clock-output-names = "mclk"; 2469 #sound-dai-cells = <1>; 2470 }; 2471 2472 swr1: soundwire@3210000 { 2473 compatible = "qcom,soundwire-v1.7.0"; 2474 reg = <0 0x03210000 0 0x2000>; 2475 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2476 clocks = <&rxmacro>; 2477 clock-names = "iface"; 2478 label = "RX"; 2479 qcom,din-ports = <0>; 2480 qcom,dout-ports = <5>; 2481 2482 pinctrl-0 = <&rx_swr_active>; 2483 pinctrl-names = "default"; 2484 2485 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2486 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; 2487 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2488 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2489 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2490 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2491 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2492 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2493 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2494 2495 #address-cells = <2>; 2496 #size-cells = <0>; 2497 #sound-dai-cells = <1>; 2498 status = "disabled"; 2499 }; 2500 2501 txmacro: codec@3220000 { 2502 compatible = "qcom,sm8450-lpass-tx-macro"; 2503 reg = <0 0x03220000 0 0x1000>; 2504 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2505 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2506 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2507 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2508 <&vamacro>; 2509 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2510 2511 #clock-cells = <0>; 2512 clock-output-names = "mclk"; 2513 #sound-dai-cells = <1>; 2514 }; 2515 2516 wsamacro: codec@3240000 { 2517 compatible = "qcom,sm8450-lpass-wsa-macro"; 2518 reg = <0 0x03240000 0 0x1000>; 2519 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2520 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2521 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2522 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2523 <&vamacro>; 2524 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2525 2526 #clock-cells = <0>; 2527 clock-output-names = "mclk"; 2528 #sound-dai-cells = <1>; 2529 }; 2530 2531 swr0: soundwire@3250000 { 2532 compatible = "qcom,soundwire-v1.7.0"; 2533 reg = <0 0x03250000 0 0x2000>; 2534 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2535 clocks = <&wsamacro>; 2536 clock-names = "iface"; 2537 label = "WSA"; 2538 2539 pinctrl-0 = <&wsa_swr_active>; 2540 pinctrl-names = "default"; 2541 2542 qcom,din-ports = <2>; 2543 qcom,dout-ports = <6>; 2544 2545 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2546 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2547 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2548 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2549 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2550 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2551 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2552 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2553 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2554 2555 #address-cells = <2>; 2556 #size-cells = <0>; 2557 #sound-dai-cells = <1>; 2558 status = "disabled"; 2559 }; 2560 2561 swr2: soundwire@33b0000 { 2562 compatible = "qcom,soundwire-v1.7.0"; 2563 reg = <0 0x033b0000 0 0x2000>; 2564 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2565 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2566 interrupt-names = "core", "wakeup"; 2567 2568 clocks = <&txmacro>; 2569 clock-names = "iface"; 2570 label = "TX"; 2571 2572 pinctrl-0 = <&tx_swr_active>; 2573 pinctrl-names = "default"; 2574 2575 qcom,din-ports = <4>; 2576 qcom,dout-ports = <0>; 2577 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2578 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 2579 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2580 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2581 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2582 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2583 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2584 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2585 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 2586 2587 #address-cells = <2>; 2588 #size-cells = <0>; 2589 #sound-dai-cells = <1>; 2590 status = "disabled"; 2591 }; 2592 2593 vamacro: codec@33f0000 { 2594 compatible = "qcom,sm8450-lpass-va-macro"; 2595 reg = <0 0x033f0000 0 0x1000>; 2596 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2597 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2598 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2599 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2600 clock-names = "mclk", "macro", "dcodec", "npl"; 2601 2602 #clock-cells = <0>; 2603 clock-output-names = "fsgen"; 2604 #sound-dai-cells = <1>; 2605 status = "disabled"; 2606 }; 2607 2608 remoteproc_adsp: remoteproc@30000000 { 2609 compatible = "qcom,sm8450-adsp-pas"; 2610 reg = <0 0x30000000 0 0x100>; 2611 2612 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2613 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2614 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2615 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2616 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2617 interrupt-names = "wdog", "fatal", "ready", 2618 "handover", "stop-ack"; 2619 2620 clocks = <&rpmhcc RPMH_CXO_CLK>; 2621 clock-names = "xo"; 2622 2623 power-domains = <&rpmhpd RPMHPD_LCX>, 2624 <&rpmhpd RPMHPD_LMX>; 2625 power-domain-names = "lcx", "lmx"; 2626 2627 memory-region = <&adsp_mem>; 2628 2629 qcom,qmp = <&aoss_qmp>; 2630 2631 qcom,smem-states = <&smp2p_adsp_out 0>; 2632 qcom,smem-state-names = "stop"; 2633 2634 status = "disabled"; 2635 2636 remoteproc_adsp_glink: glink-edge { 2637 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2638 IPCC_MPROC_SIGNAL_GLINK_QMP 2639 IRQ_TYPE_EDGE_RISING>; 2640 mboxes = <&ipcc IPCC_CLIENT_LPASS 2641 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2642 2643 label = "lpass"; 2644 qcom,remote-pid = <2>; 2645 2646 gpr { 2647 compatible = "qcom,gpr"; 2648 qcom,glink-channels = "adsp_apps"; 2649 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2650 qcom,intents = <512 20>; 2651 #address-cells = <1>; 2652 #size-cells = <0>; 2653 2654 q6apm: service@1 { 2655 compatible = "qcom,q6apm"; 2656 reg = <GPR_APM_MODULE_IID>; 2657 #sound-dai-cells = <0>; 2658 qcom,protection-domain = "avs/audio", 2659 "msm/adsp/audio_pd"; 2660 2661 q6apmdai: dais { 2662 compatible = "qcom,q6apm-dais"; 2663 iommus = <&apps_smmu 0x1801 0x0>; 2664 }; 2665 2666 q6apmbedai: bedais { 2667 compatible = "qcom,q6apm-lpass-dais"; 2668 #sound-dai-cells = <1>; 2669 }; 2670 }; 2671 2672 q6prm: service@2 { 2673 compatible = "qcom,q6prm"; 2674 reg = <GPR_PRM_MODULE_IID>; 2675 qcom,protection-domain = "avs/audio", 2676 "msm/adsp/audio_pd"; 2677 2678 q6prmcc: clock-controller { 2679 compatible = "qcom,q6prm-lpass-clocks"; 2680 #clock-cells = <2>; 2681 }; 2682 }; 2683 }; 2684 2685 fastrpc { 2686 compatible = "qcom,fastrpc"; 2687 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2688 label = "adsp"; 2689 qcom,non-secure-domain; 2690 #address-cells = <1>; 2691 #size-cells = <0>; 2692 2693 compute-cb@3 { 2694 compatible = "qcom,fastrpc-compute-cb"; 2695 reg = <3>; 2696 iommus = <&apps_smmu 0x1803 0x0>; 2697 }; 2698 2699 compute-cb@4 { 2700 compatible = "qcom,fastrpc-compute-cb"; 2701 reg = <4>; 2702 iommus = <&apps_smmu 0x1804 0x0>; 2703 }; 2704 2705 compute-cb@5 { 2706 compatible = "qcom,fastrpc-compute-cb"; 2707 reg = <5>; 2708 iommus = <&apps_smmu 0x1805 0x0>; 2709 }; 2710 }; 2711 }; 2712 }; 2713 2714 remoteproc_cdsp: remoteproc@32300000 { 2715 compatible = "qcom,sm8450-cdsp-pas"; 2716 reg = <0 0x32300000 0 0x1400000>; 2717 2718 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2719 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2720 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2721 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2722 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 2723 interrupt-names = "wdog", "fatal", "ready", 2724 "handover", "stop-ack"; 2725 2726 clocks = <&rpmhcc RPMH_CXO_CLK>; 2727 clock-names = "xo"; 2728 2729 power-domains = <&rpmhpd RPMHPD_CX>, 2730 <&rpmhpd RPMHPD_MXC>; 2731 power-domain-names = "cx", "mxc"; 2732 2733 memory-region = <&cdsp_mem>; 2734 2735 qcom,qmp = <&aoss_qmp>; 2736 2737 qcom,smem-states = <&smp2p_cdsp_out 0>; 2738 qcom,smem-state-names = "stop"; 2739 2740 status = "disabled"; 2741 2742 glink-edge { 2743 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2744 IPCC_MPROC_SIGNAL_GLINK_QMP 2745 IRQ_TYPE_EDGE_RISING>; 2746 mboxes = <&ipcc IPCC_CLIENT_CDSP 2747 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2748 2749 label = "cdsp"; 2750 qcom,remote-pid = <5>; 2751 2752 fastrpc { 2753 compatible = "qcom,fastrpc"; 2754 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2755 label = "cdsp"; 2756 qcom,non-secure-domain; 2757 #address-cells = <1>; 2758 #size-cells = <0>; 2759 2760 compute-cb@1 { 2761 compatible = "qcom,fastrpc-compute-cb"; 2762 reg = <1>; 2763 iommus = <&apps_smmu 0x2161 0x0400>, 2764 <&apps_smmu 0x1021 0x1420>; 2765 }; 2766 2767 compute-cb@2 { 2768 compatible = "qcom,fastrpc-compute-cb"; 2769 reg = <2>; 2770 iommus = <&apps_smmu 0x2162 0x0400>, 2771 <&apps_smmu 0x1022 0x1420>; 2772 }; 2773 2774 compute-cb@3 { 2775 compatible = "qcom,fastrpc-compute-cb"; 2776 reg = <3>; 2777 iommus = <&apps_smmu 0x2163 0x0400>, 2778 <&apps_smmu 0x1023 0x1420>; 2779 }; 2780 2781 compute-cb@4 { 2782 compatible = "qcom,fastrpc-compute-cb"; 2783 reg = <4>; 2784 iommus = <&apps_smmu 0x2164 0x0400>, 2785 <&apps_smmu 0x1024 0x1420>; 2786 }; 2787 2788 compute-cb@5 { 2789 compatible = "qcom,fastrpc-compute-cb"; 2790 reg = <5>; 2791 iommus = <&apps_smmu 0x2165 0x0400>, 2792 <&apps_smmu 0x1025 0x1420>; 2793 }; 2794 2795 compute-cb@6 { 2796 compatible = "qcom,fastrpc-compute-cb"; 2797 reg = <6>; 2798 iommus = <&apps_smmu 0x2166 0x0400>, 2799 <&apps_smmu 0x1026 0x1420>; 2800 }; 2801 2802 compute-cb@7 { 2803 compatible = "qcom,fastrpc-compute-cb"; 2804 reg = <7>; 2805 iommus = <&apps_smmu 0x2167 0x0400>, 2806 <&apps_smmu 0x1027 0x1420>; 2807 }; 2808 2809 compute-cb@8 { 2810 compatible = "qcom,fastrpc-compute-cb"; 2811 reg = <8>; 2812 iommus = <&apps_smmu 0x2168 0x0400>, 2813 <&apps_smmu 0x1028 0x1420>; 2814 }; 2815 2816 /* note: secure cb9 in downstream */ 2817 }; 2818 }; 2819 }; 2820 2821 remoteproc_mpss: remoteproc@4080000 { 2822 compatible = "qcom,sm8450-mpss-pas"; 2823 reg = <0x0 0x04080000 0x0 0x4040>; 2824 2825 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2826 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2827 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2828 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2829 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2830 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2831 interrupt-names = "wdog", "fatal", "ready", "handover", 2832 "stop-ack", "shutdown-ack"; 2833 2834 clocks = <&rpmhcc RPMH_CXO_CLK>; 2835 clock-names = "xo"; 2836 2837 power-domains = <&rpmhpd RPMHPD_CX>, 2838 <&rpmhpd RPMHPD_MSS>; 2839 power-domain-names = "cx", "mss"; 2840 2841 memory-region = <&mpss_mem>; 2842 2843 qcom,qmp = <&aoss_qmp>; 2844 2845 qcom,smem-states = <&smp2p_modem_out 0>; 2846 qcom,smem-state-names = "stop"; 2847 2848 status = "disabled"; 2849 2850 glink-edge { 2851 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2852 IPCC_MPROC_SIGNAL_GLINK_QMP 2853 IRQ_TYPE_EDGE_RISING>; 2854 mboxes = <&ipcc IPCC_CLIENT_MPSS 2855 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2856 label = "modem"; 2857 qcom,remote-pid = <1>; 2858 }; 2859 }; 2860 2861 videocc: clock-controller@aaf0000 { 2862 compatible = "qcom,sm8450-videocc"; 2863 reg = <0 0x0aaf0000 0 0x10000>; 2864 clocks = <&rpmhcc RPMH_CXO_CLK>, 2865 <&gcc GCC_VIDEO_AHB_CLK>; 2866 power-domains = <&rpmhpd RPMHPD_MMCX>; 2867 required-opps = <&rpmhpd_opp_low_svs>; 2868 #clock-cells = <1>; 2869 #reset-cells = <1>; 2870 #power-domain-cells = <1>; 2871 }; 2872 2873 cci0: cci@ac15000 { 2874 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; 2875 reg = <0 0x0ac15000 0 0x1000>; 2876 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 2877 power-domains = <&camcc TITAN_TOP_GDSC>; 2878 2879 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 2880 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 2881 <&camcc CAM_CC_CPAS_AHB_CLK>, 2882 <&camcc CAM_CC_CCI_0_CLK>, 2883 <&camcc CAM_CC_CCI_0_CLK_SRC>; 2884 clock-names = "camnoc_axi", 2885 "slow_ahb_src", 2886 "cpas_ahb", 2887 "cci", 2888 "cci_src"; 2889 pinctrl-0 = <&cci0_default &cci1_default>; 2890 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 2891 pinctrl-names = "default", "sleep"; 2892 2893 status = "disabled"; 2894 #address-cells = <1>; 2895 #size-cells = <0>; 2896 2897 cci0_i2c0: i2c-bus@0 { 2898 reg = <0>; 2899 clock-frequency = <1000000>; 2900 #address-cells = <1>; 2901 #size-cells = <0>; 2902 }; 2903 2904 cci0_i2c1: i2c-bus@1 { 2905 reg = <1>; 2906 clock-frequency = <1000000>; 2907 #address-cells = <1>; 2908 #size-cells = <0>; 2909 }; 2910 }; 2911 2912 cci1: cci@ac16000 { 2913 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; 2914 reg = <0 0x0ac16000 0 0x1000>; 2915 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 2916 power-domains = <&camcc TITAN_TOP_GDSC>; 2917 2918 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 2919 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 2920 <&camcc CAM_CC_CPAS_AHB_CLK>, 2921 <&camcc CAM_CC_CCI_1_CLK>, 2922 <&camcc CAM_CC_CCI_1_CLK_SRC>; 2923 clock-names = "camnoc_axi", 2924 "slow_ahb_src", 2925 "cpas_ahb", 2926 "cci", 2927 "cci_src"; 2928 pinctrl-0 = <&cci2_default &cci3_default>; 2929 pinctrl-1 = <&cci2_sleep &cci3_sleep>; 2930 pinctrl-names = "default", "sleep"; 2931 2932 status = "disabled"; 2933 #address-cells = <1>; 2934 #size-cells = <0>; 2935 2936 cci1_i2c0: i2c-bus@0 { 2937 reg = <0>; 2938 clock-frequency = <1000000>; 2939 #address-cells = <1>; 2940 #size-cells = <0>; 2941 }; 2942 2943 cci1_i2c1: i2c-bus@1 { 2944 reg = <1>; 2945 clock-frequency = <1000000>; 2946 #address-cells = <1>; 2947 #size-cells = <0>; 2948 }; 2949 }; 2950 2951 camcc: clock-controller@ade0000 { 2952 compatible = "qcom,sm8450-camcc"; 2953 reg = <0 0x0ade0000 0 0x20000>; 2954 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 2955 <&rpmhcc RPMH_CXO_CLK>, 2956 <&rpmhcc RPMH_CXO_CLK_A>, 2957 <&sleep_clk>; 2958 power-domains = <&rpmhpd RPMHPD_MMCX>; 2959 required-opps = <&rpmhpd_opp_low_svs>; 2960 #clock-cells = <1>; 2961 #reset-cells = <1>; 2962 #power-domain-cells = <1>; 2963 status = "disabled"; 2964 }; 2965 2966 mdss: display-subsystem@ae00000 { 2967 compatible = "qcom,sm8450-mdss"; 2968 reg = <0 0x0ae00000 0 0x1000>; 2969 reg-names = "mdss"; 2970 2971 /* same path used twice */ 2972 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, 2973 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, 2974 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2975 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 2976 interconnect-names = "mdp0-mem", 2977 "mdp1-mem", 2978 "cpu-cfg"; 2979 2980 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2981 2982 power-domains = <&dispcc MDSS_GDSC>; 2983 2984 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2985 <&gcc GCC_DISP_HF_AXI_CLK>, 2986 <&gcc GCC_DISP_SF_AXI_CLK>, 2987 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2988 2989 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2990 interrupt-controller; 2991 #interrupt-cells = <1>; 2992 2993 iommus = <&apps_smmu 0x2800 0x402>; 2994 2995 #address-cells = <2>; 2996 #size-cells = <2>; 2997 ranges; 2998 2999 status = "disabled"; 3000 3001 mdss_mdp: display-controller@ae01000 { 3002 compatible = "qcom,sm8450-dpu"; 3003 reg = <0 0x0ae01000 0 0x8f000>, 3004 <0 0x0aeb0000 0 0x2008>; 3005 reg-names = "mdp", "vbif"; 3006 3007 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3008 <&gcc GCC_DISP_SF_AXI_CLK>, 3009 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3010 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3011 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3012 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3013 clock-names = "bus", 3014 "nrt_bus", 3015 "iface", 3016 "lut", 3017 "core", 3018 "vsync"; 3019 3020 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3021 assigned-clock-rates = <19200000>; 3022 3023 operating-points-v2 = <&mdp_opp_table>; 3024 power-domains = <&rpmhpd RPMHPD_MMCX>; 3025 3026 interrupt-parent = <&mdss>; 3027 interrupts = <0>; 3028 3029 ports { 3030 #address-cells = <1>; 3031 #size-cells = <0>; 3032 3033 port@0 { 3034 reg = <0>; 3035 dpu_intf1_out: endpoint { 3036 remote-endpoint = <&mdss_dsi0_in>; 3037 }; 3038 }; 3039 3040 port@1 { 3041 reg = <1>; 3042 dpu_intf2_out: endpoint { 3043 remote-endpoint = <&mdss_dsi1_in>; 3044 }; 3045 }; 3046 3047 port@2 { 3048 reg = <2>; 3049 dpu_intf0_out: endpoint { 3050 remote-endpoint = <&mdss_dp0_in>; 3051 }; 3052 }; 3053 }; 3054 3055 mdp_opp_table: opp-table { 3056 compatible = "operating-points-v2"; 3057 3058 opp-172000000 { 3059 opp-hz = /bits/ 64 <172000000>; 3060 required-opps = <&rpmhpd_opp_low_svs_d1>; 3061 }; 3062 3063 opp-200000000 { 3064 opp-hz = /bits/ 64 <200000000>; 3065 required-opps = <&rpmhpd_opp_low_svs>; 3066 }; 3067 3068 opp-325000000 { 3069 opp-hz = /bits/ 64 <325000000>; 3070 required-opps = <&rpmhpd_opp_svs>; 3071 }; 3072 3073 opp-375000000 { 3074 opp-hz = /bits/ 64 <375000000>; 3075 required-opps = <&rpmhpd_opp_svs_l1>; 3076 }; 3077 3078 opp-500000000 { 3079 opp-hz = /bits/ 64 <500000000>; 3080 required-opps = <&rpmhpd_opp_nom>; 3081 }; 3082 }; 3083 }; 3084 3085 mdss_dp0: displayport-controller@ae90000 { 3086 compatible = "qcom,sm8450-dp", "qcom,sm8350-dp"; 3087 reg = <0 0xae90000 0 0x200>, 3088 <0 0xae90200 0 0x200>, 3089 <0 0xae90400 0 0xc00>, 3090 <0 0xae91000 0 0x400>, 3091 <0 0xae91400 0 0x400>; 3092 interrupt-parent = <&mdss>; 3093 interrupts = <12>; 3094 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3095 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 3096 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 3097 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 3098 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 3099 clock-names = "core_iface", 3100 "core_aux", 3101 "ctrl_link", 3102 "ctrl_link_iface", 3103 "stream_pixel"; 3104 3105 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 3106 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 3107 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3108 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3109 3110 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 3111 phy-names = "dp"; 3112 3113 #sound-dai-cells = <0>; 3114 3115 operating-points-v2 = <&dp_opp_table>; 3116 power-domains = <&rpmhpd RPMHPD_MMCX>; 3117 3118 status = "disabled"; 3119 3120 ports { 3121 #address-cells = <1>; 3122 #size-cells = <0>; 3123 3124 port@0 { 3125 reg = <0>; 3126 mdss_dp0_in: endpoint { 3127 remote-endpoint = <&dpu_intf0_out>; 3128 }; 3129 }; 3130 }; 3131 3132 dp_opp_table: opp-table { 3133 compatible = "operating-points-v2"; 3134 3135 opp-160000000 { 3136 opp-hz = /bits/ 64 <160000000>; 3137 required-opps = <&rpmhpd_opp_low_svs>; 3138 }; 3139 3140 opp-270000000 { 3141 opp-hz = /bits/ 64 <270000000>; 3142 required-opps = <&rpmhpd_opp_svs>; 3143 }; 3144 3145 opp-540000000 { 3146 opp-hz = /bits/ 64 <540000000>; 3147 required-opps = <&rpmhpd_opp_svs_l1>; 3148 }; 3149 3150 opp-810000000 { 3151 opp-hz = /bits/ 64 <810000000>; 3152 required-opps = <&rpmhpd_opp_nom>; 3153 }; 3154 }; 3155 }; 3156 3157 mdss_dsi0: dsi@ae94000 { 3158 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3159 reg = <0 0x0ae94000 0 0x400>; 3160 reg-names = "dsi_ctrl"; 3161 3162 interrupt-parent = <&mdss>; 3163 interrupts = <4>; 3164 3165 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3166 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3167 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3168 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3169 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3170 <&gcc GCC_DISP_HF_AXI_CLK>; 3171 clock-names = "byte", 3172 "byte_intf", 3173 "pixel", 3174 "core", 3175 "iface", 3176 "bus"; 3177 3178 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3179 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 3180 3181 operating-points-v2 = <&mdss_dsi_opp_table>; 3182 power-domains = <&rpmhpd RPMHPD_MMCX>; 3183 3184 phys = <&mdss_dsi0_phy>; 3185 phy-names = "dsi"; 3186 3187 #address-cells = <1>; 3188 #size-cells = <0>; 3189 3190 status = "disabled"; 3191 3192 ports { 3193 #address-cells = <1>; 3194 #size-cells = <0>; 3195 3196 port@0 { 3197 reg = <0>; 3198 mdss_dsi0_in: endpoint { 3199 remote-endpoint = <&dpu_intf1_out>; 3200 }; 3201 }; 3202 3203 port@1 { 3204 reg = <1>; 3205 mdss_dsi0_out: endpoint { 3206 }; 3207 }; 3208 }; 3209 3210 mdss_dsi_opp_table: opp-table { 3211 compatible = "operating-points-v2"; 3212 3213 opp-187500000 { 3214 opp-hz = /bits/ 64 <187500000>; 3215 required-opps = <&rpmhpd_opp_low_svs>; 3216 }; 3217 3218 opp-300000000 { 3219 opp-hz = /bits/ 64 <300000000>; 3220 required-opps = <&rpmhpd_opp_svs>; 3221 }; 3222 3223 opp-358000000 { 3224 opp-hz = /bits/ 64 <358000000>; 3225 required-opps = <&rpmhpd_opp_svs_l1>; 3226 }; 3227 }; 3228 }; 3229 3230 mdss_dsi0_phy: phy@ae94400 { 3231 compatible = "qcom,sm8450-dsi-phy-5nm"; 3232 reg = <0 0x0ae94400 0 0x200>, 3233 <0 0x0ae94600 0 0x280>, 3234 <0 0x0ae94900 0 0x260>; 3235 reg-names = "dsi_phy", 3236 "dsi_phy_lane", 3237 "dsi_pll"; 3238 3239 #clock-cells = <1>; 3240 #phy-cells = <0>; 3241 3242 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3243 <&rpmhcc RPMH_CXO_CLK>; 3244 clock-names = "iface", "ref"; 3245 3246 status = "disabled"; 3247 }; 3248 3249 mdss_dsi1: dsi@ae96000 { 3250 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3251 reg = <0 0x0ae96000 0 0x400>; 3252 reg-names = "dsi_ctrl"; 3253 3254 interrupt-parent = <&mdss>; 3255 interrupts = <5>; 3256 3257 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3258 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3259 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3260 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3261 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3262 <&gcc GCC_DISP_HF_AXI_CLK>; 3263 clock-names = "byte", 3264 "byte_intf", 3265 "pixel", 3266 "core", 3267 "iface", 3268 "bus"; 3269 3270 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3271 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 3272 3273 operating-points-v2 = <&mdss_dsi_opp_table>; 3274 power-domains = <&rpmhpd RPMHPD_MMCX>; 3275 3276 phys = <&mdss_dsi1_phy>; 3277 phy-names = "dsi"; 3278 3279 #address-cells = <1>; 3280 #size-cells = <0>; 3281 3282 status = "disabled"; 3283 3284 ports { 3285 #address-cells = <1>; 3286 #size-cells = <0>; 3287 3288 port@0 { 3289 reg = <0>; 3290 mdss_dsi1_in: endpoint { 3291 remote-endpoint = <&dpu_intf2_out>; 3292 }; 3293 }; 3294 3295 port@1 { 3296 reg = <1>; 3297 mdss_dsi1_out: endpoint { 3298 }; 3299 }; 3300 }; 3301 }; 3302 3303 mdss_dsi1_phy: phy@ae96400 { 3304 compatible = "qcom,sm8450-dsi-phy-5nm"; 3305 reg = <0 0x0ae96400 0 0x200>, 3306 <0 0x0ae96600 0 0x280>, 3307 <0 0x0ae96900 0 0x260>; 3308 reg-names = "dsi_phy", 3309 "dsi_phy_lane", 3310 "dsi_pll"; 3311 3312 #clock-cells = <1>; 3313 #phy-cells = <0>; 3314 3315 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3316 <&rpmhcc RPMH_CXO_CLK>; 3317 clock-names = "iface", "ref"; 3318 3319 status = "disabled"; 3320 }; 3321 }; 3322 3323 dispcc: clock-controller@af00000 { 3324 compatible = "qcom,sm8450-dispcc"; 3325 reg = <0 0x0af00000 0 0x20000>; 3326 clocks = <&rpmhcc RPMH_CXO_CLK>, 3327 <&rpmhcc RPMH_CXO_CLK_A>, 3328 <&gcc GCC_DISP_AHB_CLK>, 3329 <&sleep_clk>, 3330 <&mdss_dsi0_phy 0>, 3331 <&mdss_dsi0_phy 1>, 3332 <&mdss_dsi1_phy 0>, 3333 <&mdss_dsi1_phy 1>, 3334 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3335 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3336 <0>, /* dp1 */ 3337 <0>, 3338 <0>, /* dp2 */ 3339 <0>, 3340 <0>, /* dp3 */ 3341 <0>; 3342 power-domains = <&rpmhpd RPMHPD_MMCX>; 3343 required-opps = <&rpmhpd_opp_low_svs>; 3344 #clock-cells = <1>; 3345 #reset-cells = <1>; 3346 #power-domain-cells = <1>; 3347 status = "disabled"; 3348 }; 3349 3350 pdc: interrupt-controller@b220000 { 3351 compatible = "qcom,sm8450-pdc", "qcom,pdc"; 3352 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 3353 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, 3354 <94 609 31>, <125 63 1>, <126 716 12>; 3355 #interrupt-cells = <2>; 3356 interrupt-parent = <&intc>; 3357 interrupt-controller; 3358 }; 3359 3360 tsens0: thermal-sensor@c263000 { 3361 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 3362 reg = <0 0x0c263000 0 0x1000>, /* TM */ 3363 <0 0x0c222000 0 0x1000>; /* SROT */ 3364 #qcom,sensors = <16>; 3365 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3366 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3367 interrupt-names = "uplow", "critical"; 3368 #thermal-sensor-cells = <1>; 3369 }; 3370 3371 tsens1: thermal-sensor@c265000 { 3372 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 3373 reg = <0 0x0c265000 0 0x1000>, /* TM */ 3374 <0 0x0c223000 0 0x1000>; /* SROT */ 3375 #qcom,sensors = <16>; 3376 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3377 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3378 interrupt-names = "uplow", "critical"; 3379 #thermal-sensor-cells = <1>; 3380 }; 3381 3382 aoss_qmp: power-management@c300000 { 3383 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; 3384 reg = <0 0x0c300000 0 0x400>; 3385 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 3386 IRQ_TYPE_EDGE_RISING>; 3387 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3388 3389 #clock-cells = <0>; 3390 }; 3391 3392 sram@c3f0000 { 3393 compatible = "qcom,rpmh-stats"; 3394 reg = <0 0x0c3f0000 0 0x400>; 3395 }; 3396 3397 spmi_bus: spmi@c400000 { 3398 compatible = "qcom,spmi-pmic-arb"; 3399 reg = <0 0x0c400000 0 0x00003000>, 3400 <0 0x0c500000 0 0x00400000>, 3401 <0 0x0c440000 0 0x00080000>, 3402 <0 0x0c4c0000 0 0x00010000>, 3403 <0 0x0c42d000 0 0x00010000>; 3404 reg-names = "core", 3405 "chnls", 3406 "obsrvr", 3407 "intr", 3408 "cnfg"; 3409 interrupt-names = "periph_irq"; 3410 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3411 qcom,ee = <0>; 3412 qcom,channel = <0>; 3413 interrupt-controller; 3414 #interrupt-cells = <4>; 3415 #address-cells = <2>; 3416 #size-cells = <0>; 3417 }; 3418 3419 ipcc: mailbox@ed18000 { 3420 compatible = "qcom,sm8450-ipcc", "qcom,ipcc"; 3421 reg = <0 0x0ed18000 0 0x1000>; 3422 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 3423 interrupt-controller; 3424 #interrupt-cells = <3>; 3425 #mbox-cells = <2>; 3426 }; 3427 3428 tlmm: pinctrl@f100000 { 3429 compatible = "qcom,sm8450-tlmm"; 3430 reg = <0 0x0f100000 0 0x300000>; 3431 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3432 gpio-controller; 3433 #gpio-cells = <2>; 3434 interrupt-controller; 3435 #interrupt-cells = <2>; 3436 gpio-ranges = <&tlmm 0 0 211>; 3437 wakeup-parent = <&pdc>; 3438 3439 sdc2_default_state: sdc2-default-state { 3440 clk-pins { 3441 pins = "sdc2_clk"; 3442 drive-strength = <16>; 3443 bias-disable; 3444 }; 3445 3446 cmd-pins { 3447 pins = "sdc2_cmd"; 3448 drive-strength = <16>; 3449 bias-pull-up; 3450 }; 3451 3452 data-pins { 3453 pins = "sdc2_data"; 3454 drive-strength = <16>; 3455 bias-pull-up; 3456 }; 3457 }; 3458 3459 sdc2_sleep_state: sdc2-sleep-state { 3460 clk-pins { 3461 pins = "sdc2_clk"; 3462 drive-strength = <2>; 3463 bias-disable; 3464 }; 3465 3466 cmd-pins { 3467 pins = "sdc2_cmd"; 3468 drive-strength = <2>; 3469 bias-pull-up; 3470 }; 3471 3472 data-pins { 3473 pins = "sdc2_data"; 3474 drive-strength = <2>; 3475 bias-pull-up; 3476 }; 3477 }; 3478 3479 cci0_default: cci0-default-state { 3480 /* SDA, SCL */ 3481 pins = "gpio110", "gpio111"; 3482 function = "cci_i2c"; 3483 drive-strength = <2>; 3484 bias-pull-up; 3485 }; 3486 3487 cci0_sleep: cci0-sleep-state { 3488 /* SDA, SCL */ 3489 pins = "gpio110", "gpio111"; 3490 function = "cci_i2c"; 3491 drive-strength = <2>; 3492 bias-pull-down; 3493 }; 3494 3495 cci1_default: cci1-default-state { 3496 /* SDA, SCL */ 3497 pins = "gpio112", "gpio113"; 3498 function = "cci_i2c"; 3499 drive-strength = <2>; 3500 bias-pull-up; 3501 }; 3502 3503 cci1_sleep: cci1-sleep-state { 3504 /* SDA, SCL */ 3505 pins = "gpio112", "gpio113"; 3506 function = "cci_i2c"; 3507 drive-strength = <2>; 3508 bias-pull-down; 3509 }; 3510 3511 cci2_default: cci2-default-state { 3512 /* SDA, SCL */ 3513 pins = "gpio114", "gpio115"; 3514 function = "cci_i2c"; 3515 drive-strength = <2>; 3516 bias-pull-up; 3517 }; 3518 3519 cci2_sleep: cci2-sleep-state { 3520 /* SDA, SCL */ 3521 pins = "gpio114", "gpio115"; 3522 function = "cci_i2c"; 3523 drive-strength = <2>; 3524 bias-pull-down; 3525 }; 3526 3527 cci3_default: cci3-default-state { 3528 /* SDA, SCL */ 3529 pins = "gpio208", "gpio209"; 3530 function = "cci_i2c"; 3531 drive-strength = <2>; 3532 bias-pull-up; 3533 }; 3534 3535 cci3_sleep: cci3-sleep-state { 3536 /* SDA, SCL */ 3537 pins = "gpio208", "gpio209"; 3538 function = "cci_i2c"; 3539 drive-strength = <2>; 3540 bias-pull-down; 3541 }; 3542 3543 pcie0_default_state: pcie0-default-state { 3544 perst-pins { 3545 pins = "gpio94"; 3546 function = "gpio"; 3547 drive-strength = <2>; 3548 bias-pull-down; 3549 }; 3550 3551 clkreq-pins { 3552 pins = "gpio95"; 3553 function = "pcie0_clkreqn"; 3554 drive-strength = <2>; 3555 bias-pull-up; 3556 }; 3557 3558 wake-pins { 3559 pins = "gpio96"; 3560 function = "gpio"; 3561 drive-strength = <2>; 3562 bias-pull-up; 3563 }; 3564 }; 3565 3566 pcie1_default_state: pcie1-default-state { 3567 perst-pins { 3568 pins = "gpio97"; 3569 function = "gpio"; 3570 drive-strength = <2>; 3571 bias-pull-down; 3572 }; 3573 3574 clkreq-pins { 3575 pins = "gpio98"; 3576 function = "pcie1_clkreqn"; 3577 drive-strength = <2>; 3578 bias-pull-up; 3579 }; 3580 3581 wake-pins { 3582 pins = "gpio99"; 3583 function = "gpio"; 3584 drive-strength = <2>; 3585 bias-pull-up; 3586 }; 3587 }; 3588 3589 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 3590 pins = "gpio0", "gpio1"; 3591 function = "qup0"; 3592 }; 3593 3594 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 3595 pins = "gpio4", "gpio5"; 3596 function = "qup1"; 3597 }; 3598 3599 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 3600 pins = "gpio8", "gpio9"; 3601 function = "qup2"; 3602 }; 3603 3604 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 3605 pins = "gpio12", "gpio13"; 3606 function = "qup3"; 3607 }; 3608 3609 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 3610 pins = "gpio16", "gpio17"; 3611 function = "qup4"; 3612 }; 3613 3614 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 3615 pins = "gpio206", "gpio207"; 3616 function = "qup5"; 3617 }; 3618 3619 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 3620 pins = "gpio20", "gpio21"; 3621 function = "qup6"; 3622 }; 3623 3624 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 3625 pins = "gpio28", "gpio29"; 3626 function = "qup8"; 3627 }; 3628 3629 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 3630 pins = "gpio32", "gpio33"; 3631 function = "qup9"; 3632 }; 3633 3634 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 3635 pins = "gpio36", "gpio37"; 3636 function = "qup10"; 3637 }; 3638 3639 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 3640 pins = "gpio40", "gpio41"; 3641 function = "qup11"; 3642 }; 3643 3644 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 3645 pins = "gpio44", "gpio45"; 3646 function = "qup12"; 3647 }; 3648 3649 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 3650 pins = "gpio48", "gpio49"; 3651 function = "qup13"; 3652 drive-strength = <2>; 3653 bias-pull-up; 3654 }; 3655 3656 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 3657 pins = "gpio52", "gpio53"; 3658 function = "qup14"; 3659 drive-strength = <2>; 3660 bias-pull-up; 3661 }; 3662 3663 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 3664 pins = "gpio56", "gpio57"; 3665 function = "qup15"; 3666 }; 3667 3668 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 3669 pins = "gpio60", "gpio61"; 3670 function = "qup16"; 3671 }; 3672 3673 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 3674 pins = "gpio64", "gpio65"; 3675 function = "qup17"; 3676 }; 3677 3678 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 3679 pins = "gpio68", "gpio69"; 3680 function = "qup18"; 3681 }; 3682 3683 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 3684 pins = "gpio72", "gpio73"; 3685 function = "qup19"; 3686 }; 3687 3688 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 3689 pins = "gpio76", "gpio77"; 3690 function = "qup20"; 3691 }; 3692 3693 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 3694 pins = "gpio80", "gpio81"; 3695 function = "qup21"; 3696 }; 3697 3698 qup_spi0_cs: qup-spi0-cs-state { 3699 pins = "gpio3"; 3700 function = "qup0"; 3701 }; 3702 3703 qup_spi0_data_clk: qup-spi0-data-clk-state { 3704 pins = "gpio0", "gpio1", "gpio2"; 3705 function = "qup0"; 3706 }; 3707 3708 qup_spi1_cs: qup-spi1-cs-state { 3709 pins = "gpio7"; 3710 function = "qup1"; 3711 }; 3712 3713 qup_spi1_data_clk: qup-spi1-data-clk-state { 3714 pins = "gpio4", "gpio5", "gpio6"; 3715 function = "qup1"; 3716 }; 3717 3718 qup_spi2_cs: qup-spi2-cs-state { 3719 pins = "gpio11"; 3720 function = "qup2"; 3721 }; 3722 3723 qup_spi2_data_clk: qup-spi2-data-clk-state { 3724 pins = "gpio8", "gpio9", "gpio10"; 3725 function = "qup2"; 3726 }; 3727 3728 qup_spi3_cs: qup-spi3-cs-state { 3729 pins = "gpio15"; 3730 function = "qup3"; 3731 }; 3732 3733 qup_spi3_data_clk: qup-spi3-data-clk-state { 3734 pins = "gpio12", "gpio13", "gpio14"; 3735 function = "qup3"; 3736 }; 3737 3738 qup_spi4_cs: qup-spi4-cs-state { 3739 pins = "gpio19"; 3740 function = "qup4"; 3741 drive-strength = <6>; 3742 bias-disable; 3743 }; 3744 3745 qup_spi4_data_clk: qup-spi4-data-clk-state { 3746 pins = "gpio16", "gpio17", "gpio18"; 3747 function = "qup4"; 3748 }; 3749 3750 qup_spi5_cs: qup-spi5-cs-state { 3751 pins = "gpio85"; 3752 function = "qup5"; 3753 }; 3754 3755 qup_spi5_data_clk: qup-spi5-data-clk-state { 3756 pins = "gpio206", "gpio207", "gpio84"; 3757 function = "qup5"; 3758 }; 3759 3760 qup_spi6_cs: qup-spi6-cs-state { 3761 pins = "gpio23"; 3762 function = "qup6"; 3763 }; 3764 3765 qup_spi6_data_clk: qup-spi6-data-clk-state { 3766 pins = "gpio20", "gpio21", "gpio22"; 3767 function = "qup6"; 3768 }; 3769 3770 qup_spi8_cs: qup-spi8-cs-state { 3771 pins = "gpio31"; 3772 function = "qup8"; 3773 }; 3774 3775 qup_spi8_data_clk: qup-spi8-data-clk-state { 3776 pins = "gpio28", "gpio29", "gpio30"; 3777 function = "qup8"; 3778 }; 3779 3780 qup_spi9_cs: qup-spi9-cs-state { 3781 pins = "gpio35"; 3782 function = "qup9"; 3783 }; 3784 3785 qup_spi9_data_clk: qup-spi9-data-clk-state { 3786 pins = "gpio32", "gpio33", "gpio34"; 3787 function = "qup9"; 3788 }; 3789 3790 qup_spi10_cs: qup-spi10-cs-state { 3791 pins = "gpio39"; 3792 function = "qup10"; 3793 }; 3794 3795 qup_spi10_data_clk: qup-spi10-data-clk-state { 3796 pins = "gpio36", "gpio37", "gpio38"; 3797 function = "qup10"; 3798 }; 3799 3800 qup_spi11_cs: qup-spi11-cs-state { 3801 pins = "gpio43"; 3802 function = "qup11"; 3803 }; 3804 3805 qup_spi11_data_clk: qup-spi11-data-clk-state { 3806 pins = "gpio40", "gpio41", "gpio42"; 3807 function = "qup11"; 3808 }; 3809 3810 qup_spi12_cs: qup-spi12-cs-state { 3811 pins = "gpio47"; 3812 function = "qup12"; 3813 }; 3814 3815 qup_spi12_data_clk: qup-spi12-data-clk-state { 3816 pins = "gpio44", "gpio45", "gpio46"; 3817 function = "qup12"; 3818 }; 3819 3820 qup_spi13_cs: qup-spi13-cs-state { 3821 pins = "gpio51"; 3822 function = "qup13"; 3823 }; 3824 3825 qup_spi13_data_clk: qup-spi13-data-clk-state { 3826 pins = "gpio48", "gpio49", "gpio50"; 3827 function = "qup13"; 3828 }; 3829 3830 qup_spi14_cs: qup-spi14-cs-state { 3831 pins = "gpio55"; 3832 function = "qup14"; 3833 }; 3834 3835 qup_spi14_data_clk: qup-spi14-data-clk-state { 3836 pins = "gpio52", "gpio53", "gpio54"; 3837 function = "qup14"; 3838 }; 3839 3840 qup_spi15_cs: qup-spi15-cs-state { 3841 pins = "gpio59"; 3842 function = "qup15"; 3843 }; 3844 3845 qup_spi15_data_clk: qup-spi15-data-clk-state { 3846 pins = "gpio56", "gpio57", "gpio58"; 3847 function = "qup15"; 3848 }; 3849 3850 qup_spi16_cs: qup-spi16-cs-state { 3851 pins = "gpio63"; 3852 function = "qup16"; 3853 }; 3854 3855 qup_spi16_data_clk: qup-spi16-data-clk-state { 3856 pins = "gpio60", "gpio61", "gpio62"; 3857 function = "qup16"; 3858 }; 3859 3860 qup_spi17_cs: qup-spi17-cs-state { 3861 pins = "gpio67"; 3862 function = "qup17"; 3863 }; 3864 3865 qup_spi17_data_clk: qup-spi17-data-clk-state { 3866 pins = "gpio64", "gpio65", "gpio66"; 3867 function = "qup17"; 3868 }; 3869 3870 qup_spi18_cs: qup-spi18-cs-state { 3871 pins = "gpio71"; 3872 function = "qup18"; 3873 drive-strength = <6>; 3874 bias-disable; 3875 }; 3876 3877 qup_spi18_data_clk: qup-spi18-data-clk-state { 3878 pins = "gpio68", "gpio69", "gpio70"; 3879 function = "qup18"; 3880 drive-strength = <6>; 3881 bias-disable; 3882 }; 3883 3884 qup_spi19_cs: qup-spi19-cs-state { 3885 pins = "gpio75"; 3886 function = "qup19"; 3887 drive-strength = <6>; 3888 bias-disable; 3889 }; 3890 3891 qup_spi19_data_clk: qup-spi19-data-clk-state { 3892 pins = "gpio72", "gpio73", "gpio74"; 3893 function = "qup19"; 3894 drive-strength = <6>; 3895 bias-disable; 3896 }; 3897 3898 qup_spi20_cs: qup-spi20-cs-state { 3899 pins = "gpio79"; 3900 function = "qup20"; 3901 }; 3902 3903 qup_spi20_data_clk: qup-spi20-data-clk-state { 3904 pins = "gpio76", "gpio77", "gpio78"; 3905 function = "qup20"; 3906 }; 3907 3908 qup_spi21_cs: qup-spi21-cs-state { 3909 pins = "gpio83"; 3910 function = "qup21"; 3911 }; 3912 3913 qup_spi21_data_clk: qup-spi21-data-clk-state { 3914 pins = "gpio80", "gpio81", "gpio82"; 3915 function = "qup21"; 3916 }; 3917 3918 qup_uart7_rx: qup-uart7-rx-state { 3919 pins = "gpio26"; 3920 function = "qup7"; 3921 drive-strength = <2>; 3922 bias-disable; 3923 }; 3924 3925 qup_uart7_tx: qup-uart7-tx-state { 3926 pins = "gpio27"; 3927 function = "qup7"; 3928 drive-strength = <2>; 3929 bias-disable; 3930 }; 3931 3932 qup_uart20_default: qup-uart20-default-state { 3933 pins = "gpio76", "gpio77", "gpio78", "gpio79"; 3934 function = "qup20"; 3935 }; 3936 }; 3937 3938 lpass_tlmm: pinctrl@3440000 { 3939 compatible = "qcom,sm8450-lpass-lpi-pinctrl"; 3940 reg = <0 0x03440000 0x0 0x20000>, 3941 <0 0x034d0000 0x0 0x10000>; 3942 gpio-controller; 3943 #gpio-cells = <2>; 3944 gpio-ranges = <&lpass_tlmm 0 0 23>; 3945 3946 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3947 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3948 clock-names = "core", "audio"; 3949 3950 tx_swr_active: tx-swr-active-state { 3951 clk-pins { 3952 pins = "gpio0"; 3953 function = "swr_tx_clk"; 3954 drive-strength = <2>; 3955 slew-rate = <1>; 3956 bias-disable; 3957 }; 3958 3959 data-pins { 3960 pins = "gpio1", "gpio2", "gpio14"; 3961 function = "swr_tx_data"; 3962 drive-strength = <2>; 3963 slew-rate = <1>; 3964 bias-bus-hold; 3965 }; 3966 }; 3967 3968 rx_swr_active: rx-swr-active-state { 3969 clk-pins { 3970 pins = "gpio3"; 3971 function = "swr_rx_clk"; 3972 drive-strength = <2>; 3973 slew-rate = <1>; 3974 bias-disable; 3975 }; 3976 3977 data-pins { 3978 pins = "gpio4", "gpio5"; 3979 function = "swr_rx_data"; 3980 drive-strength = <2>; 3981 slew-rate = <1>; 3982 bias-bus-hold; 3983 }; 3984 }; 3985 3986 dmic01_default: dmic01-default-state { 3987 clk-pins { 3988 pins = "gpio6"; 3989 function = "dmic1_clk"; 3990 drive-strength = <8>; 3991 output-high; 3992 }; 3993 3994 data-pins { 3995 pins = "gpio7"; 3996 function = "dmic1_data"; 3997 drive-strength = <8>; 3998 }; 3999 }; 4000 4001 dmic23_default: dmic23-default-state { 4002 clk-pins { 4003 pins = "gpio8"; 4004 function = "dmic2_clk"; 4005 drive-strength = <8>; 4006 output-high; 4007 }; 4008 4009 data-pins { 4010 pins = "gpio9"; 4011 function = "dmic2_data"; 4012 drive-strength = <8>; 4013 }; 4014 }; 4015 4016 wsa_swr_active: wsa-swr-active-state { 4017 clk-pins { 4018 pins = "gpio10"; 4019 function = "wsa_swr_clk"; 4020 drive-strength = <2>; 4021 slew-rate = <1>; 4022 bias-disable; 4023 }; 4024 4025 data-pins { 4026 pins = "gpio11"; 4027 function = "wsa_swr_data"; 4028 drive-strength = <2>; 4029 slew-rate = <1>; 4030 bias-bus-hold; 4031 }; 4032 }; 4033 4034 wsa2_swr_active: wsa2-swr-active-state { 4035 clk-pins { 4036 pins = "gpio15"; 4037 function = "wsa2_swr_clk"; 4038 drive-strength = <2>; 4039 slew-rate = <1>; 4040 bias-disable; 4041 }; 4042 4043 data-pins { 4044 pins = "gpio16"; 4045 function = "wsa2_swr_data"; 4046 drive-strength = <2>; 4047 slew-rate = <1>; 4048 bias-bus-hold; 4049 }; 4050 }; 4051 }; 4052 4053 sram@146aa000 { 4054 compatible = "qcom,sm8450-imem", "syscon", "simple-mfd"; 4055 reg = <0 0x146aa000 0 0x1000>; 4056 ranges = <0 0 0x146aa000 0x1000>; 4057 4058 #address-cells = <1>; 4059 #size-cells = <1>; 4060 4061 pil-reloc@94c { 4062 compatible = "qcom,pil-reloc-info"; 4063 reg = <0x94c 0xc8>; 4064 }; 4065 }; 4066 4067 apps_smmu: iommu@15000000 { 4068 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; 4069 reg = <0 0x15000000 0 0x100000>; 4070 #iommu-cells = <2>; 4071 #global-interrupts = <1>; 4072 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4073 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4074 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4075 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4076 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4077 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4078 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4079 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4080 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4081 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4082 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4083 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4084 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4085 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4086 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4087 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4088 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4089 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4090 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4091 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4092 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4093 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4094 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4095 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4096 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4097 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4098 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4099 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4100 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4101 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4102 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4103 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4104 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4105 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4106 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4107 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4108 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4109 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4110 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4111 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4112 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4113 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4114 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4115 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4116 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4117 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4118 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4119 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4120 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4121 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4122 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4123 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4124 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4125 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4126 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4127 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4128 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4129 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4130 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4131 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4132 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4133 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4134 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4135 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4136 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4137 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4138 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4139 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4140 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4141 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4142 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4143 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4144 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4145 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4146 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4147 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4148 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4149 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4150 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4151 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4152 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 4153 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4154 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4155 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 4156 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4157 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 4158 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4159 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4160 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 4161 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 4162 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 4163 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 4164 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 4165 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 4166 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 4167 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 4168 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 4169 }; 4170 4171 intc: interrupt-controller@17100000 { 4172 compatible = "arm,gic-v3"; 4173 #interrupt-cells = <3>; 4174 interrupt-controller; 4175 #redistributor-regions = <1>; 4176 redistributor-stride = <0x0 0x40000>; 4177 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ 4178 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ 4179 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4180 #address-cells = <2>; 4181 #size-cells = <2>; 4182 ranges; 4183 4184 gic_its: msi-controller@17140000 { 4185 compatible = "arm,gic-v3-its"; 4186 reg = <0x0 0x17140000 0x0 0x20000>; 4187 msi-controller; 4188 #msi-cells = <1>; 4189 }; 4190 }; 4191 4192 timer@17420000 { 4193 compatible = "arm,armv7-timer-mem"; 4194 #address-cells = <1>; 4195 #size-cells = <1>; 4196 ranges = <0 0 0 0x20000000>; 4197 reg = <0x0 0x17420000 0x0 0x1000>; 4198 clock-frequency = <19200000>; 4199 4200 frame@17421000 { 4201 frame-number = <0>; 4202 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4203 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4204 reg = <0x17421000 0x1000>, 4205 <0x17422000 0x1000>; 4206 }; 4207 4208 frame@17423000 { 4209 frame-number = <1>; 4210 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4211 reg = <0x17423000 0x1000>; 4212 status = "disabled"; 4213 }; 4214 4215 frame@17425000 { 4216 frame-number = <2>; 4217 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4218 reg = <0x17425000 0x1000>; 4219 status = "disabled"; 4220 }; 4221 4222 frame@17427000 { 4223 frame-number = <3>; 4224 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4225 reg = <0x17427000 0x1000>; 4226 status = "disabled"; 4227 }; 4228 4229 frame@17429000 { 4230 frame-number = <4>; 4231 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4232 reg = <0x17429000 0x1000>; 4233 status = "disabled"; 4234 }; 4235 4236 frame@1742b000 { 4237 frame-number = <5>; 4238 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4239 reg = <0x1742b000 0x1000>; 4240 status = "disabled"; 4241 }; 4242 4243 frame@1742d000 { 4244 frame-number = <6>; 4245 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4246 reg = <0x1742d000 0x1000>; 4247 status = "disabled"; 4248 }; 4249 }; 4250 4251 apps_rsc: rsc@17a00000 { 4252 label = "apps_rsc"; 4253 compatible = "qcom,rpmh-rsc"; 4254 reg = <0x0 0x17a00000 0x0 0x10000>, 4255 <0x0 0x17a10000 0x0 0x10000>, 4256 <0x0 0x17a20000 0x0 0x10000>, 4257 <0x0 0x17a30000 0x0 0x10000>; 4258 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 4259 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4260 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4261 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4262 qcom,tcs-offset = <0xd00>; 4263 qcom,drv-id = <2>; 4264 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 4265 <WAKE_TCS 2>, <CONTROL_TCS 0>; 4266 power-domains = <&CLUSTER_PD>; 4267 4268 apps_bcm_voter: bcm-voter { 4269 compatible = "qcom,bcm-voter"; 4270 }; 4271 4272 rpmhcc: clock-controller { 4273 compatible = "qcom,sm8450-rpmh-clk"; 4274 #clock-cells = <1>; 4275 clock-names = "xo"; 4276 clocks = <&xo_board>; 4277 }; 4278 4279 rpmhpd: power-controller { 4280 compatible = "qcom,sm8450-rpmhpd"; 4281 #power-domain-cells = <1>; 4282 operating-points-v2 = <&rpmhpd_opp_table>; 4283 4284 rpmhpd_opp_table: opp-table { 4285 compatible = "operating-points-v2"; 4286 4287 rpmhpd_opp_ret: opp1 { 4288 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4289 }; 4290 4291 rpmhpd_opp_min_svs: opp2 { 4292 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4293 }; 4294 4295 rpmhpd_opp_low_svs_d1: opp3 { 4296 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 4297 }; 4298 4299 rpmhpd_opp_low_svs: opp4 { 4300 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4301 }; 4302 4303 rpmhpd_opp_low_svs_l1: opp5 { 4304 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 4305 }; 4306 4307 rpmhpd_opp_svs: opp6 { 4308 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4309 }; 4310 4311 rpmhpd_opp_svs_l0: opp7 { 4312 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 4313 }; 4314 4315 rpmhpd_opp_svs_l1: opp8 { 4316 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4317 }; 4318 4319 rpmhpd_opp_svs_l2: opp9 { 4320 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 4321 }; 4322 4323 rpmhpd_opp_nom: opp10 { 4324 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4325 }; 4326 4327 rpmhpd_opp_nom_l1: opp11 { 4328 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4329 }; 4330 4331 rpmhpd_opp_nom_l2: opp12 { 4332 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4333 }; 4334 4335 rpmhpd_opp_turbo: opp13 { 4336 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4337 }; 4338 4339 rpmhpd_opp_turbo_l1: opp14 { 4340 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4341 }; 4342 }; 4343 }; 4344 }; 4345 4346 cpufreq_hw: cpufreq@17d91000 { 4347 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss"; 4348 reg = <0 0x17d91000 0 0x1000>, 4349 <0 0x17d92000 0 0x1000>, 4350 <0 0x17d93000 0 0x1000>; 4351 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 4352 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4353 clock-names = "xo", "alternate"; 4354 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 4355 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 4356 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 4357 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 4358 #freq-domain-cells = <1>; 4359 #clock-cells = <1>; 4360 }; 4361 4362 gem_noc: interconnect@19100000 { 4363 compatible = "qcom,sm8450-gem-noc"; 4364 reg = <0 0x19100000 0 0xbb800>; 4365 #interconnect-cells = <2>; 4366 qcom,bcm-voters = <&apps_bcm_voter>; 4367 }; 4368 4369 system-cache-controller@19200000 { 4370 compatible = "qcom,sm8450-llcc"; 4371 reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>, 4372 <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>, 4373 <0 0x19a00000 0 0x80000>; 4374 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 4375 "llcc3_base", "llcc_broadcast_base"; 4376 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 4377 }; 4378 4379 ufs_mem_hc: ufshc@1d84000 { 4380 compatible = "qcom,sm8450-ufshc", "qcom,ufshc", 4381 "jedec,ufs-2.0"; 4382 reg = <0 0x01d84000 0 0x3000>; 4383 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 4384 phys = <&ufs_mem_phy>; 4385 phy-names = "ufsphy"; 4386 lanes-per-direction = <2>; 4387 #reset-cells = <1>; 4388 resets = <&gcc GCC_UFS_PHY_BCR>; 4389 reset-names = "rst"; 4390 4391 power-domains = <&gcc UFS_PHY_GDSC>; 4392 4393 iommus = <&apps_smmu 0xe0 0x0>; 4394 dma-coherent; 4395 4396 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 4397 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 4398 interconnect-names = "ufs-ddr", "cpu-ufs"; 4399 clock-names = 4400 "core_clk", 4401 "bus_aggr_clk", 4402 "iface_clk", 4403 "core_clk_unipro", 4404 "ref_clk", 4405 "tx_lane0_sync_clk", 4406 "rx_lane0_sync_clk", 4407 "rx_lane1_sync_clk"; 4408 clocks = 4409 <&gcc GCC_UFS_PHY_AXI_CLK>, 4410 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 4411 <&gcc GCC_UFS_PHY_AHB_CLK>, 4412 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 4413 <&rpmhcc RPMH_CXO_CLK>, 4414 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 4415 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 4416 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 4417 freq-table-hz = 4418 <75000000 300000000>, 4419 <0 0>, 4420 <0 0>, 4421 <75000000 300000000>, 4422 <75000000 300000000>, 4423 <0 0>, 4424 <0 0>, 4425 <0 0>; 4426 qcom,ice = <&ice>; 4427 4428 status = "disabled"; 4429 }; 4430 4431 ufs_mem_phy: phy@1d87000 { 4432 compatible = "qcom,sm8450-qmp-ufs-phy"; 4433 reg = <0 0x01d87000 0 0x1000>; 4434 4435 clock-names = "ref", "ref_aux", "qref"; 4436 clocks = <&rpmhcc RPMH_CXO_CLK>, 4437 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 4438 <&gcc GCC_UFS_0_CLKREF_EN>; 4439 4440 resets = <&ufs_mem_hc 0>; 4441 reset-names = "ufsphy"; 4442 4443 #clock-cells = <1>; 4444 #phy-cells = <0>; 4445 4446 status = "disabled"; 4447 }; 4448 4449 ice: crypto@1d88000 { 4450 compatible = "qcom,sm8450-inline-crypto-engine", 4451 "qcom,inline-crypto-engine"; 4452 reg = <0 0x01d88000 0 0x8000>; 4453 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 4454 }; 4455 4456 cryptobam: dma-controller@1dc4000 { 4457 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 4458 reg = <0 0x01dc4000 0 0x28000>; 4459 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 4460 #dma-cells = <1>; 4461 qcom,ee = <0>; 4462 qcom,controlled-remotely; 4463 iommus = <&apps_smmu 0x584 0x11>, 4464 <&apps_smmu 0x588 0x0>, 4465 <&apps_smmu 0x598 0x5>, 4466 <&apps_smmu 0x59a 0x0>, 4467 <&apps_smmu 0x59f 0x0>; 4468 }; 4469 4470 crypto: crypto@1dfa000 { 4471 compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce"; 4472 reg = <0 0x01dfa000 0 0x6000>; 4473 dmas = <&cryptobam 4>, <&cryptobam 5>; 4474 dma-names = "rx", "tx"; 4475 iommus = <&apps_smmu 0x584 0x11>, 4476 <&apps_smmu 0x588 0x0>, 4477 <&apps_smmu 0x598 0x5>, 4478 <&apps_smmu 0x59a 0x0>, 4479 <&apps_smmu 0x59f 0x0>; 4480 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 4481 interconnect-names = "memory"; 4482 }; 4483 4484 sdhc_2: mmc@8804000 { 4485 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5"; 4486 reg = <0 0x08804000 0 0x1000>; 4487 4488 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 4489 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 4490 interrupt-names = "hc_irq", "pwr_irq"; 4491 4492 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 4493 <&gcc GCC_SDCC2_APPS_CLK>, 4494 <&rpmhcc RPMH_CXO_CLK>; 4495 clock-names = "iface", "core", "xo"; 4496 resets = <&gcc GCC_SDCC2_BCR>; 4497 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 4498 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 4499 interconnect-names = "sdhc-ddr","cpu-sdhc"; 4500 iommus = <&apps_smmu 0x4a0 0x0>; 4501 power-domains = <&rpmhpd RPMHPD_CX>; 4502 operating-points-v2 = <&sdhc2_opp_table>; 4503 bus-width = <4>; 4504 dma-coherent; 4505 4506 /* Forbid SDR104/SDR50 - broken hw! */ 4507 sdhci-caps-mask = <0x3 0x0>; 4508 4509 status = "disabled"; 4510 4511 sdhc2_opp_table: opp-table { 4512 compatible = "operating-points-v2"; 4513 4514 opp-100000000 { 4515 opp-hz = /bits/ 64 <100000000>; 4516 required-opps = <&rpmhpd_opp_low_svs>; 4517 }; 4518 4519 opp-202000000 { 4520 opp-hz = /bits/ 64 <202000000>; 4521 required-opps = <&rpmhpd_opp_svs_l1>; 4522 }; 4523 }; 4524 }; 4525 4526 usb_1: usb@a6f8800 { 4527 compatible = "qcom,sm8450-dwc3", "qcom,dwc3"; 4528 reg = <0 0x0a6f8800 0 0x400>; 4529 status = "disabled"; 4530 #address-cells = <2>; 4531 #size-cells = <2>; 4532 ranges; 4533 4534 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4535 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4536 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4537 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4538 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4539 <&gcc GCC_USB3_0_CLKREF_EN>; 4540 clock-names = "cfg_noc", 4541 "core", 4542 "iface", 4543 "sleep", 4544 "mock_utmi", 4545 "xo"; 4546 4547 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4548 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4549 assigned-clock-rates = <19200000>, <200000000>; 4550 4551 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4552 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4553 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4554 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4555 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 4556 interrupt-names = "pwr_event", 4557 "hs_phy_irq", 4558 "dp_hs_phy_irq", 4559 "dm_hs_phy_irq", 4560 "ss_phy_irq"; 4561 4562 power-domains = <&gcc USB30_PRIM_GDSC>; 4563 4564 resets = <&gcc GCC_USB30_PRIM_BCR>; 4565 4566 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 4567 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 4568 interconnect-names = "usb-ddr", "apps-usb"; 4569 4570 usb_1_dwc3: usb@a600000 { 4571 compatible = "snps,dwc3"; 4572 reg = <0 0x0a600000 0 0xcd00>; 4573 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4574 iommus = <&apps_smmu 0x0 0x0>; 4575 snps,dis_u2_susphy_quirk; 4576 snps,dis_enblslpm_quirk; 4577 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4578 phy-names = "usb2-phy", "usb3-phy"; 4579 4580 ports { 4581 #address-cells = <1>; 4582 #size-cells = <0>; 4583 4584 port@0 { 4585 reg = <0>; 4586 4587 usb_1_dwc3_hs: endpoint { 4588 }; 4589 }; 4590 4591 port@1 { 4592 reg = <1>; 4593 4594 usb_1_dwc3_ss: endpoint { 4595 }; 4596 }; 4597 }; 4598 }; 4599 }; 4600 4601 nsp_noc: interconnect@320c0000 { 4602 compatible = "qcom,sm8450-nsp-noc"; 4603 reg = <0 0x320c0000 0 0x10000>; 4604 #interconnect-cells = <2>; 4605 qcom,bcm-voters = <&apps_bcm_voter>; 4606 }; 4607 4608 lpass_ag_noc: interconnect@3c40000 { 4609 compatible = "qcom,sm8450-lpass-ag-noc"; 4610 reg = <0 0x03c40000 0 0x17200>; 4611 #interconnect-cells = <2>; 4612 qcom,bcm-voters = <&apps_bcm_voter>; 4613 }; 4614 }; 4615 4616 sound: sound { 4617 }; 4618 4619 thermal-zones { 4620 aoss0-thermal { 4621 polling-delay-passive = <0>; 4622 polling-delay = <0>; 4623 thermal-sensors = <&tsens0 0>; 4624 4625 trips { 4626 thermal-engine-config { 4627 temperature = <125000>; 4628 hysteresis = <1000>; 4629 type = "passive"; 4630 }; 4631 4632 reset-mon-cfg { 4633 temperature = <115000>; 4634 hysteresis = <5000>; 4635 type = "passive"; 4636 }; 4637 }; 4638 }; 4639 4640 cpuss0-thermal { 4641 polling-delay-passive = <0>; 4642 polling-delay = <0>; 4643 thermal-sensors = <&tsens0 1>; 4644 4645 trips { 4646 thermal-engine-config { 4647 temperature = <125000>; 4648 hysteresis = <1000>; 4649 type = "passive"; 4650 }; 4651 4652 reset-mon-cfg { 4653 temperature = <115000>; 4654 hysteresis = <5000>; 4655 type = "passive"; 4656 }; 4657 }; 4658 }; 4659 4660 cpuss1-thermal { 4661 polling-delay-passive = <0>; 4662 polling-delay = <0>; 4663 thermal-sensors = <&tsens0 2>; 4664 4665 trips { 4666 thermal-engine-config { 4667 temperature = <125000>; 4668 hysteresis = <1000>; 4669 type = "passive"; 4670 }; 4671 4672 reset-mon-cfg { 4673 temperature = <115000>; 4674 hysteresis = <5000>; 4675 type = "passive"; 4676 }; 4677 }; 4678 }; 4679 4680 cpuss3-thermal { 4681 polling-delay-passive = <0>; 4682 polling-delay = <0>; 4683 thermal-sensors = <&tsens0 3>; 4684 4685 trips { 4686 thermal-engine-config { 4687 temperature = <125000>; 4688 hysteresis = <1000>; 4689 type = "passive"; 4690 }; 4691 4692 reset-mon-cfg { 4693 temperature = <115000>; 4694 hysteresis = <5000>; 4695 type = "passive"; 4696 }; 4697 }; 4698 }; 4699 4700 cpuss4-thermal { 4701 polling-delay-passive = <0>; 4702 polling-delay = <0>; 4703 thermal-sensors = <&tsens0 4>; 4704 4705 trips { 4706 thermal-engine-config { 4707 temperature = <125000>; 4708 hysteresis = <1000>; 4709 type = "passive"; 4710 }; 4711 4712 reset-mon-cfg { 4713 temperature = <115000>; 4714 hysteresis = <5000>; 4715 type = "passive"; 4716 }; 4717 }; 4718 }; 4719 4720 cpu4-top-thermal { 4721 polling-delay-passive = <0>; 4722 polling-delay = <0>; 4723 thermal-sensors = <&tsens0 5>; 4724 4725 trips { 4726 cpu4_top_alert0: trip-point0 { 4727 temperature = <90000>; 4728 hysteresis = <2000>; 4729 type = "passive"; 4730 }; 4731 4732 cpu4_top_alert1: trip-point1 { 4733 temperature = <95000>; 4734 hysteresis = <2000>; 4735 type = "passive"; 4736 }; 4737 4738 cpu4_top_crit: cpu-crit { 4739 temperature = <110000>; 4740 hysteresis = <1000>; 4741 type = "critical"; 4742 }; 4743 }; 4744 }; 4745 4746 cpu4-bottom-thermal { 4747 polling-delay-passive = <0>; 4748 polling-delay = <0>; 4749 thermal-sensors = <&tsens0 6>; 4750 4751 trips { 4752 cpu4_bottom_alert0: trip-point0 { 4753 temperature = <90000>; 4754 hysteresis = <2000>; 4755 type = "passive"; 4756 }; 4757 4758 cpu4_bottom_alert1: trip-point1 { 4759 temperature = <95000>; 4760 hysteresis = <2000>; 4761 type = "passive"; 4762 }; 4763 4764 cpu4_bottom_crit: cpu-crit { 4765 temperature = <110000>; 4766 hysteresis = <1000>; 4767 type = "critical"; 4768 }; 4769 }; 4770 }; 4771 4772 cpu5-top-thermal { 4773 polling-delay-passive = <0>; 4774 polling-delay = <0>; 4775 thermal-sensors = <&tsens0 7>; 4776 4777 trips { 4778 cpu5_top_alert0: trip-point0 { 4779 temperature = <90000>; 4780 hysteresis = <2000>; 4781 type = "passive"; 4782 }; 4783 4784 cpu5_top_alert1: trip-point1 { 4785 temperature = <95000>; 4786 hysteresis = <2000>; 4787 type = "passive"; 4788 }; 4789 4790 cpu5_top_crit: cpu-crit { 4791 temperature = <110000>; 4792 hysteresis = <1000>; 4793 type = "critical"; 4794 }; 4795 }; 4796 }; 4797 4798 cpu5-bottom-thermal { 4799 polling-delay-passive = <0>; 4800 polling-delay = <0>; 4801 thermal-sensors = <&tsens0 8>; 4802 4803 trips { 4804 cpu5_bottom_alert0: trip-point0 { 4805 temperature = <90000>; 4806 hysteresis = <2000>; 4807 type = "passive"; 4808 }; 4809 4810 cpu5_bottom_alert1: trip-point1 { 4811 temperature = <95000>; 4812 hysteresis = <2000>; 4813 type = "passive"; 4814 }; 4815 4816 cpu5_bottom_crit: cpu-crit { 4817 temperature = <110000>; 4818 hysteresis = <1000>; 4819 type = "critical"; 4820 }; 4821 }; 4822 }; 4823 4824 cpu6-top-thermal { 4825 polling-delay-passive = <0>; 4826 polling-delay = <0>; 4827 thermal-sensors = <&tsens0 9>; 4828 4829 trips { 4830 cpu6_top_alert0: trip-point0 { 4831 temperature = <90000>; 4832 hysteresis = <2000>; 4833 type = "passive"; 4834 }; 4835 4836 cpu6_top_alert1: trip-point1 { 4837 temperature = <95000>; 4838 hysteresis = <2000>; 4839 type = "passive"; 4840 }; 4841 4842 cpu6_top_crit: cpu-crit { 4843 temperature = <110000>; 4844 hysteresis = <1000>; 4845 type = "critical"; 4846 }; 4847 }; 4848 }; 4849 4850 cpu6-bottom-thermal { 4851 polling-delay-passive = <0>; 4852 polling-delay = <0>; 4853 thermal-sensors = <&tsens0 10>; 4854 4855 trips { 4856 cpu6_bottom_alert0: trip-point0 { 4857 temperature = <90000>; 4858 hysteresis = <2000>; 4859 type = "passive"; 4860 }; 4861 4862 cpu6_bottom_alert1: trip-point1 { 4863 temperature = <95000>; 4864 hysteresis = <2000>; 4865 type = "passive"; 4866 }; 4867 4868 cpu6_bottom_crit: cpu-crit { 4869 temperature = <110000>; 4870 hysteresis = <1000>; 4871 type = "critical"; 4872 }; 4873 }; 4874 }; 4875 4876 cpu7-top-thermal { 4877 polling-delay-passive = <0>; 4878 polling-delay = <0>; 4879 thermal-sensors = <&tsens0 11>; 4880 4881 trips { 4882 cpu7_top_alert0: trip-point0 { 4883 temperature = <90000>; 4884 hysteresis = <2000>; 4885 type = "passive"; 4886 }; 4887 4888 cpu7_top_alert1: trip-point1 { 4889 temperature = <95000>; 4890 hysteresis = <2000>; 4891 type = "passive"; 4892 }; 4893 4894 cpu7_top_crit: cpu-crit { 4895 temperature = <110000>; 4896 hysteresis = <1000>; 4897 type = "critical"; 4898 }; 4899 }; 4900 }; 4901 4902 cpu7-middle-thermal { 4903 polling-delay-passive = <0>; 4904 polling-delay = <0>; 4905 thermal-sensors = <&tsens0 12>; 4906 4907 trips { 4908 cpu7_middle_alert0: trip-point0 { 4909 temperature = <90000>; 4910 hysteresis = <2000>; 4911 type = "passive"; 4912 }; 4913 4914 cpu7_middle_alert1: trip-point1 { 4915 temperature = <95000>; 4916 hysteresis = <2000>; 4917 type = "passive"; 4918 }; 4919 4920 cpu7_middle_crit: cpu-crit { 4921 temperature = <110000>; 4922 hysteresis = <1000>; 4923 type = "critical"; 4924 }; 4925 }; 4926 }; 4927 4928 cpu7-bottom-thermal { 4929 polling-delay-passive = <0>; 4930 polling-delay = <0>; 4931 thermal-sensors = <&tsens0 13>; 4932 4933 trips { 4934 cpu7_bottom_alert0: trip-point0 { 4935 temperature = <90000>; 4936 hysteresis = <2000>; 4937 type = "passive"; 4938 }; 4939 4940 cpu7_bottom_alert1: trip-point1 { 4941 temperature = <95000>; 4942 hysteresis = <2000>; 4943 type = "passive"; 4944 }; 4945 4946 cpu7_bottom_crit: cpu-crit { 4947 temperature = <110000>; 4948 hysteresis = <1000>; 4949 type = "critical"; 4950 }; 4951 }; 4952 }; 4953 4954 gpu-top-thermal { 4955 polling-delay-passive = <10>; 4956 polling-delay = <0>; 4957 thermal-sensors = <&tsens0 14>; 4958 4959 cooling-maps { 4960 map0 { 4961 trip = <&gpu_top_alert0>; 4962 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4963 }; 4964 }; 4965 4966 trips { 4967 thermal-engine-config { 4968 temperature = <125000>; 4969 hysteresis = <1000>; 4970 type = "passive"; 4971 }; 4972 4973 thermal-hal-config { 4974 temperature = <125000>; 4975 hysteresis = <1000>; 4976 type = "passive"; 4977 }; 4978 4979 reset-mon-cfg { 4980 temperature = <115000>; 4981 hysteresis = <5000>; 4982 type = "passive"; 4983 }; 4984 4985 gpu_top_alert0: trip-point0 { 4986 temperature = <95000>; 4987 hysteresis = <5000>; 4988 type = "passive"; 4989 }; 4990 }; 4991 }; 4992 4993 gpu-bottom-thermal { 4994 polling-delay-passive = <10>; 4995 polling-delay = <0>; 4996 thermal-sensors = <&tsens0 15>; 4997 4998 cooling-maps { 4999 map0 { 5000 trip = <&gpu_bottom_alert0>; 5001 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5002 }; 5003 }; 5004 5005 trips { 5006 thermal-engine-config { 5007 temperature = <125000>; 5008 hysteresis = <1000>; 5009 type = "passive"; 5010 }; 5011 5012 thermal-hal-config { 5013 temperature = <125000>; 5014 hysteresis = <1000>; 5015 type = "passive"; 5016 }; 5017 5018 reset-mon-cfg { 5019 temperature = <115000>; 5020 hysteresis = <5000>; 5021 type = "passive"; 5022 }; 5023 5024 gpu_bottom_alert0: trip-point0 { 5025 temperature = <95000>; 5026 hysteresis = <5000>; 5027 type = "passive"; 5028 }; 5029 }; 5030 }; 5031 5032 aoss1-thermal { 5033 polling-delay-passive = <0>; 5034 polling-delay = <0>; 5035 thermal-sensors = <&tsens1 0>; 5036 5037 trips { 5038 thermal-engine-config { 5039 temperature = <125000>; 5040 hysteresis = <1000>; 5041 type = "passive"; 5042 }; 5043 5044 reset-mon-cfg { 5045 temperature = <115000>; 5046 hysteresis = <5000>; 5047 type = "passive"; 5048 }; 5049 }; 5050 }; 5051 5052 cpu0-thermal { 5053 polling-delay-passive = <0>; 5054 polling-delay = <0>; 5055 thermal-sensors = <&tsens1 1>; 5056 5057 trips { 5058 cpu0_alert0: trip-point0 { 5059 temperature = <90000>; 5060 hysteresis = <2000>; 5061 type = "passive"; 5062 }; 5063 5064 cpu0_alert1: trip-point1 { 5065 temperature = <95000>; 5066 hysteresis = <2000>; 5067 type = "passive"; 5068 }; 5069 5070 cpu0_crit: cpu-crit { 5071 temperature = <110000>; 5072 hysteresis = <1000>; 5073 type = "critical"; 5074 }; 5075 }; 5076 }; 5077 5078 cpu1-thermal { 5079 polling-delay-passive = <0>; 5080 polling-delay = <0>; 5081 thermal-sensors = <&tsens1 2>; 5082 5083 trips { 5084 cpu1_alert0: trip-point0 { 5085 temperature = <90000>; 5086 hysteresis = <2000>; 5087 type = "passive"; 5088 }; 5089 5090 cpu1_alert1: trip-point1 { 5091 temperature = <95000>; 5092 hysteresis = <2000>; 5093 type = "passive"; 5094 }; 5095 5096 cpu1_crit: cpu-crit { 5097 temperature = <110000>; 5098 hysteresis = <1000>; 5099 type = "critical"; 5100 }; 5101 }; 5102 }; 5103 5104 cpu2-thermal { 5105 polling-delay-passive = <0>; 5106 polling-delay = <0>; 5107 thermal-sensors = <&tsens1 3>; 5108 5109 trips { 5110 cpu2_alert0: trip-point0 { 5111 temperature = <90000>; 5112 hysteresis = <2000>; 5113 type = "passive"; 5114 }; 5115 5116 cpu2_alert1: trip-point1 { 5117 temperature = <95000>; 5118 hysteresis = <2000>; 5119 type = "passive"; 5120 }; 5121 5122 cpu2_crit: cpu-crit { 5123 temperature = <110000>; 5124 hysteresis = <1000>; 5125 type = "critical"; 5126 }; 5127 }; 5128 }; 5129 5130 cpu3-thermal { 5131 polling-delay-passive = <0>; 5132 polling-delay = <0>; 5133 thermal-sensors = <&tsens1 4>; 5134 5135 trips { 5136 cpu3_alert0: trip-point0 { 5137 temperature = <90000>; 5138 hysteresis = <2000>; 5139 type = "passive"; 5140 }; 5141 5142 cpu3_alert1: trip-point1 { 5143 temperature = <95000>; 5144 hysteresis = <2000>; 5145 type = "passive"; 5146 }; 5147 5148 cpu3_crit: cpu-crit { 5149 temperature = <110000>; 5150 hysteresis = <1000>; 5151 type = "critical"; 5152 }; 5153 }; 5154 }; 5155 5156 cdsp0-thermal { 5157 polling-delay-passive = <10>; 5158 polling-delay = <0>; 5159 thermal-sensors = <&tsens1 5>; 5160 5161 trips { 5162 thermal-engine-config { 5163 temperature = <125000>; 5164 hysteresis = <1000>; 5165 type = "passive"; 5166 }; 5167 5168 thermal-hal-config { 5169 temperature = <125000>; 5170 hysteresis = <1000>; 5171 type = "passive"; 5172 }; 5173 5174 reset-mon-cfg { 5175 temperature = <115000>; 5176 hysteresis = <5000>; 5177 type = "passive"; 5178 }; 5179 5180 cdsp_0_config: junction-config { 5181 temperature = <95000>; 5182 hysteresis = <5000>; 5183 type = "passive"; 5184 }; 5185 }; 5186 }; 5187 5188 cdsp1-thermal { 5189 polling-delay-passive = <10>; 5190 polling-delay = <0>; 5191 thermal-sensors = <&tsens1 6>; 5192 5193 trips { 5194 thermal-engine-config { 5195 temperature = <125000>; 5196 hysteresis = <1000>; 5197 type = "passive"; 5198 }; 5199 5200 thermal-hal-config { 5201 temperature = <125000>; 5202 hysteresis = <1000>; 5203 type = "passive"; 5204 }; 5205 5206 reset-mon-cfg { 5207 temperature = <115000>; 5208 hysteresis = <5000>; 5209 type = "passive"; 5210 }; 5211 5212 cdsp_1_config: junction-config { 5213 temperature = <95000>; 5214 hysteresis = <5000>; 5215 type = "passive"; 5216 }; 5217 }; 5218 }; 5219 5220 cdsp2-thermal { 5221 polling-delay-passive = <10>; 5222 polling-delay = <0>; 5223 thermal-sensors = <&tsens1 7>; 5224 5225 trips { 5226 thermal-engine-config { 5227 temperature = <125000>; 5228 hysteresis = <1000>; 5229 type = "passive"; 5230 }; 5231 5232 thermal-hal-config { 5233 temperature = <125000>; 5234 hysteresis = <1000>; 5235 type = "passive"; 5236 }; 5237 5238 reset-mon-cfg { 5239 temperature = <115000>; 5240 hysteresis = <5000>; 5241 type = "passive"; 5242 }; 5243 5244 cdsp_2_config: junction-config { 5245 temperature = <95000>; 5246 hysteresis = <5000>; 5247 type = "passive"; 5248 }; 5249 }; 5250 }; 5251 5252 video-thermal { 5253 polling-delay-passive = <0>; 5254 polling-delay = <0>; 5255 thermal-sensors = <&tsens1 8>; 5256 5257 trips { 5258 thermal-engine-config { 5259 temperature = <125000>; 5260 hysteresis = <1000>; 5261 type = "passive"; 5262 }; 5263 5264 reset-mon-cfg { 5265 temperature = <115000>; 5266 hysteresis = <5000>; 5267 type = "passive"; 5268 }; 5269 }; 5270 }; 5271 5272 mem-thermal { 5273 polling-delay-passive = <10>; 5274 polling-delay = <0>; 5275 thermal-sensors = <&tsens1 9>; 5276 5277 trips { 5278 thermal-engine-config { 5279 temperature = <125000>; 5280 hysteresis = <1000>; 5281 type = "passive"; 5282 }; 5283 5284 ddr_config0: ddr0-config { 5285 temperature = <90000>; 5286 hysteresis = <5000>; 5287 type = "passive"; 5288 }; 5289 5290 reset-mon-cfg { 5291 temperature = <115000>; 5292 hysteresis = <5000>; 5293 type = "passive"; 5294 }; 5295 }; 5296 }; 5297 5298 modem0-thermal { 5299 polling-delay-passive = <0>; 5300 polling-delay = <0>; 5301 thermal-sensors = <&tsens1 10>; 5302 5303 trips { 5304 thermal-engine-config { 5305 temperature = <125000>; 5306 hysteresis = <1000>; 5307 type = "passive"; 5308 }; 5309 5310 mdmss0_config0: mdmss0-config0 { 5311 temperature = <102000>; 5312 hysteresis = <3000>; 5313 type = "passive"; 5314 }; 5315 5316 mdmss0_config1: mdmss0-config1 { 5317 temperature = <105000>; 5318 hysteresis = <3000>; 5319 type = "passive"; 5320 }; 5321 5322 reset-mon-cfg { 5323 temperature = <115000>; 5324 hysteresis = <5000>; 5325 type = "passive"; 5326 }; 5327 }; 5328 }; 5329 5330 modem1-thermal { 5331 polling-delay-passive = <0>; 5332 polling-delay = <0>; 5333 thermal-sensors = <&tsens1 11>; 5334 5335 trips { 5336 thermal-engine-config { 5337 temperature = <125000>; 5338 hysteresis = <1000>; 5339 type = "passive"; 5340 }; 5341 5342 mdmss1_config0: mdmss1-config0 { 5343 temperature = <102000>; 5344 hysteresis = <3000>; 5345 type = "passive"; 5346 }; 5347 5348 mdmss1_config1: mdmss1-config1 { 5349 temperature = <105000>; 5350 hysteresis = <3000>; 5351 type = "passive"; 5352 }; 5353 5354 reset-mon-cfg { 5355 temperature = <115000>; 5356 hysteresis = <5000>; 5357 type = "passive"; 5358 }; 5359 }; 5360 }; 5361 5362 modem2-thermal { 5363 polling-delay-passive = <0>; 5364 polling-delay = <0>; 5365 thermal-sensors = <&tsens1 12>; 5366 5367 trips { 5368 thermal-engine-config { 5369 temperature = <125000>; 5370 hysteresis = <1000>; 5371 type = "passive"; 5372 }; 5373 5374 mdmss2_config0: mdmss2-config0 { 5375 temperature = <102000>; 5376 hysteresis = <3000>; 5377 type = "passive"; 5378 }; 5379 5380 mdmss2_config1: mdmss2-config1 { 5381 temperature = <105000>; 5382 hysteresis = <3000>; 5383 type = "passive"; 5384 }; 5385 5386 reset-mon-cfg { 5387 temperature = <115000>; 5388 hysteresis = <5000>; 5389 type = "passive"; 5390 }; 5391 }; 5392 }; 5393 5394 modem3-thermal { 5395 polling-delay-passive = <0>; 5396 polling-delay = <0>; 5397 thermal-sensors = <&tsens1 13>; 5398 5399 trips { 5400 thermal-engine-config { 5401 temperature = <125000>; 5402 hysteresis = <1000>; 5403 type = "passive"; 5404 }; 5405 5406 mdmss3_config0: mdmss3-config0 { 5407 temperature = <102000>; 5408 hysteresis = <3000>; 5409 type = "passive"; 5410 }; 5411 5412 mdmss3_config1: mdmss3-config1 { 5413 temperature = <105000>; 5414 hysteresis = <3000>; 5415 type = "passive"; 5416 }; 5417 5418 reset-mon-cfg { 5419 temperature = <115000>; 5420 hysteresis = <5000>; 5421 type = "passive"; 5422 }; 5423 }; 5424 }; 5425 5426 camera0-thermal { 5427 polling-delay-passive = <0>; 5428 polling-delay = <0>; 5429 thermal-sensors = <&tsens1 14>; 5430 5431 trips { 5432 thermal-engine-config { 5433 temperature = <125000>; 5434 hysteresis = <1000>; 5435 type = "passive"; 5436 }; 5437 5438 reset-mon-cfg { 5439 temperature = <115000>; 5440 hysteresis = <5000>; 5441 type = "passive"; 5442 }; 5443 }; 5444 }; 5445 5446 camera1-thermal { 5447 polling-delay-passive = <0>; 5448 polling-delay = <0>; 5449 thermal-sensors = <&tsens1 15>; 5450 5451 trips { 5452 thermal-engine-config { 5453 temperature = <125000>; 5454 hysteresis = <1000>; 5455 type = "passive"; 5456 }; 5457 5458 reset-mon-cfg { 5459 temperature = <115000>; 5460 hysteresis = <5000>; 5461 type = "passive"; 5462 }; 5463 }; 5464 }; 5465 }; 5466 5467 timer { 5468 compatible = "arm,armv8-timer"; 5469 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5470 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5471 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5472 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5473 clock-frequency = <19200000>; 5474 }; 5475}; 5476