1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Linaro Limited 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 8#include <dt-bindings/clock/qcom,gcc-sm8450.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/clock/qcom,sm8450-camcc.h> 11#include <dt-bindings/clock/qcom,sm8450-dispcc.h> 12#include <dt-bindings/clock/qcom,sm8450-gpucc.h> 13#include <dt-bindings/clock/qcom,sm8450-videocc.h> 14#include <dt-bindings/dma/qcom-gpi.h> 15#include <dt-bindings/firmware/qcom,scm.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/mailbox/qcom-ipcc.h> 18#include <dt-bindings/phy/phy-qcom-qmp.h> 19#include <dt-bindings/power/qcom,rpmhpd.h> 20#include <dt-bindings/power/qcom-rpmpd.h> 21#include <dt-bindings/interconnect/qcom,icc.h> 22#include <dt-bindings/interconnect/qcom,sm8450.h> 23#include <dt-bindings/reset/qcom,sm8450-gpucc.h> 24#include <dt-bindings/soc/qcom,gpr.h> 25#include <dt-bindings/soc/qcom,rpmh-rsc.h> 26#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 27#include <dt-bindings/thermal/thermal.h> 28 29/ { 30 interrupt-parent = <&intc>; 31 32 #address-cells = <2>; 33 #size-cells = <2>; 34 35 chosen { }; 36 37 clocks { 38 xo_board: xo-board { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <76800000>; 42 }; 43 44 sleep_clk: sleep-clk { 45 compatible = "fixed-clock"; 46 #clock-cells = <0>; 47 clock-frequency = <32764>; 48 }; 49 }; 50 51 cpus { 52 #address-cells = <2>; 53 #size-cells = <0>; 54 55 cpu0: cpu@0 { 56 device_type = "cpu"; 57 compatible = "qcom,kryo780"; 58 reg = <0x0 0x0>; 59 enable-method = "psci"; 60 next-level-cache = <&l2_0>; 61 power-domains = <&cpu_pd0>; 62 power-domain-names = "psci"; 63 qcom,freq-domain = <&cpufreq_hw 0>; 64 #cooling-cells = <2>; 65 clocks = <&cpufreq_hw 0>; 66 l2_0: l2-cache { 67 compatible = "cache"; 68 cache-level = <2>; 69 cache-unified; 70 next-level-cache = <&l3_0>; 71 l3_0: l3-cache { 72 compatible = "cache"; 73 cache-level = <3>; 74 cache-unified; 75 }; 76 }; 77 }; 78 79 cpu1: cpu@100 { 80 device_type = "cpu"; 81 compatible = "qcom,kryo780"; 82 reg = <0x0 0x100>; 83 enable-method = "psci"; 84 next-level-cache = <&l2_100>; 85 power-domains = <&cpu_pd1>; 86 power-domain-names = "psci"; 87 qcom,freq-domain = <&cpufreq_hw 0>; 88 #cooling-cells = <2>; 89 clocks = <&cpufreq_hw 0>; 90 l2_100: l2-cache { 91 compatible = "cache"; 92 cache-level = <2>; 93 cache-unified; 94 next-level-cache = <&l3_0>; 95 }; 96 }; 97 98 cpu2: cpu@200 { 99 device_type = "cpu"; 100 compatible = "qcom,kryo780"; 101 reg = <0x0 0x200>; 102 enable-method = "psci"; 103 next-level-cache = <&l2_200>; 104 power-domains = <&cpu_pd2>; 105 power-domain-names = "psci"; 106 qcom,freq-domain = <&cpufreq_hw 0>; 107 #cooling-cells = <2>; 108 clocks = <&cpufreq_hw 0>; 109 l2_200: l2-cache { 110 compatible = "cache"; 111 cache-level = <2>; 112 cache-unified; 113 next-level-cache = <&l3_0>; 114 }; 115 }; 116 117 cpu3: cpu@300 { 118 device_type = "cpu"; 119 compatible = "qcom,kryo780"; 120 reg = <0x0 0x300>; 121 enable-method = "psci"; 122 next-level-cache = <&l2_300>; 123 power-domains = <&cpu_pd3>; 124 power-domain-names = "psci"; 125 qcom,freq-domain = <&cpufreq_hw 0>; 126 #cooling-cells = <2>; 127 clocks = <&cpufreq_hw 0>; 128 l2_300: l2-cache { 129 compatible = "cache"; 130 cache-level = <2>; 131 cache-unified; 132 next-level-cache = <&l3_0>; 133 }; 134 }; 135 136 cpu4: cpu@400 { 137 device_type = "cpu"; 138 compatible = "qcom,kryo780"; 139 reg = <0x0 0x400>; 140 enable-method = "psci"; 141 next-level-cache = <&l2_400>; 142 power-domains = <&cpu_pd4>; 143 power-domain-names = "psci"; 144 qcom,freq-domain = <&cpufreq_hw 1>; 145 #cooling-cells = <2>; 146 clocks = <&cpufreq_hw 1>; 147 l2_400: l2-cache { 148 compatible = "cache"; 149 cache-level = <2>; 150 cache-unified; 151 next-level-cache = <&l3_0>; 152 }; 153 }; 154 155 cpu5: cpu@500 { 156 device_type = "cpu"; 157 compatible = "qcom,kryo780"; 158 reg = <0x0 0x500>; 159 enable-method = "psci"; 160 next-level-cache = <&l2_500>; 161 power-domains = <&cpu_pd5>; 162 power-domain-names = "psci"; 163 qcom,freq-domain = <&cpufreq_hw 1>; 164 #cooling-cells = <2>; 165 clocks = <&cpufreq_hw 1>; 166 l2_500: l2-cache { 167 compatible = "cache"; 168 cache-level = <2>; 169 cache-unified; 170 next-level-cache = <&l3_0>; 171 }; 172 }; 173 174 cpu6: cpu@600 { 175 device_type = "cpu"; 176 compatible = "qcom,kryo780"; 177 reg = <0x0 0x600>; 178 enable-method = "psci"; 179 next-level-cache = <&l2_600>; 180 power-domains = <&cpu_pd6>; 181 power-domain-names = "psci"; 182 qcom,freq-domain = <&cpufreq_hw 1>; 183 #cooling-cells = <2>; 184 clocks = <&cpufreq_hw 1>; 185 l2_600: l2-cache { 186 compatible = "cache"; 187 cache-level = <2>; 188 cache-unified; 189 next-level-cache = <&l3_0>; 190 }; 191 }; 192 193 cpu7: cpu@700 { 194 device_type = "cpu"; 195 compatible = "qcom,kryo780"; 196 reg = <0x0 0x700>; 197 enable-method = "psci"; 198 next-level-cache = <&l2_700>; 199 power-domains = <&cpu_pd7>; 200 power-domain-names = "psci"; 201 qcom,freq-domain = <&cpufreq_hw 2>; 202 #cooling-cells = <2>; 203 clocks = <&cpufreq_hw 2>; 204 l2_700: l2-cache { 205 compatible = "cache"; 206 cache-level = <2>; 207 cache-unified; 208 next-level-cache = <&l3_0>; 209 }; 210 }; 211 212 cpu-map { 213 cluster0 { 214 core0 { 215 cpu = <&cpu0>; 216 }; 217 218 core1 { 219 cpu = <&cpu1>; 220 }; 221 222 core2 { 223 cpu = <&cpu2>; 224 }; 225 226 core3 { 227 cpu = <&cpu3>; 228 }; 229 230 core4 { 231 cpu = <&cpu4>; 232 }; 233 234 core5 { 235 cpu = <&cpu5>; 236 }; 237 238 core6 { 239 cpu = <&cpu6>; 240 }; 241 242 core7 { 243 cpu = <&cpu7>; 244 }; 245 }; 246 }; 247 248 idle-states { 249 entry-method = "psci"; 250 251 little_cpu_sleep_0: cpu-sleep-0-0 { 252 compatible = "arm,idle-state"; 253 idle-state-name = "silver-rail-power-collapse"; 254 arm,psci-suspend-param = <0x40000004>; 255 entry-latency-us = <800>; 256 exit-latency-us = <750>; 257 min-residency-us = <4090>; 258 local-timer-stop; 259 }; 260 261 big_cpu_sleep_0: cpu-sleep-1-0 { 262 compatible = "arm,idle-state"; 263 idle-state-name = "gold-rail-power-collapse"; 264 arm,psci-suspend-param = <0x40000004>; 265 entry-latency-us = <600>; 266 exit-latency-us = <1550>; 267 min-residency-us = <4791>; 268 local-timer-stop; 269 }; 270 }; 271 272 domain-idle-states { 273 cluster_sleep_0: cluster-sleep-0 { 274 compatible = "domain-idle-state"; 275 arm,psci-suspend-param = <0x41000044>; 276 entry-latency-us = <1050>; 277 exit-latency-us = <2500>; 278 min-residency-us = <5309>; 279 }; 280 281 cluster_sleep_1: cluster-sleep-1 { 282 compatible = "domain-idle-state"; 283 arm,psci-suspend-param = <0x4100c344>; 284 entry-latency-us = <2700>; 285 exit-latency-us = <3500>; 286 min-residency-us = <13959>; 287 }; 288 }; 289 }; 290 291 ete-0 { 292 compatible = "arm,embedded-trace-extension"; 293 cpu = <&cpu0>; 294 295 out-ports { 296 port { 297 ete0_out_funnel_ete: endpoint { 298 remote-endpoint = <&funnel_ete_in_ete0>; 299 }; 300 }; 301 }; 302 }; 303 304 ete-1 { 305 compatible = "arm,embedded-trace-extension"; 306 cpu = <&cpu1>; 307 308 out-ports { 309 port { 310 ete1_out_funnel_ete: endpoint { 311 remote-endpoint = <&funnel_ete_in_ete1>; 312 }; 313 }; 314 }; 315 }; 316 317 ete-2 { 318 compatible = "arm,embedded-trace-extension"; 319 cpu = <&cpu2>; 320 321 out-ports { 322 port { 323 ete2_out_funnel_ete: endpoint { 324 remote-endpoint = <&funnel_ete_in_ete2>; 325 }; 326 }; 327 }; 328 }; 329 330 ete-3 { 331 compatible = "arm,embedded-trace-extension"; 332 cpu = <&cpu3>; 333 334 out-ports { 335 port { 336 ete3_out_funnel_ete: endpoint { 337 remote-endpoint = <&funnel_ete_in_ete3>; 338 }; 339 }; 340 }; 341 }; 342 343 ete-4 { 344 compatible = "arm,embedded-trace-extension"; 345 cpu = <&cpu4>; 346 347 out-ports { 348 port { 349 ete4_out_funnel_ete: endpoint { 350 remote-endpoint = <&funnel_ete_in_ete4>; 351 }; 352 }; 353 }; 354 }; 355 356 ete-5 { 357 compatible = "arm,embedded-trace-extension"; 358 cpu = <&cpu5>; 359 360 out-ports { 361 port { 362 ete5_out_funnel_ete: endpoint { 363 remote-endpoint = <&funnel_ete_in_ete5>; 364 }; 365 }; 366 }; 367 }; 368 369 ete-6 { 370 compatible = "arm,embedded-trace-extension"; 371 cpu = <&cpu6>; 372 373 out-ports { 374 port { 375 ete6_out_funnel_ete: endpoint { 376 remote-endpoint = <&funnel_ete_in_ete6>; 377 }; 378 }; 379 }; 380 }; 381 382 ete-7 { 383 compatible = "arm,embedded-trace-extension"; 384 cpu = <&cpu7>; 385 386 out-ports { 387 port { 388 ete7_out_funnel_ete: endpoint { 389 remote-endpoint = <&funnel_ete_in_ete7>; 390 }; 391 }; 392 }; 393 }; 394 395 funnel-ete { 396 compatible = "arm,coresight-static-funnel"; 397 398 out-ports { 399 port { 400 funnel_ete_out_funnel_apss: endpoint { 401 remote-endpoint = 402 <&funnel_apss_in_funnel_ete>; 403 }; 404 }; 405 }; 406 407 in-ports { 408 #address-cells = <1>; 409 #size-cells = <0>; 410 411 port@0 { 412 reg = <0>; 413 funnel_ete_in_ete0: endpoint { 414 remote-endpoint = 415 <&ete0_out_funnel_ete>; 416 }; 417 }; 418 419 port@1 { 420 reg = <1>; 421 funnel_ete_in_ete1: endpoint { 422 remote-endpoint = 423 <&ete1_out_funnel_ete>; 424 }; 425 }; 426 427 port@2 { 428 reg = <2>; 429 funnel_ete_in_ete2: endpoint { 430 remote-endpoint = 431 <&ete2_out_funnel_ete>; 432 }; 433 }; 434 435 port@3 { 436 reg = <3>; 437 funnel_ete_in_ete3: endpoint { 438 remote-endpoint = 439 <&ete3_out_funnel_ete>; 440 }; 441 }; 442 443 port@4 { 444 reg = <4>; 445 funnel_ete_in_ete4: endpoint { 446 remote-endpoint = 447 <&ete4_out_funnel_ete>; 448 }; 449 }; 450 451 port@5 { 452 reg = <5>; 453 funnel_ete_in_ete5: endpoint { 454 remote-endpoint = 455 <&ete5_out_funnel_ete>; 456 }; 457 }; 458 459 port@6 { 460 reg = <6>; 461 funnel_ete_in_ete6: endpoint { 462 remote-endpoint = 463 <&ete6_out_funnel_ete>; 464 }; 465 }; 466 467 port@7 { 468 reg = <7>; 469 funnel_ete_in_ete7: endpoint { 470 remote-endpoint = 471 <&ete7_out_funnel_ete>; 472 }; 473 }; 474 }; 475 }; 476 477 firmware { 478 scm: scm { 479 compatible = "qcom,scm-sm8450", "qcom,scm"; 480 qcom,dload-mode = <&tcsr 0x13000>; 481 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 482 #reset-cells = <1>; 483 }; 484 }; 485 486 clk_virt: interconnect-0 { 487 compatible = "qcom,sm8450-clk-virt"; 488 #interconnect-cells = <2>; 489 qcom,bcm-voters = <&apps_bcm_voter>; 490 }; 491 492 mc_virt: interconnect-1 { 493 compatible = "qcom,sm8450-mc-virt"; 494 #interconnect-cells = <2>; 495 qcom,bcm-voters = <&apps_bcm_voter>; 496 }; 497 498 memory@a0000000 { 499 device_type = "memory"; 500 /* We expect the bootloader to fill in the size */ 501 reg = <0x0 0xa0000000 0x0 0x0>; 502 }; 503 504 pmu { 505 compatible = "arm,armv8-pmuv3"; 506 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 507 }; 508 509 psci { 510 compatible = "arm,psci-1.0"; 511 method = "smc"; 512 513 cpu_pd0: power-domain-cpu0 { 514 #power-domain-cells = <0>; 515 power-domains = <&cluster_pd>; 516 domain-idle-states = <&little_cpu_sleep_0>; 517 }; 518 519 cpu_pd1: power-domain-cpu1 { 520 #power-domain-cells = <0>; 521 power-domains = <&cluster_pd>; 522 domain-idle-states = <&little_cpu_sleep_0>; 523 }; 524 525 cpu_pd2: power-domain-cpu2 { 526 #power-domain-cells = <0>; 527 power-domains = <&cluster_pd>; 528 domain-idle-states = <&little_cpu_sleep_0>; 529 }; 530 531 cpu_pd3: power-domain-cpu3 { 532 #power-domain-cells = <0>; 533 power-domains = <&cluster_pd>; 534 domain-idle-states = <&little_cpu_sleep_0>; 535 }; 536 537 cpu_pd4: power-domain-cpu4 { 538 #power-domain-cells = <0>; 539 power-domains = <&cluster_pd>; 540 domain-idle-states = <&big_cpu_sleep_0>; 541 }; 542 543 cpu_pd5: power-domain-cpu5 { 544 #power-domain-cells = <0>; 545 power-domains = <&cluster_pd>; 546 domain-idle-states = <&big_cpu_sleep_0>; 547 }; 548 549 cpu_pd6: power-domain-cpu6 { 550 #power-domain-cells = <0>; 551 power-domains = <&cluster_pd>; 552 domain-idle-states = <&big_cpu_sleep_0>; 553 }; 554 555 cpu_pd7: power-domain-cpu7 { 556 #power-domain-cells = <0>; 557 power-domains = <&cluster_pd>; 558 domain-idle-states = <&big_cpu_sleep_0>; 559 }; 560 561 cluster_pd: power-domain-cpu-cluster0 { 562 #power-domain-cells = <0>; 563 domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>; 564 }; 565 }; 566 567 qup_opp_table_100mhz: opp-table-qup { 568 compatible = "operating-points-v2"; 569 570 opp-50000000 { 571 opp-hz = /bits/ 64 <50000000>; 572 required-opps = <&rpmhpd_opp_min_svs>; 573 }; 574 575 opp-75000000 { 576 opp-hz = /bits/ 64 <75000000>; 577 required-opps = <&rpmhpd_opp_low_svs>; 578 }; 579 580 opp-100000000 { 581 opp-hz = /bits/ 64 <100000000>; 582 required-opps = <&rpmhpd_opp_svs>; 583 }; 584 }; 585 586 reserved_memory: reserved-memory { 587 #address-cells = <2>; 588 #size-cells = <2>; 589 ranges; 590 591 hyp_mem: memory@80000000 { 592 reg = <0x0 0x80000000 0x0 0x600000>; 593 no-map; 594 }; 595 596 xbl_dt_log_mem: memory@80600000 { 597 reg = <0x0 0x80600000 0x0 0x40000>; 598 no-map; 599 }; 600 601 xbl_ramdump_mem: memory@80640000 { 602 reg = <0x0 0x80640000 0x0 0x180000>; 603 no-map; 604 }; 605 606 xbl_sc_mem: memory@807c0000 { 607 reg = <0x0 0x807c0000 0x0 0x40000>; 608 no-map; 609 }; 610 611 aop_image_mem: memory@80800000 { 612 reg = <0x0 0x80800000 0x0 0x60000>; 613 no-map; 614 }; 615 616 aop_cmd_db_mem: memory@80860000 { 617 compatible = "qcom,cmd-db"; 618 reg = <0x0 0x80860000 0x0 0x20000>; 619 no-map; 620 }; 621 622 aop_config_mem: memory@80880000 { 623 reg = <0x0 0x80880000 0x0 0x20000>; 624 no-map; 625 }; 626 627 tme_crash_dump_mem: memory@808a0000 { 628 reg = <0x0 0x808a0000 0x0 0x40000>; 629 no-map; 630 }; 631 632 tme_log_mem: memory@808e0000 { 633 reg = <0x0 0x808e0000 0x0 0x4000>; 634 no-map; 635 }; 636 637 uefi_log_mem: memory@808e4000 { 638 reg = <0x0 0x808e4000 0x0 0x10000>; 639 no-map; 640 }; 641 642 /* secdata region can be reused by apps */ 643 smem: memory@80900000 { 644 compatible = "qcom,smem"; 645 reg = <0x0 0x80900000 0x0 0x200000>; 646 hwlocks = <&tcsr_mutex 3>; 647 no-map; 648 }; 649 650 cpucp_fw_mem: memory@80b00000 { 651 reg = <0x0 0x80b00000 0x0 0x100000>; 652 no-map; 653 }; 654 655 cdsp_secure_heap: memory@80c00000 { 656 reg = <0x0 0x80c00000 0x0 0x4600000>; 657 no-map; 658 }; 659 660 video_mem: memory@85700000 { 661 reg = <0x0 0x85700000 0x0 0x700000>; 662 no-map; 663 }; 664 665 adsp_mem: memory@85e00000 { 666 reg = <0x0 0x85e00000 0x0 0x2100000>; 667 no-map; 668 }; 669 670 slpi_mem: memory@88000000 { 671 reg = <0x0 0x88000000 0x0 0x1900000>; 672 no-map; 673 }; 674 675 cdsp_mem: memory@89900000 { 676 reg = <0x0 0x89900000 0x0 0x2000000>; 677 no-map; 678 }; 679 680 ipa_fw_mem: memory@8b900000 { 681 reg = <0x0 0x8b900000 0x0 0x10000>; 682 no-map; 683 }; 684 685 ipa_gsi_mem: memory@8b910000 { 686 reg = <0x0 0x8b910000 0x0 0xa000>; 687 no-map; 688 }; 689 690 gpu_micro_code_mem: memory@8b91a000 { 691 reg = <0x0 0x8b91a000 0x0 0x2000>; 692 no-map; 693 }; 694 695 spss_region_mem: memory@8ba00000 { 696 reg = <0x0 0x8ba00000 0x0 0x180000>; 697 no-map; 698 }; 699 700 /* First part of the "SPU secure shared memory" region */ 701 spu_tz_shared_mem: memory@8bb80000 { 702 reg = <0x0 0x8bb80000 0x0 0x60000>; 703 no-map; 704 }; 705 706 /* Second part of the "SPU secure shared memory" region */ 707 spu_modem_shared_mem: memory@8bbe0000 { 708 reg = <0x0 0x8bbe0000 0x0 0x20000>; 709 no-map; 710 }; 711 712 mpss_mem: memory@8bc00000 { 713 reg = <0x0 0x8bc00000 0x0 0x13200000>; 714 no-map; 715 }; 716 717 cvp_mem: memory@9ee00000 { 718 reg = <0x0 0x9ee00000 0x0 0x700000>; 719 no-map; 720 }; 721 722 camera_mem: memory@9f500000 { 723 reg = <0x0 0x9f500000 0x0 0x800000>; 724 no-map; 725 }; 726 727 rmtfs_mem: memory@9fd00000 { 728 compatible = "qcom,rmtfs-mem"; 729 reg = <0x0 0x9fd00000 0x0 0x280000>; 730 no-map; 731 732 qcom,client-id = <1>; 733 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 734 }; 735 736 xbl_sc_mem2: memory@a6e00000 { 737 reg = <0x0 0xa6e00000 0x0 0x40000>; 738 no-map; 739 }; 740 741 global_sync_mem: memory@a6f00000 { 742 reg = <0x0 0xa6f00000 0x0 0x100000>; 743 no-map; 744 }; 745 746 /* uefi region can be reused by APPS */ 747 748 /* Linux kernel image is loaded at 0xa0000000 */ 749 750 oem_vm_mem: memory@bb000000 { 751 reg = <0x0 0xbb000000 0x0 0x5000000>; 752 no-map; 753 }; 754 755 mte_mem: memory@c0000000 { 756 reg = <0x0 0xc0000000 0x0 0x20000000>; 757 no-map; 758 }; 759 760 qheebsp_reserved_mem: memory@e0000000 { 761 reg = <0x0 0xe0000000 0x0 0x600000>; 762 no-map; 763 }; 764 765 cpusys_vm_mem: memory@e0600000 { 766 reg = <0x0 0xe0600000 0x0 0x400000>; 767 no-map; 768 }; 769 770 hyp_reserved_mem: memory@e0a00000 { 771 reg = <0x0 0xe0a00000 0x0 0x100000>; 772 no-map; 773 }; 774 775 trust_ui_vm_mem: memory@e0b00000 { 776 reg = <0x0 0xe0b00000 0x0 0x4af3000>; 777 no-map; 778 }; 779 780 trust_ui_vm_qrtr: memory@e55f3000 { 781 reg = <0x0 0xe55f3000 0x0 0x9000>; 782 no-map; 783 }; 784 785 trust_ui_vm_vblk0_ring: memory@e55fc000 { 786 reg = <0x0 0xe55fc000 0x0 0x4000>; 787 no-map; 788 }; 789 790 trust_ui_vm_swiotlb: memory@e5600000 { 791 reg = <0x0 0xe5600000 0x0 0x100000>; 792 no-map; 793 }; 794 795 tz_stat_mem: memory@e8800000 { 796 reg = <0x0 0xe8800000 0x0 0x100000>; 797 no-map; 798 }; 799 800 tags_mem: memory@e8900000 { 801 reg = <0x0 0xe8900000 0x0 0x1200000>; 802 no-map; 803 }; 804 805 qtee_mem: memory@e9b00000 { 806 reg = <0x0 0xe9b00000 0x0 0x500000>; 807 no-map; 808 }; 809 810 trusted_apps_mem: memory@ea000000 { 811 reg = <0x0 0xea000000 0x0 0x3900000>; 812 no-map; 813 }; 814 815 trusted_apps_ext_mem: memory@ed900000 { 816 reg = <0x0 0xed900000 0x0 0x3b00000>; 817 no-map; 818 }; 819 }; 820 821 smp2p-adsp { 822 compatible = "qcom,smp2p"; 823 qcom,smem = <443>, <429>; 824 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 825 IPCC_MPROC_SIGNAL_SMP2P 826 IRQ_TYPE_EDGE_RISING>; 827 mboxes = <&ipcc IPCC_CLIENT_LPASS 828 IPCC_MPROC_SIGNAL_SMP2P>; 829 830 qcom,local-pid = <0>; 831 qcom,remote-pid = <2>; 832 833 smp2p_adsp_out: master-kernel { 834 qcom,entry-name = "master-kernel"; 835 #qcom,smem-state-cells = <1>; 836 }; 837 838 smp2p_adsp_in: slave-kernel { 839 qcom,entry-name = "slave-kernel"; 840 interrupt-controller; 841 #interrupt-cells = <2>; 842 }; 843 }; 844 845 smp2p-cdsp { 846 compatible = "qcom,smp2p"; 847 qcom,smem = <94>, <432>; 848 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 849 IPCC_MPROC_SIGNAL_SMP2P 850 IRQ_TYPE_EDGE_RISING>; 851 mboxes = <&ipcc IPCC_CLIENT_CDSP 852 IPCC_MPROC_SIGNAL_SMP2P>; 853 854 qcom,local-pid = <0>; 855 qcom,remote-pid = <5>; 856 857 smp2p_cdsp_out: master-kernel { 858 qcom,entry-name = "master-kernel"; 859 #qcom,smem-state-cells = <1>; 860 }; 861 862 smp2p_cdsp_in: slave-kernel { 863 qcom,entry-name = "slave-kernel"; 864 interrupt-controller; 865 #interrupt-cells = <2>; 866 }; 867 }; 868 869 smp2p-modem { 870 compatible = "qcom,smp2p"; 871 qcom,smem = <435>, <428>; 872 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 873 IPCC_MPROC_SIGNAL_SMP2P 874 IRQ_TYPE_EDGE_RISING>; 875 mboxes = <&ipcc IPCC_CLIENT_MPSS 876 IPCC_MPROC_SIGNAL_SMP2P>; 877 878 qcom,local-pid = <0>; 879 qcom,remote-pid = <1>; 880 881 smp2p_modem_out: master-kernel { 882 qcom,entry-name = "master-kernel"; 883 #qcom,smem-state-cells = <1>; 884 }; 885 886 smp2p_modem_in: slave-kernel { 887 qcom,entry-name = "slave-kernel"; 888 interrupt-controller; 889 #interrupt-cells = <2>; 890 }; 891 892 ipa_smp2p_out: ipa-ap-to-modem { 893 qcom,entry-name = "ipa"; 894 #qcom,smem-state-cells = <1>; 895 }; 896 897 ipa_smp2p_in: ipa-modem-to-ap { 898 qcom,entry-name = "ipa"; 899 interrupt-controller; 900 #interrupt-cells = <2>; 901 }; 902 }; 903 904 smp2p-slpi { 905 compatible = "qcom,smp2p"; 906 qcom,smem = <481>, <430>; 907 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 908 IPCC_MPROC_SIGNAL_SMP2P 909 IRQ_TYPE_EDGE_RISING>; 910 mboxes = <&ipcc IPCC_CLIENT_SLPI 911 IPCC_MPROC_SIGNAL_SMP2P>; 912 913 qcom,local-pid = <0>; 914 qcom,remote-pid = <3>; 915 916 smp2p_slpi_out: master-kernel { 917 qcom,entry-name = "master-kernel"; 918 #qcom,smem-state-cells = <1>; 919 }; 920 921 smp2p_slpi_in: slave-kernel { 922 qcom,entry-name = "slave-kernel"; 923 interrupt-controller; 924 #interrupt-cells = <2>; 925 }; 926 }; 927 928 soc: soc@0 { 929 #address-cells = <2>; 930 #size-cells = <2>; 931 ranges = <0 0 0 0 0x10 0>; 932 dma-ranges = <0 0 0 0 0x10 0>; 933 compatible = "simple-bus"; 934 935 gcc: clock-controller@100000 { 936 compatible = "qcom,gcc-sm8450"; 937 reg = <0x0 0x00100000 0x0 0x1f4200>; 938 #clock-cells = <1>; 939 #reset-cells = <1>; 940 #power-domain-cells = <1>; 941 clocks = <&rpmhcc RPMH_CXO_CLK>, 942 <&sleep_clk>, 943 <&pcie0_phy>, 944 <&pcie1_phy QMP_PCIE_PIPE_CLK>, 945 <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, 946 <&ufs_mem_phy 0>, 947 <&ufs_mem_phy 1>, 948 <&ufs_mem_phy 2>, 949 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 950 clock-names = "bi_tcxo", 951 "sleep_clk", 952 "pcie_0_pipe_clk", 953 "pcie_1_pipe_clk", 954 "pcie_1_phy_aux_clk", 955 "ufs_phy_rx_symbol_0_clk", 956 "ufs_phy_rx_symbol_1_clk", 957 "ufs_phy_tx_symbol_0_clk", 958 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 959 }; 960 961 gpi_dma2: dma-controller@800000 { 962 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 963 #dma-cells = <3>; 964 reg = <0 0x00800000 0 0x60000>; 965 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 975 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 976 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 977 dma-channels = <12>; 978 dma-channel-mask = <0x7e>; 979 iommus = <&apps_smmu 0x496 0x0>; 980 status = "disabled"; 981 }; 982 983 qupv3_id_2: geniqup@8c0000 { 984 compatible = "qcom,geni-se-qup"; 985 reg = <0x0 0x008c0000 0x0 0x2000>; 986 clock-names = "m-ahb", "s-ahb"; 987 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 988 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 989 iommus = <&apps_smmu 0x483 0x0>; 990 #address-cells = <2>; 991 #size-cells = <2>; 992 ranges; 993 status = "disabled"; 994 995 i2c15: i2c@880000 { 996 compatible = "qcom,geni-i2c"; 997 reg = <0x0 0x00880000 0x0 0x4000>; 998 clock-names = "se"; 999 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1000 pinctrl-names = "default"; 1001 pinctrl-0 = <&qup_i2c15_data_clk>; 1002 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1006 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1007 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1008 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1009 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1010 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1011 dma-names = "tx", "rx"; 1012 status = "disabled"; 1013 }; 1014 1015 spi15: spi@880000 { 1016 compatible = "qcom,geni-spi"; 1017 reg = <0x0 0x00880000 0x0 0x4000>; 1018 clock-names = "se"; 1019 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1020 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1021 pinctrl-names = "default"; 1022 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1023 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1024 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1025 interconnect-names = "qup-core", "qup-config"; 1026 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1027 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1028 dma-names = "tx", "rx"; 1029 #address-cells = <1>; 1030 #size-cells = <0>; 1031 status = "disabled"; 1032 }; 1033 1034 i2c16: i2c@884000 { 1035 compatible = "qcom,geni-i2c"; 1036 reg = <0x0 0x00884000 0x0 0x4000>; 1037 clock-names = "se"; 1038 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1039 pinctrl-names = "default"; 1040 pinctrl-0 = <&qup_i2c16_data_clk>; 1041 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1042 #address-cells = <1>; 1043 #size-cells = <0>; 1044 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1045 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1046 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1047 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1048 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1049 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1050 dma-names = "tx", "rx"; 1051 status = "disabled"; 1052 }; 1053 1054 spi16: spi@884000 { 1055 compatible = "qcom,geni-spi"; 1056 reg = <0x0 0x00884000 0x0 0x4000>; 1057 clock-names = "se"; 1058 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1059 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1060 pinctrl-names = "default"; 1061 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 1062 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1063 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1064 interconnect-names = "qup-core", "qup-config"; 1065 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1066 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1067 dma-names = "tx", "rx"; 1068 #address-cells = <1>; 1069 #size-cells = <0>; 1070 status = "disabled"; 1071 }; 1072 1073 i2c17: i2c@888000 { 1074 compatible = "qcom,geni-i2c"; 1075 reg = <0x0 0x00888000 0x0 0x4000>; 1076 clock-names = "se"; 1077 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1078 pinctrl-names = "default"; 1079 pinctrl-0 = <&qup_i2c17_data_clk>; 1080 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1081 #address-cells = <1>; 1082 #size-cells = <0>; 1083 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1084 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1085 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1086 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1087 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1088 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1089 dma-names = "tx", "rx"; 1090 status = "disabled"; 1091 }; 1092 1093 spi17: spi@888000 { 1094 compatible = "qcom,geni-spi"; 1095 reg = <0x0 0x00888000 0x0 0x4000>; 1096 clock-names = "se"; 1097 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1098 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1099 pinctrl-names = "default"; 1100 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 1101 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1102 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1103 interconnect-names = "qup-core", "qup-config"; 1104 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1105 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1106 dma-names = "tx", "rx"; 1107 #address-cells = <1>; 1108 #size-cells = <0>; 1109 status = "disabled"; 1110 }; 1111 1112 i2c18: i2c@88c000 { 1113 compatible = "qcom,geni-i2c"; 1114 reg = <0x0 0x0088c000 0x0 0x4000>; 1115 clock-names = "se"; 1116 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1117 pinctrl-names = "default"; 1118 pinctrl-0 = <&qup_i2c18_data_clk>; 1119 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1120 #address-cells = <1>; 1121 #size-cells = <0>; 1122 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1123 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1124 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1125 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1126 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1127 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1128 dma-names = "tx", "rx"; 1129 status = "disabled"; 1130 }; 1131 1132 spi18: spi@88c000 { 1133 compatible = "qcom,geni-spi"; 1134 reg = <0 0x0088c000 0 0x4000>; 1135 clock-names = "se"; 1136 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1137 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1138 pinctrl-names = "default"; 1139 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 1140 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1141 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1142 interconnect-names = "qup-core", "qup-config"; 1143 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1144 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1145 dma-names = "tx", "rx"; 1146 #address-cells = <1>; 1147 #size-cells = <0>; 1148 status = "disabled"; 1149 }; 1150 1151 i2c19: i2c@890000 { 1152 compatible = "qcom,geni-i2c"; 1153 reg = <0x0 0x00890000 0x0 0x4000>; 1154 clock-names = "se"; 1155 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1156 pinctrl-names = "default"; 1157 pinctrl-0 = <&qup_i2c19_data_clk>; 1158 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1159 #address-cells = <1>; 1160 #size-cells = <0>; 1161 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1162 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1163 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1164 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1165 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1166 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1167 dma-names = "tx", "rx"; 1168 status = "disabled"; 1169 }; 1170 1171 spi19: spi@890000 { 1172 compatible = "qcom,geni-spi"; 1173 reg = <0 0x00890000 0 0x4000>; 1174 clock-names = "se"; 1175 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1176 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1177 pinctrl-names = "default"; 1178 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 1179 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1180 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1181 interconnect-names = "qup-core", "qup-config"; 1182 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1183 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1184 dma-names = "tx", "rx"; 1185 #address-cells = <1>; 1186 #size-cells = <0>; 1187 status = "disabled"; 1188 }; 1189 1190 i2c20: i2c@894000 { 1191 compatible = "qcom,geni-i2c"; 1192 reg = <0x0 0x00894000 0x0 0x4000>; 1193 clock-names = "se"; 1194 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1195 pinctrl-names = "default"; 1196 pinctrl-0 = <&qup_i2c20_data_clk>; 1197 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1198 #address-cells = <1>; 1199 #size-cells = <0>; 1200 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1201 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1202 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1203 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1204 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1205 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1206 dma-names = "tx", "rx"; 1207 status = "disabled"; 1208 }; 1209 1210 uart20: serial@894000 { 1211 compatible = "qcom,geni-uart"; 1212 reg = <0 0x00894000 0 0x4000>; 1213 clock-names = "se"; 1214 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1215 pinctrl-names = "default"; 1216 pinctrl-0 = <&qup_uart20_default>; 1217 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1218 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1219 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1220 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1221 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1222 interconnect-names = "qup-core", 1223 "qup-config"; 1224 status = "disabled"; 1225 }; 1226 1227 spi20: spi@894000 { 1228 compatible = "qcom,geni-spi"; 1229 reg = <0 0x00894000 0 0x4000>; 1230 clock-names = "se"; 1231 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1232 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1233 pinctrl-names = "default"; 1234 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1235 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1236 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1237 interconnect-names = "qup-core", "qup-config"; 1238 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1239 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1240 dma-names = "tx", "rx"; 1241 #address-cells = <1>; 1242 #size-cells = <0>; 1243 status = "disabled"; 1244 }; 1245 1246 i2c21: i2c@898000 { 1247 compatible = "qcom,geni-i2c"; 1248 reg = <0x0 0x00898000 0x0 0x4000>; 1249 clock-names = "se"; 1250 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1251 pinctrl-names = "default"; 1252 pinctrl-0 = <&qup_i2c21_data_clk>; 1253 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1254 #address-cells = <1>; 1255 #size-cells = <0>; 1256 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1257 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1258 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1259 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1260 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1261 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1262 dma-names = "tx", "rx"; 1263 status = "disabled"; 1264 }; 1265 1266 spi21: spi@898000 { 1267 compatible = "qcom,geni-spi"; 1268 reg = <0 0x00898000 0 0x4000>; 1269 clock-names = "se"; 1270 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1271 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1272 pinctrl-names = "default"; 1273 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1274 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1275 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1276 interconnect-names = "qup-core", "qup-config"; 1277 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1278 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1279 dma-names = "tx", "rx"; 1280 #address-cells = <1>; 1281 #size-cells = <0>; 1282 status = "disabled"; 1283 }; 1284 }; 1285 1286 gpi_dma0: dma-controller@900000 { 1287 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1288 #dma-cells = <3>; 1289 reg = <0 0x00900000 0 0x60000>; 1290 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1291 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1292 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1293 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1294 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1295 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1296 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1297 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1298 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1299 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1300 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1301 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1302 dma-channels = <12>; 1303 dma-channel-mask = <0x7e>; 1304 iommus = <&apps_smmu 0x5b6 0x0>; 1305 status = "disabled"; 1306 }; 1307 1308 qupv3_id_0: geniqup@9c0000 { 1309 compatible = "qcom,geni-se-qup"; 1310 reg = <0x0 0x009c0000 0x0 0x2000>; 1311 clock-names = "m-ahb", "s-ahb"; 1312 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1313 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1314 iommus = <&apps_smmu 0x5a3 0x0>; 1315 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>; 1316 interconnect-names = "qup-core"; 1317 #address-cells = <2>; 1318 #size-cells = <2>; 1319 ranges; 1320 status = "disabled"; 1321 1322 i2c0: i2c@980000 { 1323 compatible = "qcom,geni-i2c"; 1324 reg = <0x0 0x00980000 0x0 0x4000>; 1325 clock-names = "se"; 1326 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1327 pinctrl-names = "default"; 1328 pinctrl-0 = <&qup_i2c0_data_clk>; 1329 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1330 #address-cells = <1>; 1331 #size-cells = <0>; 1332 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1333 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1334 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1335 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1336 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1337 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1338 dma-names = "tx", "rx"; 1339 status = "disabled"; 1340 }; 1341 1342 spi0: spi@980000 { 1343 compatible = "qcom,geni-spi"; 1344 reg = <0x0 0x00980000 0x0 0x4000>; 1345 clock-names = "se"; 1346 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1347 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1348 pinctrl-names = "default"; 1349 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1350 power-domains = <&rpmhpd RPMHPD_CX>; 1351 operating-points-v2 = <&qup_opp_table_100mhz>; 1352 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1353 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1354 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1355 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1356 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1357 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1358 dma-names = "tx", "rx"; 1359 #address-cells = <1>; 1360 #size-cells = <0>; 1361 status = "disabled"; 1362 }; 1363 1364 i2c1: i2c@984000 { 1365 compatible = "qcom,geni-i2c"; 1366 reg = <0x0 0x00984000 0x0 0x4000>; 1367 clock-names = "se"; 1368 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1369 pinctrl-names = "default"; 1370 pinctrl-0 = <&qup_i2c1_data_clk>; 1371 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1372 #address-cells = <1>; 1373 #size-cells = <0>; 1374 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1375 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1376 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1377 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1378 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1379 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1380 dma-names = "tx", "rx"; 1381 status = "disabled"; 1382 }; 1383 1384 spi1: spi@984000 { 1385 compatible = "qcom,geni-spi"; 1386 reg = <0x0 0x00984000 0x0 0x4000>; 1387 clock-names = "se"; 1388 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1389 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1390 pinctrl-names = "default"; 1391 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1392 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1393 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1394 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1395 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1396 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1397 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1398 dma-names = "tx", "rx"; 1399 #address-cells = <1>; 1400 #size-cells = <0>; 1401 status = "disabled"; 1402 }; 1403 1404 i2c2: i2c@988000 { 1405 compatible = "qcom,geni-i2c"; 1406 reg = <0x0 0x00988000 0x0 0x4000>; 1407 clock-names = "se"; 1408 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1409 pinctrl-names = "default"; 1410 pinctrl-0 = <&qup_i2c2_data_clk>; 1411 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1412 #address-cells = <1>; 1413 #size-cells = <0>; 1414 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1415 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1416 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1417 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1418 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1419 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1420 dma-names = "tx", "rx"; 1421 status = "disabled"; 1422 }; 1423 1424 spi2: spi@988000 { 1425 compatible = "qcom,geni-spi"; 1426 reg = <0x0 0x00988000 0x0 0x4000>; 1427 clock-names = "se"; 1428 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1429 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1430 pinctrl-names = "default"; 1431 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1432 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1433 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1434 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1435 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1436 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1437 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1438 dma-names = "tx", "rx"; 1439 #address-cells = <1>; 1440 #size-cells = <0>; 1441 status = "disabled"; 1442 }; 1443 1444 1445 i2c3: i2c@98c000 { 1446 compatible = "qcom,geni-i2c"; 1447 reg = <0x0 0x0098c000 0x0 0x4000>; 1448 clock-names = "se"; 1449 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1450 pinctrl-names = "default"; 1451 pinctrl-0 = <&qup_i2c3_data_clk>; 1452 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1453 #address-cells = <1>; 1454 #size-cells = <0>; 1455 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1456 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1457 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1458 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1459 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1460 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1461 dma-names = "tx", "rx"; 1462 status = "disabled"; 1463 }; 1464 1465 spi3: spi@98c000 { 1466 compatible = "qcom,geni-spi"; 1467 reg = <0x0 0x0098c000 0x0 0x4000>; 1468 clock-names = "se"; 1469 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1470 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1471 pinctrl-names = "default"; 1472 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1473 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1474 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1475 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1476 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1477 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1478 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1479 dma-names = "tx", "rx"; 1480 #address-cells = <1>; 1481 #size-cells = <0>; 1482 status = "disabled"; 1483 }; 1484 1485 i2c4: i2c@990000 { 1486 compatible = "qcom,geni-i2c"; 1487 reg = <0x0 0x00990000 0x0 0x4000>; 1488 clock-names = "se"; 1489 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1490 pinctrl-names = "default"; 1491 pinctrl-0 = <&qup_i2c4_data_clk>; 1492 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1493 #address-cells = <1>; 1494 #size-cells = <0>; 1495 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1496 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1497 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1498 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1499 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1500 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1501 dma-names = "tx", "rx"; 1502 status = "disabled"; 1503 }; 1504 1505 spi4: spi@990000 { 1506 compatible = "qcom,geni-spi"; 1507 reg = <0x0 0x00990000 0x0 0x4000>; 1508 clock-names = "se"; 1509 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1510 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1511 pinctrl-names = "default"; 1512 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1513 power-domains = <&rpmhpd RPMHPD_CX>; 1514 operating-points-v2 = <&qup_opp_table_100mhz>; 1515 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1516 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1517 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1518 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1519 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1520 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1521 dma-names = "tx", "rx"; 1522 #address-cells = <1>; 1523 #size-cells = <0>; 1524 status = "disabled"; 1525 }; 1526 1527 i2c5: i2c@994000 { 1528 compatible = "qcom,geni-i2c"; 1529 reg = <0x0 0x00994000 0x0 0x4000>; 1530 clock-names = "se"; 1531 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1532 pinctrl-names = "default"; 1533 pinctrl-0 = <&qup_i2c5_data_clk>; 1534 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1535 #address-cells = <1>; 1536 #size-cells = <0>; 1537 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1538 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1539 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1540 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1541 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1542 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1543 dma-names = "tx", "rx"; 1544 status = "disabled"; 1545 }; 1546 1547 spi5: spi@994000 { 1548 compatible = "qcom,geni-spi"; 1549 reg = <0x0 0x00994000 0x0 0x4000>; 1550 clock-names = "se"; 1551 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1552 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1553 pinctrl-names = "default"; 1554 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1555 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1556 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1557 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1558 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1559 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1560 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1561 dma-names = "tx", "rx"; 1562 #address-cells = <1>; 1563 #size-cells = <0>; 1564 status = "disabled"; 1565 }; 1566 1567 1568 i2c6: i2c@998000 { 1569 compatible = "qcom,geni-i2c"; 1570 reg = <0x0 0x00998000 0x0 0x4000>; 1571 clock-names = "se"; 1572 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1573 pinctrl-names = "default"; 1574 pinctrl-0 = <&qup_i2c6_data_clk>; 1575 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1576 #address-cells = <1>; 1577 #size-cells = <0>; 1578 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1579 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1580 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1581 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1582 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1583 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1584 dma-names = "tx", "rx"; 1585 status = "disabled"; 1586 }; 1587 1588 spi6: spi@998000 { 1589 compatible = "qcom,geni-spi"; 1590 reg = <0x0 0x00998000 0x0 0x4000>; 1591 clock-names = "se"; 1592 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1593 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1594 pinctrl-names = "default"; 1595 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1596 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1597 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1598 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1599 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1600 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1601 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1602 dma-names = "tx", "rx"; 1603 #address-cells = <1>; 1604 #size-cells = <0>; 1605 status = "disabled"; 1606 }; 1607 1608 uart7: serial@99c000 { 1609 compatible = "qcom,geni-debug-uart"; 1610 reg = <0 0x0099c000 0 0x4000>; 1611 clock-names = "se"; 1612 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1613 pinctrl-names = "default"; 1614 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 1615 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1616 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1617 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1618 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1619 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1620 interconnect-names = "qup-core", 1621 "qup-config"; 1622 status = "disabled"; 1623 }; 1624 }; 1625 1626 gpi_dma1: dma-controller@a00000 { 1627 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1628 #dma-cells = <3>; 1629 reg = <0 0x00a00000 0 0x60000>; 1630 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1631 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1632 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1633 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1634 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1636 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1637 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1638 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1639 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1640 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1641 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1642 dma-channels = <12>; 1643 dma-channel-mask = <0x7e>; 1644 iommus = <&apps_smmu 0x56 0x0>; 1645 status = "disabled"; 1646 }; 1647 1648 qupv3_id_1: geniqup@ac0000 { 1649 compatible = "qcom,geni-se-qup"; 1650 reg = <0x0 0x00ac0000 0x0 0x6000>; 1651 clock-names = "m-ahb", "s-ahb"; 1652 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1653 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1654 iommus = <&apps_smmu 0x43 0x0>; 1655 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1656 interconnect-names = "qup-core"; 1657 #address-cells = <2>; 1658 #size-cells = <2>; 1659 ranges; 1660 status = "disabled"; 1661 1662 i2c8: i2c@a80000 { 1663 compatible = "qcom,geni-i2c"; 1664 reg = <0x0 0x00a80000 0x0 0x4000>; 1665 clock-names = "se"; 1666 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1667 pinctrl-names = "default"; 1668 pinctrl-0 = <&qup_i2c8_data_clk>; 1669 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1670 #address-cells = <1>; 1671 #size-cells = <0>; 1672 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1673 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1674 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1675 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1676 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1677 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1678 dma-names = "tx", "rx"; 1679 status = "disabled"; 1680 }; 1681 1682 spi8: spi@a80000 { 1683 compatible = "qcom,geni-spi"; 1684 reg = <0x0 0x00a80000 0x0 0x4000>; 1685 clock-names = "se"; 1686 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1687 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1688 pinctrl-names = "default"; 1689 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1690 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1691 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1692 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1693 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1694 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1695 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1696 dma-names = "tx", "rx"; 1697 #address-cells = <1>; 1698 #size-cells = <0>; 1699 status = "disabled"; 1700 }; 1701 1702 i2c9: i2c@a84000 { 1703 compatible = "qcom,geni-i2c"; 1704 reg = <0x0 0x00a84000 0x0 0x4000>; 1705 clock-names = "se"; 1706 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1707 pinctrl-names = "default"; 1708 pinctrl-0 = <&qup_i2c9_data_clk>; 1709 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1710 #address-cells = <1>; 1711 #size-cells = <0>; 1712 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1713 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1714 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1715 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1716 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1717 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1718 dma-names = "tx", "rx"; 1719 status = "disabled"; 1720 }; 1721 1722 spi9: spi@a84000 { 1723 compatible = "qcom,geni-spi"; 1724 reg = <0x0 0x00a84000 0x0 0x4000>; 1725 clock-names = "se"; 1726 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1727 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1728 pinctrl-names = "default"; 1729 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1730 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1731 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1732 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1733 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1734 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1735 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1736 dma-names = "tx", "rx"; 1737 #address-cells = <1>; 1738 #size-cells = <0>; 1739 status = "disabled"; 1740 }; 1741 1742 i2c10: i2c@a88000 { 1743 compatible = "qcom,geni-i2c"; 1744 reg = <0x0 0x00a88000 0x0 0x4000>; 1745 clock-names = "se"; 1746 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1747 pinctrl-names = "default"; 1748 pinctrl-0 = <&qup_i2c10_data_clk>; 1749 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1750 #address-cells = <1>; 1751 #size-cells = <0>; 1752 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1753 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1754 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1755 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1756 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1757 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1758 dma-names = "tx", "rx"; 1759 status = "disabled"; 1760 }; 1761 1762 spi10: spi@a88000 { 1763 compatible = "qcom,geni-spi"; 1764 reg = <0x0 0x00a88000 0x0 0x4000>; 1765 clock-names = "se"; 1766 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1767 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1768 pinctrl-names = "default"; 1769 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1770 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1771 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1772 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1773 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1774 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1775 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1776 dma-names = "tx", "rx"; 1777 #address-cells = <1>; 1778 #size-cells = <0>; 1779 status = "disabled"; 1780 }; 1781 1782 i2c11: i2c@a8c000 { 1783 compatible = "qcom,geni-i2c"; 1784 reg = <0x0 0x00a8c000 0x0 0x4000>; 1785 clock-names = "se"; 1786 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1787 pinctrl-names = "default"; 1788 pinctrl-0 = <&qup_i2c11_data_clk>; 1789 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1790 #address-cells = <1>; 1791 #size-cells = <0>; 1792 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1793 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1794 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1795 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1796 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1797 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1798 dma-names = "tx", "rx"; 1799 status = "disabled"; 1800 }; 1801 1802 spi11: spi@a8c000 { 1803 compatible = "qcom,geni-spi"; 1804 reg = <0x0 0x00a8c000 0x0 0x4000>; 1805 clock-names = "se"; 1806 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1807 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1808 pinctrl-names = "default"; 1809 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1810 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1811 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1812 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1813 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1814 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1815 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1816 dma-names = "tx", "rx"; 1817 #address-cells = <1>; 1818 #size-cells = <0>; 1819 status = "disabled"; 1820 }; 1821 1822 i2c12: i2c@a90000 { 1823 compatible = "qcom,geni-i2c"; 1824 reg = <0x0 0x00a90000 0x0 0x4000>; 1825 clock-names = "se"; 1826 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1827 pinctrl-names = "default"; 1828 pinctrl-0 = <&qup_i2c12_data_clk>; 1829 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1830 #address-cells = <1>; 1831 #size-cells = <0>; 1832 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1833 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1834 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1835 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1836 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1837 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1838 dma-names = "tx", "rx"; 1839 status = "disabled"; 1840 }; 1841 1842 spi12: spi@a90000 { 1843 compatible = "qcom,geni-spi"; 1844 reg = <0x0 0x00a90000 0x0 0x4000>; 1845 clock-names = "se"; 1846 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1847 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1848 pinctrl-names = "default"; 1849 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1850 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1851 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1852 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1853 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1854 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1855 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1856 dma-names = "tx", "rx"; 1857 #address-cells = <1>; 1858 #size-cells = <0>; 1859 status = "disabled"; 1860 }; 1861 1862 i2c13: i2c@a94000 { 1863 compatible = "qcom,geni-i2c"; 1864 reg = <0 0x00a94000 0 0x4000>; 1865 clock-names = "se"; 1866 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1867 pinctrl-names = "default"; 1868 pinctrl-0 = <&qup_i2c13_data_clk>; 1869 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1870 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1871 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1872 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1873 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1874 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1875 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1876 dma-names = "tx", "rx"; 1877 #address-cells = <1>; 1878 #size-cells = <0>; 1879 status = "disabled"; 1880 }; 1881 1882 spi13: spi@a94000 { 1883 compatible = "qcom,geni-spi"; 1884 reg = <0x0 0x00a94000 0x0 0x4000>; 1885 clock-names = "se"; 1886 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1887 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1888 pinctrl-names = "default"; 1889 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1890 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1891 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1892 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1893 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1894 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1895 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1896 dma-names = "tx", "rx"; 1897 #address-cells = <1>; 1898 #size-cells = <0>; 1899 status = "disabled"; 1900 }; 1901 1902 i2c14: i2c@a98000 { 1903 compatible = "qcom,geni-i2c"; 1904 reg = <0 0x00a98000 0 0x4000>; 1905 clock-names = "se"; 1906 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1907 pinctrl-names = "default"; 1908 pinctrl-0 = <&qup_i2c14_data_clk>; 1909 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1910 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1911 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1912 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1913 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1914 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1915 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1916 dma-names = "tx", "rx"; 1917 #address-cells = <1>; 1918 #size-cells = <0>; 1919 status = "disabled"; 1920 }; 1921 1922 spi14: spi@a98000 { 1923 compatible = "qcom,geni-spi"; 1924 reg = <0x0 0x00a98000 0x0 0x4000>; 1925 clock-names = "se"; 1926 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1927 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1928 pinctrl-names = "default"; 1929 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1930 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1931 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1932 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1933 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1934 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1935 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1936 dma-names = "tx", "rx"; 1937 #address-cells = <1>; 1938 #size-cells = <0>; 1939 status = "disabled"; 1940 }; 1941 }; 1942 1943 rng: rng@10c3000 { 1944 compatible = "qcom,sm8450-trng", "qcom,trng"; 1945 reg = <0 0x010c3000 0 0x1000>; 1946 }; 1947 1948 pcie0: pcie@1c00000 { 1949 compatible = "qcom,pcie-sm8450-pcie0"; 1950 reg = <0 0x01c00000 0 0x3000>, 1951 <0 0x60000000 0 0xf1d>, 1952 <0 0x60000f20 0 0xa8>, 1953 <0 0x60001000 0 0x1000>, 1954 <0 0x60100000 0 0x100000>; 1955 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1956 device_type = "pci"; 1957 linux,pci-domain = <0>; 1958 bus-range = <0x00 0xff>; 1959 num-lanes = <1>; 1960 1961 #address-cells = <3>; 1962 #size-cells = <2>; 1963 1964 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1965 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1966 1967 msi-map = <0x0 &gic_its 0x5980 0x1>, 1968 <0x100 &gic_its 0x5981 0x1>; 1969 msi-map-mask = <0xff00>; 1970 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1971 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1972 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1973 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1974 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1975 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1976 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1977 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1978 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1979 interrupt-names = "msi0", 1980 "msi1", 1981 "msi2", 1982 "msi3", 1983 "msi4", 1984 "msi5", 1985 "msi6", 1986 "msi7", 1987 "global"; 1988 #interrupt-cells = <1>; 1989 interrupt-map-mask = <0 0 0 0x7>; 1990 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1991 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1992 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1993 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1994 1995 interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS 1996 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1997 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1998 &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; 1999 interconnect-names = "pcie-mem", "cpu-pcie"; 2000 2001 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 2002 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, 2003 <&pcie0_phy>, 2004 <&rpmhcc RPMH_CXO_CLK>, 2005 <&gcc GCC_PCIE_0_AUX_CLK>, 2006 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2007 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2008 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2009 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2010 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2011 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 2012 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2013 clock-names = "pipe", 2014 "pipe_mux", 2015 "phy_pipe", 2016 "ref", 2017 "aux", 2018 "cfg", 2019 "bus_master", 2020 "bus_slave", 2021 "slave_q2a", 2022 "ddrss_sf_tbu", 2023 "aggre0", 2024 "aggre1"; 2025 2026 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 2027 <0x100 &apps_smmu 0x1c01 0x1>; 2028 2029 resets = <&gcc GCC_PCIE_0_BCR>; 2030 reset-names = "pci"; 2031 2032 power-domains = <&gcc PCIE_0_GDSC>; 2033 2034 phys = <&pcie0_phy>; 2035 phy-names = "pciephy"; 2036 2037 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; 2038 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; 2039 2040 pinctrl-names = "default"; 2041 pinctrl-0 = <&pcie0_default_state>; 2042 2043 operating-points-v2 = <&pcie0_opp_table>; 2044 2045 status = "disabled"; 2046 2047 pcie0_opp_table: opp-table { 2048 compatible = "operating-points-v2"; 2049 2050 /* GEN 1 x1 */ 2051 opp-2500000 { 2052 opp-hz = /bits/ 64 <2500000>; 2053 required-opps = <&rpmhpd_opp_low_svs>; 2054 opp-peak-kBps = <250000 1>; 2055 }; 2056 2057 /* GEN 2 x1 */ 2058 opp-5000000 { 2059 opp-hz = /bits/ 64 <5000000>; 2060 required-opps = <&rpmhpd_opp_low_svs>; 2061 opp-peak-kBps = <500000 1>; 2062 }; 2063 2064 /* GEN 3 x1 */ 2065 opp-8000000 { 2066 opp-hz = /bits/ 64 <8000000>; 2067 required-opps = <&rpmhpd_opp_nom>; 2068 opp-peak-kBps = <984500 1>; 2069 }; 2070 }; 2071 2072 pcieport0: pcie@0 { 2073 device_type = "pci"; 2074 reg = <0x0 0x0 0x0 0x0 0x0>; 2075 bus-range = <0x01 0xff>; 2076 2077 #address-cells = <3>; 2078 #size-cells = <2>; 2079 ranges; 2080 }; 2081 }; 2082 2083 pcie0_phy: phy@1c06000 { 2084 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; 2085 reg = <0 0x01c06000 0 0x2000>; 2086 2087 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2088 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2089 <&gcc GCC_PCIE_0_CLKREF_EN>, 2090 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 2091 <&gcc GCC_PCIE_0_PIPE_CLK>; 2092 clock-names = "aux", 2093 "cfg_ahb", 2094 "ref", 2095 "rchng", 2096 "pipe"; 2097 2098 clock-output-names = "pcie_0_pipe_clk"; 2099 #clock-cells = <0>; 2100 2101 #phy-cells = <0>; 2102 2103 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2104 reset-names = "phy"; 2105 2106 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 2107 assigned-clock-rates = <100000000>; 2108 2109 status = "disabled"; 2110 }; 2111 2112 pcie1: pcie@1c08000 { 2113 compatible = "qcom,pcie-sm8450-pcie1"; 2114 reg = <0 0x01c08000 0 0x3000>, 2115 <0 0x40000000 0 0xf1d>, 2116 <0 0x40000f20 0 0xa8>, 2117 <0 0x40001000 0 0x1000>, 2118 <0 0x40100000 0 0x100000>; 2119 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2120 device_type = "pci"; 2121 linux,pci-domain = <1>; 2122 bus-range = <0x00 0xff>; 2123 num-lanes = <2>; 2124 2125 #address-cells = <3>; 2126 #size-cells = <2>; 2127 2128 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2129 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2130 2131 msi-map = <0x0 &gic_its 0x5a00 0x1>, 2132 <0x100 &gic_its 0x5a01 0x1>; 2133 msi-map-mask = <0xff00>; 2134 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2135 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2136 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2137 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2138 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2139 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2140 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2141 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2142 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 2143 interrupt-names = "msi0", 2144 "msi1", 2145 "msi2", 2146 "msi3", 2147 "msi4", 2148 "msi5", 2149 "msi6", 2150 "msi7", 2151 "global"; 2152 #interrupt-cells = <1>; 2153 interrupt-map-mask = <0 0 0 0x7>; 2154 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2155 <0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2156 <0 0 0 3 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2157 <0 0 0 4 &intc 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2158 2159 interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS 2160 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2161 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2162 &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; 2163 interconnect-names = "pcie-mem", "cpu-pcie"; 2164 2165 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2166 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2167 <&pcie1_phy QMP_PCIE_PIPE_CLK>, 2168 <&rpmhcc RPMH_CXO_CLK>, 2169 <&gcc GCC_PCIE_1_AUX_CLK>, 2170 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2171 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2172 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2173 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2174 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2175 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2176 clock-names = "pipe", 2177 "pipe_mux", 2178 "phy_pipe", 2179 "ref", 2180 "aux", 2181 "cfg", 2182 "bus_master", 2183 "bus_slave", 2184 "slave_q2a", 2185 "ddrss_sf_tbu", 2186 "aggre1"; 2187 2188 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2189 <0x100 &apps_smmu 0x1c81 0x1>; 2190 2191 resets = <&gcc GCC_PCIE_1_BCR>; 2192 reset-names = "pci"; 2193 2194 power-domains = <&gcc PCIE_1_GDSC>; 2195 2196 phys = <&pcie1_phy>; 2197 phy-names = "pciephy"; 2198 2199 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; 2200 wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; 2201 2202 pinctrl-names = "default"; 2203 pinctrl-0 = <&pcie1_default_state>; 2204 2205 operating-points-v2 = <&pcie1_opp_table>; 2206 2207 status = "disabled"; 2208 2209 pcie1_opp_table: opp-table { 2210 compatible = "operating-points-v2"; 2211 2212 /* GEN 1 x1 */ 2213 opp-2500000 { 2214 opp-hz = /bits/ 64 <2500000>; 2215 required-opps = <&rpmhpd_opp_low_svs>; 2216 opp-peak-kBps = <250000 1>; 2217 }; 2218 2219 /* GEN 1 x2 and GEN 2 x1 */ 2220 opp-5000000 { 2221 opp-hz = /bits/ 64 <5000000>; 2222 required-opps = <&rpmhpd_opp_low_svs>; 2223 opp-peak-kBps = <500000 1>; 2224 }; 2225 2226 /* GEN 2 x2 */ 2227 opp-10000000 { 2228 opp-hz = /bits/ 64 <10000000>; 2229 required-opps = <&rpmhpd_opp_low_svs>; 2230 opp-peak-kBps = <1000000 1>; 2231 }; 2232 2233 /* GEN 3 x1 */ 2234 opp-8000000 { 2235 opp-hz = /bits/ 64 <8000000>; 2236 required-opps = <&rpmhpd_opp_nom>; 2237 opp-peak-kBps = <984500 1>; 2238 }; 2239 2240 /* GEN 3 x2 and GEN 4 x1 */ 2241 opp-16000000 { 2242 opp-hz = /bits/ 64 <16000000>; 2243 required-opps = <&rpmhpd_opp_nom>; 2244 opp-peak-kBps = <1969000 1>; 2245 }; 2246 2247 /* GEN 4 x2 */ 2248 opp-32000000 { 2249 opp-hz = /bits/ 64 <32000000>; 2250 required-opps = <&rpmhpd_opp_nom>; 2251 opp-peak-kBps = <3938000 1>; 2252 }; 2253 }; 2254 2255 pcie@0 { 2256 device_type = "pci"; 2257 reg = <0x0 0x0 0x0 0x0 0x0>; 2258 bus-range = <0x01 0xff>; 2259 2260 #address-cells = <3>; 2261 #size-cells = <2>; 2262 ranges; 2263 }; 2264 }; 2265 2266 pcie1_ep: pcie-ep@1c08000 { 2267 compatible = "qcom,sm8450-pcie-ep"; 2268 reg = <0x0 0x01c08000 0x0 0x3000>, 2269 <0x0 0x40000000 0x0 0xf1d>, 2270 <0x0 0x40000f20 0x0 0xa8>, 2271 <0x0 0x40001000 0x0 0x1000>, 2272 <0x0 0x40200000 0x0 0x1000000>, 2273 <0x0 0x01c0b000 0x0 0x1000>, 2274 <0x0 0x40002000 0x0 0x1000>; 2275 reg-names = "parf", 2276 "dbi", 2277 "elbi", 2278 "atu", 2279 "addr_space", 2280 "mmio", 2281 "dma"; 2282 2283 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2284 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2285 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2286 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2287 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2288 <&rpmhcc RPMH_CXO_CLK>, 2289 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2290 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2291 clock-names = "aux", 2292 "cfg", 2293 "bus_master", 2294 "bus_slave", 2295 "slave_q2a", 2296 "ref", 2297 "ddrss_sf_tbu", 2298 "aggre_noc_axi"; 2299 2300 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 2301 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 2302 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 2303 interrupt-names = "global", 2304 "doorbell", 2305 "dma"; 2306 2307 interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS 2308 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2309 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2310 &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2311 interconnect-names = "pcie-mem", 2312 "cpu-pcie"; 2313 2314 iommus = <&apps_smmu 0x1c80 0x7f>; 2315 resets = <&gcc GCC_PCIE_1_BCR>; 2316 reset-names = "core"; 2317 power-domains = <&gcc PCIE_1_GDSC>; 2318 phys = <&pcie1_phy>; 2319 phy-names = "pciephy"; 2320 num-lanes = <2>; 2321 2322 pinctrl-names = "default"; 2323 pinctrl-0 = <&pcie1_default_state>; 2324 2325 status = "disabled"; 2326 }; 2327 2328 pcie1_phy: phy@1c0e000 { 2329 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy"; 2330 reg = <0 0x01c0e000 0 0x2000>; 2331 2332 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 2333 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2334 <&gcc GCC_PCIE_1_CLKREF_EN>, 2335 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 2336 <&gcc GCC_PCIE_1_PIPE_CLK>; 2337 clock-names = "aux", 2338 "cfg_ahb", 2339 "ref", 2340 "rchng", 2341 "pipe"; 2342 2343 clock-output-names = "pcie_1_pipe_clk"; 2344 #clock-cells = <1>; 2345 2346 #phy-cells = <0>; 2347 2348 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2349 reset-names = "phy"; 2350 2351 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 2352 assigned-clock-rates = <100000000>; 2353 2354 status = "disabled"; 2355 }; 2356 2357 config_noc: interconnect@1500000 { 2358 compatible = "qcom,sm8450-config-noc"; 2359 reg = <0 0x01500000 0 0x1c000>; 2360 #interconnect-cells = <2>; 2361 qcom,bcm-voters = <&apps_bcm_voter>; 2362 }; 2363 2364 system_noc: interconnect@1680000 { 2365 compatible = "qcom,sm8450-system-noc"; 2366 reg = <0 0x01680000 0 0x1e200>; 2367 #interconnect-cells = <2>; 2368 qcom,bcm-voters = <&apps_bcm_voter>; 2369 }; 2370 2371 pcie_noc: interconnect@16c0000 { 2372 compatible = "qcom,sm8450-pcie-anoc"; 2373 reg = <0 0x016c0000 0 0xe280>; 2374 #interconnect-cells = <2>; 2375 qcom,bcm-voters = <&apps_bcm_voter>; 2376 }; 2377 2378 aggre1_noc: interconnect@16e0000 { 2379 compatible = "qcom,sm8450-aggre1-noc"; 2380 reg = <0 0x016e0000 0 0x1c080>; 2381 #interconnect-cells = <2>; 2382 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2383 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 2384 qcom,bcm-voters = <&apps_bcm_voter>; 2385 }; 2386 2387 aggre2_noc: interconnect@1700000 { 2388 compatible = "qcom,sm8450-aggre2-noc"; 2389 reg = <0 0x01700000 0 0x31080>; 2390 #interconnect-cells = <2>; 2391 qcom,bcm-voters = <&apps_bcm_voter>; 2392 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 2393 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 2394 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2395 <&rpmhcc RPMH_IPA_CLK>; 2396 }; 2397 2398 mmss_noc: interconnect@1740000 { 2399 compatible = "qcom,sm8450-mmss-noc"; 2400 reg = <0 0x01740000 0 0x1f080>; 2401 #interconnect-cells = <2>; 2402 qcom,bcm-voters = <&apps_bcm_voter>; 2403 }; 2404 2405 tcsr_mutex: hwlock@1f40000 { 2406 compatible = "qcom,tcsr-mutex"; 2407 reg = <0x0 0x01f40000 0x0 0x40000>; 2408 #hwlock-cells = <1>; 2409 }; 2410 2411 tcsr: syscon@1fc0000 { 2412 compatible = "qcom,sm8450-tcsr", "syscon"; 2413 reg = <0x0 0x1fc0000 0x0 0x30000>; 2414 }; 2415 2416 gpu: gpu@3d00000 { 2417 compatible = "qcom,adreno-730.1", "qcom,adreno"; 2418 reg = <0x0 0x03d00000 0x0 0x40000>, 2419 <0x0 0x03d9e000 0x0 0x1000>, 2420 <0x0 0x03d61000 0x0 0x800>; 2421 reg-names = "kgsl_3d0_reg_memory", 2422 "cx_mem", 2423 "cx_dbgc"; 2424 2425 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2426 2427 iommus = <&adreno_smmu 0 0x400>, 2428 <&adreno_smmu 1 0x400>; 2429 2430 operating-points-v2 = <&gpu_opp_table>; 2431 2432 qcom,gmu = <&gmu>; 2433 #cooling-cells = <2>; 2434 2435 status = "disabled"; 2436 2437 zap-shader { 2438 memory-region = <&gpu_micro_code_mem>; 2439 }; 2440 2441 gpu_opp_table: opp-table { 2442 compatible = "operating-points-v2"; 2443 2444 opp-818000000 { 2445 opp-hz = /bits/ 64 <818000000>; 2446 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2447 }; 2448 2449 opp-791000000 { 2450 opp-hz = /bits/ 64 <791000000>; 2451 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2452 }; 2453 2454 opp-734000000 { 2455 opp-hz = /bits/ 64 <734000000>; 2456 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2457 }; 2458 2459 opp-640000000 { 2460 opp-hz = /bits/ 64 <640000000>; 2461 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2462 }; 2463 2464 opp-599000000 { 2465 opp-hz = /bits/ 64 <599000000>; 2466 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2467 }; 2468 2469 opp-545000000 { 2470 opp-hz = /bits/ 64 <545000000>; 2471 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2472 }; 2473 2474 opp-492000000 { 2475 opp-hz = /bits/ 64 <492000000>; 2476 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2477 }; 2478 2479 opp-421000000 { 2480 opp-hz = /bits/ 64 <421000000>; 2481 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 2482 }; 2483 2484 opp-350000000 { 2485 opp-hz = /bits/ 64 <350000000>; 2486 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2487 }; 2488 2489 opp-317000000 { 2490 opp-hz = /bits/ 64 <317000000>; 2491 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2492 }; 2493 2494 opp-285000000 { 2495 opp-hz = /bits/ 64 <285000000>; 2496 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 2497 }; 2498 2499 opp-220000000 { 2500 opp-hz = /bits/ 64 <220000000>; 2501 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 2502 }; 2503 }; 2504 }; 2505 2506 gmu: gmu@3d6a000 { 2507 compatible = "qcom,adreno-gmu-730.1", "qcom,adreno-gmu"; 2508 reg = <0x0 0x03d6a000 0x0 0x35000>, 2509 <0x0 0x03d50000 0x0 0x10000>, 2510 <0x0 0x0b290000 0x0 0x10000>; 2511 reg-names = "gmu", "rscc", "gmu_pdc"; 2512 2513 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2514 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2515 interrupt-names = "hfi", "gmu"; 2516 2517 clocks = <&gpucc GPU_CC_AHB_CLK>, 2518 <&gpucc GPU_CC_CX_GMU_CLK>, 2519 <&gpucc GPU_CC_CXO_CLK>, 2520 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2521 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2522 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2523 <&gpucc GPU_CC_DEMET_CLK>; 2524 clock-names = "ahb", 2525 "gmu", 2526 "cxo", 2527 "axi", 2528 "memnoc", 2529 "hub", 2530 "demet"; 2531 2532 power-domains = <&gpucc GPU_CX_GDSC>, 2533 <&gpucc GPU_GX_GDSC>; 2534 power-domain-names = "cx", 2535 "gx"; 2536 2537 iommus = <&adreno_smmu 5 0x400>; 2538 2539 qcom,qmp = <&aoss_qmp>; 2540 2541 operating-points-v2 = <&gmu_opp_table>; 2542 2543 gmu_opp_table: opp-table { 2544 compatible = "operating-points-v2"; 2545 2546 opp-500000000 { 2547 opp-hz = /bits/ 64 <500000000>; 2548 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2549 }; 2550 2551 opp-200000000 { 2552 opp-hz = /bits/ 64 <200000000>; 2553 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2554 }; 2555 }; 2556 }; 2557 2558 gpucc: clock-controller@3d90000 { 2559 compatible = "qcom,sm8450-gpucc"; 2560 reg = <0x0 0x03d90000 0x0 0xa000>; 2561 clocks = <&rpmhcc RPMH_CXO_CLK>, 2562 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2563 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2564 #clock-cells = <1>; 2565 #reset-cells = <1>; 2566 #power-domain-cells = <1>; 2567 }; 2568 2569 adreno_smmu: iommu@3da0000 { 2570 compatible = "qcom,sm8450-smmu-500", "qcom,adreno-smmu", 2571 "qcom,smmu-500", "arm,mmu-500"; 2572 reg = <0x0 0x03da0000 0x0 0x40000>; 2573 #iommu-cells = <2>; 2574 #global-interrupts = <1>; 2575 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2576 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2577 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2578 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2579 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2580 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2581 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2582 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2583 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2584 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2585 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2586 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2587 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 2588 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, 2589 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, 2590 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 2591 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, 2592 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>, 2593 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>, 2594 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>, 2595 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 2596 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 2597 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>, 2598 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 2599 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>, 2600 <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>; 2601 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2602 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2603 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2604 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2605 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2606 <&gpucc GPU_CC_AHB_CLK>; 2607 clock-names = "gmu", 2608 "hub", 2609 "hlos", 2610 "bus", 2611 "iface", 2612 "ahb"; 2613 power-domains = <&gpucc GPU_CX_GDSC>; 2614 dma-coherent; 2615 }; 2616 2617 usb_1_hsphy: phy@88e3000 { 2618 compatible = "qcom,sm8450-usb-hs-phy", 2619 "qcom,usb-snps-hs-7nm-phy"; 2620 reg = <0 0x088e3000 0 0x400>; 2621 status = "disabled"; 2622 #phy-cells = <0>; 2623 2624 clocks = <&rpmhcc RPMH_CXO_CLK>; 2625 clock-names = "ref"; 2626 2627 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2628 }; 2629 2630 usb_1_qmpphy: phy@88e8000 { 2631 compatible = "qcom,sm8450-qmp-usb3-dp-phy"; 2632 reg = <0 0x088e8000 0 0x3000>; 2633 2634 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2635 <&rpmhcc RPMH_CXO_CLK>, 2636 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2637 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2638 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2639 2640 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2641 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2642 reset-names = "phy", "common"; 2643 2644 #clock-cells = <1>; 2645 #phy-cells = <1>; 2646 2647 orientation-switch; 2648 2649 status = "disabled"; 2650 2651 ports { 2652 #address-cells = <1>; 2653 #size-cells = <0>; 2654 2655 port@0 { 2656 reg = <0>; 2657 2658 usb_1_qmpphy_out: endpoint { 2659 }; 2660 }; 2661 2662 port@1 { 2663 reg = <1>; 2664 2665 usb_1_qmpphy_usb_ss_in: endpoint { 2666 remote-endpoint = <&usb_1_dwc3_ss>; 2667 }; 2668 }; 2669 2670 port@2 { 2671 reg = <2>; 2672 2673 usb_1_qmpphy_dp_in: endpoint { 2674 remote-endpoint = <&mdss_dp0_out>; 2675 }; 2676 }; 2677 }; 2678 }; 2679 2680 remoteproc_slpi: remoteproc@2400000 { 2681 compatible = "qcom,sm8450-slpi-pas"; 2682 reg = <0 0x02400000 0 0x4000>; 2683 2684 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2685 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2686 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2687 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2688 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2689 interrupt-names = "wdog", "fatal", "ready", 2690 "handover", "stop-ack"; 2691 2692 clocks = <&rpmhcc RPMH_CXO_CLK>; 2693 clock-names = "xo"; 2694 2695 power-domains = <&rpmhpd RPMHPD_LCX>, 2696 <&rpmhpd RPMHPD_LMX>; 2697 power-domain-names = "lcx", "lmx"; 2698 2699 memory-region = <&slpi_mem>; 2700 2701 qcom,qmp = <&aoss_qmp>; 2702 2703 qcom,smem-states = <&smp2p_slpi_out 0>; 2704 qcom,smem-state-names = "stop"; 2705 2706 status = "disabled"; 2707 2708 glink-edge { 2709 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2710 IPCC_MPROC_SIGNAL_GLINK_QMP 2711 IRQ_TYPE_EDGE_RISING>; 2712 mboxes = <&ipcc IPCC_CLIENT_SLPI 2713 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2714 2715 label = "slpi"; 2716 qcom,remote-pid = <3>; 2717 2718 fastrpc { 2719 compatible = "qcom,fastrpc"; 2720 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2721 label = "sdsp"; 2722 qcom,non-secure-domain; 2723 #address-cells = <1>; 2724 #size-cells = <0>; 2725 2726 compute-cb@1 { 2727 compatible = "qcom,fastrpc-compute-cb"; 2728 reg = <1>; 2729 iommus = <&apps_smmu 0x0541 0x0>; 2730 }; 2731 2732 compute-cb@2 { 2733 compatible = "qcom,fastrpc-compute-cb"; 2734 reg = <2>; 2735 iommus = <&apps_smmu 0x0542 0x0>; 2736 }; 2737 2738 compute-cb@3 { 2739 compatible = "qcom,fastrpc-compute-cb"; 2740 reg = <3>; 2741 iommus = <&apps_smmu 0x0543 0x0>; 2742 /* note: shared-cb = <4> in downstream */ 2743 }; 2744 }; 2745 }; 2746 }; 2747 2748 remoteproc_adsp: remoteproc@3000000 { 2749 compatible = "qcom,sm8450-adsp-pas"; 2750 reg = <0x0 0x03000000 0x0 0x10000>; 2751 2752 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2753 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2754 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2755 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2756 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2757 interrupt-names = "wdog", "fatal", "ready", 2758 "handover", "stop-ack"; 2759 2760 clocks = <&rpmhcc RPMH_CXO_CLK>; 2761 clock-names = "xo"; 2762 2763 power-domains = <&rpmhpd RPMHPD_LCX>, 2764 <&rpmhpd RPMHPD_LMX>; 2765 power-domain-names = "lcx", "lmx"; 2766 2767 memory-region = <&adsp_mem>; 2768 2769 qcom,qmp = <&aoss_qmp>; 2770 2771 qcom,smem-states = <&smp2p_adsp_out 0>; 2772 qcom,smem-state-names = "stop"; 2773 2774 status = "disabled"; 2775 2776 remoteproc_adsp_glink: glink-edge { 2777 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2778 IPCC_MPROC_SIGNAL_GLINK_QMP 2779 IRQ_TYPE_EDGE_RISING>; 2780 mboxes = <&ipcc IPCC_CLIENT_LPASS 2781 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2782 2783 label = "lpass"; 2784 qcom,remote-pid = <2>; 2785 2786 gpr { 2787 compatible = "qcom,gpr"; 2788 qcom,glink-channels = "adsp_apps"; 2789 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2790 qcom,intents = <512 20>; 2791 #address-cells = <1>; 2792 #size-cells = <0>; 2793 2794 q6apm: service@1 { 2795 compatible = "qcom,q6apm"; 2796 reg = <GPR_APM_MODULE_IID>; 2797 #sound-dai-cells = <0>; 2798 qcom,protection-domain = "avs/audio", 2799 "msm/adsp/audio_pd"; 2800 2801 q6apmdai: dais { 2802 compatible = "qcom,q6apm-dais"; 2803 iommus = <&apps_smmu 0x1801 0x0>; 2804 }; 2805 2806 q6apmbedai: bedais { 2807 compatible = "qcom,q6apm-lpass-dais"; 2808 #sound-dai-cells = <1>; 2809 }; 2810 }; 2811 2812 q6prm: service@2 { 2813 compatible = "qcom,q6prm"; 2814 reg = <GPR_PRM_MODULE_IID>; 2815 qcom,protection-domain = "avs/audio", 2816 "msm/adsp/audio_pd"; 2817 2818 q6prmcc: clock-controller { 2819 compatible = "qcom,q6prm-lpass-clocks"; 2820 #clock-cells = <2>; 2821 }; 2822 }; 2823 }; 2824 2825 fastrpc { 2826 compatible = "qcom,fastrpc"; 2827 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2828 label = "adsp"; 2829 qcom,non-secure-domain; 2830 #address-cells = <1>; 2831 #size-cells = <0>; 2832 2833 compute-cb@3 { 2834 compatible = "qcom,fastrpc-compute-cb"; 2835 reg = <3>; 2836 iommus = <&apps_smmu 0x1803 0x0>; 2837 }; 2838 2839 compute-cb@4 { 2840 compatible = "qcom,fastrpc-compute-cb"; 2841 reg = <4>; 2842 iommus = <&apps_smmu 0x1804 0x0>; 2843 }; 2844 2845 compute-cb@5 { 2846 compatible = "qcom,fastrpc-compute-cb"; 2847 reg = <5>; 2848 iommus = <&apps_smmu 0x1805 0x0>; 2849 }; 2850 }; 2851 }; 2852 }; 2853 2854 wsa2macro: codec@31e0000 { 2855 compatible = "qcom,sm8450-lpass-wsa-macro"; 2856 reg = <0 0x031e0000 0 0x1000>; 2857 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2858 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2859 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2860 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2861 <&vamacro>; 2862 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2863 2864 #clock-cells = <0>; 2865 clock-output-names = "wsa2-mclk"; 2866 #sound-dai-cells = <1>; 2867 }; 2868 2869 swr4: soundwire@31f0000 { 2870 compatible = "qcom,soundwire-v1.7.0"; 2871 reg = <0 0x031f0000 0 0x2000>; 2872 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2873 clocks = <&wsa2macro>; 2874 clock-names = "iface"; 2875 label = "WSA2"; 2876 2877 pinctrl-0 = <&wsa2_swr_active>; 2878 pinctrl-names = "default"; 2879 2880 qcom,din-ports = <2>; 2881 qcom,dout-ports = <6>; 2882 2883 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2884 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2885 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2886 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2887 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2888 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2889 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2890 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2891 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2892 2893 #address-cells = <2>; 2894 #size-cells = <0>; 2895 #sound-dai-cells = <1>; 2896 status = "disabled"; 2897 }; 2898 2899 rxmacro: codec@3200000 { 2900 compatible = "qcom,sm8450-lpass-rx-macro"; 2901 reg = <0 0x03200000 0 0x1000>; 2902 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2903 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2904 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2905 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2906 <&vamacro>; 2907 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2908 2909 #clock-cells = <0>; 2910 clock-output-names = "mclk"; 2911 #sound-dai-cells = <1>; 2912 }; 2913 2914 swr1: soundwire@3210000 { 2915 compatible = "qcom,soundwire-v1.7.0"; 2916 reg = <0 0x03210000 0 0x2000>; 2917 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2918 clocks = <&rxmacro>; 2919 clock-names = "iface"; 2920 label = "RX"; 2921 qcom,din-ports = <0>; 2922 qcom,dout-ports = <5>; 2923 2924 pinctrl-0 = <&rx_swr_active>; 2925 pinctrl-names = "default"; 2926 2927 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2928 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; 2929 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2930 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2931 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2932 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2933 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2934 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2935 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2936 2937 #address-cells = <2>; 2938 #size-cells = <0>; 2939 #sound-dai-cells = <1>; 2940 status = "disabled"; 2941 }; 2942 2943 txmacro: codec@3220000 { 2944 compatible = "qcom,sm8450-lpass-tx-macro"; 2945 reg = <0 0x03220000 0 0x1000>; 2946 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2947 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2948 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2949 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2950 <&vamacro>; 2951 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2952 2953 #clock-cells = <0>; 2954 clock-output-names = "mclk"; 2955 #sound-dai-cells = <1>; 2956 }; 2957 2958 wsamacro: codec@3240000 { 2959 compatible = "qcom,sm8450-lpass-wsa-macro"; 2960 reg = <0 0x03240000 0 0x1000>; 2961 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2962 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2963 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2964 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2965 <&vamacro>; 2966 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2967 2968 #clock-cells = <0>; 2969 clock-output-names = "mclk"; 2970 #sound-dai-cells = <1>; 2971 }; 2972 2973 swr0: soundwire@3250000 { 2974 compatible = "qcom,soundwire-v1.7.0"; 2975 reg = <0 0x03250000 0 0x2000>; 2976 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2977 clocks = <&wsamacro>; 2978 clock-names = "iface"; 2979 label = "WSA"; 2980 2981 pinctrl-0 = <&wsa_swr_active>; 2982 pinctrl-names = "default"; 2983 2984 qcom,din-ports = <2>; 2985 qcom,dout-ports = <6>; 2986 2987 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2988 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2989 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2990 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2991 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2992 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2993 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2994 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2995 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2996 2997 #address-cells = <2>; 2998 #size-cells = <0>; 2999 #sound-dai-cells = <1>; 3000 status = "disabled"; 3001 }; 3002 3003 swr2: soundwire@33b0000 { 3004 compatible = "qcom,soundwire-v1.7.0"; 3005 reg = <0 0x033b0000 0 0x2000>; 3006 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 3007 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 3008 interrupt-names = "core", "wakeup"; 3009 3010 clocks = <&txmacro>; 3011 clock-names = "iface"; 3012 label = "TX"; 3013 3014 pinctrl-0 = <&tx_swr_active>; 3015 pinctrl-names = "default"; 3016 3017 qcom,din-ports = <4>; 3018 qcom,dout-ports = <0>; 3019 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 3020 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 3021 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 3022 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 3023 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 3024 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 3025 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 3026 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 3027 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 3028 3029 #address-cells = <2>; 3030 #size-cells = <0>; 3031 #sound-dai-cells = <1>; 3032 status = "disabled"; 3033 }; 3034 3035 vamacro: codec@33f0000 { 3036 compatible = "qcom,sm8450-lpass-va-macro"; 3037 reg = <0 0x033f0000 0 0x1000>; 3038 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3039 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3040 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3041 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3042 clock-names = "mclk", "macro", "dcodec", "npl"; 3043 3044 #clock-cells = <0>; 3045 clock-output-names = "fsgen"; 3046 #sound-dai-cells = <1>; 3047 status = "disabled"; 3048 }; 3049 3050 remoteproc_cdsp: remoteproc@32300000 { 3051 compatible = "qcom,sm8450-cdsp-pas"; 3052 reg = <0 0x32300000 0 0x10000>; 3053 3054 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3055 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3056 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3057 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3058 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3059 interrupt-names = "wdog", "fatal", "ready", 3060 "handover", "stop-ack"; 3061 3062 clocks = <&rpmhcc RPMH_CXO_CLK>; 3063 clock-names = "xo"; 3064 3065 power-domains = <&rpmhpd RPMHPD_CX>, 3066 <&rpmhpd RPMHPD_MXC>; 3067 power-domain-names = "cx", "mxc"; 3068 3069 memory-region = <&cdsp_mem>; 3070 3071 qcom,qmp = <&aoss_qmp>; 3072 3073 qcom,smem-states = <&smp2p_cdsp_out 0>; 3074 qcom,smem-state-names = "stop"; 3075 3076 status = "disabled"; 3077 3078 glink-edge { 3079 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3080 IPCC_MPROC_SIGNAL_GLINK_QMP 3081 IRQ_TYPE_EDGE_RISING>; 3082 mboxes = <&ipcc IPCC_CLIENT_CDSP 3083 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3084 3085 label = "cdsp"; 3086 qcom,remote-pid = <5>; 3087 3088 fastrpc { 3089 compatible = "qcom,fastrpc"; 3090 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3091 label = "cdsp"; 3092 qcom,non-secure-domain; 3093 #address-cells = <1>; 3094 #size-cells = <0>; 3095 3096 compute-cb@1 { 3097 compatible = "qcom,fastrpc-compute-cb"; 3098 reg = <1>; 3099 iommus = <&apps_smmu 0x2161 0x0400>, 3100 <&apps_smmu 0x1021 0x1420>; 3101 }; 3102 3103 compute-cb@2 { 3104 compatible = "qcom,fastrpc-compute-cb"; 3105 reg = <2>; 3106 iommus = <&apps_smmu 0x2162 0x0400>, 3107 <&apps_smmu 0x1022 0x1420>; 3108 }; 3109 3110 compute-cb@3 { 3111 compatible = "qcom,fastrpc-compute-cb"; 3112 reg = <3>; 3113 iommus = <&apps_smmu 0x2163 0x0400>, 3114 <&apps_smmu 0x1023 0x1420>; 3115 }; 3116 3117 compute-cb@4 { 3118 compatible = "qcom,fastrpc-compute-cb"; 3119 reg = <4>; 3120 iommus = <&apps_smmu 0x2164 0x0400>, 3121 <&apps_smmu 0x1024 0x1420>; 3122 }; 3123 3124 compute-cb@5 { 3125 compatible = "qcom,fastrpc-compute-cb"; 3126 reg = <5>; 3127 iommus = <&apps_smmu 0x2165 0x0400>, 3128 <&apps_smmu 0x1025 0x1420>; 3129 }; 3130 3131 compute-cb@6 { 3132 compatible = "qcom,fastrpc-compute-cb"; 3133 reg = <6>; 3134 iommus = <&apps_smmu 0x2166 0x0400>, 3135 <&apps_smmu 0x1026 0x1420>; 3136 }; 3137 3138 compute-cb@7 { 3139 compatible = "qcom,fastrpc-compute-cb"; 3140 reg = <7>; 3141 iommus = <&apps_smmu 0x2167 0x0400>, 3142 <&apps_smmu 0x1027 0x1420>; 3143 }; 3144 3145 compute-cb@8 { 3146 compatible = "qcom,fastrpc-compute-cb"; 3147 reg = <8>; 3148 iommus = <&apps_smmu 0x2168 0x0400>, 3149 <&apps_smmu 0x1028 0x1420>; 3150 }; 3151 3152 /* note: secure cb9 in downstream */ 3153 }; 3154 }; 3155 }; 3156 3157 remoteproc_mpss: remoteproc@4080000 { 3158 compatible = "qcom,sm8450-mpss-pas"; 3159 reg = <0x0 0x04080000 0x0 0x10000>; 3160 3161 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 3162 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 3163 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 3164 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 3165 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 3166 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 3167 interrupt-names = "wdog", "fatal", "ready", "handover", 3168 "stop-ack", "shutdown-ack"; 3169 3170 clocks = <&rpmhcc RPMH_CXO_CLK>; 3171 clock-names = "xo"; 3172 3173 power-domains = <&rpmhpd RPMHPD_CX>, 3174 <&rpmhpd RPMHPD_MSS>; 3175 power-domain-names = "cx", "mss"; 3176 3177 memory-region = <&mpss_mem>; 3178 3179 qcom,qmp = <&aoss_qmp>; 3180 3181 qcom,smem-states = <&smp2p_modem_out 0>; 3182 qcom,smem-state-names = "stop"; 3183 3184 status = "disabled"; 3185 3186 glink-edge { 3187 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 3188 IPCC_MPROC_SIGNAL_GLINK_QMP 3189 IRQ_TYPE_EDGE_RISING>; 3190 mboxes = <&ipcc IPCC_CLIENT_MPSS 3191 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3192 label = "modem"; 3193 qcom,remote-pid = <1>; 3194 }; 3195 }; 3196 3197 videocc: clock-controller@aaf0000 { 3198 compatible = "qcom,sm8450-videocc"; 3199 reg = <0 0x0aaf0000 0 0x10000>; 3200 clocks = <&rpmhcc RPMH_CXO_CLK>, 3201 <&gcc GCC_VIDEO_AHB_CLK>; 3202 power-domains = <&rpmhpd RPMHPD_MMCX>, 3203 <&rpmhpd RPMHPD_MXC>; 3204 required-opps = <&rpmhpd_opp_low_svs>, 3205 <&rpmhpd_opp_low_svs>; 3206 #clock-cells = <1>; 3207 #reset-cells = <1>; 3208 #power-domain-cells = <1>; 3209 }; 3210 3211 cci0: cci@ac15000 { 3212 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; 3213 reg = <0 0x0ac15000 0 0x1000>; 3214 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 3215 power-domains = <&camcc TITAN_TOP_GDSC>; 3216 3217 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3218 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3219 <&camcc CAM_CC_CPAS_AHB_CLK>, 3220 <&camcc CAM_CC_CCI_0_CLK>, 3221 <&camcc CAM_CC_CCI_0_CLK_SRC>; 3222 clock-names = "camnoc_axi", 3223 "slow_ahb_src", 3224 "cpas_ahb", 3225 "cci", 3226 "cci_src"; 3227 pinctrl-0 = <&cci0_default &cci1_default>; 3228 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 3229 pinctrl-names = "default", "sleep"; 3230 3231 status = "disabled"; 3232 #address-cells = <1>; 3233 #size-cells = <0>; 3234 3235 cci0_i2c0: i2c-bus@0 { 3236 reg = <0>; 3237 clock-frequency = <1000000>; 3238 #address-cells = <1>; 3239 #size-cells = <0>; 3240 }; 3241 3242 cci0_i2c1: i2c-bus@1 { 3243 reg = <1>; 3244 clock-frequency = <1000000>; 3245 #address-cells = <1>; 3246 #size-cells = <0>; 3247 }; 3248 }; 3249 3250 cci1: cci@ac16000 { 3251 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; 3252 reg = <0 0x0ac16000 0 0x1000>; 3253 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 3254 power-domains = <&camcc TITAN_TOP_GDSC>; 3255 3256 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3257 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3258 <&camcc CAM_CC_CPAS_AHB_CLK>, 3259 <&camcc CAM_CC_CCI_1_CLK>, 3260 <&camcc CAM_CC_CCI_1_CLK_SRC>; 3261 clock-names = "camnoc_axi", 3262 "slow_ahb_src", 3263 "cpas_ahb", 3264 "cci", 3265 "cci_src"; 3266 pinctrl-0 = <&cci2_default &cci3_default>; 3267 pinctrl-1 = <&cci2_sleep &cci3_sleep>; 3268 pinctrl-names = "default", "sleep"; 3269 3270 status = "disabled"; 3271 #address-cells = <1>; 3272 #size-cells = <0>; 3273 3274 cci1_i2c0: i2c-bus@0 { 3275 reg = <0>; 3276 clock-frequency = <1000000>; 3277 #address-cells = <1>; 3278 #size-cells = <0>; 3279 }; 3280 3281 cci1_i2c1: i2c-bus@1 { 3282 reg = <1>; 3283 clock-frequency = <1000000>; 3284 #address-cells = <1>; 3285 #size-cells = <0>; 3286 }; 3287 }; 3288 3289 camcc: clock-controller@ade0000 { 3290 compatible = "qcom,sm8450-camcc"; 3291 reg = <0 0x0ade0000 0 0x20000>; 3292 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 3293 <&rpmhcc RPMH_CXO_CLK>, 3294 <&rpmhcc RPMH_CXO_CLK_A>, 3295 <&sleep_clk>; 3296 power-domains = <&rpmhpd RPMHPD_MMCX>, 3297 <&rpmhpd RPMHPD_MXC>; 3298 required-opps = <&rpmhpd_opp_low_svs>, 3299 <&rpmhpd_opp_low_svs>; 3300 #clock-cells = <1>; 3301 #reset-cells = <1>; 3302 #power-domain-cells = <1>; 3303 }; 3304 3305 mdss: display-subsystem@ae00000 { 3306 compatible = "qcom,sm8450-mdss"; 3307 reg = <0 0x0ae00000 0 0x1000>; 3308 reg-names = "mdss"; 3309 3310 /* same path used twice */ 3311 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, 3312 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, 3313 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3314 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 3315 interconnect-names = "mdp0-mem", 3316 "mdp1-mem", 3317 "cpu-cfg"; 3318 3319 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 3320 3321 power-domains = <&dispcc MDSS_GDSC>; 3322 3323 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3324 <&gcc GCC_DISP_HF_AXI_CLK>, 3325 <&gcc GCC_DISP_SF_AXI_CLK>, 3326 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3327 3328 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3329 interrupt-controller; 3330 #interrupt-cells = <1>; 3331 3332 iommus = <&apps_smmu 0x2800 0x402>; 3333 3334 #address-cells = <2>; 3335 #size-cells = <2>; 3336 ranges; 3337 3338 status = "disabled"; 3339 3340 mdss_mdp: display-controller@ae01000 { 3341 compatible = "qcom,sm8450-dpu"; 3342 reg = <0 0x0ae01000 0 0x8f000>, 3343 <0 0x0aeb0000 0 0x3000>; 3344 reg-names = "mdp", "vbif"; 3345 3346 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3347 <&gcc GCC_DISP_SF_AXI_CLK>, 3348 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3349 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3350 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3351 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3352 clock-names = "bus", 3353 "nrt_bus", 3354 "iface", 3355 "lut", 3356 "core", 3357 "vsync"; 3358 3359 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3360 assigned-clock-rates = <19200000>; 3361 3362 operating-points-v2 = <&mdp_opp_table>; 3363 power-domains = <&rpmhpd RPMHPD_MMCX>; 3364 3365 interrupt-parent = <&mdss>; 3366 interrupts = <0>; 3367 3368 ports { 3369 #address-cells = <1>; 3370 #size-cells = <0>; 3371 3372 port@0 { 3373 reg = <0>; 3374 dpu_intf1_out: endpoint { 3375 remote-endpoint = <&mdss_dsi0_in>; 3376 }; 3377 }; 3378 3379 port@1 { 3380 reg = <1>; 3381 dpu_intf2_out: endpoint { 3382 remote-endpoint = <&mdss_dsi1_in>; 3383 }; 3384 }; 3385 3386 port@2 { 3387 reg = <2>; 3388 dpu_intf0_out: endpoint { 3389 remote-endpoint = <&mdss_dp0_in>; 3390 }; 3391 }; 3392 }; 3393 3394 mdp_opp_table: opp-table { 3395 compatible = "operating-points-v2"; 3396 3397 opp-172000000 { 3398 opp-hz = /bits/ 64 <172000000>; 3399 required-opps = <&rpmhpd_opp_low_svs_d1>; 3400 }; 3401 3402 opp-200000000 { 3403 opp-hz = /bits/ 64 <200000000>; 3404 required-opps = <&rpmhpd_opp_low_svs>; 3405 }; 3406 3407 opp-325000000 { 3408 opp-hz = /bits/ 64 <325000000>; 3409 required-opps = <&rpmhpd_opp_svs>; 3410 }; 3411 3412 opp-375000000 { 3413 opp-hz = /bits/ 64 <375000000>; 3414 required-opps = <&rpmhpd_opp_svs_l1>; 3415 }; 3416 3417 opp-500000000 { 3418 opp-hz = /bits/ 64 <500000000>; 3419 required-opps = <&rpmhpd_opp_nom>; 3420 }; 3421 }; 3422 }; 3423 3424 mdss_dp0: displayport-controller@ae90000 { 3425 compatible = "qcom,sm8450-dp", "qcom,sm8350-dp"; 3426 reg = <0 0xae90000 0 0x200>, 3427 <0 0xae90200 0 0x200>, 3428 <0 0xae90400 0 0xc00>, 3429 <0 0xae91000 0 0x400>, 3430 <0 0xae91400 0 0x400>; 3431 interrupt-parent = <&mdss>; 3432 interrupts = <12>; 3433 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3434 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 3435 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 3436 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 3437 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 3438 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; 3439 clock-names = "core_iface", 3440 "core_aux", 3441 "ctrl_link", 3442 "ctrl_link_iface", 3443 "stream_pixel", 3444 "stream_1_pixel"; 3445 3446 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 3447 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 3448 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; 3449 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3450 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3451 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3452 3453 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 3454 phy-names = "dp"; 3455 3456 #sound-dai-cells = <0>; 3457 3458 operating-points-v2 = <&dp_opp_table>; 3459 power-domains = <&rpmhpd RPMHPD_MMCX>; 3460 3461 status = "disabled"; 3462 3463 ports { 3464 #address-cells = <1>; 3465 #size-cells = <0>; 3466 3467 port@0 { 3468 reg = <0>; 3469 mdss_dp0_in: endpoint { 3470 remote-endpoint = <&dpu_intf0_out>; 3471 }; 3472 }; 3473 3474 port@1 { 3475 reg = <1>; 3476 3477 mdss_dp0_out: endpoint { 3478 remote-endpoint = <&usb_1_qmpphy_dp_in>; 3479 }; 3480 }; 3481 }; 3482 3483 dp_opp_table: opp-table { 3484 compatible = "operating-points-v2"; 3485 3486 opp-160000000 { 3487 opp-hz = /bits/ 64 <160000000>; 3488 required-opps = <&rpmhpd_opp_low_svs>; 3489 }; 3490 3491 opp-270000000 { 3492 opp-hz = /bits/ 64 <270000000>; 3493 required-opps = <&rpmhpd_opp_svs>; 3494 }; 3495 3496 opp-540000000 { 3497 opp-hz = /bits/ 64 <540000000>; 3498 required-opps = <&rpmhpd_opp_svs_l1>; 3499 }; 3500 3501 opp-810000000 { 3502 opp-hz = /bits/ 64 <810000000>; 3503 required-opps = <&rpmhpd_opp_nom>; 3504 }; 3505 }; 3506 }; 3507 3508 mdss_dsi0: dsi@ae94000 { 3509 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3510 reg = <0 0x0ae94000 0 0x400>; 3511 reg-names = "dsi_ctrl"; 3512 3513 interrupt-parent = <&mdss>; 3514 interrupts = <4>; 3515 3516 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3517 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3518 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3519 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3520 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3521 <&gcc GCC_DISP_HF_AXI_CLK>; 3522 clock-names = "byte", 3523 "byte_intf", 3524 "pixel", 3525 "core", 3526 "iface", 3527 "bus"; 3528 3529 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 3530 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3531 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 3532 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 3533 3534 operating-points-v2 = <&mdss_dsi_opp_table>; 3535 power-domains = <&rpmhpd RPMHPD_MMCX>; 3536 3537 phys = <&mdss_dsi0_phy>; 3538 phy-names = "dsi"; 3539 3540 #address-cells = <1>; 3541 #size-cells = <0>; 3542 3543 status = "disabled"; 3544 3545 ports { 3546 #address-cells = <1>; 3547 #size-cells = <0>; 3548 3549 port@0 { 3550 reg = <0>; 3551 mdss_dsi0_in: endpoint { 3552 remote-endpoint = <&dpu_intf1_out>; 3553 }; 3554 }; 3555 3556 port@1 { 3557 reg = <1>; 3558 mdss_dsi0_out: endpoint { 3559 }; 3560 }; 3561 }; 3562 3563 mdss_dsi_opp_table: opp-table { 3564 compatible = "operating-points-v2"; 3565 3566 opp-187500000 { 3567 opp-hz = /bits/ 64 <187500000>; 3568 required-opps = <&rpmhpd_opp_low_svs>; 3569 }; 3570 3571 opp-300000000 { 3572 opp-hz = /bits/ 64 <300000000>; 3573 required-opps = <&rpmhpd_opp_svs>; 3574 }; 3575 3576 opp-358000000 { 3577 opp-hz = /bits/ 64 <358000000>; 3578 required-opps = <&rpmhpd_opp_svs_l1>; 3579 }; 3580 }; 3581 }; 3582 3583 mdss_dsi0_phy: phy@ae94400 { 3584 compatible = "qcom,sm8450-dsi-phy-5nm"; 3585 reg = <0 0x0ae94400 0 0x200>, 3586 <0 0x0ae94600 0 0x280>, 3587 <0 0x0ae94900 0 0x260>; 3588 reg-names = "dsi_phy", 3589 "dsi_phy_lane", 3590 "dsi_pll"; 3591 3592 #clock-cells = <1>; 3593 #phy-cells = <0>; 3594 3595 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3596 <&rpmhcc RPMH_CXO_CLK>; 3597 clock-names = "iface", "ref"; 3598 3599 status = "disabled"; 3600 }; 3601 3602 mdss_dsi1: dsi@ae96000 { 3603 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3604 reg = <0 0x0ae96000 0 0x400>; 3605 reg-names = "dsi_ctrl"; 3606 3607 interrupt-parent = <&mdss>; 3608 interrupts = <5>; 3609 3610 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3611 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3612 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3613 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3614 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3615 <&gcc GCC_DISP_HF_AXI_CLK>; 3616 clock-names = "byte", 3617 "byte_intf", 3618 "pixel", 3619 "core", 3620 "iface", 3621 "bus"; 3622 3623 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 3624 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3625 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 3626 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 3627 3628 operating-points-v2 = <&mdss_dsi_opp_table>; 3629 power-domains = <&rpmhpd RPMHPD_MMCX>; 3630 3631 phys = <&mdss_dsi1_phy>; 3632 phy-names = "dsi"; 3633 3634 #address-cells = <1>; 3635 #size-cells = <0>; 3636 3637 status = "disabled"; 3638 3639 ports { 3640 #address-cells = <1>; 3641 #size-cells = <0>; 3642 3643 port@0 { 3644 reg = <0>; 3645 mdss_dsi1_in: endpoint { 3646 remote-endpoint = <&dpu_intf2_out>; 3647 }; 3648 }; 3649 3650 port@1 { 3651 reg = <1>; 3652 mdss_dsi1_out: endpoint { 3653 }; 3654 }; 3655 }; 3656 }; 3657 3658 mdss_dsi1_phy: phy@ae96400 { 3659 compatible = "qcom,sm8450-dsi-phy-5nm"; 3660 reg = <0 0x0ae96400 0 0x200>, 3661 <0 0x0ae96600 0 0x280>, 3662 <0 0x0ae96900 0 0x260>; 3663 reg-names = "dsi_phy", 3664 "dsi_phy_lane", 3665 "dsi_pll"; 3666 3667 #clock-cells = <1>; 3668 #phy-cells = <0>; 3669 3670 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3671 <&rpmhcc RPMH_CXO_CLK>; 3672 clock-names = "iface", "ref"; 3673 3674 status = "disabled"; 3675 }; 3676 }; 3677 3678 dispcc: clock-controller@af00000 { 3679 compatible = "qcom,sm8450-dispcc"; 3680 reg = <0 0x0af00000 0 0x20000>; 3681 clocks = <&rpmhcc RPMH_CXO_CLK>, 3682 <&rpmhcc RPMH_CXO_CLK_A>, 3683 <&gcc GCC_DISP_AHB_CLK>, 3684 <&sleep_clk>, 3685 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 3686 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 3687 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 3688 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 3689 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3690 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3691 <0>, /* dp1 */ 3692 <0>, 3693 <0>, /* dp2 */ 3694 <0>, 3695 <0>, /* dp3 */ 3696 <0>; 3697 power-domains = <&rpmhpd RPMHPD_MMCX>; 3698 required-opps = <&rpmhpd_opp_low_svs>; 3699 #clock-cells = <1>; 3700 #reset-cells = <1>; 3701 #power-domain-cells = <1>; 3702 }; 3703 3704 pdc: interrupt-controller@b220000 { 3705 compatible = "qcom,sm8450-pdc", "qcom,pdc"; 3706 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 3707 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, 3708 <94 609 31>, <125 63 1>, <126 716 12>; 3709 #interrupt-cells = <2>; 3710 interrupt-parent = <&intc>; 3711 interrupt-controller; 3712 }; 3713 3714 tsens0: thermal-sensor@c263000 { 3715 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 3716 reg = <0 0x0c263000 0 0x1000>, /* TM */ 3717 <0 0x0c222000 0 0x1000>; /* SROT */ 3718 #qcom,sensors = <16>; 3719 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3720 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3721 interrupt-names = "uplow", "critical"; 3722 #thermal-sensor-cells = <1>; 3723 }; 3724 3725 tsens1: thermal-sensor@c265000 { 3726 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 3727 reg = <0 0x0c265000 0 0x1000>, /* TM */ 3728 <0 0x0c223000 0 0x1000>; /* SROT */ 3729 #qcom,sensors = <16>; 3730 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3731 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3732 interrupt-names = "uplow", "critical"; 3733 #thermal-sensor-cells = <1>; 3734 }; 3735 3736 aoss_qmp: power-management@c300000 { 3737 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; 3738 reg = <0 0x0c300000 0 0x400>; 3739 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 3740 IRQ_TYPE_EDGE_RISING>; 3741 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3742 3743 #clock-cells = <0>; 3744 }; 3745 3746 sram@c3f0000 { 3747 compatible = "qcom,rpmh-stats"; 3748 reg = <0 0x0c3f0000 0 0x400>; 3749 qcom,qmp = <&aoss_qmp>; 3750 }; 3751 3752 spmi_bus: spmi@c400000 { 3753 compatible = "qcom,spmi-pmic-arb"; 3754 reg = <0 0x0c400000 0 0x00003000>, 3755 <0 0x0c500000 0 0x00400000>, 3756 <0 0x0c440000 0 0x00080000>, 3757 <0 0x0c4c0000 0 0x00010000>, 3758 <0 0x0c42d000 0 0x00010000>; 3759 reg-names = "core", 3760 "chnls", 3761 "obsrvr", 3762 "intr", 3763 "cnfg"; 3764 interrupt-names = "periph_irq"; 3765 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3766 qcom,ee = <0>; 3767 qcom,channel = <0>; 3768 interrupt-controller; 3769 #interrupt-cells = <4>; 3770 #address-cells = <2>; 3771 #size-cells = <0>; 3772 }; 3773 3774 ipcc: mailbox@ed18000 { 3775 compatible = "qcom,sm8450-ipcc", "qcom,ipcc"; 3776 reg = <0 0x0ed18000 0 0x1000>; 3777 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 3778 interrupt-controller; 3779 #interrupt-cells = <3>; 3780 #mbox-cells = <2>; 3781 }; 3782 3783 tlmm: pinctrl@f100000 { 3784 compatible = "qcom,sm8450-tlmm"; 3785 reg = <0 0x0f100000 0 0x300000>; 3786 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3787 gpio-controller; 3788 #gpio-cells = <2>; 3789 interrupt-controller; 3790 #interrupt-cells = <2>; 3791 gpio-ranges = <&tlmm 0 0 211>; 3792 wakeup-parent = <&pdc>; 3793 3794 sdc2_default_state: sdc2-default-state { 3795 clk-pins { 3796 pins = "sdc2_clk"; 3797 drive-strength = <16>; 3798 bias-disable; 3799 }; 3800 3801 cmd-pins { 3802 pins = "sdc2_cmd"; 3803 drive-strength = <16>; 3804 bias-pull-up; 3805 }; 3806 3807 data-pins { 3808 pins = "sdc2_data"; 3809 drive-strength = <16>; 3810 bias-pull-up; 3811 }; 3812 }; 3813 3814 sdc2_sleep_state: sdc2-sleep-state { 3815 clk-pins { 3816 pins = "sdc2_clk"; 3817 drive-strength = <2>; 3818 bias-disable; 3819 }; 3820 3821 cmd-pins { 3822 pins = "sdc2_cmd"; 3823 drive-strength = <2>; 3824 bias-pull-up; 3825 }; 3826 3827 data-pins { 3828 pins = "sdc2_data"; 3829 drive-strength = <2>; 3830 bias-pull-up; 3831 }; 3832 }; 3833 3834 cci0_default: cci0-default-state { 3835 /* SDA, SCL */ 3836 pins = "gpio110", "gpio111"; 3837 function = "cci_i2c"; 3838 drive-strength = <2>; 3839 bias-pull-up; 3840 }; 3841 3842 cci0_sleep: cci0-sleep-state { 3843 /* SDA, SCL */ 3844 pins = "gpio110", "gpio111"; 3845 function = "cci_i2c"; 3846 drive-strength = <2>; 3847 bias-pull-down; 3848 }; 3849 3850 cci1_default: cci1-default-state { 3851 /* SDA, SCL */ 3852 pins = "gpio112", "gpio113"; 3853 function = "cci_i2c"; 3854 drive-strength = <2>; 3855 bias-pull-up; 3856 }; 3857 3858 cci1_sleep: cci1-sleep-state { 3859 /* SDA, SCL */ 3860 pins = "gpio112", "gpio113"; 3861 function = "cci_i2c"; 3862 drive-strength = <2>; 3863 bias-pull-down; 3864 }; 3865 3866 cci2_default: cci2-default-state { 3867 /* SDA, SCL */ 3868 pins = "gpio114", "gpio115"; 3869 function = "cci_i2c"; 3870 drive-strength = <2>; 3871 bias-pull-up; 3872 }; 3873 3874 cci2_sleep: cci2-sleep-state { 3875 /* SDA, SCL */ 3876 pins = "gpio114", "gpio115"; 3877 function = "cci_i2c"; 3878 drive-strength = <2>; 3879 bias-pull-down; 3880 }; 3881 3882 cci3_default: cci3-default-state { 3883 /* SDA, SCL */ 3884 pins = "gpio208", "gpio209"; 3885 function = "cci_i2c"; 3886 drive-strength = <2>; 3887 bias-pull-up; 3888 }; 3889 3890 cci3_sleep: cci3-sleep-state { 3891 /* SDA, SCL */ 3892 pins = "gpio208", "gpio209"; 3893 function = "cci_i2c"; 3894 drive-strength = <2>; 3895 bias-pull-down; 3896 }; 3897 3898 pcie0_default_state: pcie0-default-state { 3899 perst-pins { 3900 pins = "gpio94"; 3901 function = "gpio"; 3902 drive-strength = <2>; 3903 bias-pull-down; 3904 }; 3905 3906 clkreq-pins { 3907 pins = "gpio95"; 3908 function = "pcie0_clkreqn"; 3909 drive-strength = <2>; 3910 bias-pull-up; 3911 }; 3912 3913 wake-pins { 3914 pins = "gpio96"; 3915 function = "gpio"; 3916 drive-strength = <2>; 3917 bias-pull-up; 3918 }; 3919 }; 3920 3921 pcie1_default_state: pcie1-default-state { 3922 perst-pins { 3923 pins = "gpio97"; 3924 function = "gpio"; 3925 drive-strength = <2>; 3926 bias-pull-down; 3927 }; 3928 3929 clkreq-pins { 3930 pins = "gpio98"; 3931 function = "pcie1_clkreqn"; 3932 drive-strength = <2>; 3933 bias-pull-up; 3934 }; 3935 3936 wake-pins { 3937 pins = "gpio99"; 3938 function = "gpio"; 3939 drive-strength = <2>; 3940 bias-pull-up; 3941 }; 3942 }; 3943 3944 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 3945 pins = "gpio0", "gpio1"; 3946 function = "qup0"; 3947 }; 3948 3949 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 3950 pins = "gpio4", "gpio5"; 3951 function = "qup1"; 3952 }; 3953 3954 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 3955 pins = "gpio8", "gpio9"; 3956 function = "qup2"; 3957 }; 3958 3959 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 3960 pins = "gpio12", "gpio13"; 3961 function = "qup3"; 3962 }; 3963 3964 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 3965 pins = "gpio16", "gpio17"; 3966 function = "qup4"; 3967 }; 3968 3969 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 3970 pins = "gpio206", "gpio207"; 3971 function = "qup5"; 3972 }; 3973 3974 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 3975 pins = "gpio20", "gpio21"; 3976 function = "qup6"; 3977 }; 3978 3979 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 3980 pins = "gpio28", "gpio29"; 3981 function = "qup8"; 3982 }; 3983 3984 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 3985 pins = "gpio32", "gpio33"; 3986 function = "qup9"; 3987 }; 3988 3989 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 3990 pins = "gpio36", "gpio37"; 3991 function = "qup10"; 3992 }; 3993 3994 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 3995 pins = "gpio40", "gpio41"; 3996 function = "qup11"; 3997 }; 3998 3999 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4000 pins = "gpio44", "gpio45"; 4001 function = "qup12"; 4002 }; 4003 4004 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4005 pins = "gpio48", "gpio49"; 4006 function = "qup13"; 4007 drive-strength = <2>; 4008 bias-pull-up; 4009 }; 4010 4011 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 4012 pins = "gpio52", "gpio53"; 4013 function = "qup14"; 4014 drive-strength = <2>; 4015 bias-pull-up; 4016 }; 4017 4018 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4019 pins = "gpio56", "gpio57"; 4020 function = "qup15"; 4021 }; 4022 4023 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 4024 pins = "gpio60", "gpio61"; 4025 function = "qup16"; 4026 }; 4027 4028 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 4029 pins = "gpio64", "gpio65"; 4030 function = "qup17"; 4031 }; 4032 4033 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 4034 pins = "gpio68", "gpio69"; 4035 function = "qup18"; 4036 }; 4037 4038 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 4039 pins = "gpio72", "gpio73"; 4040 function = "qup19"; 4041 }; 4042 4043 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 4044 pins = "gpio76", "gpio77"; 4045 function = "qup20"; 4046 }; 4047 4048 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 4049 pins = "gpio80", "gpio81"; 4050 function = "qup21"; 4051 }; 4052 4053 qup_spi0_cs: qup-spi0-cs-state { 4054 pins = "gpio3"; 4055 function = "qup0"; 4056 }; 4057 4058 qup_spi0_data_clk: qup-spi0-data-clk-state { 4059 pins = "gpio0", "gpio1", "gpio2"; 4060 function = "qup0"; 4061 }; 4062 4063 qup_spi1_cs: qup-spi1-cs-state { 4064 pins = "gpio7"; 4065 function = "qup1"; 4066 }; 4067 4068 qup_spi1_data_clk: qup-spi1-data-clk-state { 4069 pins = "gpio4", "gpio5", "gpio6"; 4070 function = "qup1"; 4071 }; 4072 4073 qup_spi2_cs: qup-spi2-cs-state { 4074 pins = "gpio11"; 4075 function = "qup2"; 4076 }; 4077 4078 qup_spi2_data_clk: qup-spi2-data-clk-state { 4079 pins = "gpio8", "gpio9", "gpio10"; 4080 function = "qup2"; 4081 }; 4082 4083 qup_spi3_cs: qup-spi3-cs-state { 4084 pins = "gpio15"; 4085 function = "qup3"; 4086 }; 4087 4088 qup_spi3_data_clk: qup-spi3-data-clk-state { 4089 pins = "gpio12", "gpio13", "gpio14"; 4090 function = "qup3"; 4091 }; 4092 4093 qup_spi4_cs: qup-spi4-cs-state { 4094 pins = "gpio19"; 4095 function = "qup4"; 4096 drive-strength = <6>; 4097 bias-disable; 4098 }; 4099 4100 qup_spi4_data_clk: qup-spi4-data-clk-state { 4101 pins = "gpio16", "gpio17", "gpio18"; 4102 function = "qup4"; 4103 }; 4104 4105 qup_spi5_cs: qup-spi5-cs-state { 4106 pins = "gpio85"; 4107 function = "qup5"; 4108 }; 4109 4110 qup_spi5_data_clk: qup-spi5-data-clk-state { 4111 pins = "gpio206", "gpio207", "gpio84"; 4112 function = "qup5"; 4113 }; 4114 4115 qup_spi6_cs: qup-spi6-cs-state { 4116 pins = "gpio23"; 4117 function = "qup6"; 4118 }; 4119 4120 qup_spi6_data_clk: qup-spi6-data-clk-state { 4121 pins = "gpio20", "gpio21", "gpio22"; 4122 function = "qup6"; 4123 }; 4124 4125 qup_spi8_cs: qup-spi8-cs-state { 4126 pins = "gpio31"; 4127 function = "qup8"; 4128 }; 4129 4130 qup_spi8_data_clk: qup-spi8-data-clk-state { 4131 pins = "gpio28", "gpio29", "gpio30"; 4132 function = "qup8"; 4133 }; 4134 4135 qup_spi9_cs: qup-spi9-cs-state { 4136 pins = "gpio35"; 4137 function = "qup9"; 4138 }; 4139 4140 qup_spi9_data_clk: qup-spi9-data-clk-state { 4141 pins = "gpio32", "gpio33", "gpio34"; 4142 function = "qup9"; 4143 }; 4144 4145 qup_spi10_cs: qup-spi10-cs-state { 4146 pins = "gpio39"; 4147 function = "qup10"; 4148 }; 4149 4150 qup_spi10_data_clk: qup-spi10-data-clk-state { 4151 pins = "gpio36", "gpio37", "gpio38"; 4152 function = "qup10"; 4153 }; 4154 4155 qup_spi11_cs: qup-spi11-cs-state { 4156 pins = "gpio43"; 4157 function = "qup11"; 4158 }; 4159 4160 qup_spi11_data_clk: qup-spi11-data-clk-state { 4161 pins = "gpio40", "gpio41", "gpio42"; 4162 function = "qup11"; 4163 }; 4164 4165 qup_spi12_cs: qup-spi12-cs-state { 4166 pins = "gpio47"; 4167 function = "qup12"; 4168 }; 4169 4170 qup_spi12_data_clk: qup-spi12-data-clk-state { 4171 pins = "gpio44", "gpio45", "gpio46"; 4172 function = "qup12"; 4173 }; 4174 4175 qup_spi13_cs: qup-spi13-cs-state { 4176 pins = "gpio51"; 4177 function = "qup13"; 4178 }; 4179 4180 qup_spi13_data_clk: qup-spi13-data-clk-state { 4181 pins = "gpio48", "gpio49", "gpio50"; 4182 function = "qup13"; 4183 }; 4184 4185 qup_spi14_cs: qup-spi14-cs-state { 4186 pins = "gpio55"; 4187 function = "qup14"; 4188 }; 4189 4190 qup_spi14_data_clk: qup-spi14-data-clk-state { 4191 pins = "gpio52", "gpio53", "gpio54"; 4192 function = "qup14"; 4193 }; 4194 4195 qup_spi15_cs: qup-spi15-cs-state { 4196 pins = "gpio59"; 4197 function = "qup15"; 4198 }; 4199 4200 qup_spi15_data_clk: qup-spi15-data-clk-state { 4201 pins = "gpio56", "gpio57", "gpio58"; 4202 function = "qup15"; 4203 }; 4204 4205 qup_spi16_cs: qup-spi16-cs-state { 4206 pins = "gpio63"; 4207 function = "qup16"; 4208 }; 4209 4210 qup_spi16_data_clk: qup-spi16-data-clk-state { 4211 pins = "gpio60", "gpio61", "gpio62"; 4212 function = "qup16"; 4213 }; 4214 4215 qup_spi17_cs: qup-spi17-cs-state { 4216 pins = "gpio67"; 4217 function = "qup17"; 4218 }; 4219 4220 qup_spi17_data_clk: qup-spi17-data-clk-state { 4221 pins = "gpio64", "gpio65", "gpio66"; 4222 function = "qup17"; 4223 }; 4224 4225 qup_spi18_cs: qup-spi18-cs-state { 4226 pins = "gpio71"; 4227 function = "qup18"; 4228 drive-strength = <6>; 4229 bias-disable; 4230 }; 4231 4232 qup_spi18_data_clk: qup-spi18-data-clk-state { 4233 pins = "gpio68", "gpio69", "gpio70"; 4234 function = "qup18"; 4235 drive-strength = <6>; 4236 bias-disable; 4237 }; 4238 4239 qup_spi19_cs: qup-spi19-cs-state { 4240 pins = "gpio75"; 4241 function = "qup19"; 4242 drive-strength = <6>; 4243 bias-disable; 4244 }; 4245 4246 qup_spi19_data_clk: qup-spi19-data-clk-state { 4247 pins = "gpio72", "gpio73", "gpio74"; 4248 function = "qup19"; 4249 drive-strength = <6>; 4250 bias-disable; 4251 }; 4252 4253 qup_spi20_cs: qup-spi20-cs-state { 4254 pins = "gpio79"; 4255 function = "qup20"; 4256 }; 4257 4258 qup_spi20_data_clk: qup-spi20-data-clk-state { 4259 pins = "gpio76", "gpio77", "gpio78"; 4260 function = "qup20"; 4261 }; 4262 4263 qup_spi21_cs: qup-spi21-cs-state { 4264 pins = "gpio83"; 4265 function = "qup21"; 4266 }; 4267 4268 qup_spi21_data_clk: qup-spi21-data-clk-state { 4269 pins = "gpio80", "gpio81", "gpio82"; 4270 function = "qup21"; 4271 }; 4272 4273 qup_uart7_rx: qup-uart7-rx-state { 4274 pins = "gpio26"; 4275 function = "qup7"; 4276 drive-strength = <2>; 4277 bias-disable; 4278 }; 4279 4280 qup_uart7_tx: qup-uart7-tx-state { 4281 pins = "gpio27"; 4282 function = "qup7"; 4283 drive-strength = <2>; 4284 bias-disable; 4285 }; 4286 4287 qup_uart20_default: qup-uart20-default-state { 4288 pins = "gpio76", "gpio77", "gpio78", "gpio79"; 4289 function = "qup20"; 4290 }; 4291 }; 4292 4293 lpass_tlmm: pinctrl@3440000 { 4294 compatible = "qcom,sm8450-lpass-lpi-pinctrl"; 4295 reg = <0 0x03440000 0x0 0x20000>, 4296 <0 0x034d0000 0x0 0x10000>; 4297 gpio-controller; 4298 #gpio-cells = <2>; 4299 gpio-ranges = <&lpass_tlmm 0 0 23>; 4300 4301 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4302 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 4303 clock-names = "core", "audio"; 4304 4305 tx_swr_active: tx-swr-active-state { 4306 clk-pins { 4307 pins = "gpio0"; 4308 function = "swr_tx_clk"; 4309 drive-strength = <2>; 4310 slew-rate = <1>; 4311 bias-disable; 4312 }; 4313 4314 data-pins { 4315 pins = "gpio1", "gpio2", "gpio14"; 4316 function = "swr_tx_data"; 4317 drive-strength = <2>; 4318 slew-rate = <1>; 4319 bias-bus-hold; 4320 }; 4321 }; 4322 4323 rx_swr_active: rx-swr-active-state { 4324 clk-pins { 4325 pins = "gpio3"; 4326 function = "swr_rx_clk"; 4327 drive-strength = <2>; 4328 slew-rate = <1>; 4329 bias-disable; 4330 }; 4331 4332 data-pins { 4333 pins = "gpio4", "gpio5"; 4334 function = "swr_rx_data"; 4335 drive-strength = <2>; 4336 slew-rate = <1>; 4337 bias-bus-hold; 4338 }; 4339 }; 4340 4341 dmic01_default: dmic01-default-state { 4342 clk-pins { 4343 pins = "gpio6"; 4344 function = "dmic1_clk"; 4345 drive-strength = <8>; 4346 output-high; 4347 }; 4348 4349 data-pins { 4350 pins = "gpio7"; 4351 function = "dmic1_data"; 4352 drive-strength = <8>; 4353 }; 4354 }; 4355 4356 dmic23_default: dmic23-default-state { 4357 clk-pins { 4358 pins = "gpio8"; 4359 function = "dmic2_clk"; 4360 drive-strength = <8>; 4361 output-high; 4362 }; 4363 4364 data-pins { 4365 pins = "gpio9"; 4366 function = "dmic2_data"; 4367 drive-strength = <8>; 4368 }; 4369 }; 4370 4371 wsa_swr_active: wsa-swr-active-state { 4372 clk-pins { 4373 pins = "gpio10"; 4374 function = "wsa_swr_clk"; 4375 drive-strength = <2>; 4376 slew-rate = <1>; 4377 bias-disable; 4378 }; 4379 4380 data-pins { 4381 pins = "gpio11"; 4382 function = "wsa_swr_data"; 4383 drive-strength = <2>; 4384 slew-rate = <1>; 4385 bias-bus-hold; 4386 }; 4387 }; 4388 4389 wsa2_swr_active: wsa2-swr-active-state { 4390 clk-pins { 4391 pins = "gpio15"; 4392 function = "wsa2_swr_clk"; 4393 drive-strength = <2>; 4394 slew-rate = <1>; 4395 bias-disable; 4396 }; 4397 4398 data-pins { 4399 pins = "gpio16"; 4400 function = "wsa2_swr_data"; 4401 drive-strength = <2>; 4402 slew-rate = <1>; 4403 bias-bus-hold; 4404 }; 4405 }; 4406 }; 4407 4408 stm@10002000 { 4409 compatible = "arm,coresight-stm", "arm,primecell"; 4410 reg = <0x0 0x10002000 0x0 0x1000>, 4411 <0x0 0x16280000 0x0 0x180000>; 4412 reg-names = "stm-base", "stm-stimulus-base"; 4413 4414 clocks = <&aoss_qmp>; 4415 clock-names = "apb_pclk"; 4416 4417 out-ports { 4418 port { 4419 stm_out_funnel_in0: endpoint { 4420 remote-endpoint = 4421 <&funnel_in0_in_stm>; 4422 }; 4423 }; 4424 }; 4425 }; 4426 4427 funnel@10041000 { 4428 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4429 reg = <0x0 0x10041000 0x0 0x1000>; 4430 4431 clocks = <&aoss_qmp>; 4432 clock-names = "apb_pclk"; 4433 4434 in-ports { 4435 #address-cells = <1>; 4436 #size-cells = <0>; 4437 4438 port@7 { 4439 reg = <7>; 4440 funnel_in0_in_stm: endpoint { 4441 remote-endpoint = 4442 <&stm_out_funnel_in0>; 4443 }; 4444 }; 4445 }; 4446 4447 out-ports { 4448 port { 4449 funnel_in0_out_funnel_qdss: endpoint { 4450 remote-endpoint = 4451 <&funnel_qdss_in_funnel_in0>; 4452 }; 4453 }; 4454 }; 4455 }; 4456 4457 funnel@10042000 { 4458 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4459 4460 reg = <0x0 0x10042000 0x0 0x1000>; 4461 4462 clocks = <&aoss_qmp>; 4463 clock-names = "apb_pclk"; 4464 4465 in-ports { 4466 #address-cells = <1>; 4467 #size-cells = <0>; 4468 4469 port@4 { 4470 reg = <4>; 4471 funnel_in1_in_funnel_apss: endpoint { 4472 remote-endpoint = 4473 <&funnel_apss_out_funnel_in1>; 4474 }; 4475 }; 4476 4477 port@6 { 4478 reg = <6>; 4479 funnel_in1_in_funnel_dl_center: endpoint { 4480 remote-endpoint = 4481 <&funnel_dl_center_out_funnel_in1>; 4482 }; 4483 }; 4484 }; 4485 4486 out-ports { 4487 port { 4488 funnel_in1_out_funnel_qdss: endpoint { 4489 remote-endpoint = 4490 <&funnel_qdss_in_funnel_in1>; 4491 }; 4492 }; 4493 }; 4494 }; 4495 4496 funnel@10045000 { 4497 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4498 reg = <0x0 0x10045000 0x0 0x1000>; 4499 4500 clocks = <&aoss_qmp>; 4501 clock-names = "apb_pclk"; 4502 4503 in-ports { 4504 #address-cells = <1>; 4505 #size-cells = <0>; 4506 4507 port@0 { 4508 reg = <0>; 4509 funnel_qdss_in_funnel_in0: endpoint { 4510 remote-endpoint = 4511 <&funnel_in0_out_funnel_qdss>; 4512 }; 4513 }; 4514 4515 port@1 { 4516 reg = <1>; 4517 funnel_qdss_in_funnel_in1: endpoint { 4518 remote-endpoint = 4519 <&funnel_in1_out_funnel_qdss>; 4520 }; 4521 }; 4522 }; 4523 4524 out-ports { 4525 port { 4526 funnel_qdss_out_funnel_aoss: endpoint { 4527 remote-endpoint = 4528 <&funnel_aoss_in_funnel_qdss>; 4529 }; 4530 }; 4531 }; 4532 }; 4533 4534 replicator@10046000 { 4535 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 4536 reg = <0x0 0x10046000 0x0 0x1000>; 4537 4538 clocks = <&aoss_qmp>; 4539 clock-names = "apb_pclk"; 4540 4541 in-ports { 4542 port { 4543 replicator_qdss_in_replicator_swao: endpoint { 4544 remote-endpoint = 4545 <&replicator_swao_out_replicator_qdss>; 4546 }; 4547 }; 4548 }; 4549 4550 out-ports { 4551 4552 port { 4553 replicator_qdss_out_replicator_etr: endpoint { 4554 remote-endpoint = 4555 <&replicator_etr_in_replicator_qdss>; 4556 }; 4557 }; 4558 }; 4559 }; 4560 4561 tmc_etr: tmc@10048000 { 4562 compatible = "arm,coresight-tmc", "arm,primecell"; 4563 reg = <0x0 0x10048000 0x0 0x1000>; 4564 4565 iommus = <&apps_smmu 0x0600 0>; 4566 arm,buffer-size = <0x10000>; 4567 4568 arm,scatter-gather; 4569 clocks = <&aoss_qmp>; 4570 clock-names = "apb_pclk"; 4571 4572 in-ports { 4573 port { 4574 tmc_etr_in_replicator_etr: endpoint { 4575 remote-endpoint = 4576 <&replicator_etr_out_tmc_etr>; 4577 }; 4578 }; 4579 }; 4580 }; 4581 4582 replicator@1004e000 { 4583 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 4584 reg = <0x0 0x1004e000 0x0 0x1000>; 4585 4586 clocks = <&aoss_qmp>; 4587 clock-names = "apb_pclk"; 4588 4589 in-ports { 4590 port { 4591 replicator_etr_in_replicator_qdss: endpoint { 4592 remote-endpoint = 4593 <&replicator_qdss_out_replicator_etr>; 4594 }; 4595 }; 4596 }; 4597 4598 out-ports { 4599 4600 port { 4601 4602 replicator_etr_out_tmc_etr: endpoint { 4603 remote-endpoint = 4604 <&tmc_etr_in_replicator_etr>; 4605 }; 4606 }; 4607 }; 4608 }; 4609 4610 funnel@10b04000 { 4611 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4612 4613 reg = <0x0 0x10b04000 0x0 0x1000>; 4614 4615 clocks = <&aoss_qmp>; 4616 clock-names = "apb_pclk"; 4617 4618 in-ports { 4619 #address-cells = <1>; 4620 #size-cells = <0>; 4621 4622 port@6 { 4623 reg = <6>; 4624 funnel_aoss_in_tpda_aoss: endpoint { 4625 remote-endpoint = 4626 <&tpda_aoss_out_funnel_aoss>; 4627 }; 4628 }; 4629 4630 port@7 { 4631 reg = <7>; 4632 funnel_aoss_in_funnel_qdss: endpoint { 4633 remote-endpoint = 4634 <&funnel_qdss_out_funnel_aoss>; 4635 }; 4636 }; 4637 }; 4638 4639 out-ports { 4640 port { 4641 funnel_aoss_out_tmc_etf: endpoint { 4642 remote-endpoint = 4643 <&tmc_etf_in_funnel_aoss>; 4644 }; 4645 }; 4646 }; 4647 }; 4648 4649 tmc@10b05000 { 4650 compatible = "arm,coresight-tmc", "arm,primecell"; 4651 reg = <0x0 0x10b05000 0x0 0x1000>; 4652 4653 clocks = <&aoss_qmp>; 4654 clock-names = "apb_pclk"; 4655 4656 in-ports { 4657 port { 4658 tmc_etf_in_funnel_aoss: endpoint { 4659 remote-endpoint = 4660 <&funnel_aoss_out_tmc_etf>; 4661 }; 4662 }; 4663 }; 4664 4665 out-ports { 4666 port { 4667 tmc_etf_out_replicator_swao: endpoint { 4668 remote-endpoint = 4669 <&replicator_swao_in_tmc_etf>; 4670 }; 4671 }; 4672 }; 4673 }; 4674 4675 replicator@10b06000 { 4676 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 4677 reg = <0x0 0x10b06000 0x0 0x1000>; 4678 4679 qcom,replicator-loses-context; 4680 clocks = <&aoss_qmp>; 4681 clock-names = "apb_pclk"; 4682 4683 in-ports { 4684 port { 4685 replicator_swao_in_tmc_etf: endpoint { 4686 remote-endpoint = 4687 <&tmc_etf_out_replicator_swao>; 4688 }; 4689 }; 4690 }; 4691 4692 out-ports { 4693 4694 port { 4695 replicator_swao_out_replicator_qdss: endpoint { 4696 remote-endpoint = 4697 <&replicator_qdss_in_replicator_swao>; 4698 }; 4699 }; 4700 }; 4701 }; 4702 4703 tpda@10b08000 { 4704 compatible = "qcom,coresight-tpda", "arm,primecell"; 4705 4706 reg = <0x0 0x10b08000 0x0 0x1000>; 4707 4708 clocks = <&aoss_qmp>; 4709 clock-names = "apb_pclk"; 4710 4711 in-ports { 4712 4713 #address-cells = <1>; 4714 #size-cells = <0>; 4715 4716 port@0 { 4717 reg = <0>; 4718 tpda_aoss_in_tpdm_swao_prio_0: endpoint { 4719 remote-endpoint = 4720 <&tpdm_swao_prio_0_out_tpda_aoss>; 4721 }; 4722 }; 4723 4724 port@4 { 4725 reg = <4>; 4726 tpda_aoss_in_tpdm_swao: endpoint { 4727 remote-endpoint = 4728 <&tpdm_swao_out_tpda_aoss>; 4729 }; 4730 }; 4731 }; 4732 4733 out-ports { 4734 4735 port { 4736 tpda_aoss_out_funnel_aoss: endpoint { 4737 remote-endpoint = 4738 <&funnel_aoss_in_tpda_aoss>; 4739 }; 4740 }; 4741 }; 4742 }; 4743 4744 tpdm@10b09000 { 4745 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4746 reg = <0x0 0x10b09000 0x0 0x1000>; 4747 4748 4749 clocks = <&aoss_qmp>; 4750 clock-names = "apb_pclk"; 4751 4752 out-ports { 4753 port { 4754 tpdm_swao_prio_0_out_tpda_aoss: endpoint { 4755 remote-endpoint = 4756 <&tpda_aoss_in_tpdm_swao_prio_0>; 4757 }; 4758 }; 4759 }; 4760 }; 4761 4762 tpdm@10b0d000 { 4763 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4764 reg = <0x0 0x10b0d000 0x0 0x1000>; 4765 4766 clocks = <&aoss_qmp>; 4767 clock-names = "apb_pclk"; 4768 4769 out-ports { 4770 port { 4771 tpdm_swao_out_tpda_aoss: endpoint { 4772 remote-endpoint = 4773 <&tpda_aoss_in_tpdm_swao>; 4774 }; 4775 }; 4776 }; 4777 }; 4778 4779 tpdm@10c28000 { 4780 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4781 reg = <0x0 0x10c28000 0x0 0x1000>; 4782 4783 clocks = <&aoss_qmp>; 4784 clock-names = "apb_pclk"; 4785 4786 out-ports { 4787 port { 4788 tpdm_dlct_out_tpda_dl_center_26: endpoint { 4789 remote-endpoint = 4790 <&tpda_dl_center_26_in_tpdm_dlct>; 4791 }; 4792 }; 4793 }; 4794 }; 4795 4796 tpdm@10c29000 { 4797 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4798 reg = <0x0 0x10c29000 0x0 0x1000>; 4799 4800 clocks = <&aoss_qmp>; 4801 clock-names = "apb_pclk"; 4802 4803 out-ports { 4804 port { 4805 tpdm_ipcc_out_tpda_dl_center_27: endpoint { 4806 remote-endpoint = 4807 <&tpda_dl_center_27_in_tpdm_ipcc>; 4808 }; 4809 }; 4810 }; 4811 }; 4812 4813 cti@10c2a000 { 4814 compatible = "arm,coresight-cti", "arm,primecell"; 4815 reg = <0x0 0x10c2a000 0x0 0x1000>; 4816 4817 clocks = <&aoss_qmp>; 4818 clock-names = "apb_pclk"; 4819 }; 4820 4821 cti@10c2b000 { 4822 compatible = "arm,coresight-cti", "arm,primecell"; 4823 reg = <0x0 0x10c2b000 0x0 0x1000>; 4824 4825 clocks = <&aoss_qmp>; 4826 clock-names = "apb_pclk"; 4827 }; 4828 4829 tpda@10c2e000 { 4830 compatible = "qcom,coresight-tpda", "arm,primecell"; 4831 reg = <0x0 0x10c2e000 0x0 0x1000>; 4832 4833 clocks = <&aoss_qmp>; 4834 clock-names = "apb_pclk"; 4835 4836 in-ports { 4837 4838 #address-cells = <1>; 4839 #size-cells = <0>; 4840 4841 port@1a { 4842 reg = <26>; 4843 tpda_dl_center_26_in_tpdm_dlct: endpoint { 4844 remote-endpoint = 4845 <&tpdm_dlct_out_tpda_dl_center_26>; 4846 }; 4847 }; 4848 4849 port@1b { 4850 reg = <27>; 4851 tpda_dl_center_27_in_tpdm_ipcc: endpoint { 4852 remote-endpoint = 4853 <&tpdm_ipcc_out_tpda_dl_center_27>; 4854 }; 4855 }; 4856 }; 4857 4858 out-ports { 4859 4860 port { 4861 tpda_dl_center_out_funnel_dl_center: endpoint { 4862 remote-endpoint = 4863 <&funnel_dl_center_in_tpda_dl_center>; 4864 }; 4865 }; 4866 }; 4867 }; 4868 4869 funnel@10c2f000 { 4870 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4871 reg = <0x0 0x10c2f000 0x0 0x1000>; 4872 4873 clocks = <&aoss_qmp>; 4874 clock-names = "apb_pclk"; 4875 4876 in-ports { 4877 4878 port { 4879 funnel_dl_center_in_tpda_dl_center: endpoint { 4880 remote-endpoint = 4881 <&tpda_dl_center_out_funnel_dl_center>; 4882 }; 4883 }; 4884 }; 4885 4886 out-ports { 4887 port { 4888 funnel_dl_center_out_funnel_in1: endpoint { 4889 remote-endpoint = 4890 <&funnel_in1_in_funnel_dl_center>; 4891 }; 4892 }; 4893 }; 4894 }; 4895 4896 funnel@13810000 { 4897 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4898 4899 reg = <0x0 0x13810000 0x0 0x1000>; 4900 4901 clocks = <&aoss_qmp>; 4902 clock-names = "apb_pclk"; 4903 4904 in-ports { 4905 4906 port { 4907 funnel_apss_in_funnel_ete: endpoint { 4908 remote-endpoint = 4909 <&funnel_ete_out_funnel_apss>; 4910 }; 4911 }; 4912 }; 4913 4914 out-ports { 4915 port { 4916 funnel_apss_out_funnel_in1: endpoint { 4917 remote-endpoint = 4918 <&funnel_in1_in_funnel_apss>; 4919 }; 4920 }; 4921 }; 4922 }; 4923 4924 cti@138e0000 { 4925 compatible = "arm,coresight-cti", "arm,primecell"; 4926 reg = <0x0 0x138e0000 0x0 0x1000>; 4927 4928 clocks = <&aoss_qmp>; 4929 clock-names = "apb_pclk"; 4930 }; 4931 4932 cti@138f0000 { 4933 compatible = "arm,coresight-cti", "arm,primecell"; 4934 reg = <0x0 0x138f0000 0x0 0x1000>; 4935 4936 clocks = <&aoss_qmp>; 4937 clock-names = "apb_pclk"; 4938 }; 4939 4940 cti@13900000 { 4941 compatible = "arm,coresight-cti", "arm,primecell"; 4942 reg = <0x0 0x13900000 0x0 0x1000>; 4943 4944 clocks = <&aoss_qmp>; 4945 clock-names = "apb_pclk"; 4946 }; 4947 4948 sram@146aa000 { 4949 compatible = "qcom,sm8450-imem", "syscon", "simple-mfd"; 4950 reg = <0 0x146aa000 0 0x1000>; 4951 ranges = <0 0 0x146aa000 0x1000>; 4952 4953 #address-cells = <1>; 4954 #size-cells = <1>; 4955 4956 pil-reloc@94c { 4957 compatible = "qcom,pil-reloc-info"; 4958 reg = <0x94c 0xc8>; 4959 }; 4960 }; 4961 4962 apps_smmu: iommu@15000000 { 4963 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; 4964 reg = <0 0x15000000 0 0x100000>; 4965 #iommu-cells = <2>; 4966 #global-interrupts = <1>; 4967 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4968 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4969 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4970 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4971 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4972 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4973 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4974 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4975 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4976 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4977 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4978 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4979 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4980 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4981 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4982 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4983 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4984 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4985 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4986 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4987 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4988 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4989 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4990 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4991 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4992 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4993 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4994 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4995 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4996 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4997 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4998 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4999 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5000 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5001 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5002 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5003 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5004 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5005 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5006 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5007 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5008 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5009 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5010 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5011 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5012 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5013 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5014 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5015 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5016 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5017 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5018 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5019 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5020 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5021 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5022 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5023 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5024 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5025 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5026 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5027 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5028 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5029 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5030 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5031 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5032 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5033 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5034 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5035 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5036 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5037 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5038 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5039 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5040 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5041 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5042 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5043 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5044 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5045 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5046 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5047 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5048 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5049 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5050 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5051 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5052 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 5053 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5054 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5055 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5056 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5057 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5058 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5059 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5060 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5061 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5062 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5063 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 5064 dma-coherent; 5065 }; 5066 5067 intc: interrupt-controller@17100000 { 5068 compatible = "arm,gic-v3"; 5069 #interrupt-cells = <3>; 5070 interrupt-controller; 5071 #redistributor-regions = <1>; 5072 redistributor-stride = <0x0 0x40000>; 5073 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ 5074 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ 5075 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5076 #address-cells = <2>; 5077 #size-cells = <2>; 5078 ranges; 5079 5080 gic_its: msi-controller@17140000 { 5081 compatible = "arm,gic-v3-its"; 5082 reg = <0x0 0x17140000 0x0 0x20000>; 5083 msi-controller; 5084 #msi-cells = <1>; 5085 }; 5086 }; 5087 5088 timer@17420000 { 5089 compatible = "arm,armv7-timer-mem"; 5090 #address-cells = <1>; 5091 #size-cells = <1>; 5092 ranges = <0 0 0 0x20000000>; 5093 reg = <0x0 0x17420000 0x0 0x1000>; 5094 clock-frequency = <19200000>; 5095 5096 frame@17421000 { 5097 frame-number = <0>; 5098 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5099 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5100 reg = <0x17421000 0x1000>, 5101 <0x17422000 0x1000>; 5102 }; 5103 5104 frame@17423000 { 5105 frame-number = <1>; 5106 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5107 reg = <0x17423000 0x1000>; 5108 status = "disabled"; 5109 }; 5110 5111 frame@17425000 { 5112 frame-number = <2>; 5113 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5114 reg = <0x17425000 0x1000>; 5115 status = "disabled"; 5116 }; 5117 5118 frame@17427000 { 5119 frame-number = <3>; 5120 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5121 reg = <0x17427000 0x1000>; 5122 status = "disabled"; 5123 }; 5124 5125 frame@17429000 { 5126 frame-number = <4>; 5127 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5128 reg = <0x17429000 0x1000>; 5129 status = "disabled"; 5130 }; 5131 5132 frame@1742b000 { 5133 frame-number = <5>; 5134 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5135 reg = <0x1742b000 0x1000>; 5136 status = "disabled"; 5137 }; 5138 5139 frame@1742d000 { 5140 frame-number = <6>; 5141 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5142 reg = <0x1742d000 0x1000>; 5143 status = "disabled"; 5144 }; 5145 }; 5146 5147 apps_rsc: rsc@17a00000 { 5148 label = "apps_rsc"; 5149 compatible = "qcom,rpmh-rsc"; 5150 reg = <0x0 0x17a00000 0x0 0x10000>, 5151 <0x0 0x17a10000 0x0 0x10000>, 5152 <0x0 0x17a20000 0x0 0x10000>, 5153 <0x0 0x17a30000 0x0 0x10000>; 5154 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 5155 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5156 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5157 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5158 qcom,tcs-offset = <0xd00>; 5159 qcom,drv-id = <2>; 5160 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 5161 <WAKE_TCS 2>, <CONTROL_TCS 0>; 5162 power-domains = <&cluster_pd>; 5163 5164 apps_bcm_voter: bcm-voter { 5165 compatible = "qcom,bcm-voter"; 5166 }; 5167 5168 rpmhcc: clock-controller { 5169 compatible = "qcom,sm8450-rpmh-clk"; 5170 #clock-cells = <1>; 5171 clock-names = "xo"; 5172 clocks = <&xo_board>; 5173 }; 5174 5175 rpmhpd: power-controller { 5176 compatible = "qcom,sm8450-rpmhpd"; 5177 #power-domain-cells = <1>; 5178 operating-points-v2 = <&rpmhpd_opp_table>; 5179 5180 rpmhpd_opp_table: opp-table { 5181 compatible = "operating-points-v2"; 5182 5183 rpmhpd_opp_ret: opp1 { 5184 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5185 }; 5186 5187 rpmhpd_opp_min_svs: opp2 { 5188 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5189 }; 5190 5191 rpmhpd_opp_low_svs_d1: opp3 { 5192 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 5193 }; 5194 5195 rpmhpd_opp_low_svs: opp4 { 5196 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5197 }; 5198 5199 rpmhpd_opp_low_svs_l1: opp5 { 5200 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 5201 }; 5202 5203 rpmhpd_opp_svs: opp6 { 5204 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5205 }; 5206 5207 rpmhpd_opp_svs_l0: opp7 { 5208 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 5209 }; 5210 5211 rpmhpd_opp_svs_l1: opp8 { 5212 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5213 }; 5214 5215 rpmhpd_opp_svs_l2: opp9 { 5216 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5217 }; 5218 5219 rpmhpd_opp_nom: opp10 { 5220 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5221 }; 5222 5223 rpmhpd_opp_nom_l1: opp11 { 5224 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5225 }; 5226 5227 rpmhpd_opp_nom_l2: opp12 { 5228 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5229 }; 5230 5231 rpmhpd_opp_turbo: opp13 { 5232 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5233 }; 5234 5235 rpmhpd_opp_turbo_l1: opp14 { 5236 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5237 }; 5238 }; 5239 }; 5240 }; 5241 5242 cpufreq_hw: cpufreq@17d91000 { 5243 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss"; 5244 reg = <0 0x17d91000 0 0x1000>, 5245 <0 0x17d92000 0 0x1000>, 5246 <0 0x17d93000 0 0x1000>; 5247 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 5248 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5249 clock-names = "xo", "alternate"; 5250 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 5251 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5252 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 5253 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 5254 #freq-domain-cells = <1>; 5255 #clock-cells = <1>; 5256 }; 5257 5258 gem_noc: interconnect@19100000 { 5259 compatible = "qcom,sm8450-gem-noc"; 5260 reg = <0 0x19100000 0 0xbb800>; 5261 #interconnect-cells = <2>; 5262 qcom,bcm-voters = <&apps_bcm_voter>; 5263 }; 5264 5265 system-cache-controller@19200000 { 5266 compatible = "qcom,sm8450-llcc"; 5267 reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>, 5268 <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>, 5269 <0 0x19a00000 0 0x80000>, <0 0x19c00000 0 0x80000>; 5270 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 5271 "llcc3_base", "llcc_broadcast_base", 5272 "llcc_broadcast_and_base"; 5273 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 5274 }; 5275 5276 ufs_mem_hc: ufshc@1d84000 { 5277 compatible = "qcom,sm8450-ufshc", "qcom,ufshc", 5278 "jedec,ufs-2.0"; 5279 reg = <0 0x01d84000 0 0x3000>; 5280 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 5281 phys = <&ufs_mem_phy>; 5282 phy-names = "ufsphy"; 5283 lanes-per-direction = <2>; 5284 #reset-cells = <1>; 5285 resets = <&gcc GCC_UFS_PHY_BCR>; 5286 reset-names = "rst"; 5287 5288 power-domains = <&gcc UFS_PHY_GDSC>; 5289 5290 iommus = <&apps_smmu 0xe0 0x0>; 5291 dma-coherent; 5292 5293 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 5294 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 5295 interconnect-names = "ufs-ddr", "cpu-ufs"; 5296 clock-names = 5297 "core_clk", 5298 "bus_aggr_clk", 5299 "iface_clk", 5300 "core_clk_unipro", 5301 "ref_clk", 5302 "tx_lane0_sync_clk", 5303 "rx_lane0_sync_clk", 5304 "rx_lane1_sync_clk"; 5305 clocks = 5306 <&gcc GCC_UFS_PHY_AXI_CLK>, 5307 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 5308 <&gcc GCC_UFS_PHY_AHB_CLK>, 5309 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 5310 <&rpmhcc RPMH_CXO_CLK>, 5311 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 5312 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 5313 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 5314 freq-table-hz = 5315 <75000000 300000000>, 5316 <0 0>, 5317 <0 0>, 5318 <75000000 300000000>, 5319 <75000000 300000000>, 5320 <0 0>, 5321 <0 0>, 5322 <0 0>; 5323 qcom,ice = <&ice>; 5324 5325 status = "disabled"; 5326 }; 5327 5328 ufs_mem_phy: phy@1d87000 { 5329 compatible = "qcom,sm8450-qmp-ufs-phy"; 5330 reg = <0 0x01d87000 0 0x1000>; 5331 5332 clock-names = "ref", "ref_aux", "qref"; 5333 clocks = <&rpmhcc RPMH_CXO_CLK>, 5334 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 5335 <&gcc GCC_UFS_0_CLKREF_EN>; 5336 5337 power-domains = <&gcc UFS_PHY_GDSC>; 5338 5339 resets = <&ufs_mem_hc 0>; 5340 reset-names = "ufsphy"; 5341 5342 #clock-cells = <1>; 5343 #phy-cells = <0>; 5344 5345 status = "disabled"; 5346 }; 5347 5348 ice: crypto@1d88000 { 5349 compatible = "qcom,sm8450-inline-crypto-engine", 5350 "qcom,inline-crypto-engine"; 5351 reg = <0 0x01d88000 0 0x8000>; 5352 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 5353 }; 5354 5355 cryptobam: dma-controller@1dc4000 { 5356 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 5357 reg = <0 0x01dc4000 0 0x28000>; 5358 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 5359 #dma-cells = <1>; 5360 qcom,ee = <0>; 5361 qcom,num-ees = <4>; 5362 num-channels = <16>; 5363 qcom,controlled-remotely; 5364 iommus = <&apps_smmu 0x584 0x11>, 5365 <&apps_smmu 0x588 0x0>, 5366 <&apps_smmu 0x598 0x5>, 5367 <&apps_smmu 0x59a 0x0>, 5368 <&apps_smmu 0x59f 0x0>; 5369 }; 5370 5371 crypto: crypto@1dfa000 { 5372 compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce"; 5373 reg = <0 0x01dfa000 0 0x6000>; 5374 dmas = <&cryptobam 4>, <&cryptobam 5>; 5375 dma-names = "rx", "tx"; 5376 iommus = <&apps_smmu 0x584 0x11>, 5377 <&apps_smmu 0x588 0x0>, 5378 <&apps_smmu 0x598 0x5>, 5379 <&apps_smmu 0x59a 0x0>, 5380 <&apps_smmu 0x59f 0x0>; 5381 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 5382 interconnect-names = "memory"; 5383 }; 5384 5385 sdhc_2: mmc@8804000 { 5386 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5"; 5387 reg = <0 0x08804000 0 0x1000>; 5388 5389 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 5390 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 5391 interrupt-names = "hc_irq", "pwr_irq"; 5392 5393 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 5394 <&gcc GCC_SDCC2_APPS_CLK>, 5395 <&rpmhcc RPMH_CXO_CLK>; 5396 clock-names = "iface", "core", "xo"; 5397 resets = <&gcc GCC_SDCC2_BCR>; 5398 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 5399 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 5400 interconnect-names = "sdhc-ddr","cpu-sdhc"; 5401 iommus = <&apps_smmu 0x4a0 0x0>; 5402 power-domains = <&rpmhpd RPMHPD_CX>; 5403 operating-points-v2 = <&sdhc2_opp_table>; 5404 bus-width = <4>; 5405 dma-coherent; 5406 5407 /* Forbid SDR104/SDR50 - broken hw! */ 5408 sdhci-caps-mask = <0x3 0x0>; 5409 5410 status = "disabled"; 5411 5412 sdhc2_opp_table: opp-table { 5413 compatible = "operating-points-v2"; 5414 5415 opp-100000000 { 5416 opp-hz = /bits/ 64 <100000000>; 5417 required-opps = <&rpmhpd_opp_low_svs>; 5418 }; 5419 5420 opp-202000000 { 5421 opp-hz = /bits/ 64 <202000000>; 5422 required-opps = <&rpmhpd_opp_svs_l1>; 5423 }; 5424 }; 5425 }; 5426 5427 usb_1: usb@a600000 { 5428 compatible = "qcom,sm8450-dwc3", "qcom,snps-dwc3"; 5429 reg = <0 0x0a600000 0 0xfc100>; 5430 status = "disabled"; 5431 5432 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 5433 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 5434 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 5435 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 5436 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5437 <&gcc GCC_USB3_0_CLKREF_EN>; 5438 clock-names = "cfg_noc", 5439 "core", 5440 "iface", 5441 "sleep", 5442 "mock_utmi", 5443 "xo"; 5444 5445 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5446 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 5447 assigned-clock-rates = <19200000>, <200000000>; 5448 5449 interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 5450 <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 5451 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 5452 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 5453 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 5454 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 5455 interrupt-names = "dwc_usb3", 5456 "pwr_event", 5457 "hs_phy_irq", 5458 "dp_hs_phy_irq", 5459 "dm_hs_phy_irq", 5460 "ss_phy_irq"; 5461 5462 power-domains = <&gcc USB30_PRIM_GDSC>; 5463 5464 resets = <&gcc GCC_USB30_PRIM_BCR>; 5465 5466 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 5467 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 5468 interconnect-names = "usb-ddr", "apps-usb"; 5469 5470 iommus = <&apps_smmu 0x0 0x0>; 5471 snps,dis_u2_susphy_quirk; 5472 snps,dis_u3_susphy_quirk; 5473 snps,dis_enblslpm_quirk; 5474 snps,dis-u1-entry-quirk; 5475 snps,dis-u2-entry-quirk; 5476 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 5477 phy-names = "usb2-phy", "usb3-phy"; 5478 usb-role-switch; 5479 5480 ports { 5481 #address-cells = <1>; 5482 #size-cells = <0>; 5483 5484 port@0 { 5485 reg = <0>; 5486 5487 usb_1_dwc3_hs: endpoint { 5488 }; 5489 }; 5490 5491 port@1 { 5492 reg = <1>; 5493 5494 usb_1_dwc3_ss: endpoint { 5495 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 5496 }; 5497 }; 5498 }; 5499 }; 5500 5501 nsp_noc: interconnect@320c0000 { 5502 compatible = "qcom,sm8450-nsp-noc"; 5503 reg = <0 0x320c0000 0 0x10000>; 5504 #interconnect-cells = <2>; 5505 qcom,bcm-voters = <&apps_bcm_voter>; 5506 }; 5507 5508 lpass_ag_noc: interconnect@3c40000 { 5509 compatible = "qcom,sm8450-lpass-ag-noc"; 5510 reg = <0 0x03c40000 0 0x17200>; 5511 #interconnect-cells = <2>; 5512 qcom,bcm-voters = <&apps_bcm_voter>; 5513 }; 5514 }; 5515 5516 sound: sound { 5517 }; 5518 5519 thermal-zones { 5520 aoss0-thermal { 5521 thermal-sensors = <&tsens0 0>; 5522 5523 trips { 5524 thermal-engine-config { 5525 temperature = <125000>; 5526 hysteresis = <1000>; 5527 type = "passive"; 5528 }; 5529 5530 reset-mon-cfg { 5531 temperature = <115000>; 5532 hysteresis = <5000>; 5533 type = "passive"; 5534 }; 5535 }; 5536 }; 5537 5538 cpuss0-thermal { 5539 thermal-sensors = <&tsens0 1>; 5540 5541 trips { 5542 thermal-engine-config { 5543 temperature = <125000>; 5544 hysteresis = <1000>; 5545 type = "passive"; 5546 }; 5547 5548 reset-mon-cfg { 5549 temperature = <115000>; 5550 hysteresis = <5000>; 5551 type = "passive"; 5552 }; 5553 }; 5554 }; 5555 5556 cpuss1-thermal { 5557 thermal-sensors = <&tsens0 2>; 5558 5559 trips { 5560 thermal-engine-config { 5561 temperature = <125000>; 5562 hysteresis = <1000>; 5563 type = "passive"; 5564 }; 5565 5566 reset-mon-cfg { 5567 temperature = <115000>; 5568 hysteresis = <5000>; 5569 type = "passive"; 5570 }; 5571 }; 5572 }; 5573 5574 cpuss3-thermal { 5575 thermal-sensors = <&tsens0 3>; 5576 5577 trips { 5578 thermal-engine-config { 5579 temperature = <125000>; 5580 hysteresis = <1000>; 5581 type = "passive"; 5582 }; 5583 5584 reset-mon-cfg { 5585 temperature = <115000>; 5586 hysteresis = <5000>; 5587 type = "passive"; 5588 }; 5589 }; 5590 }; 5591 5592 cpuss4-thermal { 5593 thermal-sensors = <&tsens0 4>; 5594 5595 trips { 5596 thermal-engine-config { 5597 temperature = <125000>; 5598 hysteresis = <1000>; 5599 type = "passive"; 5600 }; 5601 5602 reset-mon-cfg { 5603 temperature = <115000>; 5604 hysteresis = <5000>; 5605 type = "passive"; 5606 }; 5607 }; 5608 }; 5609 5610 cpu4-top-thermal { 5611 thermal-sensors = <&tsens0 5>; 5612 5613 trips { 5614 cpu4_top_alert0: trip-point0 { 5615 temperature = <90000>; 5616 hysteresis = <2000>; 5617 type = "passive"; 5618 }; 5619 5620 cpu4_top_alert1: trip-point1 { 5621 temperature = <95000>; 5622 hysteresis = <2000>; 5623 type = "passive"; 5624 }; 5625 5626 cpu4_top_crit: cpu-crit { 5627 temperature = <110000>; 5628 hysteresis = <1000>; 5629 type = "critical"; 5630 }; 5631 }; 5632 }; 5633 5634 cpu4-bottom-thermal { 5635 thermal-sensors = <&tsens0 6>; 5636 5637 trips { 5638 cpu4_bottom_alert0: trip-point0 { 5639 temperature = <90000>; 5640 hysteresis = <2000>; 5641 type = "passive"; 5642 }; 5643 5644 cpu4_bottom_alert1: trip-point1 { 5645 temperature = <95000>; 5646 hysteresis = <2000>; 5647 type = "passive"; 5648 }; 5649 5650 cpu4_bottom_crit: cpu-crit { 5651 temperature = <110000>; 5652 hysteresis = <1000>; 5653 type = "critical"; 5654 }; 5655 }; 5656 }; 5657 5658 cpu5-top-thermal { 5659 thermal-sensors = <&tsens0 7>; 5660 5661 trips { 5662 cpu5_top_alert0: trip-point0 { 5663 temperature = <90000>; 5664 hysteresis = <2000>; 5665 type = "passive"; 5666 }; 5667 5668 cpu5_top_alert1: trip-point1 { 5669 temperature = <95000>; 5670 hysteresis = <2000>; 5671 type = "passive"; 5672 }; 5673 5674 cpu5_top_crit: cpu-crit { 5675 temperature = <110000>; 5676 hysteresis = <1000>; 5677 type = "critical"; 5678 }; 5679 }; 5680 }; 5681 5682 cpu5-bottom-thermal { 5683 thermal-sensors = <&tsens0 8>; 5684 5685 trips { 5686 cpu5_bottom_alert0: trip-point0 { 5687 temperature = <90000>; 5688 hysteresis = <2000>; 5689 type = "passive"; 5690 }; 5691 5692 cpu5_bottom_alert1: trip-point1 { 5693 temperature = <95000>; 5694 hysteresis = <2000>; 5695 type = "passive"; 5696 }; 5697 5698 cpu5_bottom_crit: cpu-crit { 5699 temperature = <110000>; 5700 hysteresis = <1000>; 5701 type = "critical"; 5702 }; 5703 }; 5704 }; 5705 5706 cpu6-top-thermal { 5707 thermal-sensors = <&tsens0 9>; 5708 5709 trips { 5710 cpu6_top_alert0: trip-point0 { 5711 temperature = <90000>; 5712 hysteresis = <2000>; 5713 type = "passive"; 5714 }; 5715 5716 cpu6_top_alert1: trip-point1 { 5717 temperature = <95000>; 5718 hysteresis = <2000>; 5719 type = "passive"; 5720 }; 5721 5722 cpu6_top_crit: cpu-crit { 5723 temperature = <110000>; 5724 hysteresis = <1000>; 5725 type = "critical"; 5726 }; 5727 }; 5728 }; 5729 5730 cpu6-bottom-thermal { 5731 thermal-sensors = <&tsens0 10>; 5732 5733 trips { 5734 cpu6_bottom_alert0: trip-point0 { 5735 temperature = <90000>; 5736 hysteresis = <2000>; 5737 type = "passive"; 5738 }; 5739 5740 cpu6_bottom_alert1: trip-point1 { 5741 temperature = <95000>; 5742 hysteresis = <2000>; 5743 type = "passive"; 5744 }; 5745 5746 cpu6_bottom_crit: cpu-crit { 5747 temperature = <110000>; 5748 hysteresis = <1000>; 5749 type = "critical"; 5750 }; 5751 }; 5752 }; 5753 5754 cpu7-top-thermal { 5755 thermal-sensors = <&tsens0 11>; 5756 5757 trips { 5758 cpu7_top_alert0: trip-point0 { 5759 temperature = <90000>; 5760 hysteresis = <2000>; 5761 type = "passive"; 5762 }; 5763 5764 cpu7_top_alert1: trip-point1 { 5765 temperature = <95000>; 5766 hysteresis = <2000>; 5767 type = "passive"; 5768 }; 5769 5770 cpu7_top_crit: cpu-crit { 5771 temperature = <110000>; 5772 hysteresis = <1000>; 5773 type = "critical"; 5774 }; 5775 }; 5776 }; 5777 5778 cpu7-middle-thermal { 5779 thermal-sensors = <&tsens0 12>; 5780 5781 trips { 5782 cpu7_middle_alert0: trip-point0 { 5783 temperature = <90000>; 5784 hysteresis = <2000>; 5785 type = "passive"; 5786 }; 5787 5788 cpu7_middle_alert1: trip-point1 { 5789 temperature = <95000>; 5790 hysteresis = <2000>; 5791 type = "passive"; 5792 }; 5793 5794 cpu7_middle_crit: cpu-crit { 5795 temperature = <110000>; 5796 hysteresis = <1000>; 5797 type = "critical"; 5798 }; 5799 }; 5800 }; 5801 5802 cpu7-bottom-thermal { 5803 thermal-sensors = <&tsens0 13>; 5804 5805 trips { 5806 cpu7_bottom_alert0: trip-point0 { 5807 temperature = <90000>; 5808 hysteresis = <2000>; 5809 type = "passive"; 5810 }; 5811 5812 cpu7_bottom_alert1: trip-point1 { 5813 temperature = <95000>; 5814 hysteresis = <2000>; 5815 type = "passive"; 5816 }; 5817 5818 cpu7_bottom_crit: cpu-crit { 5819 temperature = <110000>; 5820 hysteresis = <1000>; 5821 type = "critical"; 5822 }; 5823 }; 5824 }; 5825 5826 gpu-top-thermal { 5827 polling-delay-passive = <10>; 5828 5829 thermal-sensors = <&tsens0 14>; 5830 5831 cooling-maps { 5832 map0 { 5833 trip = <&gpu_top_alert0>; 5834 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5835 }; 5836 }; 5837 5838 trips { 5839 gpu_top_alert0: trip-point0 { 5840 temperature = <85000>; 5841 hysteresis = <1000>; 5842 type = "passive"; 5843 }; 5844 5845 trip-point1 { 5846 temperature = <90000>; 5847 hysteresis = <1000>; 5848 type = "hot"; 5849 }; 5850 5851 trip-point2 { 5852 temperature = <110000>; 5853 hysteresis = <1000>; 5854 type = "critical"; 5855 }; 5856 }; 5857 }; 5858 5859 gpu-bottom-thermal { 5860 polling-delay-passive = <10>; 5861 5862 thermal-sensors = <&tsens0 15>; 5863 5864 cooling-maps { 5865 map0 { 5866 trip = <&gpu_bottom_alert0>; 5867 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5868 }; 5869 }; 5870 5871 trips { 5872 gpu_bottom_alert0: trip-point0 { 5873 temperature = <85000>; 5874 hysteresis = <1000>; 5875 type = "passive"; 5876 }; 5877 5878 trip-point1 { 5879 temperature = <90000>; 5880 hysteresis = <1000>; 5881 type = "hot"; 5882 }; 5883 5884 trip-point2 { 5885 temperature = <110000>; 5886 hysteresis = <1000>; 5887 type = "critical"; 5888 }; 5889 }; 5890 }; 5891 5892 aoss1-thermal { 5893 thermal-sensors = <&tsens1 0>; 5894 5895 trips { 5896 thermal-engine-config { 5897 temperature = <125000>; 5898 hysteresis = <1000>; 5899 type = "passive"; 5900 }; 5901 5902 reset-mon-cfg { 5903 temperature = <115000>; 5904 hysteresis = <5000>; 5905 type = "passive"; 5906 }; 5907 }; 5908 }; 5909 5910 cpu0-thermal { 5911 thermal-sensors = <&tsens1 1>; 5912 5913 trips { 5914 cpu0_alert0: trip-point0 { 5915 temperature = <90000>; 5916 hysteresis = <2000>; 5917 type = "passive"; 5918 }; 5919 5920 cpu0_alert1: trip-point1 { 5921 temperature = <95000>; 5922 hysteresis = <2000>; 5923 type = "passive"; 5924 }; 5925 5926 cpu0_crit: cpu-crit { 5927 temperature = <110000>; 5928 hysteresis = <1000>; 5929 type = "critical"; 5930 }; 5931 }; 5932 }; 5933 5934 cpu1-thermal { 5935 thermal-sensors = <&tsens1 2>; 5936 5937 trips { 5938 cpu1_alert0: trip-point0 { 5939 temperature = <90000>; 5940 hysteresis = <2000>; 5941 type = "passive"; 5942 }; 5943 5944 cpu1_alert1: trip-point1 { 5945 temperature = <95000>; 5946 hysteresis = <2000>; 5947 type = "passive"; 5948 }; 5949 5950 cpu1_crit: cpu-crit { 5951 temperature = <110000>; 5952 hysteresis = <1000>; 5953 type = "critical"; 5954 }; 5955 }; 5956 }; 5957 5958 cpu2-thermal { 5959 thermal-sensors = <&tsens1 3>; 5960 5961 trips { 5962 cpu2_alert0: trip-point0 { 5963 temperature = <90000>; 5964 hysteresis = <2000>; 5965 type = "passive"; 5966 }; 5967 5968 cpu2_alert1: trip-point1 { 5969 temperature = <95000>; 5970 hysteresis = <2000>; 5971 type = "passive"; 5972 }; 5973 5974 cpu2_crit: cpu-crit { 5975 temperature = <110000>; 5976 hysteresis = <1000>; 5977 type = "critical"; 5978 }; 5979 }; 5980 }; 5981 5982 cpu3-thermal { 5983 thermal-sensors = <&tsens1 4>; 5984 5985 trips { 5986 cpu3_alert0: trip-point0 { 5987 temperature = <90000>; 5988 hysteresis = <2000>; 5989 type = "passive"; 5990 }; 5991 5992 cpu3_alert1: trip-point1 { 5993 temperature = <95000>; 5994 hysteresis = <2000>; 5995 type = "passive"; 5996 }; 5997 5998 cpu3_crit: cpu-crit { 5999 temperature = <110000>; 6000 hysteresis = <1000>; 6001 type = "critical"; 6002 }; 6003 }; 6004 }; 6005 6006 cdsp0-thermal { 6007 polling-delay-passive = <10>; 6008 6009 thermal-sensors = <&tsens1 5>; 6010 6011 trips { 6012 thermal-engine-config { 6013 temperature = <125000>; 6014 hysteresis = <1000>; 6015 type = "passive"; 6016 }; 6017 6018 thermal-hal-config { 6019 temperature = <125000>; 6020 hysteresis = <1000>; 6021 type = "passive"; 6022 }; 6023 6024 reset-mon-cfg { 6025 temperature = <115000>; 6026 hysteresis = <5000>; 6027 type = "passive"; 6028 }; 6029 6030 cdsp_0_config: junction-config { 6031 temperature = <95000>; 6032 hysteresis = <5000>; 6033 type = "passive"; 6034 }; 6035 }; 6036 }; 6037 6038 cdsp1-thermal { 6039 polling-delay-passive = <10>; 6040 6041 thermal-sensors = <&tsens1 6>; 6042 6043 trips { 6044 thermal-engine-config { 6045 temperature = <125000>; 6046 hysteresis = <1000>; 6047 type = "passive"; 6048 }; 6049 6050 thermal-hal-config { 6051 temperature = <125000>; 6052 hysteresis = <1000>; 6053 type = "passive"; 6054 }; 6055 6056 reset-mon-cfg { 6057 temperature = <115000>; 6058 hysteresis = <5000>; 6059 type = "passive"; 6060 }; 6061 6062 cdsp_1_config: junction-config { 6063 temperature = <95000>; 6064 hysteresis = <5000>; 6065 type = "passive"; 6066 }; 6067 }; 6068 }; 6069 6070 cdsp2-thermal { 6071 polling-delay-passive = <10>; 6072 6073 thermal-sensors = <&tsens1 7>; 6074 6075 trips { 6076 thermal-engine-config { 6077 temperature = <125000>; 6078 hysteresis = <1000>; 6079 type = "passive"; 6080 }; 6081 6082 thermal-hal-config { 6083 temperature = <125000>; 6084 hysteresis = <1000>; 6085 type = "passive"; 6086 }; 6087 6088 reset-mon-cfg { 6089 temperature = <115000>; 6090 hysteresis = <5000>; 6091 type = "passive"; 6092 }; 6093 6094 cdsp_2_config: junction-config { 6095 temperature = <95000>; 6096 hysteresis = <5000>; 6097 type = "passive"; 6098 }; 6099 }; 6100 }; 6101 6102 video-thermal { 6103 thermal-sensors = <&tsens1 8>; 6104 6105 trips { 6106 thermal-engine-config { 6107 temperature = <125000>; 6108 hysteresis = <1000>; 6109 type = "passive"; 6110 }; 6111 6112 reset-mon-cfg { 6113 temperature = <115000>; 6114 hysteresis = <5000>; 6115 type = "passive"; 6116 }; 6117 }; 6118 }; 6119 6120 mem-thermal { 6121 polling-delay-passive = <10>; 6122 6123 thermal-sensors = <&tsens1 9>; 6124 6125 trips { 6126 thermal-engine-config { 6127 temperature = <125000>; 6128 hysteresis = <1000>; 6129 type = "passive"; 6130 }; 6131 6132 ddr_config0: ddr0-config { 6133 temperature = <90000>; 6134 hysteresis = <5000>; 6135 type = "passive"; 6136 }; 6137 6138 reset-mon-cfg { 6139 temperature = <115000>; 6140 hysteresis = <5000>; 6141 type = "passive"; 6142 }; 6143 }; 6144 }; 6145 6146 modem0-thermal { 6147 thermal-sensors = <&tsens1 10>; 6148 6149 trips { 6150 thermal-engine-config { 6151 temperature = <125000>; 6152 hysteresis = <1000>; 6153 type = "passive"; 6154 }; 6155 6156 mdmss0_config0: mdmss0-config0 { 6157 temperature = <102000>; 6158 hysteresis = <3000>; 6159 type = "passive"; 6160 }; 6161 6162 mdmss0_config1: mdmss0-config1 { 6163 temperature = <105000>; 6164 hysteresis = <3000>; 6165 type = "passive"; 6166 }; 6167 6168 reset-mon-cfg { 6169 temperature = <115000>; 6170 hysteresis = <5000>; 6171 type = "passive"; 6172 }; 6173 }; 6174 }; 6175 6176 modem1-thermal { 6177 thermal-sensors = <&tsens1 11>; 6178 6179 trips { 6180 thermal-engine-config { 6181 temperature = <125000>; 6182 hysteresis = <1000>; 6183 type = "passive"; 6184 }; 6185 6186 mdmss1_config0: mdmss1-config0 { 6187 temperature = <102000>; 6188 hysteresis = <3000>; 6189 type = "passive"; 6190 }; 6191 6192 mdmss1_config1: mdmss1-config1 { 6193 temperature = <105000>; 6194 hysteresis = <3000>; 6195 type = "passive"; 6196 }; 6197 6198 reset-mon-cfg { 6199 temperature = <115000>; 6200 hysteresis = <5000>; 6201 type = "passive"; 6202 }; 6203 }; 6204 }; 6205 6206 modem2-thermal { 6207 thermal-sensors = <&tsens1 12>; 6208 6209 trips { 6210 thermal-engine-config { 6211 temperature = <125000>; 6212 hysteresis = <1000>; 6213 type = "passive"; 6214 }; 6215 6216 mdmss2_config0: mdmss2-config0 { 6217 temperature = <102000>; 6218 hysteresis = <3000>; 6219 type = "passive"; 6220 }; 6221 6222 mdmss2_config1: mdmss2-config1 { 6223 temperature = <105000>; 6224 hysteresis = <3000>; 6225 type = "passive"; 6226 }; 6227 6228 reset-mon-cfg { 6229 temperature = <115000>; 6230 hysteresis = <5000>; 6231 type = "passive"; 6232 }; 6233 }; 6234 }; 6235 6236 modem3-thermal { 6237 thermal-sensors = <&tsens1 13>; 6238 6239 trips { 6240 thermal-engine-config { 6241 temperature = <125000>; 6242 hysteresis = <1000>; 6243 type = "passive"; 6244 }; 6245 6246 mdmss3_config0: mdmss3-config0 { 6247 temperature = <102000>; 6248 hysteresis = <3000>; 6249 type = "passive"; 6250 }; 6251 6252 mdmss3_config1: mdmss3-config1 { 6253 temperature = <105000>; 6254 hysteresis = <3000>; 6255 type = "passive"; 6256 }; 6257 6258 reset-mon-cfg { 6259 temperature = <115000>; 6260 hysteresis = <5000>; 6261 type = "passive"; 6262 }; 6263 }; 6264 }; 6265 6266 camera0-thermal { 6267 thermal-sensors = <&tsens1 14>; 6268 6269 trips { 6270 thermal-engine-config { 6271 temperature = <125000>; 6272 hysteresis = <1000>; 6273 type = "passive"; 6274 }; 6275 6276 reset-mon-cfg { 6277 temperature = <115000>; 6278 hysteresis = <5000>; 6279 type = "passive"; 6280 }; 6281 }; 6282 }; 6283 6284 camera1-thermal { 6285 thermal-sensors = <&tsens1 15>; 6286 6287 trips { 6288 thermal-engine-config { 6289 temperature = <125000>; 6290 hysteresis = <1000>; 6291 type = "passive"; 6292 }; 6293 6294 reset-mon-cfg { 6295 temperature = <115000>; 6296 hysteresis = <5000>; 6297 type = "passive"; 6298 }; 6299 }; 6300 }; 6301 }; 6302 6303 timer { 6304 compatible = "arm,armv8-timer"; 6305 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6306 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6307 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6308 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 6309 clock-frequency = <19200000>; 6310 }; 6311}; 6312