1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Linaro Limited 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-sm8450.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/clock/qcom,sm8450-camcc.h> 10#include <dt-bindings/clock/qcom,sm8450-dispcc.h> 11#include <dt-bindings/clock/qcom,sm8450-gpucc.h> 12#include <dt-bindings/clock/qcom,sm8450-videocc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/firmware/qcom,scm.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/phy/phy-qcom-qmp.h> 18#include <dt-bindings/power/qcom,rpmhpd.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/interconnect/qcom,icc.h> 21#include <dt-bindings/interconnect/qcom,sm8450.h> 22#include <dt-bindings/reset/qcom,sm8450-gpucc.h> 23#include <dt-bindings/soc/qcom,gpr.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 26#include <dt-bindings/thermal/thermal.h> 27 28/ { 29 interrupt-parent = <&intc>; 30 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 chosen { }; 35 36 clocks { 37 xo_board: xo-board { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <76800000>; 41 }; 42 43 sleep_clk: sleep-clk { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 clock-frequency = <32000>; 47 }; 48 }; 49 50 cpus { 51 #address-cells = <2>; 52 #size-cells = <0>; 53 54 CPU0: cpu@0 { 55 device_type = "cpu"; 56 compatible = "qcom,kryo780"; 57 reg = <0x0 0x0>; 58 enable-method = "psci"; 59 next-level-cache = <&L2_0>; 60 power-domains = <&CPU_PD0>; 61 power-domain-names = "psci"; 62 qcom,freq-domain = <&cpufreq_hw 0>; 63 #cooling-cells = <2>; 64 clocks = <&cpufreq_hw 0>; 65 L2_0: l2-cache { 66 compatible = "cache"; 67 cache-level = <2>; 68 cache-unified; 69 next-level-cache = <&L3_0>; 70 L3_0: l3-cache { 71 compatible = "cache"; 72 cache-level = <3>; 73 cache-unified; 74 }; 75 }; 76 }; 77 78 CPU1: cpu@100 { 79 device_type = "cpu"; 80 compatible = "qcom,kryo780"; 81 reg = <0x0 0x100>; 82 enable-method = "psci"; 83 next-level-cache = <&L2_100>; 84 power-domains = <&CPU_PD1>; 85 power-domain-names = "psci"; 86 qcom,freq-domain = <&cpufreq_hw 0>; 87 #cooling-cells = <2>; 88 clocks = <&cpufreq_hw 0>; 89 L2_100: l2-cache { 90 compatible = "cache"; 91 cache-level = <2>; 92 cache-unified; 93 next-level-cache = <&L3_0>; 94 }; 95 }; 96 97 CPU2: cpu@200 { 98 device_type = "cpu"; 99 compatible = "qcom,kryo780"; 100 reg = <0x0 0x200>; 101 enable-method = "psci"; 102 next-level-cache = <&L2_200>; 103 power-domains = <&CPU_PD2>; 104 power-domain-names = "psci"; 105 qcom,freq-domain = <&cpufreq_hw 0>; 106 #cooling-cells = <2>; 107 clocks = <&cpufreq_hw 0>; 108 L2_200: l2-cache { 109 compatible = "cache"; 110 cache-level = <2>; 111 cache-unified; 112 next-level-cache = <&L3_0>; 113 }; 114 }; 115 116 CPU3: cpu@300 { 117 device_type = "cpu"; 118 compatible = "qcom,kryo780"; 119 reg = <0x0 0x300>; 120 enable-method = "psci"; 121 next-level-cache = <&L2_300>; 122 power-domains = <&CPU_PD3>; 123 power-domain-names = "psci"; 124 qcom,freq-domain = <&cpufreq_hw 0>; 125 #cooling-cells = <2>; 126 clocks = <&cpufreq_hw 0>; 127 L2_300: l2-cache { 128 compatible = "cache"; 129 cache-level = <2>; 130 cache-unified; 131 next-level-cache = <&L3_0>; 132 }; 133 }; 134 135 CPU4: cpu@400 { 136 device_type = "cpu"; 137 compatible = "qcom,kryo780"; 138 reg = <0x0 0x400>; 139 enable-method = "psci"; 140 next-level-cache = <&L2_400>; 141 power-domains = <&CPU_PD4>; 142 power-domain-names = "psci"; 143 qcom,freq-domain = <&cpufreq_hw 1>; 144 #cooling-cells = <2>; 145 clocks = <&cpufreq_hw 1>; 146 L2_400: l2-cache { 147 compatible = "cache"; 148 cache-level = <2>; 149 cache-unified; 150 next-level-cache = <&L3_0>; 151 }; 152 }; 153 154 CPU5: cpu@500 { 155 device_type = "cpu"; 156 compatible = "qcom,kryo780"; 157 reg = <0x0 0x500>; 158 enable-method = "psci"; 159 next-level-cache = <&L2_500>; 160 power-domains = <&CPU_PD5>; 161 power-domain-names = "psci"; 162 qcom,freq-domain = <&cpufreq_hw 1>; 163 #cooling-cells = <2>; 164 clocks = <&cpufreq_hw 1>; 165 L2_500: l2-cache { 166 compatible = "cache"; 167 cache-level = <2>; 168 cache-unified; 169 next-level-cache = <&L3_0>; 170 }; 171 }; 172 173 CPU6: cpu@600 { 174 device_type = "cpu"; 175 compatible = "qcom,kryo780"; 176 reg = <0x0 0x600>; 177 enable-method = "psci"; 178 next-level-cache = <&L2_600>; 179 power-domains = <&CPU_PD6>; 180 power-domain-names = "psci"; 181 qcom,freq-domain = <&cpufreq_hw 1>; 182 #cooling-cells = <2>; 183 clocks = <&cpufreq_hw 1>; 184 L2_600: l2-cache { 185 compatible = "cache"; 186 cache-level = <2>; 187 cache-unified; 188 next-level-cache = <&L3_0>; 189 }; 190 }; 191 192 CPU7: cpu@700 { 193 device_type = "cpu"; 194 compatible = "qcom,kryo780"; 195 reg = <0x0 0x700>; 196 enable-method = "psci"; 197 next-level-cache = <&L2_700>; 198 power-domains = <&CPU_PD7>; 199 power-domain-names = "psci"; 200 qcom,freq-domain = <&cpufreq_hw 2>; 201 #cooling-cells = <2>; 202 clocks = <&cpufreq_hw 2>; 203 L2_700: l2-cache { 204 compatible = "cache"; 205 cache-level = <2>; 206 cache-unified; 207 next-level-cache = <&L3_0>; 208 }; 209 }; 210 211 cpu-map { 212 cluster0 { 213 core0 { 214 cpu = <&CPU0>; 215 }; 216 217 core1 { 218 cpu = <&CPU1>; 219 }; 220 221 core2 { 222 cpu = <&CPU2>; 223 }; 224 225 core3 { 226 cpu = <&CPU3>; 227 }; 228 229 core4 { 230 cpu = <&CPU4>; 231 }; 232 233 core5 { 234 cpu = <&CPU5>; 235 }; 236 237 core6 { 238 cpu = <&CPU6>; 239 }; 240 241 core7 { 242 cpu = <&CPU7>; 243 }; 244 }; 245 }; 246 247 idle-states { 248 entry-method = "psci"; 249 250 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 251 compatible = "arm,idle-state"; 252 idle-state-name = "silver-rail-power-collapse"; 253 arm,psci-suspend-param = <0x40000004>; 254 entry-latency-us = <800>; 255 exit-latency-us = <750>; 256 min-residency-us = <4090>; 257 local-timer-stop; 258 }; 259 260 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 261 compatible = "arm,idle-state"; 262 idle-state-name = "gold-rail-power-collapse"; 263 arm,psci-suspend-param = <0x40000004>; 264 entry-latency-us = <600>; 265 exit-latency-us = <1550>; 266 min-residency-us = <4791>; 267 local-timer-stop; 268 }; 269 }; 270 271 domain-idle-states { 272 CLUSTER_SLEEP_0: cluster-sleep-0 { 273 compatible = "domain-idle-state"; 274 arm,psci-suspend-param = <0x41000044>; 275 entry-latency-us = <1050>; 276 exit-latency-us = <2500>; 277 min-residency-us = <5309>; 278 }; 279 280 CLUSTER_SLEEP_1: cluster-sleep-1 { 281 compatible = "domain-idle-state"; 282 arm,psci-suspend-param = <0x4100c344>; 283 entry-latency-us = <2700>; 284 exit-latency-us = <3500>; 285 min-residency-us = <13959>; 286 }; 287 }; 288 }; 289 290 firmware { 291 scm: scm { 292 compatible = "qcom,scm-sm8450", "qcom,scm"; 293 qcom,dload-mode = <&tcsr 0x13000>; 294 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 295 #reset-cells = <1>; 296 }; 297 }; 298 299 clk_virt: interconnect-0 { 300 compatible = "qcom,sm8450-clk-virt"; 301 #interconnect-cells = <2>; 302 qcom,bcm-voters = <&apps_bcm_voter>; 303 }; 304 305 mc_virt: interconnect-1 { 306 compatible = "qcom,sm8450-mc-virt"; 307 #interconnect-cells = <2>; 308 qcom,bcm-voters = <&apps_bcm_voter>; 309 }; 310 311 memory@a0000000 { 312 device_type = "memory"; 313 /* We expect the bootloader to fill in the size */ 314 reg = <0x0 0xa0000000 0x0 0x0>; 315 }; 316 317 pmu { 318 compatible = "arm,armv8-pmuv3"; 319 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 320 }; 321 322 psci { 323 compatible = "arm,psci-1.0"; 324 method = "smc"; 325 326 CPU_PD0: power-domain-cpu0 { 327 #power-domain-cells = <0>; 328 power-domains = <&CLUSTER_PD>; 329 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 330 }; 331 332 CPU_PD1: power-domain-cpu1 { 333 #power-domain-cells = <0>; 334 power-domains = <&CLUSTER_PD>; 335 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 336 }; 337 338 CPU_PD2: power-domain-cpu2 { 339 #power-domain-cells = <0>; 340 power-domains = <&CLUSTER_PD>; 341 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 342 }; 343 344 CPU_PD3: power-domain-cpu3 { 345 #power-domain-cells = <0>; 346 power-domains = <&CLUSTER_PD>; 347 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 348 }; 349 350 CPU_PD4: power-domain-cpu4 { 351 #power-domain-cells = <0>; 352 power-domains = <&CLUSTER_PD>; 353 domain-idle-states = <&BIG_CPU_SLEEP_0>; 354 }; 355 356 CPU_PD5: power-domain-cpu5 { 357 #power-domain-cells = <0>; 358 power-domains = <&CLUSTER_PD>; 359 domain-idle-states = <&BIG_CPU_SLEEP_0>; 360 }; 361 362 CPU_PD6: power-domain-cpu6 { 363 #power-domain-cells = <0>; 364 power-domains = <&CLUSTER_PD>; 365 domain-idle-states = <&BIG_CPU_SLEEP_0>; 366 }; 367 368 CPU_PD7: power-domain-cpu7 { 369 #power-domain-cells = <0>; 370 power-domains = <&CLUSTER_PD>; 371 domain-idle-states = <&BIG_CPU_SLEEP_0>; 372 }; 373 374 CLUSTER_PD: power-domain-cpu-cluster0 { 375 #power-domain-cells = <0>; 376 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; 377 }; 378 }; 379 380 qup_opp_table_100mhz: opp-table-qup { 381 compatible = "operating-points-v2"; 382 383 opp-50000000 { 384 opp-hz = /bits/ 64 <50000000>; 385 required-opps = <&rpmhpd_opp_min_svs>; 386 }; 387 388 opp-75000000 { 389 opp-hz = /bits/ 64 <75000000>; 390 required-opps = <&rpmhpd_opp_low_svs>; 391 }; 392 393 opp-100000000 { 394 opp-hz = /bits/ 64 <100000000>; 395 required-opps = <&rpmhpd_opp_svs>; 396 }; 397 }; 398 399 reserved_memory: reserved-memory { 400 #address-cells = <2>; 401 #size-cells = <2>; 402 ranges; 403 404 hyp_mem: memory@80000000 { 405 reg = <0x0 0x80000000 0x0 0x600000>; 406 no-map; 407 }; 408 409 xbl_dt_log_mem: memory@80600000 { 410 reg = <0x0 0x80600000 0x0 0x40000>; 411 no-map; 412 }; 413 414 xbl_ramdump_mem: memory@80640000 { 415 reg = <0x0 0x80640000 0x0 0x180000>; 416 no-map; 417 }; 418 419 xbl_sc_mem: memory@807c0000 { 420 reg = <0x0 0x807c0000 0x0 0x40000>; 421 no-map; 422 }; 423 424 aop_image_mem: memory@80800000 { 425 reg = <0x0 0x80800000 0x0 0x60000>; 426 no-map; 427 }; 428 429 aop_cmd_db_mem: memory@80860000 { 430 compatible = "qcom,cmd-db"; 431 reg = <0x0 0x80860000 0x0 0x20000>; 432 no-map; 433 }; 434 435 aop_config_mem: memory@80880000 { 436 reg = <0x0 0x80880000 0x0 0x20000>; 437 no-map; 438 }; 439 440 tme_crash_dump_mem: memory@808a0000 { 441 reg = <0x0 0x808a0000 0x0 0x40000>; 442 no-map; 443 }; 444 445 tme_log_mem: memory@808e0000 { 446 reg = <0x0 0x808e0000 0x0 0x4000>; 447 no-map; 448 }; 449 450 uefi_log_mem: memory@808e4000 { 451 reg = <0x0 0x808e4000 0x0 0x10000>; 452 no-map; 453 }; 454 455 /* secdata region can be reused by apps */ 456 smem: memory@80900000 { 457 compatible = "qcom,smem"; 458 reg = <0x0 0x80900000 0x0 0x200000>; 459 hwlocks = <&tcsr_mutex 3>; 460 no-map; 461 }; 462 463 cpucp_fw_mem: memory@80b00000 { 464 reg = <0x0 0x80b00000 0x0 0x100000>; 465 no-map; 466 }; 467 468 cdsp_secure_heap: memory@80c00000 { 469 reg = <0x0 0x80c00000 0x0 0x4600000>; 470 no-map; 471 }; 472 473 video_mem: memory@85700000 { 474 reg = <0x0 0x85700000 0x0 0x700000>; 475 no-map; 476 }; 477 478 adsp_mem: memory@85e00000 { 479 reg = <0x0 0x85e00000 0x0 0x2100000>; 480 no-map; 481 }; 482 483 slpi_mem: memory@88000000 { 484 reg = <0x0 0x88000000 0x0 0x1900000>; 485 no-map; 486 }; 487 488 cdsp_mem: memory@89900000 { 489 reg = <0x0 0x89900000 0x0 0x2000000>; 490 no-map; 491 }; 492 493 ipa_fw_mem: memory@8b900000 { 494 reg = <0x0 0x8b900000 0x0 0x10000>; 495 no-map; 496 }; 497 498 ipa_gsi_mem: memory@8b910000 { 499 reg = <0x0 0x8b910000 0x0 0xa000>; 500 no-map; 501 }; 502 503 gpu_micro_code_mem: memory@8b91a000 { 504 reg = <0x0 0x8b91a000 0x0 0x2000>; 505 no-map; 506 }; 507 508 spss_region_mem: memory@8ba00000 { 509 reg = <0x0 0x8ba00000 0x0 0x180000>; 510 no-map; 511 }; 512 513 /* First part of the "SPU secure shared memory" region */ 514 spu_tz_shared_mem: memory@8bb80000 { 515 reg = <0x0 0x8bb80000 0x0 0x60000>; 516 no-map; 517 }; 518 519 /* Second part of the "SPU secure shared memory" region */ 520 spu_modem_shared_mem: memory@8bbe0000 { 521 reg = <0x0 0x8bbe0000 0x0 0x20000>; 522 no-map; 523 }; 524 525 mpss_mem: memory@8bc00000 { 526 reg = <0x0 0x8bc00000 0x0 0x13200000>; 527 no-map; 528 }; 529 530 cvp_mem: memory@9ee00000 { 531 reg = <0x0 0x9ee00000 0x0 0x700000>; 532 no-map; 533 }; 534 535 camera_mem: memory@9f500000 { 536 reg = <0x0 0x9f500000 0x0 0x800000>; 537 no-map; 538 }; 539 540 rmtfs_mem: memory@9fd00000 { 541 compatible = "qcom,rmtfs-mem"; 542 reg = <0x0 0x9fd00000 0x0 0x280000>; 543 no-map; 544 545 qcom,client-id = <1>; 546 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 547 }; 548 549 xbl_sc_mem2: memory@a6e00000 { 550 reg = <0x0 0xa6e00000 0x0 0x40000>; 551 no-map; 552 }; 553 554 global_sync_mem: memory@a6f00000 { 555 reg = <0x0 0xa6f00000 0x0 0x100000>; 556 no-map; 557 }; 558 559 /* uefi region can be reused by APPS */ 560 561 /* Linux kernel image is loaded at 0xa0000000 */ 562 563 oem_vm_mem: memory@bb000000 { 564 reg = <0x0 0xbb000000 0x0 0x5000000>; 565 no-map; 566 }; 567 568 mte_mem: memory@c0000000 { 569 reg = <0x0 0xc0000000 0x0 0x20000000>; 570 no-map; 571 }; 572 573 qheebsp_reserved_mem: memory@e0000000 { 574 reg = <0x0 0xe0000000 0x0 0x600000>; 575 no-map; 576 }; 577 578 cpusys_vm_mem: memory@e0600000 { 579 reg = <0x0 0xe0600000 0x0 0x400000>; 580 no-map; 581 }; 582 583 hyp_reserved_mem: memory@e0a00000 { 584 reg = <0x0 0xe0a00000 0x0 0x100000>; 585 no-map; 586 }; 587 588 trust_ui_vm_mem: memory@e0b00000 { 589 reg = <0x0 0xe0b00000 0x0 0x4af3000>; 590 no-map; 591 }; 592 593 trust_ui_vm_qrtr: memory@e55f3000 { 594 reg = <0x0 0xe55f3000 0x0 0x9000>; 595 no-map; 596 }; 597 598 trust_ui_vm_vblk0_ring: memory@e55fc000 { 599 reg = <0x0 0xe55fc000 0x0 0x4000>; 600 no-map; 601 }; 602 603 trust_ui_vm_swiotlb: memory@e5600000 { 604 reg = <0x0 0xe5600000 0x0 0x100000>; 605 no-map; 606 }; 607 608 tz_stat_mem: memory@e8800000 { 609 reg = <0x0 0xe8800000 0x0 0x100000>; 610 no-map; 611 }; 612 613 tags_mem: memory@e8900000 { 614 reg = <0x0 0xe8900000 0x0 0x1200000>; 615 no-map; 616 }; 617 618 qtee_mem: memory@e9b00000 { 619 reg = <0x0 0xe9b00000 0x0 0x500000>; 620 no-map; 621 }; 622 623 trusted_apps_mem: memory@ea000000 { 624 reg = <0x0 0xea000000 0x0 0x3900000>; 625 no-map; 626 }; 627 628 trusted_apps_ext_mem: memory@ed900000 { 629 reg = <0x0 0xed900000 0x0 0x3b00000>; 630 no-map; 631 }; 632 }; 633 634 smp2p-adsp { 635 compatible = "qcom,smp2p"; 636 qcom,smem = <443>, <429>; 637 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 638 IPCC_MPROC_SIGNAL_SMP2P 639 IRQ_TYPE_EDGE_RISING>; 640 mboxes = <&ipcc IPCC_CLIENT_LPASS 641 IPCC_MPROC_SIGNAL_SMP2P>; 642 643 qcom,local-pid = <0>; 644 qcom,remote-pid = <2>; 645 646 smp2p_adsp_out: master-kernel { 647 qcom,entry-name = "master-kernel"; 648 #qcom,smem-state-cells = <1>; 649 }; 650 651 smp2p_adsp_in: slave-kernel { 652 qcom,entry-name = "slave-kernel"; 653 interrupt-controller; 654 #interrupt-cells = <2>; 655 }; 656 }; 657 658 smp2p-cdsp { 659 compatible = "qcom,smp2p"; 660 qcom,smem = <94>, <432>; 661 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 662 IPCC_MPROC_SIGNAL_SMP2P 663 IRQ_TYPE_EDGE_RISING>; 664 mboxes = <&ipcc IPCC_CLIENT_CDSP 665 IPCC_MPROC_SIGNAL_SMP2P>; 666 667 qcom,local-pid = <0>; 668 qcom,remote-pid = <5>; 669 670 smp2p_cdsp_out: master-kernel { 671 qcom,entry-name = "master-kernel"; 672 #qcom,smem-state-cells = <1>; 673 }; 674 675 smp2p_cdsp_in: slave-kernel { 676 qcom,entry-name = "slave-kernel"; 677 interrupt-controller; 678 #interrupt-cells = <2>; 679 }; 680 }; 681 682 smp2p-modem { 683 compatible = "qcom,smp2p"; 684 qcom,smem = <435>, <428>; 685 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 686 IPCC_MPROC_SIGNAL_SMP2P 687 IRQ_TYPE_EDGE_RISING>; 688 mboxes = <&ipcc IPCC_CLIENT_MPSS 689 IPCC_MPROC_SIGNAL_SMP2P>; 690 691 qcom,local-pid = <0>; 692 qcom,remote-pid = <1>; 693 694 smp2p_modem_out: master-kernel { 695 qcom,entry-name = "master-kernel"; 696 #qcom,smem-state-cells = <1>; 697 }; 698 699 smp2p_modem_in: slave-kernel { 700 qcom,entry-name = "slave-kernel"; 701 interrupt-controller; 702 #interrupt-cells = <2>; 703 }; 704 705 ipa_smp2p_out: ipa-ap-to-modem { 706 qcom,entry-name = "ipa"; 707 #qcom,smem-state-cells = <1>; 708 }; 709 710 ipa_smp2p_in: ipa-modem-to-ap { 711 qcom,entry-name = "ipa"; 712 interrupt-controller; 713 #interrupt-cells = <2>; 714 }; 715 }; 716 717 smp2p-slpi { 718 compatible = "qcom,smp2p"; 719 qcom,smem = <481>, <430>; 720 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 721 IPCC_MPROC_SIGNAL_SMP2P 722 IRQ_TYPE_EDGE_RISING>; 723 mboxes = <&ipcc IPCC_CLIENT_SLPI 724 IPCC_MPROC_SIGNAL_SMP2P>; 725 726 qcom,local-pid = <0>; 727 qcom,remote-pid = <3>; 728 729 smp2p_slpi_out: master-kernel { 730 qcom,entry-name = "master-kernel"; 731 #qcom,smem-state-cells = <1>; 732 }; 733 734 smp2p_slpi_in: slave-kernel { 735 qcom,entry-name = "slave-kernel"; 736 interrupt-controller; 737 #interrupt-cells = <2>; 738 }; 739 }; 740 741 soc: soc@0 { 742 #address-cells = <2>; 743 #size-cells = <2>; 744 ranges = <0 0 0 0 0x10 0>; 745 dma-ranges = <0 0 0 0 0x10 0>; 746 compatible = "simple-bus"; 747 748 gcc: clock-controller@100000 { 749 compatible = "qcom,gcc-sm8450"; 750 reg = <0x0 0x00100000 0x0 0x1f4200>; 751 #clock-cells = <1>; 752 #reset-cells = <1>; 753 #power-domain-cells = <1>; 754 clocks = <&rpmhcc RPMH_CXO_CLK>, 755 <&sleep_clk>, 756 <&pcie0_phy>, 757 <&pcie1_phy>, 758 <0>, 759 <&ufs_mem_phy 0>, 760 <&ufs_mem_phy 1>, 761 <&ufs_mem_phy 2>, 762 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 763 clock-names = "bi_tcxo", 764 "sleep_clk", 765 "pcie_0_pipe_clk", 766 "pcie_1_pipe_clk", 767 "pcie_1_phy_aux_clk", 768 "ufs_phy_rx_symbol_0_clk", 769 "ufs_phy_rx_symbol_1_clk", 770 "ufs_phy_tx_symbol_0_clk", 771 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 772 }; 773 774 gpi_dma2: dma-controller@800000 { 775 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 776 #dma-cells = <3>; 777 reg = <0 0x00800000 0 0x60000>; 778 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 790 dma-channels = <12>; 791 dma-channel-mask = <0x7e>; 792 iommus = <&apps_smmu 0x496 0x0>; 793 status = "disabled"; 794 }; 795 796 qupv3_id_2: geniqup@8c0000 { 797 compatible = "qcom,geni-se-qup"; 798 reg = <0x0 0x008c0000 0x0 0x2000>; 799 clock-names = "m-ahb", "s-ahb"; 800 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 801 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 802 iommus = <&apps_smmu 0x483 0x0>; 803 #address-cells = <2>; 804 #size-cells = <2>; 805 ranges; 806 status = "disabled"; 807 808 i2c15: i2c@880000 { 809 compatible = "qcom,geni-i2c"; 810 reg = <0x0 0x00880000 0x0 0x4000>; 811 clock-names = "se"; 812 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 813 pinctrl-names = "default"; 814 pinctrl-0 = <&qup_i2c15_data_clk>; 815 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 816 #address-cells = <1>; 817 #size-cells = <0>; 818 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 819 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 820 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 821 interconnect-names = "qup-core", "qup-config", "qup-memory"; 822 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 823 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 824 dma-names = "tx", "rx"; 825 status = "disabled"; 826 }; 827 828 spi15: spi@880000 { 829 compatible = "qcom,geni-spi"; 830 reg = <0x0 0x00880000 0x0 0x4000>; 831 clock-names = "se"; 832 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 833 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 834 pinctrl-names = "default"; 835 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 836 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 837 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 838 interconnect-names = "qup-core", "qup-config"; 839 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 840 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 841 dma-names = "tx", "rx"; 842 #address-cells = <1>; 843 #size-cells = <0>; 844 status = "disabled"; 845 }; 846 847 i2c16: i2c@884000 { 848 compatible = "qcom,geni-i2c"; 849 reg = <0x0 0x00884000 0x0 0x4000>; 850 clock-names = "se"; 851 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 852 pinctrl-names = "default"; 853 pinctrl-0 = <&qup_i2c16_data_clk>; 854 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 855 #address-cells = <1>; 856 #size-cells = <0>; 857 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 858 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 859 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 860 interconnect-names = "qup-core", "qup-config", "qup-memory"; 861 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 862 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 863 dma-names = "tx", "rx"; 864 status = "disabled"; 865 }; 866 867 spi16: spi@884000 { 868 compatible = "qcom,geni-spi"; 869 reg = <0x0 0x00884000 0x0 0x4000>; 870 clock-names = "se"; 871 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 872 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 873 pinctrl-names = "default"; 874 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 875 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 876 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 877 interconnect-names = "qup-core", "qup-config"; 878 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 879 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 880 dma-names = "tx", "rx"; 881 #address-cells = <1>; 882 #size-cells = <0>; 883 status = "disabled"; 884 }; 885 886 i2c17: i2c@888000 { 887 compatible = "qcom,geni-i2c"; 888 reg = <0x0 0x00888000 0x0 0x4000>; 889 clock-names = "se"; 890 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 891 pinctrl-names = "default"; 892 pinctrl-0 = <&qup_i2c17_data_clk>; 893 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 894 #address-cells = <1>; 895 #size-cells = <0>; 896 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 897 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 898 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 899 interconnect-names = "qup-core", "qup-config", "qup-memory"; 900 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 901 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 902 dma-names = "tx", "rx"; 903 status = "disabled"; 904 }; 905 906 spi17: spi@888000 { 907 compatible = "qcom,geni-spi"; 908 reg = <0x0 0x00888000 0x0 0x4000>; 909 clock-names = "se"; 910 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 911 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 912 pinctrl-names = "default"; 913 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 914 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 915 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 916 interconnect-names = "qup-core", "qup-config"; 917 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 918 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 919 dma-names = "tx", "rx"; 920 #address-cells = <1>; 921 #size-cells = <0>; 922 status = "disabled"; 923 }; 924 925 i2c18: i2c@88c000 { 926 compatible = "qcom,geni-i2c"; 927 reg = <0x0 0x0088c000 0x0 0x4000>; 928 clock-names = "se"; 929 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 930 pinctrl-names = "default"; 931 pinctrl-0 = <&qup_i2c18_data_clk>; 932 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 933 #address-cells = <1>; 934 #size-cells = <0>; 935 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 936 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 937 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 938 interconnect-names = "qup-core", "qup-config", "qup-memory"; 939 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 940 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 941 dma-names = "tx", "rx"; 942 status = "disabled"; 943 }; 944 945 spi18: spi@88c000 { 946 compatible = "qcom,geni-spi"; 947 reg = <0 0x0088c000 0 0x4000>; 948 clock-names = "se"; 949 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 950 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 951 pinctrl-names = "default"; 952 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 953 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 954 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 955 interconnect-names = "qup-core", "qup-config"; 956 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 957 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 958 dma-names = "tx", "rx"; 959 #address-cells = <1>; 960 #size-cells = <0>; 961 status = "disabled"; 962 }; 963 964 i2c19: i2c@890000 { 965 compatible = "qcom,geni-i2c"; 966 reg = <0x0 0x00890000 0x0 0x4000>; 967 clock-names = "se"; 968 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 969 pinctrl-names = "default"; 970 pinctrl-0 = <&qup_i2c19_data_clk>; 971 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 972 #address-cells = <1>; 973 #size-cells = <0>; 974 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 975 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 976 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 977 interconnect-names = "qup-core", "qup-config", "qup-memory"; 978 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 979 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 980 dma-names = "tx", "rx"; 981 status = "disabled"; 982 }; 983 984 spi19: spi@890000 { 985 compatible = "qcom,geni-spi"; 986 reg = <0 0x00890000 0 0x4000>; 987 clock-names = "se"; 988 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 989 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 990 pinctrl-names = "default"; 991 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 992 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 993 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 994 interconnect-names = "qup-core", "qup-config"; 995 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 996 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 997 dma-names = "tx", "rx"; 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 status = "disabled"; 1001 }; 1002 1003 i2c20: i2c@894000 { 1004 compatible = "qcom,geni-i2c"; 1005 reg = <0x0 0x00894000 0x0 0x4000>; 1006 clock-names = "se"; 1007 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1008 pinctrl-names = "default"; 1009 pinctrl-0 = <&qup_i2c20_data_clk>; 1010 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1011 #address-cells = <1>; 1012 #size-cells = <0>; 1013 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1014 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1015 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1016 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1017 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1018 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1019 dma-names = "tx", "rx"; 1020 status = "disabled"; 1021 }; 1022 1023 uart20: serial@894000 { 1024 compatible = "qcom,geni-uart"; 1025 reg = <0 0x00894000 0 0x4000>; 1026 clock-names = "se"; 1027 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1028 pinctrl-names = "default"; 1029 pinctrl-0 = <&qup_uart20_default>; 1030 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1031 status = "disabled"; 1032 }; 1033 1034 spi20: spi@894000 { 1035 compatible = "qcom,geni-spi"; 1036 reg = <0 0x00894000 0 0x4000>; 1037 clock-names = "se"; 1038 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1039 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1040 pinctrl-names = "default"; 1041 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1042 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1043 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1044 interconnect-names = "qup-core", "qup-config"; 1045 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1046 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1047 dma-names = "tx", "rx"; 1048 #address-cells = <1>; 1049 #size-cells = <0>; 1050 status = "disabled"; 1051 }; 1052 1053 i2c21: i2c@898000 { 1054 compatible = "qcom,geni-i2c"; 1055 reg = <0x0 0x00898000 0x0 0x4000>; 1056 clock-names = "se"; 1057 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1058 pinctrl-names = "default"; 1059 pinctrl-0 = <&qup_i2c21_data_clk>; 1060 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1061 #address-cells = <1>; 1062 #size-cells = <0>; 1063 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1064 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1065 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1066 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1067 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1068 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1069 dma-names = "tx", "rx"; 1070 status = "disabled"; 1071 }; 1072 1073 spi21: spi@898000 { 1074 compatible = "qcom,geni-spi"; 1075 reg = <0 0x00898000 0 0x4000>; 1076 clock-names = "se"; 1077 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1078 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1079 pinctrl-names = "default"; 1080 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1081 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1082 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1083 interconnect-names = "qup-core", "qup-config"; 1084 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1085 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1086 dma-names = "tx", "rx"; 1087 #address-cells = <1>; 1088 #size-cells = <0>; 1089 status = "disabled"; 1090 }; 1091 }; 1092 1093 gpi_dma0: dma-controller@900000 { 1094 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1095 #dma-cells = <3>; 1096 reg = <0 0x00900000 0 0x60000>; 1097 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1098 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1103 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1109 dma-channels = <12>; 1110 dma-channel-mask = <0x7e>; 1111 iommus = <&apps_smmu 0x5b6 0x0>; 1112 status = "disabled"; 1113 }; 1114 1115 qupv3_id_0: geniqup@9c0000 { 1116 compatible = "qcom,geni-se-qup"; 1117 reg = <0x0 0x009c0000 0x0 0x2000>; 1118 clock-names = "m-ahb", "s-ahb"; 1119 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1120 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1121 iommus = <&apps_smmu 0x5a3 0x0>; 1122 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>; 1123 interconnect-names = "qup-core"; 1124 #address-cells = <2>; 1125 #size-cells = <2>; 1126 ranges; 1127 status = "disabled"; 1128 1129 i2c0: i2c@980000 { 1130 compatible = "qcom,geni-i2c"; 1131 reg = <0x0 0x00980000 0x0 0x4000>; 1132 clock-names = "se"; 1133 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1134 pinctrl-names = "default"; 1135 pinctrl-0 = <&qup_i2c0_data_clk>; 1136 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1140 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1141 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1142 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1143 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1144 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1145 dma-names = "tx", "rx"; 1146 status = "disabled"; 1147 }; 1148 1149 spi0: spi@980000 { 1150 compatible = "qcom,geni-spi"; 1151 reg = <0x0 0x00980000 0x0 0x4000>; 1152 clock-names = "se"; 1153 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1154 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1155 pinctrl-names = "default"; 1156 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1157 power-domains = <&rpmhpd RPMHPD_CX>; 1158 operating-points-v2 = <&qup_opp_table_100mhz>; 1159 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1160 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1161 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1162 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1163 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1164 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1165 dma-names = "tx", "rx"; 1166 #address-cells = <1>; 1167 #size-cells = <0>; 1168 status = "disabled"; 1169 }; 1170 1171 i2c1: i2c@984000 { 1172 compatible = "qcom,geni-i2c"; 1173 reg = <0x0 0x00984000 0x0 0x4000>; 1174 clock-names = "se"; 1175 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1176 pinctrl-names = "default"; 1177 pinctrl-0 = <&qup_i2c1_data_clk>; 1178 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1179 #address-cells = <1>; 1180 #size-cells = <0>; 1181 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1182 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1183 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1184 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1185 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1186 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1187 dma-names = "tx", "rx"; 1188 status = "disabled"; 1189 }; 1190 1191 spi1: spi@984000 { 1192 compatible = "qcom,geni-spi"; 1193 reg = <0x0 0x00984000 0x0 0x4000>; 1194 clock-names = "se"; 1195 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1196 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1197 pinctrl-names = "default"; 1198 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1199 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1200 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1201 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1202 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1203 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1204 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1205 dma-names = "tx", "rx"; 1206 #address-cells = <1>; 1207 #size-cells = <0>; 1208 status = "disabled"; 1209 }; 1210 1211 i2c2: i2c@988000 { 1212 compatible = "qcom,geni-i2c"; 1213 reg = <0x0 0x00988000 0x0 0x4000>; 1214 clock-names = "se"; 1215 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1216 pinctrl-names = "default"; 1217 pinctrl-0 = <&qup_i2c2_data_clk>; 1218 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1219 #address-cells = <1>; 1220 #size-cells = <0>; 1221 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1222 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1223 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1224 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1225 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1226 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1227 dma-names = "tx", "rx"; 1228 status = "disabled"; 1229 }; 1230 1231 spi2: spi@988000 { 1232 compatible = "qcom,geni-spi"; 1233 reg = <0x0 0x00988000 0x0 0x4000>; 1234 clock-names = "se"; 1235 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1236 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1237 pinctrl-names = "default"; 1238 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1239 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1240 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1241 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1242 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1243 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1244 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1245 dma-names = "tx", "rx"; 1246 #address-cells = <1>; 1247 #size-cells = <0>; 1248 status = "disabled"; 1249 }; 1250 1251 1252 i2c3: i2c@98c000 { 1253 compatible = "qcom,geni-i2c"; 1254 reg = <0x0 0x0098c000 0x0 0x4000>; 1255 clock-names = "se"; 1256 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1257 pinctrl-names = "default"; 1258 pinctrl-0 = <&qup_i2c3_data_clk>; 1259 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1260 #address-cells = <1>; 1261 #size-cells = <0>; 1262 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1263 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1264 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1265 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1266 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1267 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1268 dma-names = "tx", "rx"; 1269 status = "disabled"; 1270 }; 1271 1272 spi3: spi@98c000 { 1273 compatible = "qcom,geni-spi"; 1274 reg = <0x0 0x0098c000 0x0 0x4000>; 1275 clock-names = "se"; 1276 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1277 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1278 pinctrl-names = "default"; 1279 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1280 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1281 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1282 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1283 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1284 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1285 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1286 dma-names = "tx", "rx"; 1287 #address-cells = <1>; 1288 #size-cells = <0>; 1289 status = "disabled"; 1290 }; 1291 1292 i2c4: i2c@990000 { 1293 compatible = "qcom,geni-i2c"; 1294 reg = <0x0 0x00990000 0x0 0x4000>; 1295 clock-names = "se"; 1296 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1297 pinctrl-names = "default"; 1298 pinctrl-0 = <&qup_i2c4_data_clk>; 1299 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1300 #address-cells = <1>; 1301 #size-cells = <0>; 1302 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1303 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1304 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1305 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1306 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1307 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1308 dma-names = "tx", "rx"; 1309 status = "disabled"; 1310 }; 1311 1312 spi4: spi@990000 { 1313 compatible = "qcom,geni-spi"; 1314 reg = <0x0 0x00990000 0x0 0x4000>; 1315 clock-names = "se"; 1316 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1317 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1318 pinctrl-names = "default"; 1319 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1320 power-domains = <&rpmhpd RPMHPD_CX>; 1321 operating-points-v2 = <&qup_opp_table_100mhz>; 1322 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1323 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1324 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1325 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1326 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1327 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1328 dma-names = "tx", "rx"; 1329 #address-cells = <1>; 1330 #size-cells = <0>; 1331 status = "disabled"; 1332 }; 1333 1334 i2c5: i2c@994000 { 1335 compatible = "qcom,geni-i2c"; 1336 reg = <0x0 0x00994000 0x0 0x4000>; 1337 clock-names = "se"; 1338 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1339 pinctrl-names = "default"; 1340 pinctrl-0 = <&qup_i2c5_data_clk>; 1341 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1342 #address-cells = <1>; 1343 #size-cells = <0>; 1344 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1345 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1346 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1347 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1348 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1349 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1350 dma-names = "tx", "rx"; 1351 status = "disabled"; 1352 }; 1353 1354 spi5: spi@994000 { 1355 compatible = "qcom,geni-spi"; 1356 reg = <0x0 0x00994000 0x0 0x4000>; 1357 clock-names = "se"; 1358 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1359 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1360 pinctrl-names = "default"; 1361 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1362 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1363 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1364 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1365 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1366 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1367 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1368 dma-names = "tx", "rx"; 1369 #address-cells = <1>; 1370 #size-cells = <0>; 1371 status = "disabled"; 1372 }; 1373 1374 1375 i2c6: i2c@998000 { 1376 compatible = "qcom,geni-i2c"; 1377 reg = <0x0 0x00998000 0x0 0x4000>; 1378 clock-names = "se"; 1379 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1380 pinctrl-names = "default"; 1381 pinctrl-0 = <&qup_i2c6_data_clk>; 1382 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1383 #address-cells = <1>; 1384 #size-cells = <0>; 1385 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1386 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1387 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1388 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1389 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1390 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1391 dma-names = "tx", "rx"; 1392 status = "disabled"; 1393 }; 1394 1395 spi6: spi@998000 { 1396 compatible = "qcom,geni-spi"; 1397 reg = <0x0 0x00998000 0x0 0x4000>; 1398 clock-names = "se"; 1399 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1400 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1401 pinctrl-names = "default"; 1402 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1403 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1404 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1405 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1406 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1407 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1408 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1409 dma-names = "tx", "rx"; 1410 #address-cells = <1>; 1411 #size-cells = <0>; 1412 status = "disabled"; 1413 }; 1414 1415 uart7: serial@99c000 { 1416 compatible = "qcom,geni-debug-uart"; 1417 reg = <0 0x0099c000 0 0x4000>; 1418 clock-names = "se"; 1419 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1420 pinctrl-names = "default"; 1421 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 1422 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1423 status = "disabled"; 1424 }; 1425 }; 1426 1427 gpi_dma1: dma-controller@a00000 { 1428 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1429 #dma-cells = <3>; 1430 reg = <0 0x00a00000 0 0x60000>; 1431 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1432 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1433 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1434 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1435 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1436 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1437 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1438 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1439 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1440 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1441 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1442 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1443 dma-channels = <12>; 1444 dma-channel-mask = <0x7e>; 1445 iommus = <&apps_smmu 0x56 0x0>; 1446 status = "disabled"; 1447 }; 1448 1449 qupv3_id_1: geniqup@ac0000 { 1450 compatible = "qcom,geni-se-qup"; 1451 reg = <0x0 0x00ac0000 0x0 0x6000>; 1452 clock-names = "m-ahb", "s-ahb"; 1453 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1454 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1455 iommus = <&apps_smmu 0x43 0x0>; 1456 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1457 interconnect-names = "qup-core"; 1458 #address-cells = <2>; 1459 #size-cells = <2>; 1460 ranges; 1461 status = "disabled"; 1462 1463 i2c8: i2c@a80000 { 1464 compatible = "qcom,geni-i2c"; 1465 reg = <0x0 0x00a80000 0x0 0x4000>; 1466 clock-names = "se"; 1467 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1468 pinctrl-names = "default"; 1469 pinctrl-0 = <&qup_i2c8_data_clk>; 1470 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1471 #address-cells = <1>; 1472 #size-cells = <0>; 1473 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1474 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1475 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1476 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1477 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1478 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1479 dma-names = "tx", "rx"; 1480 status = "disabled"; 1481 }; 1482 1483 spi8: spi@a80000 { 1484 compatible = "qcom,geni-spi"; 1485 reg = <0x0 0x00a80000 0x0 0x4000>; 1486 clock-names = "se"; 1487 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1488 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1489 pinctrl-names = "default"; 1490 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1491 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1492 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1493 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1494 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1495 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1496 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1497 dma-names = "tx", "rx"; 1498 #address-cells = <1>; 1499 #size-cells = <0>; 1500 status = "disabled"; 1501 }; 1502 1503 i2c9: i2c@a84000 { 1504 compatible = "qcom,geni-i2c"; 1505 reg = <0x0 0x00a84000 0x0 0x4000>; 1506 clock-names = "se"; 1507 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1508 pinctrl-names = "default"; 1509 pinctrl-0 = <&qup_i2c9_data_clk>; 1510 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1511 #address-cells = <1>; 1512 #size-cells = <0>; 1513 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1514 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1515 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1516 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1517 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1518 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1519 dma-names = "tx", "rx"; 1520 status = "disabled"; 1521 }; 1522 1523 spi9: spi@a84000 { 1524 compatible = "qcom,geni-spi"; 1525 reg = <0x0 0x00a84000 0x0 0x4000>; 1526 clock-names = "se"; 1527 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1528 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1529 pinctrl-names = "default"; 1530 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1531 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1532 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1533 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1534 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1535 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1536 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1537 dma-names = "tx", "rx"; 1538 #address-cells = <1>; 1539 #size-cells = <0>; 1540 status = "disabled"; 1541 }; 1542 1543 i2c10: i2c@a88000 { 1544 compatible = "qcom,geni-i2c"; 1545 reg = <0x0 0x00a88000 0x0 0x4000>; 1546 clock-names = "se"; 1547 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1548 pinctrl-names = "default"; 1549 pinctrl-0 = <&qup_i2c10_data_clk>; 1550 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1551 #address-cells = <1>; 1552 #size-cells = <0>; 1553 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1554 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1555 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1556 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1557 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1558 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1559 dma-names = "tx", "rx"; 1560 status = "disabled"; 1561 }; 1562 1563 spi10: spi@a88000 { 1564 compatible = "qcom,geni-spi"; 1565 reg = <0x0 0x00a88000 0x0 0x4000>; 1566 clock-names = "se"; 1567 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1568 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1569 pinctrl-names = "default"; 1570 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1571 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1572 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1573 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1574 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1575 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1576 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1577 dma-names = "tx", "rx"; 1578 #address-cells = <1>; 1579 #size-cells = <0>; 1580 status = "disabled"; 1581 }; 1582 1583 i2c11: i2c@a8c000 { 1584 compatible = "qcom,geni-i2c"; 1585 reg = <0x0 0x00a8c000 0x0 0x4000>; 1586 clock-names = "se"; 1587 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1588 pinctrl-names = "default"; 1589 pinctrl-0 = <&qup_i2c11_data_clk>; 1590 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1591 #address-cells = <1>; 1592 #size-cells = <0>; 1593 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1594 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1595 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1596 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1597 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1598 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1599 dma-names = "tx", "rx"; 1600 status = "disabled"; 1601 }; 1602 1603 spi11: spi@a8c000 { 1604 compatible = "qcom,geni-spi"; 1605 reg = <0x0 0x00a8c000 0x0 0x4000>; 1606 clock-names = "se"; 1607 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1608 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1609 pinctrl-names = "default"; 1610 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1611 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1612 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1613 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1614 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1615 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1616 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1617 dma-names = "tx", "rx"; 1618 #address-cells = <1>; 1619 #size-cells = <0>; 1620 status = "disabled"; 1621 }; 1622 1623 i2c12: i2c@a90000 { 1624 compatible = "qcom,geni-i2c"; 1625 reg = <0x0 0x00a90000 0x0 0x4000>; 1626 clock-names = "se"; 1627 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1628 pinctrl-names = "default"; 1629 pinctrl-0 = <&qup_i2c12_data_clk>; 1630 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1631 #address-cells = <1>; 1632 #size-cells = <0>; 1633 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1634 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1635 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1636 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1637 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1638 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1639 dma-names = "tx", "rx"; 1640 status = "disabled"; 1641 }; 1642 1643 spi12: spi@a90000 { 1644 compatible = "qcom,geni-spi"; 1645 reg = <0x0 0x00a90000 0x0 0x4000>; 1646 clock-names = "se"; 1647 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1648 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1649 pinctrl-names = "default"; 1650 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1651 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1652 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1653 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1654 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1655 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1656 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1657 dma-names = "tx", "rx"; 1658 #address-cells = <1>; 1659 #size-cells = <0>; 1660 status = "disabled"; 1661 }; 1662 1663 i2c13: i2c@a94000 { 1664 compatible = "qcom,geni-i2c"; 1665 reg = <0 0x00a94000 0 0x4000>; 1666 clock-names = "se"; 1667 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1668 pinctrl-names = "default"; 1669 pinctrl-0 = <&qup_i2c13_data_clk>; 1670 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1671 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1672 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1673 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1674 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1675 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1676 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1677 dma-names = "tx", "rx"; 1678 #address-cells = <1>; 1679 #size-cells = <0>; 1680 status = "disabled"; 1681 }; 1682 1683 spi13: spi@a94000 { 1684 compatible = "qcom,geni-spi"; 1685 reg = <0x0 0x00a94000 0x0 0x4000>; 1686 clock-names = "se"; 1687 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1688 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1689 pinctrl-names = "default"; 1690 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1691 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1692 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1693 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1694 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1695 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1696 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1697 dma-names = "tx", "rx"; 1698 #address-cells = <1>; 1699 #size-cells = <0>; 1700 status = "disabled"; 1701 }; 1702 1703 i2c14: i2c@a98000 { 1704 compatible = "qcom,geni-i2c"; 1705 reg = <0 0x00a98000 0 0x4000>; 1706 clock-names = "se"; 1707 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1708 pinctrl-names = "default"; 1709 pinctrl-0 = <&qup_i2c14_data_clk>; 1710 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1711 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1712 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1713 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1714 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1715 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1716 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1717 dma-names = "tx", "rx"; 1718 #address-cells = <1>; 1719 #size-cells = <0>; 1720 status = "disabled"; 1721 }; 1722 1723 spi14: spi@a98000 { 1724 compatible = "qcom,geni-spi"; 1725 reg = <0x0 0x00a98000 0x0 0x4000>; 1726 clock-names = "se"; 1727 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1728 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1729 pinctrl-names = "default"; 1730 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1731 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1732 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1733 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1734 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1735 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1736 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1737 dma-names = "tx", "rx"; 1738 #address-cells = <1>; 1739 #size-cells = <0>; 1740 status = "disabled"; 1741 }; 1742 }; 1743 1744 rng: rng@10c3000 { 1745 compatible = "qcom,sm8450-trng", "qcom,trng"; 1746 reg = <0 0x010c3000 0 0x1000>; 1747 }; 1748 1749 pcie0: pcie@1c00000 { 1750 compatible = "qcom,pcie-sm8450-pcie0"; 1751 reg = <0 0x01c00000 0 0x3000>, 1752 <0 0x60000000 0 0xf1d>, 1753 <0 0x60000f20 0 0xa8>, 1754 <0 0x60001000 0 0x1000>, 1755 <0 0x60100000 0 0x100000>; 1756 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1757 device_type = "pci"; 1758 linux,pci-domain = <0>; 1759 bus-range = <0x00 0xff>; 1760 num-lanes = <1>; 1761 1762 #address-cells = <3>; 1763 #size-cells = <2>; 1764 1765 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1766 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1767 1768 /* 1769 * MSIs for BDF (1:0.0) only works with Device ID 0x5980. 1770 * Hence, the IDs are swapped. 1771 */ 1772 msi-map = <0x0 &gic_its 0x5981 0x1>, 1773 <0x100 &gic_its 0x5980 0x1>; 1774 msi-map-mask = <0xff00>; 1775 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1776 interrupt-names = "msi"; 1777 #interrupt-cells = <1>; 1778 interrupt-map-mask = <0 0 0 0x7>; 1779 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1780 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1781 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1782 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1783 1784 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1785 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, 1786 <&pcie0_phy>, 1787 <&rpmhcc RPMH_CXO_CLK>, 1788 <&gcc GCC_PCIE_0_AUX_CLK>, 1789 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1790 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1791 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1792 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1793 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1794 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 1795 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1796 clock-names = "pipe", 1797 "pipe_mux", 1798 "phy_pipe", 1799 "ref", 1800 "aux", 1801 "cfg", 1802 "bus_master", 1803 "bus_slave", 1804 "slave_q2a", 1805 "ddrss_sf_tbu", 1806 "aggre0", 1807 "aggre1"; 1808 1809 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1810 <0x100 &apps_smmu 0x1c01 0x1>; 1811 1812 resets = <&gcc GCC_PCIE_0_BCR>; 1813 reset-names = "pci"; 1814 1815 power-domains = <&gcc PCIE_0_GDSC>; 1816 1817 phys = <&pcie0_phy>; 1818 phy-names = "pciephy"; 1819 1820 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; 1821 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; 1822 1823 pinctrl-names = "default"; 1824 pinctrl-0 = <&pcie0_default_state>; 1825 1826 status = "disabled"; 1827 }; 1828 1829 pcie0_phy: phy@1c06000 { 1830 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; 1831 reg = <0 0x01c06000 0 0x2000>; 1832 1833 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1834 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1835 <&gcc GCC_PCIE_0_CLKREF_EN>, 1836 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 1837 <&gcc GCC_PCIE_0_PIPE_CLK>; 1838 clock-names = "aux", 1839 "cfg_ahb", 1840 "ref", 1841 "rchng", 1842 "pipe"; 1843 1844 clock-output-names = "pcie_0_pipe_clk"; 1845 #clock-cells = <0>; 1846 1847 #phy-cells = <0>; 1848 1849 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1850 reset-names = "phy"; 1851 1852 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 1853 assigned-clock-rates = <100000000>; 1854 1855 status = "disabled"; 1856 }; 1857 1858 pcie1: pcie@1c08000 { 1859 compatible = "qcom,pcie-sm8450-pcie1"; 1860 reg = <0 0x01c08000 0 0x3000>, 1861 <0 0x40000000 0 0xf1d>, 1862 <0 0x40000f20 0 0xa8>, 1863 <0 0x40001000 0 0x1000>, 1864 <0 0x40100000 0 0x100000>; 1865 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1866 device_type = "pci"; 1867 linux,pci-domain = <1>; 1868 bus-range = <0x00 0xff>; 1869 num-lanes = <2>; 1870 1871 #address-cells = <3>; 1872 #size-cells = <2>; 1873 1874 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1875 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1876 1877 /* 1878 * MSIs for BDF (1:0.0) only works with Device ID 0x5a00. 1879 * Hence, the IDs are swapped. 1880 */ 1881 msi-map = <0x0 &gic_its 0x5a01 0x1>, 1882 <0x100 &gic_its 0x5a00 0x1>; 1883 msi-map-mask = <0xff00>; 1884 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1885 interrupt-names = "msi"; 1886 #interrupt-cells = <1>; 1887 interrupt-map-mask = <0 0 0 0x7>; 1888 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1889 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1890 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1891 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1892 1893 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1894 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 1895 <&pcie1_phy>, 1896 <&rpmhcc RPMH_CXO_CLK>, 1897 <&gcc GCC_PCIE_1_AUX_CLK>, 1898 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1899 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1900 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1901 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1902 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1903 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1904 clock-names = "pipe", 1905 "pipe_mux", 1906 "phy_pipe", 1907 "ref", 1908 "aux", 1909 "cfg", 1910 "bus_master", 1911 "bus_slave", 1912 "slave_q2a", 1913 "ddrss_sf_tbu", 1914 "aggre1"; 1915 1916 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1917 <0x100 &apps_smmu 0x1c81 0x1>; 1918 1919 resets = <&gcc GCC_PCIE_1_BCR>; 1920 reset-names = "pci"; 1921 1922 power-domains = <&gcc PCIE_1_GDSC>; 1923 1924 phys = <&pcie1_phy>; 1925 phy-names = "pciephy"; 1926 1927 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; 1928 wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; 1929 1930 pinctrl-names = "default"; 1931 pinctrl-0 = <&pcie1_default_state>; 1932 1933 status = "disabled"; 1934 }; 1935 1936 pcie1_phy: phy@1c0e000 { 1937 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy"; 1938 reg = <0 0x01c0e000 0 0x2000>; 1939 1940 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 1941 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1942 <&gcc GCC_PCIE_1_CLKREF_EN>, 1943 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 1944 <&gcc GCC_PCIE_1_PIPE_CLK>; 1945 clock-names = "aux", 1946 "cfg_ahb", 1947 "ref", 1948 "rchng", 1949 "pipe"; 1950 1951 clock-output-names = "pcie_1_pipe_clk"; 1952 #clock-cells = <0>; 1953 1954 #phy-cells = <0>; 1955 1956 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1957 reset-names = "phy"; 1958 1959 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 1960 assigned-clock-rates = <100000000>; 1961 1962 status = "disabled"; 1963 }; 1964 1965 config_noc: interconnect@1500000 { 1966 compatible = "qcom,sm8450-config-noc"; 1967 reg = <0 0x01500000 0 0x1c000>; 1968 #interconnect-cells = <2>; 1969 qcom,bcm-voters = <&apps_bcm_voter>; 1970 }; 1971 1972 system_noc: interconnect@1680000 { 1973 compatible = "qcom,sm8450-system-noc"; 1974 reg = <0 0x01680000 0 0x1e200>; 1975 #interconnect-cells = <2>; 1976 qcom,bcm-voters = <&apps_bcm_voter>; 1977 }; 1978 1979 pcie_noc: interconnect@16c0000 { 1980 compatible = "qcom,sm8450-pcie-anoc"; 1981 reg = <0 0x016c0000 0 0xe280>; 1982 #interconnect-cells = <2>; 1983 qcom,bcm-voters = <&apps_bcm_voter>; 1984 }; 1985 1986 aggre1_noc: interconnect@16e0000 { 1987 compatible = "qcom,sm8450-aggre1-noc"; 1988 reg = <0 0x016e0000 0 0x1c080>; 1989 #interconnect-cells = <2>; 1990 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1991 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1992 qcom,bcm-voters = <&apps_bcm_voter>; 1993 }; 1994 1995 aggre2_noc: interconnect@1700000 { 1996 compatible = "qcom,sm8450-aggre2-noc"; 1997 reg = <0 0x01700000 0 0x31080>; 1998 #interconnect-cells = <2>; 1999 qcom,bcm-voters = <&apps_bcm_voter>; 2000 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 2001 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 2002 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2003 <&rpmhcc RPMH_IPA_CLK>; 2004 }; 2005 2006 mmss_noc: interconnect@1740000 { 2007 compatible = "qcom,sm8450-mmss-noc"; 2008 reg = <0 0x01740000 0 0x1f080>; 2009 #interconnect-cells = <2>; 2010 qcom,bcm-voters = <&apps_bcm_voter>; 2011 }; 2012 2013 tcsr_mutex: hwlock@1f40000 { 2014 compatible = "qcom,tcsr-mutex"; 2015 reg = <0x0 0x01f40000 0x0 0x40000>; 2016 #hwlock-cells = <1>; 2017 }; 2018 2019 tcsr: syscon@1fc0000 { 2020 compatible = "qcom,sm8450-tcsr", "syscon"; 2021 reg = <0x0 0x1fc0000 0x0 0x30000>; 2022 }; 2023 2024 gpu: gpu@3d00000 { 2025 compatible = "qcom,adreno-730.1", "qcom,adreno"; 2026 reg = <0x0 0x03d00000 0x0 0x40000>, 2027 <0x0 0x03d9e000 0x0 0x1000>, 2028 <0x0 0x03d61000 0x0 0x800>; 2029 reg-names = "kgsl_3d0_reg_memory", 2030 "cx_mem", 2031 "cx_dbgc"; 2032 2033 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2034 2035 iommus = <&adreno_smmu 0 0x400>, 2036 <&adreno_smmu 1 0x400>; 2037 2038 operating-points-v2 = <&gpu_opp_table>; 2039 2040 qcom,gmu = <&gmu>; 2041 2042 status = "disabled"; 2043 2044 zap-shader { 2045 memory-region = <&gpu_micro_code_mem>; 2046 }; 2047 2048 gpu_opp_table: opp-table { 2049 compatible = "operating-points-v2"; 2050 2051 opp-818000000 { 2052 opp-hz = /bits/ 64 <818000000>; 2053 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2054 }; 2055 2056 opp-791000000 { 2057 opp-hz = /bits/ 64 <791000000>; 2058 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2059 }; 2060 2061 opp-734000000 { 2062 opp-hz = /bits/ 64 <734000000>; 2063 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2064 }; 2065 2066 opp-640000000 { 2067 opp-hz = /bits/ 64 <640000000>; 2068 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2069 }; 2070 2071 opp-599000000 { 2072 opp-hz = /bits/ 64 <599000000>; 2073 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2074 }; 2075 2076 opp-545000000 { 2077 opp-hz = /bits/ 64 <545000000>; 2078 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2079 }; 2080 2081 opp-492000000 { 2082 opp-hz = /bits/ 64 <492000000>; 2083 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2084 }; 2085 2086 opp-421000000 { 2087 opp-hz = /bits/ 64 <421000000>; 2088 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 2089 }; 2090 2091 opp-350000000 { 2092 opp-hz = /bits/ 64 <350000000>; 2093 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2094 }; 2095 2096 opp-317000000 { 2097 opp-hz = /bits/ 64 <317000000>; 2098 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2099 }; 2100 2101 opp-285000000 { 2102 opp-hz = /bits/ 64 <285000000>; 2103 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 2104 }; 2105 2106 opp-220000000 { 2107 opp-hz = /bits/ 64 <220000000>; 2108 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 2109 }; 2110 }; 2111 }; 2112 2113 gmu: gmu@3d6a000 { 2114 compatible = "qcom,adreno-gmu-730.1", "qcom,adreno-gmu"; 2115 reg = <0x0 0x03d6a000 0x0 0x35000>, 2116 <0x0 0x03d50000 0x0 0x10000>, 2117 <0x0 0x0b290000 0x0 0x10000>; 2118 reg-names = "gmu", "rscc", "gmu_pdc"; 2119 2120 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2121 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2122 interrupt-names = "hfi", "gmu"; 2123 2124 clocks = <&gpucc GPU_CC_AHB_CLK>, 2125 <&gpucc GPU_CC_CX_GMU_CLK>, 2126 <&gpucc GPU_CC_CXO_CLK>, 2127 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2128 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2129 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2130 <&gpucc GPU_CC_DEMET_CLK>; 2131 clock-names = "ahb", 2132 "gmu", 2133 "cxo", 2134 "axi", 2135 "memnoc", 2136 "hub", 2137 "demet"; 2138 2139 power-domains = <&gpucc GPU_CX_GDSC>, 2140 <&gpucc GPU_GX_GDSC>; 2141 power-domain-names = "cx", 2142 "gx"; 2143 2144 iommus = <&adreno_smmu 5 0x400>; 2145 2146 qcom,qmp = <&aoss_qmp>; 2147 2148 operating-points-v2 = <&gmu_opp_table>; 2149 2150 gmu_opp_table: opp-table { 2151 compatible = "operating-points-v2"; 2152 2153 opp-500000000 { 2154 opp-hz = /bits/ 64 <500000000>; 2155 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2156 }; 2157 2158 opp-200000000 { 2159 opp-hz = /bits/ 64 <200000000>; 2160 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2161 }; 2162 }; 2163 }; 2164 2165 gpucc: clock-controller@3d90000 { 2166 compatible = "qcom,sm8450-gpucc"; 2167 reg = <0x0 0x03d90000 0x0 0xa000>; 2168 clocks = <&rpmhcc RPMH_CXO_CLK>, 2169 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2170 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2171 #clock-cells = <1>; 2172 #reset-cells = <1>; 2173 #power-domain-cells = <1>; 2174 }; 2175 2176 adreno_smmu: iommu@3da0000 { 2177 compatible = "qcom,sm8450-smmu-500", "qcom,adreno-smmu", 2178 "qcom,smmu-500", "arm,mmu-500"; 2179 reg = <0x0 0x03da0000 0x0 0x40000>; 2180 #iommu-cells = <2>; 2181 #global-interrupts = <1>; 2182 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2183 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2184 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2185 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2186 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2187 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2188 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2189 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2190 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2191 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2192 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2193 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2194 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 2195 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, 2196 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, 2197 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 2198 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, 2199 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>, 2200 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>, 2201 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>, 2202 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 2203 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 2204 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>, 2205 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 2206 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>, 2207 <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>; 2208 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2209 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2210 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2211 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2212 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2213 <&gpucc GPU_CC_AHB_CLK>; 2214 clock-names = "gmu", 2215 "hub", 2216 "hlos", 2217 "bus", 2218 "iface", 2219 "ahb"; 2220 power-domains = <&gpucc GPU_CX_GDSC>; 2221 dma-coherent; 2222 }; 2223 2224 usb_1_hsphy: phy@88e3000 { 2225 compatible = "qcom,sm8450-usb-hs-phy", 2226 "qcom,usb-snps-hs-7nm-phy"; 2227 reg = <0 0x088e3000 0 0x400>; 2228 status = "disabled"; 2229 #phy-cells = <0>; 2230 2231 clocks = <&rpmhcc RPMH_CXO_CLK>; 2232 clock-names = "ref"; 2233 2234 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2235 }; 2236 2237 usb_1_qmpphy: phy@88e8000 { 2238 compatible = "qcom,sm8450-qmp-usb3-dp-phy"; 2239 reg = <0 0x088e8000 0 0x3000>; 2240 2241 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2242 <&rpmhcc RPMH_CXO_CLK>, 2243 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2244 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2245 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2246 2247 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2248 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2249 reset-names = "phy", "common"; 2250 2251 #clock-cells = <1>; 2252 #phy-cells = <1>; 2253 2254 status = "disabled"; 2255 2256 ports { 2257 #address-cells = <1>; 2258 #size-cells = <0>; 2259 2260 port@0 { 2261 reg = <0>; 2262 2263 usb_1_qmpphy_out: endpoint { 2264 }; 2265 }; 2266 2267 port@1 { 2268 reg = <1>; 2269 2270 usb_1_qmpphy_usb_ss_in: endpoint { 2271 }; 2272 }; 2273 2274 port@2 { 2275 reg = <2>; 2276 2277 usb_1_qmpphy_dp_in: endpoint { 2278 }; 2279 }; 2280 }; 2281 }; 2282 2283 remoteproc_slpi: remoteproc@2400000 { 2284 compatible = "qcom,sm8450-slpi-pas"; 2285 reg = <0 0x02400000 0 0x4000>; 2286 2287 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2288 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2289 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2290 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2291 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2292 interrupt-names = "wdog", "fatal", "ready", 2293 "handover", "stop-ack"; 2294 2295 clocks = <&rpmhcc RPMH_CXO_CLK>; 2296 clock-names = "xo"; 2297 2298 power-domains = <&rpmhpd RPMHPD_LCX>, 2299 <&rpmhpd RPMHPD_LMX>; 2300 power-domain-names = "lcx", "lmx"; 2301 2302 memory-region = <&slpi_mem>; 2303 2304 qcom,qmp = <&aoss_qmp>; 2305 2306 qcom,smem-states = <&smp2p_slpi_out 0>; 2307 qcom,smem-state-names = "stop"; 2308 2309 status = "disabled"; 2310 2311 glink-edge { 2312 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2313 IPCC_MPROC_SIGNAL_GLINK_QMP 2314 IRQ_TYPE_EDGE_RISING>; 2315 mboxes = <&ipcc IPCC_CLIENT_SLPI 2316 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2317 2318 label = "slpi"; 2319 qcom,remote-pid = <3>; 2320 2321 fastrpc { 2322 compatible = "qcom,fastrpc"; 2323 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2324 label = "sdsp"; 2325 #address-cells = <1>; 2326 #size-cells = <0>; 2327 2328 compute-cb@1 { 2329 compatible = "qcom,fastrpc-compute-cb"; 2330 reg = <1>; 2331 iommus = <&apps_smmu 0x0541 0x0>; 2332 }; 2333 2334 compute-cb@2 { 2335 compatible = "qcom,fastrpc-compute-cb"; 2336 reg = <2>; 2337 iommus = <&apps_smmu 0x0542 0x0>; 2338 }; 2339 2340 compute-cb@3 { 2341 compatible = "qcom,fastrpc-compute-cb"; 2342 reg = <3>; 2343 iommus = <&apps_smmu 0x0543 0x0>; 2344 /* note: shared-cb = <4> in downstream */ 2345 }; 2346 }; 2347 }; 2348 }; 2349 2350 wsa2macro: codec@31e0000 { 2351 compatible = "qcom,sm8450-lpass-wsa-macro"; 2352 reg = <0 0x031e0000 0 0x1000>; 2353 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2354 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2355 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2356 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2357 <&vamacro>; 2358 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2359 2360 #clock-cells = <0>; 2361 clock-output-names = "wsa2-mclk"; 2362 #sound-dai-cells = <1>; 2363 }; 2364 2365 swr4: soundwire@31f0000 { 2366 compatible = "qcom,soundwire-v1.7.0"; 2367 reg = <0 0x031f0000 0 0x2000>; 2368 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2369 clocks = <&wsa2macro>; 2370 clock-names = "iface"; 2371 label = "WSA2"; 2372 2373 pinctrl-0 = <&wsa2_swr_active>; 2374 pinctrl-names = "default"; 2375 2376 qcom,din-ports = <2>; 2377 qcom,dout-ports = <6>; 2378 2379 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2380 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2381 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2382 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2383 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2384 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2385 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2386 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2387 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2388 2389 #address-cells = <2>; 2390 #size-cells = <0>; 2391 #sound-dai-cells = <1>; 2392 status = "disabled"; 2393 }; 2394 2395 rxmacro: codec@3200000 { 2396 compatible = "qcom,sm8450-lpass-rx-macro"; 2397 reg = <0 0x03200000 0 0x1000>; 2398 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2399 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2400 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2401 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2402 <&vamacro>; 2403 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2404 2405 #clock-cells = <0>; 2406 clock-output-names = "mclk"; 2407 #sound-dai-cells = <1>; 2408 }; 2409 2410 swr1: soundwire@3210000 { 2411 compatible = "qcom,soundwire-v1.7.0"; 2412 reg = <0 0x03210000 0 0x2000>; 2413 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2414 clocks = <&rxmacro>; 2415 clock-names = "iface"; 2416 label = "RX"; 2417 qcom,din-ports = <0>; 2418 qcom,dout-ports = <5>; 2419 2420 pinctrl-0 = <&rx_swr_active>; 2421 pinctrl-names = "default"; 2422 2423 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2424 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; 2425 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2426 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2427 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2428 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2429 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2430 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2431 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2432 2433 #address-cells = <2>; 2434 #size-cells = <0>; 2435 #sound-dai-cells = <1>; 2436 status = "disabled"; 2437 }; 2438 2439 txmacro: codec@3220000 { 2440 compatible = "qcom,sm8450-lpass-tx-macro"; 2441 reg = <0 0x03220000 0 0x1000>; 2442 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2443 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2444 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2445 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2446 <&vamacro>; 2447 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2448 2449 #clock-cells = <0>; 2450 clock-output-names = "mclk"; 2451 #sound-dai-cells = <1>; 2452 }; 2453 2454 wsamacro: codec@3240000 { 2455 compatible = "qcom,sm8450-lpass-wsa-macro"; 2456 reg = <0 0x03240000 0 0x1000>; 2457 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2458 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2459 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2460 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2461 <&vamacro>; 2462 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2463 2464 #clock-cells = <0>; 2465 clock-output-names = "mclk"; 2466 #sound-dai-cells = <1>; 2467 }; 2468 2469 swr0: soundwire@3250000 { 2470 compatible = "qcom,soundwire-v1.7.0"; 2471 reg = <0 0x03250000 0 0x2000>; 2472 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2473 clocks = <&wsamacro>; 2474 clock-names = "iface"; 2475 label = "WSA"; 2476 2477 pinctrl-0 = <&wsa_swr_active>; 2478 pinctrl-names = "default"; 2479 2480 qcom,din-ports = <2>; 2481 qcom,dout-ports = <6>; 2482 2483 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2484 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2485 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2486 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2487 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2488 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2489 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2490 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2491 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2492 2493 #address-cells = <2>; 2494 #size-cells = <0>; 2495 #sound-dai-cells = <1>; 2496 status = "disabled"; 2497 }; 2498 2499 swr2: soundwire@33b0000 { 2500 compatible = "qcom,soundwire-v1.7.0"; 2501 reg = <0 0x033b0000 0 0x2000>; 2502 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2503 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2504 interrupt-names = "core", "wakeup"; 2505 2506 clocks = <&txmacro>; 2507 clock-names = "iface"; 2508 label = "TX"; 2509 2510 pinctrl-0 = <&tx_swr_active>; 2511 pinctrl-names = "default"; 2512 2513 qcom,din-ports = <4>; 2514 qcom,dout-ports = <0>; 2515 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2516 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 2517 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2518 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2519 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2520 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2521 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2522 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2523 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 2524 2525 #address-cells = <2>; 2526 #size-cells = <0>; 2527 #sound-dai-cells = <1>; 2528 status = "disabled"; 2529 }; 2530 2531 vamacro: codec@33f0000 { 2532 compatible = "qcom,sm8450-lpass-va-macro"; 2533 reg = <0 0x033f0000 0 0x1000>; 2534 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2535 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2536 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2537 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2538 clock-names = "mclk", "macro", "dcodec", "npl"; 2539 2540 #clock-cells = <0>; 2541 clock-output-names = "fsgen"; 2542 #sound-dai-cells = <1>; 2543 status = "disabled"; 2544 }; 2545 2546 remoteproc_adsp: remoteproc@30000000 { 2547 compatible = "qcom,sm8450-adsp-pas"; 2548 reg = <0 0x30000000 0 0x100>; 2549 2550 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2551 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2552 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2553 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2554 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2555 interrupt-names = "wdog", "fatal", "ready", 2556 "handover", "stop-ack"; 2557 2558 clocks = <&rpmhcc RPMH_CXO_CLK>; 2559 clock-names = "xo"; 2560 2561 power-domains = <&rpmhpd RPMHPD_LCX>, 2562 <&rpmhpd RPMHPD_LMX>; 2563 power-domain-names = "lcx", "lmx"; 2564 2565 memory-region = <&adsp_mem>; 2566 2567 qcom,qmp = <&aoss_qmp>; 2568 2569 qcom,smem-states = <&smp2p_adsp_out 0>; 2570 qcom,smem-state-names = "stop"; 2571 2572 status = "disabled"; 2573 2574 remoteproc_adsp_glink: glink-edge { 2575 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2576 IPCC_MPROC_SIGNAL_GLINK_QMP 2577 IRQ_TYPE_EDGE_RISING>; 2578 mboxes = <&ipcc IPCC_CLIENT_LPASS 2579 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2580 2581 label = "lpass"; 2582 qcom,remote-pid = <2>; 2583 2584 gpr { 2585 compatible = "qcom,gpr"; 2586 qcom,glink-channels = "adsp_apps"; 2587 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2588 qcom,intents = <512 20>; 2589 #address-cells = <1>; 2590 #size-cells = <0>; 2591 2592 q6apm: service@1 { 2593 compatible = "qcom,q6apm"; 2594 reg = <GPR_APM_MODULE_IID>; 2595 #sound-dai-cells = <0>; 2596 qcom,protection-domain = "avs/audio", 2597 "msm/adsp/audio_pd"; 2598 2599 q6apmdai: dais { 2600 compatible = "qcom,q6apm-dais"; 2601 iommus = <&apps_smmu 0x1801 0x0>; 2602 }; 2603 2604 q6apmbedai: bedais { 2605 compatible = "qcom,q6apm-lpass-dais"; 2606 #sound-dai-cells = <1>; 2607 }; 2608 }; 2609 2610 q6prm: service@2 { 2611 compatible = "qcom,q6prm"; 2612 reg = <GPR_PRM_MODULE_IID>; 2613 qcom,protection-domain = "avs/audio", 2614 "msm/adsp/audio_pd"; 2615 2616 q6prmcc: clock-controller { 2617 compatible = "qcom,q6prm-lpass-clocks"; 2618 #clock-cells = <2>; 2619 }; 2620 }; 2621 }; 2622 2623 fastrpc { 2624 compatible = "qcom,fastrpc"; 2625 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2626 label = "adsp"; 2627 #address-cells = <1>; 2628 #size-cells = <0>; 2629 2630 compute-cb@3 { 2631 compatible = "qcom,fastrpc-compute-cb"; 2632 reg = <3>; 2633 iommus = <&apps_smmu 0x1803 0x0>; 2634 }; 2635 2636 compute-cb@4 { 2637 compatible = "qcom,fastrpc-compute-cb"; 2638 reg = <4>; 2639 iommus = <&apps_smmu 0x1804 0x0>; 2640 }; 2641 2642 compute-cb@5 { 2643 compatible = "qcom,fastrpc-compute-cb"; 2644 reg = <5>; 2645 iommus = <&apps_smmu 0x1805 0x0>; 2646 }; 2647 }; 2648 }; 2649 }; 2650 2651 remoteproc_cdsp: remoteproc@32300000 { 2652 compatible = "qcom,sm8450-cdsp-pas"; 2653 reg = <0 0x32300000 0 0x1400000>; 2654 2655 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2656 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2657 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2658 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2659 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 2660 interrupt-names = "wdog", "fatal", "ready", 2661 "handover", "stop-ack"; 2662 2663 clocks = <&rpmhcc RPMH_CXO_CLK>; 2664 clock-names = "xo"; 2665 2666 power-domains = <&rpmhpd RPMHPD_CX>, 2667 <&rpmhpd RPMHPD_MXC>; 2668 power-domain-names = "cx", "mxc"; 2669 2670 memory-region = <&cdsp_mem>; 2671 2672 qcom,qmp = <&aoss_qmp>; 2673 2674 qcom,smem-states = <&smp2p_cdsp_out 0>; 2675 qcom,smem-state-names = "stop"; 2676 2677 status = "disabled"; 2678 2679 glink-edge { 2680 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2681 IPCC_MPROC_SIGNAL_GLINK_QMP 2682 IRQ_TYPE_EDGE_RISING>; 2683 mboxes = <&ipcc IPCC_CLIENT_CDSP 2684 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2685 2686 label = "cdsp"; 2687 qcom,remote-pid = <5>; 2688 2689 fastrpc { 2690 compatible = "qcom,fastrpc"; 2691 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2692 label = "cdsp"; 2693 #address-cells = <1>; 2694 #size-cells = <0>; 2695 2696 compute-cb@1 { 2697 compatible = "qcom,fastrpc-compute-cb"; 2698 reg = <1>; 2699 iommus = <&apps_smmu 0x2161 0x0400>, 2700 <&apps_smmu 0x1021 0x1420>; 2701 }; 2702 2703 compute-cb@2 { 2704 compatible = "qcom,fastrpc-compute-cb"; 2705 reg = <2>; 2706 iommus = <&apps_smmu 0x2162 0x0400>, 2707 <&apps_smmu 0x1022 0x1420>; 2708 }; 2709 2710 compute-cb@3 { 2711 compatible = "qcom,fastrpc-compute-cb"; 2712 reg = <3>; 2713 iommus = <&apps_smmu 0x2163 0x0400>, 2714 <&apps_smmu 0x1023 0x1420>; 2715 }; 2716 2717 compute-cb@4 { 2718 compatible = "qcom,fastrpc-compute-cb"; 2719 reg = <4>; 2720 iommus = <&apps_smmu 0x2164 0x0400>, 2721 <&apps_smmu 0x1024 0x1420>; 2722 }; 2723 2724 compute-cb@5 { 2725 compatible = "qcom,fastrpc-compute-cb"; 2726 reg = <5>; 2727 iommus = <&apps_smmu 0x2165 0x0400>, 2728 <&apps_smmu 0x1025 0x1420>; 2729 }; 2730 2731 compute-cb@6 { 2732 compatible = "qcom,fastrpc-compute-cb"; 2733 reg = <6>; 2734 iommus = <&apps_smmu 0x2166 0x0400>, 2735 <&apps_smmu 0x1026 0x1420>; 2736 }; 2737 2738 compute-cb@7 { 2739 compatible = "qcom,fastrpc-compute-cb"; 2740 reg = <7>; 2741 iommus = <&apps_smmu 0x2167 0x0400>, 2742 <&apps_smmu 0x1027 0x1420>; 2743 }; 2744 2745 compute-cb@8 { 2746 compatible = "qcom,fastrpc-compute-cb"; 2747 reg = <8>; 2748 iommus = <&apps_smmu 0x2168 0x0400>, 2749 <&apps_smmu 0x1028 0x1420>; 2750 }; 2751 2752 /* note: secure cb9 in downstream */ 2753 }; 2754 }; 2755 }; 2756 2757 remoteproc_mpss: remoteproc@4080000 { 2758 compatible = "qcom,sm8450-mpss-pas"; 2759 reg = <0x0 0x04080000 0x0 0x4040>; 2760 2761 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2762 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2763 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2764 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2765 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2766 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2767 interrupt-names = "wdog", "fatal", "ready", "handover", 2768 "stop-ack", "shutdown-ack"; 2769 2770 clocks = <&rpmhcc RPMH_CXO_CLK>; 2771 clock-names = "xo"; 2772 2773 power-domains = <&rpmhpd RPMHPD_CX>, 2774 <&rpmhpd RPMHPD_MSS>; 2775 power-domain-names = "cx", "mss"; 2776 2777 memory-region = <&mpss_mem>; 2778 2779 qcom,qmp = <&aoss_qmp>; 2780 2781 qcom,smem-states = <&smp2p_modem_out 0>; 2782 qcom,smem-state-names = "stop"; 2783 2784 status = "disabled"; 2785 2786 glink-edge { 2787 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2788 IPCC_MPROC_SIGNAL_GLINK_QMP 2789 IRQ_TYPE_EDGE_RISING>; 2790 mboxes = <&ipcc IPCC_CLIENT_MPSS 2791 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2792 label = "modem"; 2793 qcom,remote-pid = <1>; 2794 }; 2795 }; 2796 2797 videocc: clock-controller@aaf0000 { 2798 compatible = "qcom,sm8450-videocc"; 2799 reg = <0 0x0aaf0000 0 0x10000>; 2800 clocks = <&rpmhcc RPMH_CXO_CLK>, 2801 <&gcc GCC_VIDEO_AHB_CLK>; 2802 power-domains = <&rpmhpd RPMHPD_MMCX>; 2803 required-opps = <&rpmhpd_opp_low_svs>; 2804 #clock-cells = <1>; 2805 #reset-cells = <1>; 2806 #power-domain-cells = <1>; 2807 }; 2808 2809 cci0: cci@ac15000 { 2810 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; 2811 reg = <0 0x0ac15000 0 0x1000>; 2812 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 2813 power-domains = <&camcc TITAN_TOP_GDSC>; 2814 2815 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 2816 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 2817 <&camcc CAM_CC_CPAS_AHB_CLK>, 2818 <&camcc CAM_CC_CCI_0_CLK>, 2819 <&camcc CAM_CC_CCI_0_CLK_SRC>; 2820 clock-names = "camnoc_axi", 2821 "slow_ahb_src", 2822 "cpas_ahb", 2823 "cci", 2824 "cci_src"; 2825 pinctrl-0 = <&cci0_default &cci1_default>; 2826 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 2827 pinctrl-names = "default", "sleep"; 2828 2829 status = "disabled"; 2830 #address-cells = <1>; 2831 #size-cells = <0>; 2832 2833 cci0_i2c0: i2c-bus@0 { 2834 reg = <0>; 2835 clock-frequency = <1000000>; 2836 #address-cells = <1>; 2837 #size-cells = <0>; 2838 }; 2839 2840 cci0_i2c1: i2c-bus@1 { 2841 reg = <1>; 2842 clock-frequency = <1000000>; 2843 #address-cells = <1>; 2844 #size-cells = <0>; 2845 }; 2846 }; 2847 2848 cci1: cci@ac16000 { 2849 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; 2850 reg = <0 0x0ac16000 0 0x1000>; 2851 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 2852 power-domains = <&camcc TITAN_TOP_GDSC>; 2853 2854 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 2855 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 2856 <&camcc CAM_CC_CPAS_AHB_CLK>, 2857 <&camcc CAM_CC_CCI_1_CLK>, 2858 <&camcc CAM_CC_CCI_1_CLK_SRC>; 2859 clock-names = "camnoc_axi", 2860 "slow_ahb_src", 2861 "cpas_ahb", 2862 "cci", 2863 "cci_src"; 2864 pinctrl-0 = <&cci2_default &cci3_default>; 2865 pinctrl-1 = <&cci2_sleep &cci3_sleep>; 2866 pinctrl-names = "default", "sleep"; 2867 2868 status = "disabled"; 2869 #address-cells = <1>; 2870 #size-cells = <0>; 2871 2872 cci1_i2c0: i2c-bus@0 { 2873 reg = <0>; 2874 clock-frequency = <1000000>; 2875 #address-cells = <1>; 2876 #size-cells = <0>; 2877 }; 2878 2879 cci1_i2c1: i2c-bus@1 { 2880 reg = <1>; 2881 clock-frequency = <1000000>; 2882 #address-cells = <1>; 2883 #size-cells = <0>; 2884 }; 2885 }; 2886 2887 camcc: clock-controller@ade0000 { 2888 compatible = "qcom,sm8450-camcc"; 2889 reg = <0 0x0ade0000 0 0x20000>; 2890 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 2891 <&rpmhcc RPMH_CXO_CLK>, 2892 <&rpmhcc RPMH_CXO_CLK_A>, 2893 <&sleep_clk>; 2894 power-domains = <&rpmhpd RPMHPD_MMCX>; 2895 required-opps = <&rpmhpd_opp_low_svs>; 2896 #clock-cells = <1>; 2897 #reset-cells = <1>; 2898 #power-domain-cells = <1>; 2899 status = "disabled"; 2900 }; 2901 2902 mdss: display-subsystem@ae00000 { 2903 compatible = "qcom,sm8450-mdss"; 2904 reg = <0 0x0ae00000 0 0x1000>; 2905 reg-names = "mdss"; 2906 2907 /* same path used twice */ 2908 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, 2909 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, 2910 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2911 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 2912 interconnect-names = "mdp0-mem", 2913 "mdp1-mem", 2914 "cpu-cfg"; 2915 2916 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2917 2918 power-domains = <&dispcc MDSS_GDSC>; 2919 2920 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2921 <&gcc GCC_DISP_HF_AXI_CLK>, 2922 <&gcc GCC_DISP_SF_AXI_CLK>, 2923 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2924 2925 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2926 interrupt-controller; 2927 #interrupt-cells = <1>; 2928 2929 iommus = <&apps_smmu 0x2800 0x402>; 2930 2931 #address-cells = <2>; 2932 #size-cells = <2>; 2933 ranges; 2934 2935 status = "disabled"; 2936 2937 mdss_mdp: display-controller@ae01000 { 2938 compatible = "qcom,sm8450-dpu"; 2939 reg = <0 0x0ae01000 0 0x8f000>, 2940 <0 0x0aeb0000 0 0x2008>; 2941 reg-names = "mdp", "vbif"; 2942 2943 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2944 <&gcc GCC_DISP_SF_AXI_CLK>, 2945 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2946 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2947 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2948 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2949 clock-names = "bus", 2950 "nrt_bus", 2951 "iface", 2952 "lut", 2953 "core", 2954 "vsync"; 2955 2956 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2957 assigned-clock-rates = <19200000>; 2958 2959 operating-points-v2 = <&mdp_opp_table>; 2960 power-domains = <&rpmhpd RPMHPD_MMCX>; 2961 2962 interrupt-parent = <&mdss>; 2963 interrupts = <0>; 2964 2965 ports { 2966 #address-cells = <1>; 2967 #size-cells = <0>; 2968 2969 port@0 { 2970 reg = <0>; 2971 dpu_intf1_out: endpoint { 2972 remote-endpoint = <&mdss_dsi0_in>; 2973 }; 2974 }; 2975 2976 port@1 { 2977 reg = <1>; 2978 dpu_intf2_out: endpoint { 2979 remote-endpoint = <&mdss_dsi1_in>; 2980 }; 2981 }; 2982 2983 port@2 { 2984 reg = <2>; 2985 dpu_intf0_out: endpoint { 2986 remote-endpoint = <&mdss_dp0_in>; 2987 }; 2988 }; 2989 }; 2990 2991 mdp_opp_table: opp-table { 2992 compatible = "operating-points-v2"; 2993 2994 opp-172000000 { 2995 opp-hz = /bits/ 64 <172000000>; 2996 required-opps = <&rpmhpd_opp_low_svs_d1>; 2997 }; 2998 2999 opp-200000000 { 3000 opp-hz = /bits/ 64 <200000000>; 3001 required-opps = <&rpmhpd_opp_low_svs>; 3002 }; 3003 3004 opp-325000000 { 3005 opp-hz = /bits/ 64 <325000000>; 3006 required-opps = <&rpmhpd_opp_svs>; 3007 }; 3008 3009 opp-375000000 { 3010 opp-hz = /bits/ 64 <375000000>; 3011 required-opps = <&rpmhpd_opp_svs_l1>; 3012 }; 3013 3014 opp-500000000 { 3015 opp-hz = /bits/ 64 <500000000>; 3016 required-opps = <&rpmhpd_opp_nom>; 3017 }; 3018 }; 3019 }; 3020 3021 mdss_dp0: displayport-controller@ae90000 { 3022 compatible = "qcom,sm8450-dp", "qcom,sm8350-dp"; 3023 reg = <0 0xae90000 0 0x200>, 3024 <0 0xae90200 0 0x200>, 3025 <0 0xae90400 0 0xc00>, 3026 <0 0xae91000 0 0x400>, 3027 <0 0xae91400 0 0x400>; 3028 interrupt-parent = <&mdss>; 3029 interrupts = <12>; 3030 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3031 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 3032 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 3033 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 3034 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 3035 clock-names = "core_iface", 3036 "core_aux", 3037 "ctrl_link", 3038 "ctrl_link_iface", 3039 "stream_pixel"; 3040 3041 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 3042 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 3043 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3044 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3045 3046 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 3047 phy-names = "dp"; 3048 3049 #sound-dai-cells = <0>; 3050 3051 operating-points-v2 = <&dp_opp_table>; 3052 power-domains = <&rpmhpd RPMHPD_MMCX>; 3053 3054 status = "disabled"; 3055 3056 ports { 3057 #address-cells = <1>; 3058 #size-cells = <0>; 3059 3060 port@0 { 3061 reg = <0>; 3062 mdss_dp0_in: endpoint { 3063 remote-endpoint = <&dpu_intf0_out>; 3064 }; 3065 }; 3066 }; 3067 3068 dp_opp_table: opp-table { 3069 compatible = "operating-points-v2"; 3070 3071 opp-160000000 { 3072 opp-hz = /bits/ 64 <160000000>; 3073 required-opps = <&rpmhpd_opp_low_svs>; 3074 }; 3075 3076 opp-270000000 { 3077 opp-hz = /bits/ 64 <270000000>; 3078 required-opps = <&rpmhpd_opp_svs>; 3079 }; 3080 3081 opp-540000000 { 3082 opp-hz = /bits/ 64 <540000000>; 3083 required-opps = <&rpmhpd_opp_svs_l1>; 3084 }; 3085 3086 opp-810000000 { 3087 opp-hz = /bits/ 64 <810000000>; 3088 required-opps = <&rpmhpd_opp_nom>; 3089 }; 3090 }; 3091 }; 3092 3093 mdss_dsi0: dsi@ae94000 { 3094 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3095 reg = <0 0x0ae94000 0 0x400>; 3096 reg-names = "dsi_ctrl"; 3097 3098 interrupt-parent = <&mdss>; 3099 interrupts = <4>; 3100 3101 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3102 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3103 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3104 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3105 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3106 <&gcc GCC_DISP_HF_AXI_CLK>; 3107 clock-names = "byte", 3108 "byte_intf", 3109 "pixel", 3110 "core", 3111 "iface", 3112 "bus"; 3113 3114 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3115 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 3116 3117 operating-points-v2 = <&mdss_dsi_opp_table>; 3118 power-domains = <&rpmhpd RPMHPD_MMCX>; 3119 3120 phys = <&mdss_dsi0_phy>; 3121 phy-names = "dsi"; 3122 3123 #address-cells = <1>; 3124 #size-cells = <0>; 3125 3126 status = "disabled"; 3127 3128 ports { 3129 #address-cells = <1>; 3130 #size-cells = <0>; 3131 3132 port@0 { 3133 reg = <0>; 3134 mdss_dsi0_in: endpoint { 3135 remote-endpoint = <&dpu_intf1_out>; 3136 }; 3137 }; 3138 3139 port@1 { 3140 reg = <1>; 3141 mdss_dsi0_out: endpoint { 3142 }; 3143 }; 3144 }; 3145 3146 mdss_dsi_opp_table: opp-table { 3147 compatible = "operating-points-v2"; 3148 3149 opp-187500000 { 3150 opp-hz = /bits/ 64 <187500000>; 3151 required-opps = <&rpmhpd_opp_low_svs>; 3152 }; 3153 3154 opp-300000000 { 3155 opp-hz = /bits/ 64 <300000000>; 3156 required-opps = <&rpmhpd_opp_svs>; 3157 }; 3158 3159 opp-358000000 { 3160 opp-hz = /bits/ 64 <358000000>; 3161 required-opps = <&rpmhpd_opp_svs_l1>; 3162 }; 3163 }; 3164 }; 3165 3166 mdss_dsi0_phy: phy@ae94400 { 3167 compatible = "qcom,sm8450-dsi-phy-5nm"; 3168 reg = <0 0x0ae94400 0 0x200>, 3169 <0 0x0ae94600 0 0x280>, 3170 <0 0x0ae94900 0 0x260>; 3171 reg-names = "dsi_phy", 3172 "dsi_phy_lane", 3173 "dsi_pll"; 3174 3175 #clock-cells = <1>; 3176 #phy-cells = <0>; 3177 3178 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3179 <&rpmhcc RPMH_CXO_CLK>; 3180 clock-names = "iface", "ref"; 3181 3182 status = "disabled"; 3183 }; 3184 3185 mdss_dsi1: dsi@ae96000 { 3186 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3187 reg = <0 0x0ae96000 0 0x400>; 3188 reg-names = "dsi_ctrl"; 3189 3190 interrupt-parent = <&mdss>; 3191 interrupts = <5>; 3192 3193 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3194 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3195 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3196 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3197 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3198 <&gcc GCC_DISP_HF_AXI_CLK>; 3199 clock-names = "byte", 3200 "byte_intf", 3201 "pixel", 3202 "core", 3203 "iface", 3204 "bus"; 3205 3206 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3207 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 3208 3209 operating-points-v2 = <&mdss_dsi_opp_table>; 3210 power-domains = <&rpmhpd RPMHPD_MMCX>; 3211 3212 phys = <&mdss_dsi1_phy>; 3213 phy-names = "dsi"; 3214 3215 #address-cells = <1>; 3216 #size-cells = <0>; 3217 3218 status = "disabled"; 3219 3220 ports { 3221 #address-cells = <1>; 3222 #size-cells = <0>; 3223 3224 port@0 { 3225 reg = <0>; 3226 mdss_dsi1_in: endpoint { 3227 remote-endpoint = <&dpu_intf2_out>; 3228 }; 3229 }; 3230 3231 port@1 { 3232 reg = <1>; 3233 mdss_dsi1_out: endpoint { 3234 }; 3235 }; 3236 }; 3237 }; 3238 3239 mdss_dsi1_phy: phy@ae96400 { 3240 compatible = "qcom,sm8450-dsi-phy-5nm"; 3241 reg = <0 0x0ae96400 0 0x200>, 3242 <0 0x0ae96600 0 0x280>, 3243 <0 0x0ae96900 0 0x260>; 3244 reg-names = "dsi_phy", 3245 "dsi_phy_lane", 3246 "dsi_pll"; 3247 3248 #clock-cells = <1>; 3249 #phy-cells = <0>; 3250 3251 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3252 <&rpmhcc RPMH_CXO_CLK>; 3253 clock-names = "iface", "ref"; 3254 3255 status = "disabled"; 3256 }; 3257 }; 3258 3259 dispcc: clock-controller@af00000 { 3260 compatible = "qcom,sm8450-dispcc"; 3261 reg = <0 0x0af00000 0 0x20000>; 3262 clocks = <&rpmhcc RPMH_CXO_CLK>, 3263 <&rpmhcc RPMH_CXO_CLK_A>, 3264 <&gcc GCC_DISP_AHB_CLK>, 3265 <&sleep_clk>, 3266 <&mdss_dsi0_phy 0>, 3267 <&mdss_dsi0_phy 1>, 3268 <&mdss_dsi1_phy 0>, 3269 <&mdss_dsi1_phy 1>, 3270 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3271 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3272 <0>, /* dp1 */ 3273 <0>, 3274 <0>, /* dp2 */ 3275 <0>, 3276 <0>, /* dp3 */ 3277 <0>; 3278 power-domains = <&rpmhpd RPMHPD_MMCX>; 3279 required-opps = <&rpmhpd_opp_low_svs>; 3280 #clock-cells = <1>; 3281 #reset-cells = <1>; 3282 #power-domain-cells = <1>; 3283 status = "disabled"; 3284 }; 3285 3286 pdc: interrupt-controller@b220000 { 3287 compatible = "qcom,sm8450-pdc", "qcom,pdc"; 3288 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 3289 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, 3290 <94 609 31>, <125 63 1>, <126 716 12>; 3291 #interrupt-cells = <2>; 3292 interrupt-parent = <&intc>; 3293 interrupt-controller; 3294 }; 3295 3296 tsens0: thermal-sensor@c263000 { 3297 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 3298 reg = <0 0x0c263000 0 0x1000>, /* TM */ 3299 <0 0x0c222000 0 0x1000>; /* SROT */ 3300 #qcom,sensors = <16>; 3301 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3302 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3303 interrupt-names = "uplow", "critical"; 3304 #thermal-sensor-cells = <1>; 3305 }; 3306 3307 tsens1: thermal-sensor@c265000 { 3308 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 3309 reg = <0 0x0c265000 0 0x1000>, /* TM */ 3310 <0 0x0c223000 0 0x1000>; /* SROT */ 3311 #qcom,sensors = <16>; 3312 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3313 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3314 interrupt-names = "uplow", "critical"; 3315 #thermal-sensor-cells = <1>; 3316 }; 3317 3318 aoss_qmp: power-management@c300000 { 3319 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; 3320 reg = <0 0x0c300000 0 0x400>; 3321 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 3322 IRQ_TYPE_EDGE_RISING>; 3323 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3324 3325 #clock-cells = <0>; 3326 }; 3327 3328 sram@c3f0000 { 3329 compatible = "qcom,rpmh-stats"; 3330 reg = <0 0x0c3f0000 0 0x400>; 3331 }; 3332 3333 spmi_bus: spmi@c400000 { 3334 compatible = "qcom,spmi-pmic-arb"; 3335 reg = <0 0x0c400000 0 0x00003000>, 3336 <0 0x0c500000 0 0x00400000>, 3337 <0 0x0c440000 0 0x00080000>, 3338 <0 0x0c4c0000 0 0x00010000>, 3339 <0 0x0c42d000 0 0x00010000>; 3340 reg-names = "core", 3341 "chnls", 3342 "obsrvr", 3343 "intr", 3344 "cnfg"; 3345 interrupt-names = "periph_irq"; 3346 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3347 qcom,ee = <0>; 3348 qcom,channel = <0>; 3349 interrupt-controller; 3350 #interrupt-cells = <4>; 3351 #address-cells = <2>; 3352 #size-cells = <0>; 3353 }; 3354 3355 ipcc: mailbox@ed18000 { 3356 compatible = "qcom,sm8450-ipcc", "qcom,ipcc"; 3357 reg = <0 0x0ed18000 0 0x1000>; 3358 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 3359 interrupt-controller; 3360 #interrupt-cells = <3>; 3361 #mbox-cells = <2>; 3362 }; 3363 3364 tlmm: pinctrl@f100000 { 3365 compatible = "qcom,sm8450-tlmm"; 3366 reg = <0 0x0f100000 0 0x300000>; 3367 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3368 gpio-controller; 3369 #gpio-cells = <2>; 3370 interrupt-controller; 3371 #interrupt-cells = <2>; 3372 gpio-ranges = <&tlmm 0 0 211>; 3373 wakeup-parent = <&pdc>; 3374 3375 sdc2_default_state: sdc2-default-state { 3376 clk-pins { 3377 pins = "sdc2_clk"; 3378 drive-strength = <16>; 3379 bias-disable; 3380 }; 3381 3382 cmd-pins { 3383 pins = "sdc2_cmd"; 3384 drive-strength = <16>; 3385 bias-pull-up; 3386 }; 3387 3388 data-pins { 3389 pins = "sdc2_data"; 3390 drive-strength = <16>; 3391 bias-pull-up; 3392 }; 3393 }; 3394 3395 sdc2_sleep_state: sdc2-sleep-state { 3396 clk-pins { 3397 pins = "sdc2_clk"; 3398 drive-strength = <2>; 3399 bias-disable; 3400 }; 3401 3402 cmd-pins { 3403 pins = "sdc2_cmd"; 3404 drive-strength = <2>; 3405 bias-pull-up; 3406 }; 3407 3408 data-pins { 3409 pins = "sdc2_data"; 3410 drive-strength = <2>; 3411 bias-pull-up; 3412 }; 3413 }; 3414 3415 cci0_default: cci0-default-state { 3416 /* SDA, SCL */ 3417 pins = "gpio110", "gpio111"; 3418 function = "cci_i2c"; 3419 drive-strength = <2>; 3420 bias-pull-up; 3421 }; 3422 3423 cci0_sleep: cci0-sleep-state { 3424 /* SDA, SCL */ 3425 pins = "gpio110", "gpio111"; 3426 function = "cci_i2c"; 3427 drive-strength = <2>; 3428 bias-pull-down; 3429 }; 3430 3431 cci1_default: cci1-default-state { 3432 /* SDA, SCL */ 3433 pins = "gpio112", "gpio113"; 3434 function = "cci_i2c"; 3435 drive-strength = <2>; 3436 bias-pull-up; 3437 }; 3438 3439 cci1_sleep: cci1-sleep-state { 3440 /* SDA, SCL */ 3441 pins = "gpio112", "gpio113"; 3442 function = "cci_i2c"; 3443 drive-strength = <2>; 3444 bias-pull-down; 3445 }; 3446 3447 cci2_default: cci2-default-state { 3448 /* SDA, SCL */ 3449 pins = "gpio114", "gpio115"; 3450 function = "cci_i2c"; 3451 drive-strength = <2>; 3452 bias-pull-up; 3453 }; 3454 3455 cci2_sleep: cci2-sleep-state { 3456 /* SDA, SCL */ 3457 pins = "gpio114", "gpio115"; 3458 function = "cci_i2c"; 3459 drive-strength = <2>; 3460 bias-pull-down; 3461 }; 3462 3463 cci3_default: cci3-default-state { 3464 /* SDA, SCL */ 3465 pins = "gpio208", "gpio209"; 3466 function = "cci_i2c"; 3467 drive-strength = <2>; 3468 bias-pull-up; 3469 }; 3470 3471 cci3_sleep: cci3-sleep-state { 3472 /* SDA, SCL */ 3473 pins = "gpio208", "gpio209"; 3474 function = "cci_i2c"; 3475 drive-strength = <2>; 3476 bias-pull-down; 3477 }; 3478 3479 pcie0_default_state: pcie0-default-state { 3480 perst-pins { 3481 pins = "gpio94"; 3482 function = "gpio"; 3483 drive-strength = <2>; 3484 bias-pull-down; 3485 }; 3486 3487 clkreq-pins { 3488 pins = "gpio95"; 3489 function = "pcie0_clkreqn"; 3490 drive-strength = <2>; 3491 bias-pull-up; 3492 }; 3493 3494 wake-pins { 3495 pins = "gpio96"; 3496 function = "gpio"; 3497 drive-strength = <2>; 3498 bias-pull-up; 3499 }; 3500 }; 3501 3502 pcie1_default_state: pcie1-default-state { 3503 perst-pins { 3504 pins = "gpio97"; 3505 function = "gpio"; 3506 drive-strength = <2>; 3507 bias-pull-down; 3508 }; 3509 3510 clkreq-pins { 3511 pins = "gpio98"; 3512 function = "pcie1_clkreqn"; 3513 drive-strength = <2>; 3514 bias-pull-up; 3515 }; 3516 3517 wake-pins { 3518 pins = "gpio99"; 3519 function = "gpio"; 3520 drive-strength = <2>; 3521 bias-pull-up; 3522 }; 3523 }; 3524 3525 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 3526 pins = "gpio0", "gpio1"; 3527 function = "qup0"; 3528 }; 3529 3530 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 3531 pins = "gpio4", "gpio5"; 3532 function = "qup1"; 3533 }; 3534 3535 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 3536 pins = "gpio8", "gpio9"; 3537 function = "qup2"; 3538 }; 3539 3540 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 3541 pins = "gpio12", "gpio13"; 3542 function = "qup3"; 3543 }; 3544 3545 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 3546 pins = "gpio16", "gpio17"; 3547 function = "qup4"; 3548 }; 3549 3550 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 3551 pins = "gpio206", "gpio207"; 3552 function = "qup5"; 3553 }; 3554 3555 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 3556 pins = "gpio20", "gpio21"; 3557 function = "qup6"; 3558 }; 3559 3560 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 3561 pins = "gpio28", "gpio29"; 3562 function = "qup8"; 3563 }; 3564 3565 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 3566 pins = "gpio32", "gpio33"; 3567 function = "qup9"; 3568 }; 3569 3570 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 3571 pins = "gpio36", "gpio37"; 3572 function = "qup10"; 3573 }; 3574 3575 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 3576 pins = "gpio40", "gpio41"; 3577 function = "qup11"; 3578 }; 3579 3580 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 3581 pins = "gpio44", "gpio45"; 3582 function = "qup12"; 3583 }; 3584 3585 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 3586 pins = "gpio48", "gpio49"; 3587 function = "qup13"; 3588 drive-strength = <2>; 3589 bias-pull-up; 3590 }; 3591 3592 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 3593 pins = "gpio52", "gpio53"; 3594 function = "qup14"; 3595 drive-strength = <2>; 3596 bias-pull-up; 3597 }; 3598 3599 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 3600 pins = "gpio56", "gpio57"; 3601 function = "qup15"; 3602 }; 3603 3604 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 3605 pins = "gpio60", "gpio61"; 3606 function = "qup16"; 3607 }; 3608 3609 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 3610 pins = "gpio64", "gpio65"; 3611 function = "qup17"; 3612 }; 3613 3614 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 3615 pins = "gpio68", "gpio69"; 3616 function = "qup18"; 3617 }; 3618 3619 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 3620 pins = "gpio72", "gpio73"; 3621 function = "qup19"; 3622 }; 3623 3624 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 3625 pins = "gpio76", "gpio77"; 3626 function = "qup20"; 3627 }; 3628 3629 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 3630 pins = "gpio80", "gpio81"; 3631 function = "qup21"; 3632 }; 3633 3634 qup_spi0_cs: qup-spi0-cs-state { 3635 pins = "gpio3"; 3636 function = "qup0"; 3637 }; 3638 3639 qup_spi0_data_clk: qup-spi0-data-clk-state { 3640 pins = "gpio0", "gpio1", "gpio2"; 3641 function = "qup0"; 3642 }; 3643 3644 qup_spi1_cs: qup-spi1-cs-state { 3645 pins = "gpio7"; 3646 function = "qup1"; 3647 }; 3648 3649 qup_spi1_data_clk: qup-spi1-data-clk-state { 3650 pins = "gpio4", "gpio5", "gpio6"; 3651 function = "qup1"; 3652 }; 3653 3654 qup_spi2_cs: qup-spi2-cs-state { 3655 pins = "gpio11"; 3656 function = "qup2"; 3657 }; 3658 3659 qup_spi2_data_clk: qup-spi2-data-clk-state { 3660 pins = "gpio8", "gpio9", "gpio10"; 3661 function = "qup2"; 3662 }; 3663 3664 qup_spi3_cs: qup-spi3-cs-state { 3665 pins = "gpio15"; 3666 function = "qup3"; 3667 }; 3668 3669 qup_spi3_data_clk: qup-spi3-data-clk-state { 3670 pins = "gpio12", "gpio13", "gpio14"; 3671 function = "qup3"; 3672 }; 3673 3674 qup_spi4_cs: qup-spi4-cs-state { 3675 pins = "gpio19"; 3676 function = "qup4"; 3677 drive-strength = <6>; 3678 bias-disable; 3679 }; 3680 3681 qup_spi4_data_clk: qup-spi4-data-clk-state { 3682 pins = "gpio16", "gpio17", "gpio18"; 3683 function = "qup4"; 3684 }; 3685 3686 qup_spi5_cs: qup-spi5-cs-state { 3687 pins = "gpio85"; 3688 function = "qup5"; 3689 }; 3690 3691 qup_spi5_data_clk: qup-spi5-data-clk-state { 3692 pins = "gpio206", "gpio207", "gpio84"; 3693 function = "qup5"; 3694 }; 3695 3696 qup_spi6_cs: qup-spi6-cs-state { 3697 pins = "gpio23"; 3698 function = "qup6"; 3699 }; 3700 3701 qup_spi6_data_clk: qup-spi6-data-clk-state { 3702 pins = "gpio20", "gpio21", "gpio22"; 3703 function = "qup6"; 3704 }; 3705 3706 qup_spi8_cs: qup-spi8-cs-state { 3707 pins = "gpio31"; 3708 function = "qup8"; 3709 }; 3710 3711 qup_spi8_data_clk: qup-spi8-data-clk-state { 3712 pins = "gpio28", "gpio29", "gpio30"; 3713 function = "qup8"; 3714 }; 3715 3716 qup_spi9_cs: qup-spi9-cs-state { 3717 pins = "gpio35"; 3718 function = "qup9"; 3719 }; 3720 3721 qup_spi9_data_clk: qup-spi9-data-clk-state { 3722 pins = "gpio32", "gpio33", "gpio34"; 3723 function = "qup9"; 3724 }; 3725 3726 qup_spi10_cs: qup-spi10-cs-state { 3727 pins = "gpio39"; 3728 function = "qup10"; 3729 }; 3730 3731 qup_spi10_data_clk: qup-spi10-data-clk-state { 3732 pins = "gpio36", "gpio37", "gpio38"; 3733 function = "qup10"; 3734 }; 3735 3736 qup_spi11_cs: qup-spi11-cs-state { 3737 pins = "gpio43"; 3738 function = "qup11"; 3739 }; 3740 3741 qup_spi11_data_clk: qup-spi11-data-clk-state { 3742 pins = "gpio40", "gpio41", "gpio42"; 3743 function = "qup11"; 3744 }; 3745 3746 qup_spi12_cs: qup-spi12-cs-state { 3747 pins = "gpio47"; 3748 function = "qup12"; 3749 }; 3750 3751 qup_spi12_data_clk: qup-spi12-data-clk-state { 3752 pins = "gpio44", "gpio45", "gpio46"; 3753 function = "qup12"; 3754 }; 3755 3756 qup_spi13_cs: qup-spi13-cs-state { 3757 pins = "gpio51"; 3758 function = "qup13"; 3759 }; 3760 3761 qup_spi13_data_clk: qup-spi13-data-clk-state { 3762 pins = "gpio48", "gpio49", "gpio50"; 3763 function = "qup13"; 3764 }; 3765 3766 qup_spi14_cs: qup-spi14-cs-state { 3767 pins = "gpio55"; 3768 function = "qup14"; 3769 }; 3770 3771 qup_spi14_data_clk: qup-spi14-data-clk-state { 3772 pins = "gpio52", "gpio53", "gpio54"; 3773 function = "qup14"; 3774 }; 3775 3776 qup_spi15_cs: qup-spi15-cs-state { 3777 pins = "gpio59"; 3778 function = "qup15"; 3779 }; 3780 3781 qup_spi15_data_clk: qup-spi15-data-clk-state { 3782 pins = "gpio56", "gpio57", "gpio58"; 3783 function = "qup15"; 3784 }; 3785 3786 qup_spi16_cs: qup-spi16-cs-state { 3787 pins = "gpio63"; 3788 function = "qup16"; 3789 }; 3790 3791 qup_spi16_data_clk: qup-spi16-data-clk-state { 3792 pins = "gpio60", "gpio61", "gpio62"; 3793 function = "qup16"; 3794 }; 3795 3796 qup_spi17_cs: qup-spi17-cs-state { 3797 pins = "gpio67"; 3798 function = "qup17"; 3799 }; 3800 3801 qup_spi17_data_clk: qup-spi17-data-clk-state { 3802 pins = "gpio64", "gpio65", "gpio66"; 3803 function = "qup17"; 3804 }; 3805 3806 qup_spi18_cs: qup-spi18-cs-state { 3807 pins = "gpio71"; 3808 function = "qup18"; 3809 drive-strength = <6>; 3810 bias-disable; 3811 }; 3812 3813 qup_spi18_data_clk: qup-spi18-data-clk-state { 3814 pins = "gpio68", "gpio69", "gpio70"; 3815 function = "qup18"; 3816 drive-strength = <6>; 3817 bias-disable; 3818 }; 3819 3820 qup_spi19_cs: qup-spi19-cs-state { 3821 pins = "gpio75"; 3822 function = "qup19"; 3823 drive-strength = <6>; 3824 bias-disable; 3825 }; 3826 3827 qup_spi19_data_clk: qup-spi19-data-clk-state { 3828 pins = "gpio72", "gpio73", "gpio74"; 3829 function = "qup19"; 3830 drive-strength = <6>; 3831 bias-disable; 3832 }; 3833 3834 qup_spi20_cs: qup-spi20-cs-state { 3835 pins = "gpio79"; 3836 function = "qup20"; 3837 }; 3838 3839 qup_spi20_data_clk: qup-spi20-data-clk-state { 3840 pins = "gpio76", "gpio77", "gpio78"; 3841 function = "qup20"; 3842 }; 3843 3844 qup_spi21_cs: qup-spi21-cs-state { 3845 pins = "gpio83"; 3846 function = "qup21"; 3847 }; 3848 3849 qup_spi21_data_clk: qup-spi21-data-clk-state { 3850 pins = "gpio80", "gpio81", "gpio82"; 3851 function = "qup21"; 3852 }; 3853 3854 qup_uart7_rx: qup-uart7-rx-state { 3855 pins = "gpio26"; 3856 function = "qup7"; 3857 drive-strength = <2>; 3858 bias-disable; 3859 }; 3860 3861 qup_uart7_tx: qup-uart7-tx-state { 3862 pins = "gpio27"; 3863 function = "qup7"; 3864 drive-strength = <2>; 3865 bias-disable; 3866 }; 3867 3868 qup_uart20_default: qup-uart20-default-state { 3869 pins = "gpio76", "gpio77", "gpio78", "gpio79"; 3870 function = "qup20"; 3871 }; 3872 }; 3873 3874 lpass_tlmm: pinctrl@3440000 { 3875 compatible = "qcom,sm8450-lpass-lpi-pinctrl"; 3876 reg = <0 0x03440000 0x0 0x20000>, 3877 <0 0x034d0000 0x0 0x10000>; 3878 gpio-controller; 3879 #gpio-cells = <2>; 3880 gpio-ranges = <&lpass_tlmm 0 0 23>; 3881 3882 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3883 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3884 clock-names = "core", "audio"; 3885 3886 tx_swr_active: tx-swr-active-state { 3887 clk-pins { 3888 pins = "gpio0"; 3889 function = "swr_tx_clk"; 3890 drive-strength = <2>; 3891 slew-rate = <1>; 3892 bias-disable; 3893 }; 3894 3895 data-pins { 3896 pins = "gpio1", "gpio2", "gpio14"; 3897 function = "swr_tx_data"; 3898 drive-strength = <2>; 3899 slew-rate = <1>; 3900 bias-bus-hold; 3901 }; 3902 }; 3903 3904 rx_swr_active: rx-swr-active-state { 3905 clk-pins { 3906 pins = "gpio3"; 3907 function = "swr_rx_clk"; 3908 drive-strength = <2>; 3909 slew-rate = <1>; 3910 bias-disable; 3911 }; 3912 3913 data-pins { 3914 pins = "gpio4", "gpio5"; 3915 function = "swr_rx_data"; 3916 drive-strength = <2>; 3917 slew-rate = <1>; 3918 bias-bus-hold; 3919 }; 3920 }; 3921 3922 dmic01_default: dmic01-default-state { 3923 clk-pins { 3924 pins = "gpio6"; 3925 function = "dmic1_clk"; 3926 drive-strength = <8>; 3927 output-high; 3928 }; 3929 3930 data-pins { 3931 pins = "gpio7"; 3932 function = "dmic1_data"; 3933 drive-strength = <8>; 3934 }; 3935 }; 3936 3937 dmic02_default: dmic02-default-state { 3938 clk-pins { 3939 pins = "gpio8"; 3940 function = "dmic2_clk"; 3941 drive-strength = <8>; 3942 output-high; 3943 }; 3944 3945 data-pins { 3946 pins = "gpio9"; 3947 function = "dmic2_data"; 3948 drive-strength = <8>; 3949 }; 3950 }; 3951 3952 wsa_swr_active: wsa-swr-active-state { 3953 clk-pins { 3954 pins = "gpio10"; 3955 function = "wsa_swr_clk"; 3956 drive-strength = <2>; 3957 slew-rate = <1>; 3958 bias-disable; 3959 }; 3960 3961 data-pins { 3962 pins = "gpio11"; 3963 function = "wsa_swr_data"; 3964 drive-strength = <2>; 3965 slew-rate = <1>; 3966 bias-bus-hold; 3967 }; 3968 }; 3969 3970 wsa2_swr_active: wsa2-swr-active-state { 3971 clk-pins { 3972 pins = "gpio15"; 3973 function = "wsa2_swr_clk"; 3974 drive-strength = <2>; 3975 slew-rate = <1>; 3976 bias-disable; 3977 }; 3978 3979 data-pins { 3980 pins = "gpio16"; 3981 function = "wsa2_swr_data"; 3982 drive-strength = <2>; 3983 slew-rate = <1>; 3984 bias-bus-hold; 3985 }; 3986 }; 3987 }; 3988 3989 sram@146aa000 { 3990 compatible = "qcom,sm8450-imem", "syscon", "simple-mfd"; 3991 reg = <0 0x146aa000 0 0x1000>; 3992 ranges = <0 0 0x146aa000 0x1000>; 3993 3994 #address-cells = <1>; 3995 #size-cells = <1>; 3996 3997 pil-reloc@94c { 3998 compatible = "qcom,pil-reloc-info"; 3999 reg = <0x94c 0xc8>; 4000 }; 4001 }; 4002 4003 apps_smmu: iommu@15000000 { 4004 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; 4005 reg = <0 0x15000000 0 0x100000>; 4006 #iommu-cells = <2>; 4007 #global-interrupts = <1>; 4008 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4009 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4010 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4011 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4012 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4013 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4014 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4015 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4016 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4017 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4018 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4019 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4020 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4021 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4022 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4023 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4024 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4025 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4026 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4027 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4028 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4029 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4030 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4031 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4032 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4033 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4034 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4035 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4036 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4037 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4038 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4039 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4040 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4041 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4042 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4043 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4044 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4045 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4046 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4047 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4048 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4049 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4050 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4051 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4052 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4053 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4054 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4055 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4056 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4057 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4058 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4059 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4060 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4061 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4062 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4063 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4064 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4065 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4066 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4067 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4068 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4069 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4070 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4071 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4072 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4073 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4074 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4075 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4076 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4077 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4078 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4079 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4080 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4081 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4082 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4083 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4084 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4085 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4086 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4087 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4088 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 4089 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4090 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4091 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 4092 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4093 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 4094 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4095 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4096 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 4097 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 4098 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 4099 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 4100 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 4101 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 4102 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 4103 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 4104 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 4105 }; 4106 4107 intc: interrupt-controller@17100000 { 4108 compatible = "arm,gic-v3"; 4109 #interrupt-cells = <3>; 4110 interrupt-controller; 4111 #redistributor-regions = <1>; 4112 redistributor-stride = <0x0 0x40000>; 4113 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ 4114 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ 4115 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4116 #address-cells = <2>; 4117 #size-cells = <2>; 4118 ranges; 4119 4120 gic_its: msi-controller@17140000 { 4121 compatible = "arm,gic-v3-its"; 4122 reg = <0x0 0x17140000 0x0 0x20000>; 4123 msi-controller; 4124 #msi-cells = <1>; 4125 }; 4126 }; 4127 4128 timer@17420000 { 4129 compatible = "arm,armv7-timer-mem"; 4130 #address-cells = <1>; 4131 #size-cells = <1>; 4132 ranges = <0 0 0 0x20000000>; 4133 reg = <0x0 0x17420000 0x0 0x1000>; 4134 clock-frequency = <19200000>; 4135 4136 frame@17421000 { 4137 frame-number = <0>; 4138 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4139 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4140 reg = <0x17421000 0x1000>, 4141 <0x17422000 0x1000>; 4142 }; 4143 4144 frame@17423000 { 4145 frame-number = <1>; 4146 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4147 reg = <0x17423000 0x1000>; 4148 status = "disabled"; 4149 }; 4150 4151 frame@17425000 { 4152 frame-number = <2>; 4153 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4154 reg = <0x17425000 0x1000>; 4155 status = "disabled"; 4156 }; 4157 4158 frame@17427000 { 4159 frame-number = <3>; 4160 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4161 reg = <0x17427000 0x1000>; 4162 status = "disabled"; 4163 }; 4164 4165 frame@17429000 { 4166 frame-number = <4>; 4167 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4168 reg = <0x17429000 0x1000>; 4169 status = "disabled"; 4170 }; 4171 4172 frame@1742b000 { 4173 frame-number = <5>; 4174 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4175 reg = <0x1742b000 0x1000>; 4176 status = "disabled"; 4177 }; 4178 4179 frame@1742d000 { 4180 frame-number = <6>; 4181 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4182 reg = <0x1742d000 0x1000>; 4183 status = "disabled"; 4184 }; 4185 }; 4186 4187 apps_rsc: rsc@17a00000 { 4188 label = "apps_rsc"; 4189 compatible = "qcom,rpmh-rsc"; 4190 reg = <0x0 0x17a00000 0x0 0x10000>, 4191 <0x0 0x17a10000 0x0 0x10000>, 4192 <0x0 0x17a20000 0x0 0x10000>, 4193 <0x0 0x17a30000 0x0 0x10000>; 4194 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 4195 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4196 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4197 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4198 qcom,tcs-offset = <0xd00>; 4199 qcom,drv-id = <2>; 4200 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 4201 <WAKE_TCS 2>, <CONTROL_TCS 0>; 4202 power-domains = <&CLUSTER_PD>; 4203 4204 apps_bcm_voter: bcm-voter { 4205 compatible = "qcom,bcm-voter"; 4206 }; 4207 4208 rpmhcc: clock-controller { 4209 compatible = "qcom,sm8450-rpmh-clk"; 4210 #clock-cells = <1>; 4211 clock-names = "xo"; 4212 clocks = <&xo_board>; 4213 }; 4214 4215 rpmhpd: power-controller { 4216 compatible = "qcom,sm8450-rpmhpd"; 4217 #power-domain-cells = <1>; 4218 operating-points-v2 = <&rpmhpd_opp_table>; 4219 4220 rpmhpd_opp_table: opp-table { 4221 compatible = "operating-points-v2"; 4222 4223 rpmhpd_opp_ret: opp1 { 4224 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4225 }; 4226 4227 rpmhpd_opp_min_svs: opp2 { 4228 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4229 }; 4230 4231 rpmhpd_opp_low_svs_d1: opp3 { 4232 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 4233 }; 4234 4235 rpmhpd_opp_low_svs: opp4 { 4236 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4237 }; 4238 4239 rpmhpd_opp_low_svs_l1: opp5 { 4240 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 4241 }; 4242 4243 rpmhpd_opp_svs: opp6 { 4244 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4245 }; 4246 4247 rpmhpd_opp_svs_l0: opp7 { 4248 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 4249 }; 4250 4251 rpmhpd_opp_svs_l1: opp8 { 4252 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4253 }; 4254 4255 rpmhpd_opp_svs_l2: opp9 { 4256 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 4257 }; 4258 4259 rpmhpd_opp_nom: opp10 { 4260 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4261 }; 4262 4263 rpmhpd_opp_nom_l1: opp11 { 4264 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4265 }; 4266 4267 rpmhpd_opp_nom_l2: opp12 { 4268 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4269 }; 4270 4271 rpmhpd_opp_turbo: opp13 { 4272 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4273 }; 4274 4275 rpmhpd_opp_turbo_l1: opp14 { 4276 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4277 }; 4278 }; 4279 }; 4280 }; 4281 4282 cpufreq_hw: cpufreq@17d91000 { 4283 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss"; 4284 reg = <0 0x17d91000 0 0x1000>, 4285 <0 0x17d92000 0 0x1000>, 4286 <0 0x17d93000 0 0x1000>; 4287 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 4288 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4289 clock-names = "xo", "alternate"; 4290 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 4291 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 4292 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 4293 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 4294 #freq-domain-cells = <1>; 4295 #clock-cells = <1>; 4296 }; 4297 4298 gem_noc: interconnect@19100000 { 4299 compatible = "qcom,sm8450-gem-noc"; 4300 reg = <0 0x19100000 0 0xbb800>; 4301 #interconnect-cells = <2>; 4302 qcom,bcm-voters = <&apps_bcm_voter>; 4303 }; 4304 4305 system-cache-controller@19200000 { 4306 compatible = "qcom,sm8450-llcc"; 4307 reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>, 4308 <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>, 4309 <0 0x19a00000 0 0x80000>; 4310 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 4311 "llcc3_base", "llcc_broadcast_base"; 4312 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 4313 }; 4314 4315 ufs_mem_hc: ufshc@1d84000 { 4316 compatible = "qcom,sm8450-ufshc", "qcom,ufshc", 4317 "jedec,ufs-2.0"; 4318 reg = <0 0x01d84000 0 0x3000>; 4319 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 4320 phys = <&ufs_mem_phy>; 4321 phy-names = "ufsphy"; 4322 lanes-per-direction = <2>; 4323 #reset-cells = <1>; 4324 resets = <&gcc GCC_UFS_PHY_BCR>; 4325 reset-names = "rst"; 4326 4327 power-domains = <&gcc UFS_PHY_GDSC>; 4328 4329 iommus = <&apps_smmu 0xe0 0x0>; 4330 dma-coherent; 4331 4332 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 4333 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 4334 interconnect-names = "ufs-ddr", "cpu-ufs"; 4335 clock-names = 4336 "core_clk", 4337 "bus_aggr_clk", 4338 "iface_clk", 4339 "core_clk_unipro", 4340 "ref_clk", 4341 "tx_lane0_sync_clk", 4342 "rx_lane0_sync_clk", 4343 "rx_lane1_sync_clk"; 4344 clocks = 4345 <&gcc GCC_UFS_PHY_AXI_CLK>, 4346 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 4347 <&gcc GCC_UFS_PHY_AHB_CLK>, 4348 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 4349 <&rpmhcc RPMH_CXO_CLK>, 4350 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 4351 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 4352 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 4353 freq-table-hz = 4354 <75000000 300000000>, 4355 <0 0>, 4356 <0 0>, 4357 <75000000 300000000>, 4358 <75000000 300000000>, 4359 <0 0>, 4360 <0 0>, 4361 <0 0>; 4362 qcom,ice = <&ice>; 4363 4364 status = "disabled"; 4365 }; 4366 4367 ufs_mem_phy: phy@1d87000 { 4368 compatible = "qcom,sm8450-qmp-ufs-phy"; 4369 reg = <0 0x01d87000 0 0x1000>; 4370 4371 clock-names = "ref", "ref_aux", "qref"; 4372 clocks = <&rpmhcc RPMH_CXO_CLK>, 4373 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 4374 <&gcc GCC_UFS_0_CLKREF_EN>; 4375 4376 resets = <&ufs_mem_hc 0>; 4377 reset-names = "ufsphy"; 4378 4379 #clock-cells = <1>; 4380 #phy-cells = <0>; 4381 4382 status = "disabled"; 4383 }; 4384 4385 ice: crypto@1d88000 { 4386 compatible = "qcom,sm8450-inline-crypto-engine", 4387 "qcom,inline-crypto-engine"; 4388 reg = <0 0x01d88000 0 0x8000>; 4389 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 4390 }; 4391 4392 cryptobam: dma-controller@1dc4000 { 4393 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 4394 reg = <0 0x01dc4000 0 0x28000>; 4395 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 4396 #dma-cells = <1>; 4397 qcom,ee = <0>; 4398 qcom,controlled-remotely; 4399 iommus = <&apps_smmu 0x584 0x11>, 4400 <&apps_smmu 0x588 0x0>, 4401 <&apps_smmu 0x598 0x5>, 4402 <&apps_smmu 0x59a 0x0>, 4403 <&apps_smmu 0x59f 0x0>; 4404 }; 4405 4406 crypto: crypto@1dfa000 { 4407 compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce"; 4408 reg = <0 0x01dfa000 0 0x6000>; 4409 dmas = <&cryptobam 4>, <&cryptobam 5>; 4410 dma-names = "rx", "tx"; 4411 iommus = <&apps_smmu 0x584 0x11>, 4412 <&apps_smmu 0x588 0x0>, 4413 <&apps_smmu 0x598 0x5>, 4414 <&apps_smmu 0x59a 0x0>, 4415 <&apps_smmu 0x59f 0x0>; 4416 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 4417 interconnect-names = "memory"; 4418 }; 4419 4420 sdhc_2: mmc@8804000 { 4421 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5"; 4422 reg = <0 0x08804000 0 0x1000>; 4423 4424 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 4425 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 4426 interrupt-names = "hc_irq", "pwr_irq"; 4427 4428 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 4429 <&gcc GCC_SDCC2_APPS_CLK>, 4430 <&rpmhcc RPMH_CXO_CLK>; 4431 clock-names = "iface", "core", "xo"; 4432 resets = <&gcc GCC_SDCC2_BCR>; 4433 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 4434 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 4435 interconnect-names = "sdhc-ddr","cpu-sdhc"; 4436 iommus = <&apps_smmu 0x4a0 0x0>; 4437 power-domains = <&rpmhpd RPMHPD_CX>; 4438 operating-points-v2 = <&sdhc2_opp_table>; 4439 bus-width = <4>; 4440 dma-coherent; 4441 4442 /* Forbid SDR104/SDR50 - broken hw! */ 4443 sdhci-caps-mask = <0x3 0x0>; 4444 4445 status = "disabled"; 4446 4447 sdhc2_opp_table: opp-table { 4448 compatible = "operating-points-v2"; 4449 4450 opp-100000000 { 4451 opp-hz = /bits/ 64 <100000000>; 4452 required-opps = <&rpmhpd_opp_low_svs>; 4453 }; 4454 4455 opp-202000000 { 4456 opp-hz = /bits/ 64 <202000000>; 4457 required-opps = <&rpmhpd_opp_svs_l1>; 4458 }; 4459 }; 4460 }; 4461 4462 usb_1: usb@a6f8800 { 4463 compatible = "qcom,sm8450-dwc3", "qcom,dwc3"; 4464 reg = <0 0x0a6f8800 0 0x400>; 4465 status = "disabled"; 4466 #address-cells = <2>; 4467 #size-cells = <2>; 4468 ranges; 4469 4470 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4471 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4472 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4473 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4474 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4475 <&gcc GCC_USB3_0_CLKREF_EN>; 4476 clock-names = "cfg_noc", 4477 "core", 4478 "iface", 4479 "sleep", 4480 "mock_utmi", 4481 "xo"; 4482 4483 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4484 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4485 assigned-clock-rates = <19200000>, <200000000>; 4486 4487 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4488 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 4489 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4490 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 4491 interrupt-names = "hs_phy_irq", 4492 "ss_phy_irq", 4493 "dm_hs_phy_irq", 4494 "dp_hs_phy_irq"; 4495 4496 power-domains = <&gcc USB30_PRIM_GDSC>; 4497 4498 resets = <&gcc GCC_USB30_PRIM_BCR>; 4499 4500 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 4501 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 4502 interconnect-names = "usb-ddr", "apps-usb"; 4503 4504 usb_1_dwc3: usb@a600000 { 4505 compatible = "snps,dwc3"; 4506 reg = <0 0x0a600000 0 0xcd00>; 4507 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4508 iommus = <&apps_smmu 0x0 0x0>; 4509 snps,dis_u2_susphy_quirk; 4510 snps,dis_enblslpm_quirk; 4511 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4512 phy-names = "usb2-phy", "usb3-phy"; 4513 4514 ports { 4515 #address-cells = <1>; 4516 #size-cells = <0>; 4517 4518 port@0 { 4519 reg = <0>; 4520 4521 usb_1_dwc3_hs: endpoint { 4522 }; 4523 }; 4524 4525 port@1 { 4526 reg = <1>; 4527 4528 usb_1_dwc3_ss: endpoint { 4529 }; 4530 }; 4531 }; 4532 }; 4533 }; 4534 4535 nsp_noc: interconnect@320c0000 { 4536 compatible = "qcom,sm8450-nsp-noc"; 4537 reg = <0 0x320c0000 0 0x10000>; 4538 #interconnect-cells = <2>; 4539 qcom,bcm-voters = <&apps_bcm_voter>; 4540 }; 4541 4542 lpass_ag_noc: interconnect@3c40000 { 4543 compatible = "qcom,sm8450-lpass-ag-noc"; 4544 reg = <0 0x03c40000 0 0x17200>; 4545 #interconnect-cells = <2>; 4546 qcom,bcm-voters = <&apps_bcm_voter>; 4547 }; 4548 }; 4549 4550 sound: sound { 4551 }; 4552 4553 thermal-zones { 4554 aoss0-thermal { 4555 polling-delay-passive = <0>; 4556 polling-delay = <0>; 4557 thermal-sensors = <&tsens0 0>; 4558 4559 trips { 4560 thermal-engine-config { 4561 temperature = <125000>; 4562 hysteresis = <1000>; 4563 type = "passive"; 4564 }; 4565 4566 reset-mon-cfg { 4567 temperature = <115000>; 4568 hysteresis = <5000>; 4569 type = "passive"; 4570 }; 4571 }; 4572 }; 4573 4574 cpuss0-thermal { 4575 polling-delay-passive = <0>; 4576 polling-delay = <0>; 4577 thermal-sensors = <&tsens0 1>; 4578 4579 trips { 4580 thermal-engine-config { 4581 temperature = <125000>; 4582 hysteresis = <1000>; 4583 type = "passive"; 4584 }; 4585 4586 reset-mon-cfg { 4587 temperature = <115000>; 4588 hysteresis = <5000>; 4589 type = "passive"; 4590 }; 4591 }; 4592 }; 4593 4594 cpuss1-thermal { 4595 polling-delay-passive = <0>; 4596 polling-delay = <0>; 4597 thermal-sensors = <&tsens0 2>; 4598 4599 trips { 4600 thermal-engine-config { 4601 temperature = <125000>; 4602 hysteresis = <1000>; 4603 type = "passive"; 4604 }; 4605 4606 reset-mon-cfg { 4607 temperature = <115000>; 4608 hysteresis = <5000>; 4609 type = "passive"; 4610 }; 4611 }; 4612 }; 4613 4614 cpuss3-thermal { 4615 polling-delay-passive = <0>; 4616 polling-delay = <0>; 4617 thermal-sensors = <&tsens0 3>; 4618 4619 trips { 4620 thermal-engine-config { 4621 temperature = <125000>; 4622 hysteresis = <1000>; 4623 type = "passive"; 4624 }; 4625 4626 reset-mon-cfg { 4627 temperature = <115000>; 4628 hysteresis = <5000>; 4629 type = "passive"; 4630 }; 4631 }; 4632 }; 4633 4634 cpuss4-thermal { 4635 polling-delay-passive = <0>; 4636 polling-delay = <0>; 4637 thermal-sensors = <&tsens0 4>; 4638 4639 trips { 4640 thermal-engine-config { 4641 temperature = <125000>; 4642 hysteresis = <1000>; 4643 type = "passive"; 4644 }; 4645 4646 reset-mon-cfg { 4647 temperature = <115000>; 4648 hysteresis = <5000>; 4649 type = "passive"; 4650 }; 4651 }; 4652 }; 4653 4654 cpu4-top-thermal { 4655 polling-delay-passive = <0>; 4656 polling-delay = <0>; 4657 thermal-sensors = <&tsens0 5>; 4658 4659 trips { 4660 cpu4_top_alert0: trip-point0 { 4661 temperature = <90000>; 4662 hysteresis = <2000>; 4663 type = "passive"; 4664 }; 4665 4666 cpu4_top_alert1: trip-point1 { 4667 temperature = <95000>; 4668 hysteresis = <2000>; 4669 type = "passive"; 4670 }; 4671 4672 cpu4_top_crit: cpu-crit { 4673 temperature = <110000>; 4674 hysteresis = <1000>; 4675 type = "critical"; 4676 }; 4677 }; 4678 }; 4679 4680 cpu4-bottom-thermal { 4681 polling-delay-passive = <0>; 4682 polling-delay = <0>; 4683 thermal-sensors = <&tsens0 6>; 4684 4685 trips { 4686 cpu4_bottom_alert0: trip-point0 { 4687 temperature = <90000>; 4688 hysteresis = <2000>; 4689 type = "passive"; 4690 }; 4691 4692 cpu4_bottom_alert1: trip-point1 { 4693 temperature = <95000>; 4694 hysteresis = <2000>; 4695 type = "passive"; 4696 }; 4697 4698 cpu4_bottom_crit: cpu-crit { 4699 temperature = <110000>; 4700 hysteresis = <1000>; 4701 type = "critical"; 4702 }; 4703 }; 4704 }; 4705 4706 cpu5-top-thermal { 4707 polling-delay-passive = <0>; 4708 polling-delay = <0>; 4709 thermal-sensors = <&tsens0 7>; 4710 4711 trips { 4712 cpu5_top_alert0: trip-point0 { 4713 temperature = <90000>; 4714 hysteresis = <2000>; 4715 type = "passive"; 4716 }; 4717 4718 cpu5_top_alert1: trip-point1 { 4719 temperature = <95000>; 4720 hysteresis = <2000>; 4721 type = "passive"; 4722 }; 4723 4724 cpu5_top_crit: cpu-crit { 4725 temperature = <110000>; 4726 hysteresis = <1000>; 4727 type = "critical"; 4728 }; 4729 }; 4730 }; 4731 4732 cpu5-bottom-thermal { 4733 polling-delay-passive = <0>; 4734 polling-delay = <0>; 4735 thermal-sensors = <&tsens0 8>; 4736 4737 trips { 4738 cpu5_bottom_alert0: trip-point0 { 4739 temperature = <90000>; 4740 hysteresis = <2000>; 4741 type = "passive"; 4742 }; 4743 4744 cpu5_bottom_alert1: trip-point1 { 4745 temperature = <95000>; 4746 hysteresis = <2000>; 4747 type = "passive"; 4748 }; 4749 4750 cpu5_bottom_crit: cpu-crit { 4751 temperature = <110000>; 4752 hysteresis = <1000>; 4753 type = "critical"; 4754 }; 4755 }; 4756 }; 4757 4758 cpu6-top-thermal { 4759 polling-delay-passive = <0>; 4760 polling-delay = <0>; 4761 thermal-sensors = <&tsens0 9>; 4762 4763 trips { 4764 cpu6_top_alert0: trip-point0 { 4765 temperature = <90000>; 4766 hysteresis = <2000>; 4767 type = "passive"; 4768 }; 4769 4770 cpu6_top_alert1: trip-point1 { 4771 temperature = <95000>; 4772 hysteresis = <2000>; 4773 type = "passive"; 4774 }; 4775 4776 cpu6_top_crit: cpu-crit { 4777 temperature = <110000>; 4778 hysteresis = <1000>; 4779 type = "critical"; 4780 }; 4781 }; 4782 }; 4783 4784 cpu6-bottom-thermal { 4785 polling-delay-passive = <0>; 4786 polling-delay = <0>; 4787 thermal-sensors = <&tsens0 10>; 4788 4789 trips { 4790 cpu6_bottom_alert0: trip-point0 { 4791 temperature = <90000>; 4792 hysteresis = <2000>; 4793 type = "passive"; 4794 }; 4795 4796 cpu6_bottom_alert1: trip-point1 { 4797 temperature = <95000>; 4798 hysteresis = <2000>; 4799 type = "passive"; 4800 }; 4801 4802 cpu6_bottom_crit: cpu-crit { 4803 temperature = <110000>; 4804 hysteresis = <1000>; 4805 type = "critical"; 4806 }; 4807 }; 4808 }; 4809 4810 cpu7-top-thermal { 4811 polling-delay-passive = <0>; 4812 polling-delay = <0>; 4813 thermal-sensors = <&tsens0 11>; 4814 4815 trips { 4816 cpu7_top_alert0: trip-point0 { 4817 temperature = <90000>; 4818 hysteresis = <2000>; 4819 type = "passive"; 4820 }; 4821 4822 cpu7_top_alert1: trip-point1 { 4823 temperature = <95000>; 4824 hysteresis = <2000>; 4825 type = "passive"; 4826 }; 4827 4828 cpu7_top_crit: cpu-crit { 4829 temperature = <110000>; 4830 hysteresis = <1000>; 4831 type = "critical"; 4832 }; 4833 }; 4834 }; 4835 4836 cpu7-middle-thermal { 4837 polling-delay-passive = <0>; 4838 polling-delay = <0>; 4839 thermal-sensors = <&tsens0 12>; 4840 4841 trips { 4842 cpu7_middle_alert0: trip-point0 { 4843 temperature = <90000>; 4844 hysteresis = <2000>; 4845 type = "passive"; 4846 }; 4847 4848 cpu7_middle_alert1: trip-point1 { 4849 temperature = <95000>; 4850 hysteresis = <2000>; 4851 type = "passive"; 4852 }; 4853 4854 cpu7_middle_crit: cpu-crit { 4855 temperature = <110000>; 4856 hysteresis = <1000>; 4857 type = "critical"; 4858 }; 4859 }; 4860 }; 4861 4862 cpu7-bottom-thermal { 4863 polling-delay-passive = <0>; 4864 polling-delay = <0>; 4865 thermal-sensors = <&tsens0 13>; 4866 4867 trips { 4868 cpu7_bottom_alert0: trip-point0 { 4869 temperature = <90000>; 4870 hysteresis = <2000>; 4871 type = "passive"; 4872 }; 4873 4874 cpu7_bottom_alert1: trip-point1 { 4875 temperature = <95000>; 4876 hysteresis = <2000>; 4877 type = "passive"; 4878 }; 4879 4880 cpu7_bottom_crit: cpu-crit { 4881 temperature = <110000>; 4882 hysteresis = <1000>; 4883 type = "critical"; 4884 }; 4885 }; 4886 }; 4887 4888 gpu-top-thermal { 4889 polling-delay-passive = <10>; 4890 polling-delay = <0>; 4891 thermal-sensors = <&tsens0 14>; 4892 4893 trips { 4894 thermal-engine-config { 4895 temperature = <125000>; 4896 hysteresis = <1000>; 4897 type = "passive"; 4898 }; 4899 4900 thermal-hal-config { 4901 temperature = <125000>; 4902 hysteresis = <1000>; 4903 type = "passive"; 4904 }; 4905 4906 reset-mon-cfg { 4907 temperature = <115000>; 4908 hysteresis = <5000>; 4909 type = "passive"; 4910 }; 4911 4912 gpu0_tj_cfg: tj-cfg { 4913 temperature = <95000>; 4914 hysteresis = <5000>; 4915 type = "passive"; 4916 }; 4917 }; 4918 }; 4919 4920 gpu-bottom-thermal { 4921 polling-delay-passive = <10>; 4922 polling-delay = <0>; 4923 thermal-sensors = <&tsens0 15>; 4924 4925 trips { 4926 thermal-engine-config { 4927 temperature = <125000>; 4928 hysteresis = <1000>; 4929 type = "passive"; 4930 }; 4931 4932 thermal-hal-config { 4933 temperature = <125000>; 4934 hysteresis = <1000>; 4935 type = "passive"; 4936 }; 4937 4938 reset-mon-cfg { 4939 temperature = <115000>; 4940 hysteresis = <5000>; 4941 type = "passive"; 4942 }; 4943 4944 gpu1_tj_cfg: tj-cfg { 4945 temperature = <95000>; 4946 hysteresis = <5000>; 4947 type = "passive"; 4948 }; 4949 }; 4950 }; 4951 4952 aoss1-thermal { 4953 polling-delay-passive = <0>; 4954 polling-delay = <0>; 4955 thermal-sensors = <&tsens1 0>; 4956 4957 trips { 4958 thermal-engine-config { 4959 temperature = <125000>; 4960 hysteresis = <1000>; 4961 type = "passive"; 4962 }; 4963 4964 reset-mon-cfg { 4965 temperature = <115000>; 4966 hysteresis = <5000>; 4967 type = "passive"; 4968 }; 4969 }; 4970 }; 4971 4972 cpu0-thermal { 4973 polling-delay-passive = <0>; 4974 polling-delay = <0>; 4975 thermal-sensors = <&tsens1 1>; 4976 4977 trips { 4978 cpu0_alert0: trip-point0 { 4979 temperature = <90000>; 4980 hysteresis = <2000>; 4981 type = "passive"; 4982 }; 4983 4984 cpu0_alert1: trip-point1 { 4985 temperature = <95000>; 4986 hysteresis = <2000>; 4987 type = "passive"; 4988 }; 4989 4990 cpu0_crit: cpu-crit { 4991 temperature = <110000>; 4992 hysteresis = <1000>; 4993 type = "critical"; 4994 }; 4995 }; 4996 }; 4997 4998 cpu1-thermal { 4999 polling-delay-passive = <0>; 5000 polling-delay = <0>; 5001 thermal-sensors = <&tsens1 2>; 5002 5003 trips { 5004 cpu1_alert0: trip-point0 { 5005 temperature = <90000>; 5006 hysteresis = <2000>; 5007 type = "passive"; 5008 }; 5009 5010 cpu1_alert1: trip-point1 { 5011 temperature = <95000>; 5012 hysteresis = <2000>; 5013 type = "passive"; 5014 }; 5015 5016 cpu1_crit: cpu-crit { 5017 temperature = <110000>; 5018 hysteresis = <1000>; 5019 type = "critical"; 5020 }; 5021 }; 5022 }; 5023 5024 cpu2-thermal { 5025 polling-delay-passive = <0>; 5026 polling-delay = <0>; 5027 thermal-sensors = <&tsens1 3>; 5028 5029 trips { 5030 cpu2_alert0: trip-point0 { 5031 temperature = <90000>; 5032 hysteresis = <2000>; 5033 type = "passive"; 5034 }; 5035 5036 cpu2_alert1: trip-point1 { 5037 temperature = <95000>; 5038 hysteresis = <2000>; 5039 type = "passive"; 5040 }; 5041 5042 cpu2_crit: cpu-crit { 5043 temperature = <110000>; 5044 hysteresis = <1000>; 5045 type = "critical"; 5046 }; 5047 }; 5048 }; 5049 5050 cpu3-thermal { 5051 polling-delay-passive = <0>; 5052 polling-delay = <0>; 5053 thermal-sensors = <&tsens1 4>; 5054 5055 trips { 5056 cpu3_alert0: trip-point0 { 5057 temperature = <90000>; 5058 hysteresis = <2000>; 5059 type = "passive"; 5060 }; 5061 5062 cpu3_alert1: trip-point1 { 5063 temperature = <95000>; 5064 hysteresis = <2000>; 5065 type = "passive"; 5066 }; 5067 5068 cpu3_crit: cpu-crit { 5069 temperature = <110000>; 5070 hysteresis = <1000>; 5071 type = "critical"; 5072 }; 5073 }; 5074 }; 5075 5076 cdsp0-thermal { 5077 polling-delay-passive = <10>; 5078 polling-delay = <0>; 5079 thermal-sensors = <&tsens1 5>; 5080 5081 trips { 5082 thermal-engine-config { 5083 temperature = <125000>; 5084 hysteresis = <1000>; 5085 type = "passive"; 5086 }; 5087 5088 thermal-hal-config { 5089 temperature = <125000>; 5090 hysteresis = <1000>; 5091 type = "passive"; 5092 }; 5093 5094 reset-mon-cfg { 5095 temperature = <115000>; 5096 hysteresis = <5000>; 5097 type = "passive"; 5098 }; 5099 5100 cdsp_0_config: junction-config { 5101 temperature = <95000>; 5102 hysteresis = <5000>; 5103 type = "passive"; 5104 }; 5105 }; 5106 }; 5107 5108 cdsp1-thermal { 5109 polling-delay-passive = <10>; 5110 polling-delay = <0>; 5111 thermal-sensors = <&tsens1 6>; 5112 5113 trips { 5114 thermal-engine-config { 5115 temperature = <125000>; 5116 hysteresis = <1000>; 5117 type = "passive"; 5118 }; 5119 5120 thermal-hal-config { 5121 temperature = <125000>; 5122 hysteresis = <1000>; 5123 type = "passive"; 5124 }; 5125 5126 reset-mon-cfg { 5127 temperature = <115000>; 5128 hysteresis = <5000>; 5129 type = "passive"; 5130 }; 5131 5132 cdsp_1_config: junction-config { 5133 temperature = <95000>; 5134 hysteresis = <5000>; 5135 type = "passive"; 5136 }; 5137 }; 5138 }; 5139 5140 cdsp2-thermal { 5141 polling-delay-passive = <10>; 5142 polling-delay = <0>; 5143 thermal-sensors = <&tsens1 7>; 5144 5145 trips { 5146 thermal-engine-config { 5147 temperature = <125000>; 5148 hysteresis = <1000>; 5149 type = "passive"; 5150 }; 5151 5152 thermal-hal-config { 5153 temperature = <125000>; 5154 hysteresis = <1000>; 5155 type = "passive"; 5156 }; 5157 5158 reset-mon-cfg { 5159 temperature = <115000>; 5160 hysteresis = <5000>; 5161 type = "passive"; 5162 }; 5163 5164 cdsp_2_config: junction-config { 5165 temperature = <95000>; 5166 hysteresis = <5000>; 5167 type = "passive"; 5168 }; 5169 }; 5170 }; 5171 5172 video-thermal { 5173 polling-delay-passive = <0>; 5174 polling-delay = <0>; 5175 thermal-sensors = <&tsens1 8>; 5176 5177 trips { 5178 thermal-engine-config { 5179 temperature = <125000>; 5180 hysteresis = <1000>; 5181 type = "passive"; 5182 }; 5183 5184 reset-mon-cfg { 5185 temperature = <115000>; 5186 hysteresis = <5000>; 5187 type = "passive"; 5188 }; 5189 }; 5190 }; 5191 5192 mem-thermal { 5193 polling-delay-passive = <10>; 5194 polling-delay = <0>; 5195 thermal-sensors = <&tsens1 9>; 5196 5197 trips { 5198 thermal-engine-config { 5199 temperature = <125000>; 5200 hysteresis = <1000>; 5201 type = "passive"; 5202 }; 5203 5204 ddr_config0: ddr0-config { 5205 temperature = <90000>; 5206 hysteresis = <5000>; 5207 type = "passive"; 5208 }; 5209 5210 reset-mon-cfg { 5211 temperature = <115000>; 5212 hysteresis = <5000>; 5213 type = "passive"; 5214 }; 5215 }; 5216 }; 5217 5218 modem0-thermal { 5219 polling-delay-passive = <0>; 5220 polling-delay = <0>; 5221 thermal-sensors = <&tsens1 10>; 5222 5223 trips { 5224 thermal-engine-config { 5225 temperature = <125000>; 5226 hysteresis = <1000>; 5227 type = "passive"; 5228 }; 5229 5230 mdmss0_config0: mdmss0-config0 { 5231 temperature = <102000>; 5232 hysteresis = <3000>; 5233 type = "passive"; 5234 }; 5235 5236 mdmss0_config1: mdmss0-config1 { 5237 temperature = <105000>; 5238 hysteresis = <3000>; 5239 type = "passive"; 5240 }; 5241 5242 reset-mon-cfg { 5243 temperature = <115000>; 5244 hysteresis = <5000>; 5245 type = "passive"; 5246 }; 5247 }; 5248 }; 5249 5250 modem1-thermal { 5251 polling-delay-passive = <0>; 5252 polling-delay = <0>; 5253 thermal-sensors = <&tsens1 11>; 5254 5255 trips { 5256 thermal-engine-config { 5257 temperature = <125000>; 5258 hysteresis = <1000>; 5259 type = "passive"; 5260 }; 5261 5262 mdmss1_config0: mdmss1-config0 { 5263 temperature = <102000>; 5264 hysteresis = <3000>; 5265 type = "passive"; 5266 }; 5267 5268 mdmss1_config1: mdmss1-config1 { 5269 temperature = <105000>; 5270 hysteresis = <3000>; 5271 type = "passive"; 5272 }; 5273 5274 reset-mon-cfg { 5275 temperature = <115000>; 5276 hysteresis = <5000>; 5277 type = "passive"; 5278 }; 5279 }; 5280 }; 5281 5282 modem2-thermal { 5283 polling-delay-passive = <0>; 5284 polling-delay = <0>; 5285 thermal-sensors = <&tsens1 12>; 5286 5287 trips { 5288 thermal-engine-config { 5289 temperature = <125000>; 5290 hysteresis = <1000>; 5291 type = "passive"; 5292 }; 5293 5294 mdmss2_config0: mdmss2-config0 { 5295 temperature = <102000>; 5296 hysteresis = <3000>; 5297 type = "passive"; 5298 }; 5299 5300 mdmss2_config1: mdmss2-config1 { 5301 temperature = <105000>; 5302 hysteresis = <3000>; 5303 type = "passive"; 5304 }; 5305 5306 reset-mon-cfg { 5307 temperature = <115000>; 5308 hysteresis = <5000>; 5309 type = "passive"; 5310 }; 5311 }; 5312 }; 5313 5314 modem3-thermal { 5315 polling-delay-passive = <0>; 5316 polling-delay = <0>; 5317 thermal-sensors = <&tsens1 13>; 5318 5319 trips { 5320 thermal-engine-config { 5321 temperature = <125000>; 5322 hysteresis = <1000>; 5323 type = "passive"; 5324 }; 5325 5326 mdmss3_config0: mdmss3-config0 { 5327 temperature = <102000>; 5328 hysteresis = <3000>; 5329 type = "passive"; 5330 }; 5331 5332 mdmss3_config1: mdmss3-config1 { 5333 temperature = <105000>; 5334 hysteresis = <3000>; 5335 type = "passive"; 5336 }; 5337 5338 reset-mon-cfg { 5339 temperature = <115000>; 5340 hysteresis = <5000>; 5341 type = "passive"; 5342 }; 5343 }; 5344 }; 5345 5346 camera0-thermal { 5347 polling-delay-passive = <0>; 5348 polling-delay = <0>; 5349 thermal-sensors = <&tsens1 14>; 5350 5351 trips { 5352 thermal-engine-config { 5353 temperature = <125000>; 5354 hysteresis = <1000>; 5355 type = "passive"; 5356 }; 5357 5358 reset-mon-cfg { 5359 temperature = <115000>; 5360 hysteresis = <5000>; 5361 type = "passive"; 5362 }; 5363 }; 5364 }; 5365 5366 camera1-thermal { 5367 polling-delay-passive = <0>; 5368 polling-delay = <0>; 5369 thermal-sensors = <&tsens1 15>; 5370 5371 trips { 5372 thermal-engine-config { 5373 temperature = <125000>; 5374 hysteresis = <1000>; 5375 type = "passive"; 5376 }; 5377 5378 reset-mon-cfg { 5379 temperature = <115000>; 5380 hysteresis = <5000>; 5381 type = "passive"; 5382 }; 5383 }; 5384 }; 5385 }; 5386 5387 timer { 5388 compatible = "arm,armv8-timer"; 5389 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5390 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5391 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5392 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5393 clock-frequency = <19200000>; 5394 }; 5395}; 5396