1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Linaro Limited 4 */ 5 6#include <dt-bindings/interconnect/qcom,sm8350.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/qcom,dispcc-sm8350.h> 9#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 10#include <dt-bindings/clock/qcom,gcc-sm8350.h> 11#include <dt-bindings/clock/qcom,gpucc-sm8350.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/firmware/qcom,scm.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/interconnect/qcom,icc.h> 17#include <dt-bindings/interconnect/qcom,sm8350.h> 18#include <dt-bindings/mailbox/qcom-ipcc.h> 19#include <dt-bindings/phy/phy-qcom-qmp.h> 20#include <dt-bindings/power/qcom-rpmpd.h> 21#include <dt-bindings/power/qcom,rpmhpd.h> 22#include <dt-bindings/soc/qcom,apr.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24#include <dt-bindings/sound/qcom,q6afe.h> 25#include <dt-bindings/sound/qcom,q6asm.h> 26#include <dt-bindings/thermal/thermal.h> 27#include <dt-bindings/interconnect/qcom,sm8350.h> 28 29/ { 30 interrupt-parent = <&intc>; 31 32 #address-cells = <2>; 33 #size-cells = <2>; 34 35 chosen { }; 36 37 clocks { 38 xo_board: xo-board { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <38400000>; 42 clock-output-names = "xo_board"; 43 }; 44 45 sleep_clk: sleep-clk { 46 compatible = "fixed-clock"; 47 clock-frequency = <32764>; 48 #clock-cells = <0>; 49 }; 50 }; 51 52 cpus { 53 #address-cells = <2>; 54 #size-cells = <0>; 55 56 cpu0: cpu@0 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a55"; 59 reg = <0x0 0x0>; 60 clocks = <&cpufreq_hw 0>; 61 enable-method = "psci"; 62 next-level-cache = <&l2_0>; 63 qcom,freq-domain = <&cpufreq_hw 0>; 64 power-domains = <&cpu_pd0>; 65 power-domain-names = "psci"; 66 #cooling-cells = <2>; 67 l2_0: l2-cache { 68 compatible = "cache"; 69 cache-level = <2>; 70 cache-unified; 71 next-level-cache = <&l3_0>; 72 l3_0: l3-cache { 73 compatible = "cache"; 74 cache-level = <3>; 75 cache-unified; 76 }; 77 }; 78 }; 79 80 cpu1: cpu@100 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a55"; 83 reg = <0x0 0x100>; 84 clocks = <&cpufreq_hw 0>; 85 enable-method = "psci"; 86 next-level-cache = <&l2_100>; 87 qcom,freq-domain = <&cpufreq_hw 0>; 88 power-domains = <&cpu_pd1>; 89 power-domain-names = "psci"; 90 #cooling-cells = <2>; 91 l2_100: l2-cache { 92 compatible = "cache"; 93 cache-level = <2>; 94 cache-unified; 95 next-level-cache = <&l3_0>; 96 }; 97 }; 98 99 cpu2: cpu@200 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a55"; 102 reg = <0x0 0x200>; 103 clocks = <&cpufreq_hw 0>; 104 enable-method = "psci"; 105 next-level-cache = <&l2_200>; 106 qcom,freq-domain = <&cpufreq_hw 0>; 107 power-domains = <&cpu_pd2>; 108 power-domain-names = "psci"; 109 #cooling-cells = <2>; 110 l2_200: l2-cache { 111 compatible = "cache"; 112 cache-level = <2>; 113 cache-unified; 114 next-level-cache = <&l3_0>; 115 }; 116 }; 117 118 cpu3: cpu@300 { 119 device_type = "cpu"; 120 compatible = "arm,cortex-a55"; 121 reg = <0x0 0x300>; 122 clocks = <&cpufreq_hw 0>; 123 enable-method = "psci"; 124 next-level-cache = <&l2_300>; 125 qcom,freq-domain = <&cpufreq_hw 0>; 126 power-domains = <&cpu_pd3>; 127 power-domain-names = "psci"; 128 #cooling-cells = <2>; 129 l2_300: l2-cache { 130 compatible = "cache"; 131 cache-level = <2>; 132 cache-unified; 133 next-level-cache = <&l3_0>; 134 }; 135 }; 136 137 cpu4: cpu@400 { 138 device_type = "cpu"; 139 compatible = "arm,cortex-a78"; 140 reg = <0x0 0x400>; 141 clocks = <&cpufreq_hw 1>; 142 enable-method = "psci"; 143 next-level-cache = <&l2_400>; 144 qcom,freq-domain = <&cpufreq_hw 1>; 145 power-domains = <&cpu_pd4>; 146 power-domain-names = "psci"; 147 #cooling-cells = <2>; 148 l2_400: l2-cache { 149 compatible = "cache"; 150 cache-level = <2>; 151 cache-unified; 152 next-level-cache = <&l3_0>; 153 }; 154 }; 155 156 cpu5: cpu@500 { 157 device_type = "cpu"; 158 compatible = "arm,cortex-a78"; 159 reg = <0x0 0x500>; 160 clocks = <&cpufreq_hw 1>; 161 enable-method = "psci"; 162 next-level-cache = <&l2_500>; 163 qcom,freq-domain = <&cpufreq_hw 1>; 164 power-domains = <&cpu_pd5>; 165 power-domain-names = "psci"; 166 #cooling-cells = <2>; 167 l2_500: l2-cache { 168 compatible = "cache"; 169 cache-level = <2>; 170 cache-unified; 171 next-level-cache = <&l3_0>; 172 }; 173 }; 174 175 cpu6: cpu@600 { 176 device_type = "cpu"; 177 compatible = "arm,cortex-a78"; 178 reg = <0x0 0x600>; 179 clocks = <&cpufreq_hw 1>; 180 enable-method = "psci"; 181 next-level-cache = <&l2_600>; 182 qcom,freq-domain = <&cpufreq_hw 1>; 183 power-domains = <&cpu_pd6>; 184 power-domain-names = "psci"; 185 #cooling-cells = <2>; 186 l2_600: l2-cache { 187 compatible = "cache"; 188 cache-level = <2>; 189 cache-unified; 190 next-level-cache = <&l3_0>; 191 }; 192 }; 193 194 cpu7: cpu@700 { 195 device_type = "cpu"; 196 compatible = "arm,cortex-x1"; 197 reg = <0x0 0x700>; 198 clocks = <&cpufreq_hw 2>; 199 enable-method = "psci"; 200 next-level-cache = <&l2_700>; 201 qcom,freq-domain = <&cpufreq_hw 2>; 202 power-domains = <&cpu_pd7>; 203 power-domain-names = "psci"; 204 #cooling-cells = <2>; 205 l2_700: l2-cache { 206 compatible = "cache"; 207 cache-level = <2>; 208 cache-unified; 209 next-level-cache = <&l3_0>; 210 }; 211 }; 212 213 cpu-map { 214 cluster0 { 215 core0 { 216 cpu = <&cpu0>; 217 }; 218 219 core1 { 220 cpu = <&cpu1>; 221 }; 222 223 core2 { 224 cpu = <&cpu2>; 225 }; 226 227 core3 { 228 cpu = <&cpu3>; 229 }; 230 231 core4 { 232 cpu = <&cpu4>; 233 }; 234 235 core5 { 236 cpu = <&cpu5>; 237 }; 238 239 core6 { 240 cpu = <&cpu6>; 241 }; 242 243 core7 { 244 cpu = <&cpu7>; 245 }; 246 }; 247 }; 248 249 idle-states { 250 entry-method = "psci"; 251 252 little_cpu_sleep_0: cpu-sleep-0-0 { 253 compatible = "arm,idle-state"; 254 idle-state-name = "silver-rail-power-collapse"; 255 arm,psci-suspend-param = <0x40000004>; 256 entry-latency-us = <360>; 257 exit-latency-us = <531>; 258 min-residency-us = <3934>; 259 local-timer-stop; 260 }; 261 262 big_cpu_sleep_0: cpu-sleep-1-0 { 263 compatible = "arm,idle-state"; 264 idle-state-name = "gold-rail-power-collapse"; 265 arm,psci-suspend-param = <0x40000004>; 266 entry-latency-us = <702>; 267 exit-latency-us = <1061>; 268 min-residency-us = <4488>; 269 local-timer-stop; 270 }; 271 }; 272 273 domain-idle-states { 274 cluster_sleep_apss_off: cluster-sleep-0 { 275 compatible = "domain-idle-state"; 276 arm,psci-suspend-param = <0x41000044>; 277 entry-latency-us = <2752>; 278 exit-latency-us = <3048>; 279 min-residency-us = <6118>; 280 }; 281 282 cluster_sleep_aoss_sleep: cluster-sleep-1 { 283 compatible = "domain-idle-state"; 284 arm,psci-suspend-param = <0x4100c344>; 285 entry-latency-us = <3263>; 286 exit-latency-us = <6562>; 287 min-residency-us = <9987>; 288 }; 289 }; 290 }; 291 292 firmware { 293 scm: scm { 294 compatible = "qcom,scm-sm8350", "qcom,scm"; 295 qcom,dload-mode = <&tcsr 0x13000>; 296 #reset-cells = <1>; 297 }; 298 }; 299 300 memory@80000000 { 301 device_type = "memory"; 302 /* We expect the bootloader to fill in the size */ 303 reg = <0x0 0x80000000 0x0 0x0>; 304 }; 305 306 pmu-a55 { 307 compatible = "arm,cortex-a55-pmu"; 308 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 309 }; 310 311 pmu-a78 { 312 compatible = "arm,cortex-a78-pmu"; 313 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 314 }; 315 316 pmu-x1 { 317 compatible = "arm,cortex-x1-pmu"; 318 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 319 }; 320 321 psci { 322 compatible = "arm,psci-1.0"; 323 method = "smc"; 324 325 cpu_pd0: power-domain-cpu0 { 326 #power-domain-cells = <0>; 327 power-domains = <&cluster_pd>; 328 domain-idle-states = <&little_cpu_sleep_0>; 329 }; 330 331 cpu_pd1: power-domain-cpu1 { 332 #power-domain-cells = <0>; 333 power-domains = <&cluster_pd>; 334 domain-idle-states = <&little_cpu_sleep_0>; 335 }; 336 337 cpu_pd2: power-domain-cpu2 { 338 #power-domain-cells = <0>; 339 power-domains = <&cluster_pd>; 340 domain-idle-states = <&little_cpu_sleep_0>; 341 }; 342 343 cpu_pd3: power-domain-cpu3 { 344 #power-domain-cells = <0>; 345 power-domains = <&cluster_pd>; 346 domain-idle-states = <&little_cpu_sleep_0>; 347 }; 348 349 cpu_pd4: power-domain-cpu4 { 350 #power-domain-cells = <0>; 351 power-domains = <&cluster_pd>; 352 domain-idle-states = <&big_cpu_sleep_0>; 353 }; 354 355 cpu_pd5: power-domain-cpu5 { 356 #power-domain-cells = <0>; 357 power-domains = <&cluster_pd>; 358 domain-idle-states = <&big_cpu_sleep_0>; 359 }; 360 361 cpu_pd6: power-domain-cpu6 { 362 #power-domain-cells = <0>; 363 power-domains = <&cluster_pd>; 364 domain-idle-states = <&big_cpu_sleep_0>; 365 }; 366 367 cpu_pd7: power-domain-cpu7 { 368 #power-domain-cells = <0>; 369 power-domains = <&cluster_pd>; 370 domain-idle-states = <&big_cpu_sleep_0>; 371 }; 372 373 cluster_pd: power-domain-cpu-cluster0 { 374 #power-domain-cells = <0>; 375 domain-idle-states = <&cluster_sleep_apss_off &cluster_sleep_aoss_sleep>; 376 }; 377 }; 378 379 qup_opp_table_100mhz: opp-table-qup100mhz { 380 compatible = "operating-points-v2"; 381 382 opp-50000000 { 383 opp-hz = /bits/ 64 <50000000>; 384 required-opps = <&rpmhpd_opp_min_svs>; 385 }; 386 387 opp-75000000 { 388 opp-hz = /bits/ 64 <75000000>; 389 required-opps = <&rpmhpd_opp_low_svs>; 390 }; 391 392 opp-100000000 { 393 opp-hz = /bits/ 64 <100000000>; 394 required-opps = <&rpmhpd_opp_svs>; 395 }; 396 }; 397 398 qup_opp_table_120mhz: opp-table-qup120mhz { 399 compatible = "operating-points-v2"; 400 401 opp-50000000 { 402 opp-hz = /bits/ 64 <50000000>; 403 required-opps = <&rpmhpd_opp_min_svs>; 404 }; 405 406 opp-75000000 { 407 opp-hz = /bits/ 64 <75000000>; 408 required-opps = <&rpmhpd_opp_low_svs>; 409 }; 410 411 opp-120000000 { 412 opp-hz = /bits/ 64 <120000000>; 413 required-opps = <&rpmhpd_opp_svs>; 414 }; 415 }; 416 417 reserved_memory: reserved-memory { 418 #address-cells = <2>; 419 #size-cells = <2>; 420 ranges; 421 422 hyp_mem: memory@80000000 { 423 reg = <0x0 0x80000000 0x0 0x600000>; 424 no-map; 425 }; 426 427 xbl_aop_mem: memory@80700000 { 428 no-map; 429 reg = <0x0 0x80700000 0x0 0x160000>; 430 }; 431 432 cmd_db: memory@80860000 { 433 compatible = "qcom,cmd-db"; 434 reg = <0x0 0x80860000 0x0 0x20000>; 435 no-map; 436 }; 437 438 reserved_xbl_uefi_log: memory@80880000 { 439 reg = <0x0 0x80880000 0x0 0x14000>; 440 no-map; 441 }; 442 443 smem@80900000 { 444 compatible = "qcom,smem"; 445 reg = <0x0 0x80900000 0x0 0x200000>; 446 hwlocks = <&tcsr_mutex 3>; 447 no-map; 448 }; 449 450 cpucp_fw_mem: memory@80b00000 { 451 reg = <0x0 0x80b00000 0x0 0x100000>; 452 no-map; 453 }; 454 455 cdsp_secure_heap: memory@80c00000 { 456 reg = <0x0 0x80c00000 0x0 0x4600000>; 457 no-map; 458 }; 459 460 pil_camera_mem: memory@85200000 { 461 reg = <0x0 0x85200000 0x0 0x500000>; 462 no-map; 463 }; 464 465 pil_video_mem: memory@85700000 { 466 reg = <0x0 0x85700000 0x0 0x500000>; 467 no-map; 468 }; 469 470 pil_cvp_mem: memory@85c00000 { 471 reg = <0x0 0x85c00000 0x0 0x500000>; 472 no-map; 473 }; 474 475 pil_adsp_mem: memory@86100000 { 476 reg = <0x0 0x86100000 0x0 0x2100000>; 477 no-map; 478 }; 479 480 pil_slpi_mem: memory@88200000 { 481 reg = <0x0 0x88200000 0x0 0x1500000>; 482 no-map; 483 }; 484 485 pil_cdsp_mem: memory@89700000 { 486 reg = <0x0 0x89700000 0x0 0x1e00000>; 487 no-map; 488 }; 489 490 pil_ipa_fw_mem: memory@8b500000 { 491 reg = <0x0 0x8b500000 0x0 0x10000>; 492 no-map; 493 }; 494 495 pil_ipa_gsi_mem: memory@8b510000 { 496 reg = <0x0 0x8b510000 0x0 0xa000>; 497 no-map; 498 }; 499 500 pil_gpu_mem: memory@8b51a000 { 501 reg = <0x0 0x8b51a000 0x0 0x2000>; 502 no-map; 503 }; 504 505 pil_spss_mem: memory@8b600000 { 506 reg = <0x0 0x8b600000 0x0 0x100000>; 507 no-map; 508 }; 509 510 pil_modem_mem: memory@8b800000 { 511 reg = <0x0 0x8b800000 0x0 0x10000000>; 512 no-map; 513 }; 514 515 rmtfs_mem: memory@9b800000 { 516 compatible = "qcom,rmtfs-mem"; 517 reg = <0x0 0x9b800000 0x0 0x280000>; 518 no-map; 519 520 qcom,client-id = <1>; 521 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 522 }; 523 524 hyp_reserved_mem: memory@d0000000 { 525 reg = <0x0 0xd0000000 0x0 0x800000>; 526 no-map; 527 }; 528 529 pil_trustedvm_mem: memory@d0800000 { 530 reg = <0x0 0xd0800000 0x0 0x76f7000>; 531 no-map; 532 }; 533 534 qrtr_shbuf: memory@d7ef7000 { 535 reg = <0x0 0xd7ef7000 0x0 0x9000>; 536 no-map; 537 }; 538 539 chan0_shbuf: memory@d7f00000 { 540 reg = <0x0 0xd7f00000 0x0 0x80000>; 541 no-map; 542 }; 543 544 chan1_shbuf: memory@d7f80000 { 545 reg = <0x0 0xd7f80000 0x0 0x80000>; 546 no-map; 547 }; 548 549 removed_mem: memory@d8800000 { 550 reg = <0x0 0xd8800000 0x0 0x6800000>; 551 no-map; 552 }; 553 }; 554 555 smp2p-adsp { 556 compatible = "qcom,smp2p"; 557 qcom,smem = <443>, <429>; 558 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 559 IPCC_MPROC_SIGNAL_SMP2P 560 IRQ_TYPE_EDGE_RISING>; 561 mboxes = <&ipcc IPCC_CLIENT_LPASS 562 IPCC_MPROC_SIGNAL_SMP2P>; 563 564 qcom,local-pid = <0>; 565 qcom,remote-pid = <2>; 566 567 smp2p_adsp_out: master-kernel { 568 qcom,entry-name = "master-kernel"; 569 #qcom,smem-state-cells = <1>; 570 }; 571 572 smp2p_adsp_in: slave-kernel { 573 qcom,entry-name = "slave-kernel"; 574 interrupt-controller; 575 #interrupt-cells = <2>; 576 }; 577 }; 578 579 smp2p-cdsp { 580 compatible = "qcom,smp2p"; 581 qcom,smem = <94>, <432>; 582 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 583 IPCC_MPROC_SIGNAL_SMP2P 584 IRQ_TYPE_EDGE_RISING>; 585 mboxes = <&ipcc IPCC_CLIENT_CDSP 586 IPCC_MPROC_SIGNAL_SMP2P>; 587 588 qcom,local-pid = <0>; 589 qcom,remote-pid = <5>; 590 591 smp2p_cdsp_out: master-kernel { 592 qcom,entry-name = "master-kernel"; 593 #qcom,smem-state-cells = <1>; 594 }; 595 596 smp2p_cdsp_in: slave-kernel { 597 qcom,entry-name = "slave-kernel"; 598 interrupt-controller; 599 #interrupt-cells = <2>; 600 }; 601 }; 602 603 smp2p-modem { 604 compatible = "qcom,smp2p"; 605 qcom,smem = <435>, <428>; 606 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 607 IPCC_MPROC_SIGNAL_SMP2P 608 IRQ_TYPE_EDGE_RISING>; 609 mboxes = <&ipcc IPCC_CLIENT_MPSS 610 IPCC_MPROC_SIGNAL_SMP2P>; 611 612 qcom,local-pid = <0>; 613 qcom,remote-pid = <1>; 614 615 smp2p_modem_out: master-kernel { 616 qcom,entry-name = "master-kernel"; 617 #qcom,smem-state-cells = <1>; 618 }; 619 620 smp2p_modem_in: slave-kernel { 621 qcom,entry-name = "slave-kernel"; 622 interrupt-controller; 623 #interrupt-cells = <2>; 624 }; 625 626 ipa_smp2p_out: ipa-ap-to-modem { 627 qcom,entry-name = "ipa"; 628 #qcom,smem-state-cells = <1>; 629 }; 630 631 ipa_smp2p_in: ipa-modem-to-ap { 632 qcom,entry-name = "ipa"; 633 interrupt-controller; 634 #interrupt-cells = <2>; 635 }; 636 }; 637 638 smp2p-slpi { 639 compatible = "qcom,smp2p"; 640 qcom,smem = <481>, <430>; 641 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 642 IPCC_MPROC_SIGNAL_SMP2P 643 IRQ_TYPE_EDGE_RISING>; 644 mboxes = <&ipcc IPCC_CLIENT_SLPI 645 IPCC_MPROC_SIGNAL_SMP2P>; 646 647 qcom,local-pid = <0>; 648 qcom,remote-pid = <3>; 649 650 smp2p_slpi_out: master-kernel { 651 qcom,entry-name = "master-kernel"; 652 #qcom,smem-state-cells = <1>; 653 }; 654 655 smp2p_slpi_in: slave-kernel { 656 qcom,entry-name = "slave-kernel"; 657 interrupt-controller; 658 #interrupt-cells = <2>; 659 }; 660 }; 661 662 soc: soc@0 { 663 #address-cells = <2>; 664 #size-cells = <2>; 665 ranges = <0 0 0 0 0x10 0>; 666 dma-ranges = <0 0 0 0 0x10 0>; 667 compatible = "simple-bus"; 668 669 gcc: clock-controller@100000 { 670 compatible = "qcom,gcc-sm8350"; 671 reg = <0x0 0x00100000 0x0 0x1f0000>; 672 #clock-cells = <1>; 673 #reset-cells = <1>; 674 #power-domain-cells = <1>; 675 clock-names = "bi_tcxo", 676 "sleep_clk", 677 "pcie_0_pipe_clk", 678 "pcie_1_pipe_clk", 679 "ufs_card_rx_symbol_0_clk", 680 "ufs_card_rx_symbol_1_clk", 681 "ufs_card_tx_symbol_0_clk", 682 "ufs_phy_rx_symbol_0_clk", 683 "ufs_phy_rx_symbol_1_clk", 684 "ufs_phy_tx_symbol_0_clk", 685 "usb3_phy_wrapper_gcc_usb30_pipe_clk", 686 "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; 687 clocks = <&rpmhcc RPMH_CXO_CLK>, 688 <&sleep_clk>, 689 <&pcie0_phy>, 690 <&pcie1_phy>, 691 <0>, 692 <0>, 693 <0>, 694 <&ufs_mem_phy 0>, 695 <&ufs_mem_phy 1>, 696 <&ufs_mem_phy 2>, 697 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 698 <0>; 699 }; 700 701 ipcc: mailbox@408000 { 702 compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; 703 reg = <0 0x00408000 0 0x1000>; 704 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 705 interrupt-controller; 706 #interrupt-cells = <3>; 707 #mbox-cells = <2>; 708 }; 709 710 gpi_dma2: dma-controller@800000 { 711 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 712 reg = <0 0x00800000 0 0x60000>; 713 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 725 dma-channels = <12>; 726 dma-channel-mask = <0xff>; 727 iommus = <&apps_smmu 0x5f6 0x0>; 728 #dma-cells = <3>; 729 status = "disabled"; 730 }; 731 732 qupv3_id_2: geniqup@8c0000 { 733 compatible = "qcom,geni-se-qup"; 734 reg = <0x0 0x008c0000 0x0 0x6000>; 735 clock-names = "m-ahb", "s-ahb"; 736 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 737 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 738 iommus = <&apps_smmu 0x5e3 0x0>; 739 #address-cells = <2>; 740 #size-cells = <2>; 741 ranges; 742 status = "disabled"; 743 744 i2c14: i2c@880000 { 745 compatible = "qcom,geni-i2c"; 746 reg = <0 0x00880000 0 0x4000>; 747 clock-names = "se"; 748 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 749 pinctrl-names = "default"; 750 pinctrl-0 = <&qup_i2c14_default>; 751 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 752 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 753 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 754 dma-names = "tx", "rx"; 755 #address-cells = <1>; 756 #size-cells = <0>; 757 status = "disabled"; 758 }; 759 760 spi14: spi@880000 { 761 compatible = "qcom,geni-spi"; 762 reg = <0 0x00880000 0 0x4000>; 763 clock-names = "se"; 764 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 765 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 766 power-domains = <&rpmhpd RPMHPD_CX>; 767 operating-points-v2 = <&qup_opp_table_120mhz>; 768 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 769 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 770 dma-names = "tx", "rx"; 771 #address-cells = <1>; 772 #size-cells = <0>; 773 status = "disabled"; 774 }; 775 776 i2c15: i2c@884000 { 777 compatible = "qcom,geni-i2c"; 778 reg = <0 0x00884000 0 0x4000>; 779 clock-names = "se"; 780 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 781 pinctrl-names = "default"; 782 pinctrl-0 = <&qup_i2c15_default>; 783 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 784 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 785 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 786 dma-names = "tx", "rx"; 787 #address-cells = <1>; 788 #size-cells = <0>; 789 status = "disabled"; 790 }; 791 792 spi15: spi@884000 { 793 compatible = "qcom,geni-spi"; 794 reg = <0 0x00884000 0 0x4000>; 795 clock-names = "se"; 796 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 797 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 798 power-domains = <&rpmhpd RPMHPD_CX>; 799 operating-points-v2 = <&qup_opp_table_120mhz>; 800 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 801 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 802 dma-names = "tx", "rx"; 803 #address-cells = <1>; 804 #size-cells = <0>; 805 status = "disabled"; 806 }; 807 808 i2c16: i2c@888000 { 809 compatible = "qcom,geni-i2c"; 810 reg = <0 0x00888000 0 0x4000>; 811 clock-names = "se"; 812 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 813 pinctrl-names = "default"; 814 pinctrl-0 = <&qup_i2c16_default>; 815 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 816 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 817 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 818 dma-names = "tx", "rx"; 819 #address-cells = <1>; 820 #size-cells = <0>; 821 status = "disabled"; 822 }; 823 824 spi16: spi@888000 { 825 compatible = "qcom,geni-spi"; 826 reg = <0 0x00888000 0 0x4000>; 827 clock-names = "se"; 828 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 829 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 830 power-domains = <&rpmhpd RPMHPD_CX>; 831 operating-points-v2 = <&qup_opp_table_100mhz>; 832 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 833 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 834 dma-names = "tx", "rx"; 835 #address-cells = <1>; 836 #size-cells = <0>; 837 status = "disabled"; 838 }; 839 840 i2c17: i2c@88c000 { 841 compatible = "qcom,geni-i2c"; 842 reg = <0 0x0088c000 0 0x4000>; 843 clock-names = "se"; 844 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 845 pinctrl-names = "default"; 846 pinctrl-0 = <&qup_i2c17_default>; 847 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 848 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 849 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 850 dma-names = "tx", "rx"; 851 #address-cells = <1>; 852 #size-cells = <0>; 853 status = "disabled"; 854 }; 855 856 spi17: spi@88c000 { 857 compatible = "qcom,geni-spi"; 858 reg = <0 0x0088c000 0 0x4000>; 859 clock-names = "se"; 860 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 861 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 862 power-domains = <&rpmhpd RPMHPD_CX>; 863 operating-points-v2 = <&qup_opp_table_100mhz>; 864 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 865 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 866 dma-names = "tx", "rx"; 867 #address-cells = <1>; 868 #size-cells = <0>; 869 status = "disabled"; 870 }; 871 872 /* QUP no. 18 seems to be strictly SPI/UART-only */ 873 874 spi18: spi@890000 { 875 compatible = "qcom,geni-spi"; 876 reg = <0 0x00890000 0 0x4000>; 877 clock-names = "se"; 878 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 879 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 880 power-domains = <&rpmhpd RPMHPD_CX>; 881 operating-points-v2 = <&qup_opp_table_100mhz>; 882 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 883 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 884 dma-names = "tx", "rx"; 885 #address-cells = <1>; 886 #size-cells = <0>; 887 status = "disabled"; 888 }; 889 890 uart18: serial@890000 { 891 compatible = "qcom,geni-uart"; 892 reg = <0 0x00890000 0 0x4000>; 893 clock-names = "se"; 894 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 895 pinctrl-names = "default"; 896 pinctrl-0 = <&qup_uart18_default>; 897 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 898 power-domains = <&rpmhpd RPMHPD_CX>; 899 operating-points-v2 = <&qup_opp_table_100mhz>; 900 status = "disabled"; 901 }; 902 903 i2c19: i2c@894000 { 904 compatible = "qcom,geni-i2c"; 905 reg = <0 0x00894000 0 0x4000>; 906 clock-names = "se"; 907 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 908 pinctrl-names = "default"; 909 pinctrl-0 = <&qup_i2c19_default>; 910 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 911 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 912 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 913 dma-names = "tx", "rx"; 914 #address-cells = <1>; 915 #size-cells = <0>; 916 status = "disabled"; 917 }; 918 919 spi19: spi@894000 { 920 compatible = "qcom,geni-spi"; 921 reg = <0 0x00894000 0 0x4000>; 922 clock-names = "se"; 923 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 924 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 925 power-domains = <&rpmhpd RPMHPD_CX>; 926 operating-points-v2 = <&qup_opp_table_100mhz>; 927 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 928 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 929 dma-names = "tx", "rx"; 930 #address-cells = <1>; 931 #size-cells = <0>; 932 status = "disabled"; 933 }; 934 }; 935 936 gpi_dma0: dma-controller@900000 { 937 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 938 reg = <0 0x00900000 0 0x60000>; 939 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 951 dma-channels = <12>; 952 dma-channel-mask = <0x7e>; 953 iommus = <&apps_smmu 0x5b6 0x0>; 954 #dma-cells = <3>; 955 status = "disabled"; 956 }; 957 958 qupv3_id_0: geniqup@9c0000 { 959 compatible = "qcom,geni-se-qup"; 960 reg = <0x0 0x009c0000 0x0 0x6000>; 961 clock-names = "m-ahb", "s-ahb"; 962 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 963 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 964 iommus = <&apps_smmu 0x5a3 0>; 965 #address-cells = <2>; 966 #size-cells = <2>; 967 ranges; 968 status = "disabled"; 969 970 i2c0: i2c@980000 { 971 compatible = "qcom,geni-i2c"; 972 reg = <0 0x00980000 0 0x4000>; 973 clock-names = "se"; 974 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 975 pinctrl-names = "default"; 976 pinctrl-0 = <&qup_i2c0_default>; 977 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 978 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 979 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 980 dma-names = "tx", "rx"; 981 #address-cells = <1>; 982 #size-cells = <0>; 983 status = "disabled"; 984 }; 985 986 spi0: spi@980000 { 987 compatible = "qcom,geni-spi"; 988 reg = <0 0x00980000 0 0x4000>; 989 clock-names = "se"; 990 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 991 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 992 power-domains = <&rpmhpd RPMHPD_CX>; 993 operating-points-v2 = <&qup_opp_table_100mhz>; 994 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 995 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 996 dma-names = "tx", "rx"; 997 #address-cells = <1>; 998 #size-cells = <0>; 999 status = "disabled"; 1000 }; 1001 1002 i2c1: i2c@984000 { 1003 compatible = "qcom,geni-i2c"; 1004 reg = <0 0x00984000 0 0x4000>; 1005 clock-names = "se"; 1006 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1007 pinctrl-names = "default"; 1008 pinctrl-0 = <&qup_i2c1_default>; 1009 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1010 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1011 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1012 dma-names = "tx", "rx"; 1013 #address-cells = <1>; 1014 #size-cells = <0>; 1015 status = "disabled"; 1016 }; 1017 1018 spi1: spi@984000 { 1019 compatible = "qcom,geni-spi"; 1020 reg = <0 0x00984000 0 0x4000>; 1021 clock-names = "se"; 1022 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1023 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1024 power-domains = <&rpmhpd RPMHPD_CX>; 1025 operating-points-v2 = <&qup_opp_table_100mhz>; 1026 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1027 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1028 dma-names = "tx", "rx"; 1029 #address-cells = <1>; 1030 #size-cells = <0>; 1031 status = "disabled"; 1032 }; 1033 1034 i2c2: i2c@988000 { 1035 compatible = "qcom,geni-i2c"; 1036 reg = <0 0x00988000 0 0x4000>; 1037 clock-names = "se"; 1038 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1039 pinctrl-names = "default"; 1040 pinctrl-0 = <&qup_i2c2_default>; 1041 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1042 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1043 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1044 dma-names = "tx", "rx"; 1045 #address-cells = <1>; 1046 #size-cells = <0>; 1047 status = "disabled"; 1048 }; 1049 1050 spi2: spi@988000 { 1051 compatible = "qcom,geni-spi"; 1052 reg = <0 0x00988000 0 0x4000>; 1053 clock-names = "se"; 1054 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1055 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1056 power-domains = <&rpmhpd RPMHPD_CX>; 1057 operating-points-v2 = <&qup_opp_table_100mhz>; 1058 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1059 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1060 dma-names = "tx", "rx"; 1061 #address-cells = <1>; 1062 #size-cells = <0>; 1063 status = "disabled"; 1064 }; 1065 1066 uart2: serial@98c000 { 1067 compatible = "qcom,geni-debug-uart"; 1068 reg = <0 0x0098c000 0 0x4000>; 1069 clock-names = "se"; 1070 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1071 pinctrl-names = "default"; 1072 pinctrl-0 = <&qup_uart3_default_state>; 1073 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1074 power-domains = <&rpmhpd RPMHPD_CX>; 1075 operating-points-v2 = <&qup_opp_table_100mhz>; 1076 status = "disabled"; 1077 }; 1078 1079 /* QUP no. 3 seems to be strictly SPI-only */ 1080 1081 spi3: spi@98c000 { 1082 compatible = "qcom,geni-spi"; 1083 reg = <0 0x0098c000 0 0x4000>; 1084 clock-names = "se"; 1085 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1086 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1087 power-domains = <&rpmhpd RPMHPD_CX>; 1088 operating-points-v2 = <&qup_opp_table_100mhz>; 1089 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1090 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1091 dma-names = "tx", "rx"; 1092 #address-cells = <1>; 1093 #size-cells = <0>; 1094 status = "disabled"; 1095 }; 1096 1097 i2c4: i2c@990000 { 1098 compatible = "qcom,geni-i2c"; 1099 reg = <0 0x00990000 0 0x4000>; 1100 clock-names = "se"; 1101 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1102 pinctrl-names = "default"; 1103 pinctrl-0 = <&qup_i2c4_default>; 1104 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1105 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1106 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1107 dma-names = "tx", "rx"; 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 status = "disabled"; 1111 }; 1112 1113 spi4: spi@990000 { 1114 compatible = "qcom,geni-spi"; 1115 reg = <0 0x00990000 0 0x4000>; 1116 clock-names = "se"; 1117 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1118 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1119 power-domains = <&rpmhpd RPMHPD_CX>; 1120 operating-points-v2 = <&qup_opp_table_100mhz>; 1121 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1122 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1123 dma-names = "tx", "rx"; 1124 #address-cells = <1>; 1125 #size-cells = <0>; 1126 status = "disabled"; 1127 }; 1128 1129 i2c5: i2c@994000 { 1130 compatible = "qcom,geni-i2c"; 1131 reg = <0 0x00994000 0 0x4000>; 1132 clock-names = "se"; 1133 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1134 pinctrl-names = "default"; 1135 pinctrl-0 = <&qup_i2c5_default>; 1136 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1137 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1138 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1139 dma-names = "tx", "rx"; 1140 #address-cells = <1>; 1141 #size-cells = <0>; 1142 status = "disabled"; 1143 }; 1144 1145 spi5: spi@994000 { 1146 compatible = "qcom,geni-spi"; 1147 reg = <0 0x00994000 0 0x4000>; 1148 clock-names = "se"; 1149 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1150 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1151 power-domains = <&rpmhpd RPMHPD_CX>; 1152 operating-points-v2 = <&qup_opp_table_100mhz>; 1153 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1154 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1155 dma-names = "tx", "rx"; 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 status = "disabled"; 1159 }; 1160 1161 i2c6: i2c@998000 { 1162 compatible = "qcom,geni-i2c"; 1163 reg = <0 0x00998000 0 0x4000>; 1164 clock-names = "se"; 1165 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1166 pinctrl-names = "default"; 1167 pinctrl-0 = <&qup_i2c6_default>; 1168 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1169 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1170 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1171 dma-names = "tx", "rx"; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 status = "disabled"; 1175 }; 1176 1177 spi6: spi@998000 { 1178 compatible = "qcom,geni-spi"; 1179 reg = <0 0x00998000 0 0x4000>; 1180 clock-names = "se"; 1181 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1182 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1183 power-domains = <&rpmhpd RPMHPD_CX>; 1184 operating-points-v2 = <&qup_opp_table_100mhz>; 1185 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1186 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1187 dma-names = "tx", "rx"; 1188 #address-cells = <1>; 1189 #size-cells = <0>; 1190 status = "disabled"; 1191 }; 1192 1193 uart6: serial@998000 { 1194 compatible = "qcom,geni-uart"; 1195 reg = <0 0x00998000 0 0x4000>; 1196 clock-names = "se"; 1197 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1198 pinctrl-names = "default"; 1199 pinctrl-0 = <&qup_uart6_default>; 1200 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1201 power-domains = <&rpmhpd RPMHPD_CX>; 1202 operating-points-v2 = <&qup_opp_table_100mhz>; 1203 status = "disabled"; 1204 }; 1205 1206 i2c7: i2c@99c000 { 1207 compatible = "qcom,geni-i2c"; 1208 reg = <0 0x0099c000 0 0x4000>; 1209 clock-names = "se"; 1210 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1211 pinctrl-names = "default"; 1212 pinctrl-0 = <&qup_i2c7_default>; 1213 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1214 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1215 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1216 dma-names = "tx", "rx"; 1217 #address-cells = <1>; 1218 #size-cells = <0>; 1219 status = "disabled"; 1220 }; 1221 1222 spi7: spi@99c000 { 1223 compatible = "qcom,geni-spi"; 1224 reg = <0 0x0099c000 0 0x4000>; 1225 clock-names = "se"; 1226 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1227 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1228 power-domains = <&rpmhpd RPMHPD_CX>; 1229 operating-points-v2 = <&qup_opp_table_100mhz>; 1230 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1231 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1232 dma-names = "tx", "rx"; 1233 #address-cells = <1>; 1234 #size-cells = <0>; 1235 status = "disabled"; 1236 }; 1237 }; 1238 1239 gpi_dma1: dma-controller@a00000 { 1240 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 1241 reg = <0 0x00a00000 0 0x60000>; 1242 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1254 dma-channels = <12>; 1255 dma-channel-mask = <0xff>; 1256 iommus = <&apps_smmu 0x56 0x0>; 1257 #dma-cells = <3>; 1258 status = "disabled"; 1259 }; 1260 1261 qupv3_id_1: geniqup@ac0000 { 1262 compatible = "qcom,geni-se-qup"; 1263 reg = <0x0 0x00ac0000 0x0 0x6000>; 1264 clock-names = "m-ahb", "s-ahb"; 1265 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1266 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1267 iommus = <&apps_smmu 0x43 0>; 1268 #address-cells = <2>; 1269 #size-cells = <2>; 1270 ranges; 1271 status = "disabled"; 1272 1273 i2c8: i2c@a80000 { 1274 compatible = "qcom,geni-i2c"; 1275 reg = <0 0x00a80000 0 0x4000>; 1276 clock-names = "se"; 1277 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1278 pinctrl-names = "default"; 1279 pinctrl-0 = <&qup_i2c8_default>; 1280 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1281 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1282 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1283 dma-names = "tx", "rx"; 1284 #address-cells = <1>; 1285 #size-cells = <0>; 1286 status = "disabled"; 1287 }; 1288 1289 spi8: spi@a80000 { 1290 compatible = "qcom,geni-spi"; 1291 reg = <0 0x00a80000 0 0x4000>; 1292 clock-names = "se"; 1293 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1294 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1295 power-domains = <&rpmhpd RPMHPD_CX>; 1296 operating-points-v2 = <&qup_opp_table_120mhz>; 1297 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1298 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1299 dma-names = "tx", "rx"; 1300 #address-cells = <1>; 1301 #size-cells = <0>; 1302 status = "disabled"; 1303 }; 1304 1305 i2c9: i2c@a84000 { 1306 compatible = "qcom,geni-i2c"; 1307 reg = <0 0x00a84000 0 0x4000>; 1308 clock-names = "se"; 1309 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1310 pinctrl-names = "default"; 1311 pinctrl-0 = <&qup_i2c9_default>; 1312 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1313 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1314 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1315 dma-names = "tx", "rx"; 1316 #address-cells = <1>; 1317 #size-cells = <0>; 1318 status = "disabled"; 1319 }; 1320 1321 spi9: spi@a84000 { 1322 compatible = "qcom,geni-spi"; 1323 reg = <0 0x00a84000 0 0x4000>; 1324 clock-names = "se"; 1325 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1326 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1327 power-domains = <&rpmhpd RPMHPD_CX>; 1328 operating-points-v2 = <&qup_opp_table_100mhz>; 1329 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1330 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1331 dma-names = "tx", "rx"; 1332 #address-cells = <1>; 1333 #size-cells = <0>; 1334 status = "disabled"; 1335 }; 1336 1337 i2c10: i2c@a88000 { 1338 compatible = "qcom,geni-i2c"; 1339 reg = <0 0x00a88000 0 0x4000>; 1340 clock-names = "se"; 1341 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1342 pinctrl-names = "default"; 1343 pinctrl-0 = <&qup_i2c10_default>; 1344 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1345 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1346 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1347 dma-names = "tx", "rx"; 1348 #address-cells = <1>; 1349 #size-cells = <0>; 1350 status = "disabled"; 1351 }; 1352 1353 spi10: spi@a88000 { 1354 compatible = "qcom,geni-spi"; 1355 reg = <0 0x00a88000 0 0x4000>; 1356 clock-names = "se"; 1357 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1358 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1359 power-domains = <&rpmhpd RPMHPD_CX>; 1360 operating-points-v2 = <&qup_opp_table_100mhz>; 1361 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1362 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1363 dma-names = "tx", "rx"; 1364 #address-cells = <1>; 1365 #size-cells = <0>; 1366 status = "disabled"; 1367 }; 1368 1369 i2c11: i2c@a8c000 { 1370 compatible = "qcom,geni-i2c"; 1371 reg = <0 0x00a8c000 0 0x4000>; 1372 clock-names = "se"; 1373 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1374 pinctrl-names = "default"; 1375 pinctrl-0 = <&qup_i2c11_default>; 1376 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1377 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1378 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1379 dma-names = "tx", "rx"; 1380 #address-cells = <1>; 1381 #size-cells = <0>; 1382 status = "disabled"; 1383 }; 1384 1385 spi11: spi@a8c000 { 1386 compatible = "qcom,geni-spi"; 1387 reg = <0 0x00a8c000 0 0x4000>; 1388 clock-names = "se"; 1389 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1390 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1391 power-domains = <&rpmhpd RPMHPD_CX>; 1392 operating-points-v2 = <&qup_opp_table_100mhz>; 1393 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1394 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1395 dma-names = "tx", "rx"; 1396 #address-cells = <1>; 1397 #size-cells = <0>; 1398 status = "disabled"; 1399 }; 1400 1401 i2c12: i2c@a90000 { 1402 compatible = "qcom,geni-i2c"; 1403 reg = <0 0x00a90000 0 0x4000>; 1404 clock-names = "se"; 1405 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1406 pinctrl-names = "default"; 1407 pinctrl-0 = <&qup_i2c12_default>; 1408 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1409 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1410 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1411 dma-names = "tx", "rx"; 1412 #address-cells = <1>; 1413 #size-cells = <0>; 1414 status = "disabled"; 1415 }; 1416 1417 spi12: spi@a90000 { 1418 compatible = "qcom,geni-spi"; 1419 reg = <0 0x00a90000 0 0x4000>; 1420 clock-names = "se"; 1421 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1422 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1423 power-domains = <&rpmhpd RPMHPD_CX>; 1424 operating-points-v2 = <&qup_opp_table_100mhz>; 1425 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1426 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1427 dma-names = "tx", "rx"; 1428 #address-cells = <1>; 1429 #size-cells = <0>; 1430 status = "disabled"; 1431 }; 1432 1433 i2c13: i2c@a94000 { 1434 compatible = "qcom,geni-i2c"; 1435 reg = <0 0x00a94000 0 0x4000>; 1436 clock-names = "se"; 1437 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1438 pinctrl-names = "default"; 1439 pinctrl-0 = <&qup_i2c13_default>; 1440 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1441 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1442 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1443 dma-names = "tx", "rx"; 1444 #address-cells = <1>; 1445 #size-cells = <0>; 1446 status = "disabled"; 1447 }; 1448 1449 spi13: spi@a94000 { 1450 compatible = "qcom,geni-spi"; 1451 reg = <0 0x00a94000 0 0x4000>; 1452 clock-names = "se"; 1453 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1454 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1455 power-domains = <&rpmhpd RPMHPD_CX>; 1456 operating-points-v2 = <&qup_opp_table_100mhz>; 1457 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1458 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1459 dma-names = "tx", "rx"; 1460 #address-cells = <1>; 1461 #size-cells = <0>; 1462 status = "disabled"; 1463 }; 1464 }; 1465 1466 rng: rng@10d3000 { 1467 compatible = "qcom,prng-ee"; 1468 reg = <0 0x010d3000 0 0x1000>; 1469 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1470 clock-names = "core"; 1471 }; 1472 1473 config_noc: interconnect@1500000 { 1474 compatible = "qcom,sm8350-config-noc"; 1475 reg = <0 0x01500000 0 0xa580>; 1476 #interconnect-cells = <2>; 1477 qcom,bcm-voters = <&apps_bcm_voter>; 1478 }; 1479 1480 mc_virt: interconnect@1580000 { 1481 compatible = "qcom,sm8350-mc-virt"; 1482 reg = <0 0x01580000 0 0x1000>; 1483 #interconnect-cells = <2>; 1484 qcom,bcm-voters = <&apps_bcm_voter>; 1485 }; 1486 1487 system_noc: interconnect@1680000 { 1488 compatible = "qcom,sm8350-system-noc"; 1489 reg = <0 0x01680000 0 0x1c200>; 1490 #interconnect-cells = <2>; 1491 qcom,bcm-voters = <&apps_bcm_voter>; 1492 }; 1493 1494 aggre1_noc: interconnect@16e0000 { 1495 compatible = "qcom,sm8350-aggre1-noc"; 1496 reg = <0 0x016e0000 0 0x1f180>; 1497 #interconnect-cells = <2>; 1498 qcom,bcm-voters = <&apps_bcm_voter>; 1499 }; 1500 1501 aggre2_noc: interconnect@1700000 { 1502 compatible = "qcom,sm8350-aggre2-noc"; 1503 reg = <0 0x01700000 0 0x33000>; 1504 #interconnect-cells = <2>; 1505 qcom,bcm-voters = <&apps_bcm_voter>; 1506 }; 1507 1508 mmss_noc: interconnect@1740000 { 1509 compatible = "qcom,sm8350-mmss-noc"; 1510 reg = <0 0x01740000 0 0x1f080>; 1511 #interconnect-cells = <2>; 1512 qcom,bcm-voters = <&apps_bcm_voter>; 1513 }; 1514 1515 pcie0: pcie@1c00000 { 1516 compatible = "qcom,pcie-sm8350"; 1517 reg = <0 0x01c00000 0 0x3000>, 1518 <0 0x60000000 0 0xf1d>, 1519 <0 0x60000f20 0 0xa8>, 1520 <0 0x60001000 0 0x1000>, 1521 <0 0x60100000 0 0x100000>; 1522 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1523 device_type = "pci"; 1524 linux,pci-domain = <0>; 1525 bus-range = <0x00 0xff>; 1526 num-lanes = <1>; 1527 1528 #address-cells = <3>; 1529 #size-cells = <2>; 1530 1531 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1532 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1533 1534 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1540 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1541 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1542 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1543 interrupt-names = "msi0", 1544 "msi1", 1545 "msi2", 1546 "msi3", 1547 "msi4", 1548 "msi5", 1549 "msi6", 1550 "msi7", 1551 "global"; 1552 #interrupt-cells = <1>; 1553 interrupt-map-mask = <0 0 0 0x7>; 1554 interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1555 <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1556 <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1557 <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1558 1559 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1560 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1561 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1562 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1563 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1564 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1565 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1566 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1567 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; 1568 clock-names = "aux", 1569 "cfg", 1570 "bus_master", 1571 "bus_slave", 1572 "slave_q2a", 1573 "tbu", 1574 "ddrss_sf_tbu", 1575 "aggre1", 1576 "aggre0"; 1577 1578 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1579 <0x100 &apps_smmu 0x1c01 0x1>; 1580 1581 resets = <&gcc GCC_PCIE_0_BCR>; 1582 reset-names = "pci"; 1583 1584 power-domains = <&gcc PCIE_0_GDSC>; 1585 1586 phys = <&pcie0_phy>; 1587 phy-names = "pciephy"; 1588 1589 status = "disabled"; 1590 1591 pcie@0 { 1592 device_type = "pci"; 1593 reg = <0x0 0x0 0x0 0x0 0x0>; 1594 bus-range = <0x01 0xff>; 1595 1596 #address-cells = <3>; 1597 #size-cells = <2>; 1598 ranges; 1599 }; 1600 }; 1601 1602 pcie0_phy: phy@1c06000 { 1603 compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy"; 1604 reg = <0 0x01c06000 0 0x2000>; 1605 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1606 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1607 <&gcc GCC_PCIE_0_CLKREF_EN>, 1608 <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, 1609 <&gcc GCC_PCIE_0_PIPE_CLK>; 1610 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1611 1612 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1613 reset-names = "phy"; 1614 1615 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>; 1616 assigned-clock-rates = <100000000>; 1617 1618 #clock-cells = <0>; 1619 clock-output-names = "pcie_0_pipe_clk"; 1620 1621 #phy-cells = <0>; 1622 1623 status = "disabled"; 1624 }; 1625 1626 pcie1: pcie@1c08000 { 1627 compatible = "qcom,pcie-sm8350"; 1628 reg = <0 0x01c08000 0 0x3000>, 1629 <0 0x40000000 0 0xf1d>, 1630 <0 0x40000f20 0 0xa8>, 1631 <0 0x40001000 0 0x1000>, 1632 <0 0x40100000 0 0x100000>; 1633 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1634 device_type = "pci"; 1635 linux,pci-domain = <1>; 1636 bus-range = <0x00 0xff>; 1637 num-lanes = <2>; 1638 1639 #address-cells = <3>; 1640 #size-cells = <2>; 1641 1642 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1643 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1644 1645 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1647 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1648 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1649 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1650 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1651 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 1652 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 1653 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 1654 interrupt-names = "msi0", 1655 "msi1", 1656 "msi2", 1657 "msi3", 1658 "msi4", 1659 "msi5", 1660 "msi6", 1661 "msi7", 1662 "global"; 1663 #interrupt-cells = <1>; 1664 interrupt-map-mask = <0 0 0 0x7>; 1665 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1666 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1667 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1668 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1669 1670 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1671 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1672 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1673 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1674 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1675 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1676 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1677 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1678 clock-names = "aux", 1679 "cfg", 1680 "bus_master", 1681 "bus_slave", 1682 "slave_q2a", 1683 "tbu", 1684 "ddrss_sf_tbu", 1685 "aggre1"; 1686 1687 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1688 <0x100 &apps_smmu 0x1c81 0x1>; 1689 1690 resets = <&gcc GCC_PCIE_1_BCR>; 1691 reset-names = "pci"; 1692 1693 power-domains = <&gcc PCIE_1_GDSC>; 1694 1695 phys = <&pcie1_phy>; 1696 phy-names = "pciephy"; 1697 1698 status = "disabled"; 1699 1700 pcie@0 { 1701 device_type = "pci"; 1702 reg = <0x0 0x0 0x0 0x0 0x0>; 1703 bus-range = <0x01 0xff>; 1704 1705 #address-cells = <3>; 1706 #size-cells = <2>; 1707 ranges; 1708 }; 1709 }; 1710 1711 pcie1_phy: phy@1c0e000 { 1712 compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy"; 1713 reg = <0 0x01c0e000 0 0x2000>; 1714 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1715 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1716 <&gcc GCC_PCIE_1_CLKREF_EN>, 1717 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, 1718 <&gcc GCC_PCIE_1_PIPE_CLK>; 1719 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1720 1721 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1722 reset-names = "phy"; 1723 1724 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1725 assigned-clock-rates = <100000000>; 1726 1727 #clock-cells = <0>; 1728 clock-output-names = "pcie_1_pipe_clk"; 1729 1730 #phy-cells = <0>; 1731 1732 status = "disabled"; 1733 }; 1734 1735 ufs_mem_hc: ufshc@1d84000 { 1736 compatible = "qcom,sm8350-ufshc", "qcom,ufshc", 1737 "jedec,ufs-2.0"; 1738 reg = <0 0x01d84000 0 0x3000>; 1739 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1740 phys = <&ufs_mem_phy>; 1741 phy-names = "ufsphy"; 1742 lanes-per-direction = <2>; 1743 #reset-cells = <1>; 1744 resets = <&gcc GCC_UFS_PHY_BCR>; 1745 reset-names = "rst"; 1746 1747 power-domains = <&gcc UFS_PHY_GDSC>; 1748 1749 iommus = <&apps_smmu 0xe0 0x0>; 1750 dma-coherent; 1751 1752 clock-names = 1753 "core_clk", 1754 "bus_aggr_clk", 1755 "iface_clk", 1756 "core_clk_unipro", 1757 "ref_clk", 1758 "tx_lane0_sync_clk", 1759 "rx_lane0_sync_clk", 1760 "rx_lane1_sync_clk"; 1761 clocks = 1762 <&gcc GCC_UFS_PHY_AXI_CLK>, 1763 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1764 <&gcc GCC_UFS_PHY_AHB_CLK>, 1765 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1766 <&rpmhcc RPMH_CXO_CLK>, 1767 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1768 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1769 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1770 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 1771 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1772 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1773 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 1774 interconnect-names = "ufs-ddr", "cpu-ufs"; 1775 freq-table-hz = 1776 <75000000 300000000>, 1777 <0 0>, 1778 <0 0>, 1779 <75000000 300000000>, 1780 <0 0>, 1781 <0 0>, 1782 <0 0>, 1783 <0 0>; 1784 status = "disabled"; 1785 }; 1786 1787 ufs_mem_phy: phy@1d87000 { 1788 compatible = "qcom,sm8350-qmp-ufs-phy"; 1789 reg = <0 0x01d87000 0 0x1000>; 1790 1791 clocks = <&rpmhcc RPMH_CXO_CLK>, 1792 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1793 <&gcc GCC_UFS_1_CLKREF_EN>; 1794 clock-names = "ref", 1795 "ref_aux", 1796 "qref"; 1797 1798 power-domains = <&gcc UFS_PHY_GDSC>; 1799 1800 resets = <&ufs_mem_hc 0>; 1801 reset-names = "ufsphy"; 1802 1803 #clock-cells = <1>; 1804 #phy-cells = <0>; 1805 1806 status = "disabled"; 1807 }; 1808 1809 cryptobam: dma-controller@1dc4000 { 1810 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1811 reg = <0 0x01dc4000 0 0x24000>; 1812 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1813 #dma-cells = <1>; 1814 qcom,ee = <0>; 1815 qcom,num-ees = <4>; 1816 num-channels = <16>; 1817 qcom,controlled-remotely; 1818 iommus = <&apps_smmu 0x594 0x0011>, 1819 <&apps_smmu 0x596 0x0011>; 1820 }; 1821 1822 crypto: crypto@1dfa000 { 1823 compatible = "qcom,sm8350-qce", "qcom,sm8150-qce", "qcom,qce"; 1824 reg = <0 0x01dfa000 0 0x6000>; 1825 dmas = <&cryptobam 4>, <&cryptobam 5>; 1826 dma-names = "rx", "tx"; 1827 iommus = <&apps_smmu 0x594 0x0011>, 1828 <&apps_smmu 0x596 0x0011>; 1829 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 1830 interconnect-names = "memory"; 1831 }; 1832 1833 ipa: ipa@1e40000 { 1834 compatible = "qcom,sm8350-ipa"; 1835 1836 iommus = <&apps_smmu 0x5c0 0x0>, 1837 <&apps_smmu 0x5c2 0x0>; 1838 reg = <0 0x01e40000 0 0x8000>, 1839 <0 0x01e50000 0 0x4b20>, 1840 <0 0x01e04000 0 0x23000>; 1841 reg-names = "ipa-reg", 1842 "ipa-shared", 1843 "gsi"; 1844 1845 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, 1846 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1847 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1848 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1849 interrupt-names = "ipa", 1850 "gsi", 1851 "ipa-clock-query", 1852 "ipa-setup-ready"; 1853 1854 clocks = <&rpmhcc RPMH_IPA_CLK>; 1855 clock-names = "core"; 1856 1857 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1858 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1859 interconnect-names = "memory", 1860 "config"; 1861 1862 qcom,qmp = <&aoss_qmp>; 1863 1864 qcom,smem-states = <&ipa_smp2p_out 0>, 1865 <&ipa_smp2p_out 1>; 1866 qcom,smem-state-names = "ipa-clock-enabled-valid", 1867 "ipa-clock-enabled"; 1868 1869 sram = <&ipa_modem_tables>; 1870 1871 status = "disabled"; 1872 }; 1873 1874 tcsr_mutex: hwlock@1f40000 { 1875 compatible = "qcom,tcsr-mutex"; 1876 reg = <0x0 0x01f40000 0x0 0x40000>; 1877 #hwlock-cells = <1>; 1878 }; 1879 1880 tcsr: syscon@1fc0000 { 1881 compatible = "qcom,sm8350-tcsr", "syscon"; 1882 reg = <0x0 0x1fc0000 0x0 0x30000>; 1883 }; 1884 1885 adsp: remoteproc@3000000 { 1886 compatible = "qcom,sm8350-adsp-pas"; 1887 reg = <0x0 0x03000000 0x0 0x10000>; 1888 1889 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 1890 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1891 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1892 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1893 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1894 interrupt-names = "wdog", "fatal", "ready", 1895 "handover", "stop-ack"; 1896 1897 clocks = <&rpmhcc RPMH_CXO_CLK>; 1898 clock-names = "xo"; 1899 1900 power-domains = <&rpmhpd RPMHPD_LCX>, 1901 <&rpmhpd RPMHPD_LMX>; 1902 power-domain-names = "lcx", "lmx"; 1903 1904 memory-region = <&pil_adsp_mem>; 1905 1906 qcom,qmp = <&aoss_qmp>; 1907 1908 qcom,smem-states = <&smp2p_adsp_out 0>; 1909 qcom,smem-state-names = "stop"; 1910 1911 status = "disabled"; 1912 1913 glink-edge { 1914 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1915 IPCC_MPROC_SIGNAL_GLINK_QMP 1916 IRQ_TYPE_EDGE_RISING>; 1917 mboxes = <&ipcc IPCC_CLIENT_LPASS 1918 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1919 1920 label = "lpass"; 1921 qcom,remote-pid = <2>; 1922 1923 apr { 1924 compatible = "qcom,apr-v2"; 1925 qcom,glink-channels = "apr_audio_svc"; 1926 qcom,domain = <APR_DOMAIN_ADSP>; 1927 #address-cells = <1>; 1928 #size-cells = <0>; 1929 1930 service@3 { 1931 reg = <APR_SVC_ADSP_CORE>; 1932 compatible = "qcom,q6core"; 1933 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1934 }; 1935 1936 q6afe: service@4 { 1937 compatible = "qcom,q6afe"; 1938 reg = <APR_SVC_AFE>; 1939 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1940 1941 q6afedai: dais { 1942 compatible = "qcom,q6afe-dais"; 1943 #address-cells = <1>; 1944 #size-cells = <0>; 1945 #sound-dai-cells = <1>; 1946 }; 1947 1948 q6afecc: clock-controller { 1949 compatible = "qcom,q6afe-clocks"; 1950 #clock-cells = <2>; 1951 }; 1952 }; 1953 1954 q6asm: service@7 { 1955 compatible = "qcom,q6asm"; 1956 reg = <APR_SVC_ASM>; 1957 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1958 1959 q6asmdai: dais { 1960 compatible = "qcom,q6asm-dais"; 1961 #address-cells = <1>; 1962 #size-cells = <0>; 1963 #sound-dai-cells = <1>; 1964 iommus = <&apps_smmu 0x1801 0x0>; 1965 1966 dai@0 { 1967 reg = <MSM_FRONTEND_DAI_MULTIMEDIA1>; 1968 }; 1969 1970 dai@1 { 1971 reg = <MSM_FRONTEND_DAI_MULTIMEDIA2>; 1972 }; 1973 1974 dai@2 { 1975 reg = <MSM_FRONTEND_DAI_MULTIMEDIA3>; 1976 }; 1977 }; 1978 }; 1979 1980 q6adm: service@8 { 1981 compatible = "qcom,q6adm"; 1982 reg = <APR_SVC_ADM>; 1983 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1984 1985 q6routing: routing { 1986 compatible = "qcom,q6adm-routing"; 1987 #sound-dai-cells = <0>; 1988 }; 1989 }; 1990 }; 1991 1992 fastrpc { 1993 compatible = "qcom,fastrpc"; 1994 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1995 label = "adsp"; 1996 qcom,non-secure-domain; 1997 #address-cells = <1>; 1998 #size-cells = <0>; 1999 2000 compute-cb@3 { 2001 compatible = "qcom,fastrpc-compute-cb"; 2002 reg = <3>; 2003 iommus = <&apps_smmu 0x1803 0x0>; 2004 }; 2005 2006 compute-cb@4 { 2007 compatible = "qcom,fastrpc-compute-cb"; 2008 reg = <4>; 2009 iommus = <&apps_smmu 0x1804 0x0>; 2010 }; 2011 2012 compute-cb@5 { 2013 compatible = "qcom,fastrpc-compute-cb"; 2014 reg = <5>; 2015 iommus = <&apps_smmu 0x1805 0x0>; 2016 }; 2017 }; 2018 }; 2019 }; 2020 2021 lpass_tlmm: pinctrl@33c0000 { 2022 compatible = "qcom,sm8350-lpass-lpi-pinctrl"; 2023 reg = <0 0x033c0000 0 0x20000>, 2024 <0 0x03550000 0 0x10000>; 2025 2026 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2027 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2028 clock-names = "core", "audio"; 2029 2030 gpio-controller; 2031 #gpio-cells = <2>; 2032 gpio-ranges = <&lpass_tlmm 0 0 15>; 2033 }; 2034 2035 gpu: gpu@3d00000 { 2036 compatible = "qcom,adreno-660.1", "qcom,adreno"; 2037 2038 reg = <0 0x03d00000 0 0x40000>, 2039 <0 0x03d9e000 0 0x1000>, 2040 <0 0x03d61000 0 0x800>; 2041 reg-names = "kgsl_3d0_reg_memory", 2042 "cx_mem", 2043 "cx_dbgc"; 2044 2045 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2046 2047 iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>; 2048 2049 operating-points-v2 = <&gpu_opp_table>; 2050 2051 qcom,gmu = <&gmu>; 2052 #cooling-cells = <2>; 2053 2054 status = "disabled"; 2055 2056 gpu_zap_shader: zap-shader { 2057 memory-region = <&pil_gpu_mem>; 2058 }; 2059 2060 /* note: downstream checks gpu binning for 670 Mhz */ 2061 gpu_opp_table: opp-table { 2062 compatible = "operating-points-v2"; 2063 2064 opp-840000000 { 2065 opp-hz = /bits/ 64 <840000000>; 2066 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2067 }; 2068 2069 opp-778000000 { 2070 opp-hz = /bits/ 64 <778000000>; 2071 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2072 }; 2073 2074 opp-738000000 { 2075 opp-hz = /bits/ 64 <738000000>; 2076 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2077 }; 2078 2079 opp-676000000 { 2080 opp-hz = /bits/ 64 <676000000>; 2081 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2082 }; 2083 2084 opp-608000000 { 2085 opp-hz = /bits/ 64 <608000000>; 2086 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2087 }; 2088 2089 opp-540000000 { 2090 opp-hz = /bits/ 64 <540000000>; 2091 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2092 }; 2093 2094 opp-491000000 { 2095 opp-hz = /bits/ 64 <491000000>; 2096 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2097 }; 2098 2099 opp-443000000 { 2100 opp-hz = /bits/ 64 <443000000>; 2101 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2102 }; 2103 2104 opp-379000000 { 2105 opp-hz = /bits/ 64 <379000000>; 2106 opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>; 2107 }; 2108 2109 opp-315000000 { 2110 opp-hz = /bits/ 64 <315000000>; 2111 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2112 }; 2113 }; 2114 }; 2115 2116 gmu: gmu@3d6a000 { 2117 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu"; 2118 2119 reg = <0 0x03d6a000 0 0x34000>, 2120 <0 0x03de0000 0 0x10000>, 2121 <0 0x0b290000 0 0x10000>; 2122 reg-names = "gmu", "rscc", "gmu_pdc"; 2123 2124 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2125 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2126 interrupt-names = "hfi", "gmu"; 2127 2128 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2129 <&gpucc GPU_CC_CXO_CLK>, 2130 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2131 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2132 <&gpucc GPU_CC_AHB_CLK>, 2133 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2134 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2135 clock-names = "gmu", 2136 "cxo", 2137 "axi", 2138 "memnoc", 2139 "ahb", 2140 "hub", 2141 "smmu_vote"; 2142 2143 power-domains = <&gpucc GPU_CX_GDSC>, 2144 <&gpucc GPU_GX_GDSC>; 2145 power-domain-names = "cx", 2146 "gx"; 2147 2148 iommus = <&adreno_smmu 5 0x400>; 2149 2150 operating-points-v2 = <&gmu_opp_table>; 2151 2152 gmu_opp_table: opp-table { 2153 compatible = "operating-points-v2"; 2154 2155 opp-200000000 { 2156 opp-hz = /bits/ 64 <200000000>; 2157 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2158 }; 2159 }; 2160 }; 2161 2162 gpucc: clock-controller@3d90000 { 2163 compatible = "qcom,sm8350-gpucc"; 2164 reg = <0 0x03d90000 0 0x9000>; 2165 clocks = <&rpmhcc RPMH_CXO_CLK>, 2166 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2167 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2168 clock-names = "bi_tcxo", 2169 "gcc_gpu_gpll0_clk_src", 2170 "gcc_gpu_gpll0_div_clk_src"; 2171 #clock-cells = <1>; 2172 #reset-cells = <1>; 2173 #power-domain-cells = <1>; 2174 }; 2175 2176 adreno_smmu: iommu@3da0000 { 2177 compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu", 2178 "qcom,smmu-500", "arm,mmu-500"; 2179 reg = <0 0x03da0000 0 0x20000>; 2180 #iommu-cells = <2>; 2181 #global-interrupts = <2>; 2182 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2183 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2184 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2185 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2186 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2187 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2188 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2189 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2190 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2191 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2192 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2193 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2194 2195 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2196 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2197 <&gpucc GPU_CC_AHB_CLK>, 2198 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2199 <&gpucc GPU_CC_CX_GMU_CLK>, 2200 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2201 <&gpucc GPU_CC_HUB_AON_CLK>; 2202 clock-names = "bus", 2203 "iface", 2204 "ahb", 2205 "hlos1_vote_gpu_smmu", 2206 "cx_gmu", 2207 "hub_cx_int", 2208 "hub_aon"; 2209 2210 power-domains = <&gpucc GPU_CX_GDSC>; 2211 dma-coherent; 2212 }; 2213 2214 lpass_ag_noc: interconnect@3c40000 { 2215 compatible = "qcom,sm8350-lpass-ag-noc"; 2216 reg = <0 0x03c40000 0 0xf080>; 2217 #interconnect-cells = <2>; 2218 qcom,bcm-voters = <&apps_bcm_voter>; 2219 }; 2220 2221 mpss: remoteproc@4080000 { 2222 compatible = "qcom,sm8350-mpss-pas"; 2223 reg = <0x0 0x04080000 0x0 0x10000>; 2224 2225 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2226 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2227 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2228 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2229 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2230 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2231 interrupt-names = "wdog", "fatal", "ready", "handover", 2232 "stop-ack", "shutdown-ack"; 2233 2234 clocks = <&rpmhcc RPMH_CXO_CLK>; 2235 clock-names = "xo"; 2236 2237 power-domains = <&rpmhpd RPMHPD_CX>, 2238 <&rpmhpd RPMHPD_MSS>; 2239 power-domain-names = "cx", "mss"; 2240 2241 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2242 2243 memory-region = <&pil_modem_mem>; 2244 2245 qcom,qmp = <&aoss_qmp>; 2246 2247 qcom,smem-states = <&smp2p_modem_out 0>; 2248 qcom,smem-state-names = "stop"; 2249 2250 status = "disabled"; 2251 2252 glink-edge { 2253 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2254 IPCC_MPROC_SIGNAL_GLINK_QMP 2255 IRQ_TYPE_EDGE_RISING>; 2256 mboxes = <&ipcc IPCC_CLIENT_MPSS 2257 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2258 label = "modem"; 2259 qcom,remote-pid = <1>; 2260 }; 2261 }; 2262 2263 slpi: remoteproc@5c00000 { 2264 compatible = "qcom,sm8350-slpi-pas"; 2265 reg = <0 0x05c00000 0 0x4000>; 2266 2267 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2268 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2269 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2270 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2271 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2272 interrupt-names = "wdog", "fatal", "ready", 2273 "handover", "stop-ack"; 2274 2275 clocks = <&rpmhcc RPMH_CXO_CLK>; 2276 clock-names = "xo"; 2277 2278 power-domains = <&rpmhpd RPMHPD_LCX>, 2279 <&rpmhpd RPMHPD_LMX>; 2280 power-domain-names = "lcx", "lmx"; 2281 2282 memory-region = <&pil_slpi_mem>; 2283 2284 qcom,qmp = <&aoss_qmp>; 2285 2286 qcom,smem-states = <&smp2p_slpi_out 0>; 2287 qcom,smem-state-names = "stop"; 2288 2289 status = "disabled"; 2290 2291 glink-edge { 2292 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2293 IPCC_MPROC_SIGNAL_GLINK_QMP 2294 IRQ_TYPE_EDGE_RISING>; 2295 mboxes = <&ipcc IPCC_CLIENT_SLPI 2296 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2297 2298 label = "slpi"; 2299 qcom,remote-pid = <3>; 2300 2301 fastrpc { 2302 compatible = "qcom,fastrpc"; 2303 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2304 label = "sdsp"; 2305 qcom,non-secure-domain; 2306 #address-cells = <1>; 2307 #size-cells = <0>; 2308 2309 compute-cb@1 { 2310 compatible = "qcom,fastrpc-compute-cb"; 2311 reg = <1>; 2312 iommus = <&apps_smmu 0x0541 0x0>; 2313 }; 2314 2315 compute-cb@2 { 2316 compatible = "qcom,fastrpc-compute-cb"; 2317 reg = <2>; 2318 iommus = <&apps_smmu 0x0542 0x0>; 2319 }; 2320 2321 compute-cb@3 { 2322 compatible = "qcom,fastrpc-compute-cb"; 2323 reg = <3>; 2324 iommus = <&apps_smmu 0x0543 0x0>; 2325 /* note: shared-cb = <4> in downstream */ 2326 }; 2327 }; 2328 }; 2329 }; 2330 2331 sdhc_2: mmc@8804000 { 2332 compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5"; 2333 reg = <0 0x08804000 0 0x1000>; 2334 2335 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2336 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2337 interrupt-names = "hc_irq", "pwr_irq"; 2338 2339 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2340 <&gcc GCC_SDCC2_APPS_CLK>, 2341 <&rpmhcc RPMH_CXO_CLK>; 2342 clock-names = "iface", "core", "xo"; 2343 resets = <&gcc GCC_SDCC2_BCR>; 2344 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2345 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2346 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2347 iommus = <&apps_smmu 0x4a0 0x0>; 2348 power-domains = <&rpmhpd RPMHPD_CX>; 2349 operating-points-v2 = <&sdhc2_opp_table>; 2350 bus-width = <4>; 2351 dma-coherent; 2352 2353 status = "disabled"; 2354 2355 sdhc2_opp_table: opp-table { 2356 compatible = "operating-points-v2"; 2357 2358 opp-100000000 { 2359 opp-hz = /bits/ 64 <100000000>; 2360 required-opps = <&rpmhpd_opp_low_svs>; 2361 }; 2362 2363 opp-202000000 { 2364 opp-hz = /bits/ 64 <202000000>; 2365 required-opps = <&rpmhpd_opp_svs_l1>; 2366 }; 2367 }; 2368 }; 2369 2370 usb_1_hsphy: phy@88e3000 { 2371 compatible = "qcom,sm8350-usb-hs-phy", 2372 "qcom,usb-snps-hs-7nm-phy"; 2373 reg = <0 0x088e3000 0 0x400>; 2374 status = "disabled"; 2375 #phy-cells = <0>; 2376 2377 clocks = <&rpmhcc RPMH_CXO_CLK>; 2378 clock-names = "ref"; 2379 2380 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2381 }; 2382 2383 usb_2_hsphy: phy@88e4000 { 2384 compatible = "qcom,sm8250-usb-hs-phy", 2385 "qcom,usb-snps-hs-7nm-phy"; 2386 reg = <0 0x088e4000 0 0x400>; 2387 status = "disabled"; 2388 #phy-cells = <0>; 2389 2390 clocks = <&rpmhcc RPMH_CXO_CLK>; 2391 clock-names = "ref"; 2392 2393 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2394 }; 2395 2396 refgen: regulator@88e7000 { 2397 compatible = "qcom,sm8350-refgen-regulator", 2398 "qcom,sm8250-refgen-regulator"; 2399 reg = <0x0 0x088e7000 0x0 0x84>; 2400 }; 2401 2402 usb_1_qmpphy: phy@88e8000 { 2403 compatible = "qcom,sm8350-qmp-usb3-dp-phy"; 2404 reg = <0 0x088e8000 0 0x3000>; 2405 2406 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2407 <&rpmhcc RPMH_CXO_CLK>, 2408 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2409 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2410 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2411 2412 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2413 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2414 reset-names = "phy", "common"; 2415 2416 #clock-cells = <1>; 2417 #phy-cells = <1>; 2418 2419 orientation-switch; 2420 2421 status = "disabled"; 2422 2423 ports { 2424 #address-cells = <1>; 2425 #size-cells = <0>; 2426 2427 port@0 { 2428 reg = <0>; 2429 2430 usb_1_qmpphy_out: endpoint { 2431 }; 2432 }; 2433 2434 port@1 { 2435 reg = <1>; 2436 2437 usb_1_qmpphy_usb_ss_in: endpoint { 2438 remote-endpoint = <&usb_1_dwc3_ss>; 2439 }; 2440 }; 2441 2442 port@2 { 2443 reg = <2>; 2444 2445 usb_1_qmpphy_dp_in: endpoint { 2446 remote-endpoint = <&mdss_dp_out>; 2447 }; 2448 }; 2449 }; 2450 }; 2451 2452 usb_2_qmpphy: phy@88eb000 { 2453 compatible = "qcom,sm8350-qmp-usb3-uni-phy"; 2454 reg = <0 0x088eb000 0 0x2000>; 2455 status = "disabled"; 2456 2457 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2458 <&gcc GCC_USB3_SEC_CLKREF_EN>, 2459 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2460 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2461 clock-names = "aux", 2462 "ref", 2463 "com_aux", 2464 "pipe"; 2465 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2466 #clock-cells = <0>; 2467 #phy-cells = <0>; 2468 2469 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2470 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 2471 reset-names = "phy", 2472 "phy_phy"; 2473 }; 2474 2475 dc_noc: interconnect@90c0000 { 2476 compatible = "qcom,sm8350-dc-noc"; 2477 reg = <0 0x090c0000 0 0x4200>; 2478 #interconnect-cells = <2>; 2479 qcom,bcm-voters = <&apps_bcm_voter>; 2480 }; 2481 2482 gem_noc: interconnect@9100000 { 2483 compatible = "qcom,sm8350-gem-noc"; 2484 reg = <0 0x09100000 0 0xb4000>; 2485 #interconnect-cells = <2>; 2486 qcom,bcm-voters = <&apps_bcm_voter>; 2487 }; 2488 2489 system-cache-controller@9200000 { 2490 compatible = "qcom,sm8350-llcc"; 2491 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 2492 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 2493 <0 0x09600000 0 0x58000>; 2494 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2495 "llcc3_base", "llcc_broadcast_base"; 2496 }; 2497 2498 compute_noc: interconnect@a0c0000 { 2499 compatible = "qcom,sm8350-compute-noc"; 2500 reg = <0 0x0a0c0000 0 0xa180>; 2501 #interconnect-cells = <2>; 2502 qcom,bcm-voters = <&apps_bcm_voter>; 2503 }; 2504 2505 cdsp: remoteproc@a300000 { 2506 compatible = "qcom,sm8350-cdsp-pas"; 2507 reg = <0x0 0x0a300000 0x0 0x10000>; 2508 2509 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2510 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2511 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2512 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2513 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 2514 interrupt-names = "wdog", "fatal", "ready", 2515 "handover", "stop-ack"; 2516 2517 clocks = <&rpmhcc RPMH_CXO_CLK>; 2518 clock-names = "xo"; 2519 2520 power-domains = <&rpmhpd RPMHPD_CX>, 2521 <&rpmhpd RPMHPD_MXC>; 2522 power-domain-names = "cx", "mxc"; 2523 2524 interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 2525 2526 memory-region = <&pil_cdsp_mem>; 2527 2528 qcom,qmp = <&aoss_qmp>; 2529 2530 qcom,smem-states = <&smp2p_cdsp_out 0>; 2531 qcom,smem-state-names = "stop"; 2532 2533 status = "disabled"; 2534 2535 glink-edge { 2536 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2537 IPCC_MPROC_SIGNAL_GLINK_QMP 2538 IRQ_TYPE_EDGE_RISING>; 2539 mboxes = <&ipcc IPCC_CLIENT_CDSP 2540 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2541 2542 label = "cdsp"; 2543 qcom,remote-pid = <5>; 2544 2545 fastrpc { 2546 compatible = "qcom,fastrpc"; 2547 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2548 label = "cdsp"; 2549 qcom,non-secure-domain; 2550 #address-cells = <1>; 2551 #size-cells = <0>; 2552 2553 compute-cb@1 { 2554 compatible = "qcom,fastrpc-compute-cb"; 2555 reg = <1>; 2556 iommus = <&apps_smmu 0x2161 0x0400>, 2557 <&apps_smmu 0x1181 0x0420>; 2558 }; 2559 2560 compute-cb@2 { 2561 compatible = "qcom,fastrpc-compute-cb"; 2562 reg = <2>; 2563 iommus = <&apps_smmu 0x2162 0x0400>, 2564 <&apps_smmu 0x1182 0x0420>; 2565 }; 2566 2567 compute-cb@3 { 2568 compatible = "qcom,fastrpc-compute-cb"; 2569 reg = <3>; 2570 iommus = <&apps_smmu 0x2163 0x0400>, 2571 <&apps_smmu 0x1183 0x0420>; 2572 }; 2573 2574 compute-cb@4 { 2575 compatible = "qcom,fastrpc-compute-cb"; 2576 reg = <4>; 2577 iommus = <&apps_smmu 0x2164 0x0400>, 2578 <&apps_smmu 0x1184 0x0420>; 2579 }; 2580 2581 compute-cb@5 { 2582 compatible = "qcom,fastrpc-compute-cb"; 2583 reg = <5>; 2584 iommus = <&apps_smmu 0x2165 0x0400>, 2585 <&apps_smmu 0x1185 0x0420>; 2586 }; 2587 2588 compute-cb@6 { 2589 compatible = "qcom,fastrpc-compute-cb"; 2590 reg = <6>; 2591 iommus = <&apps_smmu 0x2166 0x0400>, 2592 <&apps_smmu 0x1186 0x0420>; 2593 }; 2594 2595 compute-cb@7 { 2596 compatible = "qcom,fastrpc-compute-cb"; 2597 reg = <7>; 2598 iommus = <&apps_smmu 0x2167 0x0400>, 2599 <&apps_smmu 0x1187 0x0420>; 2600 }; 2601 2602 compute-cb@8 { 2603 compatible = "qcom,fastrpc-compute-cb"; 2604 reg = <8>; 2605 iommus = <&apps_smmu 0x2168 0x0400>, 2606 <&apps_smmu 0x1188 0x0420>; 2607 }; 2608 2609 /* note: secure cb9 in downstream */ 2610 }; 2611 }; 2612 }; 2613 2614 usb_1: usb@a6f8800 { 2615 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2616 reg = <0 0x0a6f8800 0 0x400>; 2617 status = "disabled"; 2618 #address-cells = <2>; 2619 #size-cells = <2>; 2620 ranges; 2621 2622 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2623 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2624 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2625 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2626 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 2627 clock-names = "cfg_noc", 2628 "core", 2629 "iface", 2630 "sleep", 2631 "mock_utmi"; 2632 2633 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2634 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2635 assigned-clock-rates = <19200000>, <200000000>; 2636 2637 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2638 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2639 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2640 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2641 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2642 interrupt-names = "pwr_event", 2643 "hs_phy_irq", 2644 "dp_hs_phy_irq", 2645 "dm_hs_phy_irq", 2646 "ss_phy_irq"; 2647 2648 power-domains = <&gcc USB30_PRIM_GDSC>; 2649 2650 resets = <&gcc GCC_USB30_PRIM_BCR>; 2651 2652 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2653 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 2654 interconnect-names = "usb-ddr", "apps-usb"; 2655 2656 usb_1_dwc3: usb@a600000 { 2657 compatible = "snps,dwc3"; 2658 reg = <0 0x0a600000 0 0xcd00>; 2659 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2660 iommus = <&apps_smmu 0x0 0x0>; 2661 snps,dis_u2_susphy_quirk; 2662 snps,dis_u3_susphy_quirk; 2663 snps,dis_enblslpm_quirk; 2664 snps,dis-u1-entry-quirk; 2665 snps,dis-u2-entry-quirk; 2666 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 2667 phy-names = "usb2-phy", "usb3-phy"; 2668 2669 ports { 2670 #address-cells = <1>; 2671 #size-cells = <0>; 2672 2673 port@0 { 2674 reg = <0>; 2675 2676 usb_1_dwc3_hs: endpoint { 2677 }; 2678 }; 2679 2680 port@1 { 2681 reg = <1>; 2682 2683 usb_1_dwc3_ss: endpoint { 2684 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 2685 }; 2686 }; 2687 }; 2688 }; 2689 }; 2690 2691 usb_2: usb@a8f8800 { 2692 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2693 reg = <0 0x0a8f8800 0 0x400>; 2694 status = "disabled"; 2695 #address-cells = <2>; 2696 #size-cells = <2>; 2697 ranges; 2698 2699 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2700 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2701 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2702 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2703 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2704 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2705 clock-names = "cfg_noc", 2706 "core", 2707 "iface", 2708 "sleep", 2709 "mock_utmi", 2710 "xo"; 2711 2712 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2713 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2714 assigned-clock-rates = <19200000>, <200000000>; 2715 2716 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 2717 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2718 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 2719 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 2720 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 2721 interrupt-names = "pwr_event", 2722 "hs_phy_irq", 2723 "dp_hs_phy_irq", 2724 "dm_hs_phy_irq", 2725 "ss_phy_irq"; 2726 2727 power-domains = <&gcc USB30_SEC_GDSC>; 2728 2729 resets = <&gcc GCC_USB30_SEC_BCR>; 2730 2731 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 2732 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 2733 interconnect-names = "usb-ddr", "apps-usb"; 2734 2735 usb_2_dwc3: usb@a800000 { 2736 compatible = "snps,dwc3"; 2737 reg = <0 0x0a800000 0 0xcd00>; 2738 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2739 iommus = <&apps_smmu 0x20 0x0>; 2740 snps,dis_u2_susphy_quirk; 2741 snps,dis_u3_susphy_quirk; 2742 snps,dis_enblslpm_quirk; 2743 snps,dis-u1-entry-quirk; 2744 snps,dis-u2-entry-quirk; 2745 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>; 2746 phy-names = "usb2-phy", "usb3-phy"; 2747 }; 2748 }; 2749 2750 mdss: display-subsystem@ae00000 { 2751 compatible = "qcom,sm8350-mdss"; 2752 reg = <0 0x0ae00000 0 0x1000>; 2753 reg-names = "mdss"; 2754 2755 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 2756 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>, 2757 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2758 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 2759 interconnect-names = "mdp0-mem", 2760 "mdp1-mem", 2761 "cpu-cfg"; 2762 2763 power-domains = <&dispcc MDSS_GDSC>; 2764 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2765 2766 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2767 <&gcc GCC_DISP_HF_AXI_CLK>, 2768 <&gcc GCC_DISP_SF_AXI_CLK>, 2769 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2770 clock-names = "iface", "bus", "nrt_bus", "core"; 2771 2772 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2773 interrupt-controller; 2774 #interrupt-cells = <1>; 2775 2776 iommus = <&apps_smmu 0x820 0x402>; 2777 2778 status = "disabled"; 2779 2780 #address-cells = <2>; 2781 #size-cells = <2>; 2782 ranges; 2783 2784 mdss_mdp: display-controller@ae01000 { 2785 compatible = "qcom,sm8350-dpu"; 2786 reg = <0 0x0ae01000 0 0x8f000>, 2787 <0 0x0aeb0000 0 0x3000>; 2788 reg-names = "mdp", "vbif"; 2789 2790 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2791 <&gcc GCC_DISP_SF_AXI_CLK>, 2792 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2793 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2794 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2795 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2796 clock-names = "bus", 2797 "nrt_bus", 2798 "iface", 2799 "lut", 2800 "core", 2801 "vsync"; 2802 2803 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2804 assigned-clock-rates = <19200000>; 2805 2806 operating-points-v2 = <&dpu_opp_table>; 2807 power-domains = <&rpmhpd RPMHPD_MMCX>; 2808 2809 interrupt-parent = <&mdss>; 2810 interrupts = <0>; 2811 2812 dpu_opp_table: opp-table { 2813 compatible = "operating-points-v2"; 2814 2815 /* TODO: opp-200000000 should work with 2816 * &rpmhpd_opp_low_svs, but one some of 2817 * sm8350_hdk boards reboot using this 2818 * opp. 2819 */ 2820 opp-200000000 { 2821 opp-hz = /bits/ 64 <200000000>; 2822 required-opps = <&rpmhpd_opp_svs>; 2823 }; 2824 2825 opp-300000000 { 2826 opp-hz = /bits/ 64 <300000000>; 2827 required-opps = <&rpmhpd_opp_svs>; 2828 }; 2829 2830 opp-345000000 { 2831 opp-hz = /bits/ 64 <345000000>; 2832 required-opps = <&rpmhpd_opp_svs_l1>; 2833 }; 2834 2835 opp-460000000 { 2836 opp-hz = /bits/ 64 <460000000>; 2837 required-opps = <&rpmhpd_opp_nom>; 2838 }; 2839 }; 2840 2841 ports { 2842 #address-cells = <1>; 2843 #size-cells = <0>; 2844 2845 port@0 { 2846 reg = <0>; 2847 dpu_intf1_out: endpoint { 2848 remote-endpoint = <&mdss_dsi0_in>; 2849 }; 2850 }; 2851 2852 port@1 { 2853 reg = <1>; 2854 dpu_intf2_out: endpoint { 2855 remote-endpoint = <&mdss_dsi1_in>; 2856 }; 2857 }; 2858 2859 port@2 { 2860 reg = <2>; 2861 dpu_intf0_out: endpoint { 2862 remote-endpoint = <&mdss_dp_in>; 2863 }; 2864 }; 2865 }; 2866 }; 2867 2868 mdss_dp: displayport-controller@ae90000 { 2869 compatible = "qcom,sm8350-dp"; 2870 reg = <0 0xae90000 0 0x200>, 2871 <0 0xae90200 0 0x200>, 2872 <0 0xae90400 0 0x600>, 2873 <0 0xae91000 0 0x400>, 2874 <0 0xae91400 0 0x400>; 2875 interrupt-parent = <&mdss>; 2876 interrupts = <12>; 2877 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2878 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 2879 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 2880 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 2881 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, 2882 <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; 2883 clock-names = "core_iface", 2884 "core_aux", 2885 "ctrl_link", 2886 "ctrl_link_iface", 2887 "stream_pixel", 2888 "stream_1_pixel"; 2889 2890 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 2891 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, 2892 <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; 2893 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2894 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 2895 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2896 2897 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 2898 phy-names = "dp"; 2899 2900 #sound-dai-cells = <0>; 2901 2902 operating-points-v2 = <&dp_opp_table>; 2903 power-domains = <&rpmhpd RPMHPD_MMCX>; 2904 2905 status = "disabled"; 2906 2907 ports { 2908 #address-cells = <1>; 2909 #size-cells = <0>; 2910 2911 port@0 { 2912 reg = <0>; 2913 mdss_dp_in: endpoint { 2914 remote-endpoint = <&dpu_intf0_out>; 2915 }; 2916 }; 2917 2918 port@1 { 2919 reg = <1>; 2920 2921 mdss_dp_out: endpoint { 2922 remote-endpoint = <&usb_1_qmpphy_dp_in>; 2923 }; 2924 }; 2925 }; 2926 2927 dp_opp_table: opp-table { 2928 compatible = "operating-points-v2"; 2929 2930 opp-162000000 { 2931 opp-hz = /bits/ 64 <162000000>; 2932 required-opps = <&rpmhpd_opp_low_svs>; 2933 }; 2934 2935 opp-270000000 { 2936 opp-hz = /bits/ 64 <270000000>; 2937 required-opps = <&rpmhpd_opp_svs>; 2938 }; 2939 2940 opp-540000000 { 2941 opp-hz = /bits/ 64 <540000000>; 2942 required-opps = <&rpmhpd_opp_svs_l1>; 2943 }; 2944 2945 opp-810000000 { 2946 opp-hz = /bits/ 64 <810000000>; 2947 required-opps = <&rpmhpd_opp_nom>; 2948 }; 2949 }; 2950 }; 2951 2952 mdss_dsi0: dsi@ae94000 { 2953 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2954 reg = <0 0x0ae94000 0 0x400>; 2955 reg-names = "dsi_ctrl"; 2956 2957 interrupt-parent = <&mdss>; 2958 interrupts = <4>; 2959 2960 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2961 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2962 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2963 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2964 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2965 <&gcc GCC_DISP_HF_AXI_CLK>; 2966 clock-names = "byte", 2967 "byte_intf", 2968 "pixel", 2969 "core", 2970 "iface", 2971 "bus"; 2972 2973 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2974 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2975 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2976 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 2977 2978 operating-points-v2 = <&dsi0_opp_table>; 2979 power-domains = <&rpmhpd RPMHPD_MMCX>; 2980 refgen-supply = <&refgen>; 2981 2982 phys = <&mdss_dsi0_phy>; 2983 2984 #address-cells = <1>; 2985 #size-cells = <0>; 2986 2987 status = "disabled"; 2988 2989 dsi0_opp_table: opp-table { 2990 compatible = "operating-points-v2"; 2991 2992 /* TODO: opp-187500000 should work with 2993 * &rpmhpd_opp_low_svs, but one some of 2994 * sm8350_hdk boards reboot using this 2995 * opp. 2996 */ 2997 opp-187500000 { 2998 opp-hz = /bits/ 64 <187500000>; 2999 required-opps = <&rpmhpd_opp_svs>; 3000 }; 3001 3002 opp-300000000 { 3003 opp-hz = /bits/ 64 <300000000>; 3004 required-opps = <&rpmhpd_opp_svs>; 3005 }; 3006 3007 opp-358000000 { 3008 opp-hz = /bits/ 64 <358000000>; 3009 required-opps = <&rpmhpd_opp_svs_l1>; 3010 }; 3011 }; 3012 3013 ports { 3014 #address-cells = <1>; 3015 #size-cells = <0>; 3016 3017 port@0 { 3018 reg = <0>; 3019 mdss_dsi0_in: endpoint { 3020 remote-endpoint = <&dpu_intf1_out>; 3021 }; 3022 }; 3023 3024 port@1 { 3025 reg = <1>; 3026 mdss_dsi0_out: endpoint { 3027 }; 3028 }; 3029 }; 3030 }; 3031 3032 mdss_dsi0_phy: phy@ae94400 { 3033 compatible = "qcom,sm8350-dsi-phy-5nm"; 3034 reg = <0 0x0ae94400 0 0x200>, 3035 <0 0x0ae94600 0 0x280>, 3036 <0 0x0ae94900 0 0x27c>; 3037 reg-names = "dsi_phy", 3038 "dsi_phy_lane", 3039 "dsi_pll"; 3040 3041 #clock-cells = <1>; 3042 #phy-cells = <0>; 3043 3044 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3045 <&rpmhcc RPMH_CXO_CLK>; 3046 clock-names = "iface", "ref"; 3047 3048 status = "disabled"; 3049 }; 3050 3051 mdss_dsi1: dsi@ae96000 { 3052 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3053 reg = <0 0x0ae96000 0 0x400>; 3054 reg-names = "dsi_ctrl"; 3055 3056 interrupt-parent = <&mdss>; 3057 interrupts = <5>; 3058 3059 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3060 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3061 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3062 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3063 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3064 <&gcc GCC_DISP_HF_AXI_CLK>; 3065 clock-names = "byte", 3066 "byte_intf", 3067 "pixel", 3068 "core", 3069 "iface", 3070 "bus"; 3071 3072 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 3073 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3074 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 3075 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 3076 3077 operating-points-v2 = <&dsi1_opp_table>; 3078 power-domains = <&rpmhpd RPMHPD_MMCX>; 3079 refgen-supply = <&refgen>; 3080 3081 phys = <&mdss_dsi1_phy>; 3082 3083 #address-cells = <1>; 3084 #size-cells = <0>; 3085 3086 status = "disabled"; 3087 3088 dsi1_opp_table: opp-table { 3089 compatible = "operating-points-v2"; 3090 3091 /* TODO: opp-187500000 should work with 3092 * &rpmhpd_opp_low_svs, but one some of 3093 * sm8350_hdk boards reboot using this 3094 * opp. 3095 */ 3096 opp-187500000 { 3097 opp-hz = /bits/ 64 <187500000>; 3098 required-opps = <&rpmhpd_opp_svs>; 3099 }; 3100 3101 opp-300000000 { 3102 opp-hz = /bits/ 64 <300000000>; 3103 required-opps = <&rpmhpd_opp_svs>; 3104 }; 3105 3106 opp-358000000 { 3107 opp-hz = /bits/ 64 <358000000>; 3108 required-opps = <&rpmhpd_opp_svs_l1>; 3109 }; 3110 }; 3111 3112 ports { 3113 #address-cells = <1>; 3114 #size-cells = <0>; 3115 3116 port@0 { 3117 reg = <0>; 3118 mdss_dsi1_in: endpoint { 3119 remote-endpoint = <&dpu_intf2_out>; 3120 }; 3121 }; 3122 3123 port@1 { 3124 reg = <1>; 3125 mdss_dsi1_out: endpoint { 3126 }; 3127 }; 3128 }; 3129 }; 3130 3131 mdss_dsi1_phy: phy@ae96400 { 3132 compatible = "qcom,sm8350-dsi-phy-5nm"; 3133 reg = <0 0x0ae96400 0 0x200>, 3134 <0 0x0ae96600 0 0x280>, 3135 <0 0x0ae96900 0 0x27c>; 3136 reg-names = "dsi_phy", 3137 "dsi_phy_lane", 3138 "dsi_pll"; 3139 3140 #clock-cells = <1>; 3141 #phy-cells = <0>; 3142 3143 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3144 <&rpmhcc RPMH_CXO_CLK>; 3145 clock-names = "iface", "ref"; 3146 3147 status = "disabled"; 3148 }; 3149 }; 3150 3151 dispcc: clock-controller@af00000 { 3152 compatible = "qcom,sm8350-dispcc"; 3153 reg = <0 0x0af00000 0 0x10000>; 3154 clocks = <&rpmhcc RPMH_CXO_CLK>, 3155 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 3156 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 3157 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 3158 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 3159 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3160 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3161 clock-names = "bi_tcxo", 3162 "dsi0_phy_pll_out_byteclk", 3163 "dsi0_phy_pll_out_dsiclk", 3164 "dsi1_phy_pll_out_byteclk", 3165 "dsi1_phy_pll_out_dsiclk", 3166 "dp_phy_pll_link_clk", 3167 "dp_phy_pll_vco_div_clk"; 3168 #clock-cells = <1>; 3169 #reset-cells = <1>; 3170 #power-domain-cells = <1>; 3171 3172 power-domains = <&rpmhpd RPMHPD_MMCX>; 3173 }; 3174 3175 pdc: interrupt-controller@b220000 { 3176 compatible = "qcom,sm8350-pdc", "qcom,pdc"; 3177 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 3178 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, 3179 <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, 3180 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, 3181 <156 716 12>; 3182 #interrupt-cells = <2>; 3183 interrupt-parent = <&intc>; 3184 interrupt-controller; 3185 }; 3186 3187 tsens0: thermal-sensor@c263000 { 3188 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 3189 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3190 <0 0x0c222000 0 0x8>; /* SROT */ 3191 #qcom,sensors = <15>; 3192 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 3193 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 3194 interrupt-names = "uplow", "critical"; 3195 #thermal-sensor-cells = <1>; 3196 }; 3197 3198 tsens1: thermal-sensor@c265000 { 3199 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 3200 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3201 <0 0x0c223000 0 0x8>; /* SROT */ 3202 #qcom,sensors = <14>; 3203 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 3204 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 3205 interrupt-names = "uplow", "critical"; 3206 #thermal-sensor-cells = <1>; 3207 }; 3208 3209 aoss_qmp: power-management@c300000 { 3210 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; 3211 reg = <0 0x0c300000 0 0x400>; 3212 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 3213 IRQ_TYPE_EDGE_RISING>; 3214 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3215 3216 #clock-cells = <0>; 3217 }; 3218 3219 sram@c3f0000 { 3220 compatible = "qcom,rpmh-stats"; 3221 reg = <0 0x0c3f0000 0 0x400>; 3222 }; 3223 3224 spmi_bus: spmi@c440000 { 3225 compatible = "qcom,spmi-pmic-arb"; 3226 reg = <0x0 0x0c440000 0x0 0x1100>, 3227 <0x0 0x0c600000 0x0 0x2000000>, 3228 <0x0 0x0e600000 0x0 0x100000>, 3229 <0x0 0x0e700000 0x0 0xa0000>, 3230 <0x0 0x0c40a000 0x0 0x26000>; 3231 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3232 interrupt-names = "periph_irq"; 3233 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3234 qcom,ee = <0>; 3235 qcom,channel = <0>; 3236 #address-cells = <2>; 3237 #size-cells = <0>; 3238 interrupt-controller; 3239 #interrupt-cells = <4>; 3240 }; 3241 3242 tlmm: pinctrl@f100000 { 3243 compatible = "qcom,sm8350-tlmm"; 3244 reg = <0 0x0f100000 0 0x300000>; 3245 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3246 gpio-controller; 3247 #gpio-cells = <2>; 3248 interrupt-controller; 3249 #interrupt-cells = <2>; 3250 gpio-ranges = <&tlmm 0 0 204>; 3251 wakeup-parent = <&pdc>; 3252 3253 sdc2_default_state: sdc2-default-state { 3254 clk-pins { 3255 pins = "sdc2_clk"; 3256 drive-strength = <16>; 3257 bias-disable; 3258 }; 3259 3260 cmd-pins { 3261 pins = "sdc2_cmd"; 3262 drive-strength = <16>; 3263 bias-pull-up; 3264 }; 3265 3266 data-pins { 3267 pins = "sdc2_data"; 3268 drive-strength = <16>; 3269 bias-pull-up; 3270 }; 3271 }; 3272 3273 sdc2_sleep_state: sdc2-sleep-state { 3274 clk-pins { 3275 pins = "sdc2_clk"; 3276 drive-strength = <2>; 3277 bias-disable; 3278 }; 3279 3280 cmd-pins { 3281 pins = "sdc2_cmd"; 3282 drive-strength = <2>; 3283 bias-pull-up; 3284 }; 3285 3286 data-pins { 3287 pins = "sdc2_data"; 3288 drive-strength = <2>; 3289 bias-pull-up; 3290 }; 3291 }; 3292 3293 qup_uart3_default_state: qup-uart3-default-state { 3294 rx-pins { 3295 pins = "gpio18"; 3296 function = "qup3"; 3297 }; 3298 tx-pins { 3299 pins = "gpio19"; 3300 function = "qup3"; 3301 }; 3302 }; 3303 3304 qup_uart6_default: qup-uart6-default-state { 3305 pins = "gpio30", "gpio31"; 3306 function = "qup6"; 3307 drive-strength = <2>; 3308 bias-disable; 3309 }; 3310 3311 qup_uart18_default: qup-uart18-default-state { 3312 pins = "gpio68", "gpio69"; 3313 function = "qup18"; 3314 drive-strength = <2>; 3315 bias-disable; 3316 }; 3317 3318 qup_i2c0_default: qup-i2c0-default-state { 3319 pins = "gpio4", "gpio5"; 3320 function = "qup0"; 3321 drive-strength = <2>; 3322 bias-pull-up; 3323 }; 3324 3325 qup_i2c1_default: qup-i2c1-default-state { 3326 pins = "gpio8", "gpio9"; 3327 function = "qup1"; 3328 drive-strength = <2>; 3329 bias-pull-up; 3330 }; 3331 3332 qup_i2c2_default: qup-i2c2-default-state { 3333 pins = "gpio12", "gpio13"; 3334 function = "qup2"; 3335 drive-strength = <2>; 3336 bias-pull-up; 3337 }; 3338 3339 qup_i2c4_default: qup-i2c4-default-state { 3340 pins = "gpio20", "gpio21"; 3341 function = "qup4"; 3342 drive-strength = <2>; 3343 bias-pull-up; 3344 }; 3345 3346 qup_i2c5_default: qup-i2c5-default-state { 3347 pins = "gpio24", "gpio25"; 3348 function = "qup5"; 3349 drive-strength = <2>; 3350 bias-pull-up; 3351 }; 3352 3353 qup_i2c6_default: qup-i2c6-default-state { 3354 pins = "gpio28", "gpio29"; 3355 function = "qup6"; 3356 drive-strength = <2>; 3357 bias-pull-up; 3358 }; 3359 3360 qup_i2c7_default: qup-i2c7-default-state { 3361 pins = "gpio32", "gpio33"; 3362 function = "qup7"; 3363 drive-strength = <2>; 3364 bias-disable; 3365 }; 3366 3367 qup_i2c8_default: qup-i2c8-default-state { 3368 pins = "gpio36", "gpio37"; 3369 function = "qup8"; 3370 drive-strength = <2>; 3371 bias-pull-up; 3372 }; 3373 3374 qup_i2c9_default: qup-i2c9-default-state { 3375 pins = "gpio40", "gpio41"; 3376 function = "qup9"; 3377 drive-strength = <2>; 3378 bias-pull-up; 3379 }; 3380 3381 qup_i2c10_default: qup-i2c10-default-state { 3382 pins = "gpio44", "gpio45"; 3383 function = "qup10"; 3384 drive-strength = <2>; 3385 bias-pull-up; 3386 }; 3387 3388 qup_i2c11_default: qup-i2c11-default-state { 3389 pins = "gpio48", "gpio49"; 3390 function = "qup11"; 3391 drive-strength = <2>; 3392 bias-pull-up; 3393 }; 3394 3395 qup_i2c12_default: qup-i2c12-default-state { 3396 pins = "gpio52", "gpio53"; 3397 function = "qup12"; 3398 drive-strength = <2>; 3399 bias-pull-up; 3400 }; 3401 3402 qup_i2c13_default: qup-i2c13-default-state { 3403 pins = "gpio0", "gpio1"; 3404 function = "qup13"; 3405 drive-strength = <2>; 3406 bias-pull-up; 3407 }; 3408 3409 qup_i2c14_default: qup-i2c14-default-state { 3410 pins = "gpio56", "gpio57"; 3411 function = "qup14"; 3412 drive-strength = <2>; 3413 bias-disable; 3414 }; 3415 3416 qup_i2c15_default: qup-i2c15-default-state { 3417 pins = "gpio60", "gpio61"; 3418 function = "qup15"; 3419 drive-strength = <2>; 3420 bias-disable; 3421 }; 3422 3423 qup_i2c16_default: qup-i2c16-default-state { 3424 pins = "gpio64", "gpio65"; 3425 function = "qup16"; 3426 drive-strength = <2>; 3427 bias-disable; 3428 }; 3429 3430 qup_i2c17_default: qup-i2c17-default-state { 3431 pins = "gpio72", "gpio73"; 3432 function = "qup17"; 3433 drive-strength = <2>; 3434 bias-disable; 3435 }; 3436 3437 qup_i2c19_default: qup-i2c19-default-state { 3438 pins = "gpio76", "gpio77"; 3439 function = "qup19"; 3440 drive-strength = <2>; 3441 bias-disable; 3442 }; 3443 }; 3444 3445 sram@14680000 { 3446 compatible = "qcom,sm8350-imem", "syscon", "simple-mfd"; 3447 reg = <0 0x14680000 0 0x40000>; 3448 3449 #address-cells = <1>; 3450 #size-cells = <1>; 3451 3452 ranges = <0 0 0x14680000 0x40000>; 3453 3454 ipa_modem_tables: modem-tables@3d000 { 3455 reg = <0x3d000 0x2000>; 3456 }; 3457 }; 3458 3459 apps_smmu: iommu@15000000 { 3460 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; 3461 reg = <0 0x15000000 0 0x100000>; 3462 #iommu-cells = <2>; 3463 #global-interrupts = <2>; 3464 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 3465 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3466 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3467 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3468 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3469 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3470 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3471 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3472 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3473 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3474 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3475 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3476 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3477 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3478 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3479 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3480 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3481 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3482 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3483 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3484 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3485 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3486 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3487 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3488 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3489 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3490 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3491 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3492 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3493 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3494 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3495 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3496 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3497 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3498 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3499 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3500 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3501 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3502 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3503 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3504 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3505 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3506 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3507 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3508 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3509 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3510 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3511 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3512 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3513 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3514 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3515 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3516 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3517 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3518 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3519 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3520 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3521 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3522 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3523 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3524 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3525 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3526 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3527 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3528 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3529 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3530 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3531 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3532 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3533 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3534 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3535 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3536 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3537 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3538 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3539 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3540 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3541 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3542 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3543 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3544 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3545 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3546 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3547 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3548 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3549 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3550 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3551 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3552 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3553 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3554 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3555 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3556 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3557 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3558 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3559 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3560 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 3561 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 3562 dma-coherent; 3563 }; 3564 3565 intc: interrupt-controller@17a00000 { 3566 compatible = "arm,gic-v3"; 3567 #address-cells = <0>; 3568 #interrupt-cells = <3>; 3569 interrupt-controller; 3570 #redistributor-regions = <1>; 3571 redistributor-stride = <0 0x20000>; 3572 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3573 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3574 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3575 }; 3576 3577 timer@17c20000 { 3578 compatible = "arm,armv7-timer-mem"; 3579 #address-cells = <1>; 3580 #size-cells = <1>; 3581 ranges = <0 0 0 0x20000000>; 3582 reg = <0x0 0x17c20000 0x0 0x1000>; 3583 clock-frequency = <19200000>; 3584 3585 frame@17c21000 { 3586 frame-number = <0>; 3587 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3588 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3589 reg = <0x17c21000 0x1000>, 3590 <0x17c22000 0x1000>; 3591 }; 3592 3593 frame@17c23000 { 3594 frame-number = <1>; 3595 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3596 reg = <0x17c23000 0x1000>; 3597 status = "disabled"; 3598 }; 3599 3600 frame@17c25000 { 3601 frame-number = <2>; 3602 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3603 reg = <0x17c25000 0x1000>; 3604 status = "disabled"; 3605 }; 3606 3607 frame@17c27000 { 3608 frame-number = <3>; 3609 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3610 reg = <0x17c27000 0x1000>; 3611 status = "disabled"; 3612 }; 3613 3614 frame@17c29000 { 3615 frame-number = <4>; 3616 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3617 reg = <0x17c29000 0x1000>; 3618 status = "disabled"; 3619 }; 3620 3621 frame@17c2b000 { 3622 frame-number = <5>; 3623 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3624 reg = <0x17c2b000 0x1000>; 3625 status = "disabled"; 3626 }; 3627 3628 frame@17c2d000 { 3629 frame-number = <6>; 3630 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3631 reg = <0x17c2d000 0x1000>; 3632 status = "disabled"; 3633 }; 3634 }; 3635 3636 apps_rsc: rsc@18200000 { 3637 label = "apps_rsc"; 3638 compatible = "qcom,rpmh-rsc"; 3639 reg = <0x0 0x18200000 0x0 0x10000>, 3640 <0x0 0x18210000 0x0 0x10000>, 3641 <0x0 0x18220000 0x0 0x10000>; 3642 reg-names = "drv-0", "drv-1", "drv-2"; 3643 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3644 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3645 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3646 qcom,tcs-offset = <0xd00>; 3647 qcom,drv-id = <2>; 3648 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 3649 <WAKE_TCS 3>, <CONTROL_TCS 0>; 3650 power-domains = <&cluster_pd>; 3651 3652 rpmhcc: clock-controller { 3653 compatible = "qcom,sm8350-rpmh-clk"; 3654 #clock-cells = <1>; 3655 clock-names = "xo"; 3656 clocks = <&xo_board>; 3657 }; 3658 3659 rpmhpd: power-controller { 3660 compatible = "qcom,sm8350-rpmhpd"; 3661 #power-domain-cells = <1>; 3662 operating-points-v2 = <&rpmhpd_opp_table>; 3663 3664 rpmhpd_opp_table: opp-table { 3665 compatible = "operating-points-v2"; 3666 3667 rpmhpd_opp_ret: opp1 { 3668 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3669 }; 3670 3671 rpmhpd_opp_min_svs: opp2 { 3672 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3673 }; 3674 3675 rpmhpd_opp_low_svs: opp3 { 3676 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3677 }; 3678 3679 rpmhpd_opp_svs: opp4 { 3680 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3681 }; 3682 3683 rpmhpd_opp_svs_l1: opp5 { 3684 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3685 }; 3686 3687 rpmhpd_opp_nom: opp6 { 3688 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3689 }; 3690 3691 rpmhpd_opp_nom_l1: opp7 { 3692 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3693 }; 3694 3695 rpmhpd_opp_nom_l2: opp8 { 3696 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3697 }; 3698 3699 rpmhpd_opp_turbo: opp9 { 3700 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3701 }; 3702 3703 rpmhpd_opp_turbo_l1: opp10 { 3704 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3705 }; 3706 }; 3707 }; 3708 3709 apps_bcm_voter: bcm-voter { 3710 compatible = "qcom,bcm-voter"; 3711 }; 3712 }; 3713 3714 cpufreq_hw: cpufreq@18591000 { 3715 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss"; 3716 reg = <0 0x18591000 0 0x1000>, 3717 <0 0x18592000 0 0x1000>, 3718 <0 0x18593000 0 0x1000>; 3719 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3720 3721 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 3722 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3723 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 3724 interrupt-names = "dcvsh-irq-0", 3725 "dcvsh-irq-1", 3726 "dcvsh-irq-2"; 3727 3728 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3729 clock-names = "xo", "alternate"; 3730 3731 #freq-domain-cells = <1>; 3732 #clock-cells = <1>; 3733 }; 3734 }; 3735 3736 thermal_zones: thermal-zones { 3737 cpu0-thermal { 3738 polling-delay-passive = <250>; 3739 3740 thermal-sensors = <&tsens0 1>; 3741 3742 trips { 3743 cpu0_alert0: trip-point0 { 3744 temperature = <90000>; 3745 hysteresis = <2000>; 3746 type = "passive"; 3747 }; 3748 3749 cpu0_alert1: trip-point1 { 3750 temperature = <95000>; 3751 hysteresis = <2000>; 3752 type = "passive"; 3753 }; 3754 3755 cpu0_crit: cpu-crit { 3756 temperature = <110000>; 3757 hysteresis = <1000>; 3758 type = "critical"; 3759 }; 3760 }; 3761 3762 cooling-maps { 3763 map0 { 3764 trip = <&cpu0_alert0>; 3765 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3766 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3767 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3768 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3769 }; 3770 map1 { 3771 trip = <&cpu0_alert1>; 3772 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3773 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3774 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3775 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3776 }; 3777 }; 3778 }; 3779 3780 cpu1-thermal { 3781 polling-delay-passive = <250>; 3782 3783 thermal-sensors = <&tsens0 2>; 3784 3785 trips { 3786 cpu1_alert0: trip-point0 { 3787 temperature = <90000>; 3788 hysteresis = <2000>; 3789 type = "passive"; 3790 }; 3791 3792 cpu1_alert1: trip-point1 { 3793 temperature = <95000>; 3794 hysteresis = <2000>; 3795 type = "passive"; 3796 }; 3797 3798 cpu1_crit: cpu-crit { 3799 temperature = <110000>; 3800 hysteresis = <1000>; 3801 type = "critical"; 3802 }; 3803 }; 3804 3805 cooling-maps { 3806 map0 { 3807 trip = <&cpu1_alert0>; 3808 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3809 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3810 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3811 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3812 }; 3813 map1 { 3814 trip = <&cpu1_alert1>; 3815 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3816 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3817 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3818 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3819 }; 3820 }; 3821 }; 3822 3823 cpu2-thermal { 3824 polling-delay-passive = <250>; 3825 3826 thermal-sensors = <&tsens0 3>; 3827 3828 trips { 3829 cpu2_alert0: trip-point0 { 3830 temperature = <90000>; 3831 hysteresis = <2000>; 3832 type = "passive"; 3833 }; 3834 3835 cpu2_alert1: trip-point1 { 3836 temperature = <95000>; 3837 hysteresis = <2000>; 3838 type = "passive"; 3839 }; 3840 3841 cpu2_crit: cpu-crit { 3842 temperature = <110000>; 3843 hysteresis = <1000>; 3844 type = "critical"; 3845 }; 3846 }; 3847 3848 cooling-maps { 3849 map0 { 3850 trip = <&cpu2_alert0>; 3851 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3852 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3853 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3854 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3855 }; 3856 map1 { 3857 trip = <&cpu2_alert1>; 3858 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3859 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3860 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3861 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3862 }; 3863 }; 3864 }; 3865 3866 cpu3-thermal { 3867 polling-delay-passive = <250>; 3868 3869 thermal-sensors = <&tsens0 4>; 3870 3871 trips { 3872 cpu3_alert0: trip-point0 { 3873 temperature = <90000>; 3874 hysteresis = <2000>; 3875 type = "passive"; 3876 }; 3877 3878 cpu3_alert1: trip-point1 { 3879 temperature = <95000>; 3880 hysteresis = <2000>; 3881 type = "passive"; 3882 }; 3883 3884 cpu3_crit: cpu-crit { 3885 temperature = <110000>; 3886 hysteresis = <1000>; 3887 type = "critical"; 3888 }; 3889 }; 3890 3891 cooling-maps { 3892 map0 { 3893 trip = <&cpu3_alert0>; 3894 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3895 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3896 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3897 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3898 }; 3899 map1 { 3900 trip = <&cpu3_alert1>; 3901 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3902 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3903 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3904 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3905 }; 3906 }; 3907 }; 3908 3909 cpu4-top-thermal { 3910 polling-delay-passive = <250>; 3911 3912 thermal-sensors = <&tsens0 7>; 3913 3914 trips { 3915 cpu4_top_alert0: trip-point0 { 3916 temperature = <90000>; 3917 hysteresis = <2000>; 3918 type = "passive"; 3919 }; 3920 3921 cpu4_top_alert1: trip-point1 { 3922 temperature = <95000>; 3923 hysteresis = <2000>; 3924 type = "passive"; 3925 }; 3926 3927 cpu4_top_crit: cpu-crit { 3928 temperature = <110000>; 3929 hysteresis = <1000>; 3930 type = "critical"; 3931 }; 3932 }; 3933 3934 cooling-maps { 3935 map0 { 3936 trip = <&cpu4_top_alert0>; 3937 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3938 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3939 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3940 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3941 }; 3942 map1 { 3943 trip = <&cpu4_top_alert1>; 3944 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3945 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3946 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3947 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3948 }; 3949 }; 3950 }; 3951 3952 cpu5-top-thermal { 3953 polling-delay-passive = <250>; 3954 3955 thermal-sensors = <&tsens0 8>; 3956 3957 trips { 3958 cpu5_top_alert0: trip-point0 { 3959 temperature = <90000>; 3960 hysteresis = <2000>; 3961 type = "passive"; 3962 }; 3963 3964 cpu5_top_alert1: trip-point1 { 3965 temperature = <95000>; 3966 hysteresis = <2000>; 3967 type = "passive"; 3968 }; 3969 3970 cpu5_top_crit: cpu-crit { 3971 temperature = <110000>; 3972 hysteresis = <1000>; 3973 type = "critical"; 3974 }; 3975 }; 3976 3977 cooling-maps { 3978 map0 { 3979 trip = <&cpu5_top_alert0>; 3980 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3981 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3982 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3983 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3984 }; 3985 map1 { 3986 trip = <&cpu5_top_alert1>; 3987 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3988 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3989 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3990 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3991 }; 3992 }; 3993 }; 3994 3995 cpu6-top-thermal { 3996 polling-delay-passive = <250>; 3997 3998 thermal-sensors = <&tsens0 9>; 3999 4000 trips { 4001 cpu6_top_alert0: trip-point0 { 4002 temperature = <90000>; 4003 hysteresis = <2000>; 4004 type = "passive"; 4005 }; 4006 4007 cpu6_top_alert1: trip-point1 { 4008 temperature = <95000>; 4009 hysteresis = <2000>; 4010 type = "passive"; 4011 }; 4012 4013 cpu6_top_crit: cpu-crit { 4014 temperature = <110000>; 4015 hysteresis = <1000>; 4016 type = "critical"; 4017 }; 4018 }; 4019 4020 cooling-maps { 4021 map0 { 4022 trip = <&cpu6_top_alert0>; 4023 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4024 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4025 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4026 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4027 }; 4028 map1 { 4029 trip = <&cpu6_top_alert1>; 4030 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4031 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4032 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4033 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4034 }; 4035 }; 4036 }; 4037 4038 cpu7-top-thermal { 4039 polling-delay-passive = <250>; 4040 4041 thermal-sensors = <&tsens0 10>; 4042 4043 trips { 4044 cpu7_top_alert0: trip-point0 { 4045 temperature = <90000>; 4046 hysteresis = <2000>; 4047 type = "passive"; 4048 }; 4049 4050 cpu7_top_alert1: trip-point1 { 4051 temperature = <95000>; 4052 hysteresis = <2000>; 4053 type = "passive"; 4054 }; 4055 4056 cpu7_top_crit: cpu-crit { 4057 temperature = <110000>; 4058 hysteresis = <1000>; 4059 type = "critical"; 4060 }; 4061 }; 4062 4063 cooling-maps { 4064 map0 { 4065 trip = <&cpu7_top_alert0>; 4066 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4067 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4068 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4069 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4070 }; 4071 map1 { 4072 trip = <&cpu7_top_alert1>; 4073 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4074 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4075 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4076 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4077 }; 4078 }; 4079 }; 4080 4081 cpu4-bottom-thermal { 4082 polling-delay-passive = <250>; 4083 4084 thermal-sensors = <&tsens0 11>; 4085 4086 trips { 4087 cpu4_bottom_alert0: trip-point0 { 4088 temperature = <90000>; 4089 hysteresis = <2000>; 4090 type = "passive"; 4091 }; 4092 4093 cpu4_bottom_alert1: trip-point1 { 4094 temperature = <95000>; 4095 hysteresis = <2000>; 4096 type = "passive"; 4097 }; 4098 4099 cpu4_bottom_crit: cpu-crit { 4100 temperature = <110000>; 4101 hysteresis = <1000>; 4102 type = "critical"; 4103 }; 4104 }; 4105 4106 cooling-maps { 4107 map0 { 4108 trip = <&cpu4_bottom_alert0>; 4109 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4110 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4111 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4112 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4113 }; 4114 map1 { 4115 trip = <&cpu4_bottom_alert1>; 4116 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4117 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4118 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4119 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4120 }; 4121 }; 4122 }; 4123 4124 cpu5-bottom-thermal { 4125 polling-delay-passive = <250>; 4126 4127 thermal-sensors = <&tsens0 12>; 4128 4129 trips { 4130 cpu5_bottom_alert0: trip-point0 { 4131 temperature = <90000>; 4132 hysteresis = <2000>; 4133 type = "passive"; 4134 }; 4135 4136 cpu5_bottom_alert1: trip-point1 { 4137 temperature = <95000>; 4138 hysteresis = <2000>; 4139 type = "passive"; 4140 }; 4141 4142 cpu5_bottom_crit: cpu-crit { 4143 temperature = <110000>; 4144 hysteresis = <1000>; 4145 type = "critical"; 4146 }; 4147 }; 4148 4149 cooling-maps { 4150 map0 { 4151 trip = <&cpu5_bottom_alert0>; 4152 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4153 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4154 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4155 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4156 }; 4157 map1 { 4158 trip = <&cpu5_bottom_alert1>; 4159 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4160 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4161 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4162 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4163 }; 4164 }; 4165 }; 4166 4167 cpu6-bottom-thermal { 4168 polling-delay-passive = <250>; 4169 4170 thermal-sensors = <&tsens0 13>; 4171 4172 trips { 4173 cpu6_bottom_alert0: trip-point0 { 4174 temperature = <90000>; 4175 hysteresis = <2000>; 4176 type = "passive"; 4177 }; 4178 4179 cpu6_bottom_alert1: trip-point1 { 4180 temperature = <95000>; 4181 hysteresis = <2000>; 4182 type = "passive"; 4183 }; 4184 4185 cpu6_bottom_crit: cpu-crit { 4186 temperature = <110000>; 4187 hysteresis = <1000>; 4188 type = "critical"; 4189 }; 4190 }; 4191 4192 cooling-maps { 4193 map0 { 4194 trip = <&cpu6_bottom_alert0>; 4195 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4196 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4197 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4198 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4199 }; 4200 map1 { 4201 trip = <&cpu6_bottom_alert1>; 4202 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4203 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4204 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4205 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4206 }; 4207 }; 4208 }; 4209 4210 cpu7-bottom-thermal { 4211 polling-delay-passive = <250>; 4212 4213 thermal-sensors = <&tsens0 14>; 4214 4215 trips { 4216 cpu7_bottom_alert0: trip-point0 { 4217 temperature = <90000>; 4218 hysteresis = <2000>; 4219 type = "passive"; 4220 }; 4221 4222 cpu7_bottom_alert1: trip-point1 { 4223 temperature = <95000>; 4224 hysteresis = <2000>; 4225 type = "passive"; 4226 }; 4227 4228 cpu7_bottom_crit: cpu-crit { 4229 temperature = <110000>; 4230 hysteresis = <1000>; 4231 type = "critical"; 4232 }; 4233 }; 4234 4235 cooling-maps { 4236 map0 { 4237 trip = <&cpu7_bottom_alert0>; 4238 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4239 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4240 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4241 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4242 }; 4243 map1 { 4244 trip = <&cpu7_bottom_alert1>; 4245 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4246 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4247 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4248 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4249 }; 4250 }; 4251 }; 4252 4253 aoss0-thermal { 4254 polling-delay-passive = <250>; 4255 4256 thermal-sensors = <&tsens0 0>; 4257 4258 trips { 4259 aoss0_alert0: trip-point0 { 4260 temperature = <90000>; 4261 hysteresis = <2000>; 4262 type = "hot"; 4263 }; 4264 }; 4265 }; 4266 4267 cluster0-thermal { 4268 polling-delay-passive = <250>; 4269 4270 thermal-sensors = <&tsens0 5>; 4271 4272 trips { 4273 cluster0_alert0: trip-point0 { 4274 temperature = <90000>; 4275 hysteresis = <2000>; 4276 type = "hot"; 4277 }; 4278 cluster0_crit: cluster0-crit { 4279 temperature = <110000>; 4280 hysteresis = <2000>; 4281 type = "critical"; 4282 }; 4283 }; 4284 }; 4285 4286 cluster1-thermal { 4287 polling-delay-passive = <250>; 4288 4289 thermal-sensors = <&tsens0 6>; 4290 4291 trips { 4292 cluster1_alert0: trip-point0 { 4293 temperature = <90000>; 4294 hysteresis = <2000>; 4295 type = "hot"; 4296 }; 4297 cluster1_crit: cluster1-crit { 4298 temperature = <110000>; 4299 hysteresis = <2000>; 4300 type = "critical"; 4301 }; 4302 }; 4303 }; 4304 4305 aoss1-thermal { 4306 polling-delay-passive = <250>; 4307 4308 thermal-sensors = <&tsens1 0>; 4309 4310 trips { 4311 aoss1_alert0: trip-point0 { 4312 temperature = <90000>; 4313 hysteresis = <2000>; 4314 type = "hot"; 4315 }; 4316 }; 4317 }; 4318 4319 gpu-top-thermal { 4320 polling-delay-passive = <250>; 4321 4322 thermal-sensors = <&tsens1 1>; 4323 4324 cooling-maps { 4325 map0 { 4326 trip = <&gpu_top_alert0>; 4327 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4328 }; 4329 }; 4330 4331 trips { 4332 gpu_top_alert0: trip-point0 { 4333 temperature = <85000>; 4334 hysteresis = <1000>; 4335 type = "passive"; 4336 }; 4337 4338 trip-point1 { 4339 temperature = <90000>; 4340 hysteresis = <1000>; 4341 type = "hot"; 4342 }; 4343 4344 trip-point2 { 4345 temperature = <110000>; 4346 hysteresis = <1000>; 4347 type = "critical"; 4348 }; 4349 }; 4350 }; 4351 4352 gpu-bottom-thermal { 4353 polling-delay-passive = <250>; 4354 4355 thermal-sensors = <&tsens1 2>; 4356 4357 cooling-maps { 4358 map0 { 4359 trip = <&gpu_bottom_alert0>; 4360 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4361 }; 4362 }; 4363 4364 trips { 4365 gpu_bottom_alert0: trip-point0 { 4366 temperature = <85000>; 4367 hysteresis = <1000>; 4368 type = "passive"; 4369 }; 4370 4371 trip-point1 { 4372 temperature = <90000>; 4373 hysteresis = <1000>; 4374 type = "hot"; 4375 }; 4376 4377 trip-point2 { 4378 temperature = <110000>; 4379 hysteresis = <1000>; 4380 type = "critical"; 4381 }; 4382 }; 4383 }; 4384 4385 nspss1-thermal { 4386 polling-delay-passive = <250>; 4387 4388 thermal-sensors = <&tsens1 3>; 4389 4390 trips { 4391 nspss1_alert0: trip-point0 { 4392 temperature = <90000>; 4393 hysteresis = <1000>; 4394 type = "hot"; 4395 }; 4396 }; 4397 }; 4398 4399 nspss2-thermal { 4400 polling-delay-passive = <250>; 4401 4402 thermal-sensors = <&tsens1 4>; 4403 4404 trips { 4405 nspss2_alert0: trip-point0 { 4406 temperature = <90000>; 4407 hysteresis = <1000>; 4408 type = "hot"; 4409 }; 4410 }; 4411 }; 4412 4413 nspss3-thermal { 4414 polling-delay-passive = <250>; 4415 4416 thermal-sensors = <&tsens1 5>; 4417 4418 trips { 4419 nspss3_alert0: trip-point0 { 4420 temperature = <90000>; 4421 hysteresis = <1000>; 4422 type = "hot"; 4423 }; 4424 }; 4425 }; 4426 4427 video-thermal { 4428 polling-delay-passive = <250>; 4429 4430 thermal-sensors = <&tsens1 6>; 4431 4432 trips { 4433 video_alert0: trip-point0 { 4434 temperature = <90000>; 4435 hysteresis = <2000>; 4436 type = "hot"; 4437 }; 4438 }; 4439 }; 4440 4441 mem-thermal { 4442 polling-delay-passive = <250>; 4443 4444 thermal-sensors = <&tsens1 7>; 4445 4446 trips { 4447 mem_alert0: trip-point0 { 4448 temperature = <90000>; 4449 hysteresis = <2000>; 4450 type = "hot"; 4451 }; 4452 }; 4453 }; 4454 4455 modem1-top-thermal { 4456 polling-delay-passive = <250>; 4457 4458 thermal-sensors = <&tsens1 8>; 4459 4460 trips { 4461 modem1_alert0: trip-point0 { 4462 temperature = <90000>; 4463 hysteresis = <2000>; 4464 type = "hot"; 4465 }; 4466 }; 4467 }; 4468 4469 modem2-top-thermal { 4470 polling-delay-passive = <250>; 4471 4472 thermal-sensors = <&tsens1 9>; 4473 4474 trips { 4475 modem2_alert0: trip-point0 { 4476 temperature = <90000>; 4477 hysteresis = <2000>; 4478 type = "hot"; 4479 }; 4480 }; 4481 }; 4482 4483 modem3-top-thermal { 4484 polling-delay-passive = <250>; 4485 4486 thermal-sensors = <&tsens1 10>; 4487 4488 trips { 4489 modem3_alert0: trip-point0 { 4490 temperature = <90000>; 4491 hysteresis = <2000>; 4492 type = "hot"; 4493 }; 4494 }; 4495 }; 4496 4497 modem4-top-thermal { 4498 polling-delay-passive = <250>; 4499 4500 thermal-sensors = <&tsens1 11>; 4501 4502 trips { 4503 modem4_alert0: trip-point0 { 4504 temperature = <90000>; 4505 hysteresis = <2000>; 4506 type = "hot"; 4507 }; 4508 }; 4509 }; 4510 4511 camera-top-thermal { 4512 polling-delay-passive = <250>; 4513 4514 thermal-sensors = <&tsens1 12>; 4515 4516 trips { 4517 camera1_alert0: trip-point0 { 4518 temperature = <90000>; 4519 hysteresis = <2000>; 4520 type = "hot"; 4521 }; 4522 }; 4523 }; 4524 4525 cam-bottom-thermal { 4526 polling-delay-passive = <250>; 4527 4528 thermal-sensors = <&tsens1 13>; 4529 4530 trips { 4531 camera2_alert0: trip-point0 { 4532 temperature = <90000>; 4533 hysteresis = <2000>; 4534 type = "hot"; 4535 }; 4536 }; 4537 }; 4538 }; 4539 4540 timer { 4541 compatible = "arm,armv8-timer"; 4542 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 4543 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 4544 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 4545 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 4546 }; 4547}; 4548