1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Linaro Limited 4 */ 5 6#include <dt-bindings/interconnect/qcom,sm8350.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/qcom,dispcc-sm8350.h> 9#include <dt-bindings/clock/qcom,gcc-sm8350.h> 10#include <dt-bindings/clock/qcom,gpucc-sm8350.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/firmware/qcom,scm.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interconnect/qcom,sm8350.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/phy/phy-qcom-qmp.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/power/qcom,rpmhpd.h> 20#include <dt-bindings/soc/qcom,apr.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/sound/qcom,q6afe.h> 23#include <dt-bindings/thermal/thermal.h> 24#include <dt-bindings/interconnect/qcom,sm8350.h> 25 26/ { 27 interrupt-parent = <&intc>; 28 29 #address-cells = <2>; 30 #size-cells = <2>; 31 32 chosen { }; 33 34 clocks { 35 xo_board: xo-board { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <38400000>; 39 clock-output-names = "xo_board"; 40 }; 41 42 sleep_clk: sleep-clk { 43 compatible = "fixed-clock"; 44 clock-frequency = <32000>; 45 #clock-cells = <0>; 46 }; 47 }; 48 49 cpus { 50 #address-cells = <2>; 51 #size-cells = <0>; 52 53 CPU0: cpu@0 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a55"; 56 reg = <0x0 0x0>; 57 clocks = <&cpufreq_hw 0>; 58 enable-method = "psci"; 59 next-level-cache = <&L2_0>; 60 qcom,freq-domain = <&cpufreq_hw 0>; 61 power-domains = <&CPU_PD0>; 62 power-domain-names = "psci"; 63 #cooling-cells = <2>; 64 L2_0: l2-cache { 65 compatible = "cache"; 66 cache-level = <2>; 67 cache-unified; 68 next-level-cache = <&L3_0>; 69 L3_0: l3-cache { 70 compatible = "cache"; 71 cache-level = <3>; 72 cache-unified; 73 }; 74 }; 75 }; 76 77 CPU1: cpu@100 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a55"; 80 reg = <0x0 0x100>; 81 clocks = <&cpufreq_hw 0>; 82 enable-method = "psci"; 83 next-level-cache = <&L2_100>; 84 qcom,freq-domain = <&cpufreq_hw 0>; 85 power-domains = <&CPU_PD1>; 86 power-domain-names = "psci"; 87 #cooling-cells = <2>; 88 L2_100: l2-cache { 89 compatible = "cache"; 90 cache-level = <2>; 91 cache-unified; 92 next-level-cache = <&L3_0>; 93 }; 94 }; 95 96 CPU2: cpu@200 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a55"; 99 reg = <0x0 0x200>; 100 clocks = <&cpufreq_hw 0>; 101 enable-method = "psci"; 102 next-level-cache = <&L2_200>; 103 qcom,freq-domain = <&cpufreq_hw 0>; 104 power-domains = <&CPU_PD2>; 105 power-domain-names = "psci"; 106 #cooling-cells = <2>; 107 L2_200: l2-cache { 108 compatible = "cache"; 109 cache-level = <2>; 110 cache-unified; 111 next-level-cache = <&L3_0>; 112 }; 113 }; 114 115 CPU3: cpu@300 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a55"; 118 reg = <0x0 0x300>; 119 clocks = <&cpufreq_hw 0>; 120 enable-method = "psci"; 121 next-level-cache = <&L2_300>; 122 qcom,freq-domain = <&cpufreq_hw 0>; 123 power-domains = <&CPU_PD3>; 124 power-domain-names = "psci"; 125 #cooling-cells = <2>; 126 L2_300: l2-cache { 127 compatible = "cache"; 128 cache-level = <2>; 129 cache-unified; 130 next-level-cache = <&L3_0>; 131 }; 132 }; 133 134 CPU4: cpu@400 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-a78"; 137 reg = <0x0 0x400>; 138 clocks = <&cpufreq_hw 1>; 139 enable-method = "psci"; 140 next-level-cache = <&L2_400>; 141 qcom,freq-domain = <&cpufreq_hw 1>; 142 power-domains = <&CPU_PD4>; 143 power-domain-names = "psci"; 144 #cooling-cells = <2>; 145 L2_400: l2-cache { 146 compatible = "cache"; 147 cache-level = <2>; 148 cache-unified; 149 next-level-cache = <&L3_0>; 150 }; 151 }; 152 153 CPU5: cpu@500 { 154 device_type = "cpu"; 155 compatible = "arm,cortex-a78"; 156 reg = <0x0 0x500>; 157 clocks = <&cpufreq_hw 1>; 158 enable-method = "psci"; 159 next-level-cache = <&L2_500>; 160 qcom,freq-domain = <&cpufreq_hw 1>; 161 power-domains = <&CPU_PD5>; 162 power-domain-names = "psci"; 163 #cooling-cells = <2>; 164 L2_500: l2-cache { 165 compatible = "cache"; 166 cache-level = <2>; 167 cache-unified; 168 next-level-cache = <&L3_0>; 169 }; 170 }; 171 172 CPU6: cpu@600 { 173 device_type = "cpu"; 174 compatible = "arm,cortex-a78"; 175 reg = <0x0 0x600>; 176 clocks = <&cpufreq_hw 1>; 177 enable-method = "psci"; 178 next-level-cache = <&L2_600>; 179 qcom,freq-domain = <&cpufreq_hw 1>; 180 power-domains = <&CPU_PD6>; 181 power-domain-names = "psci"; 182 #cooling-cells = <2>; 183 L2_600: l2-cache { 184 compatible = "cache"; 185 cache-level = <2>; 186 cache-unified; 187 next-level-cache = <&L3_0>; 188 }; 189 }; 190 191 CPU7: cpu@700 { 192 device_type = "cpu"; 193 compatible = "arm,cortex-x1"; 194 reg = <0x0 0x700>; 195 clocks = <&cpufreq_hw 2>; 196 enable-method = "psci"; 197 next-level-cache = <&L2_700>; 198 qcom,freq-domain = <&cpufreq_hw 2>; 199 power-domains = <&CPU_PD7>; 200 power-domain-names = "psci"; 201 #cooling-cells = <2>; 202 L2_700: l2-cache { 203 compatible = "cache"; 204 cache-level = <2>; 205 cache-unified; 206 next-level-cache = <&L3_0>; 207 }; 208 }; 209 210 cpu-map { 211 cluster0 { 212 core0 { 213 cpu = <&CPU0>; 214 }; 215 216 core1 { 217 cpu = <&CPU1>; 218 }; 219 220 core2 { 221 cpu = <&CPU2>; 222 }; 223 224 core3 { 225 cpu = <&CPU3>; 226 }; 227 228 core4 { 229 cpu = <&CPU4>; 230 }; 231 232 core5 { 233 cpu = <&CPU5>; 234 }; 235 236 core6 { 237 cpu = <&CPU6>; 238 }; 239 240 core7 { 241 cpu = <&CPU7>; 242 }; 243 }; 244 }; 245 246 idle-states { 247 entry-method = "psci"; 248 249 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 250 compatible = "arm,idle-state"; 251 idle-state-name = "silver-rail-power-collapse"; 252 arm,psci-suspend-param = <0x40000004>; 253 entry-latency-us = <360>; 254 exit-latency-us = <531>; 255 min-residency-us = <3934>; 256 local-timer-stop; 257 }; 258 259 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 260 compatible = "arm,idle-state"; 261 idle-state-name = "gold-rail-power-collapse"; 262 arm,psci-suspend-param = <0x40000004>; 263 entry-latency-us = <702>; 264 exit-latency-us = <1061>; 265 min-residency-us = <4488>; 266 local-timer-stop; 267 }; 268 }; 269 270 domain-idle-states { 271 CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { 272 compatible = "domain-idle-state"; 273 arm,psci-suspend-param = <0x41000044>; 274 entry-latency-us = <2752>; 275 exit-latency-us = <3048>; 276 min-residency-us = <6118>; 277 }; 278 279 CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 { 280 compatible = "domain-idle-state"; 281 arm,psci-suspend-param = <0x4100c344>; 282 entry-latency-us = <3263>; 283 exit-latency-us = <6562>; 284 min-residency-us = <9987>; 285 }; 286 }; 287 }; 288 289 firmware { 290 scm: scm { 291 compatible = "qcom,scm-sm8350", "qcom,scm"; 292 qcom,dload-mode = <&tcsr 0x13000>; 293 #reset-cells = <1>; 294 }; 295 }; 296 297 memory@80000000 { 298 device_type = "memory"; 299 /* We expect the bootloader to fill in the size */ 300 reg = <0x0 0x80000000 0x0 0x0>; 301 }; 302 303 pmu { 304 compatible = "arm,armv8-pmuv3"; 305 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 306 }; 307 308 psci { 309 compatible = "arm,psci-1.0"; 310 method = "smc"; 311 312 CPU_PD0: power-domain-cpu0 { 313 #power-domain-cells = <0>; 314 power-domains = <&CLUSTER_PD>; 315 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 316 }; 317 318 CPU_PD1: power-domain-cpu1 { 319 #power-domain-cells = <0>; 320 power-domains = <&CLUSTER_PD>; 321 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 322 }; 323 324 CPU_PD2: power-domain-cpu2 { 325 #power-domain-cells = <0>; 326 power-domains = <&CLUSTER_PD>; 327 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 328 }; 329 330 CPU_PD3: power-domain-cpu3 { 331 #power-domain-cells = <0>; 332 power-domains = <&CLUSTER_PD>; 333 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 334 }; 335 336 CPU_PD4: power-domain-cpu4 { 337 #power-domain-cells = <0>; 338 power-domains = <&CLUSTER_PD>; 339 domain-idle-states = <&BIG_CPU_SLEEP_0>; 340 }; 341 342 CPU_PD5: power-domain-cpu5 { 343 #power-domain-cells = <0>; 344 power-domains = <&CLUSTER_PD>; 345 domain-idle-states = <&BIG_CPU_SLEEP_0>; 346 }; 347 348 CPU_PD6: power-domain-cpu6 { 349 #power-domain-cells = <0>; 350 power-domains = <&CLUSTER_PD>; 351 domain-idle-states = <&BIG_CPU_SLEEP_0>; 352 }; 353 354 CPU_PD7: power-domain-cpu7 { 355 #power-domain-cells = <0>; 356 power-domains = <&CLUSTER_PD>; 357 domain-idle-states = <&BIG_CPU_SLEEP_0>; 358 }; 359 360 CLUSTER_PD: power-domain-cpu-cluster0 { 361 #power-domain-cells = <0>; 362 domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLEEP>; 363 }; 364 }; 365 366 qup_opp_table_100mhz: opp-table-qup100mhz { 367 compatible = "operating-points-v2"; 368 369 opp-50000000 { 370 opp-hz = /bits/ 64 <50000000>; 371 required-opps = <&rpmhpd_opp_min_svs>; 372 }; 373 374 opp-75000000 { 375 opp-hz = /bits/ 64 <75000000>; 376 required-opps = <&rpmhpd_opp_low_svs>; 377 }; 378 379 opp-100000000 { 380 opp-hz = /bits/ 64 <100000000>; 381 required-opps = <&rpmhpd_opp_svs>; 382 }; 383 }; 384 385 qup_opp_table_120mhz: opp-table-qup120mhz { 386 compatible = "operating-points-v2"; 387 388 opp-50000000 { 389 opp-hz = /bits/ 64 <50000000>; 390 required-opps = <&rpmhpd_opp_min_svs>; 391 }; 392 393 opp-75000000 { 394 opp-hz = /bits/ 64 <75000000>; 395 required-opps = <&rpmhpd_opp_low_svs>; 396 }; 397 398 opp-120000000 { 399 opp-hz = /bits/ 64 <120000000>; 400 required-opps = <&rpmhpd_opp_svs>; 401 }; 402 }; 403 404 reserved_memory: reserved-memory { 405 #address-cells = <2>; 406 #size-cells = <2>; 407 ranges; 408 409 hyp_mem: memory@80000000 { 410 reg = <0x0 0x80000000 0x0 0x600000>; 411 no-map; 412 }; 413 414 xbl_aop_mem: memory@80700000 { 415 no-map; 416 reg = <0x0 0x80700000 0x0 0x160000>; 417 }; 418 419 cmd_db: memory@80860000 { 420 compatible = "qcom,cmd-db"; 421 reg = <0x0 0x80860000 0x0 0x20000>; 422 no-map; 423 }; 424 425 reserved_xbl_uefi_log: memory@80880000 { 426 reg = <0x0 0x80880000 0x0 0x14000>; 427 no-map; 428 }; 429 430 smem@80900000 { 431 compatible = "qcom,smem"; 432 reg = <0x0 0x80900000 0x0 0x200000>; 433 hwlocks = <&tcsr_mutex 3>; 434 no-map; 435 }; 436 437 cpucp_fw_mem: memory@80b00000 { 438 reg = <0x0 0x80b00000 0x0 0x100000>; 439 no-map; 440 }; 441 442 cdsp_secure_heap: memory@80c00000 { 443 reg = <0x0 0x80c00000 0x0 0x4600000>; 444 no-map; 445 }; 446 447 pil_camera_mem: mmeory@85200000 { 448 reg = <0x0 0x85200000 0x0 0x500000>; 449 no-map; 450 }; 451 452 pil_video_mem: memory@85700000 { 453 reg = <0x0 0x85700000 0x0 0x500000>; 454 no-map; 455 }; 456 457 pil_cvp_mem: memory@85c00000 { 458 reg = <0x0 0x85c00000 0x0 0x500000>; 459 no-map; 460 }; 461 462 pil_adsp_mem: memory@86100000 { 463 reg = <0x0 0x86100000 0x0 0x2100000>; 464 no-map; 465 }; 466 467 pil_slpi_mem: memory@88200000 { 468 reg = <0x0 0x88200000 0x0 0x1500000>; 469 no-map; 470 }; 471 472 pil_cdsp_mem: memory@89700000 { 473 reg = <0x0 0x89700000 0x0 0x1e00000>; 474 no-map; 475 }; 476 477 pil_ipa_fw_mem: memory@8b500000 { 478 reg = <0x0 0x8b500000 0x0 0x10000>; 479 no-map; 480 }; 481 482 pil_ipa_gsi_mem: memory@8b510000 { 483 reg = <0x0 0x8b510000 0x0 0xa000>; 484 no-map; 485 }; 486 487 pil_gpu_mem: memory@8b51a000 { 488 reg = <0x0 0x8b51a000 0x0 0x2000>; 489 no-map; 490 }; 491 492 pil_spss_mem: memory@8b600000 { 493 reg = <0x0 0x8b600000 0x0 0x100000>; 494 no-map; 495 }; 496 497 pil_modem_mem: memory@8b800000 { 498 reg = <0x0 0x8b800000 0x0 0x10000000>; 499 no-map; 500 }; 501 502 rmtfs_mem: memory@9b800000 { 503 compatible = "qcom,rmtfs-mem"; 504 reg = <0x0 0x9b800000 0x0 0x280000>; 505 no-map; 506 507 qcom,client-id = <1>; 508 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 509 }; 510 511 hyp_reserved_mem: memory@d0000000 { 512 reg = <0x0 0xd0000000 0x0 0x800000>; 513 no-map; 514 }; 515 516 pil_trustedvm_mem: memory@d0800000 { 517 reg = <0x0 0xd0800000 0x0 0x76f7000>; 518 no-map; 519 }; 520 521 qrtr_shbuf: memory@d7ef7000 { 522 reg = <0x0 0xd7ef7000 0x0 0x9000>; 523 no-map; 524 }; 525 526 chan0_shbuf: memory@d7f00000 { 527 reg = <0x0 0xd7f00000 0x0 0x80000>; 528 no-map; 529 }; 530 531 chan1_shbuf: memory@d7f80000 { 532 reg = <0x0 0xd7f80000 0x0 0x80000>; 533 no-map; 534 }; 535 536 removed_mem: memory@d8800000 { 537 reg = <0x0 0xd8800000 0x0 0x6800000>; 538 no-map; 539 }; 540 }; 541 542 smp2p-adsp { 543 compatible = "qcom,smp2p"; 544 qcom,smem = <443>, <429>; 545 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 546 IPCC_MPROC_SIGNAL_SMP2P 547 IRQ_TYPE_EDGE_RISING>; 548 mboxes = <&ipcc IPCC_CLIENT_LPASS 549 IPCC_MPROC_SIGNAL_SMP2P>; 550 551 qcom,local-pid = <0>; 552 qcom,remote-pid = <2>; 553 554 smp2p_adsp_out: master-kernel { 555 qcom,entry-name = "master-kernel"; 556 #qcom,smem-state-cells = <1>; 557 }; 558 559 smp2p_adsp_in: slave-kernel { 560 qcom,entry-name = "slave-kernel"; 561 interrupt-controller; 562 #interrupt-cells = <2>; 563 }; 564 }; 565 566 smp2p-cdsp { 567 compatible = "qcom,smp2p"; 568 qcom,smem = <94>, <432>; 569 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 570 IPCC_MPROC_SIGNAL_SMP2P 571 IRQ_TYPE_EDGE_RISING>; 572 mboxes = <&ipcc IPCC_CLIENT_CDSP 573 IPCC_MPROC_SIGNAL_SMP2P>; 574 575 qcom,local-pid = <0>; 576 qcom,remote-pid = <5>; 577 578 smp2p_cdsp_out: master-kernel { 579 qcom,entry-name = "master-kernel"; 580 #qcom,smem-state-cells = <1>; 581 }; 582 583 smp2p_cdsp_in: slave-kernel { 584 qcom,entry-name = "slave-kernel"; 585 interrupt-controller; 586 #interrupt-cells = <2>; 587 }; 588 }; 589 590 smp2p-modem { 591 compatible = "qcom,smp2p"; 592 qcom,smem = <435>, <428>; 593 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 594 IPCC_MPROC_SIGNAL_SMP2P 595 IRQ_TYPE_EDGE_RISING>; 596 mboxes = <&ipcc IPCC_CLIENT_MPSS 597 IPCC_MPROC_SIGNAL_SMP2P>; 598 599 qcom,local-pid = <0>; 600 qcom,remote-pid = <1>; 601 602 smp2p_modem_out: master-kernel { 603 qcom,entry-name = "master-kernel"; 604 #qcom,smem-state-cells = <1>; 605 }; 606 607 smp2p_modem_in: slave-kernel { 608 qcom,entry-name = "slave-kernel"; 609 interrupt-controller; 610 #interrupt-cells = <2>; 611 }; 612 613 ipa_smp2p_out: ipa-ap-to-modem { 614 qcom,entry-name = "ipa"; 615 #qcom,smem-state-cells = <1>; 616 }; 617 618 ipa_smp2p_in: ipa-modem-to-ap { 619 qcom,entry-name = "ipa"; 620 interrupt-controller; 621 #interrupt-cells = <2>; 622 }; 623 }; 624 625 smp2p-slpi { 626 compatible = "qcom,smp2p"; 627 qcom,smem = <481>, <430>; 628 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 629 IPCC_MPROC_SIGNAL_SMP2P 630 IRQ_TYPE_EDGE_RISING>; 631 mboxes = <&ipcc IPCC_CLIENT_SLPI 632 IPCC_MPROC_SIGNAL_SMP2P>; 633 634 qcom,local-pid = <0>; 635 qcom,remote-pid = <3>; 636 637 smp2p_slpi_out: master-kernel { 638 qcom,entry-name = "master-kernel"; 639 #qcom,smem-state-cells = <1>; 640 }; 641 642 smp2p_slpi_in: slave-kernel { 643 qcom,entry-name = "slave-kernel"; 644 interrupt-controller; 645 #interrupt-cells = <2>; 646 }; 647 }; 648 649 soc: soc@0 { 650 #address-cells = <2>; 651 #size-cells = <2>; 652 ranges = <0 0 0 0 0x10 0>; 653 dma-ranges = <0 0 0 0 0x10 0>; 654 compatible = "simple-bus"; 655 656 gcc: clock-controller@100000 { 657 compatible = "qcom,gcc-sm8350"; 658 reg = <0x0 0x00100000 0x0 0x1f0000>; 659 #clock-cells = <1>; 660 #reset-cells = <1>; 661 #power-domain-cells = <1>; 662 clock-names = "bi_tcxo", 663 "sleep_clk", 664 "pcie_0_pipe_clk", 665 "pcie_1_pipe_clk", 666 "ufs_card_rx_symbol_0_clk", 667 "ufs_card_rx_symbol_1_clk", 668 "ufs_card_tx_symbol_0_clk", 669 "ufs_phy_rx_symbol_0_clk", 670 "ufs_phy_rx_symbol_1_clk", 671 "ufs_phy_tx_symbol_0_clk", 672 "usb3_phy_wrapper_gcc_usb30_pipe_clk", 673 "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; 674 clocks = <&rpmhcc RPMH_CXO_CLK>, 675 <&sleep_clk>, 676 <&pcie0_phy>, 677 <&pcie1_phy>, 678 <0>, 679 <0>, 680 <0>, 681 <&ufs_mem_phy 0>, 682 <&ufs_mem_phy 1>, 683 <&ufs_mem_phy 2>, 684 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 685 <0>; 686 }; 687 688 ipcc: mailbox@408000 { 689 compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; 690 reg = <0 0x00408000 0 0x1000>; 691 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 692 interrupt-controller; 693 #interrupt-cells = <3>; 694 #mbox-cells = <2>; 695 }; 696 697 gpi_dma2: dma-controller@800000 { 698 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 699 reg = <0 0x00800000 0 0x60000>; 700 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 712 dma-channels = <12>; 713 dma-channel-mask = <0xff>; 714 iommus = <&apps_smmu 0x5f6 0x0>; 715 #dma-cells = <3>; 716 status = "disabled"; 717 }; 718 719 qupv3_id_2: geniqup@8c0000 { 720 compatible = "qcom,geni-se-qup"; 721 reg = <0x0 0x008c0000 0x0 0x6000>; 722 clock-names = "m-ahb", "s-ahb"; 723 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 724 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 725 iommus = <&apps_smmu 0x5e3 0x0>; 726 #address-cells = <2>; 727 #size-cells = <2>; 728 ranges; 729 status = "disabled"; 730 731 i2c14: i2c@880000 { 732 compatible = "qcom,geni-i2c"; 733 reg = <0 0x00880000 0 0x4000>; 734 clock-names = "se"; 735 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 736 pinctrl-names = "default"; 737 pinctrl-0 = <&qup_i2c14_default>; 738 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 739 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 740 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 741 dma-names = "tx", "rx"; 742 #address-cells = <1>; 743 #size-cells = <0>; 744 status = "disabled"; 745 }; 746 747 spi14: spi@880000 { 748 compatible = "qcom,geni-spi"; 749 reg = <0 0x00880000 0 0x4000>; 750 clock-names = "se"; 751 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 752 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 753 power-domains = <&rpmhpd RPMHPD_CX>; 754 operating-points-v2 = <&qup_opp_table_120mhz>; 755 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 756 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 757 dma-names = "tx", "rx"; 758 #address-cells = <1>; 759 #size-cells = <0>; 760 status = "disabled"; 761 }; 762 763 i2c15: i2c@884000 { 764 compatible = "qcom,geni-i2c"; 765 reg = <0 0x00884000 0 0x4000>; 766 clock-names = "se"; 767 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 768 pinctrl-names = "default"; 769 pinctrl-0 = <&qup_i2c15_default>; 770 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 771 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 772 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 773 dma-names = "tx", "rx"; 774 #address-cells = <1>; 775 #size-cells = <0>; 776 status = "disabled"; 777 }; 778 779 spi15: spi@884000 { 780 compatible = "qcom,geni-spi"; 781 reg = <0 0x00884000 0 0x4000>; 782 clock-names = "se"; 783 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 784 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 785 power-domains = <&rpmhpd RPMHPD_CX>; 786 operating-points-v2 = <&qup_opp_table_120mhz>; 787 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 788 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 789 dma-names = "tx", "rx"; 790 #address-cells = <1>; 791 #size-cells = <0>; 792 status = "disabled"; 793 }; 794 795 i2c16: i2c@888000 { 796 compatible = "qcom,geni-i2c"; 797 reg = <0 0x00888000 0 0x4000>; 798 clock-names = "se"; 799 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 800 pinctrl-names = "default"; 801 pinctrl-0 = <&qup_i2c16_default>; 802 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 803 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 804 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 805 dma-names = "tx", "rx"; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 status = "disabled"; 809 }; 810 811 spi16: spi@888000 { 812 compatible = "qcom,geni-spi"; 813 reg = <0 0x00888000 0 0x4000>; 814 clock-names = "se"; 815 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 816 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 817 power-domains = <&rpmhpd RPMHPD_CX>; 818 operating-points-v2 = <&qup_opp_table_100mhz>; 819 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 820 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 821 dma-names = "tx", "rx"; 822 #address-cells = <1>; 823 #size-cells = <0>; 824 status = "disabled"; 825 }; 826 827 i2c17: i2c@88c000 { 828 compatible = "qcom,geni-i2c"; 829 reg = <0 0x0088c000 0 0x4000>; 830 clock-names = "se"; 831 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 832 pinctrl-names = "default"; 833 pinctrl-0 = <&qup_i2c17_default>; 834 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 835 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 836 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 837 dma-names = "tx", "rx"; 838 #address-cells = <1>; 839 #size-cells = <0>; 840 status = "disabled"; 841 }; 842 843 spi17: spi@88c000 { 844 compatible = "qcom,geni-spi"; 845 reg = <0 0x0088c000 0 0x4000>; 846 clock-names = "se"; 847 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 848 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 849 power-domains = <&rpmhpd RPMHPD_CX>; 850 operating-points-v2 = <&qup_opp_table_100mhz>; 851 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 852 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 853 dma-names = "tx", "rx"; 854 #address-cells = <1>; 855 #size-cells = <0>; 856 status = "disabled"; 857 }; 858 859 /* QUP no. 18 seems to be strictly SPI/UART-only */ 860 861 spi18: spi@890000 { 862 compatible = "qcom,geni-spi"; 863 reg = <0 0x00890000 0 0x4000>; 864 clock-names = "se"; 865 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 866 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 867 power-domains = <&rpmhpd RPMHPD_CX>; 868 operating-points-v2 = <&qup_opp_table_100mhz>; 869 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 870 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 871 dma-names = "tx", "rx"; 872 #address-cells = <1>; 873 #size-cells = <0>; 874 status = "disabled"; 875 }; 876 877 uart18: serial@890000 { 878 compatible = "qcom,geni-uart"; 879 reg = <0 0x00890000 0 0x4000>; 880 clock-names = "se"; 881 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 882 pinctrl-names = "default"; 883 pinctrl-0 = <&qup_uart18_default>; 884 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 885 power-domains = <&rpmhpd RPMHPD_CX>; 886 operating-points-v2 = <&qup_opp_table_100mhz>; 887 status = "disabled"; 888 }; 889 890 i2c19: i2c@894000 { 891 compatible = "qcom,geni-i2c"; 892 reg = <0 0x00894000 0 0x4000>; 893 clock-names = "se"; 894 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 895 pinctrl-names = "default"; 896 pinctrl-0 = <&qup_i2c19_default>; 897 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 898 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 899 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 900 dma-names = "tx", "rx"; 901 #address-cells = <1>; 902 #size-cells = <0>; 903 status = "disabled"; 904 }; 905 906 spi19: spi@894000 { 907 compatible = "qcom,geni-spi"; 908 reg = <0 0x00894000 0 0x4000>; 909 clock-names = "se"; 910 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 911 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 912 power-domains = <&rpmhpd RPMHPD_CX>; 913 operating-points-v2 = <&qup_opp_table_100mhz>; 914 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 915 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 916 dma-names = "tx", "rx"; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 status = "disabled"; 920 }; 921 }; 922 923 gpi_dma0: dma-controller@900000 { 924 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 925 reg = <0 0x00900000 0 0x60000>; 926 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 938 dma-channels = <12>; 939 dma-channel-mask = <0x7e>; 940 iommus = <&apps_smmu 0x5b6 0x0>; 941 #dma-cells = <3>; 942 status = "disabled"; 943 }; 944 945 qupv3_id_0: geniqup@9c0000 { 946 compatible = "qcom,geni-se-qup"; 947 reg = <0x0 0x009c0000 0x0 0x6000>; 948 clock-names = "m-ahb", "s-ahb"; 949 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 950 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 951 iommus = <&apps_smmu 0x5a3 0>; 952 #address-cells = <2>; 953 #size-cells = <2>; 954 ranges; 955 status = "disabled"; 956 957 i2c0: i2c@980000 { 958 compatible = "qcom,geni-i2c"; 959 reg = <0 0x00980000 0 0x4000>; 960 clock-names = "se"; 961 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 962 pinctrl-names = "default"; 963 pinctrl-0 = <&qup_i2c0_default>; 964 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 965 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 966 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 967 dma-names = "tx", "rx"; 968 #address-cells = <1>; 969 #size-cells = <0>; 970 status = "disabled"; 971 }; 972 973 spi0: spi@980000 { 974 compatible = "qcom,geni-spi"; 975 reg = <0 0x00980000 0 0x4000>; 976 clock-names = "se"; 977 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 978 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 979 power-domains = <&rpmhpd RPMHPD_CX>; 980 operating-points-v2 = <&qup_opp_table_100mhz>; 981 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 982 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 983 dma-names = "tx", "rx"; 984 #address-cells = <1>; 985 #size-cells = <0>; 986 status = "disabled"; 987 }; 988 989 i2c1: i2c@984000 { 990 compatible = "qcom,geni-i2c"; 991 reg = <0 0x00984000 0 0x4000>; 992 clock-names = "se"; 993 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 994 pinctrl-names = "default"; 995 pinctrl-0 = <&qup_i2c1_default>; 996 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 997 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 998 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 999 dma-names = "tx", "rx"; 1000 #address-cells = <1>; 1001 #size-cells = <0>; 1002 status = "disabled"; 1003 }; 1004 1005 spi1: spi@984000 { 1006 compatible = "qcom,geni-spi"; 1007 reg = <0 0x00984000 0 0x4000>; 1008 clock-names = "se"; 1009 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1010 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1011 power-domains = <&rpmhpd RPMHPD_CX>; 1012 operating-points-v2 = <&qup_opp_table_100mhz>; 1013 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1014 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1015 dma-names = "tx", "rx"; 1016 #address-cells = <1>; 1017 #size-cells = <0>; 1018 status = "disabled"; 1019 }; 1020 1021 i2c2: i2c@988000 { 1022 compatible = "qcom,geni-i2c"; 1023 reg = <0 0x00988000 0 0x4000>; 1024 clock-names = "se"; 1025 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1026 pinctrl-names = "default"; 1027 pinctrl-0 = <&qup_i2c2_default>; 1028 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1029 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1030 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1031 dma-names = "tx", "rx"; 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 status = "disabled"; 1035 }; 1036 1037 spi2: spi@988000 { 1038 compatible = "qcom,geni-spi"; 1039 reg = <0 0x00988000 0 0x4000>; 1040 clock-names = "se"; 1041 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1042 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1043 power-domains = <&rpmhpd RPMHPD_CX>; 1044 operating-points-v2 = <&qup_opp_table_100mhz>; 1045 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1046 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1047 dma-names = "tx", "rx"; 1048 #address-cells = <1>; 1049 #size-cells = <0>; 1050 status = "disabled"; 1051 }; 1052 1053 uart2: serial@98c000 { 1054 compatible = "qcom,geni-debug-uart"; 1055 reg = <0 0x0098c000 0 0x4000>; 1056 clock-names = "se"; 1057 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1058 pinctrl-names = "default"; 1059 pinctrl-0 = <&qup_uart3_default_state>; 1060 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1061 power-domains = <&rpmhpd RPMHPD_CX>; 1062 operating-points-v2 = <&qup_opp_table_100mhz>; 1063 status = "disabled"; 1064 }; 1065 1066 /* QUP no. 3 seems to be strictly SPI-only */ 1067 1068 spi3: spi@98c000 { 1069 compatible = "qcom,geni-spi"; 1070 reg = <0 0x0098c000 0 0x4000>; 1071 clock-names = "se"; 1072 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1073 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1074 power-domains = <&rpmhpd RPMHPD_CX>; 1075 operating-points-v2 = <&qup_opp_table_100mhz>; 1076 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1077 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1078 dma-names = "tx", "rx"; 1079 #address-cells = <1>; 1080 #size-cells = <0>; 1081 status = "disabled"; 1082 }; 1083 1084 i2c4: i2c@990000 { 1085 compatible = "qcom,geni-i2c"; 1086 reg = <0 0x00990000 0 0x4000>; 1087 clock-names = "se"; 1088 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1089 pinctrl-names = "default"; 1090 pinctrl-0 = <&qup_i2c4_default>; 1091 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1092 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1093 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1094 dma-names = "tx", "rx"; 1095 #address-cells = <1>; 1096 #size-cells = <0>; 1097 status = "disabled"; 1098 }; 1099 1100 spi4: spi@990000 { 1101 compatible = "qcom,geni-spi"; 1102 reg = <0 0x00990000 0 0x4000>; 1103 clock-names = "se"; 1104 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1105 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1106 power-domains = <&rpmhpd RPMHPD_CX>; 1107 operating-points-v2 = <&qup_opp_table_100mhz>; 1108 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1109 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1110 dma-names = "tx", "rx"; 1111 #address-cells = <1>; 1112 #size-cells = <0>; 1113 status = "disabled"; 1114 }; 1115 1116 i2c5: i2c@994000 { 1117 compatible = "qcom,geni-i2c"; 1118 reg = <0 0x00994000 0 0x4000>; 1119 clock-names = "se"; 1120 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1121 pinctrl-names = "default"; 1122 pinctrl-0 = <&qup_i2c5_default>; 1123 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1124 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1125 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1126 dma-names = "tx", "rx"; 1127 #address-cells = <1>; 1128 #size-cells = <0>; 1129 status = "disabled"; 1130 }; 1131 1132 spi5: spi@994000 { 1133 compatible = "qcom,geni-spi"; 1134 reg = <0 0x00994000 0 0x4000>; 1135 clock-names = "se"; 1136 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1137 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1138 power-domains = <&rpmhpd RPMHPD_CX>; 1139 operating-points-v2 = <&qup_opp_table_100mhz>; 1140 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1141 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1142 dma-names = "tx", "rx"; 1143 #address-cells = <1>; 1144 #size-cells = <0>; 1145 status = "disabled"; 1146 }; 1147 1148 i2c6: i2c@998000 { 1149 compatible = "qcom,geni-i2c"; 1150 reg = <0 0x00998000 0 0x4000>; 1151 clock-names = "se"; 1152 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1153 pinctrl-names = "default"; 1154 pinctrl-0 = <&qup_i2c6_default>; 1155 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1156 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1157 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1158 dma-names = "tx", "rx"; 1159 #address-cells = <1>; 1160 #size-cells = <0>; 1161 status = "disabled"; 1162 }; 1163 1164 spi6: spi@998000 { 1165 compatible = "qcom,geni-spi"; 1166 reg = <0 0x00998000 0 0x4000>; 1167 clock-names = "se"; 1168 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1169 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1170 power-domains = <&rpmhpd RPMHPD_CX>; 1171 operating-points-v2 = <&qup_opp_table_100mhz>; 1172 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1173 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1174 dma-names = "tx", "rx"; 1175 #address-cells = <1>; 1176 #size-cells = <0>; 1177 status = "disabled"; 1178 }; 1179 1180 uart6: serial@998000 { 1181 compatible = "qcom,geni-uart"; 1182 reg = <0 0x00998000 0 0x4000>; 1183 clock-names = "se"; 1184 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1185 pinctrl-names = "default"; 1186 pinctrl-0 = <&qup_uart6_default>; 1187 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1188 power-domains = <&rpmhpd RPMHPD_CX>; 1189 operating-points-v2 = <&qup_opp_table_100mhz>; 1190 status = "disabled"; 1191 }; 1192 1193 i2c7: i2c@99c000 { 1194 compatible = "qcom,geni-i2c"; 1195 reg = <0 0x0099c000 0 0x4000>; 1196 clock-names = "se"; 1197 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1198 pinctrl-names = "default"; 1199 pinctrl-0 = <&qup_i2c7_default>; 1200 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1201 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1202 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1203 dma-names = "tx", "rx"; 1204 #address-cells = <1>; 1205 #size-cells = <0>; 1206 status = "disabled"; 1207 }; 1208 1209 spi7: spi@99c000 { 1210 compatible = "qcom,geni-spi"; 1211 reg = <0 0x0099c000 0 0x4000>; 1212 clock-names = "se"; 1213 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1214 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1215 power-domains = <&rpmhpd RPMHPD_CX>; 1216 operating-points-v2 = <&qup_opp_table_100mhz>; 1217 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1218 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1219 dma-names = "tx", "rx"; 1220 #address-cells = <1>; 1221 #size-cells = <0>; 1222 status = "disabled"; 1223 }; 1224 }; 1225 1226 gpi_dma1: dma-controller@a00000 { 1227 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 1228 reg = <0 0x00a00000 0 0x60000>; 1229 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1241 dma-channels = <12>; 1242 dma-channel-mask = <0xff>; 1243 iommus = <&apps_smmu 0x56 0x0>; 1244 #dma-cells = <3>; 1245 status = "disabled"; 1246 }; 1247 1248 qupv3_id_1: geniqup@ac0000 { 1249 compatible = "qcom,geni-se-qup"; 1250 reg = <0x0 0x00ac0000 0x0 0x6000>; 1251 clock-names = "m-ahb", "s-ahb"; 1252 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1253 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1254 iommus = <&apps_smmu 0x43 0>; 1255 #address-cells = <2>; 1256 #size-cells = <2>; 1257 ranges; 1258 status = "disabled"; 1259 1260 i2c8: i2c@a80000 { 1261 compatible = "qcom,geni-i2c"; 1262 reg = <0 0x00a80000 0 0x4000>; 1263 clock-names = "se"; 1264 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1265 pinctrl-names = "default"; 1266 pinctrl-0 = <&qup_i2c8_default>; 1267 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1268 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1269 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1270 dma-names = "tx", "rx"; 1271 #address-cells = <1>; 1272 #size-cells = <0>; 1273 status = "disabled"; 1274 }; 1275 1276 spi8: spi@a80000 { 1277 compatible = "qcom,geni-spi"; 1278 reg = <0 0x00a80000 0 0x4000>; 1279 clock-names = "se"; 1280 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1281 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1282 power-domains = <&rpmhpd RPMHPD_CX>; 1283 operating-points-v2 = <&qup_opp_table_120mhz>; 1284 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1285 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1286 dma-names = "tx", "rx"; 1287 #address-cells = <1>; 1288 #size-cells = <0>; 1289 status = "disabled"; 1290 }; 1291 1292 i2c9: i2c@a84000 { 1293 compatible = "qcom,geni-i2c"; 1294 reg = <0 0x00a84000 0 0x4000>; 1295 clock-names = "se"; 1296 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1297 pinctrl-names = "default"; 1298 pinctrl-0 = <&qup_i2c9_default>; 1299 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1300 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1301 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1302 dma-names = "tx", "rx"; 1303 #address-cells = <1>; 1304 #size-cells = <0>; 1305 status = "disabled"; 1306 }; 1307 1308 spi9: spi@a84000 { 1309 compatible = "qcom,geni-spi"; 1310 reg = <0 0x00a84000 0 0x4000>; 1311 clock-names = "se"; 1312 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1313 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1314 power-domains = <&rpmhpd RPMHPD_CX>; 1315 operating-points-v2 = <&qup_opp_table_100mhz>; 1316 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1317 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1318 dma-names = "tx", "rx"; 1319 #address-cells = <1>; 1320 #size-cells = <0>; 1321 status = "disabled"; 1322 }; 1323 1324 i2c10: i2c@a88000 { 1325 compatible = "qcom,geni-i2c"; 1326 reg = <0 0x00a88000 0 0x4000>; 1327 clock-names = "se"; 1328 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1329 pinctrl-names = "default"; 1330 pinctrl-0 = <&qup_i2c10_default>; 1331 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1332 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1333 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1334 dma-names = "tx", "rx"; 1335 #address-cells = <1>; 1336 #size-cells = <0>; 1337 status = "disabled"; 1338 }; 1339 1340 spi10: spi@a88000 { 1341 compatible = "qcom,geni-spi"; 1342 reg = <0 0x00a88000 0 0x4000>; 1343 clock-names = "se"; 1344 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1345 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1346 power-domains = <&rpmhpd RPMHPD_CX>; 1347 operating-points-v2 = <&qup_opp_table_100mhz>; 1348 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1349 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1350 dma-names = "tx", "rx"; 1351 #address-cells = <1>; 1352 #size-cells = <0>; 1353 status = "disabled"; 1354 }; 1355 1356 i2c11: i2c@a8c000 { 1357 compatible = "qcom,geni-i2c"; 1358 reg = <0 0x00a8c000 0 0x4000>; 1359 clock-names = "se"; 1360 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1361 pinctrl-names = "default"; 1362 pinctrl-0 = <&qup_i2c11_default>; 1363 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1364 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1365 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1366 dma-names = "tx", "rx"; 1367 #address-cells = <1>; 1368 #size-cells = <0>; 1369 status = "disabled"; 1370 }; 1371 1372 spi11: spi@a8c000 { 1373 compatible = "qcom,geni-spi"; 1374 reg = <0 0x00a8c000 0 0x4000>; 1375 clock-names = "se"; 1376 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1377 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1378 power-domains = <&rpmhpd RPMHPD_CX>; 1379 operating-points-v2 = <&qup_opp_table_100mhz>; 1380 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1381 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1382 dma-names = "tx", "rx"; 1383 #address-cells = <1>; 1384 #size-cells = <0>; 1385 status = "disabled"; 1386 }; 1387 1388 i2c12: i2c@a90000 { 1389 compatible = "qcom,geni-i2c"; 1390 reg = <0 0x00a90000 0 0x4000>; 1391 clock-names = "se"; 1392 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1393 pinctrl-names = "default"; 1394 pinctrl-0 = <&qup_i2c12_default>; 1395 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1396 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1397 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1398 dma-names = "tx", "rx"; 1399 #address-cells = <1>; 1400 #size-cells = <0>; 1401 status = "disabled"; 1402 }; 1403 1404 spi12: spi@a90000 { 1405 compatible = "qcom,geni-spi"; 1406 reg = <0 0x00a90000 0 0x4000>; 1407 clock-names = "se"; 1408 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1409 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1410 power-domains = <&rpmhpd RPMHPD_CX>; 1411 operating-points-v2 = <&qup_opp_table_100mhz>; 1412 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1413 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1414 dma-names = "tx", "rx"; 1415 #address-cells = <1>; 1416 #size-cells = <0>; 1417 status = "disabled"; 1418 }; 1419 1420 i2c13: i2c@a94000 { 1421 compatible = "qcom,geni-i2c"; 1422 reg = <0 0x00a94000 0 0x4000>; 1423 clock-names = "se"; 1424 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1425 pinctrl-names = "default"; 1426 pinctrl-0 = <&qup_i2c13_default>; 1427 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1428 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1429 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1430 dma-names = "tx", "rx"; 1431 #address-cells = <1>; 1432 #size-cells = <0>; 1433 status = "disabled"; 1434 }; 1435 1436 spi13: spi@a94000 { 1437 compatible = "qcom,geni-spi"; 1438 reg = <0 0x00a94000 0 0x4000>; 1439 clock-names = "se"; 1440 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1441 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1442 power-domains = <&rpmhpd RPMHPD_CX>; 1443 operating-points-v2 = <&qup_opp_table_100mhz>; 1444 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1445 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1446 dma-names = "tx", "rx"; 1447 #address-cells = <1>; 1448 #size-cells = <0>; 1449 status = "disabled"; 1450 }; 1451 }; 1452 1453 rng: rng@10d3000 { 1454 compatible = "qcom,prng-ee"; 1455 reg = <0 0x010d3000 0 0x1000>; 1456 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1457 clock-names = "core"; 1458 }; 1459 1460 config_noc: interconnect@1500000 { 1461 compatible = "qcom,sm8350-config-noc"; 1462 reg = <0 0x01500000 0 0xa580>; 1463 #interconnect-cells = <2>; 1464 qcom,bcm-voters = <&apps_bcm_voter>; 1465 }; 1466 1467 mc_virt: interconnect@1580000 { 1468 compatible = "qcom,sm8350-mc-virt"; 1469 reg = <0 0x01580000 0 0x1000>; 1470 #interconnect-cells = <2>; 1471 qcom,bcm-voters = <&apps_bcm_voter>; 1472 }; 1473 1474 system_noc: interconnect@1680000 { 1475 compatible = "qcom,sm8350-system-noc"; 1476 reg = <0 0x01680000 0 0x1c200>; 1477 #interconnect-cells = <2>; 1478 qcom,bcm-voters = <&apps_bcm_voter>; 1479 }; 1480 1481 aggre1_noc: interconnect@16e0000 { 1482 compatible = "qcom,sm8350-aggre1-noc"; 1483 reg = <0 0x016e0000 0 0x1f180>; 1484 #interconnect-cells = <2>; 1485 qcom,bcm-voters = <&apps_bcm_voter>; 1486 }; 1487 1488 aggre2_noc: interconnect@1700000 { 1489 compatible = "qcom,sm8350-aggre2-noc"; 1490 reg = <0 0x01700000 0 0x33000>; 1491 #interconnect-cells = <2>; 1492 qcom,bcm-voters = <&apps_bcm_voter>; 1493 }; 1494 1495 mmss_noc: interconnect@1740000 { 1496 compatible = "qcom,sm8350-mmss-noc"; 1497 reg = <0 0x01740000 0 0x1f080>; 1498 #interconnect-cells = <2>; 1499 qcom,bcm-voters = <&apps_bcm_voter>; 1500 }; 1501 1502 pcie0: pcie@1c00000 { 1503 compatible = "qcom,pcie-sm8350"; 1504 reg = <0 0x01c00000 0 0x3000>, 1505 <0 0x60000000 0 0xf1d>, 1506 <0 0x60000f20 0 0xa8>, 1507 <0 0x60001000 0 0x1000>, 1508 <0 0x60100000 0 0x100000>; 1509 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1510 device_type = "pci"; 1511 linux,pci-domain = <0>; 1512 bus-range = <0x00 0xff>; 1513 num-lanes = <1>; 1514 1515 #address-cells = <3>; 1516 #size-cells = <2>; 1517 1518 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1519 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1520 1521 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1522 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1529 interrupt-names = "msi0", 1530 "msi1", 1531 "msi2", 1532 "msi3", 1533 "msi4", 1534 "msi5", 1535 "msi6", 1536 "msi7"; 1537 #interrupt-cells = <1>; 1538 interrupt-map-mask = <0 0 0 0x7>; 1539 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1540 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1541 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1542 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1543 1544 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1545 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1546 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1547 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1548 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1549 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1550 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1551 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1552 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; 1553 clock-names = "aux", 1554 "cfg", 1555 "bus_master", 1556 "bus_slave", 1557 "slave_q2a", 1558 "tbu", 1559 "ddrss_sf_tbu", 1560 "aggre1", 1561 "aggre0"; 1562 1563 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1564 <0x100 &apps_smmu 0x1c01 0x1>; 1565 1566 resets = <&gcc GCC_PCIE_0_BCR>; 1567 reset-names = "pci"; 1568 1569 power-domains = <&gcc PCIE_0_GDSC>; 1570 1571 phys = <&pcie0_phy>; 1572 phy-names = "pciephy"; 1573 1574 status = "disabled"; 1575 }; 1576 1577 pcie0_phy: phy@1c06000 { 1578 compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy"; 1579 reg = <0 0x01c06000 0 0x2000>; 1580 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1581 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1582 <&gcc GCC_PCIE_0_CLKREF_EN>, 1583 <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, 1584 <&gcc GCC_PCIE_0_PIPE_CLK>; 1585 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1586 1587 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1588 reset-names = "phy"; 1589 1590 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>; 1591 assigned-clock-rates = <100000000>; 1592 1593 #clock-cells = <0>; 1594 clock-output-names = "pcie_0_pipe_clk"; 1595 1596 #phy-cells = <0>; 1597 1598 status = "disabled"; 1599 }; 1600 1601 pcie1: pcie@1c08000 { 1602 compatible = "qcom,pcie-sm8350"; 1603 reg = <0 0x01c08000 0 0x3000>, 1604 <0 0x40000000 0 0xf1d>, 1605 <0 0x40000f20 0 0xa8>, 1606 <0 0x40001000 0 0x1000>, 1607 <0 0x40100000 0 0x100000>; 1608 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1609 device_type = "pci"; 1610 linux,pci-domain = <1>; 1611 bus-range = <0x00 0xff>; 1612 num-lanes = <2>; 1613 1614 #address-cells = <3>; 1615 #size-cells = <2>; 1616 1617 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1618 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1619 1620 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1621 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1622 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1623 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1624 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1625 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1626 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 1627 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1628 interrupt-names = "msi0", 1629 "msi1", 1630 "msi2", 1631 "msi3", 1632 "msi4", 1633 "msi5", 1634 "msi6", 1635 "msi7"; 1636 #interrupt-cells = <1>; 1637 interrupt-map-mask = <0 0 0 0x7>; 1638 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1639 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1640 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1641 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1642 1643 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1644 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1645 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1646 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1647 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1648 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1649 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1650 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1651 clock-names = "aux", 1652 "cfg", 1653 "bus_master", 1654 "bus_slave", 1655 "slave_q2a", 1656 "tbu", 1657 "ddrss_sf_tbu", 1658 "aggre1"; 1659 1660 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1661 <0x100 &apps_smmu 0x1c81 0x1>; 1662 1663 resets = <&gcc GCC_PCIE_1_BCR>; 1664 reset-names = "pci"; 1665 1666 power-domains = <&gcc PCIE_1_GDSC>; 1667 1668 phys = <&pcie1_phy>; 1669 phy-names = "pciephy"; 1670 1671 status = "disabled"; 1672 }; 1673 1674 pcie1_phy: phy@1c0e000 { 1675 compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy"; 1676 reg = <0 0x01c0e000 0 0x2000>; 1677 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1678 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1679 <&gcc GCC_PCIE_1_CLKREF_EN>, 1680 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, 1681 <&gcc GCC_PCIE_1_PIPE_CLK>; 1682 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1683 1684 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1685 reset-names = "phy"; 1686 1687 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1688 assigned-clock-rates = <100000000>; 1689 1690 #clock-cells = <0>; 1691 clock-output-names = "pcie_1_pipe_clk"; 1692 1693 #phy-cells = <0>; 1694 1695 status = "disabled"; 1696 }; 1697 1698 ufs_mem_hc: ufshc@1d84000 { 1699 compatible = "qcom,sm8350-ufshc", "qcom,ufshc", 1700 "jedec,ufs-2.0"; 1701 reg = <0 0x01d84000 0 0x3000>; 1702 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1703 phys = <&ufs_mem_phy>; 1704 phy-names = "ufsphy"; 1705 lanes-per-direction = <2>; 1706 #reset-cells = <1>; 1707 resets = <&gcc GCC_UFS_PHY_BCR>; 1708 reset-names = "rst"; 1709 1710 power-domains = <&gcc UFS_PHY_GDSC>; 1711 1712 iommus = <&apps_smmu 0xe0 0x0>; 1713 dma-coherent; 1714 1715 clock-names = 1716 "core_clk", 1717 "bus_aggr_clk", 1718 "iface_clk", 1719 "core_clk_unipro", 1720 "ref_clk", 1721 "tx_lane0_sync_clk", 1722 "rx_lane0_sync_clk", 1723 "rx_lane1_sync_clk"; 1724 clocks = 1725 <&gcc GCC_UFS_PHY_AXI_CLK>, 1726 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1727 <&gcc GCC_UFS_PHY_AHB_CLK>, 1728 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1729 <&rpmhcc RPMH_CXO_CLK>, 1730 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1731 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1732 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1733 freq-table-hz = 1734 <75000000 300000000>, 1735 <0 0>, 1736 <0 0>, 1737 <75000000 300000000>, 1738 <0 0>, 1739 <0 0>, 1740 <0 0>, 1741 <0 0>; 1742 status = "disabled"; 1743 }; 1744 1745 ufs_mem_phy: phy@1d87000 { 1746 compatible = "qcom,sm8350-qmp-ufs-phy"; 1747 reg = <0 0x01d87000 0 0x1000>; 1748 1749 clocks = <&rpmhcc RPMH_CXO_CLK>, 1750 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1751 <&gcc GCC_UFS_1_CLKREF_EN>; 1752 clock-names = "ref", 1753 "ref_aux", 1754 "qref"; 1755 1756 resets = <&ufs_mem_hc 0>; 1757 reset-names = "ufsphy"; 1758 1759 #clock-cells = <1>; 1760 #phy-cells = <0>; 1761 1762 status = "disabled"; 1763 }; 1764 1765 cryptobam: dma-controller@1dc4000 { 1766 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1767 reg = <0 0x01dc4000 0 0x24000>; 1768 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1769 #dma-cells = <1>; 1770 qcom,ee = <0>; 1771 qcom,controlled-remotely; 1772 iommus = <&apps_smmu 0x594 0x0011>, 1773 <&apps_smmu 0x596 0x0011>; 1774 /* FIXME: Probing BAM DMA causes some abort and system hang */ 1775 status = "fail"; 1776 }; 1777 1778 crypto: crypto@1dfa000 { 1779 compatible = "qcom,sm8350-qce", "qcom,sm8150-qce", "qcom,qce"; 1780 reg = <0 0x01dfa000 0 0x6000>; 1781 dmas = <&cryptobam 4>, <&cryptobam 5>; 1782 dma-names = "rx", "tx"; 1783 iommus = <&apps_smmu 0x594 0x0011>, 1784 <&apps_smmu 0x596 0x0011>; 1785 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 1786 interconnect-names = "memory"; 1787 /* FIXME: dependency BAM DMA is disabled */ 1788 status = "disabled"; 1789 }; 1790 1791 ipa: ipa@1e40000 { 1792 compatible = "qcom,sm8350-ipa"; 1793 1794 iommus = <&apps_smmu 0x5c0 0x0>, 1795 <&apps_smmu 0x5c2 0x0>; 1796 reg = <0 0x01e40000 0 0x8000>, 1797 <0 0x01e50000 0 0x4b20>, 1798 <0 0x01e04000 0 0x23000>; 1799 reg-names = "ipa-reg", 1800 "ipa-shared", 1801 "gsi"; 1802 1803 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, 1804 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1805 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1806 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1807 interrupt-names = "ipa", 1808 "gsi", 1809 "ipa-clock-query", 1810 "ipa-setup-ready"; 1811 1812 clocks = <&rpmhcc RPMH_IPA_CLK>; 1813 clock-names = "core"; 1814 1815 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1816 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1817 interconnect-names = "memory", 1818 "config"; 1819 1820 qcom,qmp = <&aoss_qmp>; 1821 1822 qcom,smem-states = <&ipa_smp2p_out 0>, 1823 <&ipa_smp2p_out 1>; 1824 qcom,smem-state-names = "ipa-clock-enabled-valid", 1825 "ipa-clock-enabled"; 1826 1827 status = "disabled"; 1828 }; 1829 1830 tcsr_mutex: hwlock@1f40000 { 1831 compatible = "qcom,tcsr-mutex"; 1832 reg = <0x0 0x01f40000 0x0 0x40000>; 1833 #hwlock-cells = <1>; 1834 }; 1835 1836 tcsr: syscon@1fc0000 { 1837 compatible = "qcom,sm8350-tcsr", "syscon"; 1838 reg = <0x0 0x1fc0000 0x0 0x30000>; 1839 }; 1840 1841 lpass_tlmm: pinctrl@33c0000 { 1842 compatible = "qcom,sm8350-lpass-lpi-pinctrl"; 1843 reg = <0 0x033c0000 0 0x20000>, 1844 <0 0x03550000 0 0x10000>; 1845 1846 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1847 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1848 clock-names = "core", "audio"; 1849 1850 gpio-controller; 1851 #gpio-cells = <2>; 1852 gpio-ranges = <&lpass_tlmm 0 0 15>; 1853 }; 1854 1855 gpu: gpu@3d00000 { 1856 compatible = "qcom,adreno-660.1", "qcom,adreno"; 1857 1858 reg = <0 0x03d00000 0 0x40000>, 1859 <0 0x03d9e000 0 0x1000>, 1860 <0 0x03d61000 0 0x800>; 1861 reg-names = "kgsl_3d0_reg_memory", 1862 "cx_mem", 1863 "cx_dbgc"; 1864 1865 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1866 1867 iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>; 1868 1869 operating-points-v2 = <&gpu_opp_table>; 1870 1871 qcom,gmu = <&gmu>; 1872 #cooling-cells = <2>; 1873 1874 status = "disabled"; 1875 1876 zap-shader { 1877 memory-region = <&pil_gpu_mem>; 1878 }; 1879 1880 /* note: downstream checks gpu binning for 670 Mhz */ 1881 gpu_opp_table: opp-table { 1882 compatible = "operating-points-v2"; 1883 1884 opp-840000000 { 1885 opp-hz = /bits/ 64 <840000000>; 1886 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1887 }; 1888 1889 opp-778000000 { 1890 opp-hz = /bits/ 64 <778000000>; 1891 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1892 }; 1893 1894 opp-738000000 { 1895 opp-hz = /bits/ 64 <738000000>; 1896 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1897 }; 1898 1899 opp-676000000 { 1900 opp-hz = /bits/ 64 <676000000>; 1901 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1902 }; 1903 1904 opp-608000000 { 1905 opp-hz = /bits/ 64 <608000000>; 1906 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1907 }; 1908 1909 opp-540000000 { 1910 opp-hz = /bits/ 64 <540000000>; 1911 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1912 }; 1913 1914 opp-491000000 { 1915 opp-hz = /bits/ 64 <491000000>; 1916 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 1917 }; 1918 1919 opp-443000000 { 1920 opp-hz = /bits/ 64 <443000000>; 1921 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1922 }; 1923 1924 opp-379000000 { 1925 opp-hz = /bits/ 64 <379000000>; 1926 opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>; 1927 }; 1928 1929 opp-315000000 { 1930 opp-hz = /bits/ 64 <315000000>; 1931 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1932 }; 1933 }; 1934 }; 1935 1936 gmu: gmu@3d6a000 { 1937 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu"; 1938 1939 reg = <0 0x03d6a000 0 0x34000>, 1940 <0 0x03de0000 0 0x10000>, 1941 <0 0x0b290000 0 0x10000>; 1942 reg-names = "gmu", "rscc", "gmu_pdc"; 1943 1944 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1945 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1946 interrupt-names = "hfi", "gmu"; 1947 1948 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 1949 <&gpucc GPU_CC_CXO_CLK>, 1950 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1951 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1952 <&gpucc GPU_CC_AHB_CLK>, 1953 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 1954 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 1955 clock-names = "gmu", 1956 "cxo", 1957 "axi", 1958 "memnoc", 1959 "ahb", 1960 "hub", 1961 "smmu_vote"; 1962 1963 power-domains = <&gpucc GPU_CX_GDSC>, 1964 <&gpucc GPU_GX_GDSC>; 1965 power-domain-names = "cx", 1966 "gx"; 1967 1968 iommus = <&adreno_smmu 5 0x400>; 1969 1970 operating-points-v2 = <&gmu_opp_table>; 1971 1972 gmu_opp_table: opp-table { 1973 compatible = "operating-points-v2"; 1974 1975 opp-200000000 { 1976 opp-hz = /bits/ 64 <200000000>; 1977 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1978 }; 1979 }; 1980 }; 1981 1982 gpucc: clock-controller@3d90000 { 1983 compatible = "qcom,sm8350-gpucc"; 1984 reg = <0 0x03d90000 0 0x9000>; 1985 clocks = <&rpmhcc RPMH_CXO_CLK>, 1986 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1987 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1988 clock-names = "bi_tcxo", 1989 "gcc_gpu_gpll0_clk_src", 1990 "gcc_gpu_gpll0_div_clk_src"; 1991 #clock-cells = <1>; 1992 #reset-cells = <1>; 1993 #power-domain-cells = <1>; 1994 }; 1995 1996 adreno_smmu: iommu@3da0000 { 1997 compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu", 1998 "qcom,smmu-500", "arm,mmu-500"; 1999 reg = <0 0x03da0000 0 0x20000>; 2000 #iommu-cells = <2>; 2001 #global-interrupts = <2>; 2002 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2003 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2004 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2005 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2006 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2007 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2008 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2009 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2010 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2011 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2012 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2013 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2014 2015 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2016 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2017 <&gpucc GPU_CC_AHB_CLK>, 2018 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2019 <&gpucc GPU_CC_CX_GMU_CLK>, 2020 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2021 <&gpucc GPU_CC_HUB_AON_CLK>; 2022 clock-names = "bus", 2023 "iface", 2024 "ahb", 2025 "hlos1_vote_gpu_smmu", 2026 "cx_gmu", 2027 "hub_cx_int", 2028 "hub_aon"; 2029 2030 power-domains = <&gpucc GPU_CX_GDSC>; 2031 dma-coherent; 2032 }; 2033 2034 lpass_ag_noc: interconnect@3c40000 { 2035 compatible = "qcom,sm8350-lpass-ag-noc"; 2036 reg = <0 0x03c40000 0 0xf080>; 2037 #interconnect-cells = <2>; 2038 qcom,bcm-voters = <&apps_bcm_voter>; 2039 }; 2040 2041 mpss: remoteproc@4080000 { 2042 compatible = "qcom,sm8350-mpss-pas"; 2043 reg = <0x0 0x04080000 0x0 0x4040>; 2044 2045 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2046 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2047 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2048 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2049 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2050 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2051 interrupt-names = "wdog", "fatal", "ready", "handover", 2052 "stop-ack", "shutdown-ack"; 2053 2054 clocks = <&rpmhcc RPMH_CXO_CLK>; 2055 clock-names = "xo"; 2056 2057 power-domains = <&rpmhpd RPMHPD_CX>, 2058 <&rpmhpd RPMHPD_MSS>; 2059 power-domain-names = "cx", "mss"; 2060 2061 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2062 2063 memory-region = <&pil_modem_mem>; 2064 2065 qcom,qmp = <&aoss_qmp>; 2066 2067 qcom,smem-states = <&smp2p_modem_out 0>; 2068 qcom,smem-state-names = "stop"; 2069 2070 status = "disabled"; 2071 2072 glink-edge { 2073 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2074 IPCC_MPROC_SIGNAL_GLINK_QMP 2075 IRQ_TYPE_EDGE_RISING>; 2076 mboxes = <&ipcc IPCC_CLIENT_MPSS 2077 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2078 label = "modem"; 2079 qcom,remote-pid = <1>; 2080 }; 2081 }; 2082 2083 slpi: remoteproc@5c00000 { 2084 compatible = "qcom,sm8350-slpi-pas"; 2085 reg = <0 0x05c00000 0 0x4000>; 2086 2087 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2088 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2089 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2090 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2091 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2092 interrupt-names = "wdog", "fatal", "ready", 2093 "handover", "stop-ack"; 2094 2095 clocks = <&rpmhcc RPMH_CXO_CLK>; 2096 clock-names = "xo"; 2097 2098 power-domains = <&rpmhpd RPMHPD_LCX>, 2099 <&rpmhpd RPMHPD_LMX>; 2100 power-domain-names = "lcx", "lmx"; 2101 2102 memory-region = <&pil_slpi_mem>; 2103 2104 qcom,qmp = <&aoss_qmp>; 2105 2106 qcom,smem-states = <&smp2p_slpi_out 0>; 2107 qcom,smem-state-names = "stop"; 2108 2109 status = "disabled"; 2110 2111 glink-edge { 2112 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2113 IPCC_MPROC_SIGNAL_GLINK_QMP 2114 IRQ_TYPE_EDGE_RISING>; 2115 mboxes = <&ipcc IPCC_CLIENT_SLPI 2116 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2117 2118 label = "slpi"; 2119 qcom,remote-pid = <3>; 2120 2121 fastrpc { 2122 compatible = "qcom,fastrpc"; 2123 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2124 label = "sdsp"; 2125 qcom,non-secure-domain; 2126 #address-cells = <1>; 2127 #size-cells = <0>; 2128 2129 compute-cb@1 { 2130 compatible = "qcom,fastrpc-compute-cb"; 2131 reg = <1>; 2132 iommus = <&apps_smmu 0x0541 0x0>; 2133 }; 2134 2135 compute-cb@2 { 2136 compatible = "qcom,fastrpc-compute-cb"; 2137 reg = <2>; 2138 iommus = <&apps_smmu 0x0542 0x0>; 2139 }; 2140 2141 compute-cb@3 { 2142 compatible = "qcom,fastrpc-compute-cb"; 2143 reg = <3>; 2144 iommus = <&apps_smmu 0x0543 0x0>; 2145 /* note: shared-cb = <4> in downstream */ 2146 }; 2147 }; 2148 }; 2149 }; 2150 2151 sdhc_2: mmc@8804000 { 2152 compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5"; 2153 reg = <0 0x08804000 0 0x1000>; 2154 2155 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2156 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2157 interrupt-names = "hc_irq", "pwr_irq"; 2158 2159 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2160 <&gcc GCC_SDCC2_APPS_CLK>, 2161 <&rpmhcc RPMH_CXO_CLK>; 2162 clock-names = "iface", "core", "xo"; 2163 resets = <&gcc GCC_SDCC2_BCR>; 2164 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2165 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2166 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2167 iommus = <&apps_smmu 0x4a0 0x0>; 2168 power-domains = <&rpmhpd RPMHPD_CX>; 2169 operating-points-v2 = <&sdhc2_opp_table>; 2170 bus-width = <4>; 2171 dma-coherent; 2172 2173 status = "disabled"; 2174 2175 sdhc2_opp_table: opp-table { 2176 compatible = "operating-points-v2"; 2177 2178 opp-100000000 { 2179 opp-hz = /bits/ 64 <100000000>; 2180 required-opps = <&rpmhpd_opp_low_svs>; 2181 }; 2182 2183 opp-202000000 { 2184 opp-hz = /bits/ 64 <202000000>; 2185 required-opps = <&rpmhpd_opp_svs_l1>; 2186 }; 2187 }; 2188 }; 2189 2190 usb_1_hsphy: phy@88e3000 { 2191 compatible = "qcom,sm8350-usb-hs-phy", 2192 "qcom,usb-snps-hs-7nm-phy"; 2193 reg = <0 0x088e3000 0 0x400>; 2194 status = "disabled"; 2195 #phy-cells = <0>; 2196 2197 clocks = <&rpmhcc RPMH_CXO_CLK>; 2198 clock-names = "ref"; 2199 2200 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2201 }; 2202 2203 usb_2_hsphy: phy@88e4000 { 2204 compatible = "qcom,sm8250-usb-hs-phy", 2205 "qcom,usb-snps-hs-7nm-phy"; 2206 reg = <0 0x088e4000 0 0x400>; 2207 status = "disabled"; 2208 #phy-cells = <0>; 2209 2210 clocks = <&rpmhcc RPMH_CXO_CLK>; 2211 clock-names = "ref"; 2212 2213 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2214 }; 2215 2216 usb_1_qmpphy: phy@88e8000 { 2217 compatible = "qcom,sm8350-qmp-usb3-dp-phy"; 2218 reg = <0 0x088e8000 0 0x3000>; 2219 2220 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2221 <&rpmhcc RPMH_CXO_CLK>, 2222 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2223 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2224 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2225 2226 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2227 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2228 reset-names = "phy", "common"; 2229 2230 #clock-cells = <1>; 2231 #phy-cells = <1>; 2232 2233 status = "disabled"; 2234 2235 ports { 2236 #address-cells = <1>; 2237 #size-cells = <0>; 2238 2239 port@0 { 2240 reg = <0>; 2241 2242 usb_1_qmpphy_out: endpoint { 2243 }; 2244 }; 2245 2246 port@1 { 2247 reg = <1>; 2248 2249 usb_1_qmpphy_usb_ss_in: endpoint { 2250 }; 2251 }; 2252 2253 port@2 { 2254 reg = <2>; 2255 2256 usb_1_qmpphy_dp_in: endpoint { 2257 }; 2258 }; 2259 }; 2260 }; 2261 2262 usb_2_qmpphy: phy@88eb000 { 2263 compatible = "qcom,sm8350-qmp-usb3-uni-phy"; 2264 reg = <0 0x088eb000 0 0x2000>; 2265 status = "disabled"; 2266 2267 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2268 <&gcc GCC_USB3_SEC_CLKREF_EN>, 2269 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2270 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2271 clock-names = "aux", 2272 "ref", 2273 "com_aux", 2274 "pipe"; 2275 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2276 #clock-cells = <0>; 2277 #phy-cells = <0>; 2278 2279 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2280 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 2281 reset-names = "phy", 2282 "phy_phy"; 2283 }; 2284 2285 dc_noc: interconnect@90c0000 { 2286 compatible = "qcom,sm8350-dc-noc"; 2287 reg = <0 0x090c0000 0 0x4200>; 2288 #interconnect-cells = <2>; 2289 qcom,bcm-voters = <&apps_bcm_voter>; 2290 }; 2291 2292 gem_noc: interconnect@9100000 { 2293 compatible = "qcom,sm8350-gem-noc"; 2294 reg = <0 0x09100000 0 0xb4000>; 2295 #interconnect-cells = <2>; 2296 qcom,bcm-voters = <&apps_bcm_voter>; 2297 }; 2298 2299 system-cache-controller@9200000 { 2300 compatible = "qcom,sm8350-llcc"; 2301 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 2302 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 2303 <0 0x09600000 0 0x58000>; 2304 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2305 "llcc3_base", "llcc_broadcast_base"; 2306 }; 2307 2308 compute_noc: interconnect@a0c0000 { 2309 compatible = "qcom,sm8350-compute-noc"; 2310 reg = <0 0x0a0c0000 0 0xa180>; 2311 #interconnect-cells = <2>; 2312 qcom,bcm-voters = <&apps_bcm_voter>; 2313 }; 2314 2315 usb_1: usb@a6f8800 { 2316 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2317 reg = <0 0x0a6f8800 0 0x400>; 2318 status = "disabled"; 2319 #address-cells = <2>; 2320 #size-cells = <2>; 2321 ranges; 2322 2323 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2324 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2325 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2326 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2327 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 2328 clock-names = "cfg_noc", 2329 "core", 2330 "iface", 2331 "sleep", 2332 "mock_utmi"; 2333 2334 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2335 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2336 assigned-clock-rates = <19200000>, <200000000>; 2337 2338 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2339 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2340 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2341 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2342 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2343 interrupt-names = "pwr_event", 2344 "hs_phy_irq", 2345 "dp_hs_phy_irq", 2346 "dm_hs_phy_irq", 2347 "ss_phy_irq"; 2348 2349 power-domains = <&gcc USB30_PRIM_GDSC>; 2350 2351 resets = <&gcc GCC_USB30_PRIM_BCR>; 2352 2353 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2354 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 2355 interconnect-names = "usb-ddr", "apps-usb"; 2356 2357 usb_1_dwc3: usb@a600000 { 2358 compatible = "snps,dwc3"; 2359 reg = <0 0x0a600000 0 0xcd00>; 2360 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2361 iommus = <&apps_smmu 0x0 0x0>; 2362 snps,dis_u2_susphy_quirk; 2363 snps,dis_enblslpm_quirk; 2364 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 2365 phy-names = "usb2-phy", "usb3-phy"; 2366 2367 ports { 2368 #address-cells = <1>; 2369 #size-cells = <0>; 2370 2371 port@0 { 2372 reg = <0>; 2373 2374 usb_1_dwc3_hs: endpoint { 2375 }; 2376 }; 2377 2378 port@1 { 2379 reg = <1>; 2380 2381 usb_1_dwc3_ss: endpoint { 2382 }; 2383 }; 2384 }; 2385 }; 2386 }; 2387 2388 usb_2: usb@a8f8800 { 2389 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2390 reg = <0 0x0a8f8800 0 0x400>; 2391 status = "disabled"; 2392 #address-cells = <2>; 2393 #size-cells = <2>; 2394 ranges; 2395 2396 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2397 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2398 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2399 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2400 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2401 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2402 clock-names = "cfg_noc", 2403 "core", 2404 "iface", 2405 "sleep", 2406 "mock_utmi", 2407 "xo"; 2408 2409 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2410 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2411 assigned-clock-rates = <19200000>, <200000000>; 2412 2413 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 2414 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2415 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 2416 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 2417 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 2418 interrupt-names = "pwr_event", 2419 "hs_phy_irq", 2420 "dp_hs_phy_irq", 2421 "dm_hs_phy_irq", 2422 "ss_phy_irq"; 2423 2424 power-domains = <&gcc USB30_SEC_GDSC>; 2425 2426 resets = <&gcc GCC_USB30_SEC_BCR>; 2427 2428 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 2429 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 2430 interconnect-names = "usb-ddr", "apps-usb"; 2431 2432 usb_2_dwc3: usb@a800000 { 2433 compatible = "snps,dwc3"; 2434 reg = <0 0x0a800000 0 0xcd00>; 2435 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2436 iommus = <&apps_smmu 0x20 0x0>; 2437 snps,dis_u2_susphy_quirk; 2438 snps,dis_enblslpm_quirk; 2439 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>; 2440 phy-names = "usb2-phy", "usb3-phy"; 2441 }; 2442 }; 2443 2444 mdss: display-subsystem@ae00000 { 2445 compatible = "qcom,sm8350-mdss"; 2446 reg = <0 0x0ae00000 0 0x1000>; 2447 reg-names = "mdss"; 2448 2449 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 2450 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 2451 interconnect-names = "mdp0-mem", "mdp1-mem"; 2452 2453 power-domains = <&dispcc MDSS_GDSC>; 2454 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2455 2456 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2457 <&gcc GCC_DISP_HF_AXI_CLK>, 2458 <&gcc GCC_DISP_SF_AXI_CLK>, 2459 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2460 clock-names = "iface", "bus", "nrt_bus", "core"; 2461 2462 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2463 interrupt-controller; 2464 #interrupt-cells = <1>; 2465 2466 iommus = <&apps_smmu 0x820 0x402>; 2467 2468 status = "disabled"; 2469 2470 #address-cells = <2>; 2471 #size-cells = <2>; 2472 ranges; 2473 2474 mdss_mdp: display-controller@ae01000 { 2475 compatible = "qcom,sm8350-dpu"; 2476 reg = <0 0x0ae01000 0 0x8f000>, 2477 <0 0x0aeb0000 0 0x2008>; 2478 reg-names = "mdp", "vbif"; 2479 2480 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2481 <&gcc GCC_DISP_SF_AXI_CLK>, 2482 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2483 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2484 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2485 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2486 clock-names = "bus", 2487 "nrt_bus", 2488 "iface", 2489 "lut", 2490 "core", 2491 "vsync"; 2492 2493 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2494 assigned-clock-rates = <19200000>; 2495 2496 operating-points-v2 = <&dpu_opp_table>; 2497 power-domains = <&rpmhpd RPMHPD_MMCX>; 2498 2499 interrupt-parent = <&mdss>; 2500 interrupts = <0>; 2501 2502 dpu_opp_table: opp-table { 2503 compatible = "operating-points-v2"; 2504 2505 /* TODO: opp-200000000 should work with 2506 * &rpmhpd_opp_low_svs, but one some of 2507 * sm8350_hdk boards reboot using this 2508 * opp. 2509 */ 2510 opp-200000000 { 2511 opp-hz = /bits/ 64 <200000000>; 2512 required-opps = <&rpmhpd_opp_svs>; 2513 }; 2514 2515 opp-300000000 { 2516 opp-hz = /bits/ 64 <300000000>; 2517 required-opps = <&rpmhpd_opp_svs>; 2518 }; 2519 2520 opp-345000000 { 2521 opp-hz = /bits/ 64 <345000000>; 2522 required-opps = <&rpmhpd_opp_svs_l1>; 2523 }; 2524 2525 opp-460000000 { 2526 opp-hz = /bits/ 64 <460000000>; 2527 required-opps = <&rpmhpd_opp_nom>; 2528 }; 2529 }; 2530 2531 ports { 2532 #address-cells = <1>; 2533 #size-cells = <0>; 2534 2535 port@0 { 2536 reg = <0>; 2537 dpu_intf1_out: endpoint { 2538 remote-endpoint = <&mdss_dsi0_in>; 2539 }; 2540 }; 2541 2542 port@1 { 2543 reg = <1>; 2544 dpu_intf2_out: endpoint { 2545 remote-endpoint = <&mdss_dsi1_in>; 2546 }; 2547 }; 2548 2549 port@2 { 2550 reg = <2>; 2551 dpu_intf0_out: endpoint { 2552 remote-endpoint = <&mdss_dp_in>; 2553 }; 2554 }; 2555 }; 2556 }; 2557 2558 mdss_dp: displayport-controller@ae90000 { 2559 compatible = "qcom,sm8350-dp"; 2560 reg = <0 0xae90000 0 0x200>, 2561 <0 0xae90200 0 0x200>, 2562 <0 0xae90400 0 0x600>, 2563 <0 0xae91000 0 0x400>, 2564 <0 0xae91400 0 0x400>; 2565 interrupt-parent = <&mdss>; 2566 interrupts = <12>; 2567 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2568 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 2569 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 2570 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 2571 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 2572 clock-names = "core_iface", 2573 "core_aux", 2574 "ctrl_link", 2575 "ctrl_link_iface", 2576 "stream_pixel"; 2577 2578 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 2579 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 2580 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2581 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2582 2583 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 2584 phy-names = "dp"; 2585 2586 #sound-dai-cells = <0>; 2587 2588 operating-points-v2 = <&dp_opp_table>; 2589 power-domains = <&rpmhpd RPMHPD_MMCX>; 2590 2591 status = "disabled"; 2592 2593 ports { 2594 #address-cells = <1>; 2595 #size-cells = <0>; 2596 2597 port@0 { 2598 reg = <0>; 2599 mdss_dp_in: endpoint { 2600 remote-endpoint = <&dpu_intf0_out>; 2601 }; 2602 }; 2603 }; 2604 2605 dp_opp_table: opp-table { 2606 compatible = "operating-points-v2"; 2607 2608 opp-160000000 { 2609 opp-hz = /bits/ 64 <160000000>; 2610 required-opps = <&rpmhpd_opp_low_svs>; 2611 }; 2612 2613 opp-270000000 { 2614 opp-hz = /bits/ 64 <270000000>; 2615 required-opps = <&rpmhpd_opp_svs>; 2616 }; 2617 2618 opp-540000000 { 2619 opp-hz = /bits/ 64 <540000000>; 2620 required-opps = <&rpmhpd_opp_svs_l1>; 2621 }; 2622 2623 opp-810000000 { 2624 opp-hz = /bits/ 64 <810000000>; 2625 required-opps = <&rpmhpd_opp_nom>; 2626 }; 2627 }; 2628 }; 2629 2630 mdss_dsi0: dsi@ae94000 { 2631 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2632 reg = <0 0x0ae94000 0 0x400>; 2633 reg-names = "dsi_ctrl"; 2634 2635 interrupt-parent = <&mdss>; 2636 interrupts = <4>; 2637 2638 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2639 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2640 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2641 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2642 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2643 <&gcc GCC_DISP_HF_AXI_CLK>; 2644 clock-names = "byte", 2645 "byte_intf", 2646 "pixel", 2647 "core", 2648 "iface", 2649 "bus"; 2650 2651 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2652 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2653 assigned-clock-parents = <&mdss_dsi0_phy 0>, 2654 <&mdss_dsi0_phy 1>; 2655 2656 operating-points-v2 = <&dsi0_opp_table>; 2657 power-domains = <&rpmhpd RPMHPD_MMCX>; 2658 2659 phys = <&mdss_dsi0_phy>; 2660 2661 #address-cells = <1>; 2662 #size-cells = <0>; 2663 2664 status = "disabled"; 2665 2666 dsi0_opp_table: opp-table { 2667 compatible = "operating-points-v2"; 2668 2669 /* TODO: opp-187500000 should work with 2670 * &rpmhpd_opp_low_svs, but one some of 2671 * sm8350_hdk boards reboot using this 2672 * opp. 2673 */ 2674 opp-187500000 { 2675 opp-hz = /bits/ 64 <187500000>; 2676 required-opps = <&rpmhpd_opp_svs>; 2677 }; 2678 2679 opp-300000000 { 2680 opp-hz = /bits/ 64 <300000000>; 2681 required-opps = <&rpmhpd_opp_svs>; 2682 }; 2683 2684 opp-358000000 { 2685 opp-hz = /bits/ 64 <358000000>; 2686 required-opps = <&rpmhpd_opp_svs_l1>; 2687 }; 2688 }; 2689 2690 ports { 2691 #address-cells = <1>; 2692 #size-cells = <0>; 2693 2694 port@0 { 2695 reg = <0>; 2696 mdss_dsi0_in: endpoint { 2697 remote-endpoint = <&dpu_intf1_out>; 2698 }; 2699 }; 2700 2701 port@1 { 2702 reg = <1>; 2703 mdss_dsi0_out: endpoint { 2704 }; 2705 }; 2706 }; 2707 }; 2708 2709 mdss_dsi0_phy: phy@ae94400 { 2710 compatible = "qcom,sm8350-dsi-phy-5nm"; 2711 reg = <0 0x0ae94400 0 0x200>, 2712 <0 0x0ae94600 0 0x280>, 2713 <0 0x0ae94900 0 0x27c>; 2714 reg-names = "dsi_phy", 2715 "dsi_phy_lane", 2716 "dsi_pll"; 2717 2718 #clock-cells = <1>; 2719 #phy-cells = <0>; 2720 2721 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2722 <&rpmhcc RPMH_CXO_CLK>; 2723 clock-names = "iface", "ref"; 2724 2725 status = "disabled"; 2726 }; 2727 2728 mdss_dsi1: dsi@ae96000 { 2729 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2730 reg = <0 0x0ae96000 0 0x400>; 2731 reg-names = "dsi_ctrl"; 2732 2733 interrupt-parent = <&mdss>; 2734 interrupts = <5>; 2735 2736 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2737 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2738 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2739 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2740 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2741 <&gcc GCC_DISP_HF_AXI_CLK>; 2742 clock-names = "byte", 2743 "byte_intf", 2744 "pixel", 2745 "core", 2746 "iface", 2747 "bus"; 2748 2749 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 2750 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2751 assigned-clock-parents = <&mdss_dsi1_phy 0>, 2752 <&mdss_dsi1_phy 1>; 2753 2754 operating-points-v2 = <&dsi1_opp_table>; 2755 power-domains = <&rpmhpd RPMHPD_MMCX>; 2756 2757 phys = <&mdss_dsi1_phy>; 2758 2759 #address-cells = <1>; 2760 #size-cells = <0>; 2761 2762 status = "disabled"; 2763 2764 dsi1_opp_table: opp-table { 2765 compatible = "operating-points-v2"; 2766 2767 /* TODO: opp-187500000 should work with 2768 * &rpmhpd_opp_low_svs, but one some of 2769 * sm8350_hdk boards reboot using this 2770 * opp. 2771 */ 2772 opp-187500000 { 2773 opp-hz = /bits/ 64 <187500000>; 2774 required-opps = <&rpmhpd_opp_svs>; 2775 }; 2776 2777 opp-300000000 { 2778 opp-hz = /bits/ 64 <300000000>; 2779 required-opps = <&rpmhpd_opp_svs>; 2780 }; 2781 2782 opp-358000000 { 2783 opp-hz = /bits/ 64 <358000000>; 2784 required-opps = <&rpmhpd_opp_svs_l1>; 2785 }; 2786 }; 2787 2788 ports { 2789 #address-cells = <1>; 2790 #size-cells = <0>; 2791 2792 port@0 { 2793 reg = <0>; 2794 mdss_dsi1_in: endpoint { 2795 remote-endpoint = <&dpu_intf2_out>; 2796 }; 2797 }; 2798 2799 port@1 { 2800 reg = <1>; 2801 mdss_dsi1_out: endpoint { 2802 }; 2803 }; 2804 }; 2805 }; 2806 2807 mdss_dsi1_phy: phy@ae96400 { 2808 compatible = "qcom,sm8350-dsi-phy-5nm"; 2809 reg = <0 0x0ae96400 0 0x200>, 2810 <0 0x0ae96600 0 0x280>, 2811 <0 0x0ae96900 0 0x27c>; 2812 reg-names = "dsi_phy", 2813 "dsi_phy_lane", 2814 "dsi_pll"; 2815 2816 #clock-cells = <1>; 2817 #phy-cells = <0>; 2818 2819 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2820 <&rpmhcc RPMH_CXO_CLK>; 2821 clock-names = "iface", "ref"; 2822 2823 status = "disabled"; 2824 }; 2825 }; 2826 2827 dispcc: clock-controller@af00000 { 2828 compatible = "qcom,sm8350-dispcc"; 2829 reg = <0 0x0af00000 0 0x10000>; 2830 clocks = <&rpmhcc RPMH_CXO_CLK>, 2831 <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, 2832 <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, 2833 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2834 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2835 clock-names = "bi_tcxo", 2836 "dsi0_phy_pll_out_byteclk", 2837 "dsi0_phy_pll_out_dsiclk", 2838 "dsi1_phy_pll_out_byteclk", 2839 "dsi1_phy_pll_out_dsiclk", 2840 "dp_phy_pll_link_clk", 2841 "dp_phy_pll_vco_div_clk"; 2842 #clock-cells = <1>; 2843 #reset-cells = <1>; 2844 #power-domain-cells = <1>; 2845 2846 power-domains = <&rpmhpd RPMHPD_MMCX>; 2847 }; 2848 2849 pdc: interrupt-controller@b220000 { 2850 compatible = "qcom,sm8350-pdc", "qcom,pdc"; 2851 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 2852 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, 2853 <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, 2854 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, 2855 <156 716 12>; 2856 #interrupt-cells = <2>; 2857 interrupt-parent = <&intc>; 2858 interrupt-controller; 2859 }; 2860 2861 tsens0: thermal-sensor@c263000 { 2862 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 2863 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2864 <0 0x0c222000 0 0x8>; /* SROT */ 2865 #qcom,sensors = <15>; 2866 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 2867 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 2868 interrupt-names = "uplow", "critical"; 2869 #thermal-sensor-cells = <1>; 2870 }; 2871 2872 tsens1: thermal-sensor@c265000 { 2873 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 2874 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2875 <0 0x0c223000 0 0x8>; /* SROT */ 2876 #qcom,sensors = <14>; 2877 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 2878 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 2879 interrupt-names = "uplow", "critical"; 2880 #thermal-sensor-cells = <1>; 2881 }; 2882 2883 aoss_qmp: power-management@c300000 { 2884 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; 2885 reg = <0 0x0c300000 0 0x400>; 2886 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2887 IRQ_TYPE_EDGE_RISING>; 2888 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2889 2890 #clock-cells = <0>; 2891 }; 2892 2893 sram@c3f0000 { 2894 compatible = "qcom,rpmh-stats"; 2895 reg = <0 0x0c3f0000 0 0x400>; 2896 }; 2897 2898 spmi_bus: spmi@c440000 { 2899 compatible = "qcom,spmi-pmic-arb"; 2900 reg = <0x0 0x0c440000 0x0 0x1100>, 2901 <0x0 0x0c600000 0x0 0x2000000>, 2902 <0x0 0x0e600000 0x0 0x100000>, 2903 <0x0 0x0e700000 0x0 0xa0000>, 2904 <0x0 0x0c40a000 0x0 0x26000>; 2905 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2906 interrupt-names = "periph_irq"; 2907 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2908 qcom,ee = <0>; 2909 qcom,channel = <0>; 2910 #address-cells = <2>; 2911 #size-cells = <0>; 2912 interrupt-controller; 2913 #interrupt-cells = <4>; 2914 }; 2915 2916 tlmm: pinctrl@f100000 { 2917 compatible = "qcom,sm8350-tlmm"; 2918 reg = <0 0x0f100000 0 0x300000>; 2919 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2920 gpio-controller; 2921 #gpio-cells = <2>; 2922 interrupt-controller; 2923 #interrupt-cells = <2>; 2924 gpio-ranges = <&tlmm 0 0 204>; 2925 wakeup-parent = <&pdc>; 2926 2927 sdc2_default_state: sdc2-default-state { 2928 clk-pins { 2929 pins = "sdc2_clk"; 2930 drive-strength = <16>; 2931 bias-disable; 2932 }; 2933 2934 cmd-pins { 2935 pins = "sdc2_cmd"; 2936 drive-strength = <16>; 2937 bias-pull-up; 2938 }; 2939 2940 data-pins { 2941 pins = "sdc2_data"; 2942 drive-strength = <16>; 2943 bias-pull-up; 2944 }; 2945 }; 2946 2947 sdc2_sleep_state: sdc2-sleep-state { 2948 clk-pins { 2949 pins = "sdc2_clk"; 2950 drive-strength = <2>; 2951 bias-disable; 2952 }; 2953 2954 cmd-pins { 2955 pins = "sdc2_cmd"; 2956 drive-strength = <2>; 2957 bias-pull-up; 2958 }; 2959 2960 data-pins { 2961 pins = "sdc2_data"; 2962 drive-strength = <2>; 2963 bias-pull-up; 2964 }; 2965 }; 2966 2967 qup_uart3_default_state: qup-uart3-default-state { 2968 rx-pins { 2969 pins = "gpio18"; 2970 function = "qup3"; 2971 }; 2972 tx-pins { 2973 pins = "gpio19"; 2974 function = "qup3"; 2975 }; 2976 }; 2977 2978 qup_uart6_default: qup-uart6-default-state { 2979 pins = "gpio30", "gpio31"; 2980 function = "qup6"; 2981 drive-strength = <2>; 2982 bias-disable; 2983 }; 2984 2985 qup_uart18_default: qup-uart18-default-state { 2986 pins = "gpio68", "gpio69"; 2987 function = "qup18"; 2988 drive-strength = <2>; 2989 bias-disable; 2990 }; 2991 2992 qup_i2c0_default: qup-i2c0-default-state { 2993 pins = "gpio4", "gpio5"; 2994 function = "qup0"; 2995 drive-strength = <2>; 2996 bias-pull-up; 2997 }; 2998 2999 qup_i2c1_default: qup-i2c1-default-state { 3000 pins = "gpio8", "gpio9"; 3001 function = "qup1"; 3002 drive-strength = <2>; 3003 bias-pull-up; 3004 }; 3005 3006 qup_i2c2_default: qup-i2c2-default-state { 3007 pins = "gpio12", "gpio13"; 3008 function = "qup2"; 3009 drive-strength = <2>; 3010 bias-pull-up; 3011 }; 3012 3013 qup_i2c4_default: qup-i2c4-default-state { 3014 pins = "gpio20", "gpio21"; 3015 function = "qup4"; 3016 drive-strength = <2>; 3017 bias-pull-up; 3018 }; 3019 3020 qup_i2c5_default: qup-i2c5-default-state { 3021 pins = "gpio24", "gpio25"; 3022 function = "qup5"; 3023 drive-strength = <2>; 3024 bias-pull-up; 3025 }; 3026 3027 qup_i2c6_default: qup-i2c6-default-state { 3028 pins = "gpio28", "gpio29"; 3029 function = "qup6"; 3030 drive-strength = <2>; 3031 bias-pull-up; 3032 }; 3033 3034 qup_i2c7_default: qup-i2c7-default-state { 3035 pins = "gpio32", "gpio33"; 3036 function = "qup7"; 3037 drive-strength = <2>; 3038 bias-disable; 3039 }; 3040 3041 qup_i2c8_default: qup-i2c8-default-state { 3042 pins = "gpio36", "gpio37"; 3043 function = "qup8"; 3044 drive-strength = <2>; 3045 bias-pull-up; 3046 }; 3047 3048 qup_i2c9_default: qup-i2c9-default-state { 3049 pins = "gpio40", "gpio41"; 3050 function = "qup9"; 3051 drive-strength = <2>; 3052 bias-pull-up; 3053 }; 3054 3055 qup_i2c10_default: qup-i2c10-default-state { 3056 pins = "gpio44", "gpio45"; 3057 function = "qup10"; 3058 drive-strength = <2>; 3059 bias-pull-up; 3060 }; 3061 3062 qup_i2c11_default: qup-i2c11-default-state { 3063 pins = "gpio48", "gpio49"; 3064 function = "qup11"; 3065 drive-strength = <2>; 3066 bias-pull-up; 3067 }; 3068 3069 qup_i2c12_default: qup-i2c12-default-state { 3070 pins = "gpio52", "gpio53"; 3071 function = "qup12"; 3072 drive-strength = <2>; 3073 bias-pull-up; 3074 }; 3075 3076 qup_i2c13_default: qup-i2c13-default-state { 3077 pins = "gpio0", "gpio1"; 3078 function = "qup13"; 3079 drive-strength = <2>; 3080 bias-pull-up; 3081 }; 3082 3083 qup_i2c14_default: qup-i2c14-default-state { 3084 pins = "gpio56", "gpio57"; 3085 function = "qup14"; 3086 drive-strength = <2>; 3087 bias-disable; 3088 }; 3089 3090 qup_i2c15_default: qup-i2c15-default-state { 3091 pins = "gpio60", "gpio61"; 3092 function = "qup15"; 3093 drive-strength = <2>; 3094 bias-disable; 3095 }; 3096 3097 qup_i2c16_default: qup-i2c16-default-state { 3098 pins = "gpio64", "gpio65"; 3099 function = "qup16"; 3100 drive-strength = <2>; 3101 bias-disable; 3102 }; 3103 3104 qup_i2c17_default: qup-i2c17-default-state { 3105 pins = "gpio72", "gpio73"; 3106 function = "qup17"; 3107 drive-strength = <2>; 3108 bias-disable; 3109 }; 3110 3111 qup_i2c19_default: qup-i2c19-default-state { 3112 pins = "gpio76", "gpio77"; 3113 function = "qup19"; 3114 drive-strength = <2>; 3115 bias-disable; 3116 }; 3117 }; 3118 3119 apps_smmu: iommu@15000000 { 3120 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; 3121 reg = <0 0x15000000 0 0x100000>; 3122 #iommu-cells = <2>; 3123 #global-interrupts = <2>; 3124 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 3125 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3126 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3127 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3128 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3129 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3130 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3131 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3132 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3133 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3134 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3135 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3136 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3137 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3138 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3139 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3140 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3141 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3142 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3143 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3144 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3145 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3146 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3147 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3148 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3149 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3150 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3151 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3152 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3153 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3154 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3155 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3156 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3157 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3158 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3159 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3160 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3161 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3162 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3163 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3164 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3165 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3166 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3167 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3168 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3169 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3170 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3171 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3172 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3173 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3174 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3175 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3176 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3177 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3178 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3179 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3180 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3181 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3182 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3183 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3184 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3185 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3186 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3187 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3188 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3189 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3190 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3191 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3192 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3193 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3194 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3195 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3196 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3197 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3198 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3199 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3200 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3201 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3202 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3203 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3204 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3205 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3206 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3207 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3208 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3209 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3210 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3211 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3212 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3213 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3214 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3215 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3216 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3217 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3218 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3219 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3220 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 3221 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 3222 }; 3223 3224 adsp: remoteproc@17300000 { 3225 compatible = "qcom,sm8350-adsp-pas"; 3226 reg = <0 0x17300000 0 0x100>; 3227 3228 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 3229 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3230 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3231 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3232 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 3233 interrupt-names = "wdog", "fatal", "ready", 3234 "handover", "stop-ack"; 3235 3236 clocks = <&rpmhcc RPMH_CXO_CLK>; 3237 clock-names = "xo"; 3238 3239 power-domains = <&rpmhpd RPMHPD_LCX>, 3240 <&rpmhpd RPMHPD_LMX>; 3241 power-domain-names = "lcx", "lmx"; 3242 3243 memory-region = <&pil_adsp_mem>; 3244 3245 qcom,qmp = <&aoss_qmp>; 3246 3247 qcom,smem-states = <&smp2p_adsp_out 0>; 3248 qcom,smem-state-names = "stop"; 3249 3250 status = "disabled"; 3251 3252 glink-edge { 3253 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3254 IPCC_MPROC_SIGNAL_GLINK_QMP 3255 IRQ_TYPE_EDGE_RISING>; 3256 mboxes = <&ipcc IPCC_CLIENT_LPASS 3257 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3258 3259 label = "lpass"; 3260 qcom,remote-pid = <2>; 3261 3262 apr { 3263 compatible = "qcom,apr-v2"; 3264 qcom,glink-channels = "apr_audio_svc"; 3265 qcom,domain = <APR_DOMAIN_ADSP>; 3266 #address-cells = <1>; 3267 #size-cells = <0>; 3268 3269 service@3 { 3270 reg = <APR_SVC_ADSP_CORE>; 3271 compatible = "qcom,q6core"; 3272 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3273 }; 3274 3275 q6afe: service@4 { 3276 compatible = "qcom,q6afe"; 3277 reg = <APR_SVC_AFE>; 3278 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3279 3280 q6afedai: dais { 3281 compatible = "qcom,q6afe-dais"; 3282 #address-cells = <1>; 3283 #size-cells = <0>; 3284 #sound-dai-cells = <1>; 3285 }; 3286 3287 q6afecc: clock-controller { 3288 compatible = "qcom,q6afe-clocks"; 3289 #clock-cells = <2>; 3290 }; 3291 }; 3292 3293 q6asm: service@7 { 3294 compatible = "qcom,q6asm"; 3295 reg = <APR_SVC_ASM>; 3296 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3297 3298 q6asmdai: dais { 3299 compatible = "qcom,q6asm-dais"; 3300 #address-cells = <1>; 3301 #size-cells = <0>; 3302 #sound-dai-cells = <1>; 3303 iommus = <&apps_smmu 0x1801 0x0>; 3304 3305 dai@0 { 3306 reg = <0>; 3307 }; 3308 3309 dai@1 { 3310 reg = <1>; 3311 }; 3312 3313 dai@2 { 3314 reg = <2>; 3315 }; 3316 }; 3317 }; 3318 3319 q6adm: service@8 { 3320 compatible = "qcom,q6adm"; 3321 reg = <APR_SVC_ADM>; 3322 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3323 3324 q6routing: routing { 3325 compatible = "qcom,q6adm-routing"; 3326 #sound-dai-cells = <0>; 3327 }; 3328 }; 3329 }; 3330 3331 fastrpc { 3332 compatible = "qcom,fastrpc"; 3333 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3334 label = "adsp"; 3335 qcom,non-secure-domain; 3336 #address-cells = <1>; 3337 #size-cells = <0>; 3338 3339 compute-cb@3 { 3340 compatible = "qcom,fastrpc-compute-cb"; 3341 reg = <3>; 3342 iommus = <&apps_smmu 0x1803 0x0>; 3343 }; 3344 3345 compute-cb@4 { 3346 compatible = "qcom,fastrpc-compute-cb"; 3347 reg = <4>; 3348 iommus = <&apps_smmu 0x1804 0x0>; 3349 }; 3350 3351 compute-cb@5 { 3352 compatible = "qcom,fastrpc-compute-cb"; 3353 reg = <5>; 3354 iommus = <&apps_smmu 0x1805 0x0>; 3355 }; 3356 }; 3357 }; 3358 }; 3359 3360 intc: interrupt-controller@17a00000 { 3361 compatible = "arm,gic-v3"; 3362 #interrupt-cells = <3>; 3363 interrupt-controller; 3364 #redistributor-regions = <1>; 3365 redistributor-stride = <0 0x20000>; 3366 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3367 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3368 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3369 }; 3370 3371 timer@17c20000 { 3372 compatible = "arm,armv7-timer-mem"; 3373 #address-cells = <1>; 3374 #size-cells = <1>; 3375 ranges = <0 0 0 0x20000000>; 3376 reg = <0x0 0x17c20000 0x0 0x1000>; 3377 clock-frequency = <19200000>; 3378 3379 frame@17c21000 { 3380 frame-number = <0>; 3381 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3382 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3383 reg = <0x17c21000 0x1000>, 3384 <0x17c22000 0x1000>; 3385 }; 3386 3387 frame@17c23000 { 3388 frame-number = <1>; 3389 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3390 reg = <0x17c23000 0x1000>; 3391 status = "disabled"; 3392 }; 3393 3394 frame@17c25000 { 3395 frame-number = <2>; 3396 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3397 reg = <0x17c25000 0x1000>; 3398 status = "disabled"; 3399 }; 3400 3401 frame@17c27000 { 3402 frame-number = <3>; 3403 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3404 reg = <0x17c27000 0x1000>; 3405 status = "disabled"; 3406 }; 3407 3408 frame@17c29000 { 3409 frame-number = <4>; 3410 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3411 reg = <0x17c29000 0x1000>; 3412 status = "disabled"; 3413 }; 3414 3415 frame@17c2b000 { 3416 frame-number = <5>; 3417 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3418 reg = <0x17c2b000 0x1000>; 3419 status = "disabled"; 3420 }; 3421 3422 frame@17c2d000 { 3423 frame-number = <6>; 3424 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3425 reg = <0x17c2d000 0x1000>; 3426 status = "disabled"; 3427 }; 3428 }; 3429 3430 apps_rsc: rsc@18200000 { 3431 label = "apps_rsc"; 3432 compatible = "qcom,rpmh-rsc"; 3433 reg = <0x0 0x18200000 0x0 0x10000>, 3434 <0x0 0x18210000 0x0 0x10000>, 3435 <0x0 0x18220000 0x0 0x10000>; 3436 reg-names = "drv-0", "drv-1", "drv-2"; 3437 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3438 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3439 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3440 qcom,tcs-offset = <0xd00>; 3441 qcom,drv-id = <2>; 3442 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 3443 <WAKE_TCS 3>, <CONTROL_TCS 0>; 3444 power-domains = <&CLUSTER_PD>; 3445 3446 rpmhcc: clock-controller { 3447 compatible = "qcom,sm8350-rpmh-clk"; 3448 #clock-cells = <1>; 3449 clock-names = "xo"; 3450 clocks = <&xo_board>; 3451 }; 3452 3453 rpmhpd: power-controller { 3454 compatible = "qcom,sm8350-rpmhpd"; 3455 #power-domain-cells = <1>; 3456 operating-points-v2 = <&rpmhpd_opp_table>; 3457 3458 rpmhpd_opp_table: opp-table { 3459 compatible = "operating-points-v2"; 3460 3461 rpmhpd_opp_ret: opp1 { 3462 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3463 }; 3464 3465 rpmhpd_opp_min_svs: opp2 { 3466 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3467 }; 3468 3469 rpmhpd_opp_low_svs: opp3 { 3470 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3471 }; 3472 3473 rpmhpd_opp_svs: opp4 { 3474 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3475 }; 3476 3477 rpmhpd_opp_svs_l1: opp5 { 3478 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3479 }; 3480 3481 rpmhpd_opp_nom: opp6 { 3482 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3483 }; 3484 3485 rpmhpd_opp_nom_l1: opp7 { 3486 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3487 }; 3488 3489 rpmhpd_opp_nom_l2: opp8 { 3490 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3491 }; 3492 3493 rpmhpd_opp_turbo: opp9 { 3494 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3495 }; 3496 3497 rpmhpd_opp_turbo_l1: opp10 { 3498 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3499 }; 3500 }; 3501 }; 3502 3503 apps_bcm_voter: bcm-voter { 3504 compatible = "qcom,bcm-voter"; 3505 }; 3506 }; 3507 3508 cpufreq_hw: cpufreq@18591000 { 3509 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss"; 3510 reg = <0 0x18591000 0 0x1000>, 3511 <0 0x18592000 0 0x1000>, 3512 <0 0x18593000 0 0x1000>; 3513 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3514 3515 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 3516 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3517 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 3518 interrupt-names = "dcvsh-irq-0", 3519 "dcvsh-irq-1", 3520 "dcvsh-irq-2"; 3521 3522 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3523 clock-names = "xo", "alternate"; 3524 3525 #freq-domain-cells = <1>; 3526 #clock-cells = <1>; 3527 }; 3528 3529 cdsp: remoteproc@98900000 { 3530 compatible = "qcom,sm8350-cdsp-pas"; 3531 reg = <0 0x98900000 0 0x1400000>; 3532 3533 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3534 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3535 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3536 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3537 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3538 interrupt-names = "wdog", "fatal", "ready", 3539 "handover", "stop-ack"; 3540 3541 clocks = <&rpmhcc RPMH_CXO_CLK>; 3542 clock-names = "xo"; 3543 3544 power-domains = <&rpmhpd RPMHPD_CX>, 3545 <&rpmhpd RPMHPD_MXC>; 3546 power-domain-names = "cx", "mxc"; 3547 3548 interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 3549 3550 memory-region = <&pil_cdsp_mem>; 3551 3552 qcom,qmp = <&aoss_qmp>; 3553 3554 qcom,smem-states = <&smp2p_cdsp_out 0>; 3555 qcom,smem-state-names = "stop"; 3556 3557 status = "disabled"; 3558 3559 glink-edge { 3560 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3561 IPCC_MPROC_SIGNAL_GLINK_QMP 3562 IRQ_TYPE_EDGE_RISING>; 3563 mboxes = <&ipcc IPCC_CLIENT_CDSP 3564 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3565 3566 label = "cdsp"; 3567 qcom,remote-pid = <5>; 3568 3569 fastrpc { 3570 compatible = "qcom,fastrpc"; 3571 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3572 label = "cdsp"; 3573 qcom,non-secure-domain; 3574 #address-cells = <1>; 3575 #size-cells = <0>; 3576 3577 compute-cb@1 { 3578 compatible = "qcom,fastrpc-compute-cb"; 3579 reg = <1>; 3580 iommus = <&apps_smmu 0x2161 0x0400>, 3581 <&apps_smmu 0x1181 0x0420>; 3582 }; 3583 3584 compute-cb@2 { 3585 compatible = "qcom,fastrpc-compute-cb"; 3586 reg = <2>; 3587 iommus = <&apps_smmu 0x2162 0x0400>, 3588 <&apps_smmu 0x1182 0x0420>; 3589 }; 3590 3591 compute-cb@3 { 3592 compatible = "qcom,fastrpc-compute-cb"; 3593 reg = <3>; 3594 iommus = <&apps_smmu 0x2163 0x0400>, 3595 <&apps_smmu 0x1183 0x0420>; 3596 }; 3597 3598 compute-cb@4 { 3599 compatible = "qcom,fastrpc-compute-cb"; 3600 reg = <4>; 3601 iommus = <&apps_smmu 0x2164 0x0400>, 3602 <&apps_smmu 0x1184 0x0420>; 3603 }; 3604 3605 compute-cb@5 { 3606 compatible = "qcom,fastrpc-compute-cb"; 3607 reg = <5>; 3608 iommus = <&apps_smmu 0x2165 0x0400>, 3609 <&apps_smmu 0x1185 0x0420>; 3610 }; 3611 3612 compute-cb@6 { 3613 compatible = "qcom,fastrpc-compute-cb"; 3614 reg = <6>; 3615 iommus = <&apps_smmu 0x2166 0x0400>, 3616 <&apps_smmu 0x1186 0x0420>; 3617 }; 3618 3619 compute-cb@7 { 3620 compatible = "qcom,fastrpc-compute-cb"; 3621 reg = <7>; 3622 iommus = <&apps_smmu 0x2167 0x0400>, 3623 <&apps_smmu 0x1187 0x0420>; 3624 }; 3625 3626 compute-cb@8 { 3627 compatible = "qcom,fastrpc-compute-cb"; 3628 reg = <8>; 3629 iommus = <&apps_smmu 0x2168 0x0400>, 3630 <&apps_smmu 0x1188 0x0420>; 3631 }; 3632 3633 /* note: secure cb9 in downstream */ 3634 }; 3635 }; 3636 }; 3637 }; 3638 3639 thermal_zones: thermal-zones { 3640 cpu0-thermal { 3641 polling-delay-passive = <250>; 3642 polling-delay = <1000>; 3643 3644 thermal-sensors = <&tsens0 1>; 3645 3646 trips { 3647 cpu0_alert0: trip-point0 { 3648 temperature = <90000>; 3649 hysteresis = <2000>; 3650 type = "passive"; 3651 }; 3652 3653 cpu0_alert1: trip-point1 { 3654 temperature = <95000>; 3655 hysteresis = <2000>; 3656 type = "passive"; 3657 }; 3658 3659 cpu0_crit: cpu-crit { 3660 temperature = <110000>; 3661 hysteresis = <1000>; 3662 type = "critical"; 3663 }; 3664 }; 3665 3666 cooling-maps { 3667 map0 { 3668 trip = <&cpu0_alert0>; 3669 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3670 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3671 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3672 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3673 }; 3674 map1 { 3675 trip = <&cpu0_alert1>; 3676 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3677 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3678 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3679 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3680 }; 3681 }; 3682 }; 3683 3684 cpu1-thermal { 3685 polling-delay-passive = <250>; 3686 polling-delay = <1000>; 3687 3688 thermal-sensors = <&tsens0 2>; 3689 3690 trips { 3691 cpu1_alert0: trip-point0 { 3692 temperature = <90000>; 3693 hysteresis = <2000>; 3694 type = "passive"; 3695 }; 3696 3697 cpu1_alert1: trip-point1 { 3698 temperature = <95000>; 3699 hysteresis = <2000>; 3700 type = "passive"; 3701 }; 3702 3703 cpu1_crit: cpu-crit { 3704 temperature = <110000>; 3705 hysteresis = <1000>; 3706 type = "critical"; 3707 }; 3708 }; 3709 3710 cooling-maps { 3711 map0 { 3712 trip = <&cpu1_alert0>; 3713 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3714 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3715 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3716 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3717 }; 3718 map1 { 3719 trip = <&cpu1_alert1>; 3720 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3721 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3722 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3723 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3724 }; 3725 }; 3726 }; 3727 3728 cpu2-thermal { 3729 polling-delay-passive = <250>; 3730 polling-delay = <1000>; 3731 3732 thermal-sensors = <&tsens0 3>; 3733 3734 trips { 3735 cpu2_alert0: trip-point0 { 3736 temperature = <90000>; 3737 hysteresis = <2000>; 3738 type = "passive"; 3739 }; 3740 3741 cpu2_alert1: trip-point1 { 3742 temperature = <95000>; 3743 hysteresis = <2000>; 3744 type = "passive"; 3745 }; 3746 3747 cpu2_crit: cpu-crit { 3748 temperature = <110000>; 3749 hysteresis = <1000>; 3750 type = "critical"; 3751 }; 3752 }; 3753 3754 cooling-maps { 3755 map0 { 3756 trip = <&cpu2_alert0>; 3757 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3758 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3759 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3760 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3761 }; 3762 map1 { 3763 trip = <&cpu2_alert1>; 3764 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3765 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3766 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3767 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3768 }; 3769 }; 3770 }; 3771 3772 cpu3-thermal { 3773 polling-delay-passive = <250>; 3774 polling-delay = <1000>; 3775 3776 thermal-sensors = <&tsens0 4>; 3777 3778 trips { 3779 cpu3_alert0: trip-point0 { 3780 temperature = <90000>; 3781 hysteresis = <2000>; 3782 type = "passive"; 3783 }; 3784 3785 cpu3_alert1: trip-point1 { 3786 temperature = <95000>; 3787 hysteresis = <2000>; 3788 type = "passive"; 3789 }; 3790 3791 cpu3_crit: cpu-crit { 3792 temperature = <110000>; 3793 hysteresis = <1000>; 3794 type = "critical"; 3795 }; 3796 }; 3797 3798 cooling-maps { 3799 map0 { 3800 trip = <&cpu3_alert0>; 3801 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3802 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3803 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3804 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3805 }; 3806 map1 { 3807 trip = <&cpu3_alert1>; 3808 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3809 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3810 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3811 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3812 }; 3813 }; 3814 }; 3815 3816 cpu4-top-thermal { 3817 polling-delay-passive = <250>; 3818 polling-delay = <1000>; 3819 3820 thermal-sensors = <&tsens0 7>; 3821 3822 trips { 3823 cpu4_top_alert0: trip-point0 { 3824 temperature = <90000>; 3825 hysteresis = <2000>; 3826 type = "passive"; 3827 }; 3828 3829 cpu4_top_alert1: trip-point1 { 3830 temperature = <95000>; 3831 hysteresis = <2000>; 3832 type = "passive"; 3833 }; 3834 3835 cpu4_top_crit: cpu-crit { 3836 temperature = <110000>; 3837 hysteresis = <1000>; 3838 type = "critical"; 3839 }; 3840 }; 3841 3842 cooling-maps { 3843 map0 { 3844 trip = <&cpu4_top_alert0>; 3845 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3846 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3847 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3848 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3849 }; 3850 map1 { 3851 trip = <&cpu4_top_alert1>; 3852 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3853 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3854 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3855 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3856 }; 3857 }; 3858 }; 3859 3860 cpu5-top-thermal { 3861 polling-delay-passive = <250>; 3862 polling-delay = <1000>; 3863 3864 thermal-sensors = <&tsens0 8>; 3865 3866 trips { 3867 cpu5_top_alert0: trip-point0 { 3868 temperature = <90000>; 3869 hysteresis = <2000>; 3870 type = "passive"; 3871 }; 3872 3873 cpu5_top_alert1: trip-point1 { 3874 temperature = <95000>; 3875 hysteresis = <2000>; 3876 type = "passive"; 3877 }; 3878 3879 cpu5_top_crit: cpu-crit { 3880 temperature = <110000>; 3881 hysteresis = <1000>; 3882 type = "critical"; 3883 }; 3884 }; 3885 3886 cooling-maps { 3887 map0 { 3888 trip = <&cpu5_top_alert0>; 3889 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3890 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3891 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3892 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3893 }; 3894 map1 { 3895 trip = <&cpu5_top_alert1>; 3896 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3897 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3898 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3899 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3900 }; 3901 }; 3902 }; 3903 3904 cpu6-top-thermal { 3905 polling-delay-passive = <250>; 3906 polling-delay = <1000>; 3907 3908 thermal-sensors = <&tsens0 9>; 3909 3910 trips { 3911 cpu6_top_alert0: trip-point0 { 3912 temperature = <90000>; 3913 hysteresis = <2000>; 3914 type = "passive"; 3915 }; 3916 3917 cpu6_top_alert1: trip-point1 { 3918 temperature = <95000>; 3919 hysteresis = <2000>; 3920 type = "passive"; 3921 }; 3922 3923 cpu6_top_crit: cpu-crit { 3924 temperature = <110000>; 3925 hysteresis = <1000>; 3926 type = "critical"; 3927 }; 3928 }; 3929 3930 cooling-maps { 3931 map0 { 3932 trip = <&cpu6_top_alert0>; 3933 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3934 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3935 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3936 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3937 }; 3938 map1 { 3939 trip = <&cpu6_top_alert1>; 3940 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3941 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3942 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3943 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3944 }; 3945 }; 3946 }; 3947 3948 cpu7-top-thermal { 3949 polling-delay-passive = <250>; 3950 polling-delay = <1000>; 3951 3952 thermal-sensors = <&tsens0 10>; 3953 3954 trips { 3955 cpu7_top_alert0: trip-point0 { 3956 temperature = <90000>; 3957 hysteresis = <2000>; 3958 type = "passive"; 3959 }; 3960 3961 cpu7_top_alert1: trip-point1 { 3962 temperature = <95000>; 3963 hysteresis = <2000>; 3964 type = "passive"; 3965 }; 3966 3967 cpu7_top_crit: cpu-crit { 3968 temperature = <110000>; 3969 hysteresis = <1000>; 3970 type = "critical"; 3971 }; 3972 }; 3973 3974 cooling-maps { 3975 map0 { 3976 trip = <&cpu7_top_alert0>; 3977 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3978 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3979 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3980 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3981 }; 3982 map1 { 3983 trip = <&cpu7_top_alert1>; 3984 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3985 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3986 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3987 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3988 }; 3989 }; 3990 }; 3991 3992 cpu4-bottom-thermal { 3993 polling-delay-passive = <250>; 3994 polling-delay = <1000>; 3995 3996 thermal-sensors = <&tsens0 11>; 3997 3998 trips { 3999 cpu4_bottom_alert0: trip-point0 { 4000 temperature = <90000>; 4001 hysteresis = <2000>; 4002 type = "passive"; 4003 }; 4004 4005 cpu4_bottom_alert1: trip-point1 { 4006 temperature = <95000>; 4007 hysteresis = <2000>; 4008 type = "passive"; 4009 }; 4010 4011 cpu4_bottom_crit: cpu-crit { 4012 temperature = <110000>; 4013 hysteresis = <1000>; 4014 type = "critical"; 4015 }; 4016 }; 4017 4018 cooling-maps { 4019 map0 { 4020 trip = <&cpu4_bottom_alert0>; 4021 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4022 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4023 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4024 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4025 }; 4026 map1 { 4027 trip = <&cpu4_bottom_alert1>; 4028 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4029 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4030 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4031 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4032 }; 4033 }; 4034 }; 4035 4036 cpu5-bottom-thermal { 4037 polling-delay-passive = <250>; 4038 polling-delay = <1000>; 4039 4040 thermal-sensors = <&tsens0 12>; 4041 4042 trips { 4043 cpu5_bottom_alert0: trip-point0 { 4044 temperature = <90000>; 4045 hysteresis = <2000>; 4046 type = "passive"; 4047 }; 4048 4049 cpu5_bottom_alert1: trip-point1 { 4050 temperature = <95000>; 4051 hysteresis = <2000>; 4052 type = "passive"; 4053 }; 4054 4055 cpu5_bottom_crit: cpu-crit { 4056 temperature = <110000>; 4057 hysteresis = <1000>; 4058 type = "critical"; 4059 }; 4060 }; 4061 4062 cooling-maps { 4063 map0 { 4064 trip = <&cpu5_bottom_alert0>; 4065 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4066 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4067 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4068 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4069 }; 4070 map1 { 4071 trip = <&cpu5_bottom_alert1>; 4072 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4073 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4074 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4075 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4076 }; 4077 }; 4078 }; 4079 4080 cpu6-bottom-thermal { 4081 polling-delay-passive = <250>; 4082 polling-delay = <1000>; 4083 4084 thermal-sensors = <&tsens0 13>; 4085 4086 trips { 4087 cpu6_bottom_alert0: trip-point0 { 4088 temperature = <90000>; 4089 hysteresis = <2000>; 4090 type = "passive"; 4091 }; 4092 4093 cpu6_bottom_alert1: trip-point1 { 4094 temperature = <95000>; 4095 hysteresis = <2000>; 4096 type = "passive"; 4097 }; 4098 4099 cpu6_bottom_crit: cpu-crit { 4100 temperature = <110000>; 4101 hysteresis = <1000>; 4102 type = "critical"; 4103 }; 4104 }; 4105 4106 cooling-maps { 4107 map0 { 4108 trip = <&cpu6_bottom_alert0>; 4109 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4110 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4111 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4112 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4113 }; 4114 map1 { 4115 trip = <&cpu6_bottom_alert1>; 4116 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4117 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4118 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4119 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4120 }; 4121 }; 4122 }; 4123 4124 cpu7-bottom-thermal { 4125 polling-delay-passive = <250>; 4126 polling-delay = <1000>; 4127 4128 thermal-sensors = <&tsens0 14>; 4129 4130 trips { 4131 cpu7_bottom_alert0: trip-point0 { 4132 temperature = <90000>; 4133 hysteresis = <2000>; 4134 type = "passive"; 4135 }; 4136 4137 cpu7_bottom_alert1: trip-point1 { 4138 temperature = <95000>; 4139 hysteresis = <2000>; 4140 type = "passive"; 4141 }; 4142 4143 cpu7_bottom_crit: cpu-crit { 4144 temperature = <110000>; 4145 hysteresis = <1000>; 4146 type = "critical"; 4147 }; 4148 }; 4149 4150 cooling-maps { 4151 map0 { 4152 trip = <&cpu7_bottom_alert0>; 4153 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4154 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4155 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4156 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4157 }; 4158 map1 { 4159 trip = <&cpu7_bottom_alert1>; 4160 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4161 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4162 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4163 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4164 }; 4165 }; 4166 }; 4167 4168 aoss0-thermal { 4169 polling-delay-passive = <250>; 4170 polling-delay = <1000>; 4171 4172 thermal-sensors = <&tsens0 0>; 4173 4174 trips { 4175 aoss0_alert0: trip-point0 { 4176 temperature = <90000>; 4177 hysteresis = <2000>; 4178 type = "hot"; 4179 }; 4180 }; 4181 }; 4182 4183 cluster0-thermal { 4184 polling-delay-passive = <250>; 4185 polling-delay = <1000>; 4186 4187 thermal-sensors = <&tsens0 5>; 4188 4189 trips { 4190 cluster0_alert0: trip-point0 { 4191 temperature = <90000>; 4192 hysteresis = <2000>; 4193 type = "hot"; 4194 }; 4195 cluster0_crit: cluster0-crit { 4196 temperature = <110000>; 4197 hysteresis = <2000>; 4198 type = "critical"; 4199 }; 4200 }; 4201 }; 4202 4203 cluster1-thermal { 4204 polling-delay-passive = <250>; 4205 polling-delay = <1000>; 4206 4207 thermal-sensors = <&tsens0 6>; 4208 4209 trips { 4210 cluster1_alert0: trip-point0 { 4211 temperature = <90000>; 4212 hysteresis = <2000>; 4213 type = "hot"; 4214 }; 4215 cluster1_crit: cluster1-crit { 4216 temperature = <110000>; 4217 hysteresis = <2000>; 4218 type = "critical"; 4219 }; 4220 }; 4221 }; 4222 4223 aoss1-thermal { 4224 polling-delay-passive = <250>; 4225 polling-delay = <1000>; 4226 4227 thermal-sensors = <&tsens1 0>; 4228 4229 trips { 4230 aoss1_alert0: trip-point0 { 4231 temperature = <90000>; 4232 hysteresis = <2000>; 4233 type = "hot"; 4234 }; 4235 }; 4236 }; 4237 4238 gpu-top-thermal { 4239 polling-delay-passive = <250>; 4240 polling-delay = <1000>; 4241 4242 thermal-sensors = <&tsens1 1>; 4243 4244 cooling-maps { 4245 map0 { 4246 trip = <&gpu_top_alert0>; 4247 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4248 }; 4249 }; 4250 4251 trips { 4252 gpu_top_alert0: trip-point0 { 4253 temperature = <90000>; 4254 hysteresis = <1000>; 4255 type = "hot"; 4256 }; 4257 }; 4258 }; 4259 4260 gpu-bottom-thermal { 4261 polling-delay-passive = <250>; 4262 polling-delay = <1000>; 4263 4264 thermal-sensors = <&tsens1 2>; 4265 4266 cooling-maps { 4267 map0 { 4268 trip = <&gpu_bottom_alert0>; 4269 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4270 }; 4271 }; 4272 4273 trips { 4274 gpu_bottom_alert0: trip-point0 { 4275 temperature = <90000>; 4276 hysteresis = <1000>; 4277 type = "hot"; 4278 }; 4279 }; 4280 }; 4281 4282 nspss1-thermal { 4283 polling-delay-passive = <250>; 4284 polling-delay = <1000>; 4285 4286 thermal-sensors = <&tsens1 3>; 4287 4288 trips { 4289 nspss1_alert0: trip-point0 { 4290 temperature = <90000>; 4291 hysteresis = <1000>; 4292 type = "hot"; 4293 }; 4294 }; 4295 }; 4296 4297 nspss2-thermal { 4298 polling-delay-passive = <250>; 4299 polling-delay = <1000>; 4300 4301 thermal-sensors = <&tsens1 4>; 4302 4303 trips { 4304 nspss2_alert0: trip-point0 { 4305 temperature = <90000>; 4306 hysteresis = <1000>; 4307 type = "hot"; 4308 }; 4309 }; 4310 }; 4311 4312 nspss3-thermal { 4313 polling-delay-passive = <250>; 4314 polling-delay = <1000>; 4315 4316 thermal-sensors = <&tsens1 5>; 4317 4318 trips { 4319 nspss3_alert0: trip-point0 { 4320 temperature = <90000>; 4321 hysteresis = <1000>; 4322 type = "hot"; 4323 }; 4324 }; 4325 }; 4326 4327 video-thermal { 4328 polling-delay-passive = <250>; 4329 polling-delay = <1000>; 4330 4331 thermal-sensors = <&tsens1 6>; 4332 4333 trips { 4334 video_alert0: trip-point0 { 4335 temperature = <90000>; 4336 hysteresis = <2000>; 4337 type = "hot"; 4338 }; 4339 }; 4340 }; 4341 4342 mem-thermal { 4343 polling-delay-passive = <250>; 4344 polling-delay = <1000>; 4345 4346 thermal-sensors = <&tsens1 7>; 4347 4348 trips { 4349 mem_alert0: trip-point0 { 4350 temperature = <90000>; 4351 hysteresis = <2000>; 4352 type = "hot"; 4353 }; 4354 }; 4355 }; 4356 4357 modem1-top-thermal { 4358 polling-delay-passive = <250>; 4359 polling-delay = <1000>; 4360 4361 thermal-sensors = <&tsens1 8>; 4362 4363 trips { 4364 modem1_alert0: trip-point0 { 4365 temperature = <90000>; 4366 hysteresis = <2000>; 4367 type = "hot"; 4368 }; 4369 }; 4370 }; 4371 4372 modem2-top-thermal { 4373 polling-delay-passive = <250>; 4374 polling-delay = <1000>; 4375 4376 thermal-sensors = <&tsens1 9>; 4377 4378 trips { 4379 modem2_alert0: trip-point0 { 4380 temperature = <90000>; 4381 hysteresis = <2000>; 4382 type = "hot"; 4383 }; 4384 }; 4385 }; 4386 4387 modem3-top-thermal { 4388 polling-delay-passive = <250>; 4389 polling-delay = <1000>; 4390 4391 thermal-sensors = <&tsens1 10>; 4392 4393 trips { 4394 modem3_alert0: trip-point0 { 4395 temperature = <90000>; 4396 hysteresis = <2000>; 4397 type = "hot"; 4398 }; 4399 }; 4400 }; 4401 4402 modem4-top-thermal { 4403 polling-delay-passive = <250>; 4404 polling-delay = <1000>; 4405 4406 thermal-sensors = <&tsens1 11>; 4407 4408 trips { 4409 modem4_alert0: trip-point0 { 4410 temperature = <90000>; 4411 hysteresis = <2000>; 4412 type = "hot"; 4413 }; 4414 }; 4415 }; 4416 4417 camera-top-thermal { 4418 polling-delay-passive = <250>; 4419 polling-delay = <1000>; 4420 4421 thermal-sensors = <&tsens1 12>; 4422 4423 trips { 4424 camera1_alert0: trip-point0 { 4425 temperature = <90000>; 4426 hysteresis = <2000>; 4427 type = "hot"; 4428 }; 4429 }; 4430 }; 4431 4432 cam-bottom-thermal { 4433 polling-delay-passive = <250>; 4434 polling-delay = <1000>; 4435 4436 thermal-sensors = <&tsens1 13>; 4437 4438 trips { 4439 camera2_alert0: trip-point0 { 4440 temperature = <90000>; 4441 hysteresis = <2000>; 4442 type = "hot"; 4443 }; 4444 }; 4445 }; 4446 }; 4447 4448 timer { 4449 compatible = "arm,armv8-timer"; 4450 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4451 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4452 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4453 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4454 }; 4455}; 4456