1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Linaro Limited 4 */ 5 6#include <dt-bindings/interconnect/qcom,sm8350.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/qcom,dispcc-sm8350.h> 9#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 10#include <dt-bindings/clock/qcom,gcc-sm8350.h> 11#include <dt-bindings/clock/qcom,gpucc-sm8350.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/firmware/qcom,scm.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/interconnect/qcom,icc.h> 17#include <dt-bindings/interconnect/qcom,sm8350.h> 18#include <dt-bindings/mailbox/qcom-ipcc.h> 19#include <dt-bindings/phy/phy-qcom-qmp.h> 20#include <dt-bindings/power/qcom-rpmpd.h> 21#include <dt-bindings/power/qcom,rpmhpd.h> 22#include <dt-bindings/soc/qcom,apr.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24#include <dt-bindings/sound/qcom,q6afe.h> 25#include <dt-bindings/sound/qcom,q6asm.h> 26#include <dt-bindings/thermal/thermal.h> 27#include <dt-bindings/interconnect/qcom,sm8350.h> 28 29/ { 30 interrupt-parent = <&intc>; 31 32 #address-cells = <2>; 33 #size-cells = <2>; 34 35 chosen { }; 36 37 clocks { 38 xo_board: xo-board { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <38400000>; 42 clock-output-names = "xo_board"; 43 }; 44 45 sleep_clk: sleep-clk { 46 compatible = "fixed-clock"; 47 clock-frequency = <32764>; 48 #clock-cells = <0>; 49 }; 50 }; 51 52 cpus { 53 #address-cells = <2>; 54 #size-cells = <0>; 55 56 cpu0: cpu@0 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a55"; 59 reg = <0x0 0x0>; 60 clocks = <&cpufreq_hw 0>; 61 enable-method = "psci"; 62 next-level-cache = <&l2_0>; 63 qcom,freq-domain = <&cpufreq_hw 0>; 64 power-domains = <&cpu_pd0>; 65 power-domain-names = "psci"; 66 #cooling-cells = <2>; 67 l2_0: l2-cache { 68 compatible = "cache"; 69 cache-level = <2>; 70 cache-unified; 71 next-level-cache = <&l3_0>; 72 l3_0: l3-cache { 73 compatible = "cache"; 74 cache-level = <3>; 75 cache-unified; 76 }; 77 }; 78 }; 79 80 cpu1: cpu@100 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a55"; 83 reg = <0x0 0x100>; 84 clocks = <&cpufreq_hw 0>; 85 enable-method = "psci"; 86 next-level-cache = <&l2_100>; 87 qcom,freq-domain = <&cpufreq_hw 0>; 88 power-domains = <&cpu_pd1>; 89 power-domain-names = "psci"; 90 #cooling-cells = <2>; 91 l2_100: l2-cache { 92 compatible = "cache"; 93 cache-level = <2>; 94 cache-unified; 95 next-level-cache = <&l3_0>; 96 }; 97 }; 98 99 cpu2: cpu@200 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a55"; 102 reg = <0x0 0x200>; 103 clocks = <&cpufreq_hw 0>; 104 enable-method = "psci"; 105 next-level-cache = <&l2_200>; 106 qcom,freq-domain = <&cpufreq_hw 0>; 107 power-domains = <&cpu_pd2>; 108 power-domain-names = "psci"; 109 #cooling-cells = <2>; 110 l2_200: l2-cache { 111 compatible = "cache"; 112 cache-level = <2>; 113 cache-unified; 114 next-level-cache = <&l3_0>; 115 }; 116 }; 117 118 cpu3: cpu@300 { 119 device_type = "cpu"; 120 compatible = "arm,cortex-a55"; 121 reg = <0x0 0x300>; 122 clocks = <&cpufreq_hw 0>; 123 enable-method = "psci"; 124 next-level-cache = <&l2_300>; 125 qcom,freq-domain = <&cpufreq_hw 0>; 126 power-domains = <&cpu_pd3>; 127 power-domain-names = "psci"; 128 #cooling-cells = <2>; 129 l2_300: l2-cache { 130 compatible = "cache"; 131 cache-level = <2>; 132 cache-unified; 133 next-level-cache = <&l3_0>; 134 }; 135 }; 136 137 cpu4: cpu@400 { 138 device_type = "cpu"; 139 compatible = "arm,cortex-a78"; 140 reg = <0x0 0x400>; 141 clocks = <&cpufreq_hw 1>; 142 enable-method = "psci"; 143 next-level-cache = <&l2_400>; 144 qcom,freq-domain = <&cpufreq_hw 1>; 145 power-domains = <&cpu_pd4>; 146 power-domain-names = "psci"; 147 #cooling-cells = <2>; 148 l2_400: l2-cache { 149 compatible = "cache"; 150 cache-level = <2>; 151 cache-unified; 152 next-level-cache = <&l3_0>; 153 }; 154 }; 155 156 cpu5: cpu@500 { 157 device_type = "cpu"; 158 compatible = "arm,cortex-a78"; 159 reg = <0x0 0x500>; 160 clocks = <&cpufreq_hw 1>; 161 enable-method = "psci"; 162 next-level-cache = <&l2_500>; 163 qcom,freq-domain = <&cpufreq_hw 1>; 164 power-domains = <&cpu_pd5>; 165 power-domain-names = "psci"; 166 #cooling-cells = <2>; 167 l2_500: l2-cache { 168 compatible = "cache"; 169 cache-level = <2>; 170 cache-unified; 171 next-level-cache = <&l3_0>; 172 }; 173 }; 174 175 cpu6: cpu@600 { 176 device_type = "cpu"; 177 compatible = "arm,cortex-a78"; 178 reg = <0x0 0x600>; 179 clocks = <&cpufreq_hw 1>; 180 enable-method = "psci"; 181 next-level-cache = <&l2_600>; 182 qcom,freq-domain = <&cpufreq_hw 1>; 183 power-domains = <&cpu_pd6>; 184 power-domain-names = "psci"; 185 #cooling-cells = <2>; 186 l2_600: l2-cache { 187 compatible = "cache"; 188 cache-level = <2>; 189 cache-unified; 190 next-level-cache = <&l3_0>; 191 }; 192 }; 193 194 cpu7: cpu@700 { 195 device_type = "cpu"; 196 compatible = "arm,cortex-x1"; 197 reg = <0x0 0x700>; 198 clocks = <&cpufreq_hw 2>; 199 enable-method = "psci"; 200 next-level-cache = <&l2_700>; 201 qcom,freq-domain = <&cpufreq_hw 2>; 202 power-domains = <&cpu_pd7>; 203 power-domain-names = "psci"; 204 #cooling-cells = <2>; 205 l2_700: l2-cache { 206 compatible = "cache"; 207 cache-level = <2>; 208 cache-unified; 209 next-level-cache = <&l3_0>; 210 }; 211 }; 212 213 cpu-map { 214 cluster0 { 215 core0 { 216 cpu = <&cpu0>; 217 }; 218 219 core1 { 220 cpu = <&cpu1>; 221 }; 222 223 core2 { 224 cpu = <&cpu2>; 225 }; 226 227 core3 { 228 cpu = <&cpu3>; 229 }; 230 231 core4 { 232 cpu = <&cpu4>; 233 }; 234 235 core5 { 236 cpu = <&cpu5>; 237 }; 238 239 core6 { 240 cpu = <&cpu6>; 241 }; 242 243 core7 { 244 cpu = <&cpu7>; 245 }; 246 }; 247 }; 248 249 idle-states { 250 entry-method = "psci"; 251 252 little_cpu_sleep_0: cpu-sleep-0-0 { 253 compatible = "arm,idle-state"; 254 idle-state-name = "silver-rail-power-collapse"; 255 arm,psci-suspend-param = <0x40000004>; 256 entry-latency-us = <360>; 257 exit-latency-us = <531>; 258 min-residency-us = <3934>; 259 local-timer-stop; 260 }; 261 262 big_cpu_sleep_0: cpu-sleep-1-0 { 263 compatible = "arm,idle-state"; 264 idle-state-name = "gold-rail-power-collapse"; 265 arm,psci-suspend-param = <0x40000004>; 266 entry-latency-us = <702>; 267 exit-latency-us = <1061>; 268 min-residency-us = <4488>; 269 local-timer-stop; 270 }; 271 }; 272 273 domain-idle-states { 274 cluster_sleep_apss_off: cluster-sleep-0 { 275 compatible = "domain-idle-state"; 276 arm,psci-suspend-param = <0x41000044>; 277 entry-latency-us = <2752>; 278 exit-latency-us = <3048>; 279 min-residency-us = <6118>; 280 }; 281 282 cluster_sleep_aoss_sleep: cluster-sleep-1 { 283 compatible = "domain-idle-state"; 284 arm,psci-suspend-param = <0x4100c344>; 285 entry-latency-us = <3263>; 286 exit-latency-us = <6562>; 287 min-residency-us = <9987>; 288 }; 289 }; 290 }; 291 292 firmware { 293 scm: scm { 294 compatible = "qcom,scm-sm8350", "qcom,scm"; 295 qcom,dload-mode = <&tcsr 0x13000>; 296 #reset-cells = <1>; 297 }; 298 }; 299 300 memory@80000000 { 301 device_type = "memory"; 302 /* We expect the bootloader to fill in the size */ 303 reg = <0x0 0x80000000 0x0 0x0>; 304 }; 305 306 pmu-a55 { 307 compatible = "arm,cortex-a55-pmu"; 308 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 309 }; 310 311 pmu-a78 { 312 compatible = "arm,cortex-a78-pmu"; 313 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 314 }; 315 316 pmu-x1 { 317 compatible = "arm,cortex-x1-pmu"; 318 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 319 }; 320 321 psci { 322 compatible = "arm,psci-1.0"; 323 method = "smc"; 324 325 cpu_pd0: power-domain-cpu0 { 326 #power-domain-cells = <0>; 327 power-domains = <&cluster_pd>; 328 domain-idle-states = <&little_cpu_sleep_0>; 329 }; 330 331 cpu_pd1: power-domain-cpu1 { 332 #power-domain-cells = <0>; 333 power-domains = <&cluster_pd>; 334 domain-idle-states = <&little_cpu_sleep_0>; 335 }; 336 337 cpu_pd2: power-domain-cpu2 { 338 #power-domain-cells = <0>; 339 power-domains = <&cluster_pd>; 340 domain-idle-states = <&little_cpu_sleep_0>; 341 }; 342 343 cpu_pd3: power-domain-cpu3 { 344 #power-domain-cells = <0>; 345 power-domains = <&cluster_pd>; 346 domain-idle-states = <&little_cpu_sleep_0>; 347 }; 348 349 cpu_pd4: power-domain-cpu4 { 350 #power-domain-cells = <0>; 351 power-domains = <&cluster_pd>; 352 domain-idle-states = <&big_cpu_sleep_0>; 353 }; 354 355 cpu_pd5: power-domain-cpu5 { 356 #power-domain-cells = <0>; 357 power-domains = <&cluster_pd>; 358 domain-idle-states = <&big_cpu_sleep_0>; 359 }; 360 361 cpu_pd6: power-domain-cpu6 { 362 #power-domain-cells = <0>; 363 power-domains = <&cluster_pd>; 364 domain-idle-states = <&big_cpu_sleep_0>; 365 }; 366 367 cpu_pd7: power-domain-cpu7 { 368 #power-domain-cells = <0>; 369 power-domains = <&cluster_pd>; 370 domain-idle-states = <&big_cpu_sleep_0>; 371 }; 372 373 cluster_pd: power-domain-cpu-cluster0 { 374 #power-domain-cells = <0>; 375 domain-idle-states = <&cluster_sleep_apss_off &cluster_sleep_aoss_sleep>; 376 }; 377 }; 378 379 qup_opp_table_100mhz: opp-table-qup100mhz { 380 compatible = "operating-points-v2"; 381 382 opp-50000000 { 383 opp-hz = /bits/ 64 <50000000>; 384 required-opps = <&rpmhpd_opp_min_svs>; 385 }; 386 387 opp-75000000 { 388 opp-hz = /bits/ 64 <75000000>; 389 required-opps = <&rpmhpd_opp_low_svs>; 390 }; 391 392 opp-100000000 { 393 opp-hz = /bits/ 64 <100000000>; 394 required-opps = <&rpmhpd_opp_svs>; 395 }; 396 }; 397 398 qup_opp_table_120mhz: opp-table-qup120mhz { 399 compatible = "operating-points-v2"; 400 401 opp-50000000 { 402 opp-hz = /bits/ 64 <50000000>; 403 required-opps = <&rpmhpd_opp_min_svs>; 404 }; 405 406 opp-75000000 { 407 opp-hz = /bits/ 64 <75000000>; 408 required-opps = <&rpmhpd_opp_low_svs>; 409 }; 410 411 opp-120000000 { 412 opp-hz = /bits/ 64 <120000000>; 413 required-opps = <&rpmhpd_opp_svs>; 414 }; 415 }; 416 417 reserved_memory: reserved-memory { 418 #address-cells = <2>; 419 #size-cells = <2>; 420 ranges; 421 422 hyp_mem: memory@80000000 { 423 reg = <0x0 0x80000000 0x0 0x600000>; 424 no-map; 425 }; 426 427 xbl_aop_mem: memory@80700000 { 428 no-map; 429 reg = <0x0 0x80700000 0x0 0x160000>; 430 }; 431 432 cmd_db: memory@80860000 { 433 compatible = "qcom,cmd-db"; 434 reg = <0x0 0x80860000 0x0 0x20000>; 435 no-map; 436 }; 437 438 reserved_xbl_uefi_log: memory@80880000 { 439 reg = <0x0 0x80880000 0x0 0x14000>; 440 no-map; 441 }; 442 443 smem@80900000 { 444 compatible = "qcom,smem"; 445 reg = <0x0 0x80900000 0x0 0x200000>; 446 hwlocks = <&tcsr_mutex 3>; 447 no-map; 448 }; 449 450 cpucp_fw_mem: memory@80b00000 { 451 reg = <0x0 0x80b00000 0x0 0x100000>; 452 no-map; 453 }; 454 455 cdsp_secure_heap: memory@80c00000 { 456 reg = <0x0 0x80c00000 0x0 0x4600000>; 457 no-map; 458 }; 459 460 pil_camera_mem: memory@85200000 { 461 reg = <0x0 0x85200000 0x0 0x500000>; 462 no-map; 463 }; 464 465 pil_video_mem: memory@85700000 { 466 reg = <0x0 0x85700000 0x0 0x500000>; 467 no-map; 468 }; 469 470 pil_cvp_mem: memory@85c00000 { 471 reg = <0x0 0x85c00000 0x0 0x500000>; 472 no-map; 473 }; 474 475 pil_adsp_mem: memory@86100000 { 476 reg = <0x0 0x86100000 0x0 0x2100000>; 477 no-map; 478 }; 479 480 pil_slpi_mem: memory@88200000 { 481 reg = <0x0 0x88200000 0x0 0x1500000>; 482 no-map; 483 }; 484 485 pil_cdsp_mem: memory@89700000 { 486 reg = <0x0 0x89700000 0x0 0x1e00000>; 487 no-map; 488 }; 489 490 pil_ipa_fw_mem: memory@8b500000 { 491 reg = <0x0 0x8b500000 0x0 0x10000>; 492 no-map; 493 }; 494 495 pil_ipa_gsi_mem: memory@8b510000 { 496 reg = <0x0 0x8b510000 0x0 0xa000>; 497 no-map; 498 }; 499 500 pil_gpu_mem: memory@8b51a000 { 501 reg = <0x0 0x8b51a000 0x0 0x2000>; 502 no-map; 503 }; 504 505 pil_spss_mem: memory@8b600000 { 506 reg = <0x0 0x8b600000 0x0 0x100000>; 507 no-map; 508 }; 509 510 pil_modem_mem: memory@8b800000 { 511 reg = <0x0 0x8b800000 0x0 0x10000000>; 512 no-map; 513 }; 514 515 rmtfs_mem: memory@9b800000 { 516 compatible = "qcom,rmtfs-mem"; 517 reg = <0x0 0x9b800000 0x0 0x280000>; 518 no-map; 519 520 qcom,client-id = <1>; 521 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 522 }; 523 524 hyp_reserved_mem: memory@d0000000 { 525 reg = <0x0 0xd0000000 0x0 0x800000>; 526 no-map; 527 }; 528 529 pil_trustedvm_mem: memory@d0800000 { 530 reg = <0x0 0xd0800000 0x0 0x76f7000>; 531 no-map; 532 }; 533 534 qrtr_shbuf: memory@d7ef7000 { 535 reg = <0x0 0xd7ef7000 0x0 0x9000>; 536 no-map; 537 }; 538 539 chan0_shbuf: memory@d7f00000 { 540 reg = <0x0 0xd7f00000 0x0 0x80000>; 541 no-map; 542 }; 543 544 chan1_shbuf: memory@d7f80000 { 545 reg = <0x0 0xd7f80000 0x0 0x80000>; 546 no-map; 547 }; 548 549 removed_mem: memory@d8800000 { 550 reg = <0x0 0xd8800000 0x0 0x6800000>; 551 no-map; 552 }; 553 }; 554 555 smp2p-adsp { 556 compatible = "qcom,smp2p"; 557 qcom,smem = <443>, <429>; 558 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 559 IPCC_MPROC_SIGNAL_SMP2P 560 IRQ_TYPE_EDGE_RISING>; 561 mboxes = <&ipcc IPCC_CLIENT_LPASS 562 IPCC_MPROC_SIGNAL_SMP2P>; 563 564 qcom,local-pid = <0>; 565 qcom,remote-pid = <2>; 566 567 smp2p_adsp_out: master-kernel { 568 qcom,entry-name = "master-kernel"; 569 #qcom,smem-state-cells = <1>; 570 }; 571 572 smp2p_adsp_in: slave-kernel { 573 qcom,entry-name = "slave-kernel"; 574 interrupt-controller; 575 #interrupt-cells = <2>; 576 }; 577 }; 578 579 smp2p-cdsp { 580 compatible = "qcom,smp2p"; 581 qcom,smem = <94>, <432>; 582 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 583 IPCC_MPROC_SIGNAL_SMP2P 584 IRQ_TYPE_EDGE_RISING>; 585 mboxes = <&ipcc IPCC_CLIENT_CDSP 586 IPCC_MPROC_SIGNAL_SMP2P>; 587 588 qcom,local-pid = <0>; 589 qcom,remote-pid = <5>; 590 591 smp2p_cdsp_out: master-kernel { 592 qcom,entry-name = "master-kernel"; 593 #qcom,smem-state-cells = <1>; 594 }; 595 596 smp2p_cdsp_in: slave-kernel { 597 qcom,entry-name = "slave-kernel"; 598 interrupt-controller; 599 #interrupt-cells = <2>; 600 }; 601 }; 602 603 smp2p-modem { 604 compatible = "qcom,smp2p"; 605 qcom,smem = <435>, <428>; 606 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 607 IPCC_MPROC_SIGNAL_SMP2P 608 IRQ_TYPE_EDGE_RISING>; 609 mboxes = <&ipcc IPCC_CLIENT_MPSS 610 IPCC_MPROC_SIGNAL_SMP2P>; 611 612 qcom,local-pid = <0>; 613 qcom,remote-pid = <1>; 614 615 smp2p_modem_out: master-kernel { 616 qcom,entry-name = "master-kernel"; 617 #qcom,smem-state-cells = <1>; 618 }; 619 620 smp2p_modem_in: slave-kernel { 621 qcom,entry-name = "slave-kernel"; 622 interrupt-controller; 623 #interrupt-cells = <2>; 624 }; 625 626 ipa_smp2p_out: ipa-ap-to-modem { 627 qcom,entry-name = "ipa"; 628 #qcom,smem-state-cells = <1>; 629 }; 630 631 ipa_smp2p_in: ipa-modem-to-ap { 632 qcom,entry-name = "ipa"; 633 interrupt-controller; 634 #interrupt-cells = <2>; 635 }; 636 }; 637 638 smp2p-slpi { 639 compatible = "qcom,smp2p"; 640 qcom,smem = <481>, <430>; 641 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 642 IPCC_MPROC_SIGNAL_SMP2P 643 IRQ_TYPE_EDGE_RISING>; 644 mboxes = <&ipcc IPCC_CLIENT_SLPI 645 IPCC_MPROC_SIGNAL_SMP2P>; 646 647 qcom,local-pid = <0>; 648 qcom,remote-pid = <3>; 649 650 smp2p_slpi_out: master-kernel { 651 qcom,entry-name = "master-kernel"; 652 #qcom,smem-state-cells = <1>; 653 }; 654 655 smp2p_slpi_in: slave-kernel { 656 qcom,entry-name = "slave-kernel"; 657 interrupt-controller; 658 #interrupt-cells = <2>; 659 }; 660 }; 661 662 soc: soc@0 { 663 #address-cells = <2>; 664 #size-cells = <2>; 665 ranges = <0 0 0 0 0x10 0>; 666 dma-ranges = <0 0 0 0 0x10 0>; 667 compatible = "simple-bus"; 668 669 gcc: clock-controller@100000 { 670 compatible = "qcom,gcc-sm8350"; 671 reg = <0x0 0x00100000 0x0 0x1f0000>; 672 #clock-cells = <1>; 673 #reset-cells = <1>; 674 #power-domain-cells = <1>; 675 clock-names = "bi_tcxo", 676 "sleep_clk", 677 "pcie_0_pipe_clk", 678 "pcie_1_pipe_clk", 679 "ufs_card_rx_symbol_0_clk", 680 "ufs_card_rx_symbol_1_clk", 681 "ufs_card_tx_symbol_0_clk", 682 "ufs_phy_rx_symbol_0_clk", 683 "ufs_phy_rx_symbol_1_clk", 684 "ufs_phy_tx_symbol_0_clk", 685 "usb3_phy_wrapper_gcc_usb30_pipe_clk", 686 "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; 687 clocks = <&rpmhcc RPMH_CXO_CLK>, 688 <&sleep_clk>, 689 <&pcie0_phy>, 690 <&pcie1_phy>, 691 <0>, 692 <0>, 693 <0>, 694 <&ufs_mem_phy 0>, 695 <&ufs_mem_phy 1>, 696 <&ufs_mem_phy 2>, 697 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 698 <0>; 699 }; 700 701 ipcc: mailbox@408000 { 702 compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; 703 reg = <0 0x00408000 0 0x1000>; 704 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 705 interrupt-controller; 706 #interrupt-cells = <3>; 707 #mbox-cells = <2>; 708 }; 709 710 gpi_dma2: dma-controller@800000 { 711 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 712 reg = <0 0x00800000 0 0x60000>; 713 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 725 dma-channels = <12>; 726 dma-channel-mask = <0xff>; 727 iommus = <&apps_smmu 0x5f6 0x0>; 728 #dma-cells = <3>; 729 status = "disabled"; 730 }; 731 732 qupv3_id_2: geniqup@8c0000 { 733 compatible = "qcom,geni-se-qup"; 734 reg = <0x0 0x008c0000 0x0 0x6000>; 735 clock-names = "m-ahb", "s-ahb"; 736 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 737 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 738 iommus = <&apps_smmu 0x5e3 0x0>; 739 #address-cells = <2>; 740 #size-cells = <2>; 741 ranges; 742 status = "disabled"; 743 744 i2c14: i2c@880000 { 745 compatible = "qcom,geni-i2c"; 746 reg = <0 0x00880000 0 0x4000>; 747 clock-names = "se"; 748 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 749 pinctrl-names = "default"; 750 pinctrl-0 = <&qup_i2c14_default>; 751 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 752 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 753 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 754 dma-names = "tx", "rx"; 755 #address-cells = <1>; 756 #size-cells = <0>; 757 status = "disabled"; 758 }; 759 760 spi14: spi@880000 { 761 compatible = "qcom,geni-spi"; 762 reg = <0 0x00880000 0 0x4000>; 763 clock-names = "se"; 764 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 765 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 766 power-domains = <&rpmhpd RPMHPD_CX>; 767 operating-points-v2 = <&qup_opp_table_120mhz>; 768 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 769 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 770 dma-names = "tx", "rx"; 771 #address-cells = <1>; 772 #size-cells = <0>; 773 status = "disabled"; 774 }; 775 776 i2c15: i2c@884000 { 777 compatible = "qcom,geni-i2c"; 778 reg = <0 0x00884000 0 0x4000>; 779 clock-names = "se"; 780 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 781 pinctrl-names = "default"; 782 pinctrl-0 = <&qup_i2c15_default>; 783 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 784 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 785 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 786 dma-names = "tx", "rx"; 787 #address-cells = <1>; 788 #size-cells = <0>; 789 status = "disabled"; 790 }; 791 792 spi15: spi@884000 { 793 compatible = "qcom,geni-spi"; 794 reg = <0 0x00884000 0 0x4000>; 795 clock-names = "se"; 796 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 797 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 798 power-domains = <&rpmhpd RPMHPD_CX>; 799 operating-points-v2 = <&qup_opp_table_120mhz>; 800 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 801 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 802 dma-names = "tx", "rx"; 803 #address-cells = <1>; 804 #size-cells = <0>; 805 status = "disabled"; 806 }; 807 808 i2c16: i2c@888000 { 809 compatible = "qcom,geni-i2c"; 810 reg = <0 0x00888000 0 0x4000>; 811 clock-names = "se"; 812 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 813 pinctrl-names = "default"; 814 pinctrl-0 = <&qup_i2c16_default>; 815 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 816 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 817 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 818 dma-names = "tx", "rx"; 819 #address-cells = <1>; 820 #size-cells = <0>; 821 status = "disabled"; 822 }; 823 824 spi16: spi@888000 { 825 compatible = "qcom,geni-spi"; 826 reg = <0 0x00888000 0 0x4000>; 827 clock-names = "se"; 828 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 829 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 830 power-domains = <&rpmhpd RPMHPD_CX>; 831 operating-points-v2 = <&qup_opp_table_100mhz>; 832 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 833 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 834 dma-names = "tx", "rx"; 835 #address-cells = <1>; 836 #size-cells = <0>; 837 status = "disabled"; 838 }; 839 840 i2c17: i2c@88c000 { 841 compatible = "qcom,geni-i2c"; 842 reg = <0 0x0088c000 0 0x4000>; 843 clock-names = "se"; 844 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 845 pinctrl-names = "default"; 846 pinctrl-0 = <&qup_i2c17_default>; 847 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 848 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 849 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 850 dma-names = "tx", "rx"; 851 #address-cells = <1>; 852 #size-cells = <0>; 853 status = "disabled"; 854 }; 855 856 spi17: spi@88c000 { 857 compatible = "qcom,geni-spi"; 858 reg = <0 0x0088c000 0 0x4000>; 859 clock-names = "se"; 860 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 861 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 862 power-domains = <&rpmhpd RPMHPD_CX>; 863 operating-points-v2 = <&qup_opp_table_100mhz>; 864 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 865 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 866 dma-names = "tx", "rx"; 867 #address-cells = <1>; 868 #size-cells = <0>; 869 status = "disabled"; 870 }; 871 872 /* QUP no. 18 seems to be strictly SPI/UART-only */ 873 874 spi18: spi@890000 { 875 compatible = "qcom,geni-spi"; 876 reg = <0 0x00890000 0 0x4000>; 877 clock-names = "se"; 878 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 879 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 880 power-domains = <&rpmhpd RPMHPD_CX>; 881 operating-points-v2 = <&qup_opp_table_100mhz>; 882 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 883 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 884 dma-names = "tx", "rx"; 885 #address-cells = <1>; 886 #size-cells = <0>; 887 status = "disabled"; 888 }; 889 890 uart18: serial@890000 { 891 compatible = "qcom,geni-uart"; 892 reg = <0 0x00890000 0 0x4000>; 893 clock-names = "se"; 894 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 895 pinctrl-names = "default"; 896 pinctrl-0 = <&qup_uart18_default>; 897 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 898 power-domains = <&rpmhpd RPMHPD_CX>; 899 operating-points-v2 = <&qup_opp_table_100mhz>; 900 status = "disabled"; 901 }; 902 903 i2c19: i2c@894000 { 904 compatible = "qcom,geni-i2c"; 905 reg = <0 0x00894000 0 0x4000>; 906 clock-names = "se"; 907 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 908 pinctrl-names = "default"; 909 pinctrl-0 = <&qup_i2c19_default>; 910 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 911 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 912 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 913 dma-names = "tx", "rx"; 914 #address-cells = <1>; 915 #size-cells = <0>; 916 status = "disabled"; 917 }; 918 919 spi19: spi@894000 { 920 compatible = "qcom,geni-spi"; 921 reg = <0 0x00894000 0 0x4000>; 922 clock-names = "se"; 923 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 924 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 925 power-domains = <&rpmhpd RPMHPD_CX>; 926 operating-points-v2 = <&qup_opp_table_100mhz>; 927 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 928 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 929 dma-names = "tx", "rx"; 930 #address-cells = <1>; 931 #size-cells = <0>; 932 status = "disabled"; 933 }; 934 }; 935 936 gpi_dma0: dma-controller@900000 { 937 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 938 reg = <0 0x00900000 0 0x60000>; 939 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 951 dma-channels = <12>; 952 dma-channel-mask = <0x7e>; 953 iommus = <&apps_smmu 0x5b6 0x0>; 954 #dma-cells = <3>; 955 status = "disabled"; 956 }; 957 958 qupv3_id_0: geniqup@9c0000 { 959 compatible = "qcom,geni-se-qup"; 960 reg = <0x0 0x009c0000 0x0 0x6000>; 961 clock-names = "m-ahb", "s-ahb"; 962 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 963 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 964 iommus = <&apps_smmu 0x5a3 0>; 965 #address-cells = <2>; 966 #size-cells = <2>; 967 ranges; 968 status = "disabled"; 969 970 i2c0: i2c@980000 { 971 compatible = "qcom,geni-i2c"; 972 reg = <0 0x00980000 0 0x4000>; 973 clock-names = "se"; 974 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 975 pinctrl-names = "default"; 976 pinctrl-0 = <&qup_i2c0_default>; 977 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 978 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 979 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 980 dma-names = "tx", "rx"; 981 #address-cells = <1>; 982 #size-cells = <0>; 983 status = "disabled"; 984 }; 985 986 spi0: spi@980000 { 987 compatible = "qcom,geni-spi"; 988 reg = <0 0x00980000 0 0x4000>; 989 clock-names = "se"; 990 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 991 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 992 power-domains = <&rpmhpd RPMHPD_CX>; 993 operating-points-v2 = <&qup_opp_table_100mhz>; 994 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 995 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 996 dma-names = "tx", "rx"; 997 #address-cells = <1>; 998 #size-cells = <0>; 999 status = "disabled"; 1000 }; 1001 1002 i2c1: i2c@984000 { 1003 compatible = "qcom,geni-i2c"; 1004 reg = <0 0x00984000 0 0x4000>; 1005 clock-names = "se"; 1006 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1007 pinctrl-names = "default"; 1008 pinctrl-0 = <&qup_i2c1_default>; 1009 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1010 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1011 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1012 dma-names = "tx", "rx"; 1013 #address-cells = <1>; 1014 #size-cells = <0>; 1015 status = "disabled"; 1016 }; 1017 1018 spi1: spi@984000 { 1019 compatible = "qcom,geni-spi"; 1020 reg = <0 0x00984000 0 0x4000>; 1021 clock-names = "se"; 1022 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1023 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1024 power-domains = <&rpmhpd RPMHPD_CX>; 1025 operating-points-v2 = <&qup_opp_table_100mhz>; 1026 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1027 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1028 dma-names = "tx", "rx"; 1029 #address-cells = <1>; 1030 #size-cells = <0>; 1031 status = "disabled"; 1032 }; 1033 1034 i2c2: i2c@988000 { 1035 compatible = "qcom,geni-i2c"; 1036 reg = <0 0x00988000 0 0x4000>; 1037 clock-names = "se"; 1038 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1039 pinctrl-names = "default"; 1040 pinctrl-0 = <&qup_i2c2_default>; 1041 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1042 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1043 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1044 dma-names = "tx", "rx"; 1045 #address-cells = <1>; 1046 #size-cells = <0>; 1047 status = "disabled"; 1048 }; 1049 1050 spi2: spi@988000 { 1051 compatible = "qcom,geni-spi"; 1052 reg = <0 0x00988000 0 0x4000>; 1053 clock-names = "se"; 1054 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1055 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1056 power-domains = <&rpmhpd RPMHPD_CX>; 1057 operating-points-v2 = <&qup_opp_table_100mhz>; 1058 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1059 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1060 dma-names = "tx", "rx"; 1061 #address-cells = <1>; 1062 #size-cells = <0>; 1063 status = "disabled"; 1064 }; 1065 1066 uart2: serial@98c000 { 1067 compatible = "qcom,geni-debug-uart"; 1068 reg = <0 0x0098c000 0 0x4000>; 1069 clock-names = "se"; 1070 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1071 pinctrl-names = "default"; 1072 pinctrl-0 = <&qup_uart3_default_state>; 1073 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1074 power-domains = <&rpmhpd RPMHPD_CX>; 1075 operating-points-v2 = <&qup_opp_table_100mhz>; 1076 status = "disabled"; 1077 }; 1078 1079 /* QUP no. 3 seems to be strictly SPI-only */ 1080 1081 spi3: spi@98c000 { 1082 compatible = "qcom,geni-spi"; 1083 reg = <0 0x0098c000 0 0x4000>; 1084 clock-names = "se"; 1085 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1086 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1087 power-domains = <&rpmhpd RPMHPD_CX>; 1088 operating-points-v2 = <&qup_opp_table_100mhz>; 1089 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1090 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1091 dma-names = "tx", "rx"; 1092 #address-cells = <1>; 1093 #size-cells = <0>; 1094 status = "disabled"; 1095 }; 1096 1097 i2c4: i2c@990000 { 1098 compatible = "qcom,geni-i2c"; 1099 reg = <0 0x00990000 0 0x4000>; 1100 clock-names = "se"; 1101 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1102 pinctrl-names = "default"; 1103 pinctrl-0 = <&qup_i2c4_default>; 1104 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1105 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1106 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1107 dma-names = "tx", "rx"; 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 status = "disabled"; 1111 }; 1112 1113 spi4: spi@990000 { 1114 compatible = "qcom,geni-spi"; 1115 reg = <0 0x00990000 0 0x4000>; 1116 clock-names = "se"; 1117 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1118 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1119 power-domains = <&rpmhpd RPMHPD_CX>; 1120 operating-points-v2 = <&qup_opp_table_100mhz>; 1121 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1122 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1123 dma-names = "tx", "rx"; 1124 #address-cells = <1>; 1125 #size-cells = <0>; 1126 status = "disabled"; 1127 }; 1128 1129 i2c5: i2c@994000 { 1130 compatible = "qcom,geni-i2c"; 1131 reg = <0 0x00994000 0 0x4000>; 1132 clock-names = "se"; 1133 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1134 pinctrl-names = "default"; 1135 pinctrl-0 = <&qup_i2c5_default>; 1136 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1137 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1138 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1139 dma-names = "tx", "rx"; 1140 #address-cells = <1>; 1141 #size-cells = <0>; 1142 status = "disabled"; 1143 }; 1144 1145 spi5: spi@994000 { 1146 compatible = "qcom,geni-spi"; 1147 reg = <0 0x00994000 0 0x4000>; 1148 clock-names = "se"; 1149 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1150 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1151 power-domains = <&rpmhpd RPMHPD_CX>; 1152 operating-points-v2 = <&qup_opp_table_100mhz>; 1153 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1154 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1155 dma-names = "tx", "rx"; 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 status = "disabled"; 1159 }; 1160 1161 i2c6: i2c@998000 { 1162 compatible = "qcom,geni-i2c"; 1163 reg = <0 0x00998000 0 0x4000>; 1164 clock-names = "se"; 1165 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1166 pinctrl-names = "default"; 1167 pinctrl-0 = <&qup_i2c6_default>; 1168 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1169 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1170 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1171 dma-names = "tx", "rx"; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 status = "disabled"; 1175 }; 1176 1177 spi6: spi@998000 { 1178 compatible = "qcom,geni-spi"; 1179 reg = <0 0x00998000 0 0x4000>; 1180 clock-names = "se"; 1181 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1182 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1183 power-domains = <&rpmhpd RPMHPD_CX>; 1184 operating-points-v2 = <&qup_opp_table_100mhz>; 1185 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1186 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1187 dma-names = "tx", "rx"; 1188 #address-cells = <1>; 1189 #size-cells = <0>; 1190 status = "disabled"; 1191 }; 1192 1193 uart6: serial@998000 { 1194 compatible = "qcom,geni-uart"; 1195 reg = <0 0x00998000 0 0x4000>; 1196 clock-names = "se"; 1197 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1198 pinctrl-names = "default"; 1199 pinctrl-0 = <&qup_uart6_default>; 1200 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1201 power-domains = <&rpmhpd RPMHPD_CX>; 1202 operating-points-v2 = <&qup_opp_table_100mhz>; 1203 status = "disabled"; 1204 }; 1205 1206 i2c7: i2c@99c000 { 1207 compatible = "qcom,geni-i2c"; 1208 reg = <0 0x0099c000 0 0x4000>; 1209 clock-names = "se"; 1210 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1211 pinctrl-names = "default"; 1212 pinctrl-0 = <&qup_i2c7_default>; 1213 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1214 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1215 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1216 dma-names = "tx", "rx"; 1217 #address-cells = <1>; 1218 #size-cells = <0>; 1219 status = "disabled"; 1220 }; 1221 1222 spi7: spi@99c000 { 1223 compatible = "qcom,geni-spi"; 1224 reg = <0 0x0099c000 0 0x4000>; 1225 clock-names = "se"; 1226 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1227 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1228 power-domains = <&rpmhpd RPMHPD_CX>; 1229 operating-points-v2 = <&qup_opp_table_100mhz>; 1230 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1231 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1232 dma-names = "tx", "rx"; 1233 #address-cells = <1>; 1234 #size-cells = <0>; 1235 status = "disabled"; 1236 }; 1237 }; 1238 1239 gpi_dma1: dma-controller@a00000 { 1240 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 1241 reg = <0 0x00a00000 0 0x60000>; 1242 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1254 dma-channels = <12>; 1255 dma-channel-mask = <0xff>; 1256 iommus = <&apps_smmu 0x56 0x0>; 1257 #dma-cells = <3>; 1258 status = "disabled"; 1259 }; 1260 1261 qupv3_id_1: geniqup@ac0000 { 1262 compatible = "qcom,geni-se-qup"; 1263 reg = <0x0 0x00ac0000 0x0 0x6000>; 1264 clock-names = "m-ahb", "s-ahb"; 1265 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1266 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1267 iommus = <&apps_smmu 0x43 0>; 1268 #address-cells = <2>; 1269 #size-cells = <2>; 1270 ranges; 1271 status = "disabled"; 1272 1273 i2c8: i2c@a80000 { 1274 compatible = "qcom,geni-i2c"; 1275 reg = <0 0x00a80000 0 0x4000>; 1276 clock-names = "se"; 1277 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1278 pinctrl-names = "default"; 1279 pinctrl-0 = <&qup_i2c8_default>; 1280 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1281 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1282 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1283 dma-names = "tx", "rx"; 1284 #address-cells = <1>; 1285 #size-cells = <0>; 1286 status = "disabled"; 1287 }; 1288 1289 spi8: spi@a80000 { 1290 compatible = "qcom,geni-spi"; 1291 reg = <0 0x00a80000 0 0x4000>; 1292 clock-names = "se"; 1293 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1294 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1295 power-domains = <&rpmhpd RPMHPD_CX>; 1296 operating-points-v2 = <&qup_opp_table_120mhz>; 1297 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1298 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1299 dma-names = "tx", "rx"; 1300 #address-cells = <1>; 1301 #size-cells = <0>; 1302 status = "disabled"; 1303 }; 1304 1305 i2c9: i2c@a84000 { 1306 compatible = "qcom,geni-i2c"; 1307 reg = <0 0x00a84000 0 0x4000>; 1308 clock-names = "se"; 1309 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1310 pinctrl-names = "default"; 1311 pinctrl-0 = <&qup_i2c9_default>; 1312 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1313 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1314 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1315 dma-names = "tx", "rx"; 1316 #address-cells = <1>; 1317 #size-cells = <0>; 1318 status = "disabled"; 1319 }; 1320 1321 spi9: spi@a84000 { 1322 compatible = "qcom,geni-spi"; 1323 reg = <0 0x00a84000 0 0x4000>; 1324 clock-names = "se"; 1325 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1326 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1327 power-domains = <&rpmhpd RPMHPD_CX>; 1328 operating-points-v2 = <&qup_opp_table_100mhz>; 1329 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1330 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1331 dma-names = "tx", "rx"; 1332 #address-cells = <1>; 1333 #size-cells = <0>; 1334 status = "disabled"; 1335 }; 1336 1337 i2c10: i2c@a88000 { 1338 compatible = "qcom,geni-i2c"; 1339 reg = <0 0x00a88000 0 0x4000>; 1340 clock-names = "se"; 1341 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1342 pinctrl-names = "default"; 1343 pinctrl-0 = <&qup_i2c10_default>; 1344 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1345 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1346 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1347 dma-names = "tx", "rx"; 1348 #address-cells = <1>; 1349 #size-cells = <0>; 1350 status = "disabled"; 1351 }; 1352 1353 spi10: spi@a88000 { 1354 compatible = "qcom,geni-spi"; 1355 reg = <0 0x00a88000 0 0x4000>; 1356 clock-names = "se"; 1357 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1358 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1359 power-domains = <&rpmhpd RPMHPD_CX>; 1360 operating-points-v2 = <&qup_opp_table_100mhz>; 1361 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1362 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1363 dma-names = "tx", "rx"; 1364 #address-cells = <1>; 1365 #size-cells = <0>; 1366 status = "disabled"; 1367 }; 1368 1369 i2c11: i2c@a8c000 { 1370 compatible = "qcom,geni-i2c"; 1371 reg = <0 0x00a8c000 0 0x4000>; 1372 clock-names = "se"; 1373 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1374 pinctrl-names = "default"; 1375 pinctrl-0 = <&qup_i2c11_default>; 1376 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1377 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1378 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1379 dma-names = "tx", "rx"; 1380 #address-cells = <1>; 1381 #size-cells = <0>; 1382 status = "disabled"; 1383 }; 1384 1385 spi11: spi@a8c000 { 1386 compatible = "qcom,geni-spi"; 1387 reg = <0 0x00a8c000 0 0x4000>; 1388 clock-names = "se"; 1389 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1390 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1391 power-domains = <&rpmhpd RPMHPD_CX>; 1392 operating-points-v2 = <&qup_opp_table_100mhz>; 1393 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1394 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1395 dma-names = "tx", "rx"; 1396 #address-cells = <1>; 1397 #size-cells = <0>; 1398 status = "disabled"; 1399 }; 1400 1401 i2c12: i2c@a90000 { 1402 compatible = "qcom,geni-i2c"; 1403 reg = <0 0x00a90000 0 0x4000>; 1404 clock-names = "se"; 1405 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1406 pinctrl-names = "default"; 1407 pinctrl-0 = <&qup_i2c12_default>; 1408 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1409 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1410 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1411 dma-names = "tx", "rx"; 1412 #address-cells = <1>; 1413 #size-cells = <0>; 1414 status = "disabled"; 1415 }; 1416 1417 spi12: spi@a90000 { 1418 compatible = "qcom,geni-spi"; 1419 reg = <0 0x00a90000 0 0x4000>; 1420 clock-names = "se"; 1421 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1422 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1423 power-domains = <&rpmhpd RPMHPD_CX>; 1424 operating-points-v2 = <&qup_opp_table_100mhz>; 1425 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1426 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1427 dma-names = "tx", "rx"; 1428 #address-cells = <1>; 1429 #size-cells = <0>; 1430 status = "disabled"; 1431 }; 1432 1433 i2c13: i2c@a94000 { 1434 compatible = "qcom,geni-i2c"; 1435 reg = <0 0x00a94000 0 0x4000>; 1436 clock-names = "se"; 1437 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1438 pinctrl-names = "default"; 1439 pinctrl-0 = <&qup_i2c13_default>; 1440 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1441 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1442 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1443 dma-names = "tx", "rx"; 1444 #address-cells = <1>; 1445 #size-cells = <0>; 1446 status = "disabled"; 1447 }; 1448 1449 spi13: spi@a94000 { 1450 compatible = "qcom,geni-spi"; 1451 reg = <0 0x00a94000 0 0x4000>; 1452 clock-names = "se"; 1453 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1454 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1455 power-domains = <&rpmhpd RPMHPD_CX>; 1456 operating-points-v2 = <&qup_opp_table_100mhz>; 1457 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1458 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1459 dma-names = "tx", "rx"; 1460 #address-cells = <1>; 1461 #size-cells = <0>; 1462 status = "disabled"; 1463 }; 1464 }; 1465 1466 rng: rng@10d3000 { 1467 compatible = "qcom,prng-ee"; 1468 reg = <0 0x010d3000 0 0x1000>; 1469 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1470 clock-names = "core"; 1471 }; 1472 1473 config_noc: interconnect@1500000 { 1474 compatible = "qcom,sm8350-config-noc"; 1475 reg = <0 0x01500000 0 0xa580>; 1476 #interconnect-cells = <2>; 1477 qcom,bcm-voters = <&apps_bcm_voter>; 1478 }; 1479 1480 mc_virt: interconnect@1580000 { 1481 compatible = "qcom,sm8350-mc-virt"; 1482 reg = <0 0x01580000 0 0x1000>; 1483 #interconnect-cells = <2>; 1484 qcom,bcm-voters = <&apps_bcm_voter>; 1485 }; 1486 1487 system_noc: interconnect@1680000 { 1488 compatible = "qcom,sm8350-system-noc"; 1489 reg = <0 0x01680000 0 0x1c200>; 1490 #interconnect-cells = <2>; 1491 qcom,bcm-voters = <&apps_bcm_voter>; 1492 }; 1493 1494 aggre1_noc: interconnect@16e0000 { 1495 compatible = "qcom,sm8350-aggre1-noc"; 1496 reg = <0 0x016e0000 0 0x1f180>; 1497 #interconnect-cells = <2>; 1498 qcom,bcm-voters = <&apps_bcm_voter>; 1499 }; 1500 1501 aggre2_noc: interconnect@1700000 { 1502 compatible = "qcom,sm8350-aggre2-noc"; 1503 reg = <0 0x01700000 0 0x33000>; 1504 #interconnect-cells = <2>; 1505 qcom,bcm-voters = <&apps_bcm_voter>; 1506 }; 1507 1508 mmss_noc: interconnect@1740000 { 1509 compatible = "qcom,sm8350-mmss-noc"; 1510 reg = <0 0x01740000 0 0x1f080>; 1511 #interconnect-cells = <2>; 1512 qcom,bcm-voters = <&apps_bcm_voter>; 1513 }; 1514 1515 pcie0: pcie@1c00000 { 1516 compatible = "qcom,pcie-sm8350"; 1517 reg = <0 0x01c00000 0 0x3000>, 1518 <0 0x60000000 0 0xf1d>, 1519 <0 0x60000f20 0 0xa8>, 1520 <0 0x60001000 0 0x1000>, 1521 <0 0x60100000 0 0x100000>; 1522 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1523 device_type = "pci"; 1524 linux,pci-domain = <0>; 1525 bus-range = <0x00 0xff>; 1526 num-lanes = <1>; 1527 1528 #address-cells = <3>; 1529 #size-cells = <2>; 1530 1531 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1532 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1533 1534 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1540 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1541 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1542 interrupt-names = "msi0", 1543 "msi1", 1544 "msi2", 1545 "msi3", 1546 "msi4", 1547 "msi5", 1548 "msi6", 1549 "msi7"; 1550 #interrupt-cells = <1>; 1551 interrupt-map-mask = <0 0 0 0x7>; 1552 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1553 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1554 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1555 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1556 1557 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1558 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1559 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1560 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1561 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1562 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1563 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1564 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1565 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; 1566 clock-names = "aux", 1567 "cfg", 1568 "bus_master", 1569 "bus_slave", 1570 "slave_q2a", 1571 "tbu", 1572 "ddrss_sf_tbu", 1573 "aggre1", 1574 "aggre0"; 1575 1576 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1577 <0x100 &apps_smmu 0x1c01 0x1>; 1578 1579 resets = <&gcc GCC_PCIE_0_BCR>; 1580 reset-names = "pci"; 1581 1582 power-domains = <&gcc PCIE_0_GDSC>; 1583 1584 phys = <&pcie0_phy>; 1585 phy-names = "pciephy"; 1586 1587 status = "disabled"; 1588 1589 pcie@0 { 1590 device_type = "pci"; 1591 reg = <0x0 0x0 0x0 0x0 0x0>; 1592 bus-range = <0x01 0xff>; 1593 1594 #address-cells = <3>; 1595 #size-cells = <2>; 1596 ranges; 1597 }; 1598 }; 1599 1600 pcie0_phy: phy@1c06000 { 1601 compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy"; 1602 reg = <0 0x01c06000 0 0x2000>; 1603 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1604 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1605 <&gcc GCC_PCIE_0_CLKREF_EN>, 1606 <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, 1607 <&gcc GCC_PCIE_0_PIPE_CLK>; 1608 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1609 1610 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1611 reset-names = "phy"; 1612 1613 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>; 1614 assigned-clock-rates = <100000000>; 1615 1616 #clock-cells = <0>; 1617 clock-output-names = "pcie_0_pipe_clk"; 1618 1619 #phy-cells = <0>; 1620 1621 status = "disabled"; 1622 }; 1623 1624 pcie1: pcie@1c08000 { 1625 compatible = "qcom,pcie-sm8350"; 1626 reg = <0 0x01c08000 0 0x3000>, 1627 <0 0x40000000 0 0xf1d>, 1628 <0 0x40000f20 0 0xa8>, 1629 <0 0x40001000 0 0x1000>, 1630 <0 0x40100000 0 0x100000>; 1631 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1632 device_type = "pci"; 1633 linux,pci-domain = <1>; 1634 bus-range = <0x00 0xff>; 1635 num-lanes = <2>; 1636 1637 #address-cells = <3>; 1638 #size-cells = <2>; 1639 1640 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1641 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1642 1643 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1644 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1645 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1647 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1648 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1649 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 1650 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1651 interrupt-names = "msi0", 1652 "msi1", 1653 "msi2", 1654 "msi3", 1655 "msi4", 1656 "msi5", 1657 "msi6", 1658 "msi7"; 1659 #interrupt-cells = <1>; 1660 interrupt-map-mask = <0 0 0 0x7>; 1661 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1662 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1663 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1664 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1665 1666 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1667 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1668 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1669 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1670 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1671 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1672 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1673 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1674 clock-names = "aux", 1675 "cfg", 1676 "bus_master", 1677 "bus_slave", 1678 "slave_q2a", 1679 "tbu", 1680 "ddrss_sf_tbu", 1681 "aggre1"; 1682 1683 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1684 <0x100 &apps_smmu 0x1c81 0x1>; 1685 1686 resets = <&gcc GCC_PCIE_1_BCR>; 1687 reset-names = "pci"; 1688 1689 power-domains = <&gcc PCIE_1_GDSC>; 1690 1691 phys = <&pcie1_phy>; 1692 phy-names = "pciephy"; 1693 1694 status = "disabled"; 1695 1696 pcie@0 { 1697 device_type = "pci"; 1698 reg = <0x0 0x0 0x0 0x0 0x0>; 1699 bus-range = <0x01 0xff>; 1700 1701 #address-cells = <3>; 1702 #size-cells = <2>; 1703 ranges; 1704 }; 1705 }; 1706 1707 pcie1_phy: phy@1c0e000 { 1708 compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy"; 1709 reg = <0 0x01c0e000 0 0x2000>; 1710 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1711 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1712 <&gcc GCC_PCIE_1_CLKREF_EN>, 1713 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, 1714 <&gcc GCC_PCIE_1_PIPE_CLK>; 1715 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1716 1717 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1718 reset-names = "phy"; 1719 1720 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1721 assigned-clock-rates = <100000000>; 1722 1723 #clock-cells = <0>; 1724 clock-output-names = "pcie_1_pipe_clk"; 1725 1726 #phy-cells = <0>; 1727 1728 status = "disabled"; 1729 }; 1730 1731 ufs_mem_hc: ufshc@1d84000 { 1732 compatible = "qcom,sm8350-ufshc", "qcom,ufshc", 1733 "jedec,ufs-2.0"; 1734 reg = <0 0x01d84000 0 0x3000>; 1735 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1736 phys = <&ufs_mem_phy>; 1737 phy-names = "ufsphy"; 1738 lanes-per-direction = <2>; 1739 #reset-cells = <1>; 1740 resets = <&gcc GCC_UFS_PHY_BCR>; 1741 reset-names = "rst"; 1742 1743 power-domains = <&gcc UFS_PHY_GDSC>; 1744 1745 iommus = <&apps_smmu 0xe0 0x0>; 1746 dma-coherent; 1747 1748 clock-names = 1749 "core_clk", 1750 "bus_aggr_clk", 1751 "iface_clk", 1752 "core_clk_unipro", 1753 "ref_clk", 1754 "tx_lane0_sync_clk", 1755 "rx_lane0_sync_clk", 1756 "rx_lane1_sync_clk"; 1757 clocks = 1758 <&gcc GCC_UFS_PHY_AXI_CLK>, 1759 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1760 <&gcc GCC_UFS_PHY_AHB_CLK>, 1761 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1762 <&rpmhcc RPMH_CXO_CLK>, 1763 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1764 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1765 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1766 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 1767 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1768 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1769 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 1770 interconnect-names = "ufs-ddr", "cpu-ufs"; 1771 freq-table-hz = 1772 <75000000 300000000>, 1773 <0 0>, 1774 <0 0>, 1775 <75000000 300000000>, 1776 <0 0>, 1777 <0 0>, 1778 <0 0>, 1779 <0 0>; 1780 status = "disabled"; 1781 }; 1782 1783 ufs_mem_phy: phy@1d87000 { 1784 compatible = "qcom,sm8350-qmp-ufs-phy"; 1785 reg = <0 0x01d87000 0 0x1000>; 1786 1787 clocks = <&rpmhcc RPMH_CXO_CLK>, 1788 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1789 <&gcc GCC_UFS_1_CLKREF_EN>; 1790 clock-names = "ref", 1791 "ref_aux", 1792 "qref"; 1793 1794 power-domains = <&gcc UFS_PHY_GDSC>; 1795 1796 resets = <&ufs_mem_hc 0>; 1797 reset-names = "ufsphy"; 1798 1799 #clock-cells = <1>; 1800 #phy-cells = <0>; 1801 1802 status = "disabled"; 1803 }; 1804 1805 cryptobam: dma-controller@1dc4000 { 1806 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1807 reg = <0 0x01dc4000 0 0x24000>; 1808 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1809 #dma-cells = <1>; 1810 qcom,ee = <0>; 1811 qcom,num-ees = <4>; 1812 num-channels = <16>; 1813 qcom,controlled-remotely; 1814 iommus = <&apps_smmu 0x594 0x0011>, 1815 <&apps_smmu 0x596 0x0011>; 1816 }; 1817 1818 crypto: crypto@1dfa000 { 1819 compatible = "qcom,sm8350-qce", "qcom,sm8150-qce", "qcom,qce"; 1820 reg = <0 0x01dfa000 0 0x6000>; 1821 dmas = <&cryptobam 4>, <&cryptobam 5>; 1822 dma-names = "rx", "tx"; 1823 iommus = <&apps_smmu 0x594 0x0011>, 1824 <&apps_smmu 0x596 0x0011>; 1825 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 1826 interconnect-names = "memory"; 1827 }; 1828 1829 ipa: ipa@1e40000 { 1830 compatible = "qcom,sm8350-ipa"; 1831 1832 iommus = <&apps_smmu 0x5c0 0x0>, 1833 <&apps_smmu 0x5c2 0x0>; 1834 reg = <0 0x01e40000 0 0x8000>, 1835 <0 0x01e50000 0 0x4b20>, 1836 <0 0x01e04000 0 0x23000>; 1837 reg-names = "ipa-reg", 1838 "ipa-shared", 1839 "gsi"; 1840 1841 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, 1842 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1843 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1844 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1845 interrupt-names = "ipa", 1846 "gsi", 1847 "ipa-clock-query", 1848 "ipa-setup-ready"; 1849 1850 clocks = <&rpmhcc RPMH_IPA_CLK>; 1851 clock-names = "core"; 1852 1853 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1854 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1855 interconnect-names = "memory", 1856 "config"; 1857 1858 qcom,qmp = <&aoss_qmp>; 1859 1860 qcom,smem-states = <&ipa_smp2p_out 0>, 1861 <&ipa_smp2p_out 1>; 1862 qcom,smem-state-names = "ipa-clock-enabled-valid", 1863 "ipa-clock-enabled"; 1864 1865 status = "disabled"; 1866 }; 1867 1868 tcsr_mutex: hwlock@1f40000 { 1869 compatible = "qcom,tcsr-mutex"; 1870 reg = <0x0 0x01f40000 0x0 0x40000>; 1871 #hwlock-cells = <1>; 1872 }; 1873 1874 tcsr: syscon@1fc0000 { 1875 compatible = "qcom,sm8350-tcsr", "syscon"; 1876 reg = <0x0 0x1fc0000 0x0 0x30000>; 1877 }; 1878 1879 adsp: remoteproc@3000000 { 1880 compatible = "qcom,sm8350-adsp-pas"; 1881 reg = <0x0 0x03000000 0x0 0x10000>; 1882 1883 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 1884 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1885 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1886 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1887 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1888 interrupt-names = "wdog", "fatal", "ready", 1889 "handover", "stop-ack"; 1890 1891 clocks = <&rpmhcc RPMH_CXO_CLK>; 1892 clock-names = "xo"; 1893 1894 power-domains = <&rpmhpd RPMHPD_LCX>, 1895 <&rpmhpd RPMHPD_LMX>; 1896 power-domain-names = "lcx", "lmx"; 1897 1898 memory-region = <&pil_adsp_mem>; 1899 1900 qcom,qmp = <&aoss_qmp>; 1901 1902 qcom,smem-states = <&smp2p_adsp_out 0>; 1903 qcom,smem-state-names = "stop"; 1904 1905 status = "disabled"; 1906 1907 glink-edge { 1908 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1909 IPCC_MPROC_SIGNAL_GLINK_QMP 1910 IRQ_TYPE_EDGE_RISING>; 1911 mboxes = <&ipcc IPCC_CLIENT_LPASS 1912 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1913 1914 label = "lpass"; 1915 qcom,remote-pid = <2>; 1916 1917 apr { 1918 compatible = "qcom,apr-v2"; 1919 qcom,glink-channels = "apr_audio_svc"; 1920 qcom,domain = <APR_DOMAIN_ADSP>; 1921 #address-cells = <1>; 1922 #size-cells = <0>; 1923 1924 service@3 { 1925 reg = <APR_SVC_ADSP_CORE>; 1926 compatible = "qcom,q6core"; 1927 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1928 }; 1929 1930 q6afe: service@4 { 1931 compatible = "qcom,q6afe"; 1932 reg = <APR_SVC_AFE>; 1933 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1934 1935 q6afedai: dais { 1936 compatible = "qcom,q6afe-dais"; 1937 #address-cells = <1>; 1938 #size-cells = <0>; 1939 #sound-dai-cells = <1>; 1940 }; 1941 1942 q6afecc: clock-controller { 1943 compatible = "qcom,q6afe-clocks"; 1944 #clock-cells = <2>; 1945 }; 1946 }; 1947 1948 q6asm: service@7 { 1949 compatible = "qcom,q6asm"; 1950 reg = <APR_SVC_ASM>; 1951 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1952 1953 q6asmdai: dais { 1954 compatible = "qcom,q6asm-dais"; 1955 #address-cells = <1>; 1956 #size-cells = <0>; 1957 #sound-dai-cells = <1>; 1958 iommus = <&apps_smmu 0x1801 0x0>; 1959 1960 dai@0 { 1961 reg = <MSM_FRONTEND_DAI_MULTIMEDIA1>; 1962 }; 1963 1964 dai@1 { 1965 reg = <MSM_FRONTEND_DAI_MULTIMEDIA2>; 1966 }; 1967 1968 dai@2 { 1969 reg = <MSM_FRONTEND_DAI_MULTIMEDIA3>; 1970 }; 1971 }; 1972 }; 1973 1974 q6adm: service@8 { 1975 compatible = "qcom,q6adm"; 1976 reg = <APR_SVC_ADM>; 1977 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1978 1979 q6routing: routing { 1980 compatible = "qcom,q6adm-routing"; 1981 #sound-dai-cells = <0>; 1982 }; 1983 }; 1984 }; 1985 1986 fastrpc { 1987 compatible = "qcom,fastrpc"; 1988 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1989 label = "adsp"; 1990 qcom,non-secure-domain; 1991 #address-cells = <1>; 1992 #size-cells = <0>; 1993 1994 compute-cb@3 { 1995 compatible = "qcom,fastrpc-compute-cb"; 1996 reg = <3>; 1997 iommus = <&apps_smmu 0x1803 0x0>; 1998 }; 1999 2000 compute-cb@4 { 2001 compatible = "qcom,fastrpc-compute-cb"; 2002 reg = <4>; 2003 iommus = <&apps_smmu 0x1804 0x0>; 2004 }; 2005 2006 compute-cb@5 { 2007 compatible = "qcom,fastrpc-compute-cb"; 2008 reg = <5>; 2009 iommus = <&apps_smmu 0x1805 0x0>; 2010 }; 2011 }; 2012 }; 2013 }; 2014 2015 lpass_tlmm: pinctrl@33c0000 { 2016 compatible = "qcom,sm8350-lpass-lpi-pinctrl"; 2017 reg = <0 0x033c0000 0 0x20000>, 2018 <0 0x03550000 0 0x10000>; 2019 2020 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2021 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2022 clock-names = "core", "audio"; 2023 2024 gpio-controller; 2025 #gpio-cells = <2>; 2026 gpio-ranges = <&lpass_tlmm 0 0 15>; 2027 }; 2028 2029 gpu: gpu@3d00000 { 2030 compatible = "qcom,adreno-660.1", "qcom,adreno"; 2031 2032 reg = <0 0x03d00000 0 0x40000>, 2033 <0 0x03d9e000 0 0x1000>, 2034 <0 0x03d61000 0 0x800>; 2035 reg-names = "kgsl_3d0_reg_memory", 2036 "cx_mem", 2037 "cx_dbgc"; 2038 2039 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2040 2041 iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>; 2042 2043 operating-points-v2 = <&gpu_opp_table>; 2044 2045 qcom,gmu = <&gmu>; 2046 #cooling-cells = <2>; 2047 2048 status = "disabled"; 2049 2050 zap-shader { 2051 memory-region = <&pil_gpu_mem>; 2052 }; 2053 2054 /* note: downstream checks gpu binning for 670 Mhz */ 2055 gpu_opp_table: opp-table { 2056 compatible = "operating-points-v2"; 2057 2058 opp-840000000 { 2059 opp-hz = /bits/ 64 <840000000>; 2060 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2061 }; 2062 2063 opp-778000000 { 2064 opp-hz = /bits/ 64 <778000000>; 2065 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2066 }; 2067 2068 opp-738000000 { 2069 opp-hz = /bits/ 64 <738000000>; 2070 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2071 }; 2072 2073 opp-676000000 { 2074 opp-hz = /bits/ 64 <676000000>; 2075 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2076 }; 2077 2078 opp-608000000 { 2079 opp-hz = /bits/ 64 <608000000>; 2080 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2081 }; 2082 2083 opp-540000000 { 2084 opp-hz = /bits/ 64 <540000000>; 2085 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2086 }; 2087 2088 opp-491000000 { 2089 opp-hz = /bits/ 64 <491000000>; 2090 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2091 }; 2092 2093 opp-443000000 { 2094 opp-hz = /bits/ 64 <443000000>; 2095 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2096 }; 2097 2098 opp-379000000 { 2099 opp-hz = /bits/ 64 <379000000>; 2100 opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>; 2101 }; 2102 2103 opp-315000000 { 2104 opp-hz = /bits/ 64 <315000000>; 2105 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2106 }; 2107 }; 2108 }; 2109 2110 gmu: gmu@3d6a000 { 2111 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu"; 2112 2113 reg = <0 0x03d6a000 0 0x34000>, 2114 <0 0x03de0000 0 0x10000>, 2115 <0 0x0b290000 0 0x10000>; 2116 reg-names = "gmu", "rscc", "gmu_pdc"; 2117 2118 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2119 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2120 interrupt-names = "hfi", "gmu"; 2121 2122 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2123 <&gpucc GPU_CC_CXO_CLK>, 2124 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2125 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2126 <&gpucc GPU_CC_AHB_CLK>, 2127 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2128 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2129 clock-names = "gmu", 2130 "cxo", 2131 "axi", 2132 "memnoc", 2133 "ahb", 2134 "hub", 2135 "smmu_vote"; 2136 2137 power-domains = <&gpucc GPU_CX_GDSC>, 2138 <&gpucc GPU_GX_GDSC>; 2139 power-domain-names = "cx", 2140 "gx"; 2141 2142 iommus = <&adreno_smmu 5 0x400>; 2143 2144 operating-points-v2 = <&gmu_opp_table>; 2145 2146 gmu_opp_table: opp-table { 2147 compatible = "operating-points-v2"; 2148 2149 opp-200000000 { 2150 opp-hz = /bits/ 64 <200000000>; 2151 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2152 }; 2153 }; 2154 }; 2155 2156 gpucc: clock-controller@3d90000 { 2157 compatible = "qcom,sm8350-gpucc"; 2158 reg = <0 0x03d90000 0 0x9000>; 2159 clocks = <&rpmhcc RPMH_CXO_CLK>, 2160 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2161 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2162 clock-names = "bi_tcxo", 2163 "gcc_gpu_gpll0_clk_src", 2164 "gcc_gpu_gpll0_div_clk_src"; 2165 #clock-cells = <1>; 2166 #reset-cells = <1>; 2167 #power-domain-cells = <1>; 2168 }; 2169 2170 adreno_smmu: iommu@3da0000 { 2171 compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu", 2172 "qcom,smmu-500", "arm,mmu-500"; 2173 reg = <0 0x03da0000 0 0x20000>; 2174 #iommu-cells = <2>; 2175 #global-interrupts = <2>; 2176 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2177 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2178 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2179 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2180 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2181 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2182 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2183 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2184 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2185 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2186 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2187 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2188 2189 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2190 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2191 <&gpucc GPU_CC_AHB_CLK>, 2192 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2193 <&gpucc GPU_CC_CX_GMU_CLK>, 2194 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2195 <&gpucc GPU_CC_HUB_AON_CLK>; 2196 clock-names = "bus", 2197 "iface", 2198 "ahb", 2199 "hlos1_vote_gpu_smmu", 2200 "cx_gmu", 2201 "hub_cx_int", 2202 "hub_aon"; 2203 2204 power-domains = <&gpucc GPU_CX_GDSC>; 2205 dma-coherent; 2206 }; 2207 2208 lpass_ag_noc: interconnect@3c40000 { 2209 compatible = "qcom,sm8350-lpass-ag-noc"; 2210 reg = <0 0x03c40000 0 0xf080>; 2211 #interconnect-cells = <2>; 2212 qcom,bcm-voters = <&apps_bcm_voter>; 2213 }; 2214 2215 mpss: remoteproc@4080000 { 2216 compatible = "qcom,sm8350-mpss-pas"; 2217 reg = <0x0 0x04080000 0x0 0x10000>; 2218 2219 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2220 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2221 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2222 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2223 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2224 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2225 interrupt-names = "wdog", "fatal", "ready", "handover", 2226 "stop-ack", "shutdown-ack"; 2227 2228 clocks = <&rpmhcc RPMH_CXO_CLK>; 2229 clock-names = "xo"; 2230 2231 power-domains = <&rpmhpd RPMHPD_CX>, 2232 <&rpmhpd RPMHPD_MSS>; 2233 power-domain-names = "cx", "mss"; 2234 2235 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2236 2237 memory-region = <&pil_modem_mem>; 2238 2239 qcom,qmp = <&aoss_qmp>; 2240 2241 qcom,smem-states = <&smp2p_modem_out 0>; 2242 qcom,smem-state-names = "stop"; 2243 2244 status = "disabled"; 2245 2246 glink-edge { 2247 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2248 IPCC_MPROC_SIGNAL_GLINK_QMP 2249 IRQ_TYPE_EDGE_RISING>; 2250 mboxes = <&ipcc IPCC_CLIENT_MPSS 2251 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2252 label = "modem"; 2253 qcom,remote-pid = <1>; 2254 }; 2255 }; 2256 2257 slpi: remoteproc@5c00000 { 2258 compatible = "qcom,sm8350-slpi-pas"; 2259 reg = <0 0x05c00000 0 0x4000>; 2260 2261 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2262 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2263 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2264 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2265 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2266 interrupt-names = "wdog", "fatal", "ready", 2267 "handover", "stop-ack"; 2268 2269 clocks = <&rpmhcc RPMH_CXO_CLK>; 2270 clock-names = "xo"; 2271 2272 power-domains = <&rpmhpd RPMHPD_LCX>, 2273 <&rpmhpd RPMHPD_LMX>; 2274 power-domain-names = "lcx", "lmx"; 2275 2276 memory-region = <&pil_slpi_mem>; 2277 2278 qcom,qmp = <&aoss_qmp>; 2279 2280 qcom,smem-states = <&smp2p_slpi_out 0>; 2281 qcom,smem-state-names = "stop"; 2282 2283 status = "disabled"; 2284 2285 glink-edge { 2286 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2287 IPCC_MPROC_SIGNAL_GLINK_QMP 2288 IRQ_TYPE_EDGE_RISING>; 2289 mboxes = <&ipcc IPCC_CLIENT_SLPI 2290 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2291 2292 label = "slpi"; 2293 qcom,remote-pid = <3>; 2294 2295 fastrpc { 2296 compatible = "qcom,fastrpc"; 2297 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2298 label = "sdsp"; 2299 qcom,non-secure-domain; 2300 #address-cells = <1>; 2301 #size-cells = <0>; 2302 2303 compute-cb@1 { 2304 compatible = "qcom,fastrpc-compute-cb"; 2305 reg = <1>; 2306 iommus = <&apps_smmu 0x0541 0x0>; 2307 }; 2308 2309 compute-cb@2 { 2310 compatible = "qcom,fastrpc-compute-cb"; 2311 reg = <2>; 2312 iommus = <&apps_smmu 0x0542 0x0>; 2313 }; 2314 2315 compute-cb@3 { 2316 compatible = "qcom,fastrpc-compute-cb"; 2317 reg = <3>; 2318 iommus = <&apps_smmu 0x0543 0x0>; 2319 /* note: shared-cb = <4> in downstream */ 2320 }; 2321 }; 2322 }; 2323 }; 2324 2325 sdhc_2: mmc@8804000 { 2326 compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5"; 2327 reg = <0 0x08804000 0 0x1000>; 2328 2329 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2330 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2331 interrupt-names = "hc_irq", "pwr_irq"; 2332 2333 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2334 <&gcc GCC_SDCC2_APPS_CLK>, 2335 <&rpmhcc RPMH_CXO_CLK>; 2336 clock-names = "iface", "core", "xo"; 2337 resets = <&gcc GCC_SDCC2_BCR>; 2338 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2339 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2340 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2341 iommus = <&apps_smmu 0x4a0 0x0>; 2342 power-domains = <&rpmhpd RPMHPD_CX>; 2343 operating-points-v2 = <&sdhc2_opp_table>; 2344 bus-width = <4>; 2345 dma-coherent; 2346 2347 status = "disabled"; 2348 2349 sdhc2_opp_table: opp-table { 2350 compatible = "operating-points-v2"; 2351 2352 opp-100000000 { 2353 opp-hz = /bits/ 64 <100000000>; 2354 required-opps = <&rpmhpd_opp_low_svs>; 2355 }; 2356 2357 opp-202000000 { 2358 opp-hz = /bits/ 64 <202000000>; 2359 required-opps = <&rpmhpd_opp_svs_l1>; 2360 }; 2361 }; 2362 }; 2363 2364 usb_1_hsphy: phy@88e3000 { 2365 compatible = "qcom,sm8350-usb-hs-phy", 2366 "qcom,usb-snps-hs-7nm-phy"; 2367 reg = <0 0x088e3000 0 0x400>; 2368 status = "disabled"; 2369 #phy-cells = <0>; 2370 2371 clocks = <&rpmhcc RPMH_CXO_CLK>; 2372 clock-names = "ref"; 2373 2374 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2375 }; 2376 2377 usb_2_hsphy: phy@88e4000 { 2378 compatible = "qcom,sm8250-usb-hs-phy", 2379 "qcom,usb-snps-hs-7nm-phy"; 2380 reg = <0 0x088e4000 0 0x400>; 2381 status = "disabled"; 2382 #phy-cells = <0>; 2383 2384 clocks = <&rpmhcc RPMH_CXO_CLK>; 2385 clock-names = "ref"; 2386 2387 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2388 }; 2389 2390 refgen: regulator@88e7000 { 2391 compatible = "qcom,sm8350-refgen-regulator", 2392 "qcom,sm8250-refgen-regulator"; 2393 reg = <0x0 0x088e7000 0x0 0x84>; 2394 }; 2395 2396 usb_1_qmpphy: phy@88e8000 { 2397 compatible = "qcom,sm8350-qmp-usb3-dp-phy"; 2398 reg = <0 0x088e8000 0 0x3000>; 2399 2400 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2401 <&rpmhcc RPMH_CXO_CLK>, 2402 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2403 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2404 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2405 2406 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2407 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2408 reset-names = "phy", "common"; 2409 2410 #clock-cells = <1>; 2411 #phy-cells = <1>; 2412 2413 orientation-switch; 2414 2415 status = "disabled"; 2416 2417 ports { 2418 #address-cells = <1>; 2419 #size-cells = <0>; 2420 2421 port@0 { 2422 reg = <0>; 2423 2424 usb_1_qmpphy_out: endpoint { 2425 }; 2426 }; 2427 2428 port@1 { 2429 reg = <1>; 2430 2431 usb_1_qmpphy_usb_ss_in: endpoint { 2432 remote-endpoint = <&usb_1_dwc3_ss>; 2433 }; 2434 }; 2435 2436 port@2 { 2437 reg = <2>; 2438 2439 usb_1_qmpphy_dp_in: endpoint { 2440 remote-endpoint = <&mdss_dp_out>; 2441 }; 2442 }; 2443 }; 2444 }; 2445 2446 usb_2_qmpphy: phy@88eb000 { 2447 compatible = "qcom,sm8350-qmp-usb3-uni-phy"; 2448 reg = <0 0x088eb000 0 0x2000>; 2449 status = "disabled"; 2450 2451 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2452 <&gcc GCC_USB3_SEC_CLKREF_EN>, 2453 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2454 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2455 clock-names = "aux", 2456 "ref", 2457 "com_aux", 2458 "pipe"; 2459 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2460 #clock-cells = <0>; 2461 #phy-cells = <0>; 2462 2463 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2464 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 2465 reset-names = "phy", 2466 "phy_phy"; 2467 }; 2468 2469 dc_noc: interconnect@90c0000 { 2470 compatible = "qcom,sm8350-dc-noc"; 2471 reg = <0 0x090c0000 0 0x4200>; 2472 #interconnect-cells = <2>; 2473 qcom,bcm-voters = <&apps_bcm_voter>; 2474 }; 2475 2476 gem_noc: interconnect@9100000 { 2477 compatible = "qcom,sm8350-gem-noc"; 2478 reg = <0 0x09100000 0 0xb4000>; 2479 #interconnect-cells = <2>; 2480 qcom,bcm-voters = <&apps_bcm_voter>; 2481 }; 2482 2483 system-cache-controller@9200000 { 2484 compatible = "qcom,sm8350-llcc"; 2485 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 2486 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 2487 <0 0x09600000 0 0x58000>; 2488 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2489 "llcc3_base", "llcc_broadcast_base"; 2490 }; 2491 2492 compute_noc: interconnect@a0c0000 { 2493 compatible = "qcom,sm8350-compute-noc"; 2494 reg = <0 0x0a0c0000 0 0xa180>; 2495 #interconnect-cells = <2>; 2496 qcom,bcm-voters = <&apps_bcm_voter>; 2497 }; 2498 2499 cdsp: remoteproc@a300000 { 2500 compatible = "qcom,sm8350-cdsp-pas"; 2501 reg = <0x0 0x0a300000 0x0 0x10000>; 2502 2503 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2504 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2505 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2506 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2507 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 2508 interrupt-names = "wdog", "fatal", "ready", 2509 "handover", "stop-ack"; 2510 2511 clocks = <&rpmhcc RPMH_CXO_CLK>; 2512 clock-names = "xo"; 2513 2514 power-domains = <&rpmhpd RPMHPD_CX>, 2515 <&rpmhpd RPMHPD_MXC>; 2516 power-domain-names = "cx", "mxc"; 2517 2518 interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 2519 2520 memory-region = <&pil_cdsp_mem>; 2521 2522 qcom,qmp = <&aoss_qmp>; 2523 2524 qcom,smem-states = <&smp2p_cdsp_out 0>; 2525 qcom,smem-state-names = "stop"; 2526 2527 status = "disabled"; 2528 2529 glink-edge { 2530 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2531 IPCC_MPROC_SIGNAL_GLINK_QMP 2532 IRQ_TYPE_EDGE_RISING>; 2533 mboxes = <&ipcc IPCC_CLIENT_CDSP 2534 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2535 2536 label = "cdsp"; 2537 qcom,remote-pid = <5>; 2538 2539 fastrpc { 2540 compatible = "qcom,fastrpc"; 2541 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2542 label = "cdsp"; 2543 qcom,non-secure-domain; 2544 #address-cells = <1>; 2545 #size-cells = <0>; 2546 2547 compute-cb@1 { 2548 compatible = "qcom,fastrpc-compute-cb"; 2549 reg = <1>; 2550 iommus = <&apps_smmu 0x2161 0x0400>, 2551 <&apps_smmu 0x1181 0x0420>; 2552 }; 2553 2554 compute-cb@2 { 2555 compatible = "qcom,fastrpc-compute-cb"; 2556 reg = <2>; 2557 iommus = <&apps_smmu 0x2162 0x0400>, 2558 <&apps_smmu 0x1182 0x0420>; 2559 }; 2560 2561 compute-cb@3 { 2562 compatible = "qcom,fastrpc-compute-cb"; 2563 reg = <3>; 2564 iommus = <&apps_smmu 0x2163 0x0400>, 2565 <&apps_smmu 0x1183 0x0420>; 2566 }; 2567 2568 compute-cb@4 { 2569 compatible = "qcom,fastrpc-compute-cb"; 2570 reg = <4>; 2571 iommus = <&apps_smmu 0x2164 0x0400>, 2572 <&apps_smmu 0x1184 0x0420>; 2573 }; 2574 2575 compute-cb@5 { 2576 compatible = "qcom,fastrpc-compute-cb"; 2577 reg = <5>; 2578 iommus = <&apps_smmu 0x2165 0x0400>, 2579 <&apps_smmu 0x1185 0x0420>; 2580 }; 2581 2582 compute-cb@6 { 2583 compatible = "qcom,fastrpc-compute-cb"; 2584 reg = <6>; 2585 iommus = <&apps_smmu 0x2166 0x0400>, 2586 <&apps_smmu 0x1186 0x0420>; 2587 }; 2588 2589 compute-cb@7 { 2590 compatible = "qcom,fastrpc-compute-cb"; 2591 reg = <7>; 2592 iommus = <&apps_smmu 0x2167 0x0400>, 2593 <&apps_smmu 0x1187 0x0420>; 2594 }; 2595 2596 compute-cb@8 { 2597 compatible = "qcom,fastrpc-compute-cb"; 2598 reg = <8>; 2599 iommus = <&apps_smmu 0x2168 0x0400>, 2600 <&apps_smmu 0x1188 0x0420>; 2601 }; 2602 2603 /* note: secure cb9 in downstream */ 2604 }; 2605 }; 2606 }; 2607 2608 usb_1: usb@a6f8800 { 2609 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2610 reg = <0 0x0a6f8800 0 0x400>; 2611 status = "disabled"; 2612 #address-cells = <2>; 2613 #size-cells = <2>; 2614 ranges; 2615 2616 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2617 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2618 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2619 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2620 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 2621 clock-names = "cfg_noc", 2622 "core", 2623 "iface", 2624 "sleep", 2625 "mock_utmi"; 2626 2627 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2628 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2629 assigned-clock-rates = <19200000>, <200000000>; 2630 2631 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2632 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2633 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2634 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2635 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2636 interrupt-names = "pwr_event", 2637 "hs_phy_irq", 2638 "dp_hs_phy_irq", 2639 "dm_hs_phy_irq", 2640 "ss_phy_irq"; 2641 2642 power-domains = <&gcc USB30_PRIM_GDSC>; 2643 2644 resets = <&gcc GCC_USB30_PRIM_BCR>; 2645 2646 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2647 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 2648 interconnect-names = "usb-ddr", "apps-usb"; 2649 2650 usb_1_dwc3: usb@a600000 { 2651 compatible = "snps,dwc3"; 2652 reg = <0 0x0a600000 0 0xcd00>; 2653 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2654 iommus = <&apps_smmu 0x0 0x0>; 2655 snps,dis_u2_susphy_quirk; 2656 snps,dis_u3_susphy_quirk; 2657 snps,dis_enblslpm_quirk; 2658 snps,dis-u1-entry-quirk; 2659 snps,dis-u2-entry-quirk; 2660 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 2661 phy-names = "usb2-phy", "usb3-phy"; 2662 2663 ports { 2664 #address-cells = <1>; 2665 #size-cells = <0>; 2666 2667 port@0 { 2668 reg = <0>; 2669 2670 usb_1_dwc3_hs: endpoint { 2671 }; 2672 }; 2673 2674 port@1 { 2675 reg = <1>; 2676 2677 usb_1_dwc3_ss: endpoint { 2678 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 2679 }; 2680 }; 2681 }; 2682 }; 2683 }; 2684 2685 usb_2: usb@a8f8800 { 2686 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2687 reg = <0 0x0a8f8800 0 0x400>; 2688 status = "disabled"; 2689 #address-cells = <2>; 2690 #size-cells = <2>; 2691 ranges; 2692 2693 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2694 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2695 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2696 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2697 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2698 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2699 clock-names = "cfg_noc", 2700 "core", 2701 "iface", 2702 "sleep", 2703 "mock_utmi", 2704 "xo"; 2705 2706 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2707 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2708 assigned-clock-rates = <19200000>, <200000000>; 2709 2710 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 2711 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2712 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 2713 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 2714 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 2715 interrupt-names = "pwr_event", 2716 "hs_phy_irq", 2717 "dp_hs_phy_irq", 2718 "dm_hs_phy_irq", 2719 "ss_phy_irq"; 2720 2721 power-domains = <&gcc USB30_SEC_GDSC>; 2722 2723 resets = <&gcc GCC_USB30_SEC_BCR>; 2724 2725 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 2726 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 2727 interconnect-names = "usb-ddr", "apps-usb"; 2728 2729 usb_2_dwc3: usb@a800000 { 2730 compatible = "snps,dwc3"; 2731 reg = <0 0x0a800000 0 0xcd00>; 2732 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2733 iommus = <&apps_smmu 0x20 0x0>; 2734 snps,dis_u2_susphy_quirk; 2735 snps,dis_u3_susphy_quirk; 2736 snps,dis_enblslpm_quirk; 2737 snps,dis-u1-entry-quirk; 2738 snps,dis-u2-entry-quirk; 2739 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>; 2740 phy-names = "usb2-phy", "usb3-phy"; 2741 }; 2742 }; 2743 2744 mdss: display-subsystem@ae00000 { 2745 compatible = "qcom,sm8350-mdss"; 2746 reg = <0 0x0ae00000 0 0x1000>; 2747 reg-names = "mdss"; 2748 2749 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 2750 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>, 2751 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2752 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 2753 interconnect-names = "mdp0-mem", 2754 "mdp1-mem", 2755 "cpu-cfg"; 2756 2757 power-domains = <&dispcc MDSS_GDSC>; 2758 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2759 2760 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2761 <&gcc GCC_DISP_HF_AXI_CLK>, 2762 <&gcc GCC_DISP_SF_AXI_CLK>, 2763 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2764 clock-names = "iface", "bus", "nrt_bus", "core"; 2765 2766 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2767 interrupt-controller; 2768 #interrupt-cells = <1>; 2769 2770 iommus = <&apps_smmu 0x820 0x402>; 2771 2772 status = "disabled"; 2773 2774 #address-cells = <2>; 2775 #size-cells = <2>; 2776 ranges; 2777 2778 mdss_mdp: display-controller@ae01000 { 2779 compatible = "qcom,sm8350-dpu"; 2780 reg = <0 0x0ae01000 0 0x8f000>, 2781 <0 0x0aeb0000 0 0x3000>; 2782 reg-names = "mdp", "vbif"; 2783 2784 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2785 <&gcc GCC_DISP_SF_AXI_CLK>, 2786 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2787 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2788 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2789 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2790 clock-names = "bus", 2791 "nrt_bus", 2792 "iface", 2793 "lut", 2794 "core", 2795 "vsync"; 2796 2797 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2798 assigned-clock-rates = <19200000>; 2799 2800 operating-points-v2 = <&dpu_opp_table>; 2801 power-domains = <&rpmhpd RPMHPD_MMCX>; 2802 2803 interrupt-parent = <&mdss>; 2804 interrupts = <0>; 2805 2806 dpu_opp_table: opp-table { 2807 compatible = "operating-points-v2"; 2808 2809 /* TODO: opp-200000000 should work with 2810 * &rpmhpd_opp_low_svs, but one some of 2811 * sm8350_hdk boards reboot using this 2812 * opp. 2813 */ 2814 opp-200000000 { 2815 opp-hz = /bits/ 64 <200000000>; 2816 required-opps = <&rpmhpd_opp_svs>; 2817 }; 2818 2819 opp-300000000 { 2820 opp-hz = /bits/ 64 <300000000>; 2821 required-opps = <&rpmhpd_opp_svs>; 2822 }; 2823 2824 opp-345000000 { 2825 opp-hz = /bits/ 64 <345000000>; 2826 required-opps = <&rpmhpd_opp_svs_l1>; 2827 }; 2828 2829 opp-460000000 { 2830 opp-hz = /bits/ 64 <460000000>; 2831 required-opps = <&rpmhpd_opp_nom>; 2832 }; 2833 }; 2834 2835 ports { 2836 #address-cells = <1>; 2837 #size-cells = <0>; 2838 2839 port@0 { 2840 reg = <0>; 2841 dpu_intf1_out: endpoint { 2842 remote-endpoint = <&mdss_dsi0_in>; 2843 }; 2844 }; 2845 2846 port@1 { 2847 reg = <1>; 2848 dpu_intf2_out: endpoint { 2849 remote-endpoint = <&mdss_dsi1_in>; 2850 }; 2851 }; 2852 2853 port@2 { 2854 reg = <2>; 2855 dpu_intf0_out: endpoint { 2856 remote-endpoint = <&mdss_dp_in>; 2857 }; 2858 }; 2859 }; 2860 }; 2861 2862 mdss_dp: displayport-controller@ae90000 { 2863 compatible = "qcom,sm8350-dp"; 2864 reg = <0 0xae90000 0 0x200>, 2865 <0 0xae90200 0 0x200>, 2866 <0 0xae90400 0 0x600>, 2867 <0 0xae91000 0 0x400>, 2868 <0 0xae91400 0 0x400>; 2869 interrupt-parent = <&mdss>; 2870 interrupts = <12>; 2871 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2872 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 2873 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 2874 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 2875 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 2876 clock-names = "core_iface", 2877 "core_aux", 2878 "ctrl_link", 2879 "ctrl_link_iface", 2880 "stream_pixel"; 2881 2882 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 2883 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 2884 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2885 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2886 2887 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 2888 phy-names = "dp"; 2889 2890 #sound-dai-cells = <0>; 2891 2892 operating-points-v2 = <&dp_opp_table>; 2893 power-domains = <&rpmhpd RPMHPD_MMCX>; 2894 2895 status = "disabled"; 2896 2897 ports { 2898 #address-cells = <1>; 2899 #size-cells = <0>; 2900 2901 port@0 { 2902 reg = <0>; 2903 mdss_dp_in: endpoint { 2904 remote-endpoint = <&dpu_intf0_out>; 2905 }; 2906 }; 2907 2908 port@1 { 2909 reg = <1>; 2910 2911 mdss_dp_out: endpoint { 2912 remote-endpoint = <&usb_1_qmpphy_dp_in>; 2913 }; 2914 }; 2915 }; 2916 2917 dp_opp_table: opp-table { 2918 compatible = "operating-points-v2"; 2919 2920 opp-160000000 { 2921 opp-hz = /bits/ 64 <160000000>; 2922 required-opps = <&rpmhpd_opp_low_svs>; 2923 }; 2924 2925 opp-270000000 { 2926 opp-hz = /bits/ 64 <270000000>; 2927 required-opps = <&rpmhpd_opp_svs>; 2928 }; 2929 2930 opp-540000000 { 2931 opp-hz = /bits/ 64 <540000000>; 2932 required-opps = <&rpmhpd_opp_svs_l1>; 2933 }; 2934 2935 opp-810000000 { 2936 opp-hz = /bits/ 64 <810000000>; 2937 required-opps = <&rpmhpd_opp_nom>; 2938 }; 2939 }; 2940 }; 2941 2942 mdss_dsi0: dsi@ae94000 { 2943 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2944 reg = <0 0x0ae94000 0 0x400>; 2945 reg-names = "dsi_ctrl"; 2946 2947 interrupt-parent = <&mdss>; 2948 interrupts = <4>; 2949 2950 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2951 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2952 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2953 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2954 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2955 <&gcc GCC_DISP_HF_AXI_CLK>; 2956 clock-names = "byte", 2957 "byte_intf", 2958 "pixel", 2959 "core", 2960 "iface", 2961 "bus"; 2962 2963 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2964 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2965 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2966 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 2967 2968 operating-points-v2 = <&dsi0_opp_table>; 2969 power-domains = <&rpmhpd RPMHPD_MMCX>; 2970 refgen-supply = <&refgen>; 2971 2972 phys = <&mdss_dsi0_phy>; 2973 2974 #address-cells = <1>; 2975 #size-cells = <0>; 2976 2977 status = "disabled"; 2978 2979 dsi0_opp_table: opp-table { 2980 compatible = "operating-points-v2"; 2981 2982 /* TODO: opp-187500000 should work with 2983 * &rpmhpd_opp_low_svs, but one some of 2984 * sm8350_hdk boards reboot using this 2985 * opp. 2986 */ 2987 opp-187500000 { 2988 opp-hz = /bits/ 64 <187500000>; 2989 required-opps = <&rpmhpd_opp_svs>; 2990 }; 2991 2992 opp-300000000 { 2993 opp-hz = /bits/ 64 <300000000>; 2994 required-opps = <&rpmhpd_opp_svs>; 2995 }; 2996 2997 opp-358000000 { 2998 opp-hz = /bits/ 64 <358000000>; 2999 required-opps = <&rpmhpd_opp_svs_l1>; 3000 }; 3001 }; 3002 3003 ports { 3004 #address-cells = <1>; 3005 #size-cells = <0>; 3006 3007 port@0 { 3008 reg = <0>; 3009 mdss_dsi0_in: endpoint { 3010 remote-endpoint = <&dpu_intf1_out>; 3011 }; 3012 }; 3013 3014 port@1 { 3015 reg = <1>; 3016 mdss_dsi0_out: endpoint { 3017 }; 3018 }; 3019 }; 3020 }; 3021 3022 mdss_dsi0_phy: phy@ae94400 { 3023 compatible = "qcom,sm8350-dsi-phy-5nm"; 3024 reg = <0 0x0ae94400 0 0x200>, 3025 <0 0x0ae94600 0 0x280>, 3026 <0 0x0ae94900 0 0x27c>; 3027 reg-names = "dsi_phy", 3028 "dsi_phy_lane", 3029 "dsi_pll"; 3030 3031 #clock-cells = <1>; 3032 #phy-cells = <0>; 3033 3034 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3035 <&rpmhcc RPMH_CXO_CLK>; 3036 clock-names = "iface", "ref"; 3037 3038 status = "disabled"; 3039 }; 3040 3041 mdss_dsi1: dsi@ae96000 { 3042 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3043 reg = <0 0x0ae96000 0 0x400>; 3044 reg-names = "dsi_ctrl"; 3045 3046 interrupt-parent = <&mdss>; 3047 interrupts = <5>; 3048 3049 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3050 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3051 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3052 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3053 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3054 <&gcc GCC_DISP_HF_AXI_CLK>; 3055 clock-names = "byte", 3056 "byte_intf", 3057 "pixel", 3058 "core", 3059 "iface", 3060 "bus"; 3061 3062 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 3063 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3064 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 3065 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 3066 3067 operating-points-v2 = <&dsi1_opp_table>; 3068 power-domains = <&rpmhpd RPMHPD_MMCX>; 3069 refgen-supply = <&refgen>; 3070 3071 phys = <&mdss_dsi1_phy>; 3072 3073 #address-cells = <1>; 3074 #size-cells = <0>; 3075 3076 status = "disabled"; 3077 3078 dsi1_opp_table: opp-table { 3079 compatible = "operating-points-v2"; 3080 3081 /* TODO: opp-187500000 should work with 3082 * &rpmhpd_opp_low_svs, but one some of 3083 * sm8350_hdk boards reboot using this 3084 * opp. 3085 */ 3086 opp-187500000 { 3087 opp-hz = /bits/ 64 <187500000>; 3088 required-opps = <&rpmhpd_opp_svs>; 3089 }; 3090 3091 opp-300000000 { 3092 opp-hz = /bits/ 64 <300000000>; 3093 required-opps = <&rpmhpd_opp_svs>; 3094 }; 3095 3096 opp-358000000 { 3097 opp-hz = /bits/ 64 <358000000>; 3098 required-opps = <&rpmhpd_opp_svs_l1>; 3099 }; 3100 }; 3101 3102 ports { 3103 #address-cells = <1>; 3104 #size-cells = <0>; 3105 3106 port@0 { 3107 reg = <0>; 3108 mdss_dsi1_in: endpoint { 3109 remote-endpoint = <&dpu_intf2_out>; 3110 }; 3111 }; 3112 3113 port@1 { 3114 reg = <1>; 3115 mdss_dsi1_out: endpoint { 3116 }; 3117 }; 3118 }; 3119 }; 3120 3121 mdss_dsi1_phy: phy@ae96400 { 3122 compatible = "qcom,sm8350-dsi-phy-5nm"; 3123 reg = <0 0x0ae96400 0 0x200>, 3124 <0 0x0ae96600 0 0x280>, 3125 <0 0x0ae96900 0 0x27c>; 3126 reg-names = "dsi_phy", 3127 "dsi_phy_lane", 3128 "dsi_pll"; 3129 3130 #clock-cells = <1>; 3131 #phy-cells = <0>; 3132 3133 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3134 <&rpmhcc RPMH_CXO_CLK>; 3135 clock-names = "iface", "ref"; 3136 3137 status = "disabled"; 3138 }; 3139 }; 3140 3141 dispcc: clock-controller@af00000 { 3142 compatible = "qcom,sm8350-dispcc"; 3143 reg = <0 0x0af00000 0 0x10000>; 3144 clocks = <&rpmhcc RPMH_CXO_CLK>, 3145 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 3146 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 3147 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 3148 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 3149 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3150 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3151 clock-names = "bi_tcxo", 3152 "dsi0_phy_pll_out_byteclk", 3153 "dsi0_phy_pll_out_dsiclk", 3154 "dsi1_phy_pll_out_byteclk", 3155 "dsi1_phy_pll_out_dsiclk", 3156 "dp_phy_pll_link_clk", 3157 "dp_phy_pll_vco_div_clk"; 3158 #clock-cells = <1>; 3159 #reset-cells = <1>; 3160 #power-domain-cells = <1>; 3161 3162 power-domains = <&rpmhpd RPMHPD_MMCX>; 3163 }; 3164 3165 pdc: interrupt-controller@b220000 { 3166 compatible = "qcom,sm8350-pdc", "qcom,pdc"; 3167 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 3168 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, 3169 <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, 3170 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, 3171 <156 716 12>; 3172 #interrupt-cells = <2>; 3173 interrupt-parent = <&intc>; 3174 interrupt-controller; 3175 }; 3176 3177 tsens0: thermal-sensor@c263000 { 3178 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 3179 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3180 <0 0x0c222000 0 0x8>; /* SROT */ 3181 #qcom,sensors = <15>; 3182 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 3183 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 3184 interrupt-names = "uplow", "critical"; 3185 #thermal-sensor-cells = <1>; 3186 }; 3187 3188 tsens1: thermal-sensor@c265000 { 3189 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 3190 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3191 <0 0x0c223000 0 0x8>; /* SROT */ 3192 #qcom,sensors = <14>; 3193 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 3194 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 3195 interrupt-names = "uplow", "critical"; 3196 #thermal-sensor-cells = <1>; 3197 }; 3198 3199 aoss_qmp: power-management@c300000 { 3200 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; 3201 reg = <0 0x0c300000 0 0x400>; 3202 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 3203 IRQ_TYPE_EDGE_RISING>; 3204 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3205 3206 #clock-cells = <0>; 3207 }; 3208 3209 sram@c3f0000 { 3210 compatible = "qcom,rpmh-stats"; 3211 reg = <0 0x0c3f0000 0 0x400>; 3212 }; 3213 3214 spmi_bus: spmi@c440000 { 3215 compatible = "qcom,spmi-pmic-arb"; 3216 reg = <0x0 0x0c440000 0x0 0x1100>, 3217 <0x0 0x0c600000 0x0 0x2000000>, 3218 <0x0 0x0e600000 0x0 0x100000>, 3219 <0x0 0x0e700000 0x0 0xa0000>, 3220 <0x0 0x0c40a000 0x0 0x26000>; 3221 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3222 interrupt-names = "periph_irq"; 3223 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3224 qcom,ee = <0>; 3225 qcom,channel = <0>; 3226 #address-cells = <2>; 3227 #size-cells = <0>; 3228 interrupt-controller; 3229 #interrupt-cells = <4>; 3230 }; 3231 3232 tlmm: pinctrl@f100000 { 3233 compatible = "qcom,sm8350-tlmm"; 3234 reg = <0 0x0f100000 0 0x300000>; 3235 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3236 gpio-controller; 3237 #gpio-cells = <2>; 3238 interrupt-controller; 3239 #interrupt-cells = <2>; 3240 gpio-ranges = <&tlmm 0 0 204>; 3241 wakeup-parent = <&pdc>; 3242 3243 sdc2_default_state: sdc2-default-state { 3244 clk-pins { 3245 pins = "sdc2_clk"; 3246 drive-strength = <16>; 3247 bias-disable; 3248 }; 3249 3250 cmd-pins { 3251 pins = "sdc2_cmd"; 3252 drive-strength = <16>; 3253 bias-pull-up; 3254 }; 3255 3256 data-pins { 3257 pins = "sdc2_data"; 3258 drive-strength = <16>; 3259 bias-pull-up; 3260 }; 3261 }; 3262 3263 sdc2_sleep_state: sdc2-sleep-state { 3264 clk-pins { 3265 pins = "sdc2_clk"; 3266 drive-strength = <2>; 3267 bias-disable; 3268 }; 3269 3270 cmd-pins { 3271 pins = "sdc2_cmd"; 3272 drive-strength = <2>; 3273 bias-pull-up; 3274 }; 3275 3276 data-pins { 3277 pins = "sdc2_data"; 3278 drive-strength = <2>; 3279 bias-pull-up; 3280 }; 3281 }; 3282 3283 qup_uart3_default_state: qup-uart3-default-state { 3284 rx-pins { 3285 pins = "gpio18"; 3286 function = "qup3"; 3287 }; 3288 tx-pins { 3289 pins = "gpio19"; 3290 function = "qup3"; 3291 }; 3292 }; 3293 3294 qup_uart6_default: qup-uart6-default-state { 3295 pins = "gpio30", "gpio31"; 3296 function = "qup6"; 3297 drive-strength = <2>; 3298 bias-disable; 3299 }; 3300 3301 qup_uart18_default: qup-uart18-default-state { 3302 pins = "gpio68", "gpio69"; 3303 function = "qup18"; 3304 drive-strength = <2>; 3305 bias-disable; 3306 }; 3307 3308 qup_i2c0_default: qup-i2c0-default-state { 3309 pins = "gpio4", "gpio5"; 3310 function = "qup0"; 3311 drive-strength = <2>; 3312 bias-pull-up; 3313 }; 3314 3315 qup_i2c1_default: qup-i2c1-default-state { 3316 pins = "gpio8", "gpio9"; 3317 function = "qup1"; 3318 drive-strength = <2>; 3319 bias-pull-up; 3320 }; 3321 3322 qup_i2c2_default: qup-i2c2-default-state { 3323 pins = "gpio12", "gpio13"; 3324 function = "qup2"; 3325 drive-strength = <2>; 3326 bias-pull-up; 3327 }; 3328 3329 qup_i2c4_default: qup-i2c4-default-state { 3330 pins = "gpio20", "gpio21"; 3331 function = "qup4"; 3332 drive-strength = <2>; 3333 bias-pull-up; 3334 }; 3335 3336 qup_i2c5_default: qup-i2c5-default-state { 3337 pins = "gpio24", "gpio25"; 3338 function = "qup5"; 3339 drive-strength = <2>; 3340 bias-pull-up; 3341 }; 3342 3343 qup_i2c6_default: qup-i2c6-default-state { 3344 pins = "gpio28", "gpio29"; 3345 function = "qup6"; 3346 drive-strength = <2>; 3347 bias-pull-up; 3348 }; 3349 3350 qup_i2c7_default: qup-i2c7-default-state { 3351 pins = "gpio32", "gpio33"; 3352 function = "qup7"; 3353 drive-strength = <2>; 3354 bias-disable; 3355 }; 3356 3357 qup_i2c8_default: qup-i2c8-default-state { 3358 pins = "gpio36", "gpio37"; 3359 function = "qup8"; 3360 drive-strength = <2>; 3361 bias-pull-up; 3362 }; 3363 3364 qup_i2c9_default: qup-i2c9-default-state { 3365 pins = "gpio40", "gpio41"; 3366 function = "qup9"; 3367 drive-strength = <2>; 3368 bias-pull-up; 3369 }; 3370 3371 qup_i2c10_default: qup-i2c10-default-state { 3372 pins = "gpio44", "gpio45"; 3373 function = "qup10"; 3374 drive-strength = <2>; 3375 bias-pull-up; 3376 }; 3377 3378 qup_i2c11_default: qup-i2c11-default-state { 3379 pins = "gpio48", "gpio49"; 3380 function = "qup11"; 3381 drive-strength = <2>; 3382 bias-pull-up; 3383 }; 3384 3385 qup_i2c12_default: qup-i2c12-default-state { 3386 pins = "gpio52", "gpio53"; 3387 function = "qup12"; 3388 drive-strength = <2>; 3389 bias-pull-up; 3390 }; 3391 3392 qup_i2c13_default: qup-i2c13-default-state { 3393 pins = "gpio0", "gpio1"; 3394 function = "qup13"; 3395 drive-strength = <2>; 3396 bias-pull-up; 3397 }; 3398 3399 qup_i2c14_default: qup-i2c14-default-state { 3400 pins = "gpio56", "gpio57"; 3401 function = "qup14"; 3402 drive-strength = <2>; 3403 bias-disable; 3404 }; 3405 3406 qup_i2c15_default: qup-i2c15-default-state { 3407 pins = "gpio60", "gpio61"; 3408 function = "qup15"; 3409 drive-strength = <2>; 3410 bias-disable; 3411 }; 3412 3413 qup_i2c16_default: qup-i2c16-default-state { 3414 pins = "gpio64", "gpio65"; 3415 function = "qup16"; 3416 drive-strength = <2>; 3417 bias-disable; 3418 }; 3419 3420 qup_i2c17_default: qup-i2c17-default-state { 3421 pins = "gpio72", "gpio73"; 3422 function = "qup17"; 3423 drive-strength = <2>; 3424 bias-disable; 3425 }; 3426 3427 qup_i2c19_default: qup-i2c19-default-state { 3428 pins = "gpio76", "gpio77"; 3429 function = "qup19"; 3430 drive-strength = <2>; 3431 bias-disable; 3432 }; 3433 }; 3434 3435 apps_smmu: iommu@15000000 { 3436 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; 3437 reg = <0 0x15000000 0 0x100000>; 3438 #iommu-cells = <2>; 3439 #global-interrupts = <2>; 3440 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 3441 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3442 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3443 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3444 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3445 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3446 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3447 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3448 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3449 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3450 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3451 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3452 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3453 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3454 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3455 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3456 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3457 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3458 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3459 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3460 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3461 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3462 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3463 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3464 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3465 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3466 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3467 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3468 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3469 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3470 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3471 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3472 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3473 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3474 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3475 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3476 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3477 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3478 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3479 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3480 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3481 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3482 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3483 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3484 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3485 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3486 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3487 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3488 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3489 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3490 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3491 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3492 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3493 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3494 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3495 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3496 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3497 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3498 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3499 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3500 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3501 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3502 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3503 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3504 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3505 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3506 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3507 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3508 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3509 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3510 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3511 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3512 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3513 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3514 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3515 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3516 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3517 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3518 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3519 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3520 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3521 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3522 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3523 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3524 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3525 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3526 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3527 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3528 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3529 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3530 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3531 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3532 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3533 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3534 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3535 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3536 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 3537 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 3538 dma-coherent; 3539 }; 3540 3541 intc: interrupt-controller@17a00000 { 3542 compatible = "arm,gic-v3"; 3543 #interrupt-cells = <3>; 3544 interrupt-controller; 3545 #redistributor-regions = <1>; 3546 redistributor-stride = <0 0x20000>; 3547 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3548 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3549 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3550 }; 3551 3552 timer@17c20000 { 3553 compatible = "arm,armv7-timer-mem"; 3554 #address-cells = <1>; 3555 #size-cells = <1>; 3556 ranges = <0 0 0 0x20000000>; 3557 reg = <0x0 0x17c20000 0x0 0x1000>; 3558 clock-frequency = <19200000>; 3559 3560 frame@17c21000 { 3561 frame-number = <0>; 3562 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3563 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3564 reg = <0x17c21000 0x1000>, 3565 <0x17c22000 0x1000>; 3566 }; 3567 3568 frame@17c23000 { 3569 frame-number = <1>; 3570 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3571 reg = <0x17c23000 0x1000>; 3572 status = "disabled"; 3573 }; 3574 3575 frame@17c25000 { 3576 frame-number = <2>; 3577 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3578 reg = <0x17c25000 0x1000>; 3579 status = "disabled"; 3580 }; 3581 3582 frame@17c27000 { 3583 frame-number = <3>; 3584 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3585 reg = <0x17c27000 0x1000>; 3586 status = "disabled"; 3587 }; 3588 3589 frame@17c29000 { 3590 frame-number = <4>; 3591 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3592 reg = <0x17c29000 0x1000>; 3593 status = "disabled"; 3594 }; 3595 3596 frame@17c2b000 { 3597 frame-number = <5>; 3598 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3599 reg = <0x17c2b000 0x1000>; 3600 status = "disabled"; 3601 }; 3602 3603 frame@17c2d000 { 3604 frame-number = <6>; 3605 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3606 reg = <0x17c2d000 0x1000>; 3607 status = "disabled"; 3608 }; 3609 }; 3610 3611 apps_rsc: rsc@18200000 { 3612 label = "apps_rsc"; 3613 compatible = "qcom,rpmh-rsc"; 3614 reg = <0x0 0x18200000 0x0 0x10000>, 3615 <0x0 0x18210000 0x0 0x10000>, 3616 <0x0 0x18220000 0x0 0x10000>; 3617 reg-names = "drv-0", "drv-1", "drv-2"; 3618 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3619 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3620 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3621 qcom,tcs-offset = <0xd00>; 3622 qcom,drv-id = <2>; 3623 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 3624 <WAKE_TCS 3>, <CONTROL_TCS 0>; 3625 power-domains = <&cluster_pd>; 3626 3627 rpmhcc: clock-controller { 3628 compatible = "qcom,sm8350-rpmh-clk"; 3629 #clock-cells = <1>; 3630 clock-names = "xo"; 3631 clocks = <&xo_board>; 3632 }; 3633 3634 rpmhpd: power-controller { 3635 compatible = "qcom,sm8350-rpmhpd"; 3636 #power-domain-cells = <1>; 3637 operating-points-v2 = <&rpmhpd_opp_table>; 3638 3639 rpmhpd_opp_table: opp-table { 3640 compatible = "operating-points-v2"; 3641 3642 rpmhpd_opp_ret: opp1 { 3643 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3644 }; 3645 3646 rpmhpd_opp_min_svs: opp2 { 3647 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3648 }; 3649 3650 rpmhpd_opp_low_svs: opp3 { 3651 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3652 }; 3653 3654 rpmhpd_opp_svs: opp4 { 3655 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3656 }; 3657 3658 rpmhpd_opp_svs_l1: opp5 { 3659 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3660 }; 3661 3662 rpmhpd_opp_nom: opp6 { 3663 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3664 }; 3665 3666 rpmhpd_opp_nom_l1: opp7 { 3667 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3668 }; 3669 3670 rpmhpd_opp_nom_l2: opp8 { 3671 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3672 }; 3673 3674 rpmhpd_opp_turbo: opp9 { 3675 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3676 }; 3677 3678 rpmhpd_opp_turbo_l1: opp10 { 3679 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3680 }; 3681 }; 3682 }; 3683 3684 apps_bcm_voter: bcm-voter { 3685 compatible = "qcom,bcm-voter"; 3686 }; 3687 }; 3688 3689 cpufreq_hw: cpufreq@18591000 { 3690 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss"; 3691 reg = <0 0x18591000 0 0x1000>, 3692 <0 0x18592000 0 0x1000>, 3693 <0 0x18593000 0 0x1000>; 3694 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3695 3696 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 3697 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3698 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 3699 interrupt-names = "dcvsh-irq-0", 3700 "dcvsh-irq-1", 3701 "dcvsh-irq-2"; 3702 3703 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3704 clock-names = "xo", "alternate"; 3705 3706 #freq-domain-cells = <1>; 3707 #clock-cells = <1>; 3708 }; 3709 }; 3710 3711 thermal_zones: thermal-zones { 3712 cpu0-thermal { 3713 polling-delay-passive = <250>; 3714 3715 thermal-sensors = <&tsens0 1>; 3716 3717 trips { 3718 cpu0_alert0: trip-point0 { 3719 temperature = <90000>; 3720 hysteresis = <2000>; 3721 type = "passive"; 3722 }; 3723 3724 cpu0_alert1: trip-point1 { 3725 temperature = <95000>; 3726 hysteresis = <2000>; 3727 type = "passive"; 3728 }; 3729 3730 cpu0_crit: cpu-crit { 3731 temperature = <110000>; 3732 hysteresis = <1000>; 3733 type = "critical"; 3734 }; 3735 }; 3736 3737 cooling-maps { 3738 map0 { 3739 trip = <&cpu0_alert0>; 3740 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3741 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3742 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3743 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3744 }; 3745 map1 { 3746 trip = <&cpu0_alert1>; 3747 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3748 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3749 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3750 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3751 }; 3752 }; 3753 }; 3754 3755 cpu1-thermal { 3756 polling-delay-passive = <250>; 3757 3758 thermal-sensors = <&tsens0 2>; 3759 3760 trips { 3761 cpu1_alert0: trip-point0 { 3762 temperature = <90000>; 3763 hysteresis = <2000>; 3764 type = "passive"; 3765 }; 3766 3767 cpu1_alert1: trip-point1 { 3768 temperature = <95000>; 3769 hysteresis = <2000>; 3770 type = "passive"; 3771 }; 3772 3773 cpu1_crit: cpu-crit { 3774 temperature = <110000>; 3775 hysteresis = <1000>; 3776 type = "critical"; 3777 }; 3778 }; 3779 3780 cooling-maps { 3781 map0 { 3782 trip = <&cpu1_alert0>; 3783 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3784 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3785 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3786 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3787 }; 3788 map1 { 3789 trip = <&cpu1_alert1>; 3790 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3791 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3792 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3793 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3794 }; 3795 }; 3796 }; 3797 3798 cpu2-thermal { 3799 polling-delay-passive = <250>; 3800 3801 thermal-sensors = <&tsens0 3>; 3802 3803 trips { 3804 cpu2_alert0: trip-point0 { 3805 temperature = <90000>; 3806 hysteresis = <2000>; 3807 type = "passive"; 3808 }; 3809 3810 cpu2_alert1: trip-point1 { 3811 temperature = <95000>; 3812 hysteresis = <2000>; 3813 type = "passive"; 3814 }; 3815 3816 cpu2_crit: cpu-crit { 3817 temperature = <110000>; 3818 hysteresis = <1000>; 3819 type = "critical"; 3820 }; 3821 }; 3822 3823 cooling-maps { 3824 map0 { 3825 trip = <&cpu2_alert0>; 3826 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3827 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3828 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3829 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3830 }; 3831 map1 { 3832 trip = <&cpu2_alert1>; 3833 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3834 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3835 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3836 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3837 }; 3838 }; 3839 }; 3840 3841 cpu3-thermal { 3842 polling-delay-passive = <250>; 3843 3844 thermal-sensors = <&tsens0 4>; 3845 3846 trips { 3847 cpu3_alert0: trip-point0 { 3848 temperature = <90000>; 3849 hysteresis = <2000>; 3850 type = "passive"; 3851 }; 3852 3853 cpu3_alert1: trip-point1 { 3854 temperature = <95000>; 3855 hysteresis = <2000>; 3856 type = "passive"; 3857 }; 3858 3859 cpu3_crit: cpu-crit { 3860 temperature = <110000>; 3861 hysteresis = <1000>; 3862 type = "critical"; 3863 }; 3864 }; 3865 3866 cooling-maps { 3867 map0 { 3868 trip = <&cpu3_alert0>; 3869 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3870 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3871 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3872 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3873 }; 3874 map1 { 3875 trip = <&cpu3_alert1>; 3876 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3877 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3878 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3879 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3880 }; 3881 }; 3882 }; 3883 3884 cpu4-top-thermal { 3885 polling-delay-passive = <250>; 3886 3887 thermal-sensors = <&tsens0 7>; 3888 3889 trips { 3890 cpu4_top_alert0: trip-point0 { 3891 temperature = <90000>; 3892 hysteresis = <2000>; 3893 type = "passive"; 3894 }; 3895 3896 cpu4_top_alert1: trip-point1 { 3897 temperature = <95000>; 3898 hysteresis = <2000>; 3899 type = "passive"; 3900 }; 3901 3902 cpu4_top_crit: cpu-crit { 3903 temperature = <110000>; 3904 hysteresis = <1000>; 3905 type = "critical"; 3906 }; 3907 }; 3908 3909 cooling-maps { 3910 map0 { 3911 trip = <&cpu4_top_alert0>; 3912 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3913 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3914 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3915 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3916 }; 3917 map1 { 3918 trip = <&cpu4_top_alert1>; 3919 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3920 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3921 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3922 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3923 }; 3924 }; 3925 }; 3926 3927 cpu5-top-thermal { 3928 polling-delay-passive = <250>; 3929 3930 thermal-sensors = <&tsens0 8>; 3931 3932 trips { 3933 cpu5_top_alert0: trip-point0 { 3934 temperature = <90000>; 3935 hysteresis = <2000>; 3936 type = "passive"; 3937 }; 3938 3939 cpu5_top_alert1: trip-point1 { 3940 temperature = <95000>; 3941 hysteresis = <2000>; 3942 type = "passive"; 3943 }; 3944 3945 cpu5_top_crit: cpu-crit { 3946 temperature = <110000>; 3947 hysteresis = <1000>; 3948 type = "critical"; 3949 }; 3950 }; 3951 3952 cooling-maps { 3953 map0 { 3954 trip = <&cpu5_top_alert0>; 3955 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3956 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3957 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3958 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3959 }; 3960 map1 { 3961 trip = <&cpu5_top_alert1>; 3962 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3963 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3964 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3965 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3966 }; 3967 }; 3968 }; 3969 3970 cpu6-top-thermal { 3971 polling-delay-passive = <250>; 3972 3973 thermal-sensors = <&tsens0 9>; 3974 3975 trips { 3976 cpu6_top_alert0: trip-point0 { 3977 temperature = <90000>; 3978 hysteresis = <2000>; 3979 type = "passive"; 3980 }; 3981 3982 cpu6_top_alert1: trip-point1 { 3983 temperature = <95000>; 3984 hysteresis = <2000>; 3985 type = "passive"; 3986 }; 3987 3988 cpu6_top_crit: cpu-crit { 3989 temperature = <110000>; 3990 hysteresis = <1000>; 3991 type = "critical"; 3992 }; 3993 }; 3994 3995 cooling-maps { 3996 map0 { 3997 trip = <&cpu6_top_alert0>; 3998 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3999 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4000 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4001 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4002 }; 4003 map1 { 4004 trip = <&cpu6_top_alert1>; 4005 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4006 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4007 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4008 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4009 }; 4010 }; 4011 }; 4012 4013 cpu7-top-thermal { 4014 polling-delay-passive = <250>; 4015 4016 thermal-sensors = <&tsens0 10>; 4017 4018 trips { 4019 cpu7_top_alert0: trip-point0 { 4020 temperature = <90000>; 4021 hysteresis = <2000>; 4022 type = "passive"; 4023 }; 4024 4025 cpu7_top_alert1: trip-point1 { 4026 temperature = <95000>; 4027 hysteresis = <2000>; 4028 type = "passive"; 4029 }; 4030 4031 cpu7_top_crit: cpu-crit { 4032 temperature = <110000>; 4033 hysteresis = <1000>; 4034 type = "critical"; 4035 }; 4036 }; 4037 4038 cooling-maps { 4039 map0 { 4040 trip = <&cpu7_top_alert0>; 4041 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4042 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4043 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4044 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4045 }; 4046 map1 { 4047 trip = <&cpu7_top_alert1>; 4048 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4049 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4050 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4051 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4052 }; 4053 }; 4054 }; 4055 4056 cpu4-bottom-thermal { 4057 polling-delay-passive = <250>; 4058 4059 thermal-sensors = <&tsens0 11>; 4060 4061 trips { 4062 cpu4_bottom_alert0: trip-point0 { 4063 temperature = <90000>; 4064 hysteresis = <2000>; 4065 type = "passive"; 4066 }; 4067 4068 cpu4_bottom_alert1: trip-point1 { 4069 temperature = <95000>; 4070 hysteresis = <2000>; 4071 type = "passive"; 4072 }; 4073 4074 cpu4_bottom_crit: cpu-crit { 4075 temperature = <110000>; 4076 hysteresis = <1000>; 4077 type = "critical"; 4078 }; 4079 }; 4080 4081 cooling-maps { 4082 map0 { 4083 trip = <&cpu4_bottom_alert0>; 4084 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4085 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4086 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4087 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4088 }; 4089 map1 { 4090 trip = <&cpu4_bottom_alert1>; 4091 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4092 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4093 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4094 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4095 }; 4096 }; 4097 }; 4098 4099 cpu5-bottom-thermal { 4100 polling-delay-passive = <250>; 4101 4102 thermal-sensors = <&tsens0 12>; 4103 4104 trips { 4105 cpu5_bottom_alert0: trip-point0 { 4106 temperature = <90000>; 4107 hysteresis = <2000>; 4108 type = "passive"; 4109 }; 4110 4111 cpu5_bottom_alert1: trip-point1 { 4112 temperature = <95000>; 4113 hysteresis = <2000>; 4114 type = "passive"; 4115 }; 4116 4117 cpu5_bottom_crit: cpu-crit { 4118 temperature = <110000>; 4119 hysteresis = <1000>; 4120 type = "critical"; 4121 }; 4122 }; 4123 4124 cooling-maps { 4125 map0 { 4126 trip = <&cpu5_bottom_alert0>; 4127 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4128 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4129 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4130 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4131 }; 4132 map1 { 4133 trip = <&cpu5_bottom_alert1>; 4134 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4135 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4136 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4137 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4138 }; 4139 }; 4140 }; 4141 4142 cpu6-bottom-thermal { 4143 polling-delay-passive = <250>; 4144 4145 thermal-sensors = <&tsens0 13>; 4146 4147 trips { 4148 cpu6_bottom_alert0: trip-point0 { 4149 temperature = <90000>; 4150 hysteresis = <2000>; 4151 type = "passive"; 4152 }; 4153 4154 cpu6_bottom_alert1: trip-point1 { 4155 temperature = <95000>; 4156 hysteresis = <2000>; 4157 type = "passive"; 4158 }; 4159 4160 cpu6_bottom_crit: cpu-crit { 4161 temperature = <110000>; 4162 hysteresis = <1000>; 4163 type = "critical"; 4164 }; 4165 }; 4166 4167 cooling-maps { 4168 map0 { 4169 trip = <&cpu6_bottom_alert0>; 4170 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4171 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4172 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4173 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4174 }; 4175 map1 { 4176 trip = <&cpu6_bottom_alert1>; 4177 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4178 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4179 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4180 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4181 }; 4182 }; 4183 }; 4184 4185 cpu7-bottom-thermal { 4186 polling-delay-passive = <250>; 4187 4188 thermal-sensors = <&tsens0 14>; 4189 4190 trips { 4191 cpu7_bottom_alert0: trip-point0 { 4192 temperature = <90000>; 4193 hysteresis = <2000>; 4194 type = "passive"; 4195 }; 4196 4197 cpu7_bottom_alert1: trip-point1 { 4198 temperature = <95000>; 4199 hysteresis = <2000>; 4200 type = "passive"; 4201 }; 4202 4203 cpu7_bottom_crit: cpu-crit { 4204 temperature = <110000>; 4205 hysteresis = <1000>; 4206 type = "critical"; 4207 }; 4208 }; 4209 4210 cooling-maps { 4211 map0 { 4212 trip = <&cpu7_bottom_alert0>; 4213 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4214 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4215 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4216 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4217 }; 4218 map1 { 4219 trip = <&cpu7_bottom_alert1>; 4220 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4221 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4222 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4223 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4224 }; 4225 }; 4226 }; 4227 4228 aoss0-thermal { 4229 polling-delay-passive = <250>; 4230 4231 thermal-sensors = <&tsens0 0>; 4232 4233 trips { 4234 aoss0_alert0: trip-point0 { 4235 temperature = <90000>; 4236 hysteresis = <2000>; 4237 type = "hot"; 4238 }; 4239 }; 4240 }; 4241 4242 cluster0-thermal { 4243 polling-delay-passive = <250>; 4244 4245 thermal-sensors = <&tsens0 5>; 4246 4247 trips { 4248 cluster0_alert0: trip-point0 { 4249 temperature = <90000>; 4250 hysteresis = <2000>; 4251 type = "hot"; 4252 }; 4253 cluster0_crit: cluster0-crit { 4254 temperature = <110000>; 4255 hysteresis = <2000>; 4256 type = "critical"; 4257 }; 4258 }; 4259 }; 4260 4261 cluster1-thermal { 4262 polling-delay-passive = <250>; 4263 4264 thermal-sensors = <&tsens0 6>; 4265 4266 trips { 4267 cluster1_alert0: trip-point0 { 4268 temperature = <90000>; 4269 hysteresis = <2000>; 4270 type = "hot"; 4271 }; 4272 cluster1_crit: cluster1-crit { 4273 temperature = <110000>; 4274 hysteresis = <2000>; 4275 type = "critical"; 4276 }; 4277 }; 4278 }; 4279 4280 aoss1-thermal { 4281 polling-delay-passive = <250>; 4282 4283 thermal-sensors = <&tsens1 0>; 4284 4285 trips { 4286 aoss1_alert0: trip-point0 { 4287 temperature = <90000>; 4288 hysteresis = <2000>; 4289 type = "hot"; 4290 }; 4291 }; 4292 }; 4293 4294 gpu-top-thermal { 4295 polling-delay-passive = <250>; 4296 4297 thermal-sensors = <&tsens1 1>; 4298 4299 cooling-maps { 4300 map0 { 4301 trip = <&gpu_top_alert0>; 4302 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4303 }; 4304 }; 4305 4306 trips { 4307 gpu_top_alert0: trip-point0 { 4308 temperature = <85000>; 4309 hysteresis = <1000>; 4310 type = "passive"; 4311 }; 4312 4313 trip-point1 { 4314 temperature = <90000>; 4315 hysteresis = <1000>; 4316 type = "hot"; 4317 }; 4318 4319 trip-point2 { 4320 temperature = <110000>; 4321 hysteresis = <1000>; 4322 type = "critical"; 4323 }; 4324 }; 4325 }; 4326 4327 gpu-bottom-thermal { 4328 polling-delay-passive = <250>; 4329 4330 thermal-sensors = <&tsens1 2>; 4331 4332 cooling-maps { 4333 map0 { 4334 trip = <&gpu_bottom_alert0>; 4335 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4336 }; 4337 }; 4338 4339 trips { 4340 gpu_bottom_alert0: trip-point0 { 4341 temperature = <85000>; 4342 hysteresis = <1000>; 4343 type = "passive"; 4344 }; 4345 4346 trip-point1 { 4347 temperature = <90000>; 4348 hysteresis = <1000>; 4349 type = "hot"; 4350 }; 4351 4352 trip-point2 { 4353 temperature = <110000>; 4354 hysteresis = <1000>; 4355 type = "critical"; 4356 }; 4357 }; 4358 }; 4359 4360 nspss1-thermal { 4361 polling-delay-passive = <250>; 4362 4363 thermal-sensors = <&tsens1 3>; 4364 4365 trips { 4366 nspss1_alert0: trip-point0 { 4367 temperature = <90000>; 4368 hysteresis = <1000>; 4369 type = "hot"; 4370 }; 4371 }; 4372 }; 4373 4374 nspss2-thermal { 4375 polling-delay-passive = <250>; 4376 4377 thermal-sensors = <&tsens1 4>; 4378 4379 trips { 4380 nspss2_alert0: trip-point0 { 4381 temperature = <90000>; 4382 hysteresis = <1000>; 4383 type = "hot"; 4384 }; 4385 }; 4386 }; 4387 4388 nspss3-thermal { 4389 polling-delay-passive = <250>; 4390 4391 thermal-sensors = <&tsens1 5>; 4392 4393 trips { 4394 nspss3_alert0: trip-point0 { 4395 temperature = <90000>; 4396 hysteresis = <1000>; 4397 type = "hot"; 4398 }; 4399 }; 4400 }; 4401 4402 video-thermal { 4403 polling-delay-passive = <250>; 4404 4405 thermal-sensors = <&tsens1 6>; 4406 4407 trips { 4408 video_alert0: trip-point0 { 4409 temperature = <90000>; 4410 hysteresis = <2000>; 4411 type = "hot"; 4412 }; 4413 }; 4414 }; 4415 4416 mem-thermal { 4417 polling-delay-passive = <250>; 4418 4419 thermal-sensors = <&tsens1 7>; 4420 4421 trips { 4422 mem_alert0: trip-point0 { 4423 temperature = <90000>; 4424 hysteresis = <2000>; 4425 type = "hot"; 4426 }; 4427 }; 4428 }; 4429 4430 modem1-top-thermal { 4431 polling-delay-passive = <250>; 4432 4433 thermal-sensors = <&tsens1 8>; 4434 4435 trips { 4436 modem1_alert0: trip-point0 { 4437 temperature = <90000>; 4438 hysteresis = <2000>; 4439 type = "hot"; 4440 }; 4441 }; 4442 }; 4443 4444 modem2-top-thermal { 4445 polling-delay-passive = <250>; 4446 4447 thermal-sensors = <&tsens1 9>; 4448 4449 trips { 4450 modem2_alert0: trip-point0 { 4451 temperature = <90000>; 4452 hysteresis = <2000>; 4453 type = "hot"; 4454 }; 4455 }; 4456 }; 4457 4458 modem3-top-thermal { 4459 polling-delay-passive = <250>; 4460 4461 thermal-sensors = <&tsens1 10>; 4462 4463 trips { 4464 modem3_alert0: trip-point0 { 4465 temperature = <90000>; 4466 hysteresis = <2000>; 4467 type = "hot"; 4468 }; 4469 }; 4470 }; 4471 4472 modem4-top-thermal { 4473 polling-delay-passive = <250>; 4474 4475 thermal-sensors = <&tsens1 11>; 4476 4477 trips { 4478 modem4_alert0: trip-point0 { 4479 temperature = <90000>; 4480 hysteresis = <2000>; 4481 type = "hot"; 4482 }; 4483 }; 4484 }; 4485 4486 camera-top-thermal { 4487 polling-delay-passive = <250>; 4488 4489 thermal-sensors = <&tsens1 12>; 4490 4491 trips { 4492 camera1_alert0: trip-point0 { 4493 temperature = <90000>; 4494 hysteresis = <2000>; 4495 type = "hot"; 4496 }; 4497 }; 4498 }; 4499 4500 cam-bottom-thermal { 4501 polling-delay-passive = <250>; 4502 4503 thermal-sensors = <&tsens1 13>; 4504 4505 trips { 4506 camera2_alert0: trip-point0 { 4507 temperature = <90000>; 4508 hysteresis = <2000>; 4509 type = "hot"; 4510 }; 4511 }; 4512 }; 4513 }; 4514 4515 timer { 4516 compatible = "arm,armv8-timer"; 4517 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4518 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4519 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4520 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4521 }; 4522}; 4523