1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Linaro Limited 4 */ 5 6#include <dt-bindings/interconnect/qcom,sm8350.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/qcom,dispcc-sm8350.h> 9#include <dt-bindings/clock/qcom,gcc-sm8350.h> 10#include <dt-bindings/clock/qcom,gpucc-sm8350.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/firmware/qcom,scm.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interconnect/qcom,sm8350.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/phy/phy-qcom-qmp.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/power/qcom,rpmhpd.h> 20#include <dt-bindings/soc/qcom,apr.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/sound/qcom,q6afe.h> 23#include <dt-bindings/thermal/thermal.h> 24#include <dt-bindings/interconnect/qcom,sm8350.h> 25 26/ { 27 interrupt-parent = <&intc>; 28 29 #address-cells = <2>; 30 #size-cells = <2>; 31 32 chosen { }; 33 34 clocks { 35 xo_board: xo-board { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <38400000>; 39 clock-output-names = "xo_board"; 40 }; 41 42 sleep_clk: sleep-clk { 43 compatible = "fixed-clock"; 44 clock-frequency = <32000>; 45 #clock-cells = <0>; 46 }; 47 }; 48 49 cpus { 50 #address-cells = <2>; 51 #size-cells = <0>; 52 53 CPU0: cpu@0 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a55"; 56 reg = <0x0 0x0>; 57 clocks = <&cpufreq_hw 0>; 58 enable-method = "psci"; 59 next-level-cache = <&L2_0>; 60 qcom,freq-domain = <&cpufreq_hw 0>; 61 power-domains = <&CPU_PD0>; 62 power-domain-names = "psci"; 63 #cooling-cells = <2>; 64 L2_0: l2-cache { 65 compatible = "cache"; 66 cache-level = <2>; 67 cache-unified; 68 next-level-cache = <&L3_0>; 69 L3_0: l3-cache { 70 compatible = "cache"; 71 cache-level = <3>; 72 cache-unified; 73 }; 74 }; 75 }; 76 77 CPU1: cpu@100 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a55"; 80 reg = <0x0 0x100>; 81 clocks = <&cpufreq_hw 0>; 82 enable-method = "psci"; 83 next-level-cache = <&L2_100>; 84 qcom,freq-domain = <&cpufreq_hw 0>; 85 power-domains = <&CPU_PD1>; 86 power-domain-names = "psci"; 87 #cooling-cells = <2>; 88 L2_100: l2-cache { 89 compatible = "cache"; 90 cache-level = <2>; 91 cache-unified; 92 next-level-cache = <&L3_0>; 93 }; 94 }; 95 96 CPU2: cpu@200 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a55"; 99 reg = <0x0 0x200>; 100 clocks = <&cpufreq_hw 0>; 101 enable-method = "psci"; 102 next-level-cache = <&L2_200>; 103 qcom,freq-domain = <&cpufreq_hw 0>; 104 power-domains = <&CPU_PD2>; 105 power-domain-names = "psci"; 106 #cooling-cells = <2>; 107 L2_200: l2-cache { 108 compatible = "cache"; 109 cache-level = <2>; 110 cache-unified; 111 next-level-cache = <&L3_0>; 112 }; 113 }; 114 115 CPU3: cpu@300 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a55"; 118 reg = <0x0 0x300>; 119 clocks = <&cpufreq_hw 0>; 120 enable-method = "psci"; 121 next-level-cache = <&L2_300>; 122 qcom,freq-domain = <&cpufreq_hw 0>; 123 power-domains = <&CPU_PD3>; 124 power-domain-names = "psci"; 125 #cooling-cells = <2>; 126 L2_300: l2-cache { 127 compatible = "cache"; 128 cache-level = <2>; 129 cache-unified; 130 next-level-cache = <&L3_0>; 131 }; 132 }; 133 134 CPU4: cpu@400 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-a78"; 137 reg = <0x0 0x400>; 138 clocks = <&cpufreq_hw 1>; 139 enable-method = "psci"; 140 next-level-cache = <&L2_400>; 141 qcom,freq-domain = <&cpufreq_hw 1>; 142 power-domains = <&CPU_PD4>; 143 power-domain-names = "psci"; 144 #cooling-cells = <2>; 145 L2_400: l2-cache { 146 compatible = "cache"; 147 cache-level = <2>; 148 cache-unified; 149 next-level-cache = <&L3_0>; 150 }; 151 }; 152 153 CPU5: cpu@500 { 154 device_type = "cpu"; 155 compatible = "arm,cortex-a78"; 156 reg = <0x0 0x500>; 157 clocks = <&cpufreq_hw 1>; 158 enable-method = "psci"; 159 next-level-cache = <&L2_500>; 160 qcom,freq-domain = <&cpufreq_hw 1>; 161 power-domains = <&CPU_PD5>; 162 power-domain-names = "psci"; 163 #cooling-cells = <2>; 164 L2_500: l2-cache { 165 compatible = "cache"; 166 cache-level = <2>; 167 cache-unified; 168 next-level-cache = <&L3_0>; 169 }; 170 }; 171 172 CPU6: cpu@600 { 173 device_type = "cpu"; 174 compatible = "arm,cortex-a78"; 175 reg = <0x0 0x600>; 176 clocks = <&cpufreq_hw 1>; 177 enable-method = "psci"; 178 next-level-cache = <&L2_600>; 179 qcom,freq-domain = <&cpufreq_hw 1>; 180 power-domains = <&CPU_PD6>; 181 power-domain-names = "psci"; 182 #cooling-cells = <2>; 183 L2_600: l2-cache { 184 compatible = "cache"; 185 cache-level = <2>; 186 cache-unified; 187 next-level-cache = <&L3_0>; 188 }; 189 }; 190 191 CPU7: cpu@700 { 192 device_type = "cpu"; 193 compatible = "arm,cortex-x1"; 194 reg = <0x0 0x700>; 195 clocks = <&cpufreq_hw 2>; 196 enable-method = "psci"; 197 next-level-cache = <&L2_700>; 198 qcom,freq-domain = <&cpufreq_hw 2>; 199 power-domains = <&CPU_PD7>; 200 power-domain-names = "psci"; 201 #cooling-cells = <2>; 202 L2_700: l2-cache { 203 compatible = "cache"; 204 cache-level = <2>; 205 cache-unified; 206 next-level-cache = <&L3_0>; 207 }; 208 }; 209 210 cpu-map { 211 cluster0 { 212 core0 { 213 cpu = <&CPU0>; 214 }; 215 216 core1 { 217 cpu = <&CPU1>; 218 }; 219 220 core2 { 221 cpu = <&CPU2>; 222 }; 223 224 core3 { 225 cpu = <&CPU3>; 226 }; 227 228 core4 { 229 cpu = <&CPU4>; 230 }; 231 232 core5 { 233 cpu = <&CPU5>; 234 }; 235 236 core6 { 237 cpu = <&CPU6>; 238 }; 239 240 core7 { 241 cpu = <&CPU7>; 242 }; 243 }; 244 }; 245 246 idle-states { 247 entry-method = "psci"; 248 249 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 250 compatible = "arm,idle-state"; 251 idle-state-name = "silver-rail-power-collapse"; 252 arm,psci-suspend-param = <0x40000004>; 253 entry-latency-us = <360>; 254 exit-latency-us = <531>; 255 min-residency-us = <3934>; 256 local-timer-stop; 257 }; 258 259 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 260 compatible = "arm,idle-state"; 261 idle-state-name = "gold-rail-power-collapse"; 262 arm,psci-suspend-param = <0x40000004>; 263 entry-latency-us = <702>; 264 exit-latency-us = <1061>; 265 min-residency-us = <4488>; 266 local-timer-stop; 267 }; 268 }; 269 270 domain-idle-states { 271 CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { 272 compatible = "domain-idle-state"; 273 arm,psci-suspend-param = <0x41000044>; 274 entry-latency-us = <2752>; 275 exit-latency-us = <3048>; 276 min-residency-us = <6118>; 277 }; 278 279 CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 { 280 compatible = "domain-idle-state"; 281 arm,psci-suspend-param = <0x4100c344>; 282 entry-latency-us = <3263>; 283 exit-latency-us = <6562>; 284 min-residency-us = <9987>; 285 }; 286 }; 287 }; 288 289 firmware { 290 scm: scm { 291 compatible = "qcom,scm-sm8350", "qcom,scm"; 292 #reset-cells = <1>; 293 }; 294 }; 295 296 memory@80000000 { 297 device_type = "memory"; 298 /* We expect the bootloader to fill in the size */ 299 reg = <0x0 0x80000000 0x0 0x0>; 300 }; 301 302 pmu { 303 compatible = "arm,armv8-pmuv3"; 304 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 305 }; 306 307 psci { 308 compatible = "arm,psci-1.0"; 309 method = "smc"; 310 311 CPU_PD0: power-domain-cpu0 { 312 #power-domain-cells = <0>; 313 power-domains = <&CLUSTER_PD>; 314 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 315 }; 316 317 CPU_PD1: power-domain-cpu1 { 318 #power-domain-cells = <0>; 319 power-domains = <&CLUSTER_PD>; 320 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 321 }; 322 323 CPU_PD2: power-domain-cpu2 { 324 #power-domain-cells = <0>; 325 power-domains = <&CLUSTER_PD>; 326 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 327 }; 328 329 CPU_PD3: power-domain-cpu3 { 330 #power-domain-cells = <0>; 331 power-domains = <&CLUSTER_PD>; 332 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 333 }; 334 335 CPU_PD4: power-domain-cpu4 { 336 #power-domain-cells = <0>; 337 power-domains = <&CLUSTER_PD>; 338 domain-idle-states = <&BIG_CPU_SLEEP_0>; 339 }; 340 341 CPU_PD5: power-domain-cpu5 { 342 #power-domain-cells = <0>; 343 power-domains = <&CLUSTER_PD>; 344 domain-idle-states = <&BIG_CPU_SLEEP_0>; 345 }; 346 347 CPU_PD6: power-domain-cpu6 { 348 #power-domain-cells = <0>; 349 power-domains = <&CLUSTER_PD>; 350 domain-idle-states = <&BIG_CPU_SLEEP_0>; 351 }; 352 353 CPU_PD7: power-domain-cpu7 { 354 #power-domain-cells = <0>; 355 power-domains = <&CLUSTER_PD>; 356 domain-idle-states = <&BIG_CPU_SLEEP_0>; 357 }; 358 359 CLUSTER_PD: power-domain-cpu-cluster0 { 360 #power-domain-cells = <0>; 361 domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLEEP>; 362 }; 363 }; 364 365 qup_opp_table_100mhz: opp-table-qup100mhz { 366 compatible = "operating-points-v2"; 367 368 opp-50000000 { 369 opp-hz = /bits/ 64 <50000000>; 370 required-opps = <&rpmhpd_opp_min_svs>; 371 }; 372 373 opp-75000000 { 374 opp-hz = /bits/ 64 <75000000>; 375 required-opps = <&rpmhpd_opp_low_svs>; 376 }; 377 378 opp-100000000 { 379 opp-hz = /bits/ 64 <100000000>; 380 required-opps = <&rpmhpd_opp_svs>; 381 }; 382 }; 383 384 qup_opp_table_120mhz: opp-table-qup120mhz { 385 compatible = "operating-points-v2"; 386 387 opp-50000000 { 388 opp-hz = /bits/ 64 <50000000>; 389 required-opps = <&rpmhpd_opp_min_svs>; 390 }; 391 392 opp-75000000 { 393 opp-hz = /bits/ 64 <75000000>; 394 required-opps = <&rpmhpd_opp_low_svs>; 395 }; 396 397 opp-120000000 { 398 opp-hz = /bits/ 64 <120000000>; 399 required-opps = <&rpmhpd_opp_svs>; 400 }; 401 }; 402 403 reserved_memory: reserved-memory { 404 #address-cells = <2>; 405 #size-cells = <2>; 406 ranges; 407 408 hyp_mem: memory@80000000 { 409 reg = <0x0 0x80000000 0x0 0x600000>; 410 no-map; 411 }; 412 413 xbl_aop_mem: memory@80700000 { 414 no-map; 415 reg = <0x0 0x80700000 0x0 0x160000>; 416 }; 417 418 cmd_db: memory@80860000 { 419 compatible = "qcom,cmd-db"; 420 reg = <0x0 0x80860000 0x0 0x20000>; 421 no-map; 422 }; 423 424 reserved_xbl_uefi_log: memory@80880000 { 425 reg = <0x0 0x80880000 0x0 0x14000>; 426 no-map; 427 }; 428 429 smem@80900000 { 430 compatible = "qcom,smem"; 431 reg = <0x0 0x80900000 0x0 0x200000>; 432 hwlocks = <&tcsr_mutex 3>; 433 no-map; 434 }; 435 436 cpucp_fw_mem: memory@80b00000 { 437 reg = <0x0 0x80b00000 0x0 0x100000>; 438 no-map; 439 }; 440 441 cdsp_secure_heap: memory@80c00000 { 442 reg = <0x0 0x80c00000 0x0 0x4600000>; 443 no-map; 444 }; 445 446 pil_camera_mem: mmeory@85200000 { 447 reg = <0x0 0x85200000 0x0 0x500000>; 448 no-map; 449 }; 450 451 pil_video_mem: memory@85700000 { 452 reg = <0x0 0x85700000 0x0 0x500000>; 453 no-map; 454 }; 455 456 pil_cvp_mem: memory@85c00000 { 457 reg = <0x0 0x85c00000 0x0 0x500000>; 458 no-map; 459 }; 460 461 pil_adsp_mem: memory@86100000 { 462 reg = <0x0 0x86100000 0x0 0x2100000>; 463 no-map; 464 }; 465 466 pil_slpi_mem: memory@88200000 { 467 reg = <0x0 0x88200000 0x0 0x1500000>; 468 no-map; 469 }; 470 471 pil_cdsp_mem: memory@89700000 { 472 reg = <0x0 0x89700000 0x0 0x1e00000>; 473 no-map; 474 }; 475 476 pil_ipa_fw_mem: memory@8b500000 { 477 reg = <0x0 0x8b500000 0x0 0x10000>; 478 no-map; 479 }; 480 481 pil_ipa_gsi_mem: memory@8b510000 { 482 reg = <0x0 0x8b510000 0x0 0xa000>; 483 no-map; 484 }; 485 486 pil_gpu_mem: memory@8b51a000 { 487 reg = <0x0 0x8b51a000 0x0 0x2000>; 488 no-map; 489 }; 490 491 pil_spss_mem: memory@8b600000 { 492 reg = <0x0 0x8b600000 0x0 0x100000>; 493 no-map; 494 }; 495 496 pil_modem_mem: memory@8b800000 { 497 reg = <0x0 0x8b800000 0x0 0x10000000>; 498 no-map; 499 }; 500 501 rmtfs_mem: memory@9b800000 { 502 compatible = "qcom,rmtfs-mem"; 503 reg = <0x0 0x9b800000 0x0 0x280000>; 504 no-map; 505 506 qcom,client-id = <1>; 507 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 508 }; 509 510 hyp_reserved_mem: memory@d0000000 { 511 reg = <0x0 0xd0000000 0x0 0x800000>; 512 no-map; 513 }; 514 515 pil_trustedvm_mem: memory@d0800000 { 516 reg = <0x0 0xd0800000 0x0 0x76f7000>; 517 no-map; 518 }; 519 520 qrtr_shbuf: memory@d7ef7000 { 521 reg = <0x0 0xd7ef7000 0x0 0x9000>; 522 no-map; 523 }; 524 525 chan0_shbuf: memory@d7f00000 { 526 reg = <0x0 0xd7f00000 0x0 0x80000>; 527 no-map; 528 }; 529 530 chan1_shbuf: memory@d7f80000 { 531 reg = <0x0 0xd7f80000 0x0 0x80000>; 532 no-map; 533 }; 534 535 removed_mem: memory@d8800000 { 536 reg = <0x0 0xd8800000 0x0 0x6800000>; 537 no-map; 538 }; 539 }; 540 541 smp2p-adsp { 542 compatible = "qcom,smp2p"; 543 qcom,smem = <443>, <429>; 544 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 545 IPCC_MPROC_SIGNAL_SMP2P 546 IRQ_TYPE_EDGE_RISING>; 547 mboxes = <&ipcc IPCC_CLIENT_LPASS 548 IPCC_MPROC_SIGNAL_SMP2P>; 549 550 qcom,local-pid = <0>; 551 qcom,remote-pid = <2>; 552 553 smp2p_adsp_out: master-kernel { 554 qcom,entry-name = "master-kernel"; 555 #qcom,smem-state-cells = <1>; 556 }; 557 558 smp2p_adsp_in: slave-kernel { 559 qcom,entry-name = "slave-kernel"; 560 interrupt-controller; 561 #interrupt-cells = <2>; 562 }; 563 }; 564 565 smp2p-cdsp { 566 compatible = "qcom,smp2p"; 567 qcom,smem = <94>, <432>; 568 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 569 IPCC_MPROC_SIGNAL_SMP2P 570 IRQ_TYPE_EDGE_RISING>; 571 mboxes = <&ipcc IPCC_CLIENT_CDSP 572 IPCC_MPROC_SIGNAL_SMP2P>; 573 574 qcom,local-pid = <0>; 575 qcom,remote-pid = <5>; 576 577 smp2p_cdsp_out: master-kernel { 578 qcom,entry-name = "master-kernel"; 579 #qcom,smem-state-cells = <1>; 580 }; 581 582 smp2p_cdsp_in: slave-kernel { 583 qcom,entry-name = "slave-kernel"; 584 interrupt-controller; 585 #interrupt-cells = <2>; 586 }; 587 }; 588 589 smp2p-modem { 590 compatible = "qcom,smp2p"; 591 qcom,smem = <435>, <428>; 592 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 593 IPCC_MPROC_SIGNAL_SMP2P 594 IRQ_TYPE_EDGE_RISING>; 595 mboxes = <&ipcc IPCC_CLIENT_MPSS 596 IPCC_MPROC_SIGNAL_SMP2P>; 597 598 qcom,local-pid = <0>; 599 qcom,remote-pid = <1>; 600 601 smp2p_modem_out: master-kernel { 602 qcom,entry-name = "master-kernel"; 603 #qcom,smem-state-cells = <1>; 604 }; 605 606 smp2p_modem_in: slave-kernel { 607 qcom,entry-name = "slave-kernel"; 608 interrupt-controller; 609 #interrupt-cells = <2>; 610 }; 611 612 ipa_smp2p_out: ipa-ap-to-modem { 613 qcom,entry-name = "ipa"; 614 #qcom,smem-state-cells = <1>; 615 }; 616 617 ipa_smp2p_in: ipa-modem-to-ap { 618 qcom,entry-name = "ipa"; 619 interrupt-controller; 620 #interrupt-cells = <2>; 621 }; 622 }; 623 624 smp2p-slpi { 625 compatible = "qcom,smp2p"; 626 qcom,smem = <481>, <430>; 627 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 628 IPCC_MPROC_SIGNAL_SMP2P 629 IRQ_TYPE_EDGE_RISING>; 630 mboxes = <&ipcc IPCC_CLIENT_SLPI 631 IPCC_MPROC_SIGNAL_SMP2P>; 632 633 qcom,local-pid = <0>; 634 qcom,remote-pid = <3>; 635 636 smp2p_slpi_out: master-kernel { 637 qcom,entry-name = "master-kernel"; 638 #qcom,smem-state-cells = <1>; 639 }; 640 641 smp2p_slpi_in: slave-kernel { 642 qcom,entry-name = "slave-kernel"; 643 interrupt-controller; 644 #interrupt-cells = <2>; 645 }; 646 }; 647 648 soc: soc@0 { 649 #address-cells = <2>; 650 #size-cells = <2>; 651 ranges = <0 0 0 0 0x10 0>; 652 dma-ranges = <0 0 0 0 0x10 0>; 653 compatible = "simple-bus"; 654 655 gcc: clock-controller@100000 { 656 compatible = "qcom,gcc-sm8350"; 657 reg = <0x0 0x00100000 0x0 0x1f0000>; 658 #clock-cells = <1>; 659 #reset-cells = <1>; 660 #power-domain-cells = <1>; 661 clock-names = "bi_tcxo", 662 "sleep_clk", 663 "pcie_0_pipe_clk", 664 "pcie_1_pipe_clk", 665 "ufs_card_rx_symbol_0_clk", 666 "ufs_card_rx_symbol_1_clk", 667 "ufs_card_tx_symbol_0_clk", 668 "ufs_phy_rx_symbol_0_clk", 669 "ufs_phy_rx_symbol_1_clk", 670 "ufs_phy_tx_symbol_0_clk", 671 "usb3_phy_wrapper_gcc_usb30_pipe_clk", 672 "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; 673 clocks = <&rpmhcc RPMH_CXO_CLK>, 674 <&sleep_clk>, 675 <&pcie0_phy>, 676 <&pcie1_phy>, 677 <0>, 678 <0>, 679 <0>, 680 <&ufs_mem_phy_lanes 0>, 681 <&ufs_mem_phy_lanes 1>, 682 <&ufs_mem_phy_lanes 2>, 683 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 684 <0>; 685 }; 686 687 ipcc: mailbox@408000 { 688 compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; 689 reg = <0 0x00408000 0 0x1000>; 690 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 691 interrupt-controller; 692 #interrupt-cells = <3>; 693 #mbox-cells = <2>; 694 }; 695 696 gpi_dma2: dma-controller@800000 { 697 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 698 reg = <0 0x00800000 0 0x60000>; 699 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 711 dma-channels = <12>; 712 dma-channel-mask = <0xff>; 713 iommus = <&apps_smmu 0x5f6 0x0>; 714 #dma-cells = <3>; 715 status = "disabled"; 716 }; 717 718 qupv3_id_2: geniqup@8c0000 { 719 compatible = "qcom,geni-se-qup"; 720 reg = <0x0 0x008c0000 0x0 0x6000>; 721 clock-names = "m-ahb", "s-ahb"; 722 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 723 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 724 iommus = <&apps_smmu 0x5e3 0x0>; 725 #address-cells = <2>; 726 #size-cells = <2>; 727 ranges; 728 status = "disabled"; 729 730 i2c14: i2c@880000 { 731 compatible = "qcom,geni-i2c"; 732 reg = <0 0x00880000 0 0x4000>; 733 clock-names = "se"; 734 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 735 pinctrl-names = "default"; 736 pinctrl-0 = <&qup_i2c14_default>; 737 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 738 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 739 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 740 dma-names = "tx", "rx"; 741 #address-cells = <1>; 742 #size-cells = <0>; 743 status = "disabled"; 744 }; 745 746 spi14: spi@880000 { 747 compatible = "qcom,geni-spi"; 748 reg = <0 0x00880000 0 0x4000>; 749 clock-names = "se"; 750 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 751 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 752 power-domains = <&rpmhpd RPMHPD_CX>; 753 operating-points-v2 = <&qup_opp_table_120mhz>; 754 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 755 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 756 dma-names = "tx", "rx"; 757 #address-cells = <1>; 758 #size-cells = <0>; 759 status = "disabled"; 760 }; 761 762 i2c15: i2c@884000 { 763 compatible = "qcom,geni-i2c"; 764 reg = <0 0x00884000 0 0x4000>; 765 clock-names = "se"; 766 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 767 pinctrl-names = "default"; 768 pinctrl-0 = <&qup_i2c15_default>; 769 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 770 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 771 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 772 dma-names = "tx", "rx"; 773 #address-cells = <1>; 774 #size-cells = <0>; 775 status = "disabled"; 776 }; 777 778 spi15: spi@884000 { 779 compatible = "qcom,geni-spi"; 780 reg = <0 0x00884000 0 0x4000>; 781 clock-names = "se"; 782 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 783 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 784 power-domains = <&rpmhpd RPMHPD_CX>; 785 operating-points-v2 = <&qup_opp_table_120mhz>; 786 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 787 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 788 dma-names = "tx", "rx"; 789 #address-cells = <1>; 790 #size-cells = <0>; 791 status = "disabled"; 792 }; 793 794 i2c16: i2c@888000 { 795 compatible = "qcom,geni-i2c"; 796 reg = <0 0x00888000 0 0x4000>; 797 clock-names = "se"; 798 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 799 pinctrl-names = "default"; 800 pinctrl-0 = <&qup_i2c16_default>; 801 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 802 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 803 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 804 dma-names = "tx", "rx"; 805 #address-cells = <1>; 806 #size-cells = <0>; 807 status = "disabled"; 808 }; 809 810 spi16: spi@888000 { 811 compatible = "qcom,geni-spi"; 812 reg = <0 0x00888000 0 0x4000>; 813 clock-names = "se"; 814 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 815 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 816 power-domains = <&rpmhpd RPMHPD_CX>; 817 operating-points-v2 = <&qup_opp_table_100mhz>; 818 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 819 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 820 dma-names = "tx", "rx"; 821 #address-cells = <1>; 822 #size-cells = <0>; 823 status = "disabled"; 824 }; 825 826 i2c17: i2c@88c000 { 827 compatible = "qcom,geni-i2c"; 828 reg = <0 0x0088c000 0 0x4000>; 829 clock-names = "se"; 830 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 831 pinctrl-names = "default"; 832 pinctrl-0 = <&qup_i2c17_default>; 833 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 834 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 835 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 836 dma-names = "tx", "rx"; 837 #address-cells = <1>; 838 #size-cells = <0>; 839 status = "disabled"; 840 }; 841 842 spi17: spi@88c000 { 843 compatible = "qcom,geni-spi"; 844 reg = <0 0x0088c000 0 0x4000>; 845 clock-names = "se"; 846 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 847 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 848 power-domains = <&rpmhpd RPMHPD_CX>; 849 operating-points-v2 = <&qup_opp_table_100mhz>; 850 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 851 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 852 dma-names = "tx", "rx"; 853 #address-cells = <1>; 854 #size-cells = <0>; 855 status = "disabled"; 856 }; 857 858 /* QUP no. 18 seems to be strictly SPI/UART-only */ 859 860 spi18: spi@890000 { 861 compatible = "qcom,geni-spi"; 862 reg = <0 0x00890000 0 0x4000>; 863 clock-names = "se"; 864 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 865 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 866 power-domains = <&rpmhpd RPMHPD_CX>; 867 operating-points-v2 = <&qup_opp_table_100mhz>; 868 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 869 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 870 dma-names = "tx", "rx"; 871 #address-cells = <1>; 872 #size-cells = <0>; 873 status = "disabled"; 874 }; 875 876 uart18: serial@890000 { 877 compatible = "qcom,geni-uart"; 878 reg = <0 0x00890000 0 0x4000>; 879 clock-names = "se"; 880 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 881 pinctrl-names = "default"; 882 pinctrl-0 = <&qup_uart18_default>; 883 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 884 power-domains = <&rpmhpd RPMHPD_CX>; 885 operating-points-v2 = <&qup_opp_table_100mhz>; 886 status = "disabled"; 887 }; 888 889 i2c19: i2c@894000 { 890 compatible = "qcom,geni-i2c"; 891 reg = <0 0x00894000 0 0x4000>; 892 clock-names = "se"; 893 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 894 pinctrl-names = "default"; 895 pinctrl-0 = <&qup_i2c19_default>; 896 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 897 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 898 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 899 dma-names = "tx", "rx"; 900 #address-cells = <1>; 901 #size-cells = <0>; 902 status = "disabled"; 903 }; 904 905 spi19: spi@894000 { 906 compatible = "qcom,geni-spi"; 907 reg = <0 0x00894000 0 0x4000>; 908 clock-names = "se"; 909 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 910 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 911 power-domains = <&rpmhpd RPMHPD_CX>; 912 operating-points-v2 = <&qup_opp_table_100mhz>; 913 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 914 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 915 dma-names = "tx", "rx"; 916 #address-cells = <1>; 917 #size-cells = <0>; 918 status = "disabled"; 919 }; 920 }; 921 922 gpi_dma0: dma-controller@9800000 { 923 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 924 reg = <0 0x09800000 0 0x60000>; 925 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 937 dma-channels = <12>; 938 dma-channel-mask = <0x7e>; 939 iommus = <&apps_smmu 0x5b6 0x0>; 940 #dma-cells = <3>; 941 status = "disabled"; 942 }; 943 944 qupv3_id_0: geniqup@9c0000 { 945 compatible = "qcom,geni-se-qup"; 946 reg = <0x0 0x009c0000 0x0 0x6000>; 947 clock-names = "m-ahb", "s-ahb"; 948 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 949 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 950 iommus = <&apps_smmu 0x5a3 0>; 951 #address-cells = <2>; 952 #size-cells = <2>; 953 ranges; 954 status = "disabled"; 955 956 i2c0: i2c@980000 { 957 compatible = "qcom,geni-i2c"; 958 reg = <0 0x00980000 0 0x4000>; 959 clock-names = "se"; 960 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 961 pinctrl-names = "default"; 962 pinctrl-0 = <&qup_i2c0_default>; 963 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 964 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 965 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 966 dma-names = "tx", "rx"; 967 #address-cells = <1>; 968 #size-cells = <0>; 969 status = "disabled"; 970 }; 971 972 spi0: spi@980000 { 973 compatible = "qcom,geni-spi"; 974 reg = <0 0x00980000 0 0x4000>; 975 clock-names = "se"; 976 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 977 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 978 power-domains = <&rpmhpd RPMHPD_CX>; 979 operating-points-v2 = <&qup_opp_table_100mhz>; 980 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 981 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 982 dma-names = "tx", "rx"; 983 #address-cells = <1>; 984 #size-cells = <0>; 985 status = "disabled"; 986 }; 987 988 i2c1: i2c@984000 { 989 compatible = "qcom,geni-i2c"; 990 reg = <0 0x00984000 0 0x4000>; 991 clock-names = "se"; 992 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 993 pinctrl-names = "default"; 994 pinctrl-0 = <&qup_i2c1_default>; 995 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 996 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 997 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 998 dma-names = "tx", "rx"; 999 #address-cells = <1>; 1000 #size-cells = <0>; 1001 status = "disabled"; 1002 }; 1003 1004 spi1: spi@984000 { 1005 compatible = "qcom,geni-spi"; 1006 reg = <0 0x00984000 0 0x4000>; 1007 clock-names = "se"; 1008 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1009 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1010 power-domains = <&rpmhpd RPMHPD_CX>; 1011 operating-points-v2 = <&qup_opp_table_100mhz>; 1012 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1013 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1014 dma-names = "tx", "rx"; 1015 #address-cells = <1>; 1016 #size-cells = <0>; 1017 status = "disabled"; 1018 }; 1019 1020 i2c2: i2c@988000 { 1021 compatible = "qcom,geni-i2c"; 1022 reg = <0 0x00988000 0 0x4000>; 1023 clock-names = "se"; 1024 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1025 pinctrl-names = "default"; 1026 pinctrl-0 = <&qup_i2c2_default>; 1027 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1028 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1029 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1030 dma-names = "tx", "rx"; 1031 #address-cells = <1>; 1032 #size-cells = <0>; 1033 status = "disabled"; 1034 }; 1035 1036 spi2: spi@988000 { 1037 compatible = "qcom,geni-spi"; 1038 reg = <0 0x00988000 0 0x4000>; 1039 clock-names = "se"; 1040 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1041 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1042 power-domains = <&rpmhpd RPMHPD_CX>; 1043 operating-points-v2 = <&qup_opp_table_100mhz>; 1044 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1045 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1046 dma-names = "tx", "rx"; 1047 #address-cells = <1>; 1048 #size-cells = <0>; 1049 status = "disabled"; 1050 }; 1051 1052 uart2: serial@98c000 { 1053 compatible = "qcom,geni-debug-uart"; 1054 reg = <0 0x0098c000 0 0x4000>; 1055 clock-names = "se"; 1056 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1057 pinctrl-names = "default"; 1058 pinctrl-0 = <&qup_uart3_default_state>; 1059 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1060 power-domains = <&rpmhpd RPMHPD_CX>; 1061 operating-points-v2 = <&qup_opp_table_100mhz>; 1062 status = "disabled"; 1063 }; 1064 1065 /* QUP no. 3 seems to be strictly SPI-only */ 1066 1067 spi3: spi@98c000 { 1068 compatible = "qcom,geni-spi"; 1069 reg = <0 0x0098c000 0 0x4000>; 1070 clock-names = "se"; 1071 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1072 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1073 power-domains = <&rpmhpd RPMHPD_CX>; 1074 operating-points-v2 = <&qup_opp_table_100mhz>; 1075 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1076 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1077 dma-names = "tx", "rx"; 1078 #address-cells = <1>; 1079 #size-cells = <0>; 1080 status = "disabled"; 1081 }; 1082 1083 i2c4: i2c@990000 { 1084 compatible = "qcom,geni-i2c"; 1085 reg = <0 0x00990000 0 0x4000>; 1086 clock-names = "se"; 1087 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1088 pinctrl-names = "default"; 1089 pinctrl-0 = <&qup_i2c4_default>; 1090 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1091 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1092 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1093 dma-names = "tx", "rx"; 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 status = "disabled"; 1097 }; 1098 1099 spi4: spi@990000 { 1100 compatible = "qcom,geni-spi"; 1101 reg = <0 0x00990000 0 0x4000>; 1102 clock-names = "se"; 1103 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1104 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1105 power-domains = <&rpmhpd RPMHPD_CX>; 1106 operating-points-v2 = <&qup_opp_table_100mhz>; 1107 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1108 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1109 dma-names = "tx", "rx"; 1110 #address-cells = <1>; 1111 #size-cells = <0>; 1112 status = "disabled"; 1113 }; 1114 1115 i2c5: i2c@994000 { 1116 compatible = "qcom,geni-i2c"; 1117 reg = <0 0x00994000 0 0x4000>; 1118 clock-names = "se"; 1119 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1120 pinctrl-names = "default"; 1121 pinctrl-0 = <&qup_i2c5_default>; 1122 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1123 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1124 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1125 dma-names = "tx", "rx"; 1126 #address-cells = <1>; 1127 #size-cells = <0>; 1128 status = "disabled"; 1129 }; 1130 1131 spi5: spi@994000 { 1132 compatible = "qcom,geni-spi"; 1133 reg = <0 0x00994000 0 0x4000>; 1134 clock-names = "se"; 1135 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1136 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1137 power-domains = <&rpmhpd RPMHPD_CX>; 1138 operating-points-v2 = <&qup_opp_table_100mhz>; 1139 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1140 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1141 dma-names = "tx", "rx"; 1142 #address-cells = <1>; 1143 #size-cells = <0>; 1144 status = "disabled"; 1145 }; 1146 1147 i2c6: i2c@998000 { 1148 compatible = "qcom,geni-i2c"; 1149 reg = <0 0x00998000 0 0x4000>; 1150 clock-names = "se"; 1151 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1152 pinctrl-names = "default"; 1153 pinctrl-0 = <&qup_i2c6_default>; 1154 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1155 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1156 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1157 dma-names = "tx", "rx"; 1158 #address-cells = <1>; 1159 #size-cells = <0>; 1160 status = "disabled"; 1161 }; 1162 1163 spi6: spi@998000 { 1164 compatible = "qcom,geni-spi"; 1165 reg = <0 0x00998000 0 0x4000>; 1166 clock-names = "se"; 1167 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1168 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1169 power-domains = <&rpmhpd RPMHPD_CX>; 1170 operating-points-v2 = <&qup_opp_table_100mhz>; 1171 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1172 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1173 dma-names = "tx", "rx"; 1174 #address-cells = <1>; 1175 #size-cells = <0>; 1176 status = "disabled"; 1177 }; 1178 1179 uart6: serial@998000 { 1180 compatible = "qcom,geni-uart"; 1181 reg = <0 0x00998000 0 0x4000>; 1182 clock-names = "se"; 1183 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1184 pinctrl-names = "default"; 1185 pinctrl-0 = <&qup_uart6_default>; 1186 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1187 power-domains = <&rpmhpd RPMHPD_CX>; 1188 operating-points-v2 = <&qup_opp_table_100mhz>; 1189 status = "disabled"; 1190 }; 1191 1192 i2c7: i2c@99c000 { 1193 compatible = "qcom,geni-i2c"; 1194 reg = <0 0x0099c000 0 0x4000>; 1195 clock-names = "se"; 1196 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1197 pinctrl-names = "default"; 1198 pinctrl-0 = <&qup_i2c7_default>; 1199 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1200 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1201 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1202 dma-names = "tx", "rx"; 1203 #address-cells = <1>; 1204 #size-cells = <0>; 1205 status = "disabled"; 1206 }; 1207 1208 spi7: spi@99c000 { 1209 compatible = "qcom,geni-spi"; 1210 reg = <0 0x0099c000 0 0x4000>; 1211 clock-names = "se"; 1212 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1213 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1214 power-domains = <&rpmhpd RPMHPD_CX>; 1215 operating-points-v2 = <&qup_opp_table_100mhz>; 1216 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1217 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1218 dma-names = "tx", "rx"; 1219 #address-cells = <1>; 1220 #size-cells = <0>; 1221 status = "disabled"; 1222 }; 1223 }; 1224 1225 gpi_dma1: dma-controller@a00000 { 1226 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 1227 reg = <0 0x00a00000 0 0x60000>; 1228 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1240 dma-channels = <12>; 1241 dma-channel-mask = <0xff>; 1242 iommus = <&apps_smmu 0x56 0x0>; 1243 #dma-cells = <3>; 1244 status = "disabled"; 1245 }; 1246 1247 qupv3_id_1: geniqup@ac0000 { 1248 compatible = "qcom,geni-se-qup"; 1249 reg = <0x0 0x00ac0000 0x0 0x6000>; 1250 clock-names = "m-ahb", "s-ahb"; 1251 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1252 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1253 iommus = <&apps_smmu 0x43 0>; 1254 #address-cells = <2>; 1255 #size-cells = <2>; 1256 ranges; 1257 status = "disabled"; 1258 1259 i2c8: i2c@a80000 { 1260 compatible = "qcom,geni-i2c"; 1261 reg = <0 0x00a80000 0 0x4000>; 1262 clock-names = "se"; 1263 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1264 pinctrl-names = "default"; 1265 pinctrl-0 = <&qup_i2c8_default>; 1266 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1267 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1268 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1269 dma-names = "tx", "rx"; 1270 #address-cells = <1>; 1271 #size-cells = <0>; 1272 status = "disabled"; 1273 }; 1274 1275 spi8: spi@a80000 { 1276 compatible = "qcom,geni-spi"; 1277 reg = <0 0x00a80000 0 0x4000>; 1278 clock-names = "se"; 1279 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1280 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1281 power-domains = <&rpmhpd RPMHPD_CX>; 1282 operating-points-v2 = <&qup_opp_table_120mhz>; 1283 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1284 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1285 dma-names = "tx", "rx"; 1286 #address-cells = <1>; 1287 #size-cells = <0>; 1288 status = "disabled"; 1289 }; 1290 1291 i2c9: i2c@a84000 { 1292 compatible = "qcom,geni-i2c"; 1293 reg = <0 0x00a84000 0 0x4000>; 1294 clock-names = "se"; 1295 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1296 pinctrl-names = "default"; 1297 pinctrl-0 = <&qup_i2c9_default>; 1298 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1299 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1300 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1301 dma-names = "tx", "rx"; 1302 #address-cells = <1>; 1303 #size-cells = <0>; 1304 status = "disabled"; 1305 }; 1306 1307 spi9: spi@a84000 { 1308 compatible = "qcom,geni-spi"; 1309 reg = <0 0x00a84000 0 0x4000>; 1310 clock-names = "se"; 1311 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1312 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1313 power-domains = <&rpmhpd RPMHPD_CX>; 1314 operating-points-v2 = <&qup_opp_table_100mhz>; 1315 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1316 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1317 dma-names = "tx", "rx"; 1318 #address-cells = <1>; 1319 #size-cells = <0>; 1320 status = "disabled"; 1321 }; 1322 1323 i2c10: i2c@a88000 { 1324 compatible = "qcom,geni-i2c"; 1325 reg = <0 0x00a88000 0 0x4000>; 1326 clock-names = "se"; 1327 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1328 pinctrl-names = "default"; 1329 pinctrl-0 = <&qup_i2c10_default>; 1330 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1331 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1332 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1333 dma-names = "tx", "rx"; 1334 #address-cells = <1>; 1335 #size-cells = <0>; 1336 status = "disabled"; 1337 }; 1338 1339 spi10: spi@a88000 { 1340 compatible = "qcom,geni-spi"; 1341 reg = <0 0x00a88000 0 0x4000>; 1342 clock-names = "se"; 1343 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1344 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1345 power-domains = <&rpmhpd RPMHPD_CX>; 1346 operating-points-v2 = <&qup_opp_table_100mhz>; 1347 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1348 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1349 dma-names = "tx", "rx"; 1350 #address-cells = <1>; 1351 #size-cells = <0>; 1352 status = "disabled"; 1353 }; 1354 1355 i2c11: i2c@a8c000 { 1356 compatible = "qcom,geni-i2c"; 1357 reg = <0 0x00a8c000 0 0x4000>; 1358 clock-names = "se"; 1359 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1360 pinctrl-names = "default"; 1361 pinctrl-0 = <&qup_i2c11_default>; 1362 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1363 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1364 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1365 dma-names = "tx", "rx"; 1366 #address-cells = <1>; 1367 #size-cells = <0>; 1368 status = "disabled"; 1369 }; 1370 1371 spi11: spi@a8c000 { 1372 compatible = "qcom,geni-spi"; 1373 reg = <0 0x00a8c000 0 0x4000>; 1374 clock-names = "se"; 1375 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1376 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1377 power-domains = <&rpmhpd RPMHPD_CX>; 1378 operating-points-v2 = <&qup_opp_table_100mhz>; 1379 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1380 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1381 dma-names = "tx", "rx"; 1382 #address-cells = <1>; 1383 #size-cells = <0>; 1384 status = "disabled"; 1385 }; 1386 1387 i2c12: i2c@a90000 { 1388 compatible = "qcom,geni-i2c"; 1389 reg = <0 0x00a90000 0 0x4000>; 1390 clock-names = "se"; 1391 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1392 pinctrl-names = "default"; 1393 pinctrl-0 = <&qup_i2c12_default>; 1394 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1395 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1396 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1397 dma-names = "tx", "rx"; 1398 #address-cells = <1>; 1399 #size-cells = <0>; 1400 status = "disabled"; 1401 }; 1402 1403 spi12: spi@a90000 { 1404 compatible = "qcom,geni-spi"; 1405 reg = <0 0x00a90000 0 0x4000>; 1406 clock-names = "se"; 1407 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1408 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1409 power-domains = <&rpmhpd RPMHPD_CX>; 1410 operating-points-v2 = <&qup_opp_table_100mhz>; 1411 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1412 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1413 dma-names = "tx", "rx"; 1414 #address-cells = <1>; 1415 #size-cells = <0>; 1416 status = "disabled"; 1417 }; 1418 1419 i2c13: i2c@a94000 { 1420 compatible = "qcom,geni-i2c"; 1421 reg = <0 0x00a94000 0 0x4000>; 1422 clock-names = "se"; 1423 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1424 pinctrl-names = "default"; 1425 pinctrl-0 = <&qup_i2c13_default>; 1426 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1427 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1428 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1429 dma-names = "tx", "rx"; 1430 #address-cells = <1>; 1431 #size-cells = <0>; 1432 status = "disabled"; 1433 }; 1434 1435 spi13: spi@a94000 { 1436 compatible = "qcom,geni-spi"; 1437 reg = <0 0x00a94000 0 0x4000>; 1438 clock-names = "se"; 1439 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1440 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1441 power-domains = <&rpmhpd RPMHPD_CX>; 1442 operating-points-v2 = <&qup_opp_table_100mhz>; 1443 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1444 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1445 dma-names = "tx", "rx"; 1446 #address-cells = <1>; 1447 #size-cells = <0>; 1448 status = "disabled"; 1449 }; 1450 }; 1451 1452 rng: rng@10d3000 { 1453 compatible = "qcom,prng-ee"; 1454 reg = <0 0x010d3000 0 0x1000>; 1455 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1456 clock-names = "core"; 1457 }; 1458 1459 config_noc: interconnect@1500000 { 1460 compatible = "qcom,sm8350-config-noc"; 1461 reg = <0 0x01500000 0 0xa580>; 1462 #interconnect-cells = <2>; 1463 qcom,bcm-voters = <&apps_bcm_voter>; 1464 }; 1465 1466 mc_virt: interconnect@1580000 { 1467 compatible = "qcom,sm8350-mc-virt"; 1468 reg = <0 0x01580000 0 0x1000>; 1469 #interconnect-cells = <2>; 1470 qcom,bcm-voters = <&apps_bcm_voter>; 1471 }; 1472 1473 system_noc: interconnect@1680000 { 1474 compatible = "qcom,sm8350-system-noc"; 1475 reg = <0 0x01680000 0 0x1c200>; 1476 #interconnect-cells = <2>; 1477 qcom,bcm-voters = <&apps_bcm_voter>; 1478 }; 1479 1480 aggre1_noc: interconnect@16e0000 { 1481 compatible = "qcom,sm8350-aggre1-noc"; 1482 reg = <0 0x016e0000 0 0x1f180>; 1483 #interconnect-cells = <2>; 1484 qcom,bcm-voters = <&apps_bcm_voter>; 1485 }; 1486 1487 aggre2_noc: interconnect@1700000 { 1488 compatible = "qcom,sm8350-aggre2-noc"; 1489 reg = <0 0x01700000 0 0x33000>; 1490 #interconnect-cells = <2>; 1491 qcom,bcm-voters = <&apps_bcm_voter>; 1492 }; 1493 1494 mmss_noc: interconnect@1740000 { 1495 compatible = "qcom,sm8350-mmss-noc"; 1496 reg = <0 0x01740000 0 0x1f080>; 1497 #interconnect-cells = <2>; 1498 qcom,bcm-voters = <&apps_bcm_voter>; 1499 }; 1500 1501 pcie0: pci@1c00000 { 1502 compatible = "qcom,pcie-sm8350"; 1503 reg = <0 0x01c00000 0 0x3000>, 1504 <0 0x60000000 0 0xf1d>, 1505 <0 0x60000f20 0 0xa8>, 1506 <0 0x60001000 0 0x1000>, 1507 <0 0x60100000 0 0x100000>; 1508 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1509 device_type = "pci"; 1510 linux,pci-domain = <0>; 1511 bus-range = <0x00 0xff>; 1512 num-lanes = <1>; 1513 1514 #address-cells = <3>; 1515 #size-cells = <2>; 1516 1517 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1518 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1519 1520 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1521 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1522 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1528 interrupt-names = "msi0", "msi1", "msi2", "msi3", 1529 "msi4", "msi5", "msi6", "msi7"; 1530 #interrupt-cells = <1>; 1531 interrupt-map-mask = <0 0 0 0x7>; 1532 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1533 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1534 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1535 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1536 1537 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1538 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1539 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1540 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1541 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1542 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1543 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1544 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1545 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; 1546 clock-names = "aux", 1547 "cfg", 1548 "bus_master", 1549 "bus_slave", 1550 "slave_q2a", 1551 "tbu", 1552 "ddrss_sf_tbu", 1553 "aggre1", 1554 "aggre0"; 1555 1556 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1557 <0x100 &apps_smmu 0x1c01 0x1>; 1558 1559 resets = <&gcc GCC_PCIE_0_BCR>; 1560 reset-names = "pci"; 1561 1562 power-domains = <&gcc PCIE_0_GDSC>; 1563 1564 phys = <&pcie0_phy>; 1565 phy-names = "pciephy"; 1566 1567 status = "disabled"; 1568 }; 1569 1570 pcie0_phy: phy@1c06000 { 1571 compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy"; 1572 reg = <0 0x01c06000 0 0x2000>; 1573 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1574 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1575 <&gcc GCC_PCIE_0_CLKREF_EN>, 1576 <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, 1577 <&gcc GCC_PCIE_0_PIPE_CLK>; 1578 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1579 1580 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1581 reset-names = "phy"; 1582 1583 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>; 1584 assigned-clock-rates = <100000000>; 1585 1586 #clock-cells = <0>; 1587 clock-output-names = "pcie_0_pipe_clk"; 1588 1589 #phy-cells = <0>; 1590 1591 status = "disabled"; 1592 }; 1593 1594 pcie1: pci@1c08000 { 1595 compatible = "qcom,pcie-sm8350"; 1596 reg = <0 0x01c08000 0 0x3000>, 1597 <0 0x40000000 0 0xf1d>, 1598 <0 0x40000f20 0 0xa8>, 1599 <0 0x40001000 0 0x1000>, 1600 <0 0x40100000 0 0x100000>; 1601 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1602 device_type = "pci"; 1603 linux,pci-domain = <1>; 1604 bus-range = <0x00 0xff>; 1605 num-lanes = <2>; 1606 1607 #address-cells = <3>; 1608 #size-cells = <2>; 1609 1610 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1611 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1612 1613 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1614 interrupt-names = "msi"; 1615 #interrupt-cells = <1>; 1616 interrupt-map-mask = <0 0 0 0x7>; 1617 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1618 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1619 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1620 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1621 1622 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1623 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1624 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1625 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1626 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1627 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1628 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1629 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1630 clock-names = "aux", 1631 "cfg", 1632 "bus_master", 1633 "bus_slave", 1634 "slave_q2a", 1635 "tbu", 1636 "ddrss_sf_tbu", 1637 "aggre1"; 1638 1639 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1640 <0x100 &apps_smmu 0x1c81 0x1>; 1641 1642 resets = <&gcc GCC_PCIE_1_BCR>; 1643 reset-names = "pci"; 1644 1645 power-domains = <&gcc PCIE_1_GDSC>; 1646 1647 phys = <&pcie1_phy>; 1648 phy-names = "pciephy"; 1649 1650 status = "disabled"; 1651 }; 1652 1653 pcie1_phy: phy@1c0e000 { 1654 compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy"; 1655 reg = <0 0x01c0e000 0 0x2000>; 1656 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1657 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1658 <&gcc GCC_PCIE_1_CLKREF_EN>, 1659 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, 1660 <&gcc GCC_PCIE_1_PIPE_CLK>; 1661 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1662 1663 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1664 reset-names = "phy"; 1665 1666 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1667 assigned-clock-rates = <100000000>; 1668 1669 #clock-cells = <0>; 1670 clock-output-names = "pcie_1_pipe_clk"; 1671 1672 #phy-cells = <0>; 1673 1674 status = "disabled"; 1675 }; 1676 1677 ufs_mem_hc: ufshc@1d84000 { 1678 compatible = "qcom,sm8350-ufshc", "qcom,ufshc", 1679 "jedec,ufs-2.0"; 1680 reg = <0 0x01d84000 0 0x3000>; 1681 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1682 phys = <&ufs_mem_phy_lanes>; 1683 phy-names = "ufsphy"; 1684 lanes-per-direction = <2>; 1685 #reset-cells = <1>; 1686 resets = <&gcc GCC_UFS_PHY_BCR>; 1687 reset-names = "rst"; 1688 1689 power-domains = <&gcc UFS_PHY_GDSC>; 1690 1691 iommus = <&apps_smmu 0xe0 0x0>; 1692 dma-coherent; 1693 1694 clock-names = 1695 "core_clk", 1696 "bus_aggr_clk", 1697 "iface_clk", 1698 "core_clk_unipro", 1699 "ref_clk", 1700 "tx_lane0_sync_clk", 1701 "rx_lane0_sync_clk", 1702 "rx_lane1_sync_clk"; 1703 clocks = 1704 <&gcc GCC_UFS_PHY_AXI_CLK>, 1705 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1706 <&gcc GCC_UFS_PHY_AHB_CLK>, 1707 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1708 <&rpmhcc RPMH_CXO_CLK>, 1709 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1710 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1711 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1712 freq-table-hz = 1713 <75000000 300000000>, 1714 <0 0>, 1715 <0 0>, 1716 <75000000 300000000>, 1717 <0 0>, 1718 <0 0>, 1719 <0 0>, 1720 <0 0>; 1721 status = "disabled"; 1722 }; 1723 1724 ufs_mem_phy: phy@1d87000 { 1725 compatible = "qcom,sm8350-qmp-ufs-phy"; 1726 reg = <0 0x01d87000 0 0x1c4>; 1727 #address-cells = <2>; 1728 #size-cells = <2>; 1729 ranges; 1730 clock-names = "ref", 1731 "ref_aux"; 1732 clocks = <&rpmhcc RPMH_CXO_CLK>, 1733 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1734 1735 resets = <&ufs_mem_hc 0>; 1736 reset-names = "ufsphy"; 1737 status = "disabled"; 1738 1739 ufs_mem_phy_lanes: phy@1d87400 { 1740 reg = <0 0x01d87400 0 0x188>, 1741 <0 0x01d87600 0 0x200>, 1742 <0 0x01d87c00 0 0x200>, 1743 <0 0x01d87800 0 0x188>, 1744 <0 0x01d87a00 0 0x200>; 1745 #clock-cells = <1>; 1746 #phy-cells = <0>; 1747 }; 1748 }; 1749 1750 cryptobam: dma-controller@1dc4000 { 1751 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1752 reg = <0 0x01dc4000 0 0x24000>; 1753 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1754 #dma-cells = <1>; 1755 qcom,ee = <0>; 1756 qcom,controlled-remotely; 1757 iommus = <&apps_smmu 0x594 0x0011>, 1758 <&apps_smmu 0x596 0x0011>; 1759 /* FIXME: Probing BAM DMA causes some abort and system hang */ 1760 status = "fail"; 1761 }; 1762 1763 crypto: crypto@1dfa000 { 1764 compatible = "qcom,sm8350-qce", "qcom,sm8150-qce", "qcom,qce"; 1765 reg = <0 0x01dfa000 0 0x6000>; 1766 dmas = <&cryptobam 4>, <&cryptobam 5>; 1767 dma-names = "rx", "tx"; 1768 iommus = <&apps_smmu 0x594 0x0011>, 1769 <&apps_smmu 0x596 0x0011>; 1770 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 1771 interconnect-names = "memory"; 1772 /* FIXME: dependency BAM DMA is disabled */ 1773 status = "disabled"; 1774 }; 1775 1776 ipa: ipa@1e40000 { 1777 compatible = "qcom,sm8350-ipa"; 1778 1779 iommus = <&apps_smmu 0x5c0 0x0>, 1780 <&apps_smmu 0x5c2 0x0>; 1781 reg = <0 0x01e40000 0 0x8000>, 1782 <0 0x01e50000 0 0x4b20>, 1783 <0 0x01e04000 0 0x23000>; 1784 reg-names = "ipa-reg", 1785 "ipa-shared", 1786 "gsi"; 1787 1788 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, 1789 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1790 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1791 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1792 interrupt-names = "ipa", 1793 "gsi", 1794 "ipa-clock-query", 1795 "ipa-setup-ready"; 1796 1797 clocks = <&rpmhcc RPMH_IPA_CLK>; 1798 clock-names = "core"; 1799 1800 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1801 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1802 interconnect-names = "memory", 1803 "config"; 1804 1805 qcom,qmp = <&aoss_qmp>; 1806 1807 qcom,smem-states = <&ipa_smp2p_out 0>, 1808 <&ipa_smp2p_out 1>; 1809 qcom,smem-state-names = "ipa-clock-enabled-valid", 1810 "ipa-clock-enabled"; 1811 1812 status = "disabled"; 1813 }; 1814 1815 tcsr_mutex: hwlock@1f40000 { 1816 compatible = "qcom,tcsr-mutex"; 1817 reg = <0x0 0x01f40000 0x0 0x40000>; 1818 #hwlock-cells = <1>; 1819 }; 1820 1821 lpass_tlmm: pinctrl@33c0000 { 1822 compatible = "qcom,sm8350-lpass-lpi-pinctrl"; 1823 reg = <0 0x033c0000 0 0x20000>, 1824 <0 0x03550000 0 0x10000>; 1825 1826 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1827 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1828 clock-names = "core", "audio"; 1829 1830 gpio-controller; 1831 #gpio-cells = <2>; 1832 gpio-ranges = <&lpass_tlmm 0 0 15>; 1833 }; 1834 1835 gpu: gpu@3d00000 { 1836 compatible = "qcom,adreno-660.1", "qcom,adreno"; 1837 1838 reg = <0 0x03d00000 0 0x40000>, 1839 <0 0x03d9e000 0 0x1000>, 1840 <0 0x03d61000 0 0x800>; 1841 reg-names = "kgsl_3d0_reg_memory", 1842 "cx_mem", 1843 "cx_dbgc"; 1844 1845 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1846 1847 iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>; 1848 1849 operating-points-v2 = <&gpu_opp_table>; 1850 1851 qcom,gmu = <&gmu>; 1852 1853 status = "disabled"; 1854 1855 zap-shader { 1856 memory-region = <&pil_gpu_mem>; 1857 }; 1858 1859 /* note: downstream checks gpu binning for 670 Mhz */ 1860 gpu_opp_table: opp-table { 1861 compatible = "operating-points-v2"; 1862 1863 opp-840000000 { 1864 opp-hz = /bits/ 64 <840000000>; 1865 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1866 }; 1867 1868 opp-778000000 { 1869 opp-hz = /bits/ 64 <778000000>; 1870 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1871 }; 1872 1873 opp-738000000 { 1874 opp-hz = /bits/ 64 <738000000>; 1875 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1876 }; 1877 1878 opp-676000000 { 1879 opp-hz = /bits/ 64 <676000000>; 1880 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1881 }; 1882 1883 opp-608000000 { 1884 opp-hz = /bits/ 64 <608000000>; 1885 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1886 }; 1887 1888 opp-540000000 { 1889 opp-hz = /bits/ 64 <540000000>; 1890 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1891 }; 1892 1893 opp-491000000 { 1894 opp-hz = /bits/ 64 <491000000>; 1895 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 1896 }; 1897 1898 opp-443000000 { 1899 opp-hz = /bits/ 64 <443000000>; 1900 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1901 }; 1902 1903 opp-379000000 { 1904 opp-hz = /bits/ 64 <379000000>; 1905 opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>; 1906 }; 1907 1908 opp-315000000 { 1909 opp-hz = /bits/ 64 <315000000>; 1910 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1911 }; 1912 }; 1913 }; 1914 1915 gmu: gmu@3d6a000 { 1916 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu"; 1917 1918 reg = <0 0x03d6a000 0 0x34000>, 1919 <0 0x03de0000 0 0x10000>, 1920 <0 0x0b290000 0 0x10000>; 1921 reg-names = "gmu", "rscc", "gmu_pdc"; 1922 1923 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1924 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1925 interrupt-names = "hfi", "gmu"; 1926 1927 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 1928 <&gpucc GPU_CC_CXO_CLK>, 1929 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1930 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1931 <&gpucc GPU_CC_AHB_CLK>, 1932 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 1933 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 1934 clock-names = "gmu", 1935 "cxo", 1936 "axi", 1937 "memnoc", 1938 "ahb", 1939 "hub", 1940 "smmu_vote"; 1941 1942 power-domains = <&gpucc GPU_CX_GDSC>, 1943 <&gpucc GPU_GX_GDSC>; 1944 power-domain-names = "cx", 1945 "gx"; 1946 1947 iommus = <&adreno_smmu 5 0x400>; 1948 1949 operating-points-v2 = <&gmu_opp_table>; 1950 1951 gmu_opp_table: opp-table { 1952 compatible = "operating-points-v2"; 1953 1954 opp-200000000 { 1955 opp-hz = /bits/ 64 <200000000>; 1956 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1957 }; 1958 }; 1959 }; 1960 1961 gpucc: clock-controller@3d90000 { 1962 compatible = "qcom,sm8350-gpucc"; 1963 reg = <0 0x03d90000 0 0x9000>; 1964 clocks = <&rpmhcc RPMH_CXO_CLK>, 1965 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1966 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1967 clock-names = "bi_tcxo", 1968 "gcc_gpu_gpll0_clk_src", 1969 "gcc_gpu_gpll0_div_clk_src"; 1970 #clock-cells = <1>; 1971 #reset-cells = <1>; 1972 #power-domain-cells = <1>; 1973 }; 1974 1975 adreno_smmu: iommu@3da0000 { 1976 compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu", 1977 "qcom,smmu-500", "arm,mmu-500"; 1978 reg = <0 0x03da0000 0 0x20000>; 1979 #iommu-cells = <2>; 1980 #global-interrupts = <2>; 1981 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 1982 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1983 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1984 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1985 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1986 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1987 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1988 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1989 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1990 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1991 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1992 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 1993 1994 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1995 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1996 <&gpucc GPU_CC_AHB_CLK>, 1997 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1998 <&gpucc GPU_CC_CX_GMU_CLK>, 1999 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2000 <&gpucc GPU_CC_HUB_AON_CLK>; 2001 clock-names = "bus", 2002 "iface", 2003 "ahb", 2004 "hlos1_vote_gpu_smmu", 2005 "cx_gmu", 2006 "hub_cx_int", 2007 "hub_aon"; 2008 2009 power-domains = <&gpucc GPU_CX_GDSC>; 2010 dma-coherent; 2011 }; 2012 2013 lpass_ag_noc: interconnect@3c40000 { 2014 compatible = "qcom,sm8350-lpass-ag-noc"; 2015 reg = <0 0x03c40000 0 0xf080>; 2016 #interconnect-cells = <2>; 2017 qcom,bcm-voters = <&apps_bcm_voter>; 2018 }; 2019 2020 mpss: remoteproc@4080000 { 2021 compatible = "qcom,sm8350-mpss-pas"; 2022 reg = <0x0 0x04080000 0x0 0x4040>; 2023 2024 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 2025 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2026 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2027 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2028 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2029 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2030 interrupt-names = "wdog", "fatal", "ready", "handover", 2031 "stop-ack", "shutdown-ack"; 2032 2033 clocks = <&rpmhcc RPMH_CXO_CLK>; 2034 clock-names = "xo"; 2035 2036 power-domains = <&rpmhpd RPMHPD_CX>, 2037 <&rpmhpd RPMHPD_MSS>; 2038 power-domain-names = "cx", "mss"; 2039 2040 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2041 2042 memory-region = <&pil_modem_mem>; 2043 2044 qcom,qmp = <&aoss_qmp>; 2045 2046 qcom,smem-states = <&smp2p_modem_out 0>; 2047 qcom,smem-state-names = "stop"; 2048 2049 status = "disabled"; 2050 2051 glink-edge { 2052 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2053 IPCC_MPROC_SIGNAL_GLINK_QMP 2054 IRQ_TYPE_EDGE_RISING>; 2055 mboxes = <&ipcc IPCC_CLIENT_MPSS 2056 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2057 label = "modem"; 2058 qcom,remote-pid = <1>; 2059 }; 2060 }; 2061 2062 slpi: remoteproc@5c00000 { 2063 compatible = "qcom,sm8350-slpi-pas"; 2064 reg = <0 0x05c00000 0 0x4000>; 2065 2066 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 2067 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2068 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2069 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2070 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2071 interrupt-names = "wdog", "fatal", "ready", 2072 "handover", "stop-ack"; 2073 2074 clocks = <&rpmhcc RPMH_CXO_CLK>; 2075 clock-names = "xo"; 2076 2077 power-domains = <&rpmhpd RPMHPD_LCX>, 2078 <&rpmhpd RPMHPD_LMX>; 2079 power-domain-names = "lcx", "lmx"; 2080 2081 memory-region = <&pil_slpi_mem>; 2082 2083 qcom,qmp = <&aoss_qmp>; 2084 2085 qcom,smem-states = <&smp2p_slpi_out 0>; 2086 qcom,smem-state-names = "stop"; 2087 2088 status = "disabled"; 2089 2090 glink-edge { 2091 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2092 IPCC_MPROC_SIGNAL_GLINK_QMP 2093 IRQ_TYPE_EDGE_RISING>; 2094 mboxes = <&ipcc IPCC_CLIENT_SLPI 2095 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2096 2097 label = "slpi"; 2098 qcom,remote-pid = <3>; 2099 2100 fastrpc { 2101 compatible = "qcom,fastrpc"; 2102 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2103 label = "sdsp"; 2104 qcom,non-secure-domain; 2105 #address-cells = <1>; 2106 #size-cells = <0>; 2107 2108 compute-cb@1 { 2109 compatible = "qcom,fastrpc-compute-cb"; 2110 reg = <1>; 2111 iommus = <&apps_smmu 0x0541 0x0>; 2112 }; 2113 2114 compute-cb@2 { 2115 compatible = "qcom,fastrpc-compute-cb"; 2116 reg = <2>; 2117 iommus = <&apps_smmu 0x0542 0x0>; 2118 }; 2119 2120 compute-cb@3 { 2121 compatible = "qcom,fastrpc-compute-cb"; 2122 reg = <3>; 2123 iommus = <&apps_smmu 0x0543 0x0>; 2124 /* note: shared-cb = <4> in downstream */ 2125 }; 2126 }; 2127 }; 2128 }; 2129 2130 sdhc_2: mmc@8804000 { 2131 compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5"; 2132 reg = <0 0x08804000 0 0x1000>; 2133 2134 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2135 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2136 interrupt-names = "hc_irq", "pwr_irq"; 2137 2138 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2139 <&gcc GCC_SDCC2_APPS_CLK>, 2140 <&rpmhcc RPMH_CXO_CLK>; 2141 clock-names = "iface", "core", "xo"; 2142 resets = <&gcc GCC_SDCC2_BCR>; 2143 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2144 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2145 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2146 iommus = <&apps_smmu 0x4a0 0x0>; 2147 power-domains = <&rpmhpd RPMHPD_CX>; 2148 operating-points-v2 = <&sdhc2_opp_table>; 2149 bus-width = <4>; 2150 dma-coherent; 2151 2152 status = "disabled"; 2153 2154 sdhc2_opp_table: opp-table { 2155 compatible = "operating-points-v2"; 2156 2157 opp-100000000 { 2158 opp-hz = /bits/ 64 <100000000>; 2159 required-opps = <&rpmhpd_opp_low_svs>; 2160 }; 2161 2162 opp-202000000 { 2163 opp-hz = /bits/ 64 <202000000>; 2164 required-opps = <&rpmhpd_opp_svs_l1>; 2165 }; 2166 }; 2167 }; 2168 2169 usb_1_hsphy: phy@88e3000 { 2170 compatible = "qcom,sm8350-usb-hs-phy", 2171 "qcom,usb-snps-hs-7nm-phy"; 2172 reg = <0 0x088e3000 0 0x400>; 2173 status = "disabled"; 2174 #phy-cells = <0>; 2175 2176 clocks = <&rpmhcc RPMH_CXO_CLK>; 2177 clock-names = "ref"; 2178 2179 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2180 }; 2181 2182 usb_2_hsphy: phy@88e4000 { 2183 compatible = "qcom,sm8250-usb-hs-phy", 2184 "qcom,usb-snps-hs-7nm-phy"; 2185 reg = <0 0x088e4000 0 0x400>; 2186 status = "disabled"; 2187 #phy-cells = <0>; 2188 2189 clocks = <&rpmhcc RPMH_CXO_CLK>; 2190 clock-names = "ref"; 2191 2192 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2193 }; 2194 2195 usb_1_qmpphy: phy@88e8000 { 2196 compatible = "qcom,sm8350-qmp-usb3-dp-phy"; 2197 reg = <0 0x088e8000 0 0x3000>; 2198 2199 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2200 <&rpmhcc RPMH_CXO_CLK>, 2201 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2202 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2203 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2204 2205 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2206 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2207 reset-names = "phy", "common"; 2208 2209 #clock-cells = <1>; 2210 #phy-cells = <1>; 2211 2212 status = "disabled"; 2213 2214 ports { 2215 #address-cells = <1>; 2216 #size-cells = <0>; 2217 2218 port@0 { 2219 reg = <0>; 2220 2221 usb_1_qmpphy_out: endpoint { 2222 }; 2223 }; 2224 2225 port@1 { 2226 reg = <1>; 2227 2228 usb_1_qmpphy_usb_ss_in: endpoint { 2229 }; 2230 }; 2231 2232 port@2 { 2233 reg = <2>; 2234 2235 usb_1_qmpphy_dp_in: endpoint { 2236 }; 2237 }; 2238 }; 2239 }; 2240 2241 usb_2_qmpphy: phy-wrapper@88eb000 { 2242 compatible = "qcom,sm8350-qmp-usb3-uni-phy"; 2243 reg = <0 0x088eb000 0 0x200>; 2244 status = "disabled"; 2245 #address-cells = <2>; 2246 #size-cells = <2>; 2247 ranges; 2248 2249 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2250 <&rpmhcc RPMH_CXO_CLK>, 2251 <&gcc GCC_USB3_SEC_CLKREF_EN>, 2252 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2253 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 2254 2255 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 2256 <&gcc GCC_USB3_PHY_SEC_BCR>; 2257 reset-names = "phy", "common"; 2258 2259 usb_2_ssphy: phy@88ebe00 { 2260 reg = <0 0x088ebe00 0 0x200>, 2261 <0 0x088ec000 0 0x200>, 2262 <0 0x088eb200 0 0x1100>; 2263 #phy-cells = <0>; 2264 #clock-cells = <0>; 2265 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2266 clock-names = "pipe0"; 2267 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2268 }; 2269 }; 2270 2271 dc_noc: interconnect@90c0000 { 2272 compatible = "qcom,sm8350-dc-noc"; 2273 reg = <0 0x090c0000 0 0x4200>; 2274 #interconnect-cells = <2>; 2275 qcom,bcm-voters = <&apps_bcm_voter>; 2276 }; 2277 2278 gem_noc: interconnect@9100000 { 2279 compatible = "qcom,sm8350-gem-noc"; 2280 reg = <0 0x09100000 0 0xb4000>; 2281 #interconnect-cells = <2>; 2282 qcom,bcm-voters = <&apps_bcm_voter>; 2283 }; 2284 2285 system-cache-controller@9200000 { 2286 compatible = "qcom,sm8350-llcc"; 2287 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 2288 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 2289 <0 0x09600000 0 0x58000>; 2290 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2291 "llcc3_base", "llcc_broadcast_base"; 2292 }; 2293 2294 compute_noc: interconnect@a0c0000 { 2295 compatible = "qcom,sm8350-compute-noc"; 2296 reg = <0 0x0a0c0000 0 0xa180>; 2297 #interconnect-cells = <2>; 2298 qcom,bcm-voters = <&apps_bcm_voter>; 2299 }; 2300 2301 usb_1: usb@a6f8800 { 2302 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2303 reg = <0 0x0a6f8800 0 0x400>; 2304 status = "disabled"; 2305 #address-cells = <2>; 2306 #size-cells = <2>; 2307 ranges; 2308 2309 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2310 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2311 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2312 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2313 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 2314 clock-names = "cfg_noc", 2315 "core", 2316 "iface", 2317 "sleep", 2318 "mock_utmi"; 2319 2320 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2321 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2322 assigned-clock-rates = <19200000>, <200000000>; 2323 2324 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2325 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 2326 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2327 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 2328 interrupt-names = "hs_phy_irq", 2329 "ss_phy_irq", 2330 "dm_hs_phy_irq", 2331 "dp_hs_phy_irq"; 2332 2333 power-domains = <&gcc USB30_PRIM_GDSC>; 2334 2335 resets = <&gcc GCC_USB30_PRIM_BCR>; 2336 2337 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2338 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 2339 interconnect-names = "usb-ddr", "apps-usb"; 2340 2341 usb_1_dwc3: usb@a600000 { 2342 compatible = "snps,dwc3"; 2343 reg = <0 0x0a600000 0 0xcd00>; 2344 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2345 iommus = <&apps_smmu 0x0 0x0>; 2346 snps,dis_u2_susphy_quirk; 2347 snps,dis_enblslpm_quirk; 2348 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 2349 phy-names = "usb2-phy", "usb3-phy"; 2350 2351 ports { 2352 #address-cells = <1>; 2353 #size-cells = <0>; 2354 2355 port@0 { 2356 reg = <0>; 2357 2358 usb_1_dwc3_hs: endpoint { 2359 }; 2360 }; 2361 2362 port@1 { 2363 reg = <1>; 2364 2365 usb_1_dwc3_ss: endpoint { 2366 }; 2367 }; 2368 }; 2369 }; 2370 }; 2371 2372 usb_2: usb@a8f8800 { 2373 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2374 reg = <0 0x0a8f8800 0 0x400>; 2375 status = "disabled"; 2376 #address-cells = <2>; 2377 #size-cells = <2>; 2378 ranges; 2379 2380 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2381 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2382 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2383 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2384 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2385 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2386 clock-names = "cfg_noc", 2387 "core", 2388 "iface", 2389 "sleep", 2390 "mock_utmi", 2391 "xo"; 2392 2393 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2394 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2395 assigned-clock-rates = <19200000>, <200000000>; 2396 2397 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2398 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, 2399 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 2400 <&pdc 12 IRQ_TYPE_EDGE_BOTH>; 2401 interrupt-names = "hs_phy_irq", 2402 "ss_phy_irq", 2403 "dm_hs_phy_irq", 2404 "dp_hs_phy_irq"; 2405 2406 power-domains = <&gcc USB30_SEC_GDSC>; 2407 2408 resets = <&gcc GCC_USB30_SEC_BCR>; 2409 2410 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 2411 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 2412 interconnect-names = "usb-ddr", "apps-usb"; 2413 2414 usb_2_dwc3: usb@a800000 { 2415 compatible = "snps,dwc3"; 2416 reg = <0 0x0a800000 0 0xcd00>; 2417 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2418 iommus = <&apps_smmu 0x20 0x0>; 2419 snps,dis_u2_susphy_quirk; 2420 snps,dis_enblslpm_quirk; 2421 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 2422 phy-names = "usb2-phy", "usb3-phy"; 2423 }; 2424 }; 2425 2426 mdss: display-subsystem@ae00000 { 2427 compatible = "qcom,sm8350-mdss"; 2428 reg = <0 0x0ae00000 0 0x1000>; 2429 reg-names = "mdss"; 2430 2431 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 2432 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 2433 interconnect-names = "mdp0-mem", "mdp1-mem"; 2434 2435 power-domains = <&dispcc MDSS_GDSC>; 2436 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2437 2438 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2439 <&gcc GCC_DISP_HF_AXI_CLK>, 2440 <&gcc GCC_DISP_SF_AXI_CLK>, 2441 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2442 clock-names = "iface", "bus", "nrt_bus", "core"; 2443 2444 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2445 interrupt-controller; 2446 #interrupt-cells = <1>; 2447 2448 iommus = <&apps_smmu 0x820 0x402>; 2449 2450 status = "disabled"; 2451 2452 #address-cells = <2>; 2453 #size-cells = <2>; 2454 ranges; 2455 2456 dpu_opp_table: opp-table { 2457 compatible = "operating-points-v2"; 2458 2459 /* TODO: opp-200000000 should work with 2460 * &rpmhpd_opp_low_svs, but one some of 2461 * sm8350_hdk boards reboot using this 2462 * opp. 2463 */ 2464 opp-200000000 { 2465 opp-hz = /bits/ 64 <200000000>; 2466 required-opps = <&rpmhpd_opp_svs>; 2467 }; 2468 2469 opp-300000000 { 2470 opp-hz = /bits/ 64 <300000000>; 2471 required-opps = <&rpmhpd_opp_svs>; 2472 }; 2473 2474 opp-345000000 { 2475 opp-hz = /bits/ 64 <345000000>; 2476 required-opps = <&rpmhpd_opp_svs_l1>; 2477 }; 2478 2479 opp-460000000 { 2480 opp-hz = /bits/ 64 <460000000>; 2481 required-opps = <&rpmhpd_opp_nom>; 2482 }; 2483 }; 2484 2485 mdss_mdp: display-controller@ae01000 { 2486 compatible = "qcom,sm8350-dpu"; 2487 reg = <0 0x0ae01000 0 0x8f000>, 2488 <0 0x0aeb0000 0 0x2008>; 2489 reg-names = "mdp", "vbif"; 2490 2491 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2492 <&gcc GCC_DISP_SF_AXI_CLK>, 2493 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2494 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2495 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2496 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2497 clock-names = "bus", 2498 "nrt_bus", 2499 "iface", 2500 "lut", 2501 "core", 2502 "vsync"; 2503 2504 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2505 assigned-clock-rates = <19200000>; 2506 2507 operating-points-v2 = <&dpu_opp_table>; 2508 power-domains = <&rpmhpd RPMHPD_MMCX>; 2509 2510 interrupt-parent = <&mdss>; 2511 interrupts = <0>; 2512 2513 ports { 2514 #address-cells = <1>; 2515 #size-cells = <0>; 2516 2517 port@0 { 2518 reg = <0>; 2519 dpu_intf1_out: endpoint { 2520 remote-endpoint = <&mdss_dsi0_in>; 2521 }; 2522 }; 2523 2524 port@1 { 2525 reg = <1>; 2526 dpu_intf2_out: endpoint { 2527 remote-endpoint = <&mdss_dsi1_in>; 2528 }; 2529 }; 2530 2531 port@2 { 2532 reg = <2>; 2533 dpu_intf0_out: endpoint { 2534 remote-endpoint = <&mdss_dp_in>; 2535 }; 2536 }; 2537 }; 2538 }; 2539 2540 mdss_dp: displayport-controller@ae90000 { 2541 compatible = "qcom,sm8350-dp"; 2542 reg = <0 0xae90000 0 0x200>, 2543 <0 0xae90200 0 0x200>, 2544 <0 0xae90400 0 0x600>, 2545 <0 0xae91000 0 0x400>, 2546 <0 0xae91400 0 0x400>; 2547 interrupt-parent = <&mdss>; 2548 interrupts = <12>; 2549 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2550 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 2551 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 2552 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 2553 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 2554 clock-names = "core_iface", 2555 "core_aux", 2556 "ctrl_link", 2557 "ctrl_link_iface", 2558 "stream_pixel"; 2559 2560 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 2561 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 2562 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2563 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2564 2565 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 2566 phy-names = "dp"; 2567 2568 #sound-dai-cells = <0>; 2569 2570 operating-points-v2 = <&dp_opp_table>; 2571 power-domains = <&rpmhpd RPMHPD_MMCX>; 2572 2573 status = "disabled"; 2574 2575 ports { 2576 #address-cells = <1>; 2577 #size-cells = <0>; 2578 2579 port@0 { 2580 reg = <0>; 2581 mdss_dp_in: endpoint { 2582 remote-endpoint = <&dpu_intf0_out>; 2583 }; 2584 }; 2585 }; 2586 2587 dp_opp_table: opp-table { 2588 compatible = "operating-points-v2"; 2589 2590 opp-160000000 { 2591 opp-hz = /bits/ 64 <160000000>; 2592 required-opps = <&rpmhpd_opp_low_svs>; 2593 }; 2594 2595 opp-270000000 { 2596 opp-hz = /bits/ 64 <270000000>; 2597 required-opps = <&rpmhpd_opp_svs>; 2598 }; 2599 2600 opp-540000000 { 2601 opp-hz = /bits/ 64 <540000000>; 2602 required-opps = <&rpmhpd_opp_svs_l1>; 2603 }; 2604 2605 opp-810000000 { 2606 opp-hz = /bits/ 64 <810000000>; 2607 required-opps = <&rpmhpd_opp_nom>; 2608 }; 2609 }; 2610 }; 2611 2612 mdss_dsi0: dsi@ae94000 { 2613 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2614 reg = <0 0x0ae94000 0 0x400>; 2615 reg-names = "dsi_ctrl"; 2616 2617 interrupt-parent = <&mdss>; 2618 interrupts = <4>; 2619 2620 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2621 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2622 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2623 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2624 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2625 <&gcc GCC_DISP_HF_AXI_CLK>; 2626 clock-names = "byte", 2627 "byte_intf", 2628 "pixel", 2629 "core", 2630 "iface", 2631 "bus"; 2632 2633 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2634 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2635 assigned-clock-parents = <&mdss_dsi0_phy 0>, 2636 <&mdss_dsi0_phy 1>; 2637 2638 operating-points-v2 = <&dsi0_opp_table>; 2639 power-domains = <&rpmhpd RPMHPD_MMCX>; 2640 2641 phys = <&mdss_dsi0_phy>; 2642 2643 #address-cells = <1>; 2644 #size-cells = <0>; 2645 2646 status = "disabled"; 2647 2648 dsi0_opp_table: opp-table { 2649 compatible = "operating-points-v2"; 2650 2651 /* TODO: opp-187500000 should work with 2652 * &rpmhpd_opp_low_svs, but one some of 2653 * sm8350_hdk boards reboot using this 2654 * opp. 2655 */ 2656 opp-187500000 { 2657 opp-hz = /bits/ 64 <187500000>; 2658 required-opps = <&rpmhpd_opp_svs>; 2659 }; 2660 2661 opp-300000000 { 2662 opp-hz = /bits/ 64 <300000000>; 2663 required-opps = <&rpmhpd_opp_svs>; 2664 }; 2665 2666 opp-358000000 { 2667 opp-hz = /bits/ 64 <358000000>; 2668 required-opps = <&rpmhpd_opp_svs_l1>; 2669 }; 2670 }; 2671 2672 ports { 2673 #address-cells = <1>; 2674 #size-cells = <0>; 2675 2676 port@0 { 2677 reg = <0>; 2678 mdss_dsi0_in: endpoint { 2679 remote-endpoint = <&dpu_intf1_out>; 2680 }; 2681 }; 2682 2683 port@1 { 2684 reg = <1>; 2685 mdss_dsi0_out: endpoint { 2686 }; 2687 }; 2688 }; 2689 }; 2690 2691 mdss_dsi0_phy: phy@ae94400 { 2692 compatible = "qcom,sm8350-dsi-phy-5nm"; 2693 reg = <0 0x0ae94400 0 0x200>, 2694 <0 0x0ae94600 0 0x280>, 2695 <0 0x0ae94900 0 0x27c>; 2696 reg-names = "dsi_phy", 2697 "dsi_phy_lane", 2698 "dsi_pll"; 2699 2700 #clock-cells = <1>; 2701 #phy-cells = <0>; 2702 2703 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2704 <&rpmhcc RPMH_CXO_CLK>; 2705 clock-names = "iface", "ref"; 2706 2707 status = "disabled"; 2708 }; 2709 2710 mdss_dsi1: dsi@ae96000 { 2711 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2712 reg = <0 0x0ae96000 0 0x400>; 2713 reg-names = "dsi_ctrl"; 2714 2715 interrupt-parent = <&mdss>; 2716 interrupts = <5>; 2717 2718 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2719 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2720 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2721 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2722 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2723 <&gcc GCC_DISP_HF_AXI_CLK>; 2724 clock-names = "byte", 2725 "byte_intf", 2726 "pixel", 2727 "core", 2728 "iface", 2729 "bus"; 2730 2731 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 2732 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2733 assigned-clock-parents = <&mdss_dsi1_phy 0>, 2734 <&mdss_dsi1_phy 1>; 2735 2736 operating-points-v2 = <&dsi1_opp_table>; 2737 power-domains = <&rpmhpd RPMHPD_MMCX>; 2738 2739 phys = <&mdss_dsi1_phy>; 2740 2741 #address-cells = <1>; 2742 #size-cells = <0>; 2743 2744 status = "disabled"; 2745 2746 dsi1_opp_table: opp-table { 2747 compatible = "operating-points-v2"; 2748 2749 /* TODO: opp-187500000 should work with 2750 * &rpmhpd_opp_low_svs, but one some of 2751 * sm8350_hdk boards reboot using this 2752 * opp. 2753 */ 2754 opp-187500000 { 2755 opp-hz = /bits/ 64 <187500000>; 2756 required-opps = <&rpmhpd_opp_svs>; 2757 }; 2758 2759 opp-300000000 { 2760 opp-hz = /bits/ 64 <300000000>; 2761 required-opps = <&rpmhpd_opp_svs>; 2762 }; 2763 2764 opp-358000000 { 2765 opp-hz = /bits/ 64 <358000000>; 2766 required-opps = <&rpmhpd_opp_svs_l1>; 2767 }; 2768 }; 2769 2770 ports { 2771 #address-cells = <1>; 2772 #size-cells = <0>; 2773 2774 port@0 { 2775 reg = <0>; 2776 mdss_dsi1_in: endpoint { 2777 remote-endpoint = <&dpu_intf2_out>; 2778 }; 2779 }; 2780 2781 port@1 { 2782 reg = <1>; 2783 mdss_dsi1_out: endpoint { 2784 }; 2785 }; 2786 }; 2787 }; 2788 2789 mdss_dsi1_phy: phy@ae96400 { 2790 compatible = "qcom,sm8350-dsi-phy-5nm"; 2791 reg = <0 0x0ae96400 0 0x200>, 2792 <0 0x0ae96600 0 0x280>, 2793 <0 0x0ae96900 0 0x27c>; 2794 reg-names = "dsi_phy", 2795 "dsi_phy_lane", 2796 "dsi_pll"; 2797 2798 #clock-cells = <1>; 2799 #phy-cells = <0>; 2800 2801 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2802 <&rpmhcc RPMH_CXO_CLK>; 2803 clock-names = "iface", "ref"; 2804 2805 status = "disabled"; 2806 }; 2807 }; 2808 2809 dispcc: clock-controller@af00000 { 2810 compatible = "qcom,sm8350-dispcc"; 2811 reg = <0 0x0af00000 0 0x10000>; 2812 clocks = <&rpmhcc RPMH_CXO_CLK>, 2813 <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, 2814 <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, 2815 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2816 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2817 clock-names = "bi_tcxo", 2818 "dsi0_phy_pll_out_byteclk", 2819 "dsi0_phy_pll_out_dsiclk", 2820 "dsi1_phy_pll_out_byteclk", 2821 "dsi1_phy_pll_out_dsiclk", 2822 "dp_phy_pll_link_clk", 2823 "dp_phy_pll_vco_div_clk"; 2824 #clock-cells = <1>; 2825 #reset-cells = <1>; 2826 #power-domain-cells = <1>; 2827 2828 power-domains = <&rpmhpd RPMHPD_MMCX>; 2829 }; 2830 2831 pdc: interrupt-controller@b220000 { 2832 compatible = "qcom,sm8350-pdc", "qcom,pdc"; 2833 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 2834 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, 2835 <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, 2836 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, 2837 <156 716 12>; 2838 #interrupt-cells = <2>; 2839 interrupt-parent = <&intc>; 2840 interrupt-controller; 2841 }; 2842 2843 tsens0: thermal-sensor@c263000 { 2844 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 2845 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2846 <0 0x0c222000 0 0x8>; /* SROT */ 2847 #qcom,sensors = <15>; 2848 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 2849 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 2850 interrupt-names = "uplow", "critical"; 2851 #thermal-sensor-cells = <1>; 2852 }; 2853 2854 tsens1: thermal-sensor@c265000 { 2855 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 2856 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2857 <0 0x0c223000 0 0x8>; /* SROT */ 2858 #qcom,sensors = <14>; 2859 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 2860 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 2861 interrupt-names = "uplow", "critical"; 2862 #thermal-sensor-cells = <1>; 2863 }; 2864 2865 aoss_qmp: power-management@c300000 { 2866 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; 2867 reg = <0 0x0c300000 0 0x400>; 2868 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2869 IRQ_TYPE_EDGE_RISING>; 2870 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2871 2872 #clock-cells = <0>; 2873 }; 2874 2875 sram@c3f0000 { 2876 compatible = "qcom,rpmh-stats"; 2877 reg = <0 0x0c3f0000 0 0x400>; 2878 }; 2879 2880 spmi_bus: spmi@c440000 { 2881 compatible = "qcom,spmi-pmic-arb"; 2882 reg = <0x0 0x0c440000 0x0 0x1100>, 2883 <0x0 0x0c600000 0x0 0x2000000>, 2884 <0x0 0x0e600000 0x0 0x100000>, 2885 <0x0 0x0e700000 0x0 0xa0000>, 2886 <0x0 0x0c40a000 0x0 0x26000>; 2887 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2888 interrupt-names = "periph_irq"; 2889 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2890 qcom,ee = <0>; 2891 qcom,channel = <0>; 2892 #address-cells = <2>; 2893 #size-cells = <0>; 2894 interrupt-controller; 2895 #interrupt-cells = <4>; 2896 }; 2897 2898 tlmm: pinctrl@f100000 { 2899 compatible = "qcom,sm8350-tlmm"; 2900 reg = <0 0x0f100000 0 0x300000>; 2901 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2902 gpio-controller; 2903 #gpio-cells = <2>; 2904 interrupt-controller; 2905 #interrupt-cells = <2>; 2906 gpio-ranges = <&tlmm 0 0 204>; 2907 wakeup-parent = <&pdc>; 2908 2909 sdc2_default_state: sdc2-default-state { 2910 clk-pins { 2911 pins = "sdc2_clk"; 2912 drive-strength = <16>; 2913 bias-disable; 2914 }; 2915 2916 cmd-pins { 2917 pins = "sdc2_cmd"; 2918 drive-strength = <16>; 2919 bias-pull-up; 2920 }; 2921 2922 data-pins { 2923 pins = "sdc2_data"; 2924 drive-strength = <16>; 2925 bias-pull-up; 2926 }; 2927 }; 2928 2929 sdc2_sleep_state: sdc2-sleep-state { 2930 clk-pins { 2931 pins = "sdc2_clk"; 2932 drive-strength = <2>; 2933 bias-disable; 2934 }; 2935 2936 cmd-pins { 2937 pins = "sdc2_cmd"; 2938 drive-strength = <2>; 2939 bias-pull-up; 2940 }; 2941 2942 data-pins { 2943 pins = "sdc2_data"; 2944 drive-strength = <2>; 2945 bias-pull-up; 2946 }; 2947 }; 2948 2949 qup_uart3_default_state: qup-uart3-default-state { 2950 rx-pins { 2951 pins = "gpio18"; 2952 function = "qup3"; 2953 }; 2954 tx-pins { 2955 pins = "gpio19"; 2956 function = "qup3"; 2957 }; 2958 }; 2959 2960 qup_uart6_default: qup-uart6-default-state { 2961 pins = "gpio30", "gpio31"; 2962 function = "qup6"; 2963 drive-strength = <2>; 2964 bias-disable; 2965 }; 2966 2967 qup_uart18_default: qup-uart18-default-state { 2968 pins = "gpio68", "gpio69"; 2969 function = "qup18"; 2970 drive-strength = <2>; 2971 bias-disable; 2972 }; 2973 2974 qup_i2c0_default: qup-i2c0-default-state { 2975 pins = "gpio4", "gpio5"; 2976 function = "qup0"; 2977 drive-strength = <2>; 2978 bias-pull-up; 2979 }; 2980 2981 qup_i2c1_default: qup-i2c1-default-state { 2982 pins = "gpio8", "gpio9"; 2983 function = "qup1"; 2984 drive-strength = <2>; 2985 bias-pull-up; 2986 }; 2987 2988 qup_i2c2_default: qup-i2c2-default-state { 2989 pins = "gpio12", "gpio13"; 2990 function = "qup2"; 2991 drive-strength = <2>; 2992 bias-pull-up; 2993 }; 2994 2995 qup_i2c4_default: qup-i2c4-default-state { 2996 pins = "gpio20", "gpio21"; 2997 function = "qup4"; 2998 drive-strength = <2>; 2999 bias-pull-up; 3000 }; 3001 3002 qup_i2c5_default: qup-i2c5-default-state { 3003 pins = "gpio24", "gpio25"; 3004 function = "qup5"; 3005 drive-strength = <2>; 3006 bias-pull-up; 3007 }; 3008 3009 qup_i2c6_default: qup-i2c6-default-state { 3010 pins = "gpio28", "gpio29"; 3011 function = "qup6"; 3012 drive-strength = <2>; 3013 bias-pull-up; 3014 }; 3015 3016 qup_i2c7_default: qup-i2c7-default-state { 3017 pins = "gpio32", "gpio33"; 3018 function = "qup7"; 3019 drive-strength = <2>; 3020 bias-disable; 3021 }; 3022 3023 qup_i2c8_default: qup-i2c8-default-state { 3024 pins = "gpio36", "gpio37"; 3025 function = "qup8"; 3026 drive-strength = <2>; 3027 bias-pull-up; 3028 }; 3029 3030 qup_i2c9_default: qup-i2c9-default-state { 3031 pins = "gpio40", "gpio41"; 3032 function = "qup9"; 3033 drive-strength = <2>; 3034 bias-pull-up; 3035 }; 3036 3037 qup_i2c10_default: qup-i2c10-default-state { 3038 pins = "gpio44", "gpio45"; 3039 function = "qup10"; 3040 drive-strength = <2>; 3041 bias-pull-up; 3042 }; 3043 3044 qup_i2c11_default: qup-i2c11-default-state { 3045 pins = "gpio48", "gpio49"; 3046 function = "qup11"; 3047 drive-strength = <2>; 3048 bias-pull-up; 3049 }; 3050 3051 qup_i2c12_default: qup-i2c12-default-state { 3052 pins = "gpio52", "gpio53"; 3053 function = "qup12"; 3054 drive-strength = <2>; 3055 bias-pull-up; 3056 }; 3057 3058 qup_i2c13_default: qup-i2c13-default-state { 3059 pins = "gpio0", "gpio1"; 3060 function = "qup13"; 3061 drive-strength = <2>; 3062 bias-pull-up; 3063 }; 3064 3065 qup_i2c14_default: qup-i2c14-default-state { 3066 pins = "gpio56", "gpio57"; 3067 function = "qup14"; 3068 drive-strength = <2>; 3069 bias-disable; 3070 }; 3071 3072 qup_i2c15_default: qup-i2c15-default-state { 3073 pins = "gpio60", "gpio61"; 3074 function = "qup15"; 3075 drive-strength = <2>; 3076 bias-disable; 3077 }; 3078 3079 qup_i2c16_default: qup-i2c16-default-state { 3080 pins = "gpio64", "gpio65"; 3081 function = "qup16"; 3082 drive-strength = <2>; 3083 bias-disable; 3084 }; 3085 3086 qup_i2c17_default: qup-i2c17-default-state { 3087 pins = "gpio72", "gpio73"; 3088 function = "qup17"; 3089 drive-strength = <2>; 3090 bias-disable; 3091 }; 3092 3093 qup_i2c19_default: qup-i2c19-default-state { 3094 pins = "gpio76", "gpio77"; 3095 function = "qup19"; 3096 drive-strength = <2>; 3097 bias-disable; 3098 }; 3099 }; 3100 3101 apps_smmu: iommu@15000000 { 3102 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; 3103 reg = <0 0x15000000 0 0x100000>; 3104 #iommu-cells = <2>; 3105 #global-interrupts = <2>; 3106 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 3107 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3108 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3109 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3110 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3111 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3112 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3113 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3114 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3115 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3116 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3117 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3118 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3119 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3120 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3121 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3122 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3123 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3124 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3125 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3126 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3127 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3128 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3129 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3130 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3131 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3132 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3133 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3134 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3135 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3136 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3137 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3138 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3139 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3140 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3141 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3142 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3143 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3144 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3145 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3146 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3147 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3148 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3149 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3150 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3151 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3152 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3153 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3154 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3155 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3156 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3157 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3158 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3159 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3160 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3161 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3162 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3163 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3164 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3165 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3166 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3167 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3168 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3169 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3170 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3171 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3172 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3173 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3174 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3175 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3176 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3177 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3178 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3179 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3180 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3181 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3182 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3183 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3184 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3185 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3186 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3187 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3188 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3189 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3190 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3191 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3192 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3193 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3194 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3195 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3196 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3197 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3198 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3199 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3200 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3201 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3202 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 3203 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 3204 }; 3205 3206 adsp: remoteproc@17300000 { 3207 compatible = "qcom,sm8350-adsp-pas"; 3208 reg = <0 0x17300000 0 0x100>; 3209 3210 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 3211 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3212 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3213 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3214 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 3215 interrupt-names = "wdog", "fatal", "ready", 3216 "handover", "stop-ack"; 3217 3218 clocks = <&rpmhcc RPMH_CXO_CLK>; 3219 clock-names = "xo"; 3220 3221 power-domains = <&rpmhpd RPMHPD_LCX>, 3222 <&rpmhpd RPMHPD_LMX>; 3223 power-domain-names = "lcx", "lmx"; 3224 3225 memory-region = <&pil_adsp_mem>; 3226 3227 qcom,qmp = <&aoss_qmp>; 3228 3229 qcom,smem-states = <&smp2p_adsp_out 0>; 3230 qcom,smem-state-names = "stop"; 3231 3232 status = "disabled"; 3233 3234 glink-edge { 3235 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3236 IPCC_MPROC_SIGNAL_GLINK_QMP 3237 IRQ_TYPE_EDGE_RISING>; 3238 mboxes = <&ipcc IPCC_CLIENT_LPASS 3239 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3240 3241 label = "lpass"; 3242 qcom,remote-pid = <2>; 3243 3244 apr { 3245 compatible = "qcom,apr-v2"; 3246 qcom,glink-channels = "apr_audio_svc"; 3247 qcom,domain = <APR_DOMAIN_ADSP>; 3248 #address-cells = <1>; 3249 #size-cells = <0>; 3250 3251 service@3 { 3252 reg = <APR_SVC_ADSP_CORE>; 3253 compatible = "qcom,q6core"; 3254 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3255 }; 3256 3257 q6afe: service@4 { 3258 compatible = "qcom,q6afe"; 3259 reg = <APR_SVC_AFE>; 3260 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3261 3262 q6afedai: dais { 3263 compatible = "qcom,q6afe-dais"; 3264 #address-cells = <1>; 3265 #size-cells = <0>; 3266 #sound-dai-cells = <1>; 3267 }; 3268 3269 q6afecc: clock-controller { 3270 compatible = "qcom,q6afe-clocks"; 3271 #clock-cells = <2>; 3272 }; 3273 }; 3274 3275 q6asm: service@7 { 3276 compatible = "qcom,q6asm"; 3277 reg = <APR_SVC_ASM>; 3278 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3279 3280 q6asmdai: dais { 3281 compatible = "qcom,q6asm-dais"; 3282 #address-cells = <1>; 3283 #size-cells = <0>; 3284 #sound-dai-cells = <1>; 3285 iommus = <&apps_smmu 0x1801 0x0>; 3286 3287 dai@0 { 3288 reg = <0>; 3289 }; 3290 3291 dai@1 { 3292 reg = <1>; 3293 }; 3294 3295 dai@2 { 3296 reg = <2>; 3297 }; 3298 }; 3299 }; 3300 3301 q6adm: service@8 { 3302 compatible = "qcom,q6adm"; 3303 reg = <APR_SVC_ADM>; 3304 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3305 3306 q6routing: routing { 3307 compatible = "qcom,q6adm-routing"; 3308 #sound-dai-cells = <0>; 3309 }; 3310 }; 3311 }; 3312 3313 fastrpc { 3314 compatible = "qcom,fastrpc"; 3315 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3316 label = "adsp"; 3317 qcom,non-secure-domain; 3318 #address-cells = <1>; 3319 #size-cells = <0>; 3320 3321 compute-cb@3 { 3322 compatible = "qcom,fastrpc-compute-cb"; 3323 reg = <3>; 3324 iommus = <&apps_smmu 0x1803 0x0>; 3325 }; 3326 3327 compute-cb@4 { 3328 compatible = "qcom,fastrpc-compute-cb"; 3329 reg = <4>; 3330 iommus = <&apps_smmu 0x1804 0x0>; 3331 }; 3332 3333 compute-cb@5 { 3334 compatible = "qcom,fastrpc-compute-cb"; 3335 reg = <5>; 3336 iommus = <&apps_smmu 0x1805 0x0>; 3337 }; 3338 }; 3339 }; 3340 }; 3341 3342 intc: interrupt-controller@17a00000 { 3343 compatible = "arm,gic-v3"; 3344 #interrupt-cells = <3>; 3345 interrupt-controller; 3346 #redistributor-regions = <1>; 3347 redistributor-stride = <0 0x20000>; 3348 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3349 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3350 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3351 }; 3352 3353 timer@17c20000 { 3354 compatible = "arm,armv7-timer-mem"; 3355 #address-cells = <1>; 3356 #size-cells = <1>; 3357 ranges = <0 0 0 0x20000000>; 3358 reg = <0x0 0x17c20000 0x0 0x1000>; 3359 clock-frequency = <19200000>; 3360 3361 frame@17c21000 { 3362 frame-number = <0>; 3363 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3364 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3365 reg = <0x17c21000 0x1000>, 3366 <0x17c22000 0x1000>; 3367 }; 3368 3369 frame@17c23000 { 3370 frame-number = <1>; 3371 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3372 reg = <0x17c23000 0x1000>; 3373 status = "disabled"; 3374 }; 3375 3376 frame@17c25000 { 3377 frame-number = <2>; 3378 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3379 reg = <0x17c25000 0x1000>; 3380 status = "disabled"; 3381 }; 3382 3383 frame@17c27000 { 3384 frame-number = <3>; 3385 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3386 reg = <0x17c27000 0x1000>; 3387 status = "disabled"; 3388 }; 3389 3390 frame@17c29000 { 3391 frame-number = <4>; 3392 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3393 reg = <0x17c29000 0x1000>; 3394 status = "disabled"; 3395 }; 3396 3397 frame@17c2b000 { 3398 frame-number = <5>; 3399 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3400 reg = <0x17c2b000 0x1000>; 3401 status = "disabled"; 3402 }; 3403 3404 frame@17c2d000 { 3405 frame-number = <6>; 3406 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3407 reg = <0x17c2d000 0x1000>; 3408 status = "disabled"; 3409 }; 3410 }; 3411 3412 apps_rsc: rsc@18200000 { 3413 label = "apps_rsc"; 3414 compatible = "qcom,rpmh-rsc"; 3415 reg = <0x0 0x18200000 0x0 0x10000>, 3416 <0x0 0x18210000 0x0 0x10000>, 3417 <0x0 0x18220000 0x0 0x10000>; 3418 reg-names = "drv-0", "drv-1", "drv-2"; 3419 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3420 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3421 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3422 qcom,tcs-offset = <0xd00>; 3423 qcom,drv-id = <2>; 3424 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 3425 <WAKE_TCS 3>, <CONTROL_TCS 0>; 3426 power-domains = <&CLUSTER_PD>; 3427 3428 rpmhcc: clock-controller { 3429 compatible = "qcom,sm8350-rpmh-clk"; 3430 #clock-cells = <1>; 3431 clock-names = "xo"; 3432 clocks = <&xo_board>; 3433 }; 3434 3435 rpmhpd: power-controller { 3436 compatible = "qcom,sm8350-rpmhpd"; 3437 #power-domain-cells = <1>; 3438 operating-points-v2 = <&rpmhpd_opp_table>; 3439 3440 rpmhpd_opp_table: opp-table { 3441 compatible = "operating-points-v2"; 3442 3443 rpmhpd_opp_ret: opp1 { 3444 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3445 }; 3446 3447 rpmhpd_opp_min_svs: opp2 { 3448 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3449 }; 3450 3451 rpmhpd_opp_low_svs: opp3 { 3452 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3453 }; 3454 3455 rpmhpd_opp_svs: opp4 { 3456 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3457 }; 3458 3459 rpmhpd_opp_svs_l1: opp5 { 3460 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3461 }; 3462 3463 rpmhpd_opp_nom: opp6 { 3464 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3465 }; 3466 3467 rpmhpd_opp_nom_l1: opp7 { 3468 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3469 }; 3470 3471 rpmhpd_opp_nom_l2: opp8 { 3472 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3473 }; 3474 3475 rpmhpd_opp_turbo: opp9 { 3476 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3477 }; 3478 3479 rpmhpd_opp_turbo_l1: opp10 { 3480 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3481 }; 3482 }; 3483 }; 3484 3485 apps_bcm_voter: bcm-voter { 3486 compatible = "qcom,bcm-voter"; 3487 }; 3488 }; 3489 3490 cpufreq_hw: cpufreq@18591000 { 3491 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss"; 3492 reg = <0 0x18591000 0 0x1000>, 3493 <0 0x18592000 0 0x1000>, 3494 <0 0x18593000 0 0x1000>; 3495 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3496 3497 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 3498 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3499 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 3500 interrupt-names = "dcvsh-irq-0", 3501 "dcvsh-irq-1", 3502 "dcvsh-irq-2"; 3503 3504 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3505 clock-names = "xo", "alternate"; 3506 3507 #freq-domain-cells = <1>; 3508 #clock-cells = <1>; 3509 }; 3510 3511 cdsp: remoteproc@98900000 { 3512 compatible = "qcom,sm8350-cdsp-pas"; 3513 reg = <0 0x98900000 0 0x1400000>; 3514 3515 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 3516 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3517 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3518 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3519 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3520 interrupt-names = "wdog", "fatal", "ready", 3521 "handover", "stop-ack"; 3522 3523 clocks = <&rpmhcc RPMH_CXO_CLK>; 3524 clock-names = "xo"; 3525 3526 power-domains = <&rpmhpd RPMHPD_CX>, 3527 <&rpmhpd RPMHPD_MXC>; 3528 power-domain-names = "cx", "mxc"; 3529 3530 interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 3531 3532 memory-region = <&pil_cdsp_mem>; 3533 3534 qcom,qmp = <&aoss_qmp>; 3535 3536 qcom,smem-states = <&smp2p_cdsp_out 0>; 3537 qcom,smem-state-names = "stop"; 3538 3539 status = "disabled"; 3540 3541 glink-edge { 3542 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3543 IPCC_MPROC_SIGNAL_GLINK_QMP 3544 IRQ_TYPE_EDGE_RISING>; 3545 mboxes = <&ipcc IPCC_CLIENT_CDSP 3546 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3547 3548 label = "cdsp"; 3549 qcom,remote-pid = <5>; 3550 3551 fastrpc { 3552 compatible = "qcom,fastrpc"; 3553 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3554 label = "cdsp"; 3555 qcom,non-secure-domain; 3556 #address-cells = <1>; 3557 #size-cells = <0>; 3558 3559 compute-cb@1 { 3560 compatible = "qcom,fastrpc-compute-cb"; 3561 reg = <1>; 3562 iommus = <&apps_smmu 0x2161 0x0400>, 3563 <&apps_smmu 0x1181 0x0420>; 3564 }; 3565 3566 compute-cb@2 { 3567 compatible = "qcom,fastrpc-compute-cb"; 3568 reg = <2>; 3569 iommus = <&apps_smmu 0x2162 0x0400>, 3570 <&apps_smmu 0x1182 0x0420>; 3571 }; 3572 3573 compute-cb@3 { 3574 compatible = "qcom,fastrpc-compute-cb"; 3575 reg = <3>; 3576 iommus = <&apps_smmu 0x2163 0x0400>, 3577 <&apps_smmu 0x1183 0x0420>; 3578 }; 3579 3580 compute-cb@4 { 3581 compatible = "qcom,fastrpc-compute-cb"; 3582 reg = <4>; 3583 iommus = <&apps_smmu 0x2164 0x0400>, 3584 <&apps_smmu 0x1184 0x0420>; 3585 }; 3586 3587 compute-cb@5 { 3588 compatible = "qcom,fastrpc-compute-cb"; 3589 reg = <5>; 3590 iommus = <&apps_smmu 0x2165 0x0400>, 3591 <&apps_smmu 0x1185 0x0420>; 3592 }; 3593 3594 compute-cb@6 { 3595 compatible = "qcom,fastrpc-compute-cb"; 3596 reg = <6>; 3597 iommus = <&apps_smmu 0x2166 0x0400>, 3598 <&apps_smmu 0x1186 0x0420>; 3599 }; 3600 3601 compute-cb@7 { 3602 compatible = "qcom,fastrpc-compute-cb"; 3603 reg = <7>; 3604 iommus = <&apps_smmu 0x2167 0x0400>, 3605 <&apps_smmu 0x1187 0x0420>; 3606 }; 3607 3608 compute-cb@8 { 3609 compatible = "qcom,fastrpc-compute-cb"; 3610 reg = <8>; 3611 iommus = <&apps_smmu 0x2168 0x0400>, 3612 <&apps_smmu 0x1188 0x0420>; 3613 }; 3614 3615 /* note: secure cb9 in downstream */ 3616 }; 3617 }; 3618 }; 3619 }; 3620 3621 thermal_zones: thermal-zones { 3622 cpu0-thermal { 3623 polling-delay-passive = <250>; 3624 polling-delay = <1000>; 3625 3626 thermal-sensors = <&tsens0 1>; 3627 3628 trips { 3629 cpu0_alert0: trip-point0 { 3630 temperature = <90000>; 3631 hysteresis = <2000>; 3632 type = "passive"; 3633 }; 3634 3635 cpu0_alert1: trip-point1 { 3636 temperature = <95000>; 3637 hysteresis = <2000>; 3638 type = "passive"; 3639 }; 3640 3641 cpu0_crit: cpu-crit { 3642 temperature = <110000>; 3643 hysteresis = <1000>; 3644 type = "critical"; 3645 }; 3646 }; 3647 3648 cooling-maps { 3649 map0 { 3650 trip = <&cpu0_alert0>; 3651 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3652 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3653 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3654 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3655 }; 3656 map1 { 3657 trip = <&cpu0_alert1>; 3658 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3659 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3660 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3661 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3662 }; 3663 }; 3664 }; 3665 3666 cpu1-thermal { 3667 polling-delay-passive = <250>; 3668 polling-delay = <1000>; 3669 3670 thermal-sensors = <&tsens0 2>; 3671 3672 trips { 3673 cpu1_alert0: trip-point0 { 3674 temperature = <90000>; 3675 hysteresis = <2000>; 3676 type = "passive"; 3677 }; 3678 3679 cpu1_alert1: trip-point1 { 3680 temperature = <95000>; 3681 hysteresis = <2000>; 3682 type = "passive"; 3683 }; 3684 3685 cpu1_crit: cpu-crit { 3686 temperature = <110000>; 3687 hysteresis = <1000>; 3688 type = "critical"; 3689 }; 3690 }; 3691 3692 cooling-maps { 3693 map0 { 3694 trip = <&cpu1_alert0>; 3695 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3696 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3697 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3698 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3699 }; 3700 map1 { 3701 trip = <&cpu1_alert1>; 3702 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3703 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3704 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3705 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3706 }; 3707 }; 3708 }; 3709 3710 cpu2-thermal { 3711 polling-delay-passive = <250>; 3712 polling-delay = <1000>; 3713 3714 thermal-sensors = <&tsens0 3>; 3715 3716 trips { 3717 cpu2_alert0: trip-point0 { 3718 temperature = <90000>; 3719 hysteresis = <2000>; 3720 type = "passive"; 3721 }; 3722 3723 cpu2_alert1: trip-point1 { 3724 temperature = <95000>; 3725 hysteresis = <2000>; 3726 type = "passive"; 3727 }; 3728 3729 cpu2_crit: cpu-crit { 3730 temperature = <110000>; 3731 hysteresis = <1000>; 3732 type = "critical"; 3733 }; 3734 }; 3735 3736 cooling-maps { 3737 map0 { 3738 trip = <&cpu2_alert0>; 3739 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3740 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3741 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3742 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3743 }; 3744 map1 { 3745 trip = <&cpu2_alert1>; 3746 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3747 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3748 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3749 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3750 }; 3751 }; 3752 }; 3753 3754 cpu3-thermal { 3755 polling-delay-passive = <250>; 3756 polling-delay = <1000>; 3757 3758 thermal-sensors = <&tsens0 4>; 3759 3760 trips { 3761 cpu3_alert0: trip-point0 { 3762 temperature = <90000>; 3763 hysteresis = <2000>; 3764 type = "passive"; 3765 }; 3766 3767 cpu3_alert1: trip-point1 { 3768 temperature = <95000>; 3769 hysteresis = <2000>; 3770 type = "passive"; 3771 }; 3772 3773 cpu3_crit: cpu-crit { 3774 temperature = <110000>; 3775 hysteresis = <1000>; 3776 type = "critical"; 3777 }; 3778 }; 3779 3780 cooling-maps { 3781 map0 { 3782 trip = <&cpu3_alert0>; 3783 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3784 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3785 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3786 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3787 }; 3788 map1 { 3789 trip = <&cpu3_alert1>; 3790 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3791 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3792 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3793 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3794 }; 3795 }; 3796 }; 3797 3798 cpu4-top-thermal { 3799 polling-delay-passive = <250>; 3800 polling-delay = <1000>; 3801 3802 thermal-sensors = <&tsens0 7>; 3803 3804 trips { 3805 cpu4_top_alert0: trip-point0 { 3806 temperature = <90000>; 3807 hysteresis = <2000>; 3808 type = "passive"; 3809 }; 3810 3811 cpu4_top_alert1: trip-point1 { 3812 temperature = <95000>; 3813 hysteresis = <2000>; 3814 type = "passive"; 3815 }; 3816 3817 cpu4_top_crit: cpu-crit { 3818 temperature = <110000>; 3819 hysteresis = <1000>; 3820 type = "critical"; 3821 }; 3822 }; 3823 3824 cooling-maps { 3825 map0 { 3826 trip = <&cpu4_top_alert0>; 3827 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3828 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3829 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3830 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3831 }; 3832 map1 { 3833 trip = <&cpu4_top_alert1>; 3834 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3835 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3836 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3837 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3838 }; 3839 }; 3840 }; 3841 3842 cpu5-top-thermal { 3843 polling-delay-passive = <250>; 3844 polling-delay = <1000>; 3845 3846 thermal-sensors = <&tsens0 8>; 3847 3848 trips { 3849 cpu5_top_alert0: trip-point0 { 3850 temperature = <90000>; 3851 hysteresis = <2000>; 3852 type = "passive"; 3853 }; 3854 3855 cpu5_top_alert1: trip-point1 { 3856 temperature = <95000>; 3857 hysteresis = <2000>; 3858 type = "passive"; 3859 }; 3860 3861 cpu5_top_crit: cpu-crit { 3862 temperature = <110000>; 3863 hysteresis = <1000>; 3864 type = "critical"; 3865 }; 3866 }; 3867 3868 cooling-maps { 3869 map0 { 3870 trip = <&cpu5_top_alert0>; 3871 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3872 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3873 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3874 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3875 }; 3876 map1 { 3877 trip = <&cpu5_top_alert1>; 3878 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3879 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3880 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3881 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3882 }; 3883 }; 3884 }; 3885 3886 cpu6-top-thermal { 3887 polling-delay-passive = <250>; 3888 polling-delay = <1000>; 3889 3890 thermal-sensors = <&tsens0 9>; 3891 3892 trips { 3893 cpu6_top_alert0: trip-point0 { 3894 temperature = <90000>; 3895 hysteresis = <2000>; 3896 type = "passive"; 3897 }; 3898 3899 cpu6_top_alert1: trip-point1 { 3900 temperature = <95000>; 3901 hysteresis = <2000>; 3902 type = "passive"; 3903 }; 3904 3905 cpu6_top_crit: cpu-crit { 3906 temperature = <110000>; 3907 hysteresis = <1000>; 3908 type = "critical"; 3909 }; 3910 }; 3911 3912 cooling-maps { 3913 map0 { 3914 trip = <&cpu6_top_alert0>; 3915 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3916 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3917 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3918 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3919 }; 3920 map1 { 3921 trip = <&cpu6_top_alert1>; 3922 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3923 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3924 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3925 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3926 }; 3927 }; 3928 }; 3929 3930 cpu7-top-thermal { 3931 polling-delay-passive = <250>; 3932 polling-delay = <1000>; 3933 3934 thermal-sensors = <&tsens0 10>; 3935 3936 trips { 3937 cpu7_top_alert0: trip-point0 { 3938 temperature = <90000>; 3939 hysteresis = <2000>; 3940 type = "passive"; 3941 }; 3942 3943 cpu7_top_alert1: trip-point1 { 3944 temperature = <95000>; 3945 hysteresis = <2000>; 3946 type = "passive"; 3947 }; 3948 3949 cpu7_top_crit: cpu-crit { 3950 temperature = <110000>; 3951 hysteresis = <1000>; 3952 type = "critical"; 3953 }; 3954 }; 3955 3956 cooling-maps { 3957 map0 { 3958 trip = <&cpu7_top_alert0>; 3959 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3960 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3961 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3962 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3963 }; 3964 map1 { 3965 trip = <&cpu7_top_alert1>; 3966 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3967 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3968 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3969 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3970 }; 3971 }; 3972 }; 3973 3974 cpu4-bottom-thermal { 3975 polling-delay-passive = <250>; 3976 polling-delay = <1000>; 3977 3978 thermal-sensors = <&tsens0 11>; 3979 3980 trips { 3981 cpu4_bottom_alert0: trip-point0 { 3982 temperature = <90000>; 3983 hysteresis = <2000>; 3984 type = "passive"; 3985 }; 3986 3987 cpu4_bottom_alert1: trip-point1 { 3988 temperature = <95000>; 3989 hysteresis = <2000>; 3990 type = "passive"; 3991 }; 3992 3993 cpu4_bottom_crit: cpu-crit { 3994 temperature = <110000>; 3995 hysteresis = <1000>; 3996 type = "critical"; 3997 }; 3998 }; 3999 4000 cooling-maps { 4001 map0 { 4002 trip = <&cpu4_bottom_alert0>; 4003 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4004 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4005 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4006 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4007 }; 4008 map1 { 4009 trip = <&cpu4_bottom_alert1>; 4010 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4011 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4012 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4013 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4014 }; 4015 }; 4016 }; 4017 4018 cpu5-bottom-thermal { 4019 polling-delay-passive = <250>; 4020 polling-delay = <1000>; 4021 4022 thermal-sensors = <&tsens0 12>; 4023 4024 trips { 4025 cpu5_bottom_alert0: trip-point0 { 4026 temperature = <90000>; 4027 hysteresis = <2000>; 4028 type = "passive"; 4029 }; 4030 4031 cpu5_bottom_alert1: trip-point1 { 4032 temperature = <95000>; 4033 hysteresis = <2000>; 4034 type = "passive"; 4035 }; 4036 4037 cpu5_bottom_crit: cpu-crit { 4038 temperature = <110000>; 4039 hysteresis = <1000>; 4040 type = "critical"; 4041 }; 4042 }; 4043 4044 cooling-maps { 4045 map0 { 4046 trip = <&cpu5_bottom_alert0>; 4047 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4048 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4049 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4050 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4051 }; 4052 map1 { 4053 trip = <&cpu5_bottom_alert1>; 4054 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4055 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4056 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4057 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4058 }; 4059 }; 4060 }; 4061 4062 cpu6-bottom-thermal { 4063 polling-delay-passive = <250>; 4064 polling-delay = <1000>; 4065 4066 thermal-sensors = <&tsens0 13>; 4067 4068 trips { 4069 cpu6_bottom_alert0: trip-point0 { 4070 temperature = <90000>; 4071 hysteresis = <2000>; 4072 type = "passive"; 4073 }; 4074 4075 cpu6_bottom_alert1: trip-point1 { 4076 temperature = <95000>; 4077 hysteresis = <2000>; 4078 type = "passive"; 4079 }; 4080 4081 cpu6_bottom_crit: cpu-crit { 4082 temperature = <110000>; 4083 hysteresis = <1000>; 4084 type = "critical"; 4085 }; 4086 }; 4087 4088 cooling-maps { 4089 map0 { 4090 trip = <&cpu6_bottom_alert0>; 4091 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4092 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4093 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4094 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4095 }; 4096 map1 { 4097 trip = <&cpu6_bottom_alert1>; 4098 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4099 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4100 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4101 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4102 }; 4103 }; 4104 }; 4105 4106 cpu7-bottom-thermal { 4107 polling-delay-passive = <250>; 4108 polling-delay = <1000>; 4109 4110 thermal-sensors = <&tsens0 14>; 4111 4112 trips { 4113 cpu7_bottom_alert0: trip-point0 { 4114 temperature = <90000>; 4115 hysteresis = <2000>; 4116 type = "passive"; 4117 }; 4118 4119 cpu7_bottom_alert1: trip-point1 { 4120 temperature = <95000>; 4121 hysteresis = <2000>; 4122 type = "passive"; 4123 }; 4124 4125 cpu7_bottom_crit: cpu-crit { 4126 temperature = <110000>; 4127 hysteresis = <1000>; 4128 type = "critical"; 4129 }; 4130 }; 4131 4132 cooling-maps { 4133 map0 { 4134 trip = <&cpu7_bottom_alert0>; 4135 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4136 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4137 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4138 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4139 }; 4140 map1 { 4141 trip = <&cpu7_bottom_alert1>; 4142 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4143 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4144 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4145 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4146 }; 4147 }; 4148 }; 4149 4150 aoss0-thermal { 4151 polling-delay-passive = <250>; 4152 polling-delay = <1000>; 4153 4154 thermal-sensors = <&tsens0 0>; 4155 4156 trips { 4157 aoss0_alert0: trip-point0 { 4158 temperature = <90000>; 4159 hysteresis = <2000>; 4160 type = "hot"; 4161 }; 4162 }; 4163 }; 4164 4165 cluster0-thermal { 4166 polling-delay-passive = <250>; 4167 polling-delay = <1000>; 4168 4169 thermal-sensors = <&tsens0 5>; 4170 4171 trips { 4172 cluster0_alert0: trip-point0 { 4173 temperature = <90000>; 4174 hysteresis = <2000>; 4175 type = "hot"; 4176 }; 4177 cluster0_crit: cluster0_crit { 4178 temperature = <110000>; 4179 hysteresis = <2000>; 4180 type = "critical"; 4181 }; 4182 }; 4183 }; 4184 4185 cluster1-thermal { 4186 polling-delay-passive = <250>; 4187 polling-delay = <1000>; 4188 4189 thermal-sensors = <&tsens0 6>; 4190 4191 trips { 4192 cluster1_alert0: trip-point0 { 4193 temperature = <90000>; 4194 hysteresis = <2000>; 4195 type = "hot"; 4196 }; 4197 cluster1_crit: cluster1_crit { 4198 temperature = <110000>; 4199 hysteresis = <2000>; 4200 type = "critical"; 4201 }; 4202 }; 4203 }; 4204 4205 aoss1-thermal { 4206 polling-delay-passive = <250>; 4207 polling-delay = <1000>; 4208 4209 thermal-sensors = <&tsens1 0>; 4210 4211 trips { 4212 aoss1_alert0: trip-point0 { 4213 temperature = <90000>; 4214 hysteresis = <2000>; 4215 type = "hot"; 4216 }; 4217 }; 4218 }; 4219 4220 gpu-top-thermal { 4221 polling-delay-passive = <250>; 4222 polling-delay = <1000>; 4223 4224 thermal-sensors = <&tsens1 1>; 4225 4226 trips { 4227 gpu1_alert0: trip-point0 { 4228 temperature = <90000>; 4229 hysteresis = <1000>; 4230 type = "hot"; 4231 }; 4232 }; 4233 }; 4234 4235 gpu-bottom-thermal { 4236 polling-delay-passive = <250>; 4237 polling-delay = <1000>; 4238 4239 thermal-sensors = <&tsens1 2>; 4240 4241 trips { 4242 gpu2_alert0: trip-point0 { 4243 temperature = <90000>; 4244 hysteresis = <1000>; 4245 type = "hot"; 4246 }; 4247 }; 4248 }; 4249 4250 nspss1-thermal { 4251 polling-delay-passive = <250>; 4252 polling-delay = <1000>; 4253 4254 thermal-sensors = <&tsens1 3>; 4255 4256 trips { 4257 nspss1_alert0: trip-point0 { 4258 temperature = <90000>; 4259 hysteresis = <1000>; 4260 type = "hot"; 4261 }; 4262 }; 4263 }; 4264 4265 nspss2-thermal { 4266 polling-delay-passive = <250>; 4267 polling-delay = <1000>; 4268 4269 thermal-sensors = <&tsens1 4>; 4270 4271 trips { 4272 nspss2_alert0: trip-point0 { 4273 temperature = <90000>; 4274 hysteresis = <1000>; 4275 type = "hot"; 4276 }; 4277 }; 4278 }; 4279 4280 nspss3-thermal { 4281 polling-delay-passive = <250>; 4282 polling-delay = <1000>; 4283 4284 thermal-sensors = <&tsens1 5>; 4285 4286 trips { 4287 nspss3_alert0: trip-point0 { 4288 temperature = <90000>; 4289 hysteresis = <1000>; 4290 type = "hot"; 4291 }; 4292 }; 4293 }; 4294 4295 video-thermal { 4296 polling-delay-passive = <250>; 4297 polling-delay = <1000>; 4298 4299 thermal-sensors = <&tsens1 6>; 4300 4301 trips { 4302 video_alert0: trip-point0 { 4303 temperature = <90000>; 4304 hysteresis = <2000>; 4305 type = "hot"; 4306 }; 4307 }; 4308 }; 4309 4310 mem-thermal { 4311 polling-delay-passive = <250>; 4312 polling-delay = <1000>; 4313 4314 thermal-sensors = <&tsens1 7>; 4315 4316 trips { 4317 mem_alert0: trip-point0 { 4318 temperature = <90000>; 4319 hysteresis = <2000>; 4320 type = "hot"; 4321 }; 4322 }; 4323 }; 4324 4325 modem1-top-thermal { 4326 polling-delay-passive = <250>; 4327 polling-delay = <1000>; 4328 4329 thermal-sensors = <&tsens1 8>; 4330 4331 trips { 4332 modem1_alert0: trip-point0 { 4333 temperature = <90000>; 4334 hysteresis = <2000>; 4335 type = "hot"; 4336 }; 4337 }; 4338 }; 4339 4340 modem2-top-thermal { 4341 polling-delay-passive = <250>; 4342 polling-delay = <1000>; 4343 4344 thermal-sensors = <&tsens1 9>; 4345 4346 trips { 4347 modem2_alert0: trip-point0 { 4348 temperature = <90000>; 4349 hysteresis = <2000>; 4350 type = "hot"; 4351 }; 4352 }; 4353 }; 4354 4355 modem3-top-thermal { 4356 polling-delay-passive = <250>; 4357 polling-delay = <1000>; 4358 4359 thermal-sensors = <&tsens1 10>; 4360 4361 trips { 4362 modem3_alert0: trip-point0 { 4363 temperature = <90000>; 4364 hysteresis = <2000>; 4365 type = "hot"; 4366 }; 4367 }; 4368 }; 4369 4370 modem4-top-thermal { 4371 polling-delay-passive = <250>; 4372 polling-delay = <1000>; 4373 4374 thermal-sensors = <&tsens1 11>; 4375 4376 trips { 4377 modem4_alert0: trip-point0 { 4378 temperature = <90000>; 4379 hysteresis = <2000>; 4380 type = "hot"; 4381 }; 4382 }; 4383 }; 4384 4385 camera-top-thermal { 4386 polling-delay-passive = <250>; 4387 polling-delay = <1000>; 4388 4389 thermal-sensors = <&tsens1 12>; 4390 4391 trips { 4392 camera1_alert0: trip-point0 { 4393 temperature = <90000>; 4394 hysteresis = <2000>; 4395 type = "hot"; 4396 }; 4397 }; 4398 }; 4399 4400 cam-bottom-thermal { 4401 polling-delay-passive = <250>; 4402 polling-delay = <1000>; 4403 4404 thermal-sensors = <&tsens1 13>; 4405 4406 trips { 4407 camera2_alert0: trip-point0 { 4408 temperature = <90000>; 4409 hysteresis = <2000>; 4410 type = "hot"; 4411 }; 4412 }; 4413 }; 4414 }; 4415 4416 timer { 4417 compatible = "arm,armv8-timer"; 4418 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4419 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4420 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4421 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4422 }; 4423}; 4424