1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Linaro Limited 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,dispcc-sm8350.h> 8#include <dt-bindings/clock/qcom,gcc-sm8350.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/dma/qcom-gpi.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interconnect/qcom,sm8350.h> 13#include <dt-bindings/mailbox/qcom-ipcc.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15#include <dt-bindings/soc/qcom,rpmh-rsc.h> 16#include <dt-bindings/thermal/thermal.h> 17#include <dt-bindings/interconnect/qcom,sm8350.h> 18 19/ { 20 interrupt-parent = <&intc>; 21 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 chosen { }; 26 27 clocks { 28 xo_board: xo-board { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <38400000>; 32 clock-output-names = "xo_board"; 33 }; 34 35 sleep_clk: sleep-clk { 36 compatible = "fixed-clock"; 37 clock-frequency = <32000>; 38 #clock-cells = <0>; 39 }; 40 41 ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0 { 42 compatible = "fixed-clock"; 43 clock-frequency = <1000>; 44 #clock-cells = <0>; 45 }; 46 47 ufs_phy_rx_symbol_1_clk: ufs-phy-rx-symbol-1 { 48 compatible = "fixed-clock"; 49 clock-frequency = <1000>; 50 #clock-cells = <0>; 51 }; 52 53 ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0 { 54 compatible = "fixed-clock"; 55 clock-frequency = <1000>; 56 #clock-cells = <0>; 57 }; 58 }; 59 60 cpus { 61 #address-cells = <2>; 62 #size-cells = <0>; 63 64 CPU0: cpu@0 { 65 device_type = "cpu"; 66 compatible = "qcom,kryo685"; 67 reg = <0x0 0x0>; 68 enable-method = "psci"; 69 next-level-cache = <&L2_0>; 70 qcom,freq-domain = <&cpufreq_hw 0>; 71 power-domains = <&CPU_PD0>; 72 power-domain-names = "psci"; 73 #cooling-cells = <2>; 74 L2_0: l2-cache { 75 compatible = "cache"; 76 next-level-cache = <&L3_0>; 77 L3_0: l3-cache { 78 compatible = "cache"; 79 }; 80 }; 81 }; 82 83 CPU1: cpu@100 { 84 device_type = "cpu"; 85 compatible = "qcom,kryo685"; 86 reg = <0x0 0x100>; 87 enable-method = "psci"; 88 next-level-cache = <&L2_100>; 89 qcom,freq-domain = <&cpufreq_hw 0>; 90 power-domains = <&CPU_PD1>; 91 power-domain-names = "psci"; 92 #cooling-cells = <2>; 93 L2_100: l2-cache { 94 compatible = "cache"; 95 next-level-cache = <&L3_0>; 96 }; 97 }; 98 99 CPU2: cpu@200 { 100 device_type = "cpu"; 101 compatible = "qcom,kryo685"; 102 reg = <0x0 0x200>; 103 enable-method = "psci"; 104 next-level-cache = <&L2_200>; 105 qcom,freq-domain = <&cpufreq_hw 0>; 106 power-domains = <&CPU_PD2>; 107 power-domain-names = "psci"; 108 #cooling-cells = <2>; 109 L2_200: l2-cache { 110 compatible = "cache"; 111 next-level-cache = <&L3_0>; 112 }; 113 }; 114 115 CPU3: cpu@300 { 116 device_type = "cpu"; 117 compatible = "qcom,kryo685"; 118 reg = <0x0 0x300>; 119 enable-method = "psci"; 120 next-level-cache = <&L2_300>; 121 qcom,freq-domain = <&cpufreq_hw 0>; 122 power-domains = <&CPU_PD3>; 123 power-domain-names = "psci"; 124 #cooling-cells = <2>; 125 L2_300: l2-cache { 126 compatible = "cache"; 127 next-level-cache = <&L3_0>; 128 }; 129 }; 130 131 CPU4: cpu@400 { 132 device_type = "cpu"; 133 compatible = "qcom,kryo685"; 134 reg = <0x0 0x400>; 135 enable-method = "psci"; 136 next-level-cache = <&L2_400>; 137 qcom,freq-domain = <&cpufreq_hw 1>; 138 power-domains = <&CPU_PD4>; 139 power-domain-names = "psci"; 140 #cooling-cells = <2>; 141 L2_400: l2-cache { 142 compatible = "cache"; 143 next-level-cache = <&L3_0>; 144 }; 145 }; 146 147 CPU5: cpu@500 { 148 device_type = "cpu"; 149 compatible = "qcom,kryo685"; 150 reg = <0x0 0x500>; 151 enable-method = "psci"; 152 next-level-cache = <&L2_500>; 153 qcom,freq-domain = <&cpufreq_hw 1>; 154 power-domains = <&CPU_PD5>; 155 power-domain-names = "psci"; 156 #cooling-cells = <2>; 157 L2_500: l2-cache { 158 compatible = "cache"; 159 next-level-cache = <&L3_0>; 160 }; 161 162 }; 163 164 CPU6: cpu@600 { 165 device_type = "cpu"; 166 compatible = "qcom,kryo685"; 167 reg = <0x0 0x600>; 168 enable-method = "psci"; 169 next-level-cache = <&L2_600>; 170 qcom,freq-domain = <&cpufreq_hw 1>; 171 power-domains = <&CPU_PD6>; 172 power-domain-names = "psci"; 173 #cooling-cells = <2>; 174 L2_600: l2-cache { 175 compatible = "cache"; 176 next-level-cache = <&L3_0>; 177 }; 178 }; 179 180 CPU7: cpu@700 { 181 device_type = "cpu"; 182 compatible = "qcom,kryo685"; 183 reg = <0x0 0x700>; 184 enable-method = "psci"; 185 next-level-cache = <&L2_700>; 186 qcom,freq-domain = <&cpufreq_hw 2>; 187 power-domains = <&CPU_PD7>; 188 power-domain-names = "psci"; 189 #cooling-cells = <2>; 190 L2_700: l2-cache { 191 compatible = "cache"; 192 next-level-cache = <&L3_0>; 193 }; 194 }; 195 196 cpu-map { 197 cluster0 { 198 core0 { 199 cpu = <&CPU0>; 200 }; 201 202 core1 { 203 cpu = <&CPU1>; 204 }; 205 206 core2 { 207 cpu = <&CPU2>; 208 }; 209 210 core3 { 211 cpu = <&CPU3>; 212 }; 213 214 core4 { 215 cpu = <&CPU4>; 216 }; 217 218 core5 { 219 cpu = <&CPU5>; 220 }; 221 222 core6 { 223 cpu = <&CPU6>; 224 }; 225 226 core7 { 227 cpu = <&CPU7>; 228 }; 229 }; 230 }; 231 232 idle-states { 233 entry-method = "psci"; 234 235 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 236 compatible = "arm,idle-state"; 237 idle-state-name = "silver-rail-power-collapse"; 238 arm,psci-suspend-param = <0x40000004>; 239 entry-latency-us = <355>; 240 exit-latency-us = <909>; 241 min-residency-us = <3934>; 242 local-timer-stop; 243 }; 244 245 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 246 compatible = "arm,idle-state"; 247 idle-state-name = "gold-rail-power-collapse"; 248 arm,psci-suspend-param = <0x40000004>; 249 entry-latency-us = <241>; 250 exit-latency-us = <1461>; 251 min-residency-us = <4488>; 252 local-timer-stop; 253 }; 254 }; 255 256 domain-idle-states { 257 CLUSTER_SLEEP_0: cluster-sleep-0 { 258 compatible = "domain-idle-state"; 259 idle-state-name = "cluster-power-collapse"; 260 arm,psci-suspend-param = <0x4100c344>; 261 entry-latency-us = <3263>; 262 exit-latency-us = <6562>; 263 min-residency-us = <9987>; 264 local-timer-stop; 265 }; 266 }; 267 }; 268 269 firmware { 270 scm: scm { 271 compatible = "qcom,scm-sm8350", "qcom,scm"; 272 #reset-cells = <1>; 273 }; 274 }; 275 276 memory@80000000 { 277 device_type = "memory"; 278 /* We expect the bootloader to fill in the size */ 279 reg = <0x0 0x80000000 0x0 0x0>; 280 }; 281 282 pmu { 283 compatible = "arm,armv8-pmuv3"; 284 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 285 }; 286 287 psci { 288 compatible = "arm,psci-1.0"; 289 method = "smc"; 290 291 CPU_PD0: cpu0 { 292 #power-domain-cells = <0>; 293 power-domains = <&CLUSTER_PD>; 294 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 295 }; 296 297 CPU_PD1: cpu1 { 298 #power-domain-cells = <0>; 299 power-domains = <&CLUSTER_PD>; 300 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 301 }; 302 303 CPU_PD2: cpu2 { 304 #power-domain-cells = <0>; 305 power-domains = <&CLUSTER_PD>; 306 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 307 }; 308 309 CPU_PD3: cpu3 { 310 #power-domain-cells = <0>; 311 power-domains = <&CLUSTER_PD>; 312 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 313 }; 314 315 CPU_PD4: cpu4 { 316 #power-domain-cells = <0>; 317 power-domains = <&CLUSTER_PD>; 318 domain-idle-states = <&BIG_CPU_SLEEP_0>; 319 }; 320 321 CPU_PD5: cpu5 { 322 #power-domain-cells = <0>; 323 power-domains = <&CLUSTER_PD>; 324 domain-idle-states = <&BIG_CPU_SLEEP_0>; 325 }; 326 327 CPU_PD6: cpu6 { 328 #power-domain-cells = <0>; 329 power-domains = <&CLUSTER_PD>; 330 domain-idle-states = <&BIG_CPU_SLEEP_0>; 331 }; 332 333 CPU_PD7: cpu7 { 334 #power-domain-cells = <0>; 335 power-domains = <&CLUSTER_PD>; 336 domain-idle-states = <&BIG_CPU_SLEEP_0>; 337 }; 338 339 CLUSTER_PD: cpu-cluster0 { 340 #power-domain-cells = <0>; 341 domain-idle-states = <&CLUSTER_SLEEP_0>; 342 }; 343 }; 344 345 qup_opp_table_100mhz: opp-table-qup100mhz { 346 compatible = "operating-points-v2"; 347 348 opp-50000000 { 349 opp-hz = /bits/ 64 <50000000>; 350 required-opps = <&rpmhpd_opp_min_svs>; 351 }; 352 353 opp-75000000 { 354 opp-hz = /bits/ 64 <75000000>; 355 required-opps = <&rpmhpd_opp_low_svs>; 356 }; 357 358 opp-100000000 { 359 opp-hz = /bits/ 64 <100000000>; 360 required-opps = <&rpmhpd_opp_svs>; 361 }; 362 }; 363 364 qup_opp_table_120mhz: opp-table-qup120mhz { 365 compatible = "operating-points-v2"; 366 367 opp-50000000 { 368 opp-hz = /bits/ 64 <50000000>; 369 required-opps = <&rpmhpd_opp_min_svs>; 370 }; 371 372 opp-75000000 { 373 opp-hz = /bits/ 64 <75000000>; 374 required-opps = <&rpmhpd_opp_low_svs>; 375 }; 376 377 opp-120000000 { 378 opp-hz = /bits/ 64 <120000000>; 379 required-opps = <&rpmhpd_opp_svs>; 380 }; 381 }; 382 383 reserved_memory: reserved-memory { 384 #address-cells = <2>; 385 #size-cells = <2>; 386 ranges; 387 388 hyp_mem: memory@80000000 { 389 reg = <0x0 0x80000000 0x0 0x600000>; 390 no-map; 391 }; 392 393 xbl_aop_mem: memory@80700000 { 394 no-map; 395 reg = <0x0 0x80700000 0x0 0x160000>; 396 }; 397 398 cmd_db: memory@80860000 { 399 compatible = "qcom,cmd-db"; 400 reg = <0x0 0x80860000 0x0 0x20000>; 401 no-map; 402 }; 403 404 reserved_xbl_uefi_log: memory@80880000 { 405 reg = <0x0 0x80880000 0x0 0x14000>; 406 no-map; 407 }; 408 409 smem_mem: memory@80900000 { 410 reg = <0x0 0x80900000 0x0 0x200000>; 411 no-map; 412 }; 413 414 cpucp_fw_mem: memory@80b00000 { 415 reg = <0x0 0x80b00000 0x0 0x100000>; 416 no-map; 417 }; 418 419 cdsp_secure_heap: memory@80c00000 { 420 reg = <0x0 0x80c00000 0x0 0x4600000>; 421 no-map; 422 }; 423 424 pil_camera_mem: mmeory@85200000 { 425 reg = <0x0 0x85200000 0x0 0x500000>; 426 no-map; 427 }; 428 429 pil_video_mem: memory@85700000 { 430 reg = <0x0 0x85700000 0x0 0x500000>; 431 no-map; 432 }; 433 434 pil_cvp_mem: memory@85c00000 { 435 reg = <0x0 0x85c00000 0x0 0x500000>; 436 no-map; 437 }; 438 439 pil_adsp_mem: memory@86100000 { 440 reg = <0x0 0x86100000 0x0 0x2100000>; 441 no-map; 442 }; 443 444 pil_slpi_mem: memory@88200000 { 445 reg = <0x0 0x88200000 0x0 0x1500000>; 446 no-map; 447 }; 448 449 pil_cdsp_mem: memory@89700000 { 450 reg = <0x0 0x89700000 0x0 0x1e00000>; 451 no-map; 452 }; 453 454 pil_ipa_fw_mem: memory@8b500000 { 455 reg = <0x0 0x8b500000 0x0 0x10000>; 456 no-map; 457 }; 458 459 pil_ipa_gsi_mem: memory@8b510000 { 460 reg = <0x0 0x8b510000 0x0 0xa000>; 461 no-map; 462 }; 463 464 pil_gpu_mem: memory@8b51a000 { 465 reg = <0x0 0x8b51a000 0x0 0x2000>; 466 no-map; 467 }; 468 469 pil_spss_mem: memory@8b600000 { 470 reg = <0x0 0x8b600000 0x0 0x100000>; 471 no-map; 472 }; 473 474 pil_modem_mem: memory@8b800000 { 475 reg = <0x0 0x8b800000 0x0 0x10000000>; 476 no-map; 477 }; 478 479 rmtfs_mem: memory@9b800000 { 480 compatible = "qcom,rmtfs-mem"; 481 reg = <0x0 0x9b800000 0x0 0x280000>; 482 no-map; 483 484 qcom,client-id = <1>; 485 qcom,vmid = <15>; 486 }; 487 488 hyp_reserved_mem: memory@d0000000 { 489 reg = <0x0 0xd0000000 0x0 0x800000>; 490 no-map; 491 }; 492 493 pil_trustedvm_mem: memory@d0800000 { 494 reg = <0x0 0xd0800000 0x0 0x76f7000>; 495 no-map; 496 }; 497 498 qrtr_shbuf: memory@d7ef7000 { 499 reg = <0x0 0xd7ef7000 0x0 0x9000>; 500 no-map; 501 }; 502 503 chan0_shbuf: memory@d7f00000 { 504 reg = <0x0 0xd7f00000 0x0 0x80000>; 505 no-map; 506 }; 507 508 chan1_shbuf: memory@d7f80000 { 509 reg = <0x0 0xd7f80000 0x0 0x80000>; 510 no-map; 511 }; 512 513 removed_mem: memory@d8800000 { 514 reg = <0x0 0xd8800000 0x0 0x6800000>; 515 no-map; 516 }; 517 }; 518 519 smem: qcom,smem { 520 compatible = "qcom,smem"; 521 memory-region = <&smem_mem>; 522 hwlocks = <&tcsr_mutex 3>; 523 }; 524 525 smp2p-adsp { 526 compatible = "qcom,smp2p"; 527 qcom,smem = <443>, <429>; 528 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 529 IPCC_MPROC_SIGNAL_SMP2P 530 IRQ_TYPE_EDGE_RISING>; 531 mboxes = <&ipcc IPCC_CLIENT_LPASS 532 IPCC_MPROC_SIGNAL_SMP2P>; 533 534 qcom,local-pid = <0>; 535 qcom,remote-pid = <2>; 536 537 smp2p_adsp_out: master-kernel { 538 qcom,entry-name = "master-kernel"; 539 #qcom,smem-state-cells = <1>; 540 }; 541 542 smp2p_adsp_in: slave-kernel { 543 qcom,entry-name = "slave-kernel"; 544 interrupt-controller; 545 #interrupt-cells = <2>; 546 }; 547 }; 548 549 smp2p-cdsp { 550 compatible = "qcom,smp2p"; 551 qcom,smem = <94>, <432>; 552 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 553 IPCC_MPROC_SIGNAL_SMP2P 554 IRQ_TYPE_EDGE_RISING>; 555 mboxes = <&ipcc IPCC_CLIENT_CDSP 556 IPCC_MPROC_SIGNAL_SMP2P>; 557 558 qcom,local-pid = <0>; 559 qcom,remote-pid = <5>; 560 561 smp2p_cdsp_out: master-kernel { 562 qcom,entry-name = "master-kernel"; 563 #qcom,smem-state-cells = <1>; 564 }; 565 566 smp2p_cdsp_in: slave-kernel { 567 qcom,entry-name = "slave-kernel"; 568 interrupt-controller; 569 #interrupt-cells = <2>; 570 }; 571 }; 572 573 smp2p-modem { 574 compatible = "qcom,smp2p"; 575 qcom,smem = <435>, <428>; 576 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 577 IPCC_MPROC_SIGNAL_SMP2P 578 IRQ_TYPE_EDGE_RISING>; 579 mboxes = <&ipcc IPCC_CLIENT_MPSS 580 IPCC_MPROC_SIGNAL_SMP2P>; 581 582 qcom,local-pid = <0>; 583 qcom,remote-pid = <1>; 584 585 smp2p_modem_out: master-kernel { 586 qcom,entry-name = "master-kernel"; 587 #qcom,smem-state-cells = <1>; 588 }; 589 590 smp2p_modem_in: slave-kernel { 591 qcom,entry-name = "slave-kernel"; 592 interrupt-controller; 593 #interrupt-cells = <2>; 594 }; 595 596 ipa_smp2p_out: ipa-ap-to-modem { 597 qcom,entry-name = "ipa"; 598 #qcom,smem-state-cells = <1>; 599 }; 600 601 ipa_smp2p_in: ipa-modem-to-ap { 602 qcom,entry-name = "ipa"; 603 interrupt-controller; 604 #interrupt-cells = <2>; 605 }; 606 }; 607 608 smp2p-slpi { 609 compatible = "qcom,smp2p"; 610 qcom,smem = <481>, <430>; 611 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 612 IPCC_MPROC_SIGNAL_SMP2P 613 IRQ_TYPE_EDGE_RISING>; 614 mboxes = <&ipcc IPCC_CLIENT_SLPI 615 IPCC_MPROC_SIGNAL_SMP2P>; 616 617 qcom,local-pid = <0>; 618 qcom,remote-pid = <3>; 619 620 smp2p_slpi_out: master-kernel { 621 qcom,entry-name = "master-kernel"; 622 #qcom,smem-state-cells = <1>; 623 }; 624 625 smp2p_slpi_in: slave-kernel { 626 qcom,entry-name = "slave-kernel"; 627 interrupt-controller; 628 #interrupt-cells = <2>; 629 }; 630 }; 631 632 soc: soc@0 { 633 #address-cells = <2>; 634 #size-cells = <2>; 635 ranges = <0 0 0 0 0x10 0>; 636 dma-ranges = <0 0 0 0 0x10 0>; 637 compatible = "simple-bus"; 638 639 gcc: clock-controller@100000 { 640 compatible = "qcom,gcc-sm8350"; 641 reg = <0x0 0x00100000 0x0 0x1f0000>; 642 #clock-cells = <1>; 643 #reset-cells = <1>; 644 #power-domain-cells = <1>; 645 clock-names = "bi_tcxo", 646 "sleep_clk", 647 "pcie_0_pipe_clk", 648 "pcie_1_pipe_clk", 649 "ufs_card_rx_symbol_0_clk", 650 "ufs_card_rx_symbol_1_clk", 651 "ufs_card_tx_symbol_0_clk", 652 "ufs_phy_rx_symbol_0_clk", 653 "ufs_phy_rx_symbol_1_clk", 654 "ufs_phy_tx_symbol_0_clk", 655 "usb3_phy_wrapper_gcc_usb30_pipe_clk", 656 "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; 657 clocks = <&rpmhcc RPMH_CXO_CLK>, 658 <&sleep_clk>, 659 <0>, 660 <0>, 661 <0>, 662 <0>, 663 <0>, 664 <&ufs_phy_rx_symbol_0_clk>, 665 <&ufs_phy_rx_symbol_1_clk>, 666 <&ufs_phy_tx_symbol_0_clk>, 667 <0>, 668 <0>; 669 }; 670 671 ipcc: mailbox@408000 { 672 compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; 673 reg = <0 0x00408000 0 0x1000>; 674 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 675 interrupt-controller; 676 #interrupt-cells = <3>; 677 #mbox-cells = <2>; 678 }; 679 680 gpi_dma2: dma-controller@800000 { 681 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 682 reg = <0 0x00800000 0 0x60000>; 683 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 694 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 695 dma-channels = <12>; 696 dma-channel-mask = <0xff>; 697 iommus = <&apps_smmu 0x5f6 0x0>; 698 #dma-cells = <3>; 699 status = "disabled"; 700 }; 701 702 qupv3_id_2: geniqup@8c0000 { 703 compatible = "qcom,geni-se-qup"; 704 reg = <0x0 0x008c0000 0x0 0x6000>; 705 clock-names = "m-ahb", "s-ahb"; 706 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 707 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 708 iommus = <&apps_smmu 0x5e3 0x0>; 709 #address-cells = <2>; 710 #size-cells = <2>; 711 ranges; 712 status = "disabled"; 713 714 i2c14: i2c@880000 { 715 compatible = "qcom,geni-i2c"; 716 reg = <0 0x00880000 0 0x4000>; 717 clock-names = "se"; 718 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 719 pinctrl-names = "default"; 720 pinctrl-0 = <&qup_i2c14_default>; 721 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 722 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 723 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 724 dma-names = "tx", "rx"; 725 #address-cells = <1>; 726 #size-cells = <0>; 727 status = "disabled"; 728 }; 729 730 spi14: spi@880000 { 731 compatible = "qcom,geni-spi"; 732 reg = <0 0x00880000 0 0x4000>; 733 clock-names = "se"; 734 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 735 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 736 power-domains = <&rpmhpd SM8350_CX>; 737 operating-points-v2 = <&qup_opp_table_120mhz>; 738 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 739 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 740 dma-names = "tx", "rx"; 741 #address-cells = <1>; 742 #size-cells = <0>; 743 status = "disabled"; 744 }; 745 746 i2c15: i2c@884000 { 747 compatible = "qcom,geni-i2c"; 748 reg = <0 0x00884000 0 0x4000>; 749 clock-names = "se"; 750 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 751 pinctrl-names = "default"; 752 pinctrl-0 = <&qup_i2c15_default>; 753 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 754 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 755 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 756 dma-names = "tx", "rx"; 757 #address-cells = <1>; 758 #size-cells = <0>; 759 status = "disabled"; 760 }; 761 762 spi15: spi@884000 { 763 compatible = "qcom,geni-spi"; 764 reg = <0 0x00884000 0 0x4000>; 765 clock-names = "se"; 766 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 767 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 768 power-domains = <&rpmhpd SM8350_CX>; 769 operating-points-v2 = <&qup_opp_table_120mhz>; 770 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 771 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 772 dma-names = "tx", "rx"; 773 #address-cells = <1>; 774 #size-cells = <0>; 775 status = "disabled"; 776 }; 777 778 i2c16: i2c@888000 { 779 compatible = "qcom,geni-i2c"; 780 reg = <0 0x00888000 0 0x4000>; 781 clock-names = "se"; 782 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 783 pinctrl-names = "default"; 784 pinctrl-0 = <&qup_i2c16_default>; 785 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 786 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 787 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 788 dma-names = "tx", "rx"; 789 #address-cells = <1>; 790 #size-cells = <0>; 791 status = "disabled"; 792 }; 793 794 spi16: spi@888000 { 795 compatible = "qcom,geni-spi"; 796 reg = <0 0x00888000 0 0x4000>; 797 clock-names = "se"; 798 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 799 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 800 power-domains = <&rpmhpd SM8350_CX>; 801 operating-points-v2 = <&qup_opp_table_100mhz>; 802 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 803 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 804 dma-names = "tx", "rx"; 805 #address-cells = <1>; 806 #size-cells = <0>; 807 status = "disabled"; 808 }; 809 810 i2c17: i2c@88c000 { 811 compatible = "qcom,geni-i2c"; 812 reg = <0 0x0088c000 0 0x4000>; 813 clock-names = "se"; 814 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 815 pinctrl-names = "default"; 816 pinctrl-0 = <&qup_i2c17_default>; 817 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 818 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 819 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 820 dma-names = "tx", "rx"; 821 #address-cells = <1>; 822 #size-cells = <0>; 823 status = "disabled"; 824 }; 825 826 spi17: spi@88c000 { 827 compatible = "qcom,geni-spi"; 828 reg = <0 0x0088c000 0 0x4000>; 829 clock-names = "se"; 830 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 831 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 832 power-domains = <&rpmhpd SM8350_CX>; 833 operating-points-v2 = <&qup_opp_table_100mhz>; 834 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 835 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 836 dma-names = "tx", "rx"; 837 #address-cells = <1>; 838 #size-cells = <0>; 839 status = "disabled"; 840 }; 841 842 /* QUP no. 18 seems to be strictly SPI/UART-only */ 843 844 spi18: spi@890000 { 845 compatible = "qcom,geni-spi"; 846 reg = <0 0x00890000 0 0x4000>; 847 clock-names = "se"; 848 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 849 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 850 power-domains = <&rpmhpd SM8350_CX>; 851 operating-points-v2 = <&qup_opp_table_100mhz>; 852 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 853 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 854 dma-names = "tx", "rx"; 855 #address-cells = <1>; 856 #size-cells = <0>; 857 status = "disabled"; 858 }; 859 860 uart18: serial@890000 { 861 compatible = "qcom,geni-uart"; 862 reg = <0 0x00890000 0 0x4000>; 863 clock-names = "se"; 864 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 865 pinctrl-names = "default"; 866 pinctrl-0 = <&qup_uart18_default>; 867 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 868 power-domains = <&rpmhpd SM8350_CX>; 869 operating-points-v2 = <&qup_opp_table_100mhz>; 870 status = "disabled"; 871 }; 872 873 i2c19: i2c@894000 { 874 compatible = "qcom,geni-i2c"; 875 reg = <0 0x00894000 0 0x4000>; 876 clock-names = "se"; 877 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 878 pinctrl-names = "default"; 879 pinctrl-0 = <&qup_i2c19_default>; 880 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 881 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 882 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 883 dma-names = "tx", "rx"; 884 #address-cells = <1>; 885 #size-cells = <0>; 886 status = "disabled"; 887 }; 888 889 spi19: spi@894000 { 890 compatible = "qcom,geni-spi"; 891 reg = <0 0x00894000 0 0x4000>; 892 clock-names = "se"; 893 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 894 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 895 power-domains = <&rpmhpd SM8350_CX>; 896 operating-points-v2 = <&qup_opp_table_100mhz>; 897 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 898 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 899 dma-names = "tx", "rx"; 900 #address-cells = <1>; 901 #size-cells = <0>; 902 status = "disabled"; 903 }; 904 }; 905 906 gpi_dma0: dma-controller@900000 { 907 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 908 reg = <0 0x09800000 0 0x60000>; 909 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 911 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 916 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 917 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 918 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 919 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 920 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 921 dma-channels = <12>; 922 dma-channel-mask = <0x7e>; 923 iommus = <&apps_smmu 0x5b6 0x0>; 924 #dma-cells = <3>; 925 status = "disabled"; 926 }; 927 928 qupv3_id_0: geniqup@9c0000 { 929 compatible = "qcom,geni-se-qup"; 930 reg = <0x0 0x009c0000 0x0 0x6000>; 931 clock-names = "m-ahb", "s-ahb"; 932 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 933 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 934 iommus = <&apps_smmu 0x5a3 0>; 935 #address-cells = <2>; 936 #size-cells = <2>; 937 ranges; 938 status = "disabled"; 939 940 i2c0: i2c@980000 { 941 compatible = "qcom,geni-i2c"; 942 reg = <0 0x00980000 0 0x4000>; 943 clock-names = "se"; 944 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 945 pinctrl-names = "default"; 946 pinctrl-0 = <&qup_i2c0_default>; 947 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 948 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 949 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 950 dma-names = "tx", "rx"; 951 #address-cells = <1>; 952 #size-cells = <0>; 953 status = "disabled"; 954 }; 955 956 spi0: spi@980000 { 957 compatible = "qcom,geni-spi"; 958 reg = <0 0x00980000 0 0x4000>; 959 clock-names = "se"; 960 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 961 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 962 power-domains = <&rpmhpd SM8350_CX>; 963 operating-points-v2 = <&qup_opp_table_100mhz>; 964 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 965 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 966 dma-names = "tx", "rx"; 967 #address-cells = <1>; 968 #size-cells = <0>; 969 status = "disabled"; 970 }; 971 972 i2c1: i2c@984000 { 973 compatible = "qcom,geni-i2c"; 974 reg = <0 0x00984000 0 0x4000>; 975 clock-names = "se"; 976 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 977 pinctrl-names = "default"; 978 pinctrl-0 = <&qup_i2c1_default>; 979 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 980 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 981 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 982 dma-names = "tx", "rx"; 983 #address-cells = <1>; 984 #size-cells = <0>; 985 status = "disabled"; 986 }; 987 988 spi1: spi@984000 { 989 compatible = "qcom,geni-spi"; 990 reg = <0 0x00984000 0 0x4000>; 991 clock-names = "se"; 992 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 993 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 994 power-domains = <&rpmhpd SM8350_CX>; 995 operating-points-v2 = <&qup_opp_table_100mhz>; 996 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 997 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 998 dma-names = "tx", "rx"; 999 #address-cells = <1>; 1000 #size-cells = <0>; 1001 status = "disabled"; 1002 }; 1003 1004 i2c2: i2c@988000 { 1005 compatible = "qcom,geni-i2c"; 1006 reg = <0 0x00988000 0 0x4000>; 1007 clock-names = "se"; 1008 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1009 pinctrl-names = "default"; 1010 pinctrl-0 = <&qup_i2c2_default>; 1011 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1012 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1013 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1014 dma-names = "tx", "rx"; 1015 #address-cells = <1>; 1016 #size-cells = <0>; 1017 status = "disabled"; 1018 }; 1019 1020 spi2: spi@988000 { 1021 compatible = "qcom,geni-spi"; 1022 reg = <0 0x00988000 0 0x4000>; 1023 clock-names = "se"; 1024 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1025 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1026 power-domains = <&rpmhpd SM8350_CX>; 1027 operating-points-v2 = <&qup_opp_table_100mhz>; 1028 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1029 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1030 dma-names = "tx", "rx"; 1031 #address-cells = <1>; 1032 #size-cells = <0>; 1033 status = "disabled"; 1034 }; 1035 1036 uart2: serial@98c000 { 1037 compatible = "qcom,geni-debug-uart"; 1038 reg = <0 0x0098c000 0 0x4000>; 1039 clock-names = "se"; 1040 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1041 pinctrl-names = "default"; 1042 pinctrl-0 = <&qup_uart3_default_state>; 1043 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1044 power-domains = <&rpmhpd SM8350_CX>; 1045 operating-points-v2 = <&qup_opp_table_100mhz>; 1046 #address-cells = <1>; 1047 #size-cells = <0>; 1048 status = "disabled"; 1049 }; 1050 1051 /* QUP no. 3 seems to be strictly SPI-only */ 1052 1053 spi3: spi@98c000 { 1054 compatible = "qcom,geni-spi"; 1055 reg = <0 0x0098c000 0 0x4000>; 1056 clock-names = "se"; 1057 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1058 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1059 power-domains = <&rpmhpd SM8350_CX>; 1060 operating-points-v2 = <&qup_opp_table_100mhz>; 1061 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1062 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1063 dma-names = "tx", "rx"; 1064 #address-cells = <1>; 1065 #size-cells = <0>; 1066 status = "disabled"; 1067 }; 1068 1069 i2c4: i2c@990000 { 1070 compatible = "qcom,geni-i2c"; 1071 reg = <0 0x00990000 0 0x4000>; 1072 clock-names = "se"; 1073 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1074 pinctrl-names = "default"; 1075 pinctrl-0 = <&qup_i2c4_default>; 1076 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1077 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1078 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1079 dma-names = "tx", "rx"; 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 status = "disabled"; 1083 }; 1084 1085 spi4: spi@990000 { 1086 compatible = "qcom,geni-spi"; 1087 reg = <0 0x00990000 0 0x4000>; 1088 clock-names = "se"; 1089 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1090 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1091 power-domains = <&rpmhpd SM8350_CX>; 1092 operating-points-v2 = <&qup_opp_table_100mhz>; 1093 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1094 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1095 dma-names = "tx", "rx"; 1096 #address-cells = <1>; 1097 #size-cells = <0>; 1098 status = "disabled"; 1099 }; 1100 1101 i2c5: i2c@994000 { 1102 compatible = "qcom,geni-i2c"; 1103 reg = <0 0x00994000 0 0x4000>; 1104 clock-names = "se"; 1105 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1106 pinctrl-names = "default"; 1107 pinctrl-0 = <&qup_i2c5_default>; 1108 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1109 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1110 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1111 dma-names = "tx", "rx"; 1112 #address-cells = <1>; 1113 #size-cells = <0>; 1114 status = "disabled"; 1115 }; 1116 1117 spi5: spi@994000 { 1118 compatible = "qcom,geni-spi"; 1119 reg = <0 0x00994000 0 0x4000>; 1120 clock-names = "se"; 1121 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1122 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1123 power-domains = <&rpmhpd SM8350_CX>; 1124 operating-points-v2 = <&qup_opp_table_100mhz>; 1125 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1126 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1127 dma-names = "tx", "rx"; 1128 #address-cells = <1>; 1129 #size-cells = <0>; 1130 status = "disabled"; 1131 }; 1132 1133 i2c6: i2c@998000 { 1134 compatible = "qcom,geni-i2c"; 1135 reg = <0 0x00998000 0 0x4000>; 1136 clock-names = "se"; 1137 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1138 pinctrl-names = "default"; 1139 pinctrl-0 = <&qup_i2c6_default>; 1140 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1141 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1142 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1143 dma-names = "tx", "rx"; 1144 #address-cells = <1>; 1145 #size-cells = <0>; 1146 status = "disabled"; 1147 }; 1148 1149 spi6: spi@998000 { 1150 compatible = "qcom,geni-spi"; 1151 reg = <0 0x00998000 0 0x4000>; 1152 clock-names = "se"; 1153 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1154 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1155 power-domains = <&rpmhpd SM8350_CX>; 1156 operating-points-v2 = <&qup_opp_table_100mhz>; 1157 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1158 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1159 dma-names = "tx", "rx"; 1160 #address-cells = <1>; 1161 #size-cells = <0>; 1162 status = "disabled"; 1163 }; 1164 1165 uart6: serial@998000 { 1166 compatible = "qcom,geni-uart"; 1167 reg = <0 0x00998000 0 0x4000>; 1168 clock-names = "se"; 1169 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1170 pinctrl-names = "default"; 1171 pinctrl-0 = <&qup_uart6_default>; 1172 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1173 power-domains = <&rpmhpd SM8350_CX>; 1174 operating-points-v2 = <&qup_opp_table_100mhz>; 1175 status = "disabled"; 1176 }; 1177 1178 i2c7: i2c@99c000 { 1179 compatible = "qcom,geni-i2c"; 1180 reg = <0 0x0099c000 0 0x4000>; 1181 clock-names = "se"; 1182 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1183 pinctrl-names = "default"; 1184 pinctrl-0 = <&qup_i2c7_default>; 1185 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1186 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1187 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1188 dma-names = "tx", "rx"; 1189 #address-cells = <1>; 1190 #size-cells = <0>; 1191 status = "disabled"; 1192 }; 1193 1194 spi7: spi@99c000 { 1195 compatible = "qcom,geni-spi"; 1196 reg = <0 0x0099c000 0 0x4000>; 1197 clock-names = "se"; 1198 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1199 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1200 power-domains = <&rpmhpd SM8350_CX>; 1201 operating-points-v2 = <&qup_opp_table_100mhz>; 1202 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1203 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1204 dma-names = "tx", "rx"; 1205 #address-cells = <1>; 1206 #size-cells = <0>; 1207 status = "disabled"; 1208 }; 1209 }; 1210 1211 gpi_dma1: dma-controller@a00000 { 1212 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 1213 reg = <0 0x00a00000 0 0x60000>; 1214 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1226 dma-channels = <12>; 1227 dma-channel-mask = <0xff>; 1228 iommus = <&apps_smmu 0x56 0x0>; 1229 #dma-cells = <3>; 1230 status = "disabled"; 1231 }; 1232 1233 qupv3_id_1: geniqup@ac0000 { 1234 compatible = "qcom,geni-se-qup"; 1235 reg = <0x0 0x00ac0000 0x0 0x6000>; 1236 clock-names = "m-ahb", "s-ahb"; 1237 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1238 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1239 iommus = <&apps_smmu 0x43 0>; 1240 #address-cells = <2>; 1241 #size-cells = <2>; 1242 ranges; 1243 status = "disabled"; 1244 1245 i2c8: i2c@a80000 { 1246 compatible = "qcom,geni-i2c"; 1247 reg = <0 0x00a80000 0 0x4000>; 1248 clock-names = "se"; 1249 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1250 pinctrl-names = "default"; 1251 pinctrl-0 = <&qup_i2c8_default>; 1252 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1253 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1254 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1255 dma-names = "tx", "rx"; 1256 #address-cells = <1>; 1257 #size-cells = <0>; 1258 status = "disabled"; 1259 }; 1260 1261 spi8: spi@a80000 { 1262 compatible = "qcom,geni-spi"; 1263 reg = <0 0x00a80000 0 0x4000>; 1264 clock-names = "se"; 1265 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1266 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1267 power-domains = <&rpmhpd SM8350_CX>; 1268 operating-points-v2 = <&qup_opp_table_120mhz>; 1269 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1270 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1271 dma-names = "tx", "rx"; 1272 #address-cells = <1>; 1273 #size-cells = <0>; 1274 status = "disabled"; 1275 }; 1276 1277 i2c9: i2c@a84000 { 1278 compatible = "qcom,geni-i2c"; 1279 reg = <0 0x00a84000 0 0x4000>; 1280 clock-names = "se"; 1281 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1282 pinctrl-names = "default"; 1283 pinctrl-0 = <&qup_i2c9_default>; 1284 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1285 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1286 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1287 dma-names = "tx", "rx"; 1288 #address-cells = <1>; 1289 #size-cells = <0>; 1290 status = "disabled"; 1291 }; 1292 1293 spi9: spi@a84000 { 1294 compatible = "qcom,geni-spi"; 1295 reg = <0 0x00a84000 0 0x4000>; 1296 clock-names = "se"; 1297 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1298 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1299 power-domains = <&rpmhpd SM8350_CX>; 1300 operating-points-v2 = <&qup_opp_table_100mhz>; 1301 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1302 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1303 dma-names = "tx", "rx"; 1304 #address-cells = <1>; 1305 #size-cells = <0>; 1306 status = "disabled"; 1307 }; 1308 1309 i2c10: i2c@a88000 { 1310 compatible = "qcom,geni-i2c"; 1311 reg = <0 0x00a88000 0 0x4000>; 1312 clock-names = "se"; 1313 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1314 pinctrl-names = "default"; 1315 pinctrl-0 = <&qup_i2c10_default>; 1316 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1317 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1318 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1319 dma-names = "tx", "rx"; 1320 #address-cells = <1>; 1321 #size-cells = <0>; 1322 status = "disabled"; 1323 }; 1324 1325 spi10: spi@a88000 { 1326 compatible = "qcom,geni-spi"; 1327 reg = <0 0x00a88000 0 0x4000>; 1328 clock-names = "se"; 1329 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1330 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1331 power-domains = <&rpmhpd SM8350_CX>; 1332 operating-points-v2 = <&qup_opp_table_100mhz>; 1333 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1334 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1335 dma-names = "tx", "rx"; 1336 #address-cells = <1>; 1337 #size-cells = <0>; 1338 status = "disabled"; 1339 }; 1340 1341 i2c11: i2c@a8c000 { 1342 compatible = "qcom,geni-i2c"; 1343 reg = <0 0x00a8c000 0 0x4000>; 1344 clock-names = "se"; 1345 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1346 pinctrl-names = "default"; 1347 pinctrl-0 = <&qup_i2c11_default>; 1348 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1349 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1350 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1351 dma-names = "tx", "rx"; 1352 #address-cells = <1>; 1353 #size-cells = <0>; 1354 status = "disabled"; 1355 }; 1356 1357 spi11: spi@a8c000 { 1358 compatible = "qcom,geni-spi"; 1359 reg = <0 0x00a8c000 0 0x4000>; 1360 clock-names = "se"; 1361 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1362 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1363 power-domains = <&rpmhpd SM8350_CX>; 1364 operating-points-v2 = <&qup_opp_table_100mhz>; 1365 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1366 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1367 dma-names = "tx", "rx"; 1368 #address-cells = <1>; 1369 #size-cells = <0>; 1370 status = "disabled"; 1371 }; 1372 1373 i2c12: i2c@a90000 { 1374 compatible = "qcom,geni-i2c"; 1375 reg = <0 0x00a90000 0 0x4000>; 1376 clock-names = "se"; 1377 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1378 pinctrl-names = "default"; 1379 pinctrl-0 = <&qup_i2c12_default>; 1380 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1381 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1382 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1383 dma-names = "tx", "rx"; 1384 #address-cells = <1>; 1385 #size-cells = <0>; 1386 status = "disabled"; 1387 }; 1388 1389 spi12: spi@a90000 { 1390 compatible = "qcom,geni-spi"; 1391 reg = <0 0x00a90000 0 0x4000>; 1392 clock-names = "se"; 1393 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1394 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1395 power-domains = <&rpmhpd SM8350_CX>; 1396 operating-points-v2 = <&qup_opp_table_100mhz>; 1397 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1398 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1399 dma-names = "tx", "rx"; 1400 #address-cells = <1>; 1401 #size-cells = <0>; 1402 status = "disabled"; 1403 }; 1404 1405 i2c13: i2c@a94000 { 1406 compatible = "qcom,geni-i2c"; 1407 reg = <0 0x00a94000 0 0x4000>; 1408 clock-names = "se"; 1409 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1410 pinctrl-names = "default"; 1411 pinctrl-0 = <&qup_i2c13_default>; 1412 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1413 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1414 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1415 dma-names = "tx", "rx"; 1416 #address-cells = <1>; 1417 #size-cells = <0>; 1418 status = "disabled"; 1419 }; 1420 1421 spi13: spi@a94000 { 1422 compatible = "qcom,geni-spi"; 1423 reg = <0 0x00a94000 0 0x4000>; 1424 clock-names = "se"; 1425 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1426 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1427 power-domains = <&rpmhpd SM8350_CX>; 1428 operating-points-v2 = <&qup_opp_table_100mhz>; 1429 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1430 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1431 dma-names = "tx", "rx"; 1432 #address-cells = <1>; 1433 #size-cells = <0>; 1434 status = "disabled"; 1435 }; 1436 }; 1437 1438 apps_smmu: iommu@15000000 { 1439 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; 1440 reg = <0 0x15000000 0 0x100000>; 1441 #iommu-cells = <2>; 1442 #global-interrupts = <2>; 1443 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1461 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1464 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1465 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1466 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1471 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1473 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1476 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1490 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1491 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1492 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1493 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1494 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1495 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1496 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1497 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1498 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1499 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1500 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1501 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1502 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1503 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1504 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1505 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1506 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1507 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1508 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1509 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1510 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1511 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1512 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1513 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1514 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1515 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1516 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1517 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1518 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1519 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 1521 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 1522 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 1540 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 1541 }; 1542 1543 config_noc: interconnect@1500000 { 1544 compatible = "qcom,sm8350-config-noc"; 1545 reg = <0 0x01500000 0 0xa580>; 1546 #interconnect-cells = <1>; 1547 qcom,bcm-voters = <&apps_bcm_voter>; 1548 }; 1549 1550 mc_virt: interconnect@1580000 { 1551 compatible = "qcom,sm8350-mc-virt"; 1552 reg = <0 0x01580000 0 0x1000>; 1553 #interconnect-cells = <1>; 1554 qcom,bcm-voters = <&apps_bcm_voter>; 1555 }; 1556 1557 system_noc: interconnect@1680000 { 1558 compatible = "qcom,sm8350-system-noc"; 1559 reg = <0 0x01680000 0 0x1c200>; 1560 #interconnect-cells = <1>; 1561 qcom,bcm-voters = <&apps_bcm_voter>; 1562 }; 1563 1564 aggre1_noc: interconnect@16e0000 { 1565 compatible = "qcom,sm8350-aggre1-noc"; 1566 reg = <0 0x016e0000 0 0x1f180>; 1567 #interconnect-cells = <1>; 1568 qcom,bcm-voters = <&apps_bcm_voter>; 1569 }; 1570 1571 aggre2_noc: interconnect@1700000 { 1572 compatible = "qcom,sm8350-aggre2-noc"; 1573 reg = <0 0x01700000 0 0x33000>; 1574 #interconnect-cells = <1>; 1575 qcom,bcm-voters = <&apps_bcm_voter>; 1576 }; 1577 1578 mmss_noc: interconnect@1740000 { 1579 compatible = "qcom,sm8350-mmss-noc"; 1580 reg = <0 0x01740000 0 0x1f080>; 1581 #interconnect-cells = <1>; 1582 qcom,bcm-voters = <&apps_bcm_voter>; 1583 }; 1584 1585 lpass_ag_noc: interconnect@3c40000 { 1586 compatible = "qcom,sm8350-lpass-ag-noc"; 1587 reg = <0 0x03c40000 0 0xf080>; 1588 #interconnect-cells = <1>; 1589 qcom,bcm-voters = <&apps_bcm_voter>; 1590 }; 1591 1592 compute_noc: interconnect@a0c0000{ 1593 compatible = "qcom,sm8350-compute-noc"; 1594 reg = <0 0x0a0c0000 0 0xa180>; 1595 #interconnect-cells = <1>; 1596 qcom,bcm-voters = <&apps_bcm_voter>; 1597 }; 1598 1599 ipa: ipa@1e40000 { 1600 compatible = "qcom,sm8350-ipa"; 1601 1602 iommus = <&apps_smmu 0x5c0 0x0>, 1603 <&apps_smmu 0x5c2 0x0>; 1604 reg = <0 0x1e40000 0 0x8000>, 1605 <0 0x1e50000 0 0x4b20>, 1606 <0 0x1e04000 0 0x23000>; 1607 reg-names = "ipa-reg", 1608 "ipa-shared", 1609 "gsi"; 1610 1611 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, 1612 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1613 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1614 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1615 interrupt-names = "ipa", 1616 "gsi", 1617 "ipa-clock-query", 1618 "ipa-setup-ready"; 1619 1620 clocks = <&rpmhcc RPMH_IPA_CLK>; 1621 clock-names = "core"; 1622 1623 interconnects = <&aggre2_noc MASTER_IPA &mc_virt SLAVE_EBI1>, 1624 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>; 1625 interconnect-names = "memory", 1626 "config"; 1627 1628 qcom,qmp = <&aoss_qmp>; 1629 1630 qcom,smem-states = <&ipa_smp2p_out 0>, 1631 <&ipa_smp2p_out 1>; 1632 qcom,smem-state-names = "ipa-clock-enabled-valid", 1633 "ipa-clock-enabled"; 1634 1635 status = "disabled"; 1636 }; 1637 1638 tcsr_mutex: hwlock@1f40000 { 1639 compatible = "qcom,tcsr-mutex"; 1640 reg = <0x0 0x01f40000 0x0 0x40000>; 1641 #hwlock-cells = <1>; 1642 }; 1643 1644 mpss: remoteproc@4080000 { 1645 compatible = "qcom,sm8350-mpss-pas"; 1646 reg = <0x0 0x04080000 0x0 0x4040>; 1647 1648 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 1649 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 1650 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 1651 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 1652 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 1653 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 1654 interrupt-names = "wdog", "fatal", "ready", "handover", 1655 "stop-ack", "shutdown-ack"; 1656 1657 clocks = <&rpmhcc RPMH_CXO_CLK>; 1658 clock-names = "xo"; 1659 1660 power-domains = <&rpmhpd SM8350_CX>, 1661 <&rpmhpd SM8350_MSS>; 1662 power-domain-names = "cx", "mss"; 1663 1664 interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; 1665 1666 memory-region = <&pil_modem_mem>; 1667 1668 qcom,qmp = <&aoss_qmp>; 1669 1670 qcom,smem-states = <&smp2p_modem_out 0>; 1671 qcom,smem-state-names = "stop"; 1672 1673 status = "disabled"; 1674 1675 glink-edge { 1676 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1677 IPCC_MPROC_SIGNAL_GLINK_QMP 1678 IRQ_TYPE_EDGE_RISING>; 1679 mboxes = <&ipcc IPCC_CLIENT_MPSS 1680 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1681 label = "modem"; 1682 qcom,remote-pid = <1>; 1683 }; 1684 }; 1685 1686 pdc: interrupt-controller@b220000 { 1687 compatible = "qcom,sm8350-pdc", "qcom,pdc"; 1688 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 1689 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, 1690 <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, 1691 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, 1692 <156 716 12>; 1693 #interrupt-cells = <2>; 1694 interrupt-parent = <&intc>; 1695 interrupt-controller; 1696 }; 1697 1698 tsens0: thermal-sensor@c263000 { 1699 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 1700 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 1701 <0 0x0c222000 0 0x8>; /* SROT */ 1702 #qcom,sensors = <15>; 1703 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 1704 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 1705 interrupt-names = "uplow", "critical"; 1706 #thermal-sensor-cells = <1>; 1707 }; 1708 1709 tsens1: thermal-sensor@c265000 { 1710 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 1711 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 1712 <0 0x0c223000 0 0x8>; /* SROT */ 1713 #qcom,sensors = <14>; 1714 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 1715 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 1716 interrupt-names = "uplow", "critical"; 1717 #thermal-sensor-cells = <1>; 1718 }; 1719 1720 aoss_qmp: power-controller@c300000 { 1721 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; 1722 reg = <0 0x0c300000 0 0x400>; 1723 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 1724 IRQ_TYPE_EDGE_RISING>; 1725 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 1726 1727 #clock-cells = <0>; 1728 }; 1729 1730 sram@c3f0000 { 1731 compatible = "qcom,rpmh-stats"; 1732 reg = <0 0x0c3f0000 0 0x400>; 1733 }; 1734 1735 spmi_bus: spmi@c440000 { 1736 compatible = "qcom,spmi-pmic-arb"; 1737 reg = <0x0 0xc440000 0x0 0x1100>, 1738 <0x0 0xc600000 0x0 0x2000000>, 1739 <0x0 0xe600000 0x0 0x100000>, 1740 <0x0 0xe700000 0x0 0xa0000>, 1741 <0x0 0xc40a000 0x0 0x26000>; 1742 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1743 interrupt-names = "periph_irq"; 1744 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 1745 qcom,ee = <0>; 1746 qcom,channel = <0>; 1747 #address-cells = <2>; 1748 #size-cells = <0>; 1749 interrupt-controller; 1750 #interrupt-cells = <4>; 1751 }; 1752 1753 tlmm: pinctrl@f100000 { 1754 compatible = "qcom,sm8350-tlmm"; 1755 reg = <0 0x0f100000 0 0x300000>; 1756 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1757 gpio-controller; 1758 #gpio-cells = <2>; 1759 interrupt-controller; 1760 #interrupt-cells = <2>; 1761 gpio-ranges = <&tlmm 0 0 204>; 1762 wakeup-parent = <&pdc>; 1763 1764 sdc2_default_state: sdc2-default-state { 1765 clk-pins { 1766 pins = "sdc2_clk"; 1767 drive-strength = <16>; 1768 bias-disable; 1769 }; 1770 1771 cmd-pins { 1772 pins = "sdc2_cmd"; 1773 drive-strength = <16>; 1774 bias-pull-up; 1775 }; 1776 1777 data-pins { 1778 pins = "sdc2_data"; 1779 drive-strength = <16>; 1780 bias-pull-up; 1781 }; 1782 }; 1783 1784 sdc2_sleep_state: sdc2-sleep-state { 1785 clk-pins { 1786 pins = "sdc2_clk"; 1787 drive-strength = <2>; 1788 bias-disable; 1789 }; 1790 1791 cmd-pins { 1792 pins = "sdc2_cmd"; 1793 drive-strength = <2>; 1794 bias-pull-up; 1795 }; 1796 1797 data-pins { 1798 pins = "sdc2_data"; 1799 drive-strength = <2>; 1800 bias-pull-up; 1801 }; 1802 }; 1803 1804 qup_uart3_default_state: qup-uart3-default-state { 1805 rx-pins { 1806 pins = "gpio18"; 1807 function = "qup3"; 1808 }; 1809 tx-pins { 1810 pins = "gpio19"; 1811 function = "qup3"; 1812 }; 1813 }; 1814 1815 qup_uart6_default: qup-uart6-default-state { 1816 pins = "gpio30", "gpio31"; 1817 function = "qup6"; 1818 drive-strength = <2>; 1819 bias-disable; 1820 }; 1821 1822 qup_uart18_default: qup-uart18-default-state { 1823 pins = "gpio58", "gpio59"; 1824 function = "qup18"; 1825 drive-strength = <2>; 1826 bias-disable; 1827 }; 1828 1829 qup_i2c0_default: qup-i2c0-default-state { 1830 pins = "gpio4", "gpio5"; 1831 function = "qup0"; 1832 drive-strength = <2>; 1833 bias-pull-up; 1834 }; 1835 1836 qup_i2c1_default: qup-i2c1-default-state { 1837 pins = "gpio8", "gpio9"; 1838 function = "qup1"; 1839 drive-strength = <2>; 1840 bias-pull-up; 1841 }; 1842 1843 qup_i2c2_default: qup-i2c2-default-state { 1844 pins = "gpio12", "gpio13"; 1845 function = "qup2"; 1846 drive-strength = <2>; 1847 bias-pull-up; 1848 }; 1849 1850 qup_i2c4_default: qup-i2c4-default-state { 1851 pins = "gpio20", "gpio21"; 1852 function = "qup4"; 1853 drive-strength = <2>; 1854 bias-pull-up; 1855 }; 1856 1857 qup_i2c5_default: qup-i2c5-default-state { 1858 pins = "gpio24", "gpio25"; 1859 function = "qup5"; 1860 drive-strength = <2>; 1861 bias-pull-up; 1862 }; 1863 1864 qup_i2c6_default: qup-i2c6-default-state { 1865 pins = "gpio28", "gpio29"; 1866 function = "qup6"; 1867 drive-strength = <2>; 1868 bias-pull-up; 1869 }; 1870 1871 qup_i2c7_default: qup-i2c7-default-state { 1872 pins = "gpio32", "gpio33"; 1873 function = "qup7"; 1874 drive-strength = <2>; 1875 bias-disable; 1876 }; 1877 1878 qup_i2c8_default: qup-i2c8-default-state { 1879 pins = "gpio36", "gpio37"; 1880 function = "qup8"; 1881 drive-strength = <2>; 1882 bias-pull-up; 1883 }; 1884 1885 qup_i2c9_default: qup-i2c9-default-state { 1886 pins = "gpio40", "gpio41"; 1887 function = "qup9"; 1888 drive-strength = <2>; 1889 bias-pull-up; 1890 }; 1891 1892 qup_i2c10_default: qup-i2c10-default-state { 1893 pins = "gpio44", "gpio45"; 1894 function = "qup10"; 1895 drive-strength = <2>; 1896 bias-pull-up; 1897 }; 1898 1899 qup_i2c11_default: qup-i2c11-default-state { 1900 pins = "gpio48", "gpio49"; 1901 function = "qup11"; 1902 drive-strength = <2>; 1903 bias-pull-up; 1904 }; 1905 1906 qup_i2c12_default: qup-i2c12-default-state { 1907 pins = "gpio52", "gpio53"; 1908 function = "qup12"; 1909 drive-strength = <2>; 1910 bias-pull-up; 1911 }; 1912 1913 qup_i2c13_default: qup-i2c13-default-state { 1914 pins = "gpio0", "gpio1"; 1915 function = "qup13"; 1916 drive-strength = <2>; 1917 bias-pull-up; 1918 }; 1919 1920 qup_i2c14_default: qup-i2c14-default-state { 1921 pins = "gpio56", "gpio57"; 1922 function = "qup14"; 1923 drive-strength = <2>; 1924 bias-disable; 1925 }; 1926 1927 qup_i2c15_default: qup-i2c15-default-state { 1928 pins = "gpio60", "gpio61"; 1929 function = "qup15"; 1930 drive-strength = <2>; 1931 bias-disable; 1932 }; 1933 1934 qup_i2c16_default: qup-i2c16-default-state { 1935 pins = "gpio64", "gpio65"; 1936 function = "qup16"; 1937 drive-strength = <2>; 1938 bias-disable; 1939 }; 1940 1941 qup_i2c17_default: qup-i2c17-default-state { 1942 pins = "gpio72", "gpio73"; 1943 function = "qup17"; 1944 drive-strength = <2>; 1945 bias-disable; 1946 }; 1947 1948 qup_i2c19_default: qup-i2c19-default-state { 1949 pins = "gpio76", "gpio77"; 1950 function = "qup19"; 1951 drive-strength = <2>; 1952 bias-disable; 1953 }; 1954 }; 1955 1956 rng: rng@10d3000 { 1957 compatible = "qcom,prng-ee"; 1958 reg = <0 0x010d3000 0 0x1000>; 1959 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1960 clock-names = "core"; 1961 }; 1962 1963 intc: interrupt-controller@17a00000 { 1964 compatible = "arm,gic-v3"; 1965 #interrupt-cells = <3>; 1966 interrupt-controller; 1967 #redistributor-regions = <1>; 1968 redistributor-stride = <0 0x20000>; 1969 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 1970 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 1971 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1972 }; 1973 1974 timer@17c20000 { 1975 compatible = "arm,armv7-timer-mem"; 1976 #address-cells = <1>; 1977 #size-cells = <1>; 1978 ranges = <0 0 0 0x20000000>; 1979 reg = <0x0 0x17c20000 0x0 0x1000>; 1980 clock-frequency = <19200000>; 1981 1982 frame@17c21000 { 1983 frame-number = <0>; 1984 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1985 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1986 reg = <0x17c21000 0x1000>, 1987 <0x17c22000 0x1000>; 1988 }; 1989 1990 frame@17c23000 { 1991 frame-number = <1>; 1992 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1993 reg = <0x17c23000 0x1000>; 1994 status = "disabled"; 1995 }; 1996 1997 frame@17c25000 { 1998 frame-number = <2>; 1999 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2000 reg = <0x17c25000 0x1000>; 2001 status = "disabled"; 2002 }; 2003 2004 frame@17c27000 { 2005 frame-number = <3>; 2006 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2007 reg = <0x17c27000 0x1000>; 2008 status = "disabled"; 2009 }; 2010 2011 frame@17c29000 { 2012 frame-number = <4>; 2013 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2014 reg = <0x17c29000 0x1000>; 2015 status = "disabled"; 2016 }; 2017 2018 frame@17c2b000 { 2019 frame-number = <5>; 2020 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2021 reg = <0x17c2b000 0x1000>; 2022 status = "disabled"; 2023 }; 2024 2025 frame@17c2d000 { 2026 frame-number = <6>; 2027 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2028 reg = <0x17c2d000 0x1000>; 2029 status = "disabled"; 2030 }; 2031 }; 2032 2033 apps_rsc: rsc@18200000 { 2034 label = "apps_rsc"; 2035 compatible = "qcom,rpmh-rsc"; 2036 reg = <0x0 0x18200000 0x0 0x10000>, 2037 <0x0 0x18210000 0x0 0x10000>, 2038 <0x0 0x18220000 0x0 0x10000>; 2039 reg-names = "drv-0", "drv-1", "drv-2"; 2040 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2041 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2042 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 2043 qcom,tcs-offset = <0xd00>; 2044 qcom,drv-id = <2>; 2045 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 2046 <WAKE_TCS 3>, <CONTROL_TCS 0>; 2047 power-domains = <&CLUSTER_PD>; 2048 2049 rpmhcc: clock-controller { 2050 compatible = "qcom,sm8350-rpmh-clk"; 2051 #clock-cells = <1>; 2052 clock-names = "xo"; 2053 clocks = <&xo_board>; 2054 }; 2055 2056 rpmhpd: power-controller { 2057 compatible = "qcom,sm8350-rpmhpd"; 2058 #power-domain-cells = <1>; 2059 operating-points-v2 = <&rpmhpd_opp_table>; 2060 2061 rpmhpd_opp_table: opp-table { 2062 compatible = "operating-points-v2"; 2063 2064 rpmhpd_opp_ret: opp1 { 2065 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 2066 }; 2067 2068 rpmhpd_opp_min_svs: opp2 { 2069 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2070 }; 2071 2072 rpmhpd_opp_low_svs: opp3 { 2073 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2074 }; 2075 2076 rpmhpd_opp_svs: opp4 { 2077 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2078 }; 2079 2080 rpmhpd_opp_svs_l1: opp5 { 2081 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2082 }; 2083 2084 rpmhpd_opp_nom: opp6 { 2085 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2086 }; 2087 2088 rpmhpd_opp_nom_l1: opp7 { 2089 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2090 }; 2091 2092 rpmhpd_opp_nom_l2: opp8 { 2093 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 2094 }; 2095 2096 rpmhpd_opp_turbo: opp9 { 2097 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2098 }; 2099 2100 rpmhpd_opp_turbo_l1: opp10 { 2101 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2102 }; 2103 }; 2104 }; 2105 2106 apps_bcm_voter: bcm-voter { 2107 compatible = "qcom,bcm-voter"; 2108 }; 2109 }; 2110 2111 cpufreq_hw: cpufreq@18591000 { 2112 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss"; 2113 reg = <0 0x18591000 0 0x1000>, 2114 <0 0x18592000 0 0x1000>, 2115 <0 0x18593000 0 0x1000>; 2116 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 2117 2118 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 2119 clock-names = "xo", "alternate"; 2120 2121 #freq-domain-cells = <1>; 2122 }; 2123 2124 ufs_mem_hc: ufshc@1d84000 { 2125 compatible = "qcom,sm8350-ufshc", "qcom,ufshc", 2126 "jedec,ufs-2.0"; 2127 reg = <0 0x01d84000 0 0x3000>; 2128 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2129 phys = <&ufs_mem_phy_lanes>; 2130 phy-names = "ufsphy"; 2131 lanes-per-direction = <2>; 2132 #reset-cells = <1>; 2133 resets = <&gcc GCC_UFS_PHY_BCR>; 2134 reset-names = "rst"; 2135 2136 power-domains = <&gcc UFS_PHY_GDSC>; 2137 2138 iommus = <&apps_smmu 0xe0 0x0>; 2139 2140 clock-names = 2141 "core_clk", 2142 "bus_aggr_clk", 2143 "iface_clk", 2144 "core_clk_unipro", 2145 "ref_clk", 2146 "tx_lane0_sync_clk", 2147 "rx_lane0_sync_clk", 2148 "rx_lane1_sync_clk"; 2149 clocks = 2150 <&gcc GCC_UFS_PHY_AXI_CLK>, 2151 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2152 <&gcc GCC_UFS_PHY_AHB_CLK>, 2153 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2154 <&rpmhcc RPMH_CXO_CLK>, 2155 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2156 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2157 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2158 freq-table-hz = 2159 <75000000 300000000>, 2160 <0 0>, 2161 <0 0>, 2162 <75000000 300000000>, 2163 <0 0>, 2164 <0 0>, 2165 <0 0>, 2166 <0 0>; 2167 status = "disabled"; 2168 }; 2169 2170 ufs_mem_phy: phy@1d87000 { 2171 compatible = "qcom,sm8350-qmp-ufs-phy"; 2172 reg = <0 0x01d87000 0 0x1c4>; 2173 #address-cells = <2>; 2174 #size-cells = <2>; 2175 ranges; 2176 clock-names = "ref", 2177 "ref_aux"; 2178 clocks = <&rpmhcc RPMH_CXO_CLK>, 2179 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2180 2181 resets = <&ufs_mem_hc 0>; 2182 reset-names = "ufsphy"; 2183 status = "disabled"; 2184 2185 ufs_mem_phy_lanes: phy@1d87400 { 2186 reg = <0 0x01d87400 0 0x188>, 2187 <0 0x01d87600 0 0x200>, 2188 <0 0x01d87c00 0 0x200>, 2189 <0 0x01d87800 0 0x188>, 2190 <0 0x01d87a00 0 0x200>; 2191 #phy-cells = <0>; 2192 }; 2193 }; 2194 2195 slpi: remoteproc@5c00000 { 2196 compatible = "qcom,sm8350-slpi-pas"; 2197 reg = <0 0x05c00000 0 0x4000>; 2198 2199 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 2200 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2201 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2202 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2203 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2204 interrupt-names = "wdog", "fatal", "ready", 2205 "handover", "stop-ack"; 2206 2207 clocks = <&rpmhcc RPMH_CXO_CLK>; 2208 clock-names = "xo"; 2209 2210 power-domains = <&rpmhpd SM8350_LCX>, 2211 <&rpmhpd SM8350_LMX>; 2212 power-domain-names = "lcx", "lmx"; 2213 2214 memory-region = <&pil_slpi_mem>; 2215 2216 qcom,qmp = <&aoss_qmp>; 2217 2218 qcom,smem-states = <&smp2p_slpi_out 0>; 2219 qcom,smem-state-names = "stop"; 2220 2221 status = "disabled"; 2222 2223 glink-edge { 2224 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2225 IPCC_MPROC_SIGNAL_GLINK_QMP 2226 IRQ_TYPE_EDGE_RISING>; 2227 mboxes = <&ipcc IPCC_CLIENT_SLPI 2228 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2229 2230 label = "slpi"; 2231 qcom,remote-pid = <3>; 2232 2233 fastrpc { 2234 compatible = "qcom,fastrpc"; 2235 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2236 label = "sdsp"; 2237 qcom,non-secure-domain; 2238 #address-cells = <1>; 2239 #size-cells = <0>; 2240 2241 compute-cb@1 { 2242 compatible = "qcom,fastrpc-compute-cb"; 2243 reg = <1>; 2244 iommus = <&apps_smmu 0x0541 0x0>; 2245 }; 2246 2247 compute-cb@2 { 2248 compatible = "qcom,fastrpc-compute-cb"; 2249 reg = <2>; 2250 iommus = <&apps_smmu 0x0542 0x0>; 2251 }; 2252 2253 compute-cb@3 { 2254 compatible = "qcom,fastrpc-compute-cb"; 2255 reg = <3>; 2256 iommus = <&apps_smmu 0x0543 0x0>; 2257 /* note: shared-cb = <4> in downstream */ 2258 }; 2259 }; 2260 }; 2261 }; 2262 2263 cdsp: remoteproc@98900000 { 2264 compatible = "qcom,sm8350-cdsp-pas"; 2265 reg = <0 0x98900000 0 0x1400000>; 2266 2267 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 2268 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2269 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2270 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2271 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 2272 interrupt-names = "wdog", "fatal", "ready", 2273 "handover", "stop-ack"; 2274 2275 clocks = <&rpmhcc RPMH_CXO_CLK>; 2276 clock-names = "xo"; 2277 2278 power-domains = <&rpmhpd SM8350_CX>, 2279 <&rpmhpd SM8350_MXC>; 2280 power-domain-names = "cx", "mxc"; 2281 2282 interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; 2283 2284 memory-region = <&pil_cdsp_mem>; 2285 2286 qcom,qmp = <&aoss_qmp>; 2287 2288 qcom,smem-states = <&smp2p_cdsp_out 0>; 2289 qcom,smem-state-names = "stop"; 2290 2291 status = "disabled"; 2292 2293 glink-edge { 2294 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2295 IPCC_MPROC_SIGNAL_GLINK_QMP 2296 IRQ_TYPE_EDGE_RISING>; 2297 mboxes = <&ipcc IPCC_CLIENT_CDSP 2298 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2299 2300 label = "cdsp"; 2301 qcom,remote-pid = <5>; 2302 2303 fastrpc { 2304 compatible = "qcom,fastrpc"; 2305 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2306 label = "cdsp"; 2307 qcom,non-secure-domain; 2308 #address-cells = <1>; 2309 #size-cells = <0>; 2310 2311 compute-cb@1 { 2312 compatible = "qcom,fastrpc-compute-cb"; 2313 reg = <1>; 2314 iommus = <&apps_smmu 0x2161 0x0400>, 2315 <&apps_smmu 0x1181 0x0420>; 2316 }; 2317 2318 compute-cb@2 { 2319 compatible = "qcom,fastrpc-compute-cb"; 2320 reg = <2>; 2321 iommus = <&apps_smmu 0x2162 0x0400>, 2322 <&apps_smmu 0x1182 0x0420>; 2323 }; 2324 2325 compute-cb@3 { 2326 compatible = "qcom,fastrpc-compute-cb"; 2327 reg = <3>; 2328 iommus = <&apps_smmu 0x2163 0x0400>, 2329 <&apps_smmu 0x1183 0x0420>; 2330 }; 2331 2332 compute-cb@4 { 2333 compatible = "qcom,fastrpc-compute-cb"; 2334 reg = <4>; 2335 iommus = <&apps_smmu 0x2164 0x0400>, 2336 <&apps_smmu 0x1184 0x0420>; 2337 }; 2338 2339 compute-cb@5 { 2340 compatible = "qcom,fastrpc-compute-cb"; 2341 reg = <5>; 2342 iommus = <&apps_smmu 0x2165 0x0400>, 2343 <&apps_smmu 0x1185 0x0420>; 2344 }; 2345 2346 compute-cb@6 { 2347 compatible = "qcom,fastrpc-compute-cb"; 2348 reg = <6>; 2349 iommus = <&apps_smmu 0x2166 0x0400>, 2350 <&apps_smmu 0x1186 0x0420>; 2351 }; 2352 2353 compute-cb@7 { 2354 compatible = "qcom,fastrpc-compute-cb"; 2355 reg = <7>; 2356 iommus = <&apps_smmu 0x2167 0x0400>, 2357 <&apps_smmu 0x1187 0x0420>; 2358 }; 2359 2360 compute-cb@8 { 2361 compatible = "qcom,fastrpc-compute-cb"; 2362 reg = <8>; 2363 iommus = <&apps_smmu 0x2168 0x0400>, 2364 <&apps_smmu 0x1188 0x0420>; 2365 }; 2366 2367 /* note: secure cb9 in downstream */ 2368 }; 2369 }; 2370 }; 2371 2372 sdhc_2: sdhci@8804000 { 2373 compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5"; 2374 reg = <0 0x08804000 0 0x1000>; 2375 2376 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2377 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2378 interrupt-names = "hc_irq", "pwr_irq"; 2379 2380 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2381 <&gcc GCC_SDCC2_APPS_CLK>, 2382 <&rpmhcc RPMH_CXO_CLK>; 2383 clock-names = "iface", "core", "xo"; 2384 resets = <&gcc GCC_SDCC2_BCR>; 2385 interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>, 2386 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>; 2387 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2388 iommus = <&apps_smmu 0x4a0 0x0>; 2389 power-domains = <&rpmhpd SM8350_CX>; 2390 operating-points-v2 = <&sdhc2_opp_table>; 2391 bus-width = <4>; 2392 dma-coherent; 2393 2394 status = "disabled"; 2395 2396 sdhc2_opp_table: opp-table { 2397 compatible = "operating-points-v2"; 2398 2399 opp-100000000 { 2400 opp-hz = /bits/ 64 <100000000>; 2401 required-opps = <&rpmhpd_opp_low_svs>; 2402 }; 2403 2404 opp-202000000 { 2405 opp-hz = /bits/ 64 <202000000>; 2406 required-opps = <&rpmhpd_opp_svs_l1>; 2407 }; 2408 }; 2409 }; 2410 2411 usb_1_hsphy: phy@88e3000 { 2412 compatible = "qcom,sm8350-usb-hs-phy", 2413 "qcom,usb-snps-hs-7nm-phy"; 2414 reg = <0 0x088e3000 0 0x400>; 2415 status = "disabled"; 2416 #phy-cells = <0>; 2417 2418 clocks = <&rpmhcc RPMH_CXO_CLK>; 2419 clock-names = "ref"; 2420 2421 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2422 }; 2423 2424 usb_2_hsphy: phy@88e4000 { 2425 compatible = "qcom,sm8250-usb-hs-phy", 2426 "qcom,usb-snps-hs-7nm-phy"; 2427 reg = <0 0x088e4000 0 0x400>; 2428 status = "disabled"; 2429 #phy-cells = <0>; 2430 2431 clocks = <&rpmhcc RPMH_CXO_CLK>; 2432 clock-names = "ref"; 2433 2434 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2435 }; 2436 2437 usb_1_qmpphy: phy-wrapper@88e9000 { 2438 compatible = "qcom,sm8350-qmp-usb3-phy"; 2439 reg = <0 0x088e9000 0 0x200>, 2440 <0 0x088e8000 0 0x20>; 2441 status = "disabled"; 2442 #address-cells = <2>; 2443 #size-cells = <2>; 2444 ranges; 2445 2446 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2447 <&rpmhcc RPMH_CXO_CLK>, 2448 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2449 clock-names = "aux", "ref_clk_src", "com_aux"; 2450 2451 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2452 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2453 reset-names = "phy", "common"; 2454 2455 usb_1_ssphy: phy@88e9200 { 2456 reg = <0 0x088e9200 0 0x200>, 2457 <0 0x088e9400 0 0x200>, 2458 <0 0x088e9c00 0 0x400>, 2459 <0 0x088e9600 0 0x200>, 2460 <0 0x088e9800 0 0x200>, 2461 <0 0x088e9a00 0 0x100>; 2462 #phy-cells = <0>; 2463 #clock-cells = <0>; 2464 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2465 clock-names = "pipe0"; 2466 clock-output-names = "usb3_phy_pipe_clk_src"; 2467 }; 2468 }; 2469 2470 usb_2_qmpphy: phy-wrapper@88eb000 { 2471 compatible = "qcom,sm8350-qmp-usb3-uni-phy"; 2472 reg = <0 0x088eb000 0 0x200>; 2473 status = "disabled"; 2474 #address-cells = <2>; 2475 #size-cells = <2>; 2476 ranges; 2477 2478 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2479 <&rpmhcc RPMH_CXO_CLK>, 2480 <&gcc GCC_USB3_SEC_CLKREF_EN>, 2481 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2482 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 2483 2484 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 2485 <&gcc GCC_USB3_PHY_SEC_BCR>; 2486 reset-names = "phy", "common"; 2487 2488 usb_2_ssphy: phy@88ebe00 { 2489 reg = <0 0x088ebe00 0 0x200>, 2490 <0 0x088ec000 0 0x200>, 2491 <0 0x088eb200 0 0x1100>; 2492 #phy-cells = <0>; 2493 #clock-cells = <0>; 2494 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2495 clock-names = "pipe0"; 2496 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2497 }; 2498 }; 2499 2500 dc_noc: interconnect@90c0000 { 2501 compatible = "qcom,sm8350-dc-noc"; 2502 reg = <0 0x090c0000 0 0x4200>; 2503 #interconnect-cells = <1>; 2504 qcom,bcm-voters = <&apps_bcm_voter>; 2505 }; 2506 2507 gem_noc: interconnect@9100000 { 2508 compatible = "qcom,sm8350-gem-noc"; 2509 reg = <0 0x09100000 0 0xb4000>; 2510 #interconnect-cells = <1>; 2511 qcom,bcm-voters = <&apps_bcm_voter>; 2512 }; 2513 2514 system-cache-controller@9200000 { 2515 compatible = "qcom,sm8350-llcc"; 2516 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; 2517 reg-names = "llcc_base", "llcc_broadcast_base"; 2518 }; 2519 2520 usb_1: usb@a6f8800 { 2521 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2522 reg = <0 0x0a6f8800 0 0x400>; 2523 status = "disabled"; 2524 #address-cells = <2>; 2525 #size-cells = <2>; 2526 ranges; 2527 2528 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2529 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2530 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2531 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2532 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 2533 clock-names = "cfg_noc", 2534 "core", 2535 "iface", 2536 "sleep", 2537 "mock_utmi"; 2538 2539 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2540 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2541 assigned-clock-rates = <19200000>, <200000000>; 2542 2543 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2544 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 2545 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2546 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 2547 interrupt-names = "hs_phy_irq", 2548 "ss_phy_irq", 2549 "dm_hs_phy_irq", 2550 "dp_hs_phy_irq"; 2551 2552 power-domains = <&gcc USB30_PRIM_GDSC>; 2553 2554 resets = <&gcc GCC_USB30_PRIM_BCR>; 2555 2556 usb_1_dwc3: usb@a600000 { 2557 compatible = "snps,dwc3"; 2558 reg = <0 0x0a600000 0 0xcd00>; 2559 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2560 iommus = <&apps_smmu 0x0 0x0>; 2561 snps,dis_u2_susphy_quirk; 2562 snps,dis_enblslpm_quirk; 2563 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2564 phy-names = "usb2-phy", "usb3-phy"; 2565 }; 2566 }; 2567 2568 usb_2: usb@a8f8800 { 2569 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2570 reg = <0 0x0a8f8800 0 0x400>; 2571 status = "disabled"; 2572 #address-cells = <2>; 2573 #size-cells = <2>; 2574 ranges; 2575 2576 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2577 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2578 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2579 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2580 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2581 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2582 clock-names = "cfg_noc", 2583 "core", 2584 "iface", 2585 "sleep", 2586 "mock_utmi", 2587 "xo"; 2588 2589 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2590 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2591 assigned-clock-rates = <19200000>, <200000000>; 2592 2593 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2594 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, 2595 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 2596 <&pdc 12 IRQ_TYPE_EDGE_BOTH>; 2597 interrupt-names = "hs_phy_irq", 2598 "ss_phy_irq", 2599 "dm_hs_phy_irq", 2600 "dp_hs_phy_irq"; 2601 2602 power-domains = <&gcc USB30_SEC_GDSC>; 2603 2604 resets = <&gcc GCC_USB30_SEC_BCR>; 2605 2606 usb_2_dwc3: usb@a800000 { 2607 compatible = "snps,dwc3"; 2608 reg = <0 0x0a800000 0 0xcd00>; 2609 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2610 iommus = <&apps_smmu 0x20 0x0>; 2611 snps,dis_u2_susphy_quirk; 2612 snps,dis_enblslpm_quirk; 2613 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 2614 phy-names = "usb2-phy", "usb3-phy"; 2615 }; 2616 }; 2617 2618 dispcc: clock-controller@af00000 { 2619 compatible = "qcom,sm8350-dispcc"; 2620 reg = <0 0x0af00000 0 0x10000>; 2621 clocks = <&rpmhcc RPMH_CXO_CLK>, 2622 <0>, 2623 <0>, 2624 <0>, 2625 <0>, 2626 <0>, 2627 <0>; 2628 clock-names = "bi_tcxo", 2629 "dsi0_phy_pll_out_byteclk", 2630 "dsi0_phy_pll_out_dsiclk", 2631 "dsi1_phy_pll_out_byteclk", 2632 "dsi1_phy_pll_out_dsiclk", 2633 "dp_phy_pll_link_clk", 2634 "dp_phy_pll_vco_div_clk"; 2635 #clock-cells = <1>; 2636 #reset-cells = <1>; 2637 #power-domain-cells = <1>; 2638 2639 power-domains = <&rpmhpd SM8350_MMCX>; 2640 power-domain-names = "mmcx"; 2641 }; 2642 2643 adsp: remoteproc@17300000 { 2644 compatible = "qcom,sm8350-adsp-pas"; 2645 reg = <0 0x17300000 0 0x100>; 2646 2647 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 2648 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2649 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2650 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2651 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2652 interrupt-names = "wdog", "fatal", "ready", 2653 "handover", "stop-ack"; 2654 2655 clocks = <&rpmhcc RPMH_CXO_CLK>; 2656 clock-names = "xo"; 2657 2658 power-domains = <&rpmhpd SM8350_LCX>, 2659 <&rpmhpd SM8350_LMX>; 2660 power-domain-names = "lcx", "lmx"; 2661 2662 memory-region = <&pil_adsp_mem>; 2663 2664 qcom,qmp = <&aoss_qmp>; 2665 2666 qcom,smem-states = <&smp2p_adsp_out 0>; 2667 qcom,smem-state-names = "stop"; 2668 2669 status = "disabled"; 2670 2671 glink-edge { 2672 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2673 IPCC_MPROC_SIGNAL_GLINK_QMP 2674 IRQ_TYPE_EDGE_RISING>; 2675 mboxes = <&ipcc IPCC_CLIENT_LPASS 2676 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2677 2678 label = "lpass"; 2679 qcom,remote-pid = <2>; 2680 2681 fastrpc { 2682 compatible = "qcom,fastrpc"; 2683 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2684 label = "adsp"; 2685 qcom,non-secure-domain; 2686 #address-cells = <1>; 2687 #size-cells = <0>; 2688 2689 compute-cb@3 { 2690 compatible = "qcom,fastrpc-compute-cb"; 2691 reg = <3>; 2692 iommus = <&apps_smmu 0x1803 0x0>; 2693 }; 2694 2695 compute-cb@4 { 2696 compatible = "qcom,fastrpc-compute-cb"; 2697 reg = <4>; 2698 iommus = <&apps_smmu 0x1804 0x0>; 2699 }; 2700 2701 compute-cb@5 { 2702 compatible = "qcom,fastrpc-compute-cb"; 2703 reg = <5>; 2704 iommus = <&apps_smmu 0x1805 0x0>; 2705 }; 2706 }; 2707 }; 2708 }; 2709 }; 2710 2711 thermal_zones: thermal-zones { 2712 cpu0-thermal { 2713 polling-delay-passive = <250>; 2714 polling-delay = <1000>; 2715 2716 thermal-sensors = <&tsens0 1>; 2717 2718 trips { 2719 cpu0_alert0: trip-point0 { 2720 temperature = <90000>; 2721 hysteresis = <2000>; 2722 type = "passive"; 2723 }; 2724 2725 cpu0_alert1: trip-point1 { 2726 temperature = <95000>; 2727 hysteresis = <2000>; 2728 type = "passive"; 2729 }; 2730 2731 cpu0_crit: cpu_crit { 2732 temperature = <110000>; 2733 hysteresis = <1000>; 2734 type = "critical"; 2735 }; 2736 }; 2737 2738 cooling-maps { 2739 map0 { 2740 trip = <&cpu0_alert0>; 2741 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2742 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2743 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2744 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2745 }; 2746 map1 { 2747 trip = <&cpu0_alert1>; 2748 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2749 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2750 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2751 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2752 }; 2753 }; 2754 }; 2755 2756 cpu1-thermal { 2757 polling-delay-passive = <250>; 2758 polling-delay = <1000>; 2759 2760 thermal-sensors = <&tsens0 2>; 2761 2762 trips { 2763 cpu1_alert0: trip-point0 { 2764 temperature = <90000>; 2765 hysteresis = <2000>; 2766 type = "passive"; 2767 }; 2768 2769 cpu1_alert1: trip-point1 { 2770 temperature = <95000>; 2771 hysteresis = <2000>; 2772 type = "passive"; 2773 }; 2774 2775 cpu1_crit: cpu_crit { 2776 temperature = <110000>; 2777 hysteresis = <1000>; 2778 type = "critical"; 2779 }; 2780 }; 2781 2782 cooling-maps { 2783 map0 { 2784 trip = <&cpu1_alert0>; 2785 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2786 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2787 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2788 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2789 }; 2790 map1 { 2791 trip = <&cpu1_alert1>; 2792 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2793 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2794 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2795 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2796 }; 2797 }; 2798 }; 2799 2800 cpu2-thermal { 2801 polling-delay-passive = <250>; 2802 polling-delay = <1000>; 2803 2804 thermal-sensors = <&tsens0 3>; 2805 2806 trips { 2807 cpu2_alert0: trip-point0 { 2808 temperature = <90000>; 2809 hysteresis = <2000>; 2810 type = "passive"; 2811 }; 2812 2813 cpu2_alert1: trip-point1 { 2814 temperature = <95000>; 2815 hysteresis = <2000>; 2816 type = "passive"; 2817 }; 2818 2819 cpu2_crit: cpu_crit { 2820 temperature = <110000>; 2821 hysteresis = <1000>; 2822 type = "critical"; 2823 }; 2824 }; 2825 2826 cooling-maps { 2827 map0 { 2828 trip = <&cpu2_alert0>; 2829 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2830 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2831 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2832 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2833 }; 2834 map1 { 2835 trip = <&cpu2_alert1>; 2836 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2837 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2838 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2839 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2840 }; 2841 }; 2842 }; 2843 2844 cpu3-thermal { 2845 polling-delay-passive = <250>; 2846 polling-delay = <1000>; 2847 2848 thermal-sensors = <&tsens0 4>; 2849 2850 trips { 2851 cpu3_alert0: trip-point0 { 2852 temperature = <90000>; 2853 hysteresis = <2000>; 2854 type = "passive"; 2855 }; 2856 2857 cpu3_alert1: trip-point1 { 2858 temperature = <95000>; 2859 hysteresis = <2000>; 2860 type = "passive"; 2861 }; 2862 2863 cpu3_crit: cpu_crit { 2864 temperature = <110000>; 2865 hysteresis = <1000>; 2866 type = "critical"; 2867 }; 2868 }; 2869 2870 cooling-maps { 2871 map0 { 2872 trip = <&cpu3_alert0>; 2873 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2874 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2875 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2876 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2877 }; 2878 map1 { 2879 trip = <&cpu3_alert1>; 2880 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2881 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2882 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2883 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2884 }; 2885 }; 2886 }; 2887 2888 cpu4-top-thermal { 2889 polling-delay-passive = <250>; 2890 polling-delay = <1000>; 2891 2892 thermal-sensors = <&tsens0 7>; 2893 2894 trips { 2895 cpu4_top_alert0: trip-point0 { 2896 temperature = <90000>; 2897 hysteresis = <2000>; 2898 type = "passive"; 2899 }; 2900 2901 cpu4_top_alert1: trip-point1 { 2902 temperature = <95000>; 2903 hysteresis = <2000>; 2904 type = "passive"; 2905 }; 2906 2907 cpu4_top_crit: cpu_crit { 2908 temperature = <110000>; 2909 hysteresis = <1000>; 2910 type = "critical"; 2911 }; 2912 }; 2913 2914 cooling-maps { 2915 map0 { 2916 trip = <&cpu4_top_alert0>; 2917 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2918 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2919 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2920 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2921 }; 2922 map1 { 2923 trip = <&cpu4_top_alert1>; 2924 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2925 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2926 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2927 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2928 }; 2929 }; 2930 }; 2931 2932 cpu5-top-thermal { 2933 polling-delay-passive = <250>; 2934 polling-delay = <1000>; 2935 2936 thermal-sensors = <&tsens0 8>; 2937 2938 trips { 2939 cpu5_top_alert0: trip-point0 { 2940 temperature = <90000>; 2941 hysteresis = <2000>; 2942 type = "passive"; 2943 }; 2944 2945 cpu5_top_alert1: trip-point1 { 2946 temperature = <95000>; 2947 hysteresis = <2000>; 2948 type = "passive"; 2949 }; 2950 2951 cpu5_top_crit: cpu_crit { 2952 temperature = <110000>; 2953 hysteresis = <1000>; 2954 type = "critical"; 2955 }; 2956 }; 2957 2958 cooling-maps { 2959 map0 { 2960 trip = <&cpu5_top_alert0>; 2961 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2962 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2963 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2964 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2965 }; 2966 map1 { 2967 trip = <&cpu5_top_alert1>; 2968 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2969 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2970 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2971 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2972 }; 2973 }; 2974 }; 2975 2976 cpu6-top-thermal { 2977 polling-delay-passive = <250>; 2978 polling-delay = <1000>; 2979 2980 thermal-sensors = <&tsens0 9>; 2981 2982 trips { 2983 cpu6_top_alert0: trip-point0 { 2984 temperature = <90000>; 2985 hysteresis = <2000>; 2986 type = "passive"; 2987 }; 2988 2989 cpu6_top_alert1: trip-point1 { 2990 temperature = <95000>; 2991 hysteresis = <2000>; 2992 type = "passive"; 2993 }; 2994 2995 cpu6_top_crit: cpu_crit { 2996 temperature = <110000>; 2997 hysteresis = <1000>; 2998 type = "critical"; 2999 }; 3000 }; 3001 3002 cooling-maps { 3003 map0 { 3004 trip = <&cpu6_top_alert0>; 3005 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3006 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3007 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3008 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3009 }; 3010 map1 { 3011 trip = <&cpu6_top_alert1>; 3012 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3013 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3014 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3015 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3016 }; 3017 }; 3018 }; 3019 3020 cpu7-top-thermal { 3021 polling-delay-passive = <250>; 3022 polling-delay = <1000>; 3023 3024 thermal-sensors = <&tsens0 10>; 3025 3026 trips { 3027 cpu7_top_alert0: trip-point0 { 3028 temperature = <90000>; 3029 hysteresis = <2000>; 3030 type = "passive"; 3031 }; 3032 3033 cpu7_top_alert1: trip-point1 { 3034 temperature = <95000>; 3035 hysteresis = <2000>; 3036 type = "passive"; 3037 }; 3038 3039 cpu7_top_crit: cpu_crit { 3040 temperature = <110000>; 3041 hysteresis = <1000>; 3042 type = "critical"; 3043 }; 3044 }; 3045 3046 cooling-maps { 3047 map0 { 3048 trip = <&cpu7_top_alert0>; 3049 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3050 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3051 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3052 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3053 }; 3054 map1 { 3055 trip = <&cpu7_top_alert1>; 3056 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3057 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3058 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3059 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3060 }; 3061 }; 3062 }; 3063 3064 cpu4-bottom-thermal { 3065 polling-delay-passive = <250>; 3066 polling-delay = <1000>; 3067 3068 thermal-sensors = <&tsens0 11>; 3069 3070 trips { 3071 cpu4_bottom_alert0: trip-point0 { 3072 temperature = <90000>; 3073 hysteresis = <2000>; 3074 type = "passive"; 3075 }; 3076 3077 cpu4_bottom_alert1: trip-point1 { 3078 temperature = <95000>; 3079 hysteresis = <2000>; 3080 type = "passive"; 3081 }; 3082 3083 cpu4_bottom_crit: cpu_crit { 3084 temperature = <110000>; 3085 hysteresis = <1000>; 3086 type = "critical"; 3087 }; 3088 }; 3089 3090 cooling-maps { 3091 map0 { 3092 trip = <&cpu4_bottom_alert0>; 3093 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3094 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3095 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3096 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3097 }; 3098 map1 { 3099 trip = <&cpu4_bottom_alert1>; 3100 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3101 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3102 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3103 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3104 }; 3105 }; 3106 }; 3107 3108 cpu5-bottom-thermal { 3109 polling-delay-passive = <250>; 3110 polling-delay = <1000>; 3111 3112 thermal-sensors = <&tsens0 12>; 3113 3114 trips { 3115 cpu5_bottom_alert0: trip-point0 { 3116 temperature = <90000>; 3117 hysteresis = <2000>; 3118 type = "passive"; 3119 }; 3120 3121 cpu5_bottom_alert1: trip-point1 { 3122 temperature = <95000>; 3123 hysteresis = <2000>; 3124 type = "passive"; 3125 }; 3126 3127 cpu5_bottom_crit: cpu_crit { 3128 temperature = <110000>; 3129 hysteresis = <1000>; 3130 type = "critical"; 3131 }; 3132 }; 3133 3134 cooling-maps { 3135 map0 { 3136 trip = <&cpu5_bottom_alert0>; 3137 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3138 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3139 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3140 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3141 }; 3142 map1 { 3143 trip = <&cpu5_bottom_alert1>; 3144 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3145 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3146 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3147 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3148 }; 3149 }; 3150 }; 3151 3152 cpu6-bottom-thermal { 3153 polling-delay-passive = <250>; 3154 polling-delay = <1000>; 3155 3156 thermal-sensors = <&tsens0 13>; 3157 3158 trips { 3159 cpu6_bottom_alert0: trip-point0 { 3160 temperature = <90000>; 3161 hysteresis = <2000>; 3162 type = "passive"; 3163 }; 3164 3165 cpu6_bottom_alert1: trip-point1 { 3166 temperature = <95000>; 3167 hysteresis = <2000>; 3168 type = "passive"; 3169 }; 3170 3171 cpu6_bottom_crit: cpu_crit { 3172 temperature = <110000>; 3173 hysteresis = <1000>; 3174 type = "critical"; 3175 }; 3176 }; 3177 3178 cooling-maps { 3179 map0 { 3180 trip = <&cpu6_bottom_alert0>; 3181 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3182 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3183 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3184 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3185 }; 3186 map1 { 3187 trip = <&cpu6_bottom_alert1>; 3188 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3189 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3190 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3191 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3192 }; 3193 }; 3194 }; 3195 3196 cpu7-bottom-thermal { 3197 polling-delay-passive = <250>; 3198 polling-delay = <1000>; 3199 3200 thermal-sensors = <&tsens0 14>; 3201 3202 trips { 3203 cpu7_bottom_alert0: trip-point0 { 3204 temperature = <90000>; 3205 hysteresis = <2000>; 3206 type = "passive"; 3207 }; 3208 3209 cpu7_bottom_alert1: trip-point1 { 3210 temperature = <95000>; 3211 hysteresis = <2000>; 3212 type = "passive"; 3213 }; 3214 3215 cpu7_bottom_crit: cpu_crit { 3216 temperature = <110000>; 3217 hysteresis = <1000>; 3218 type = "critical"; 3219 }; 3220 }; 3221 3222 cooling-maps { 3223 map0 { 3224 trip = <&cpu7_bottom_alert0>; 3225 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3226 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3227 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3228 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3229 }; 3230 map1 { 3231 trip = <&cpu7_bottom_alert1>; 3232 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3233 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3234 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3235 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3236 }; 3237 }; 3238 }; 3239 3240 aoss0-thermal { 3241 polling-delay-passive = <250>; 3242 polling-delay = <1000>; 3243 3244 thermal-sensors = <&tsens0 0>; 3245 3246 trips { 3247 aoss0_alert0: trip-point0 { 3248 temperature = <90000>; 3249 hysteresis = <2000>; 3250 type = "hot"; 3251 }; 3252 }; 3253 }; 3254 3255 cluster0-thermal { 3256 polling-delay-passive = <250>; 3257 polling-delay = <1000>; 3258 3259 thermal-sensors = <&tsens0 5>; 3260 3261 trips { 3262 cluster0_alert0: trip-point0 { 3263 temperature = <90000>; 3264 hysteresis = <2000>; 3265 type = "hot"; 3266 }; 3267 cluster0_crit: cluster0_crit { 3268 temperature = <110000>; 3269 hysteresis = <2000>; 3270 type = "critical"; 3271 }; 3272 }; 3273 }; 3274 3275 cluster1-thermal { 3276 polling-delay-passive = <250>; 3277 polling-delay = <1000>; 3278 3279 thermal-sensors = <&tsens0 6>; 3280 3281 trips { 3282 cluster1_alert0: trip-point0 { 3283 temperature = <90000>; 3284 hysteresis = <2000>; 3285 type = "hot"; 3286 }; 3287 cluster1_crit: cluster1_crit { 3288 temperature = <110000>; 3289 hysteresis = <2000>; 3290 type = "critical"; 3291 }; 3292 }; 3293 }; 3294 3295 aoss1-thermal { 3296 polling-delay-passive = <250>; 3297 polling-delay = <1000>; 3298 3299 thermal-sensors = <&tsens1 0>; 3300 3301 trips { 3302 aoss1_alert0: trip-point0 { 3303 temperature = <90000>; 3304 hysteresis = <2000>; 3305 type = "hot"; 3306 }; 3307 }; 3308 }; 3309 3310 gpu-top-thermal { 3311 polling-delay-passive = <250>; 3312 polling-delay = <1000>; 3313 3314 thermal-sensors = <&tsens1 1>; 3315 3316 trips { 3317 gpu1_alert0: trip-point0 { 3318 temperature = <90000>; 3319 hysteresis = <1000>; 3320 type = "hot"; 3321 }; 3322 }; 3323 }; 3324 3325 gpu-bottom-thermal { 3326 polling-delay-passive = <250>; 3327 polling-delay = <1000>; 3328 3329 thermal-sensors = <&tsens1 2>; 3330 3331 trips { 3332 gpu2_alert0: trip-point0 { 3333 temperature = <90000>; 3334 hysteresis = <1000>; 3335 type = "hot"; 3336 }; 3337 }; 3338 }; 3339 3340 nspss1-thermal { 3341 polling-delay-passive = <250>; 3342 polling-delay = <1000>; 3343 3344 thermal-sensors = <&tsens1 3>; 3345 3346 trips { 3347 nspss1_alert0: trip-point0 { 3348 temperature = <90000>; 3349 hysteresis = <1000>; 3350 type = "hot"; 3351 }; 3352 }; 3353 }; 3354 3355 nspss2-thermal { 3356 polling-delay-passive = <250>; 3357 polling-delay = <1000>; 3358 3359 thermal-sensors = <&tsens1 4>; 3360 3361 trips { 3362 nspss2_alert0: trip-point0 { 3363 temperature = <90000>; 3364 hysteresis = <1000>; 3365 type = "hot"; 3366 }; 3367 }; 3368 }; 3369 3370 nspss3-thermal { 3371 polling-delay-passive = <250>; 3372 polling-delay = <1000>; 3373 3374 thermal-sensors = <&tsens1 5>; 3375 3376 trips { 3377 nspss3_alert0: trip-point0 { 3378 temperature = <90000>; 3379 hysteresis = <1000>; 3380 type = "hot"; 3381 }; 3382 }; 3383 }; 3384 3385 video-thermal { 3386 polling-delay-passive = <250>; 3387 polling-delay = <1000>; 3388 3389 thermal-sensors = <&tsens1 6>; 3390 3391 trips { 3392 video_alert0: trip-point0 { 3393 temperature = <90000>; 3394 hysteresis = <2000>; 3395 type = "hot"; 3396 }; 3397 }; 3398 }; 3399 3400 mem-thermal { 3401 polling-delay-passive = <250>; 3402 polling-delay = <1000>; 3403 3404 thermal-sensors = <&tsens1 7>; 3405 3406 trips { 3407 mem_alert0: trip-point0 { 3408 temperature = <90000>; 3409 hysteresis = <2000>; 3410 type = "hot"; 3411 }; 3412 }; 3413 }; 3414 3415 modem1-top-thermal { 3416 polling-delay-passive = <250>; 3417 polling-delay = <1000>; 3418 3419 thermal-sensors = <&tsens1 8>; 3420 3421 trips { 3422 modem1_alert0: trip-point0 { 3423 temperature = <90000>; 3424 hysteresis = <2000>; 3425 type = "hot"; 3426 }; 3427 }; 3428 }; 3429 3430 modem2-top-thermal { 3431 polling-delay-passive = <250>; 3432 polling-delay = <1000>; 3433 3434 thermal-sensors = <&tsens1 9>; 3435 3436 trips { 3437 modem2_alert0: trip-point0 { 3438 temperature = <90000>; 3439 hysteresis = <2000>; 3440 type = "hot"; 3441 }; 3442 }; 3443 }; 3444 3445 modem3-top-thermal { 3446 polling-delay-passive = <250>; 3447 polling-delay = <1000>; 3448 3449 thermal-sensors = <&tsens1 10>; 3450 3451 trips { 3452 modem3_alert0: trip-point0 { 3453 temperature = <90000>; 3454 hysteresis = <2000>; 3455 type = "hot"; 3456 }; 3457 }; 3458 }; 3459 3460 modem4-top-thermal { 3461 polling-delay-passive = <250>; 3462 polling-delay = <1000>; 3463 3464 thermal-sensors = <&tsens1 11>; 3465 3466 trips { 3467 modem4_alert0: trip-point0 { 3468 temperature = <90000>; 3469 hysteresis = <2000>; 3470 type = "hot"; 3471 }; 3472 }; 3473 }; 3474 3475 camera-top-thermal { 3476 polling-delay-passive = <250>; 3477 polling-delay = <1000>; 3478 3479 thermal-sensors = <&tsens1 12>; 3480 3481 trips { 3482 camera1_alert0: trip-point0 { 3483 temperature = <90000>; 3484 hysteresis = <2000>; 3485 type = "hot"; 3486 }; 3487 }; 3488 }; 3489 3490 cam-bottom-thermal { 3491 polling-delay-passive = <250>; 3492 polling-delay = <1000>; 3493 3494 thermal-sensors = <&tsens1 13>; 3495 3496 trips { 3497 camera2_alert0: trip-point0 { 3498 temperature = <90000>; 3499 hysteresis = <2000>; 3500 type = "hot"; 3501 }; 3502 }; 3503 }; 3504 }; 3505 3506 timer { 3507 compatible = "arm,armv8-timer"; 3508 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3509 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3510 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3511 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 3512 }; 3513}; 3514