1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Linaro Limited 4 */ 5 6#include <dt-bindings/interconnect/qcom,sm8350.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/qcom,dispcc-sm8350.h> 9#include <dt-bindings/clock/qcom,gcc-sm8350.h> 10#include <dt-bindings/clock/qcom,gpucc-sm8350.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/firmware/qcom,scm.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interconnect/qcom,sm8350.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/phy/phy-qcom-qmp.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/power/qcom,rpmhpd.h> 20#include <dt-bindings/soc/qcom,apr.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/sound/qcom,q6afe.h> 23#include <dt-bindings/thermal/thermal.h> 24#include <dt-bindings/interconnect/qcom,sm8350.h> 25 26/ { 27 interrupt-parent = <&intc>; 28 29 #address-cells = <2>; 30 #size-cells = <2>; 31 32 chosen { }; 33 34 clocks { 35 xo_board: xo-board { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <38400000>; 39 clock-output-names = "xo_board"; 40 }; 41 42 sleep_clk: sleep-clk { 43 compatible = "fixed-clock"; 44 clock-frequency = <32000>; 45 #clock-cells = <0>; 46 }; 47 }; 48 49 cpus { 50 #address-cells = <2>; 51 #size-cells = <0>; 52 53 CPU0: cpu@0 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a55"; 56 reg = <0x0 0x0>; 57 clocks = <&cpufreq_hw 0>; 58 enable-method = "psci"; 59 next-level-cache = <&L2_0>; 60 qcom,freq-domain = <&cpufreq_hw 0>; 61 power-domains = <&CPU_PD0>; 62 power-domain-names = "psci"; 63 #cooling-cells = <2>; 64 L2_0: l2-cache { 65 compatible = "cache"; 66 cache-level = <2>; 67 cache-unified; 68 next-level-cache = <&L3_0>; 69 L3_0: l3-cache { 70 compatible = "cache"; 71 cache-level = <3>; 72 cache-unified; 73 }; 74 }; 75 }; 76 77 CPU1: cpu@100 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a55"; 80 reg = <0x0 0x100>; 81 clocks = <&cpufreq_hw 0>; 82 enable-method = "psci"; 83 next-level-cache = <&L2_100>; 84 qcom,freq-domain = <&cpufreq_hw 0>; 85 power-domains = <&CPU_PD1>; 86 power-domain-names = "psci"; 87 #cooling-cells = <2>; 88 L2_100: l2-cache { 89 compatible = "cache"; 90 cache-level = <2>; 91 cache-unified; 92 next-level-cache = <&L3_0>; 93 }; 94 }; 95 96 CPU2: cpu@200 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a55"; 99 reg = <0x0 0x200>; 100 clocks = <&cpufreq_hw 0>; 101 enable-method = "psci"; 102 next-level-cache = <&L2_200>; 103 qcom,freq-domain = <&cpufreq_hw 0>; 104 power-domains = <&CPU_PD2>; 105 power-domain-names = "psci"; 106 #cooling-cells = <2>; 107 L2_200: l2-cache { 108 compatible = "cache"; 109 cache-level = <2>; 110 cache-unified; 111 next-level-cache = <&L3_0>; 112 }; 113 }; 114 115 CPU3: cpu@300 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a55"; 118 reg = <0x0 0x300>; 119 clocks = <&cpufreq_hw 0>; 120 enable-method = "psci"; 121 next-level-cache = <&L2_300>; 122 qcom,freq-domain = <&cpufreq_hw 0>; 123 power-domains = <&CPU_PD3>; 124 power-domain-names = "psci"; 125 #cooling-cells = <2>; 126 L2_300: l2-cache { 127 compatible = "cache"; 128 cache-level = <2>; 129 cache-unified; 130 next-level-cache = <&L3_0>; 131 }; 132 }; 133 134 CPU4: cpu@400 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-a78"; 137 reg = <0x0 0x400>; 138 clocks = <&cpufreq_hw 1>; 139 enable-method = "psci"; 140 next-level-cache = <&L2_400>; 141 qcom,freq-domain = <&cpufreq_hw 1>; 142 power-domains = <&CPU_PD4>; 143 power-domain-names = "psci"; 144 #cooling-cells = <2>; 145 L2_400: l2-cache { 146 compatible = "cache"; 147 cache-level = <2>; 148 cache-unified; 149 next-level-cache = <&L3_0>; 150 }; 151 }; 152 153 CPU5: cpu@500 { 154 device_type = "cpu"; 155 compatible = "arm,cortex-a78"; 156 reg = <0x0 0x500>; 157 clocks = <&cpufreq_hw 1>; 158 enable-method = "psci"; 159 next-level-cache = <&L2_500>; 160 qcom,freq-domain = <&cpufreq_hw 1>; 161 power-domains = <&CPU_PD5>; 162 power-domain-names = "psci"; 163 #cooling-cells = <2>; 164 L2_500: l2-cache { 165 compatible = "cache"; 166 cache-level = <2>; 167 cache-unified; 168 next-level-cache = <&L3_0>; 169 }; 170 }; 171 172 CPU6: cpu@600 { 173 device_type = "cpu"; 174 compatible = "arm,cortex-a78"; 175 reg = <0x0 0x600>; 176 clocks = <&cpufreq_hw 1>; 177 enable-method = "psci"; 178 next-level-cache = <&L2_600>; 179 qcom,freq-domain = <&cpufreq_hw 1>; 180 power-domains = <&CPU_PD6>; 181 power-domain-names = "psci"; 182 #cooling-cells = <2>; 183 L2_600: l2-cache { 184 compatible = "cache"; 185 cache-level = <2>; 186 cache-unified; 187 next-level-cache = <&L3_0>; 188 }; 189 }; 190 191 CPU7: cpu@700 { 192 device_type = "cpu"; 193 compatible = "arm,cortex-x1"; 194 reg = <0x0 0x700>; 195 clocks = <&cpufreq_hw 2>; 196 enable-method = "psci"; 197 next-level-cache = <&L2_700>; 198 qcom,freq-domain = <&cpufreq_hw 2>; 199 power-domains = <&CPU_PD7>; 200 power-domain-names = "psci"; 201 #cooling-cells = <2>; 202 L2_700: l2-cache { 203 compatible = "cache"; 204 cache-level = <2>; 205 cache-unified; 206 next-level-cache = <&L3_0>; 207 }; 208 }; 209 210 cpu-map { 211 cluster0 { 212 core0 { 213 cpu = <&CPU0>; 214 }; 215 216 core1 { 217 cpu = <&CPU1>; 218 }; 219 220 core2 { 221 cpu = <&CPU2>; 222 }; 223 224 core3 { 225 cpu = <&CPU3>; 226 }; 227 228 core4 { 229 cpu = <&CPU4>; 230 }; 231 232 core5 { 233 cpu = <&CPU5>; 234 }; 235 236 core6 { 237 cpu = <&CPU6>; 238 }; 239 240 core7 { 241 cpu = <&CPU7>; 242 }; 243 }; 244 }; 245 246 idle-states { 247 entry-method = "psci"; 248 249 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 250 compatible = "arm,idle-state"; 251 idle-state-name = "silver-rail-power-collapse"; 252 arm,psci-suspend-param = <0x40000004>; 253 entry-latency-us = <360>; 254 exit-latency-us = <531>; 255 min-residency-us = <3934>; 256 local-timer-stop; 257 }; 258 259 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 260 compatible = "arm,idle-state"; 261 idle-state-name = "gold-rail-power-collapse"; 262 arm,psci-suspend-param = <0x40000004>; 263 entry-latency-us = <702>; 264 exit-latency-us = <1061>; 265 min-residency-us = <4488>; 266 local-timer-stop; 267 }; 268 }; 269 270 domain-idle-states { 271 CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { 272 compatible = "domain-idle-state"; 273 arm,psci-suspend-param = <0x41000044>; 274 entry-latency-us = <2752>; 275 exit-latency-us = <3048>; 276 min-residency-us = <6118>; 277 }; 278 279 CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 { 280 compatible = "domain-idle-state"; 281 arm,psci-suspend-param = <0x4100c344>; 282 entry-latency-us = <3263>; 283 exit-latency-us = <6562>; 284 min-residency-us = <9987>; 285 }; 286 }; 287 }; 288 289 firmware { 290 scm: scm { 291 compatible = "qcom,scm-sm8350", "qcom,scm"; 292 qcom,dload-mode = <&tcsr 0x13000>; 293 #reset-cells = <1>; 294 }; 295 }; 296 297 memory@80000000 { 298 device_type = "memory"; 299 /* We expect the bootloader to fill in the size */ 300 reg = <0x0 0x80000000 0x0 0x0>; 301 }; 302 303 pmu { 304 compatible = "arm,armv8-pmuv3"; 305 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 306 }; 307 308 psci { 309 compatible = "arm,psci-1.0"; 310 method = "smc"; 311 312 CPU_PD0: power-domain-cpu0 { 313 #power-domain-cells = <0>; 314 power-domains = <&CLUSTER_PD>; 315 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 316 }; 317 318 CPU_PD1: power-domain-cpu1 { 319 #power-domain-cells = <0>; 320 power-domains = <&CLUSTER_PD>; 321 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 322 }; 323 324 CPU_PD2: power-domain-cpu2 { 325 #power-domain-cells = <0>; 326 power-domains = <&CLUSTER_PD>; 327 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 328 }; 329 330 CPU_PD3: power-domain-cpu3 { 331 #power-domain-cells = <0>; 332 power-domains = <&CLUSTER_PD>; 333 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 334 }; 335 336 CPU_PD4: power-domain-cpu4 { 337 #power-domain-cells = <0>; 338 power-domains = <&CLUSTER_PD>; 339 domain-idle-states = <&BIG_CPU_SLEEP_0>; 340 }; 341 342 CPU_PD5: power-domain-cpu5 { 343 #power-domain-cells = <0>; 344 power-domains = <&CLUSTER_PD>; 345 domain-idle-states = <&BIG_CPU_SLEEP_0>; 346 }; 347 348 CPU_PD6: power-domain-cpu6 { 349 #power-domain-cells = <0>; 350 power-domains = <&CLUSTER_PD>; 351 domain-idle-states = <&BIG_CPU_SLEEP_0>; 352 }; 353 354 CPU_PD7: power-domain-cpu7 { 355 #power-domain-cells = <0>; 356 power-domains = <&CLUSTER_PD>; 357 domain-idle-states = <&BIG_CPU_SLEEP_0>; 358 }; 359 360 CLUSTER_PD: power-domain-cpu-cluster0 { 361 #power-domain-cells = <0>; 362 domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLEEP>; 363 }; 364 }; 365 366 qup_opp_table_100mhz: opp-table-qup100mhz { 367 compatible = "operating-points-v2"; 368 369 opp-50000000 { 370 opp-hz = /bits/ 64 <50000000>; 371 required-opps = <&rpmhpd_opp_min_svs>; 372 }; 373 374 opp-75000000 { 375 opp-hz = /bits/ 64 <75000000>; 376 required-opps = <&rpmhpd_opp_low_svs>; 377 }; 378 379 opp-100000000 { 380 opp-hz = /bits/ 64 <100000000>; 381 required-opps = <&rpmhpd_opp_svs>; 382 }; 383 }; 384 385 qup_opp_table_120mhz: opp-table-qup120mhz { 386 compatible = "operating-points-v2"; 387 388 opp-50000000 { 389 opp-hz = /bits/ 64 <50000000>; 390 required-opps = <&rpmhpd_opp_min_svs>; 391 }; 392 393 opp-75000000 { 394 opp-hz = /bits/ 64 <75000000>; 395 required-opps = <&rpmhpd_opp_low_svs>; 396 }; 397 398 opp-120000000 { 399 opp-hz = /bits/ 64 <120000000>; 400 required-opps = <&rpmhpd_opp_svs>; 401 }; 402 }; 403 404 reserved_memory: reserved-memory { 405 #address-cells = <2>; 406 #size-cells = <2>; 407 ranges; 408 409 hyp_mem: memory@80000000 { 410 reg = <0x0 0x80000000 0x0 0x600000>; 411 no-map; 412 }; 413 414 xbl_aop_mem: memory@80700000 { 415 no-map; 416 reg = <0x0 0x80700000 0x0 0x160000>; 417 }; 418 419 cmd_db: memory@80860000 { 420 compatible = "qcom,cmd-db"; 421 reg = <0x0 0x80860000 0x0 0x20000>; 422 no-map; 423 }; 424 425 reserved_xbl_uefi_log: memory@80880000 { 426 reg = <0x0 0x80880000 0x0 0x14000>; 427 no-map; 428 }; 429 430 smem@80900000 { 431 compatible = "qcom,smem"; 432 reg = <0x0 0x80900000 0x0 0x200000>; 433 hwlocks = <&tcsr_mutex 3>; 434 no-map; 435 }; 436 437 cpucp_fw_mem: memory@80b00000 { 438 reg = <0x0 0x80b00000 0x0 0x100000>; 439 no-map; 440 }; 441 442 cdsp_secure_heap: memory@80c00000 { 443 reg = <0x0 0x80c00000 0x0 0x4600000>; 444 no-map; 445 }; 446 447 pil_camera_mem: mmeory@85200000 { 448 reg = <0x0 0x85200000 0x0 0x500000>; 449 no-map; 450 }; 451 452 pil_video_mem: memory@85700000 { 453 reg = <0x0 0x85700000 0x0 0x500000>; 454 no-map; 455 }; 456 457 pil_cvp_mem: memory@85c00000 { 458 reg = <0x0 0x85c00000 0x0 0x500000>; 459 no-map; 460 }; 461 462 pil_adsp_mem: memory@86100000 { 463 reg = <0x0 0x86100000 0x0 0x2100000>; 464 no-map; 465 }; 466 467 pil_slpi_mem: memory@88200000 { 468 reg = <0x0 0x88200000 0x0 0x1500000>; 469 no-map; 470 }; 471 472 pil_cdsp_mem: memory@89700000 { 473 reg = <0x0 0x89700000 0x0 0x1e00000>; 474 no-map; 475 }; 476 477 pil_ipa_fw_mem: memory@8b500000 { 478 reg = <0x0 0x8b500000 0x0 0x10000>; 479 no-map; 480 }; 481 482 pil_ipa_gsi_mem: memory@8b510000 { 483 reg = <0x0 0x8b510000 0x0 0xa000>; 484 no-map; 485 }; 486 487 pil_gpu_mem: memory@8b51a000 { 488 reg = <0x0 0x8b51a000 0x0 0x2000>; 489 no-map; 490 }; 491 492 pil_spss_mem: memory@8b600000 { 493 reg = <0x0 0x8b600000 0x0 0x100000>; 494 no-map; 495 }; 496 497 pil_modem_mem: memory@8b800000 { 498 reg = <0x0 0x8b800000 0x0 0x10000000>; 499 no-map; 500 }; 501 502 rmtfs_mem: memory@9b800000 { 503 compatible = "qcom,rmtfs-mem"; 504 reg = <0x0 0x9b800000 0x0 0x280000>; 505 no-map; 506 507 qcom,client-id = <1>; 508 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 509 }; 510 511 hyp_reserved_mem: memory@d0000000 { 512 reg = <0x0 0xd0000000 0x0 0x800000>; 513 no-map; 514 }; 515 516 pil_trustedvm_mem: memory@d0800000 { 517 reg = <0x0 0xd0800000 0x0 0x76f7000>; 518 no-map; 519 }; 520 521 qrtr_shbuf: memory@d7ef7000 { 522 reg = <0x0 0xd7ef7000 0x0 0x9000>; 523 no-map; 524 }; 525 526 chan0_shbuf: memory@d7f00000 { 527 reg = <0x0 0xd7f00000 0x0 0x80000>; 528 no-map; 529 }; 530 531 chan1_shbuf: memory@d7f80000 { 532 reg = <0x0 0xd7f80000 0x0 0x80000>; 533 no-map; 534 }; 535 536 removed_mem: memory@d8800000 { 537 reg = <0x0 0xd8800000 0x0 0x6800000>; 538 no-map; 539 }; 540 }; 541 542 smp2p-adsp { 543 compatible = "qcom,smp2p"; 544 qcom,smem = <443>, <429>; 545 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 546 IPCC_MPROC_SIGNAL_SMP2P 547 IRQ_TYPE_EDGE_RISING>; 548 mboxes = <&ipcc IPCC_CLIENT_LPASS 549 IPCC_MPROC_SIGNAL_SMP2P>; 550 551 qcom,local-pid = <0>; 552 qcom,remote-pid = <2>; 553 554 smp2p_adsp_out: master-kernel { 555 qcom,entry-name = "master-kernel"; 556 #qcom,smem-state-cells = <1>; 557 }; 558 559 smp2p_adsp_in: slave-kernel { 560 qcom,entry-name = "slave-kernel"; 561 interrupt-controller; 562 #interrupt-cells = <2>; 563 }; 564 }; 565 566 smp2p-cdsp { 567 compatible = "qcom,smp2p"; 568 qcom,smem = <94>, <432>; 569 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 570 IPCC_MPROC_SIGNAL_SMP2P 571 IRQ_TYPE_EDGE_RISING>; 572 mboxes = <&ipcc IPCC_CLIENT_CDSP 573 IPCC_MPROC_SIGNAL_SMP2P>; 574 575 qcom,local-pid = <0>; 576 qcom,remote-pid = <5>; 577 578 smp2p_cdsp_out: master-kernel { 579 qcom,entry-name = "master-kernel"; 580 #qcom,smem-state-cells = <1>; 581 }; 582 583 smp2p_cdsp_in: slave-kernel { 584 qcom,entry-name = "slave-kernel"; 585 interrupt-controller; 586 #interrupt-cells = <2>; 587 }; 588 }; 589 590 smp2p-modem { 591 compatible = "qcom,smp2p"; 592 qcom,smem = <435>, <428>; 593 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 594 IPCC_MPROC_SIGNAL_SMP2P 595 IRQ_TYPE_EDGE_RISING>; 596 mboxes = <&ipcc IPCC_CLIENT_MPSS 597 IPCC_MPROC_SIGNAL_SMP2P>; 598 599 qcom,local-pid = <0>; 600 qcom,remote-pid = <1>; 601 602 smp2p_modem_out: master-kernel { 603 qcom,entry-name = "master-kernel"; 604 #qcom,smem-state-cells = <1>; 605 }; 606 607 smp2p_modem_in: slave-kernel { 608 qcom,entry-name = "slave-kernel"; 609 interrupt-controller; 610 #interrupt-cells = <2>; 611 }; 612 613 ipa_smp2p_out: ipa-ap-to-modem { 614 qcom,entry-name = "ipa"; 615 #qcom,smem-state-cells = <1>; 616 }; 617 618 ipa_smp2p_in: ipa-modem-to-ap { 619 qcom,entry-name = "ipa"; 620 interrupt-controller; 621 #interrupt-cells = <2>; 622 }; 623 }; 624 625 smp2p-slpi { 626 compatible = "qcom,smp2p"; 627 qcom,smem = <481>, <430>; 628 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 629 IPCC_MPROC_SIGNAL_SMP2P 630 IRQ_TYPE_EDGE_RISING>; 631 mboxes = <&ipcc IPCC_CLIENT_SLPI 632 IPCC_MPROC_SIGNAL_SMP2P>; 633 634 qcom,local-pid = <0>; 635 qcom,remote-pid = <3>; 636 637 smp2p_slpi_out: master-kernel { 638 qcom,entry-name = "master-kernel"; 639 #qcom,smem-state-cells = <1>; 640 }; 641 642 smp2p_slpi_in: slave-kernel { 643 qcom,entry-name = "slave-kernel"; 644 interrupt-controller; 645 #interrupt-cells = <2>; 646 }; 647 }; 648 649 soc: soc@0 { 650 #address-cells = <2>; 651 #size-cells = <2>; 652 ranges = <0 0 0 0 0x10 0>; 653 dma-ranges = <0 0 0 0 0x10 0>; 654 compatible = "simple-bus"; 655 656 gcc: clock-controller@100000 { 657 compatible = "qcom,gcc-sm8350"; 658 reg = <0x0 0x00100000 0x0 0x1f0000>; 659 #clock-cells = <1>; 660 #reset-cells = <1>; 661 #power-domain-cells = <1>; 662 clock-names = "bi_tcxo", 663 "sleep_clk", 664 "pcie_0_pipe_clk", 665 "pcie_1_pipe_clk", 666 "ufs_card_rx_symbol_0_clk", 667 "ufs_card_rx_symbol_1_clk", 668 "ufs_card_tx_symbol_0_clk", 669 "ufs_phy_rx_symbol_0_clk", 670 "ufs_phy_rx_symbol_1_clk", 671 "ufs_phy_tx_symbol_0_clk", 672 "usb3_phy_wrapper_gcc_usb30_pipe_clk", 673 "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; 674 clocks = <&rpmhcc RPMH_CXO_CLK>, 675 <&sleep_clk>, 676 <&pcie0_phy>, 677 <&pcie1_phy>, 678 <0>, 679 <0>, 680 <0>, 681 <&ufs_mem_phy 0>, 682 <&ufs_mem_phy 1>, 683 <&ufs_mem_phy 2>, 684 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 685 <0>; 686 }; 687 688 ipcc: mailbox@408000 { 689 compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; 690 reg = <0 0x00408000 0 0x1000>; 691 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 692 interrupt-controller; 693 #interrupt-cells = <3>; 694 #mbox-cells = <2>; 695 }; 696 697 gpi_dma2: dma-controller@800000 { 698 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 699 reg = <0 0x00800000 0 0x60000>; 700 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 712 dma-channels = <12>; 713 dma-channel-mask = <0xff>; 714 iommus = <&apps_smmu 0x5f6 0x0>; 715 #dma-cells = <3>; 716 status = "disabled"; 717 }; 718 719 qupv3_id_2: geniqup@8c0000 { 720 compatible = "qcom,geni-se-qup"; 721 reg = <0x0 0x008c0000 0x0 0x6000>; 722 clock-names = "m-ahb", "s-ahb"; 723 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 724 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 725 iommus = <&apps_smmu 0x5e3 0x0>; 726 #address-cells = <2>; 727 #size-cells = <2>; 728 ranges; 729 status = "disabled"; 730 731 i2c14: i2c@880000 { 732 compatible = "qcom,geni-i2c"; 733 reg = <0 0x00880000 0 0x4000>; 734 clock-names = "se"; 735 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 736 pinctrl-names = "default"; 737 pinctrl-0 = <&qup_i2c14_default>; 738 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 739 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 740 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 741 dma-names = "tx", "rx"; 742 #address-cells = <1>; 743 #size-cells = <0>; 744 status = "disabled"; 745 }; 746 747 spi14: spi@880000 { 748 compatible = "qcom,geni-spi"; 749 reg = <0 0x00880000 0 0x4000>; 750 clock-names = "se"; 751 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 752 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 753 power-domains = <&rpmhpd RPMHPD_CX>; 754 operating-points-v2 = <&qup_opp_table_120mhz>; 755 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 756 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 757 dma-names = "tx", "rx"; 758 #address-cells = <1>; 759 #size-cells = <0>; 760 status = "disabled"; 761 }; 762 763 i2c15: i2c@884000 { 764 compatible = "qcom,geni-i2c"; 765 reg = <0 0x00884000 0 0x4000>; 766 clock-names = "se"; 767 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 768 pinctrl-names = "default"; 769 pinctrl-0 = <&qup_i2c15_default>; 770 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 771 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 772 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 773 dma-names = "tx", "rx"; 774 #address-cells = <1>; 775 #size-cells = <0>; 776 status = "disabled"; 777 }; 778 779 spi15: spi@884000 { 780 compatible = "qcom,geni-spi"; 781 reg = <0 0x00884000 0 0x4000>; 782 clock-names = "se"; 783 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 784 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 785 power-domains = <&rpmhpd RPMHPD_CX>; 786 operating-points-v2 = <&qup_opp_table_120mhz>; 787 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 788 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 789 dma-names = "tx", "rx"; 790 #address-cells = <1>; 791 #size-cells = <0>; 792 status = "disabled"; 793 }; 794 795 i2c16: i2c@888000 { 796 compatible = "qcom,geni-i2c"; 797 reg = <0 0x00888000 0 0x4000>; 798 clock-names = "se"; 799 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 800 pinctrl-names = "default"; 801 pinctrl-0 = <&qup_i2c16_default>; 802 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 803 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 804 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 805 dma-names = "tx", "rx"; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 status = "disabled"; 809 }; 810 811 spi16: spi@888000 { 812 compatible = "qcom,geni-spi"; 813 reg = <0 0x00888000 0 0x4000>; 814 clock-names = "se"; 815 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 816 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 817 power-domains = <&rpmhpd RPMHPD_CX>; 818 operating-points-v2 = <&qup_opp_table_100mhz>; 819 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 820 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 821 dma-names = "tx", "rx"; 822 #address-cells = <1>; 823 #size-cells = <0>; 824 status = "disabled"; 825 }; 826 827 i2c17: i2c@88c000 { 828 compatible = "qcom,geni-i2c"; 829 reg = <0 0x0088c000 0 0x4000>; 830 clock-names = "se"; 831 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 832 pinctrl-names = "default"; 833 pinctrl-0 = <&qup_i2c17_default>; 834 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 835 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 836 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 837 dma-names = "tx", "rx"; 838 #address-cells = <1>; 839 #size-cells = <0>; 840 status = "disabled"; 841 }; 842 843 spi17: spi@88c000 { 844 compatible = "qcom,geni-spi"; 845 reg = <0 0x0088c000 0 0x4000>; 846 clock-names = "se"; 847 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 848 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 849 power-domains = <&rpmhpd RPMHPD_CX>; 850 operating-points-v2 = <&qup_opp_table_100mhz>; 851 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 852 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 853 dma-names = "tx", "rx"; 854 #address-cells = <1>; 855 #size-cells = <0>; 856 status = "disabled"; 857 }; 858 859 /* QUP no. 18 seems to be strictly SPI/UART-only */ 860 861 spi18: spi@890000 { 862 compatible = "qcom,geni-spi"; 863 reg = <0 0x00890000 0 0x4000>; 864 clock-names = "se"; 865 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 866 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 867 power-domains = <&rpmhpd RPMHPD_CX>; 868 operating-points-v2 = <&qup_opp_table_100mhz>; 869 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 870 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 871 dma-names = "tx", "rx"; 872 #address-cells = <1>; 873 #size-cells = <0>; 874 status = "disabled"; 875 }; 876 877 uart18: serial@890000 { 878 compatible = "qcom,geni-uart"; 879 reg = <0 0x00890000 0 0x4000>; 880 clock-names = "se"; 881 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 882 pinctrl-names = "default"; 883 pinctrl-0 = <&qup_uart18_default>; 884 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 885 power-domains = <&rpmhpd RPMHPD_CX>; 886 operating-points-v2 = <&qup_opp_table_100mhz>; 887 status = "disabled"; 888 }; 889 890 i2c19: i2c@894000 { 891 compatible = "qcom,geni-i2c"; 892 reg = <0 0x00894000 0 0x4000>; 893 clock-names = "se"; 894 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 895 pinctrl-names = "default"; 896 pinctrl-0 = <&qup_i2c19_default>; 897 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 898 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 899 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 900 dma-names = "tx", "rx"; 901 #address-cells = <1>; 902 #size-cells = <0>; 903 status = "disabled"; 904 }; 905 906 spi19: spi@894000 { 907 compatible = "qcom,geni-spi"; 908 reg = <0 0x00894000 0 0x4000>; 909 clock-names = "se"; 910 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 911 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 912 power-domains = <&rpmhpd RPMHPD_CX>; 913 operating-points-v2 = <&qup_opp_table_100mhz>; 914 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 915 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 916 dma-names = "tx", "rx"; 917 #address-cells = <1>; 918 #size-cells = <0>; 919 status = "disabled"; 920 }; 921 }; 922 923 gpi_dma0: dma-controller@900000 { 924 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 925 reg = <0 0x00900000 0 0x60000>; 926 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 938 dma-channels = <12>; 939 dma-channel-mask = <0x7e>; 940 iommus = <&apps_smmu 0x5b6 0x0>; 941 #dma-cells = <3>; 942 status = "disabled"; 943 }; 944 945 qupv3_id_0: geniqup@9c0000 { 946 compatible = "qcom,geni-se-qup"; 947 reg = <0x0 0x009c0000 0x0 0x6000>; 948 clock-names = "m-ahb", "s-ahb"; 949 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 950 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 951 iommus = <&apps_smmu 0x5a3 0>; 952 #address-cells = <2>; 953 #size-cells = <2>; 954 ranges; 955 status = "disabled"; 956 957 i2c0: i2c@980000 { 958 compatible = "qcom,geni-i2c"; 959 reg = <0 0x00980000 0 0x4000>; 960 clock-names = "se"; 961 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 962 pinctrl-names = "default"; 963 pinctrl-0 = <&qup_i2c0_default>; 964 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 965 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 966 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 967 dma-names = "tx", "rx"; 968 #address-cells = <1>; 969 #size-cells = <0>; 970 status = "disabled"; 971 }; 972 973 spi0: spi@980000 { 974 compatible = "qcom,geni-spi"; 975 reg = <0 0x00980000 0 0x4000>; 976 clock-names = "se"; 977 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 978 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 979 power-domains = <&rpmhpd RPMHPD_CX>; 980 operating-points-v2 = <&qup_opp_table_100mhz>; 981 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 982 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 983 dma-names = "tx", "rx"; 984 #address-cells = <1>; 985 #size-cells = <0>; 986 status = "disabled"; 987 }; 988 989 i2c1: i2c@984000 { 990 compatible = "qcom,geni-i2c"; 991 reg = <0 0x00984000 0 0x4000>; 992 clock-names = "se"; 993 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 994 pinctrl-names = "default"; 995 pinctrl-0 = <&qup_i2c1_default>; 996 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 997 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 998 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 999 dma-names = "tx", "rx"; 1000 #address-cells = <1>; 1001 #size-cells = <0>; 1002 status = "disabled"; 1003 }; 1004 1005 spi1: spi@984000 { 1006 compatible = "qcom,geni-spi"; 1007 reg = <0 0x00984000 0 0x4000>; 1008 clock-names = "se"; 1009 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1010 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1011 power-domains = <&rpmhpd RPMHPD_CX>; 1012 operating-points-v2 = <&qup_opp_table_100mhz>; 1013 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1014 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1015 dma-names = "tx", "rx"; 1016 #address-cells = <1>; 1017 #size-cells = <0>; 1018 status = "disabled"; 1019 }; 1020 1021 i2c2: i2c@988000 { 1022 compatible = "qcom,geni-i2c"; 1023 reg = <0 0x00988000 0 0x4000>; 1024 clock-names = "se"; 1025 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1026 pinctrl-names = "default"; 1027 pinctrl-0 = <&qup_i2c2_default>; 1028 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1029 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1030 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1031 dma-names = "tx", "rx"; 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 status = "disabled"; 1035 }; 1036 1037 spi2: spi@988000 { 1038 compatible = "qcom,geni-spi"; 1039 reg = <0 0x00988000 0 0x4000>; 1040 clock-names = "se"; 1041 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1042 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1043 power-domains = <&rpmhpd RPMHPD_CX>; 1044 operating-points-v2 = <&qup_opp_table_100mhz>; 1045 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1046 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1047 dma-names = "tx", "rx"; 1048 #address-cells = <1>; 1049 #size-cells = <0>; 1050 status = "disabled"; 1051 }; 1052 1053 uart2: serial@98c000 { 1054 compatible = "qcom,geni-debug-uart"; 1055 reg = <0 0x0098c000 0 0x4000>; 1056 clock-names = "se"; 1057 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1058 pinctrl-names = "default"; 1059 pinctrl-0 = <&qup_uart3_default_state>; 1060 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1061 power-domains = <&rpmhpd RPMHPD_CX>; 1062 operating-points-v2 = <&qup_opp_table_100mhz>; 1063 status = "disabled"; 1064 }; 1065 1066 /* QUP no. 3 seems to be strictly SPI-only */ 1067 1068 spi3: spi@98c000 { 1069 compatible = "qcom,geni-spi"; 1070 reg = <0 0x0098c000 0 0x4000>; 1071 clock-names = "se"; 1072 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1073 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1074 power-domains = <&rpmhpd RPMHPD_CX>; 1075 operating-points-v2 = <&qup_opp_table_100mhz>; 1076 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1077 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1078 dma-names = "tx", "rx"; 1079 #address-cells = <1>; 1080 #size-cells = <0>; 1081 status = "disabled"; 1082 }; 1083 1084 i2c4: i2c@990000 { 1085 compatible = "qcom,geni-i2c"; 1086 reg = <0 0x00990000 0 0x4000>; 1087 clock-names = "se"; 1088 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1089 pinctrl-names = "default"; 1090 pinctrl-0 = <&qup_i2c4_default>; 1091 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1092 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1093 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1094 dma-names = "tx", "rx"; 1095 #address-cells = <1>; 1096 #size-cells = <0>; 1097 status = "disabled"; 1098 }; 1099 1100 spi4: spi@990000 { 1101 compatible = "qcom,geni-spi"; 1102 reg = <0 0x00990000 0 0x4000>; 1103 clock-names = "se"; 1104 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1105 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1106 power-domains = <&rpmhpd RPMHPD_CX>; 1107 operating-points-v2 = <&qup_opp_table_100mhz>; 1108 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1109 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1110 dma-names = "tx", "rx"; 1111 #address-cells = <1>; 1112 #size-cells = <0>; 1113 status = "disabled"; 1114 }; 1115 1116 i2c5: i2c@994000 { 1117 compatible = "qcom,geni-i2c"; 1118 reg = <0 0x00994000 0 0x4000>; 1119 clock-names = "se"; 1120 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1121 pinctrl-names = "default"; 1122 pinctrl-0 = <&qup_i2c5_default>; 1123 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1124 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1125 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1126 dma-names = "tx", "rx"; 1127 #address-cells = <1>; 1128 #size-cells = <0>; 1129 status = "disabled"; 1130 }; 1131 1132 spi5: spi@994000 { 1133 compatible = "qcom,geni-spi"; 1134 reg = <0 0x00994000 0 0x4000>; 1135 clock-names = "se"; 1136 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1137 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1138 power-domains = <&rpmhpd RPMHPD_CX>; 1139 operating-points-v2 = <&qup_opp_table_100mhz>; 1140 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1141 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1142 dma-names = "tx", "rx"; 1143 #address-cells = <1>; 1144 #size-cells = <0>; 1145 status = "disabled"; 1146 }; 1147 1148 i2c6: i2c@998000 { 1149 compatible = "qcom,geni-i2c"; 1150 reg = <0 0x00998000 0 0x4000>; 1151 clock-names = "se"; 1152 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1153 pinctrl-names = "default"; 1154 pinctrl-0 = <&qup_i2c6_default>; 1155 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1156 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1157 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1158 dma-names = "tx", "rx"; 1159 #address-cells = <1>; 1160 #size-cells = <0>; 1161 status = "disabled"; 1162 }; 1163 1164 spi6: spi@998000 { 1165 compatible = "qcom,geni-spi"; 1166 reg = <0 0x00998000 0 0x4000>; 1167 clock-names = "se"; 1168 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1169 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1170 power-domains = <&rpmhpd RPMHPD_CX>; 1171 operating-points-v2 = <&qup_opp_table_100mhz>; 1172 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1173 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1174 dma-names = "tx", "rx"; 1175 #address-cells = <1>; 1176 #size-cells = <0>; 1177 status = "disabled"; 1178 }; 1179 1180 uart6: serial@998000 { 1181 compatible = "qcom,geni-uart"; 1182 reg = <0 0x00998000 0 0x4000>; 1183 clock-names = "se"; 1184 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1185 pinctrl-names = "default"; 1186 pinctrl-0 = <&qup_uart6_default>; 1187 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1188 power-domains = <&rpmhpd RPMHPD_CX>; 1189 operating-points-v2 = <&qup_opp_table_100mhz>; 1190 status = "disabled"; 1191 }; 1192 1193 i2c7: i2c@99c000 { 1194 compatible = "qcom,geni-i2c"; 1195 reg = <0 0x0099c000 0 0x4000>; 1196 clock-names = "se"; 1197 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1198 pinctrl-names = "default"; 1199 pinctrl-0 = <&qup_i2c7_default>; 1200 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1201 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1202 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1203 dma-names = "tx", "rx"; 1204 #address-cells = <1>; 1205 #size-cells = <0>; 1206 status = "disabled"; 1207 }; 1208 1209 spi7: spi@99c000 { 1210 compatible = "qcom,geni-spi"; 1211 reg = <0 0x0099c000 0 0x4000>; 1212 clock-names = "se"; 1213 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1214 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1215 power-domains = <&rpmhpd RPMHPD_CX>; 1216 operating-points-v2 = <&qup_opp_table_100mhz>; 1217 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1218 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1219 dma-names = "tx", "rx"; 1220 #address-cells = <1>; 1221 #size-cells = <0>; 1222 status = "disabled"; 1223 }; 1224 }; 1225 1226 gpi_dma1: dma-controller@a00000 { 1227 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 1228 reg = <0 0x00a00000 0 0x60000>; 1229 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1241 dma-channels = <12>; 1242 dma-channel-mask = <0xff>; 1243 iommus = <&apps_smmu 0x56 0x0>; 1244 #dma-cells = <3>; 1245 status = "disabled"; 1246 }; 1247 1248 qupv3_id_1: geniqup@ac0000 { 1249 compatible = "qcom,geni-se-qup"; 1250 reg = <0x0 0x00ac0000 0x0 0x6000>; 1251 clock-names = "m-ahb", "s-ahb"; 1252 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1253 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1254 iommus = <&apps_smmu 0x43 0>; 1255 #address-cells = <2>; 1256 #size-cells = <2>; 1257 ranges; 1258 status = "disabled"; 1259 1260 i2c8: i2c@a80000 { 1261 compatible = "qcom,geni-i2c"; 1262 reg = <0 0x00a80000 0 0x4000>; 1263 clock-names = "se"; 1264 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1265 pinctrl-names = "default"; 1266 pinctrl-0 = <&qup_i2c8_default>; 1267 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1268 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1269 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1270 dma-names = "tx", "rx"; 1271 #address-cells = <1>; 1272 #size-cells = <0>; 1273 status = "disabled"; 1274 }; 1275 1276 spi8: spi@a80000 { 1277 compatible = "qcom,geni-spi"; 1278 reg = <0 0x00a80000 0 0x4000>; 1279 clock-names = "se"; 1280 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1281 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1282 power-domains = <&rpmhpd RPMHPD_CX>; 1283 operating-points-v2 = <&qup_opp_table_120mhz>; 1284 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1285 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1286 dma-names = "tx", "rx"; 1287 #address-cells = <1>; 1288 #size-cells = <0>; 1289 status = "disabled"; 1290 }; 1291 1292 i2c9: i2c@a84000 { 1293 compatible = "qcom,geni-i2c"; 1294 reg = <0 0x00a84000 0 0x4000>; 1295 clock-names = "se"; 1296 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1297 pinctrl-names = "default"; 1298 pinctrl-0 = <&qup_i2c9_default>; 1299 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1300 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1301 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1302 dma-names = "tx", "rx"; 1303 #address-cells = <1>; 1304 #size-cells = <0>; 1305 status = "disabled"; 1306 }; 1307 1308 spi9: spi@a84000 { 1309 compatible = "qcom,geni-spi"; 1310 reg = <0 0x00a84000 0 0x4000>; 1311 clock-names = "se"; 1312 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1313 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1314 power-domains = <&rpmhpd RPMHPD_CX>; 1315 operating-points-v2 = <&qup_opp_table_100mhz>; 1316 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1317 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1318 dma-names = "tx", "rx"; 1319 #address-cells = <1>; 1320 #size-cells = <0>; 1321 status = "disabled"; 1322 }; 1323 1324 i2c10: i2c@a88000 { 1325 compatible = "qcom,geni-i2c"; 1326 reg = <0 0x00a88000 0 0x4000>; 1327 clock-names = "se"; 1328 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1329 pinctrl-names = "default"; 1330 pinctrl-0 = <&qup_i2c10_default>; 1331 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1332 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1333 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1334 dma-names = "tx", "rx"; 1335 #address-cells = <1>; 1336 #size-cells = <0>; 1337 status = "disabled"; 1338 }; 1339 1340 spi10: spi@a88000 { 1341 compatible = "qcom,geni-spi"; 1342 reg = <0 0x00a88000 0 0x4000>; 1343 clock-names = "se"; 1344 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1345 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1346 power-domains = <&rpmhpd RPMHPD_CX>; 1347 operating-points-v2 = <&qup_opp_table_100mhz>; 1348 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1349 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1350 dma-names = "tx", "rx"; 1351 #address-cells = <1>; 1352 #size-cells = <0>; 1353 status = "disabled"; 1354 }; 1355 1356 i2c11: i2c@a8c000 { 1357 compatible = "qcom,geni-i2c"; 1358 reg = <0 0x00a8c000 0 0x4000>; 1359 clock-names = "se"; 1360 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1361 pinctrl-names = "default"; 1362 pinctrl-0 = <&qup_i2c11_default>; 1363 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1364 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1365 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1366 dma-names = "tx", "rx"; 1367 #address-cells = <1>; 1368 #size-cells = <0>; 1369 status = "disabled"; 1370 }; 1371 1372 spi11: spi@a8c000 { 1373 compatible = "qcom,geni-spi"; 1374 reg = <0 0x00a8c000 0 0x4000>; 1375 clock-names = "se"; 1376 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1377 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1378 power-domains = <&rpmhpd RPMHPD_CX>; 1379 operating-points-v2 = <&qup_opp_table_100mhz>; 1380 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1381 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1382 dma-names = "tx", "rx"; 1383 #address-cells = <1>; 1384 #size-cells = <0>; 1385 status = "disabled"; 1386 }; 1387 1388 i2c12: i2c@a90000 { 1389 compatible = "qcom,geni-i2c"; 1390 reg = <0 0x00a90000 0 0x4000>; 1391 clock-names = "se"; 1392 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1393 pinctrl-names = "default"; 1394 pinctrl-0 = <&qup_i2c12_default>; 1395 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1396 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1397 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1398 dma-names = "tx", "rx"; 1399 #address-cells = <1>; 1400 #size-cells = <0>; 1401 status = "disabled"; 1402 }; 1403 1404 spi12: spi@a90000 { 1405 compatible = "qcom,geni-spi"; 1406 reg = <0 0x00a90000 0 0x4000>; 1407 clock-names = "se"; 1408 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1409 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1410 power-domains = <&rpmhpd RPMHPD_CX>; 1411 operating-points-v2 = <&qup_opp_table_100mhz>; 1412 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1413 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1414 dma-names = "tx", "rx"; 1415 #address-cells = <1>; 1416 #size-cells = <0>; 1417 status = "disabled"; 1418 }; 1419 1420 i2c13: i2c@a94000 { 1421 compatible = "qcom,geni-i2c"; 1422 reg = <0 0x00a94000 0 0x4000>; 1423 clock-names = "se"; 1424 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1425 pinctrl-names = "default"; 1426 pinctrl-0 = <&qup_i2c13_default>; 1427 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1428 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1429 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1430 dma-names = "tx", "rx"; 1431 #address-cells = <1>; 1432 #size-cells = <0>; 1433 status = "disabled"; 1434 }; 1435 1436 spi13: spi@a94000 { 1437 compatible = "qcom,geni-spi"; 1438 reg = <0 0x00a94000 0 0x4000>; 1439 clock-names = "se"; 1440 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1441 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1442 power-domains = <&rpmhpd RPMHPD_CX>; 1443 operating-points-v2 = <&qup_opp_table_100mhz>; 1444 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1445 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1446 dma-names = "tx", "rx"; 1447 #address-cells = <1>; 1448 #size-cells = <0>; 1449 status = "disabled"; 1450 }; 1451 }; 1452 1453 rng: rng@10d3000 { 1454 compatible = "qcom,prng-ee"; 1455 reg = <0 0x010d3000 0 0x1000>; 1456 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1457 clock-names = "core"; 1458 }; 1459 1460 config_noc: interconnect@1500000 { 1461 compatible = "qcom,sm8350-config-noc"; 1462 reg = <0 0x01500000 0 0xa580>; 1463 #interconnect-cells = <2>; 1464 qcom,bcm-voters = <&apps_bcm_voter>; 1465 }; 1466 1467 mc_virt: interconnect@1580000 { 1468 compatible = "qcom,sm8350-mc-virt"; 1469 reg = <0 0x01580000 0 0x1000>; 1470 #interconnect-cells = <2>; 1471 qcom,bcm-voters = <&apps_bcm_voter>; 1472 }; 1473 1474 system_noc: interconnect@1680000 { 1475 compatible = "qcom,sm8350-system-noc"; 1476 reg = <0 0x01680000 0 0x1c200>; 1477 #interconnect-cells = <2>; 1478 qcom,bcm-voters = <&apps_bcm_voter>; 1479 }; 1480 1481 aggre1_noc: interconnect@16e0000 { 1482 compatible = "qcom,sm8350-aggre1-noc"; 1483 reg = <0 0x016e0000 0 0x1f180>; 1484 #interconnect-cells = <2>; 1485 qcom,bcm-voters = <&apps_bcm_voter>; 1486 }; 1487 1488 aggre2_noc: interconnect@1700000 { 1489 compatible = "qcom,sm8350-aggre2-noc"; 1490 reg = <0 0x01700000 0 0x33000>; 1491 #interconnect-cells = <2>; 1492 qcom,bcm-voters = <&apps_bcm_voter>; 1493 }; 1494 1495 mmss_noc: interconnect@1740000 { 1496 compatible = "qcom,sm8350-mmss-noc"; 1497 reg = <0 0x01740000 0 0x1f080>; 1498 #interconnect-cells = <2>; 1499 qcom,bcm-voters = <&apps_bcm_voter>; 1500 }; 1501 1502 pcie0: pcie@1c00000 { 1503 compatible = "qcom,pcie-sm8350"; 1504 reg = <0 0x01c00000 0 0x3000>, 1505 <0 0x60000000 0 0xf1d>, 1506 <0 0x60000f20 0 0xa8>, 1507 <0 0x60001000 0 0x1000>, 1508 <0 0x60100000 0 0x100000>; 1509 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1510 device_type = "pci"; 1511 linux,pci-domain = <0>; 1512 bus-range = <0x00 0xff>; 1513 num-lanes = <1>; 1514 1515 #address-cells = <3>; 1516 #size-cells = <2>; 1517 1518 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1519 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1520 1521 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1522 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1529 interrupt-names = "msi0", "msi1", "msi2", "msi3", 1530 "msi4", "msi5", "msi6", "msi7"; 1531 #interrupt-cells = <1>; 1532 interrupt-map-mask = <0 0 0 0x7>; 1533 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1534 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1535 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1536 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1537 1538 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1539 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1540 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1541 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1542 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1543 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1544 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1545 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1546 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; 1547 clock-names = "aux", 1548 "cfg", 1549 "bus_master", 1550 "bus_slave", 1551 "slave_q2a", 1552 "tbu", 1553 "ddrss_sf_tbu", 1554 "aggre1", 1555 "aggre0"; 1556 1557 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1558 <0x100 &apps_smmu 0x1c01 0x1>; 1559 1560 resets = <&gcc GCC_PCIE_0_BCR>; 1561 reset-names = "pci"; 1562 1563 power-domains = <&gcc PCIE_0_GDSC>; 1564 1565 phys = <&pcie0_phy>; 1566 phy-names = "pciephy"; 1567 1568 status = "disabled"; 1569 }; 1570 1571 pcie0_phy: phy@1c06000 { 1572 compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy"; 1573 reg = <0 0x01c06000 0 0x2000>; 1574 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1575 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1576 <&gcc GCC_PCIE_0_CLKREF_EN>, 1577 <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, 1578 <&gcc GCC_PCIE_0_PIPE_CLK>; 1579 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1580 1581 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1582 reset-names = "phy"; 1583 1584 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>; 1585 assigned-clock-rates = <100000000>; 1586 1587 #clock-cells = <0>; 1588 clock-output-names = "pcie_0_pipe_clk"; 1589 1590 #phy-cells = <0>; 1591 1592 status = "disabled"; 1593 }; 1594 1595 pcie1: pcie@1c08000 { 1596 compatible = "qcom,pcie-sm8350"; 1597 reg = <0 0x01c08000 0 0x3000>, 1598 <0 0x40000000 0 0xf1d>, 1599 <0 0x40000f20 0 0xa8>, 1600 <0 0x40001000 0 0x1000>, 1601 <0 0x40100000 0 0x100000>; 1602 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1603 device_type = "pci"; 1604 linux,pci-domain = <1>; 1605 bus-range = <0x00 0xff>; 1606 num-lanes = <2>; 1607 1608 #address-cells = <3>; 1609 #size-cells = <2>; 1610 1611 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1612 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1613 1614 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1615 interrupt-names = "msi"; 1616 #interrupt-cells = <1>; 1617 interrupt-map-mask = <0 0 0 0x7>; 1618 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1619 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1620 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1621 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1622 1623 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1624 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1625 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1626 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1627 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1628 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1629 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1630 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1631 clock-names = "aux", 1632 "cfg", 1633 "bus_master", 1634 "bus_slave", 1635 "slave_q2a", 1636 "tbu", 1637 "ddrss_sf_tbu", 1638 "aggre1"; 1639 1640 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1641 <0x100 &apps_smmu 0x1c81 0x1>; 1642 1643 resets = <&gcc GCC_PCIE_1_BCR>; 1644 reset-names = "pci"; 1645 1646 power-domains = <&gcc PCIE_1_GDSC>; 1647 1648 phys = <&pcie1_phy>; 1649 phy-names = "pciephy"; 1650 1651 status = "disabled"; 1652 }; 1653 1654 pcie1_phy: phy@1c0e000 { 1655 compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy"; 1656 reg = <0 0x01c0e000 0 0x2000>; 1657 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1658 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1659 <&gcc GCC_PCIE_1_CLKREF_EN>, 1660 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, 1661 <&gcc GCC_PCIE_1_PIPE_CLK>; 1662 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1663 1664 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1665 reset-names = "phy"; 1666 1667 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1668 assigned-clock-rates = <100000000>; 1669 1670 #clock-cells = <0>; 1671 clock-output-names = "pcie_1_pipe_clk"; 1672 1673 #phy-cells = <0>; 1674 1675 status = "disabled"; 1676 }; 1677 1678 ufs_mem_hc: ufshc@1d84000 { 1679 compatible = "qcom,sm8350-ufshc", "qcom,ufshc", 1680 "jedec,ufs-2.0"; 1681 reg = <0 0x01d84000 0 0x3000>; 1682 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1683 phys = <&ufs_mem_phy>; 1684 phy-names = "ufsphy"; 1685 lanes-per-direction = <2>; 1686 #reset-cells = <1>; 1687 resets = <&gcc GCC_UFS_PHY_BCR>; 1688 reset-names = "rst"; 1689 1690 power-domains = <&gcc UFS_PHY_GDSC>; 1691 1692 iommus = <&apps_smmu 0xe0 0x0>; 1693 dma-coherent; 1694 1695 clock-names = 1696 "core_clk", 1697 "bus_aggr_clk", 1698 "iface_clk", 1699 "core_clk_unipro", 1700 "ref_clk", 1701 "tx_lane0_sync_clk", 1702 "rx_lane0_sync_clk", 1703 "rx_lane1_sync_clk"; 1704 clocks = 1705 <&gcc GCC_UFS_PHY_AXI_CLK>, 1706 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1707 <&gcc GCC_UFS_PHY_AHB_CLK>, 1708 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1709 <&rpmhcc RPMH_CXO_CLK>, 1710 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1711 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1712 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1713 freq-table-hz = 1714 <75000000 300000000>, 1715 <0 0>, 1716 <0 0>, 1717 <75000000 300000000>, 1718 <0 0>, 1719 <0 0>, 1720 <0 0>, 1721 <0 0>; 1722 status = "disabled"; 1723 }; 1724 1725 ufs_mem_phy: phy@1d87000 { 1726 compatible = "qcom,sm8350-qmp-ufs-phy"; 1727 reg = <0 0x01d87000 0 0x1000>; 1728 1729 clock-names = "ref", 1730 "ref_aux"; 1731 clocks = <&rpmhcc RPMH_CXO_CLK>, 1732 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1733 1734 resets = <&ufs_mem_hc 0>; 1735 reset-names = "ufsphy"; 1736 1737 #clock-cells = <1>; 1738 #phy-cells = <0>; 1739 1740 status = "disabled"; 1741 }; 1742 1743 cryptobam: dma-controller@1dc4000 { 1744 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1745 reg = <0 0x01dc4000 0 0x24000>; 1746 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1747 #dma-cells = <1>; 1748 qcom,ee = <0>; 1749 qcom,controlled-remotely; 1750 iommus = <&apps_smmu 0x594 0x0011>, 1751 <&apps_smmu 0x596 0x0011>; 1752 /* FIXME: Probing BAM DMA causes some abort and system hang */ 1753 status = "fail"; 1754 }; 1755 1756 crypto: crypto@1dfa000 { 1757 compatible = "qcom,sm8350-qce", "qcom,sm8150-qce", "qcom,qce"; 1758 reg = <0 0x01dfa000 0 0x6000>; 1759 dmas = <&cryptobam 4>, <&cryptobam 5>; 1760 dma-names = "rx", "tx"; 1761 iommus = <&apps_smmu 0x594 0x0011>, 1762 <&apps_smmu 0x596 0x0011>; 1763 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 1764 interconnect-names = "memory"; 1765 /* FIXME: dependency BAM DMA is disabled */ 1766 status = "disabled"; 1767 }; 1768 1769 ipa: ipa@1e40000 { 1770 compatible = "qcom,sm8350-ipa"; 1771 1772 iommus = <&apps_smmu 0x5c0 0x0>, 1773 <&apps_smmu 0x5c2 0x0>; 1774 reg = <0 0x01e40000 0 0x8000>, 1775 <0 0x01e50000 0 0x4b20>, 1776 <0 0x01e04000 0 0x23000>; 1777 reg-names = "ipa-reg", 1778 "ipa-shared", 1779 "gsi"; 1780 1781 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, 1782 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1783 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1784 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1785 interrupt-names = "ipa", 1786 "gsi", 1787 "ipa-clock-query", 1788 "ipa-setup-ready"; 1789 1790 clocks = <&rpmhcc RPMH_IPA_CLK>; 1791 clock-names = "core"; 1792 1793 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1794 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1795 interconnect-names = "memory", 1796 "config"; 1797 1798 qcom,qmp = <&aoss_qmp>; 1799 1800 qcom,smem-states = <&ipa_smp2p_out 0>, 1801 <&ipa_smp2p_out 1>; 1802 qcom,smem-state-names = "ipa-clock-enabled-valid", 1803 "ipa-clock-enabled"; 1804 1805 status = "disabled"; 1806 }; 1807 1808 tcsr_mutex: hwlock@1f40000 { 1809 compatible = "qcom,tcsr-mutex"; 1810 reg = <0x0 0x01f40000 0x0 0x40000>; 1811 #hwlock-cells = <1>; 1812 }; 1813 1814 tcsr: syscon@1fc0000 { 1815 compatible = "qcom,sm8350-tcsr", "syscon"; 1816 reg = <0x0 0x1fc0000 0x0 0x30000>; 1817 }; 1818 1819 lpass_tlmm: pinctrl@33c0000 { 1820 compatible = "qcom,sm8350-lpass-lpi-pinctrl"; 1821 reg = <0 0x033c0000 0 0x20000>, 1822 <0 0x03550000 0 0x10000>; 1823 1824 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1825 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1826 clock-names = "core", "audio"; 1827 1828 gpio-controller; 1829 #gpio-cells = <2>; 1830 gpio-ranges = <&lpass_tlmm 0 0 15>; 1831 }; 1832 1833 gpu: gpu@3d00000 { 1834 compatible = "qcom,adreno-660.1", "qcom,adreno"; 1835 1836 reg = <0 0x03d00000 0 0x40000>, 1837 <0 0x03d9e000 0 0x1000>, 1838 <0 0x03d61000 0 0x800>; 1839 reg-names = "kgsl_3d0_reg_memory", 1840 "cx_mem", 1841 "cx_dbgc"; 1842 1843 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1844 1845 iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>; 1846 1847 operating-points-v2 = <&gpu_opp_table>; 1848 1849 qcom,gmu = <&gmu>; 1850 1851 status = "disabled"; 1852 1853 zap-shader { 1854 memory-region = <&pil_gpu_mem>; 1855 }; 1856 1857 /* note: downstream checks gpu binning for 670 Mhz */ 1858 gpu_opp_table: opp-table { 1859 compatible = "operating-points-v2"; 1860 1861 opp-840000000 { 1862 opp-hz = /bits/ 64 <840000000>; 1863 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1864 }; 1865 1866 opp-778000000 { 1867 opp-hz = /bits/ 64 <778000000>; 1868 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1869 }; 1870 1871 opp-738000000 { 1872 opp-hz = /bits/ 64 <738000000>; 1873 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1874 }; 1875 1876 opp-676000000 { 1877 opp-hz = /bits/ 64 <676000000>; 1878 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1879 }; 1880 1881 opp-608000000 { 1882 opp-hz = /bits/ 64 <608000000>; 1883 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1884 }; 1885 1886 opp-540000000 { 1887 opp-hz = /bits/ 64 <540000000>; 1888 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1889 }; 1890 1891 opp-491000000 { 1892 opp-hz = /bits/ 64 <491000000>; 1893 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 1894 }; 1895 1896 opp-443000000 { 1897 opp-hz = /bits/ 64 <443000000>; 1898 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1899 }; 1900 1901 opp-379000000 { 1902 opp-hz = /bits/ 64 <379000000>; 1903 opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>; 1904 }; 1905 1906 opp-315000000 { 1907 opp-hz = /bits/ 64 <315000000>; 1908 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1909 }; 1910 }; 1911 }; 1912 1913 gmu: gmu@3d6a000 { 1914 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu"; 1915 1916 reg = <0 0x03d6a000 0 0x34000>, 1917 <0 0x03de0000 0 0x10000>, 1918 <0 0x0b290000 0 0x10000>; 1919 reg-names = "gmu", "rscc", "gmu_pdc"; 1920 1921 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1922 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1923 interrupt-names = "hfi", "gmu"; 1924 1925 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 1926 <&gpucc GPU_CC_CXO_CLK>, 1927 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1928 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1929 <&gpucc GPU_CC_AHB_CLK>, 1930 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 1931 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 1932 clock-names = "gmu", 1933 "cxo", 1934 "axi", 1935 "memnoc", 1936 "ahb", 1937 "hub", 1938 "smmu_vote"; 1939 1940 power-domains = <&gpucc GPU_CX_GDSC>, 1941 <&gpucc GPU_GX_GDSC>; 1942 power-domain-names = "cx", 1943 "gx"; 1944 1945 iommus = <&adreno_smmu 5 0x400>; 1946 1947 operating-points-v2 = <&gmu_opp_table>; 1948 1949 gmu_opp_table: opp-table { 1950 compatible = "operating-points-v2"; 1951 1952 opp-200000000 { 1953 opp-hz = /bits/ 64 <200000000>; 1954 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1955 }; 1956 }; 1957 }; 1958 1959 gpucc: clock-controller@3d90000 { 1960 compatible = "qcom,sm8350-gpucc"; 1961 reg = <0 0x03d90000 0 0x9000>; 1962 clocks = <&rpmhcc RPMH_CXO_CLK>, 1963 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1964 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1965 clock-names = "bi_tcxo", 1966 "gcc_gpu_gpll0_clk_src", 1967 "gcc_gpu_gpll0_div_clk_src"; 1968 #clock-cells = <1>; 1969 #reset-cells = <1>; 1970 #power-domain-cells = <1>; 1971 }; 1972 1973 adreno_smmu: iommu@3da0000 { 1974 compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu", 1975 "qcom,smmu-500", "arm,mmu-500"; 1976 reg = <0 0x03da0000 0 0x20000>; 1977 #iommu-cells = <2>; 1978 #global-interrupts = <2>; 1979 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 1980 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 1981 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 1982 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 1983 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 1984 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 1985 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 1986 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 1987 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 1988 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 1989 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 1990 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 1991 1992 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1993 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 1994 <&gpucc GPU_CC_AHB_CLK>, 1995 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1996 <&gpucc GPU_CC_CX_GMU_CLK>, 1997 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 1998 <&gpucc GPU_CC_HUB_AON_CLK>; 1999 clock-names = "bus", 2000 "iface", 2001 "ahb", 2002 "hlos1_vote_gpu_smmu", 2003 "cx_gmu", 2004 "hub_cx_int", 2005 "hub_aon"; 2006 2007 power-domains = <&gpucc GPU_CX_GDSC>; 2008 dma-coherent; 2009 }; 2010 2011 lpass_ag_noc: interconnect@3c40000 { 2012 compatible = "qcom,sm8350-lpass-ag-noc"; 2013 reg = <0 0x03c40000 0 0xf080>; 2014 #interconnect-cells = <2>; 2015 qcom,bcm-voters = <&apps_bcm_voter>; 2016 }; 2017 2018 mpss: remoteproc@4080000 { 2019 compatible = "qcom,sm8350-mpss-pas"; 2020 reg = <0x0 0x04080000 0x0 0x4040>; 2021 2022 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2023 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2024 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2025 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2026 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2027 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2028 interrupt-names = "wdog", "fatal", "ready", "handover", 2029 "stop-ack", "shutdown-ack"; 2030 2031 clocks = <&rpmhcc RPMH_CXO_CLK>; 2032 clock-names = "xo"; 2033 2034 power-domains = <&rpmhpd RPMHPD_CX>, 2035 <&rpmhpd RPMHPD_MSS>; 2036 power-domain-names = "cx", "mss"; 2037 2038 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2039 2040 memory-region = <&pil_modem_mem>; 2041 2042 qcom,qmp = <&aoss_qmp>; 2043 2044 qcom,smem-states = <&smp2p_modem_out 0>; 2045 qcom,smem-state-names = "stop"; 2046 2047 status = "disabled"; 2048 2049 glink-edge { 2050 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2051 IPCC_MPROC_SIGNAL_GLINK_QMP 2052 IRQ_TYPE_EDGE_RISING>; 2053 mboxes = <&ipcc IPCC_CLIENT_MPSS 2054 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2055 label = "modem"; 2056 qcom,remote-pid = <1>; 2057 }; 2058 }; 2059 2060 slpi: remoteproc@5c00000 { 2061 compatible = "qcom,sm8350-slpi-pas"; 2062 reg = <0 0x05c00000 0 0x4000>; 2063 2064 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2065 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2066 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2067 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2068 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2069 interrupt-names = "wdog", "fatal", "ready", 2070 "handover", "stop-ack"; 2071 2072 clocks = <&rpmhcc RPMH_CXO_CLK>; 2073 clock-names = "xo"; 2074 2075 power-domains = <&rpmhpd RPMHPD_LCX>, 2076 <&rpmhpd RPMHPD_LMX>; 2077 power-domain-names = "lcx", "lmx"; 2078 2079 memory-region = <&pil_slpi_mem>; 2080 2081 qcom,qmp = <&aoss_qmp>; 2082 2083 qcom,smem-states = <&smp2p_slpi_out 0>; 2084 qcom,smem-state-names = "stop"; 2085 2086 status = "disabled"; 2087 2088 glink-edge { 2089 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2090 IPCC_MPROC_SIGNAL_GLINK_QMP 2091 IRQ_TYPE_EDGE_RISING>; 2092 mboxes = <&ipcc IPCC_CLIENT_SLPI 2093 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2094 2095 label = "slpi"; 2096 qcom,remote-pid = <3>; 2097 2098 fastrpc { 2099 compatible = "qcom,fastrpc"; 2100 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2101 label = "sdsp"; 2102 qcom,non-secure-domain; 2103 #address-cells = <1>; 2104 #size-cells = <0>; 2105 2106 compute-cb@1 { 2107 compatible = "qcom,fastrpc-compute-cb"; 2108 reg = <1>; 2109 iommus = <&apps_smmu 0x0541 0x0>; 2110 }; 2111 2112 compute-cb@2 { 2113 compatible = "qcom,fastrpc-compute-cb"; 2114 reg = <2>; 2115 iommus = <&apps_smmu 0x0542 0x0>; 2116 }; 2117 2118 compute-cb@3 { 2119 compatible = "qcom,fastrpc-compute-cb"; 2120 reg = <3>; 2121 iommus = <&apps_smmu 0x0543 0x0>; 2122 /* note: shared-cb = <4> in downstream */ 2123 }; 2124 }; 2125 }; 2126 }; 2127 2128 sdhc_2: mmc@8804000 { 2129 compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5"; 2130 reg = <0 0x08804000 0 0x1000>; 2131 2132 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2133 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2134 interrupt-names = "hc_irq", "pwr_irq"; 2135 2136 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2137 <&gcc GCC_SDCC2_APPS_CLK>, 2138 <&rpmhcc RPMH_CXO_CLK>; 2139 clock-names = "iface", "core", "xo"; 2140 resets = <&gcc GCC_SDCC2_BCR>; 2141 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2142 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2143 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2144 iommus = <&apps_smmu 0x4a0 0x0>; 2145 power-domains = <&rpmhpd RPMHPD_CX>; 2146 operating-points-v2 = <&sdhc2_opp_table>; 2147 bus-width = <4>; 2148 dma-coherent; 2149 2150 status = "disabled"; 2151 2152 sdhc2_opp_table: opp-table { 2153 compatible = "operating-points-v2"; 2154 2155 opp-100000000 { 2156 opp-hz = /bits/ 64 <100000000>; 2157 required-opps = <&rpmhpd_opp_low_svs>; 2158 }; 2159 2160 opp-202000000 { 2161 opp-hz = /bits/ 64 <202000000>; 2162 required-opps = <&rpmhpd_opp_svs_l1>; 2163 }; 2164 }; 2165 }; 2166 2167 usb_1_hsphy: phy@88e3000 { 2168 compatible = "qcom,sm8350-usb-hs-phy", 2169 "qcom,usb-snps-hs-7nm-phy"; 2170 reg = <0 0x088e3000 0 0x400>; 2171 status = "disabled"; 2172 #phy-cells = <0>; 2173 2174 clocks = <&rpmhcc RPMH_CXO_CLK>; 2175 clock-names = "ref"; 2176 2177 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2178 }; 2179 2180 usb_2_hsphy: phy@88e4000 { 2181 compatible = "qcom,sm8250-usb-hs-phy", 2182 "qcom,usb-snps-hs-7nm-phy"; 2183 reg = <0 0x088e4000 0 0x400>; 2184 status = "disabled"; 2185 #phy-cells = <0>; 2186 2187 clocks = <&rpmhcc RPMH_CXO_CLK>; 2188 clock-names = "ref"; 2189 2190 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2191 }; 2192 2193 usb_1_qmpphy: phy@88e8000 { 2194 compatible = "qcom,sm8350-qmp-usb3-dp-phy"; 2195 reg = <0 0x088e8000 0 0x3000>; 2196 2197 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2198 <&rpmhcc RPMH_CXO_CLK>, 2199 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2200 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2201 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2202 2203 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2204 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2205 reset-names = "phy", "common"; 2206 2207 #clock-cells = <1>; 2208 #phy-cells = <1>; 2209 2210 status = "disabled"; 2211 2212 ports { 2213 #address-cells = <1>; 2214 #size-cells = <0>; 2215 2216 port@0 { 2217 reg = <0>; 2218 2219 usb_1_qmpphy_out: endpoint { 2220 }; 2221 }; 2222 2223 port@1 { 2224 reg = <1>; 2225 2226 usb_1_qmpphy_usb_ss_in: endpoint { 2227 }; 2228 }; 2229 2230 port@2 { 2231 reg = <2>; 2232 2233 usb_1_qmpphy_dp_in: endpoint { 2234 }; 2235 }; 2236 }; 2237 }; 2238 2239 usb_2_qmpphy: phy@88eb000 { 2240 compatible = "qcom,sm8350-qmp-usb3-uni-phy"; 2241 reg = <0 0x088eb000 0 0x2000>; 2242 status = "disabled"; 2243 2244 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2245 <&gcc GCC_USB3_SEC_CLKREF_EN>, 2246 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2247 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2248 clock-names = "aux", 2249 "ref", 2250 "com_aux", 2251 "pipe"; 2252 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2253 #clock-cells = <0>; 2254 #phy-cells = <0>; 2255 2256 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2257 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 2258 reset-names = "phy", 2259 "phy_phy"; 2260 }; 2261 2262 dc_noc: interconnect@90c0000 { 2263 compatible = "qcom,sm8350-dc-noc"; 2264 reg = <0 0x090c0000 0 0x4200>; 2265 #interconnect-cells = <2>; 2266 qcom,bcm-voters = <&apps_bcm_voter>; 2267 }; 2268 2269 gem_noc: interconnect@9100000 { 2270 compatible = "qcom,sm8350-gem-noc"; 2271 reg = <0 0x09100000 0 0xb4000>; 2272 #interconnect-cells = <2>; 2273 qcom,bcm-voters = <&apps_bcm_voter>; 2274 }; 2275 2276 system-cache-controller@9200000 { 2277 compatible = "qcom,sm8350-llcc"; 2278 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 2279 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 2280 <0 0x09600000 0 0x58000>; 2281 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2282 "llcc3_base", "llcc_broadcast_base"; 2283 }; 2284 2285 compute_noc: interconnect@a0c0000 { 2286 compatible = "qcom,sm8350-compute-noc"; 2287 reg = <0 0x0a0c0000 0 0xa180>; 2288 #interconnect-cells = <2>; 2289 qcom,bcm-voters = <&apps_bcm_voter>; 2290 }; 2291 2292 usb_1: usb@a6f8800 { 2293 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2294 reg = <0 0x0a6f8800 0 0x400>; 2295 status = "disabled"; 2296 #address-cells = <2>; 2297 #size-cells = <2>; 2298 ranges; 2299 2300 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2301 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2302 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2303 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2304 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 2305 clock-names = "cfg_noc", 2306 "core", 2307 "iface", 2308 "sleep", 2309 "mock_utmi"; 2310 2311 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2312 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2313 assigned-clock-rates = <19200000>, <200000000>; 2314 2315 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2316 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2317 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2318 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2319 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2320 interrupt-names = "pwr_event", 2321 "hs_phy_irq", 2322 "dp_hs_phy_irq", 2323 "dm_hs_phy_irq", 2324 "ss_phy_irq"; 2325 2326 power-domains = <&gcc USB30_PRIM_GDSC>; 2327 2328 resets = <&gcc GCC_USB30_PRIM_BCR>; 2329 2330 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2331 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 2332 interconnect-names = "usb-ddr", "apps-usb"; 2333 2334 usb_1_dwc3: usb@a600000 { 2335 compatible = "snps,dwc3"; 2336 reg = <0 0x0a600000 0 0xcd00>; 2337 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2338 iommus = <&apps_smmu 0x0 0x0>; 2339 snps,dis_u2_susphy_quirk; 2340 snps,dis_enblslpm_quirk; 2341 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 2342 phy-names = "usb2-phy", "usb3-phy"; 2343 2344 ports { 2345 #address-cells = <1>; 2346 #size-cells = <0>; 2347 2348 port@0 { 2349 reg = <0>; 2350 2351 usb_1_dwc3_hs: endpoint { 2352 }; 2353 }; 2354 2355 port@1 { 2356 reg = <1>; 2357 2358 usb_1_dwc3_ss: endpoint { 2359 }; 2360 }; 2361 }; 2362 }; 2363 }; 2364 2365 usb_2: usb@a8f8800 { 2366 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2367 reg = <0 0x0a8f8800 0 0x400>; 2368 status = "disabled"; 2369 #address-cells = <2>; 2370 #size-cells = <2>; 2371 ranges; 2372 2373 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2374 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2375 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2376 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2377 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2378 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2379 clock-names = "cfg_noc", 2380 "core", 2381 "iface", 2382 "sleep", 2383 "mock_utmi", 2384 "xo"; 2385 2386 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2387 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2388 assigned-clock-rates = <19200000>, <200000000>; 2389 2390 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 2391 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2392 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 2393 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 2394 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 2395 interrupt-names = "pwr_event", 2396 "hs_phy_irq", 2397 "dp_hs_phy_irq", 2398 "dm_hs_phy_irq", 2399 "ss_phy_irq"; 2400 2401 power-domains = <&gcc USB30_SEC_GDSC>; 2402 2403 resets = <&gcc GCC_USB30_SEC_BCR>; 2404 2405 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 2406 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 2407 interconnect-names = "usb-ddr", "apps-usb"; 2408 2409 usb_2_dwc3: usb@a800000 { 2410 compatible = "snps,dwc3"; 2411 reg = <0 0x0a800000 0 0xcd00>; 2412 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2413 iommus = <&apps_smmu 0x20 0x0>; 2414 snps,dis_u2_susphy_quirk; 2415 snps,dis_enblslpm_quirk; 2416 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>; 2417 phy-names = "usb2-phy", "usb3-phy"; 2418 }; 2419 }; 2420 2421 mdss: display-subsystem@ae00000 { 2422 compatible = "qcom,sm8350-mdss"; 2423 reg = <0 0x0ae00000 0 0x1000>; 2424 reg-names = "mdss"; 2425 2426 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 2427 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 2428 interconnect-names = "mdp0-mem", "mdp1-mem"; 2429 2430 power-domains = <&dispcc MDSS_GDSC>; 2431 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2432 2433 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2434 <&gcc GCC_DISP_HF_AXI_CLK>, 2435 <&gcc GCC_DISP_SF_AXI_CLK>, 2436 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2437 clock-names = "iface", "bus", "nrt_bus", "core"; 2438 2439 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2440 interrupt-controller; 2441 #interrupt-cells = <1>; 2442 2443 iommus = <&apps_smmu 0x820 0x402>; 2444 2445 status = "disabled"; 2446 2447 #address-cells = <2>; 2448 #size-cells = <2>; 2449 ranges; 2450 2451 mdss_mdp: display-controller@ae01000 { 2452 compatible = "qcom,sm8350-dpu"; 2453 reg = <0 0x0ae01000 0 0x8f000>, 2454 <0 0x0aeb0000 0 0x2008>; 2455 reg-names = "mdp", "vbif"; 2456 2457 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2458 <&gcc GCC_DISP_SF_AXI_CLK>, 2459 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2460 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2461 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2462 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2463 clock-names = "bus", 2464 "nrt_bus", 2465 "iface", 2466 "lut", 2467 "core", 2468 "vsync"; 2469 2470 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2471 assigned-clock-rates = <19200000>; 2472 2473 operating-points-v2 = <&dpu_opp_table>; 2474 power-domains = <&rpmhpd RPMHPD_MMCX>; 2475 2476 interrupt-parent = <&mdss>; 2477 interrupts = <0>; 2478 2479 dpu_opp_table: opp-table { 2480 compatible = "operating-points-v2"; 2481 2482 /* TODO: opp-200000000 should work with 2483 * &rpmhpd_opp_low_svs, but one some of 2484 * sm8350_hdk boards reboot using this 2485 * opp. 2486 */ 2487 opp-200000000 { 2488 opp-hz = /bits/ 64 <200000000>; 2489 required-opps = <&rpmhpd_opp_svs>; 2490 }; 2491 2492 opp-300000000 { 2493 opp-hz = /bits/ 64 <300000000>; 2494 required-opps = <&rpmhpd_opp_svs>; 2495 }; 2496 2497 opp-345000000 { 2498 opp-hz = /bits/ 64 <345000000>; 2499 required-opps = <&rpmhpd_opp_svs_l1>; 2500 }; 2501 2502 opp-460000000 { 2503 opp-hz = /bits/ 64 <460000000>; 2504 required-opps = <&rpmhpd_opp_nom>; 2505 }; 2506 }; 2507 2508 ports { 2509 #address-cells = <1>; 2510 #size-cells = <0>; 2511 2512 port@0 { 2513 reg = <0>; 2514 dpu_intf1_out: endpoint { 2515 remote-endpoint = <&mdss_dsi0_in>; 2516 }; 2517 }; 2518 2519 port@1 { 2520 reg = <1>; 2521 dpu_intf2_out: endpoint { 2522 remote-endpoint = <&mdss_dsi1_in>; 2523 }; 2524 }; 2525 2526 port@2 { 2527 reg = <2>; 2528 dpu_intf0_out: endpoint { 2529 remote-endpoint = <&mdss_dp_in>; 2530 }; 2531 }; 2532 }; 2533 }; 2534 2535 mdss_dp: displayport-controller@ae90000 { 2536 compatible = "qcom,sm8350-dp"; 2537 reg = <0 0xae90000 0 0x200>, 2538 <0 0xae90200 0 0x200>, 2539 <0 0xae90400 0 0x600>, 2540 <0 0xae91000 0 0x400>, 2541 <0 0xae91400 0 0x400>; 2542 interrupt-parent = <&mdss>; 2543 interrupts = <12>; 2544 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2545 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 2546 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 2547 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 2548 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 2549 clock-names = "core_iface", 2550 "core_aux", 2551 "ctrl_link", 2552 "ctrl_link_iface", 2553 "stream_pixel"; 2554 2555 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 2556 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 2557 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2558 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2559 2560 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 2561 phy-names = "dp"; 2562 2563 #sound-dai-cells = <0>; 2564 2565 operating-points-v2 = <&dp_opp_table>; 2566 power-domains = <&rpmhpd RPMHPD_MMCX>; 2567 2568 status = "disabled"; 2569 2570 ports { 2571 #address-cells = <1>; 2572 #size-cells = <0>; 2573 2574 port@0 { 2575 reg = <0>; 2576 mdss_dp_in: endpoint { 2577 remote-endpoint = <&dpu_intf0_out>; 2578 }; 2579 }; 2580 }; 2581 2582 dp_opp_table: opp-table { 2583 compatible = "operating-points-v2"; 2584 2585 opp-160000000 { 2586 opp-hz = /bits/ 64 <160000000>; 2587 required-opps = <&rpmhpd_opp_low_svs>; 2588 }; 2589 2590 opp-270000000 { 2591 opp-hz = /bits/ 64 <270000000>; 2592 required-opps = <&rpmhpd_opp_svs>; 2593 }; 2594 2595 opp-540000000 { 2596 opp-hz = /bits/ 64 <540000000>; 2597 required-opps = <&rpmhpd_opp_svs_l1>; 2598 }; 2599 2600 opp-810000000 { 2601 opp-hz = /bits/ 64 <810000000>; 2602 required-opps = <&rpmhpd_opp_nom>; 2603 }; 2604 }; 2605 }; 2606 2607 mdss_dsi0: dsi@ae94000 { 2608 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2609 reg = <0 0x0ae94000 0 0x400>; 2610 reg-names = "dsi_ctrl"; 2611 2612 interrupt-parent = <&mdss>; 2613 interrupts = <4>; 2614 2615 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2616 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2617 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2618 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2619 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2620 <&gcc GCC_DISP_HF_AXI_CLK>; 2621 clock-names = "byte", 2622 "byte_intf", 2623 "pixel", 2624 "core", 2625 "iface", 2626 "bus"; 2627 2628 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2629 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2630 assigned-clock-parents = <&mdss_dsi0_phy 0>, 2631 <&mdss_dsi0_phy 1>; 2632 2633 operating-points-v2 = <&dsi0_opp_table>; 2634 power-domains = <&rpmhpd RPMHPD_MMCX>; 2635 2636 phys = <&mdss_dsi0_phy>; 2637 2638 #address-cells = <1>; 2639 #size-cells = <0>; 2640 2641 status = "disabled"; 2642 2643 dsi0_opp_table: opp-table { 2644 compatible = "operating-points-v2"; 2645 2646 /* TODO: opp-187500000 should work with 2647 * &rpmhpd_opp_low_svs, but one some of 2648 * sm8350_hdk boards reboot using this 2649 * opp. 2650 */ 2651 opp-187500000 { 2652 opp-hz = /bits/ 64 <187500000>; 2653 required-opps = <&rpmhpd_opp_svs>; 2654 }; 2655 2656 opp-300000000 { 2657 opp-hz = /bits/ 64 <300000000>; 2658 required-opps = <&rpmhpd_opp_svs>; 2659 }; 2660 2661 opp-358000000 { 2662 opp-hz = /bits/ 64 <358000000>; 2663 required-opps = <&rpmhpd_opp_svs_l1>; 2664 }; 2665 }; 2666 2667 ports { 2668 #address-cells = <1>; 2669 #size-cells = <0>; 2670 2671 port@0 { 2672 reg = <0>; 2673 mdss_dsi0_in: endpoint { 2674 remote-endpoint = <&dpu_intf1_out>; 2675 }; 2676 }; 2677 2678 port@1 { 2679 reg = <1>; 2680 mdss_dsi0_out: endpoint { 2681 }; 2682 }; 2683 }; 2684 }; 2685 2686 mdss_dsi0_phy: phy@ae94400 { 2687 compatible = "qcom,sm8350-dsi-phy-5nm"; 2688 reg = <0 0x0ae94400 0 0x200>, 2689 <0 0x0ae94600 0 0x280>, 2690 <0 0x0ae94900 0 0x27c>; 2691 reg-names = "dsi_phy", 2692 "dsi_phy_lane", 2693 "dsi_pll"; 2694 2695 #clock-cells = <1>; 2696 #phy-cells = <0>; 2697 2698 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2699 <&rpmhcc RPMH_CXO_CLK>; 2700 clock-names = "iface", "ref"; 2701 2702 status = "disabled"; 2703 }; 2704 2705 mdss_dsi1: dsi@ae96000 { 2706 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2707 reg = <0 0x0ae96000 0 0x400>; 2708 reg-names = "dsi_ctrl"; 2709 2710 interrupt-parent = <&mdss>; 2711 interrupts = <5>; 2712 2713 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2714 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2715 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2716 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2717 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2718 <&gcc GCC_DISP_HF_AXI_CLK>; 2719 clock-names = "byte", 2720 "byte_intf", 2721 "pixel", 2722 "core", 2723 "iface", 2724 "bus"; 2725 2726 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 2727 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2728 assigned-clock-parents = <&mdss_dsi1_phy 0>, 2729 <&mdss_dsi1_phy 1>; 2730 2731 operating-points-v2 = <&dsi1_opp_table>; 2732 power-domains = <&rpmhpd RPMHPD_MMCX>; 2733 2734 phys = <&mdss_dsi1_phy>; 2735 2736 #address-cells = <1>; 2737 #size-cells = <0>; 2738 2739 status = "disabled"; 2740 2741 dsi1_opp_table: opp-table { 2742 compatible = "operating-points-v2"; 2743 2744 /* TODO: opp-187500000 should work with 2745 * &rpmhpd_opp_low_svs, but one some of 2746 * sm8350_hdk boards reboot using this 2747 * opp. 2748 */ 2749 opp-187500000 { 2750 opp-hz = /bits/ 64 <187500000>; 2751 required-opps = <&rpmhpd_opp_svs>; 2752 }; 2753 2754 opp-300000000 { 2755 opp-hz = /bits/ 64 <300000000>; 2756 required-opps = <&rpmhpd_opp_svs>; 2757 }; 2758 2759 opp-358000000 { 2760 opp-hz = /bits/ 64 <358000000>; 2761 required-opps = <&rpmhpd_opp_svs_l1>; 2762 }; 2763 }; 2764 2765 ports { 2766 #address-cells = <1>; 2767 #size-cells = <0>; 2768 2769 port@0 { 2770 reg = <0>; 2771 mdss_dsi1_in: endpoint { 2772 remote-endpoint = <&dpu_intf2_out>; 2773 }; 2774 }; 2775 2776 port@1 { 2777 reg = <1>; 2778 mdss_dsi1_out: endpoint { 2779 }; 2780 }; 2781 }; 2782 }; 2783 2784 mdss_dsi1_phy: phy@ae96400 { 2785 compatible = "qcom,sm8350-dsi-phy-5nm"; 2786 reg = <0 0x0ae96400 0 0x200>, 2787 <0 0x0ae96600 0 0x280>, 2788 <0 0x0ae96900 0 0x27c>; 2789 reg-names = "dsi_phy", 2790 "dsi_phy_lane", 2791 "dsi_pll"; 2792 2793 #clock-cells = <1>; 2794 #phy-cells = <0>; 2795 2796 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2797 <&rpmhcc RPMH_CXO_CLK>; 2798 clock-names = "iface", "ref"; 2799 2800 status = "disabled"; 2801 }; 2802 }; 2803 2804 dispcc: clock-controller@af00000 { 2805 compatible = "qcom,sm8350-dispcc"; 2806 reg = <0 0x0af00000 0 0x10000>; 2807 clocks = <&rpmhcc RPMH_CXO_CLK>, 2808 <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, 2809 <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, 2810 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2811 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2812 clock-names = "bi_tcxo", 2813 "dsi0_phy_pll_out_byteclk", 2814 "dsi0_phy_pll_out_dsiclk", 2815 "dsi1_phy_pll_out_byteclk", 2816 "dsi1_phy_pll_out_dsiclk", 2817 "dp_phy_pll_link_clk", 2818 "dp_phy_pll_vco_div_clk"; 2819 #clock-cells = <1>; 2820 #reset-cells = <1>; 2821 #power-domain-cells = <1>; 2822 2823 power-domains = <&rpmhpd RPMHPD_MMCX>; 2824 }; 2825 2826 pdc: interrupt-controller@b220000 { 2827 compatible = "qcom,sm8350-pdc", "qcom,pdc"; 2828 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 2829 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, 2830 <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, 2831 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, 2832 <156 716 12>; 2833 #interrupt-cells = <2>; 2834 interrupt-parent = <&intc>; 2835 interrupt-controller; 2836 }; 2837 2838 tsens0: thermal-sensor@c263000 { 2839 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 2840 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2841 <0 0x0c222000 0 0x8>; /* SROT */ 2842 #qcom,sensors = <15>; 2843 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 2844 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 2845 interrupt-names = "uplow", "critical"; 2846 #thermal-sensor-cells = <1>; 2847 }; 2848 2849 tsens1: thermal-sensor@c265000 { 2850 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 2851 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2852 <0 0x0c223000 0 0x8>; /* SROT */ 2853 #qcom,sensors = <14>; 2854 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 2855 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 2856 interrupt-names = "uplow", "critical"; 2857 #thermal-sensor-cells = <1>; 2858 }; 2859 2860 aoss_qmp: power-management@c300000 { 2861 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; 2862 reg = <0 0x0c300000 0 0x400>; 2863 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2864 IRQ_TYPE_EDGE_RISING>; 2865 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2866 2867 #clock-cells = <0>; 2868 }; 2869 2870 sram@c3f0000 { 2871 compatible = "qcom,rpmh-stats"; 2872 reg = <0 0x0c3f0000 0 0x400>; 2873 }; 2874 2875 spmi_bus: spmi@c440000 { 2876 compatible = "qcom,spmi-pmic-arb"; 2877 reg = <0x0 0x0c440000 0x0 0x1100>, 2878 <0x0 0x0c600000 0x0 0x2000000>, 2879 <0x0 0x0e600000 0x0 0x100000>, 2880 <0x0 0x0e700000 0x0 0xa0000>, 2881 <0x0 0x0c40a000 0x0 0x26000>; 2882 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2883 interrupt-names = "periph_irq"; 2884 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2885 qcom,ee = <0>; 2886 qcom,channel = <0>; 2887 #address-cells = <2>; 2888 #size-cells = <0>; 2889 interrupt-controller; 2890 #interrupt-cells = <4>; 2891 }; 2892 2893 tlmm: pinctrl@f100000 { 2894 compatible = "qcom,sm8350-tlmm"; 2895 reg = <0 0x0f100000 0 0x300000>; 2896 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2897 gpio-controller; 2898 #gpio-cells = <2>; 2899 interrupt-controller; 2900 #interrupt-cells = <2>; 2901 gpio-ranges = <&tlmm 0 0 204>; 2902 wakeup-parent = <&pdc>; 2903 2904 sdc2_default_state: sdc2-default-state { 2905 clk-pins { 2906 pins = "sdc2_clk"; 2907 drive-strength = <16>; 2908 bias-disable; 2909 }; 2910 2911 cmd-pins { 2912 pins = "sdc2_cmd"; 2913 drive-strength = <16>; 2914 bias-pull-up; 2915 }; 2916 2917 data-pins { 2918 pins = "sdc2_data"; 2919 drive-strength = <16>; 2920 bias-pull-up; 2921 }; 2922 }; 2923 2924 sdc2_sleep_state: sdc2-sleep-state { 2925 clk-pins { 2926 pins = "sdc2_clk"; 2927 drive-strength = <2>; 2928 bias-disable; 2929 }; 2930 2931 cmd-pins { 2932 pins = "sdc2_cmd"; 2933 drive-strength = <2>; 2934 bias-pull-up; 2935 }; 2936 2937 data-pins { 2938 pins = "sdc2_data"; 2939 drive-strength = <2>; 2940 bias-pull-up; 2941 }; 2942 }; 2943 2944 qup_uart3_default_state: qup-uart3-default-state { 2945 rx-pins { 2946 pins = "gpio18"; 2947 function = "qup3"; 2948 }; 2949 tx-pins { 2950 pins = "gpio19"; 2951 function = "qup3"; 2952 }; 2953 }; 2954 2955 qup_uart6_default: qup-uart6-default-state { 2956 pins = "gpio30", "gpio31"; 2957 function = "qup6"; 2958 drive-strength = <2>; 2959 bias-disable; 2960 }; 2961 2962 qup_uart18_default: qup-uart18-default-state { 2963 pins = "gpio68", "gpio69"; 2964 function = "qup18"; 2965 drive-strength = <2>; 2966 bias-disable; 2967 }; 2968 2969 qup_i2c0_default: qup-i2c0-default-state { 2970 pins = "gpio4", "gpio5"; 2971 function = "qup0"; 2972 drive-strength = <2>; 2973 bias-pull-up; 2974 }; 2975 2976 qup_i2c1_default: qup-i2c1-default-state { 2977 pins = "gpio8", "gpio9"; 2978 function = "qup1"; 2979 drive-strength = <2>; 2980 bias-pull-up; 2981 }; 2982 2983 qup_i2c2_default: qup-i2c2-default-state { 2984 pins = "gpio12", "gpio13"; 2985 function = "qup2"; 2986 drive-strength = <2>; 2987 bias-pull-up; 2988 }; 2989 2990 qup_i2c4_default: qup-i2c4-default-state { 2991 pins = "gpio20", "gpio21"; 2992 function = "qup4"; 2993 drive-strength = <2>; 2994 bias-pull-up; 2995 }; 2996 2997 qup_i2c5_default: qup-i2c5-default-state { 2998 pins = "gpio24", "gpio25"; 2999 function = "qup5"; 3000 drive-strength = <2>; 3001 bias-pull-up; 3002 }; 3003 3004 qup_i2c6_default: qup-i2c6-default-state { 3005 pins = "gpio28", "gpio29"; 3006 function = "qup6"; 3007 drive-strength = <2>; 3008 bias-pull-up; 3009 }; 3010 3011 qup_i2c7_default: qup-i2c7-default-state { 3012 pins = "gpio32", "gpio33"; 3013 function = "qup7"; 3014 drive-strength = <2>; 3015 bias-disable; 3016 }; 3017 3018 qup_i2c8_default: qup-i2c8-default-state { 3019 pins = "gpio36", "gpio37"; 3020 function = "qup8"; 3021 drive-strength = <2>; 3022 bias-pull-up; 3023 }; 3024 3025 qup_i2c9_default: qup-i2c9-default-state { 3026 pins = "gpio40", "gpio41"; 3027 function = "qup9"; 3028 drive-strength = <2>; 3029 bias-pull-up; 3030 }; 3031 3032 qup_i2c10_default: qup-i2c10-default-state { 3033 pins = "gpio44", "gpio45"; 3034 function = "qup10"; 3035 drive-strength = <2>; 3036 bias-pull-up; 3037 }; 3038 3039 qup_i2c11_default: qup-i2c11-default-state { 3040 pins = "gpio48", "gpio49"; 3041 function = "qup11"; 3042 drive-strength = <2>; 3043 bias-pull-up; 3044 }; 3045 3046 qup_i2c12_default: qup-i2c12-default-state { 3047 pins = "gpio52", "gpio53"; 3048 function = "qup12"; 3049 drive-strength = <2>; 3050 bias-pull-up; 3051 }; 3052 3053 qup_i2c13_default: qup-i2c13-default-state { 3054 pins = "gpio0", "gpio1"; 3055 function = "qup13"; 3056 drive-strength = <2>; 3057 bias-pull-up; 3058 }; 3059 3060 qup_i2c14_default: qup-i2c14-default-state { 3061 pins = "gpio56", "gpio57"; 3062 function = "qup14"; 3063 drive-strength = <2>; 3064 bias-disable; 3065 }; 3066 3067 qup_i2c15_default: qup-i2c15-default-state { 3068 pins = "gpio60", "gpio61"; 3069 function = "qup15"; 3070 drive-strength = <2>; 3071 bias-disable; 3072 }; 3073 3074 qup_i2c16_default: qup-i2c16-default-state { 3075 pins = "gpio64", "gpio65"; 3076 function = "qup16"; 3077 drive-strength = <2>; 3078 bias-disable; 3079 }; 3080 3081 qup_i2c17_default: qup-i2c17-default-state { 3082 pins = "gpio72", "gpio73"; 3083 function = "qup17"; 3084 drive-strength = <2>; 3085 bias-disable; 3086 }; 3087 3088 qup_i2c19_default: qup-i2c19-default-state { 3089 pins = "gpio76", "gpio77"; 3090 function = "qup19"; 3091 drive-strength = <2>; 3092 bias-disable; 3093 }; 3094 }; 3095 3096 apps_smmu: iommu@15000000 { 3097 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; 3098 reg = <0 0x15000000 0 0x100000>; 3099 #iommu-cells = <2>; 3100 #global-interrupts = <2>; 3101 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 3102 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3103 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3104 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3105 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3106 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3107 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3108 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3109 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3110 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3111 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3112 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3113 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3114 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3115 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3116 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3117 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3118 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3119 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3120 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3121 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3122 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3123 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3124 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3125 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3126 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3127 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3128 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3129 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3130 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3131 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3132 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3133 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3134 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3135 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3136 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3137 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3138 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3139 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3140 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3141 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3142 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3143 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3144 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3145 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3146 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3147 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3148 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3149 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3150 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3151 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3152 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3153 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3154 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3155 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3156 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3157 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3158 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3159 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3160 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3161 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3162 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3163 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3164 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3165 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3166 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3167 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3168 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3169 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3170 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3171 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3172 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3173 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3174 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3175 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3176 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3177 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3178 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3179 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3180 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3181 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3182 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3183 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3184 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3185 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3186 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3187 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3188 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3189 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3190 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3191 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3192 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3193 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3194 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3195 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3196 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3197 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 3198 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 3199 }; 3200 3201 adsp: remoteproc@17300000 { 3202 compatible = "qcom,sm8350-adsp-pas"; 3203 reg = <0 0x17300000 0 0x100>; 3204 3205 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 3206 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3207 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3208 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3209 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 3210 interrupt-names = "wdog", "fatal", "ready", 3211 "handover", "stop-ack"; 3212 3213 clocks = <&rpmhcc RPMH_CXO_CLK>; 3214 clock-names = "xo"; 3215 3216 power-domains = <&rpmhpd RPMHPD_LCX>, 3217 <&rpmhpd RPMHPD_LMX>; 3218 power-domain-names = "lcx", "lmx"; 3219 3220 memory-region = <&pil_adsp_mem>; 3221 3222 qcom,qmp = <&aoss_qmp>; 3223 3224 qcom,smem-states = <&smp2p_adsp_out 0>; 3225 qcom,smem-state-names = "stop"; 3226 3227 status = "disabled"; 3228 3229 glink-edge { 3230 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3231 IPCC_MPROC_SIGNAL_GLINK_QMP 3232 IRQ_TYPE_EDGE_RISING>; 3233 mboxes = <&ipcc IPCC_CLIENT_LPASS 3234 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3235 3236 label = "lpass"; 3237 qcom,remote-pid = <2>; 3238 3239 apr { 3240 compatible = "qcom,apr-v2"; 3241 qcom,glink-channels = "apr_audio_svc"; 3242 qcom,domain = <APR_DOMAIN_ADSP>; 3243 #address-cells = <1>; 3244 #size-cells = <0>; 3245 3246 service@3 { 3247 reg = <APR_SVC_ADSP_CORE>; 3248 compatible = "qcom,q6core"; 3249 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3250 }; 3251 3252 q6afe: service@4 { 3253 compatible = "qcom,q6afe"; 3254 reg = <APR_SVC_AFE>; 3255 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3256 3257 q6afedai: dais { 3258 compatible = "qcom,q6afe-dais"; 3259 #address-cells = <1>; 3260 #size-cells = <0>; 3261 #sound-dai-cells = <1>; 3262 }; 3263 3264 q6afecc: clock-controller { 3265 compatible = "qcom,q6afe-clocks"; 3266 #clock-cells = <2>; 3267 }; 3268 }; 3269 3270 q6asm: service@7 { 3271 compatible = "qcom,q6asm"; 3272 reg = <APR_SVC_ASM>; 3273 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3274 3275 q6asmdai: dais { 3276 compatible = "qcom,q6asm-dais"; 3277 #address-cells = <1>; 3278 #size-cells = <0>; 3279 #sound-dai-cells = <1>; 3280 iommus = <&apps_smmu 0x1801 0x0>; 3281 3282 dai@0 { 3283 reg = <0>; 3284 }; 3285 3286 dai@1 { 3287 reg = <1>; 3288 }; 3289 3290 dai@2 { 3291 reg = <2>; 3292 }; 3293 }; 3294 }; 3295 3296 q6adm: service@8 { 3297 compatible = "qcom,q6adm"; 3298 reg = <APR_SVC_ADM>; 3299 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3300 3301 q6routing: routing { 3302 compatible = "qcom,q6adm-routing"; 3303 #sound-dai-cells = <0>; 3304 }; 3305 }; 3306 }; 3307 3308 fastrpc { 3309 compatible = "qcom,fastrpc"; 3310 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3311 label = "adsp"; 3312 qcom,non-secure-domain; 3313 #address-cells = <1>; 3314 #size-cells = <0>; 3315 3316 compute-cb@3 { 3317 compatible = "qcom,fastrpc-compute-cb"; 3318 reg = <3>; 3319 iommus = <&apps_smmu 0x1803 0x0>; 3320 }; 3321 3322 compute-cb@4 { 3323 compatible = "qcom,fastrpc-compute-cb"; 3324 reg = <4>; 3325 iommus = <&apps_smmu 0x1804 0x0>; 3326 }; 3327 3328 compute-cb@5 { 3329 compatible = "qcom,fastrpc-compute-cb"; 3330 reg = <5>; 3331 iommus = <&apps_smmu 0x1805 0x0>; 3332 }; 3333 }; 3334 }; 3335 }; 3336 3337 intc: interrupt-controller@17a00000 { 3338 compatible = "arm,gic-v3"; 3339 #interrupt-cells = <3>; 3340 interrupt-controller; 3341 #redistributor-regions = <1>; 3342 redistributor-stride = <0 0x20000>; 3343 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3344 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3345 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3346 }; 3347 3348 timer@17c20000 { 3349 compatible = "arm,armv7-timer-mem"; 3350 #address-cells = <1>; 3351 #size-cells = <1>; 3352 ranges = <0 0 0 0x20000000>; 3353 reg = <0x0 0x17c20000 0x0 0x1000>; 3354 clock-frequency = <19200000>; 3355 3356 frame@17c21000 { 3357 frame-number = <0>; 3358 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3359 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3360 reg = <0x17c21000 0x1000>, 3361 <0x17c22000 0x1000>; 3362 }; 3363 3364 frame@17c23000 { 3365 frame-number = <1>; 3366 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3367 reg = <0x17c23000 0x1000>; 3368 status = "disabled"; 3369 }; 3370 3371 frame@17c25000 { 3372 frame-number = <2>; 3373 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3374 reg = <0x17c25000 0x1000>; 3375 status = "disabled"; 3376 }; 3377 3378 frame@17c27000 { 3379 frame-number = <3>; 3380 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3381 reg = <0x17c27000 0x1000>; 3382 status = "disabled"; 3383 }; 3384 3385 frame@17c29000 { 3386 frame-number = <4>; 3387 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3388 reg = <0x17c29000 0x1000>; 3389 status = "disabled"; 3390 }; 3391 3392 frame@17c2b000 { 3393 frame-number = <5>; 3394 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3395 reg = <0x17c2b000 0x1000>; 3396 status = "disabled"; 3397 }; 3398 3399 frame@17c2d000 { 3400 frame-number = <6>; 3401 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3402 reg = <0x17c2d000 0x1000>; 3403 status = "disabled"; 3404 }; 3405 }; 3406 3407 apps_rsc: rsc@18200000 { 3408 label = "apps_rsc"; 3409 compatible = "qcom,rpmh-rsc"; 3410 reg = <0x0 0x18200000 0x0 0x10000>, 3411 <0x0 0x18210000 0x0 0x10000>, 3412 <0x0 0x18220000 0x0 0x10000>; 3413 reg-names = "drv-0", "drv-1", "drv-2"; 3414 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3415 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3416 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3417 qcom,tcs-offset = <0xd00>; 3418 qcom,drv-id = <2>; 3419 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 3420 <WAKE_TCS 3>, <CONTROL_TCS 0>; 3421 power-domains = <&CLUSTER_PD>; 3422 3423 rpmhcc: clock-controller { 3424 compatible = "qcom,sm8350-rpmh-clk"; 3425 #clock-cells = <1>; 3426 clock-names = "xo"; 3427 clocks = <&xo_board>; 3428 }; 3429 3430 rpmhpd: power-controller { 3431 compatible = "qcom,sm8350-rpmhpd"; 3432 #power-domain-cells = <1>; 3433 operating-points-v2 = <&rpmhpd_opp_table>; 3434 3435 rpmhpd_opp_table: opp-table { 3436 compatible = "operating-points-v2"; 3437 3438 rpmhpd_opp_ret: opp1 { 3439 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3440 }; 3441 3442 rpmhpd_opp_min_svs: opp2 { 3443 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3444 }; 3445 3446 rpmhpd_opp_low_svs: opp3 { 3447 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3448 }; 3449 3450 rpmhpd_opp_svs: opp4 { 3451 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3452 }; 3453 3454 rpmhpd_opp_svs_l1: opp5 { 3455 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3456 }; 3457 3458 rpmhpd_opp_nom: opp6 { 3459 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3460 }; 3461 3462 rpmhpd_opp_nom_l1: opp7 { 3463 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3464 }; 3465 3466 rpmhpd_opp_nom_l2: opp8 { 3467 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3468 }; 3469 3470 rpmhpd_opp_turbo: opp9 { 3471 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3472 }; 3473 3474 rpmhpd_opp_turbo_l1: opp10 { 3475 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3476 }; 3477 }; 3478 }; 3479 3480 apps_bcm_voter: bcm-voter { 3481 compatible = "qcom,bcm-voter"; 3482 }; 3483 }; 3484 3485 cpufreq_hw: cpufreq@18591000 { 3486 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss"; 3487 reg = <0 0x18591000 0 0x1000>, 3488 <0 0x18592000 0 0x1000>, 3489 <0 0x18593000 0 0x1000>; 3490 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3491 3492 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 3493 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3494 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 3495 interrupt-names = "dcvsh-irq-0", 3496 "dcvsh-irq-1", 3497 "dcvsh-irq-2"; 3498 3499 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3500 clock-names = "xo", "alternate"; 3501 3502 #freq-domain-cells = <1>; 3503 #clock-cells = <1>; 3504 }; 3505 3506 cdsp: remoteproc@98900000 { 3507 compatible = "qcom,sm8350-cdsp-pas"; 3508 reg = <0 0x98900000 0 0x1400000>; 3509 3510 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3511 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3512 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3513 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3514 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3515 interrupt-names = "wdog", "fatal", "ready", 3516 "handover", "stop-ack"; 3517 3518 clocks = <&rpmhcc RPMH_CXO_CLK>; 3519 clock-names = "xo"; 3520 3521 power-domains = <&rpmhpd RPMHPD_CX>, 3522 <&rpmhpd RPMHPD_MXC>; 3523 power-domain-names = "cx", "mxc"; 3524 3525 interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 3526 3527 memory-region = <&pil_cdsp_mem>; 3528 3529 qcom,qmp = <&aoss_qmp>; 3530 3531 qcom,smem-states = <&smp2p_cdsp_out 0>; 3532 qcom,smem-state-names = "stop"; 3533 3534 status = "disabled"; 3535 3536 glink-edge { 3537 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3538 IPCC_MPROC_SIGNAL_GLINK_QMP 3539 IRQ_TYPE_EDGE_RISING>; 3540 mboxes = <&ipcc IPCC_CLIENT_CDSP 3541 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3542 3543 label = "cdsp"; 3544 qcom,remote-pid = <5>; 3545 3546 fastrpc { 3547 compatible = "qcom,fastrpc"; 3548 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3549 label = "cdsp"; 3550 qcom,non-secure-domain; 3551 #address-cells = <1>; 3552 #size-cells = <0>; 3553 3554 compute-cb@1 { 3555 compatible = "qcom,fastrpc-compute-cb"; 3556 reg = <1>; 3557 iommus = <&apps_smmu 0x2161 0x0400>, 3558 <&apps_smmu 0x1181 0x0420>; 3559 }; 3560 3561 compute-cb@2 { 3562 compatible = "qcom,fastrpc-compute-cb"; 3563 reg = <2>; 3564 iommus = <&apps_smmu 0x2162 0x0400>, 3565 <&apps_smmu 0x1182 0x0420>; 3566 }; 3567 3568 compute-cb@3 { 3569 compatible = "qcom,fastrpc-compute-cb"; 3570 reg = <3>; 3571 iommus = <&apps_smmu 0x2163 0x0400>, 3572 <&apps_smmu 0x1183 0x0420>; 3573 }; 3574 3575 compute-cb@4 { 3576 compatible = "qcom,fastrpc-compute-cb"; 3577 reg = <4>; 3578 iommus = <&apps_smmu 0x2164 0x0400>, 3579 <&apps_smmu 0x1184 0x0420>; 3580 }; 3581 3582 compute-cb@5 { 3583 compatible = "qcom,fastrpc-compute-cb"; 3584 reg = <5>; 3585 iommus = <&apps_smmu 0x2165 0x0400>, 3586 <&apps_smmu 0x1185 0x0420>; 3587 }; 3588 3589 compute-cb@6 { 3590 compatible = "qcom,fastrpc-compute-cb"; 3591 reg = <6>; 3592 iommus = <&apps_smmu 0x2166 0x0400>, 3593 <&apps_smmu 0x1186 0x0420>; 3594 }; 3595 3596 compute-cb@7 { 3597 compatible = "qcom,fastrpc-compute-cb"; 3598 reg = <7>; 3599 iommus = <&apps_smmu 0x2167 0x0400>, 3600 <&apps_smmu 0x1187 0x0420>; 3601 }; 3602 3603 compute-cb@8 { 3604 compatible = "qcom,fastrpc-compute-cb"; 3605 reg = <8>; 3606 iommus = <&apps_smmu 0x2168 0x0400>, 3607 <&apps_smmu 0x1188 0x0420>; 3608 }; 3609 3610 /* note: secure cb9 in downstream */ 3611 }; 3612 }; 3613 }; 3614 }; 3615 3616 thermal_zones: thermal-zones { 3617 cpu0-thermal { 3618 polling-delay-passive = <250>; 3619 polling-delay = <1000>; 3620 3621 thermal-sensors = <&tsens0 1>; 3622 3623 trips { 3624 cpu0_alert0: trip-point0 { 3625 temperature = <90000>; 3626 hysteresis = <2000>; 3627 type = "passive"; 3628 }; 3629 3630 cpu0_alert1: trip-point1 { 3631 temperature = <95000>; 3632 hysteresis = <2000>; 3633 type = "passive"; 3634 }; 3635 3636 cpu0_crit: cpu-crit { 3637 temperature = <110000>; 3638 hysteresis = <1000>; 3639 type = "critical"; 3640 }; 3641 }; 3642 3643 cooling-maps { 3644 map0 { 3645 trip = <&cpu0_alert0>; 3646 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3647 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3648 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3649 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3650 }; 3651 map1 { 3652 trip = <&cpu0_alert1>; 3653 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3654 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3655 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3656 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3657 }; 3658 }; 3659 }; 3660 3661 cpu1-thermal { 3662 polling-delay-passive = <250>; 3663 polling-delay = <1000>; 3664 3665 thermal-sensors = <&tsens0 2>; 3666 3667 trips { 3668 cpu1_alert0: trip-point0 { 3669 temperature = <90000>; 3670 hysteresis = <2000>; 3671 type = "passive"; 3672 }; 3673 3674 cpu1_alert1: trip-point1 { 3675 temperature = <95000>; 3676 hysteresis = <2000>; 3677 type = "passive"; 3678 }; 3679 3680 cpu1_crit: cpu-crit { 3681 temperature = <110000>; 3682 hysteresis = <1000>; 3683 type = "critical"; 3684 }; 3685 }; 3686 3687 cooling-maps { 3688 map0 { 3689 trip = <&cpu1_alert0>; 3690 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3691 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3692 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3693 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3694 }; 3695 map1 { 3696 trip = <&cpu1_alert1>; 3697 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3698 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3699 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3700 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3701 }; 3702 }; 3703 }; 3704 3705 cpu2-thermal { 3706 polling-delay-passive = <250>; 3707 polling-delay = <1000>; 3708 3709 thermal-sensors = <&tsens0 3>; 3710 3711 trips { 3712 cpu2_alert0: trip-point0 { 3713 temperature = <90000>; 3714 hysteresis = <2000>; 3715 type = "passive"; 3716 }; 3717 3718 cpu2_alert1: trip-point1 { 3719 temperature = <95000>; 3720 hysteresis = <2000>; 3721 type = "passive"; 3722 }; 3723 3724 cpu2_crit: cpu-crit { 3725 temperature = <110000>; 3726 hysteresis = <1000>; 3727 type = "critical"; 3728 }; 3729 }; 3730 3731 cooling-maps { 3732 map0 { 3733 trip = <&cpu2_alert0>; 3734 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3735 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3736 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3737 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3738 }; 3739 map1 { 3740 trip = <&cpu2_alert1>; 3741 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3742 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3743 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3744 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3745 }; 3746 }; 3747 }; 3748 3749 cpu3-thermal { 3750 polling-delay-passive = <250>; 3751 polling-delay = <1000>; 3752 3753 thermal-sensors = <&tsens0 4>; 3754 3755 trips { 3756 cpu3_alert0: trip-point0 { 3757 temperature = <90000>; 3758 hysteresis = <2000>; 3759 type = "passive"; 3760 }; 3761 3762 cpu3_alert1: trip-point1 { 3763 temperature = <95000>; 3764 hysteresis = <2000>; 3765 type = "passive"; 3766 }; 3767 3768 cpu3_crit: cpu-crit { 3769 temperature = <110000>; 3770 hysteresis = <1000>; 3771 type = "critical"; 3772 }; 3773 }; 3774 3775 cooling-maps { 3776 map0 { 3777 trip = <&cpu3_alert0>; 3778 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3779 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3780 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3781 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3782 }; 3783 map1 { 3784 trip = <&cpu3_alert1>; 3785 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3786 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3787 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3788 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3789 }; 3790 }; 3791 }; 3792 3793 cpu4-top-thermal { 3794 polling-delay-passive = <250>; 3795 polling-delay = <1000>; 3796 3797 thermal-sensors = <&tsens0 7>; 3798 3799 trips { 3800 cpu4_top_alert0: trip-point0 { 3801 temperature = <90000>; 3802 hysteresis = <2000>; 3803 type = "passive"; 3804 }; 3805 3806 cpu4_top_alert1: trip-point1 { 3807 temperature = <95000>; 3808 hysteresis = <2000>; 3809 type = "passive"; 3810 }; 3811 3812 cpu4_top_crit: cpu-crit { 3813 temperature = <110000>; 3814 hysteresis = <1000>; 3815 type = "critical"; 3816 }; 3817 }; 3818 3819 cooling-maps { 3820 map0 { 3821 trip = <&cpu4_top_alert0>; 3822 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3823 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3824 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3825 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3826 }; 3827 map1 { 3828 trip = <&cpu4_top_alert1>; 3829 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3830 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3831 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3832 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3833 }; 3834 }; 3835 }; 3836 3837 cpu5-top-thermal { 3838 polling-delay-passive = <250>; 3839 polling-delay = <1000>; 3840 3841 thermal-sensors = <&tsens0 8>; 3842 3843 trips { 3844 cpu5_top_alert0: trip-point0 { 3845 temperature = <90000>; 3846 hysteresis = <2000>; 3847 type = "passive"; 3848 }; 3849 3850 cpu5_top_alert1: trip-point1 { 3851 temperature = <95000>; 3852 hysteresis = <2000>; 3853 type = "passive"; 3854 }; 3855 3856 cpu5_top_crit: cpu-crit { 3857 temperature = <110000>; 3858 hysteresis = <1000>; 3859 type = "critical"; 3860 }; 3861 }; 3862 3863 cooling-maps { 3864 map0 { 3865 trip = <&cpu5_top_alert0>; 3866 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3867 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3868 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3869 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3870 }; 3871 map1 { 3872 trip = <&cpu5_top_alert1>; 3873 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3874 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3875 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3876 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3877 }; 3878 }; 3879 }; 3880 3881 cpu6-top-thermal { 3882 polling-delay-passive = <250>; 3883 polling-delay = <1000>; 3884 3885 thermal-sensors = <&tsens0 9>; 3886 3887 trips { 3888 cpu6_top_alert0: trip-point0 { 3889 temperature = <90000>; 3890 hysteresis = <2000>; 3891 type = "passive"; 3892 }; 3893 3894 cpu6_top_alert1: trip-point1 { 3895 temperature = <95000>; 3896 hysteresis = <2000>; 3897 type = "passive"; 3898 }; 3899 3900 cpu6_top_crit: cpu-crit { 3901 temperature = <110000>; 3902 hysteresis = <1000>; 3903 type = "critical"; 3904 }; 3905 }; 3906 3907 cooling-maps { 3908 map0 { 3909 trip = <&cpu6_top_alert0>; 3910 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3911 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3912 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3913 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3914 }; 3915 map1 { 3916 trip = <&cpu6_top_alert1>; 3917 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3918 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3919 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3920 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3921 }; 3922 }; 3923 }; 3924 3925 cpu7-top-thermal { 3926 polling-delay-passive = <250>; 3927 polling-delay = <1000>; 3928 3929 thermal-sensors = <&tsens0 10>; 3930 3931 trips { 3932 cpu7_top_alert0: trip-point0 { 3933 temperature = <90000>; 3934 hysteresis = <2000>; 3935 type = "passive"; 3936 }; 3937 3938 cpu7_top_alert1: trip-point1 { 3939 temperature = <95000>; 3940 hysteresis = <2000>; 3941 type = "passive"; 3942 }; 3943 3944 cpu7_top_crit: cpu-crit { 3945 temperature = <110000>; 3946 hysteresis = <1000>; 3947 type = "critical"; 3948 }; 3949 }; 3950 3951 cooling-maps { 3952 map0 { 3953 trip = <&cpu7_top_alert0>; 3954 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3955 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3956 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3957 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3958 }; 3959 map1 { 3960 trip = <&cpu7_top_alert1>; 3961 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3962 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3963 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3964 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3965 }; 3966 }; 3967 }; 3968 3969 cpu4-bottom-thermal { 3970 polling-delay-passive = <250>; 3971 polling-delay = <1000>; 3972 3973 thermal-sensors = <&tsens0 11>; 3974 3975 trips { 3976 cpu4_bottom_alert0: trip-point0 { 3977 temperature = <90000>; 3978 hysteresis = <2000>; 3979 type = "passive"; 3980 }; 3981 3982 cpu4_bottom_alert1: trip-point1 { 3983 temperature = <95000>; 3984 hysteresis = <2000>; 3985 type = "passive"; 3986 }; 3987 3988 cpu4_bottom_crit: cpu-crit { 3989 temperature = <110000>; 3990 hysteresis = <1000>; 3991 type = "critical"; 3992 }; 3993 }; 3994 3995 cooling-maps { 3996 map0 { 3997 trip = <&cpu4_bottom_alert0>; 3998 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3999 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4000 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4001 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4002 }; 4003 map1 { 4004 trip = <&cpu4_bottom_alert1>; 4005 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4006 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4007 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4008 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4009 }; 4010 }; 4011 }; 4012 4013 cpu5-bottom-thermal { 4014 polling-delay-passive = <250>; 4015 polling-delay = <1000>; 4016 4017 thermal-sensors = <&tsens0 12>; 4018 4019 trips { 4020 cpu5_bottom_alert0: trip-point0 { 4021 temperature = <90000>; 4022 hysteresis = <2000>; 4023 type = "passive"; 4024 }; 4025 4026 cpu5_bottom_alert1: trip-point1 { 4027 temperature = <95000>; 4028 hysteresis = <2000>; 4029 type = "passive"; 4030 }; 4031 4032 cpu5_bottom_crit: cpu-crit { 4033 temperature = <110000>; 4034 hysteresis = <1000>; 4035 type = "critical"; 4036 }; 4037 }; 4038 4039 cooling-maps { 4040 map0 { 4041 trip = <&cpu5_bottom_alert0>; 4042 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4043 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4044 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4045 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4046 }; 4047 map1 { 4048 trip = <&cpu5_bottom_alert1>; 4049 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4050 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4051 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4052 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4053 }; 4054 }; 4055 }; 4056 4057 cpu6-bottom-thermal { 4058 polling-delay-passive = <250>; 4059 polling-delay = <1000>; 4060 4061 thermal-sensors = <&tsens0 13>; 4062 4063 trips { 4064 cpu6_bottom_alert0: trip-point0 { 4065 temperature = <90000>; 4066 hysteresis = <2000>; 4067 type = "passive"; 4068 }; 4069 4070 cpu6_bottom_alert1: trip-point1 { 4071 temperature = <95000>; 4072 hysteresis = <2000>; 4073 type = "passive"; 4074 }; 4075 4076 cpu6_bottom_crit: cpu-crit { 4077 temperature = <110000>; 4078 hysteresis = <1000>; 4079 type = "critical"; 4080 }; 4081 }; 4082 4083 cooling-maps { 4084 map0 { 4085 trip = <&cpu6_bottom_alert0>; 4086 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4087 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4088 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4089 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4090 }; 4091 map1 { 4092 trip = <&cpu6_bottom_alert1>; 4093 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4094 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4095 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4096 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4097 }; 4098 }; 4099 }; 4100 4101 cpu7-bottom-thermal { 4102 polling-delay-passive = <250>; 4103 polling-delay = <1000>; 4104 4105 thermal-sensors = <&tsens0 14>; 4106 4107 trips { 4108 cpu7_bottom_alert0: trip-point0 { 4109 temperature = <90000>; 4110 hysteresis = <2000>; 4111 type = "passive"; 4112 }; 4113 4114 cpu7_bottom_alert1: trip-point1 { 4115 temperature = <95000>; 4116 hysteresis = <2000>; 4117 type = "passive"; 4118 }; 4119 4120 cpu7_bottom_crit: cpu-crit { 4121 temperature = <110000>; 4122 hysteresis = <1000>; 4123 type = "critical"; 4124 }; 4125 }; 4126 4127 cooling-maps { 4128 map0 { 4129 trip = <&cpu7_bottom_alert0>; 4130 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4131 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4132 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4133 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4134 }; 4135 map1 { 4136 trip = <&cpu7_bottom_alert1>; 4137 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4138 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4139 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4140 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4141 }; 4142 }; 4143 }; 4144 4145 aoss0-thermal { 4146 polling-delay-passive = <250>; 4147 polling-delay = <1000>; 4148 4149 thermal-sensors = <&tsens0 0>; 4150 4151 trips { 4152 aoss0_alert0: trip-point0 { 4153 temperature = <90000>; 4154 hysteresis = <2000>; 4155 type = "hot"; 4156 }; 4157 }; 4158 }; 4159 4160 cluster0-thermal { 4161 polling-delay-passive = <250>; 4162 polling-delay = <1000>; 4163 4164 thermal-sensors = <&tsens0 5>; 4165 4166 trips { 4167 cluster0_alert0: trip-point0 { 4168 temperature = <90000>; 4169 hysteresis = <2000>; 4170 type = "hot"; 4171 }; 4172 cluster0_crit: cluster0_crit { 4173 temperature = <110000>; 4174 hysteresis = <2000>; 4175 type = "critical"; 4176 }; 4177 }; 4178 }; 4179 4180 cluster1-thermal { 4181 polling-delay-passive = <250>; 4182 polling-delay = <1000>; 4183 4184 thermal-sensors = <&tsens0 6>; 4185 4186 trips { 4187 cluster1_alert0: trip-point0 { 4188 temperature = <90000>; 4189 hysteresis = <2000>; 4190 type = "hot"; 4191 }; 4192 cluster1_crit: cluster1_crit { 4193 temperature = <110000>; 4194 hysteresis = <2000>; 4195 type = "critical"; 4196 }; 4197 }; 4198 }; 4199 4200 aoss1-thermal { 4201 polling-delay-passive = <250>; 4202 polling-delay = <1000>; 4203 4204 thermal-sensors = <&tsens1 0>; 4205 4206 trips { 4207 aoss1_alert0: trip-point0 { 4208 temperature = <90000>; 4209 hysteresis = <2000>; 4210 type = "hot"; 4211 }; 4212 }; 4213 }; 4214 4215 gpu-top-thermal { 4216 polling-delay-passive = <250>; 4217 polling-delay = <1000>; 4218 4219 thermal-sensors = <&tsens1 1>; 4220 4221 trips { 4222 gpu1_alert0: trip-point0 { 4223 temperature = <90000>; 4224 hysteresis = <1000>; 4225 type = "hot"; 4226 }; 4227 }; 4228 }; 4229 4230 gpu-bottom-thermal { 4231 polling-delay-passive = <250>; 4232 polling-delay = <1000>; 4233 4234 thermal-sensors = <&tsens1 2>; 4235 4236 trips { 4237 gpu2_alert0: trip-point0 { 4238 temperature = <90000>; 4239 hysteresis = <1000>; 4240 type = "hot"; 4241 }; 4242 }; 4243 }; 4244 4245 nspss1-thermal { 4246 polling-delay-passive = <250>; 4247 polling-delay = <1000>; 4248 4249 thermal-sensors = <&tsens1 3>; 4250 4251 trips { 4252 nspss1_alert0: trip-point0 { 4253 temperature = <90000>; 4254 hysteresis = <1000>; 4255 type = "hot"; 4256 }; 4257 }; 4258 }; 4259 4260 nspss2-thermal { 4261 polling-delay-passive = <250>; 4262 polling-delay = <1000>; 4263 4264 thermal-sensors = <&tsens1 4>; 4265 4266 trips { 4267 nspss2_alert0: trip-point0 { 4268 temperature = <90000>; 4269 hysteresis = <1000>; 4270 type = "hot"; 4271 }; 4272 }; 4273 }; 4274 4275 nspss3-thermal { 4276 polling-delay-passive = <250>; 4277 polling-delay = <1000>; 4278 4279 thermal-sensors = <&tsens1 5>; 4280 4281 trips { 4282 nspss3_alert0: trip-point0 { 4283 temperature = <90000>; 4284 hysteresis = <1000>; 4285 type = "hot"; 4286 }; 4287 }; 4288 }; 4289 4290 video-thermal { 4291 polling-delay-passive = <250>; 4292 polling-delay = <1000>; 4293 4294 thermal-sensors = <&tsens1 6>; 4295 4296 trips { 4297 video_alert0: trip-point0 { 4298 temperature = <90000>; 4299 hysteresis = <2000>; 4300 type = "hot"; 4301 }; 4302 }; 4303 }; 4304 4305 mem-thermal { 4306 polling-delay-passive = <250>; 4307 polling-delay = <1000>; 4308 4309 thermal-sensors = <&tsens1 7>; 4310 4311 trips { 4312 mem_alert0: trip-point0 { 4313 temperature = <90000>; 4314 hysteresis = <2000>; 4315 type = "hot"; 4316 }; 4317 }; 4318 }; 4319 4320 modem1-top-thermal { 4321 polling-delay-passive = <250>; 4322 polling-delay = <1000>; 4323 4324 thermal-sensors = <&tsens1 8>; 4325 4326 trips { 4327 modem1_alert0: trip-point0 { 4328 temperature = <90000>; 4329 hysteresis = <2000>; 4330 type = "hot"; 4331 }; 4332 }; 4333 }; 4334 4335 modem2-top-thermal { 4336 polling-delay-passive = <250>; 4337 polling-delay = <1000>; 4338 4339 thermal-sensors = <&tsens1 9>; 4340 4341 trips { 4342 modem2_alert0: trip-point0 { 4343 temperature = <90000>; 4344 hysteresis = <2000>; 4345 type = "hot"; 4346 }; 4347 }; 4348 }; 4349 4350 modem3-top-thermal { 4351 polling-delay-passive = <250>; 4352 polling-delay = <1000>; 4353 4354 thermal-sensors = <&tsens1 10>; 4355 4356 trips { 4357 modem3_alert0: trip-point0 { 4358 temperature = <90000>; 4359 hysteresis = <2000>; 4360 type = "hot"; 4361 }; 4362 }; 4363 }; 4364 4365 modem4-top-thermal { 4366 polling-delay-passive = <250>; 4367 polling-delay = <1000>; 4368 4369 thermal-sensors = <&tsens1 11>; 4370 4371 trips { 4372 modem4_alert0: trip-point0 { 4373 temperature = <90000>; 4374 hysteresis = <2000>; 4375 type = "hot"; 4376 }; 4377 }; 4378 }; 4379 4380 camera-top-thermal { 4381 polling-delay-passive = <250>; 4382 polling-delay = <1000>; 4383 4384 thermal-sensors = <&tsens1 12>; 4385 4386 trips { 4387 camera1_alert0: trip-point0 { 4388 temperature = <90000>; 4389 hysteresis = <2000>; 4390 type = "hot"; 4391 }; 4392 }; 4393 }; 4394 4395 cam-bottom-thermal { 4396 polling-delay-passive = <250>; 4397 polling-delay = <1000>; 4398 4399 thermal-sensors = <&tsens1 13>; 4400 4401 trips { 4402 camera2_alert0: trip-point0 { 4403 temperature = <90000>; 4404 hysteresis = <2000>; 4405 type = "hot"; 4406 }; 4407 }; 4408 }; 4409 }; 4410 4411 timer { 4412 compatible = "arm,armv8-timer"; 4413 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4414 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4415 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4416 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4417 }; 4418}; 4419