1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Linaro Limited 4 */ 5 6#include <dt-bindings/interconnect/qcom,sm8350.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/qcom,dispcc-sm8350.h> 9#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 10#include <dt-bindings/clock/qcom,gcc-sm8350.h> 11#include <dt-bindings/clock/qcom,gpucc-sm8350.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/firmware/qcom,scm.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/interconnect/qcom,icc.h> 17#include <dt-bindings/interconnect/qcom,sm8350.h> 18#include <dt-bindings/mailbox/qcom-ipcc.h> 19#include <dt-bindings/phy/phy-qcom-qmp.h> 20#include <dt-bindings/power/qcom-rpmpd.h> 21#include <dt-bindings/power/qcom,rpmhpd.h> 22#include <dt-bindings/soc/qcom,apr.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24#include <dt-bindings/sound/qcom,q6afe.h> 25#include <dt-bindings/sound/qcom,q6asm.h> 26#include <dt-bindings/thermal/thermal.h> 27#include <dt-bindings/interconnect/qcom,sm8350.h> 28 29/ { 30 interrupt-parent = <&intc>; 31 32 #address-cells = <2>; 33 #size-cells = <2>; 34 35 chosen { }; 36 37 clocks { 38 xo_board: xo-board { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <38400000>; 42 clock-output-names = "xo_board"; 43 }; 44 45 sleep_clk: sleep-clk { 46 compatible = "fixed-clock"; 47 clock-frequency = <32764>; 48 #clock-cells = <0>; 49 }; 50 }; 51 52 cpus { 53 #address-cells = <2>; 54 #size-cells = <0>; 55 56 cpu0: cpu@0 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a55"; 59 reg = <0x0 0x0>; 60 clocks = <&cpufreq_hw 0>; 61 enable-method = "psci"; 62 next-level-cache = <&l2_0>; 63 qcom,freq-domain = <&cpufreq_hw 0>; 64 power-domains = <&cpu_pd0>; 65 power-domain-names = "psci"; 66 #cooling-cells = <2>; 67 l2_0: l2-cache { 68 compatible = "cache"; 69 cache-level = <2>; 70 cache-unified; 71 next-level-cache = <&l3_0>; 72 l3_0: l3-cache { 73 compatible = "cache"; 74 cache-level = <3>; 75 cache-unified; 76 }; 77 }; 78 }; 79 80 cpu1: cpu@100 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a55"; 83 reg = <0x0 0x100>; 84 clocks = <&cpufreq_hw 0>; 85 enable-method = "psci"; 86 next-level-cache = <&l2_100>; 87 qcom,freq-domain = <&cpufreq_hw 0>; 88 power-domains = <&cpu_pd1>; 89 power-domain-names = "psci"; 90 #cooling-cells = <2>; 91 l2_100: l2-cache { 92 compatible = "cache"; 93 cache-level = <2>; 94 cache-unified; 95 next-level-cache = <&l3_0>; 96 }; 97 }; 98 99 cpu2: cpu@200 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a55"; 102 reg = <0x0 0x200>; 103 clocks = <&cpufreq_hw 0>; 104 enable-method = "psci"; 105 next-level-cache = <&l2_200>; 106 qcom,freq-domain = <&cpufreq_hw 0>; 107 power-domains = <&cpu_pd2>; 108 power-domain-names = "psci"; 109 #cooling-cells = <2>; 110 l2_200: l2-cache { 111 compatible = "cache"; 112 cache-level = <2>; 113 cache-unified; 114 next-level-cache = <&l3_0>; 115 }; 116 }; 117 118 cpu3: cpu@300 { 119 device_type = "cpu"; 120 compatible = "arm,cortex-a55"; 121 reg = <0x0 0x300>; 122 clocks = <&cpufreq_hw 0>; 123 enable-method = "psci"; 124 next-level-cache = <&l2_300>; 125 qcom,freq-domain = <&cpufreq_hw 0>; 126 power-domains = <&cpu_pd3>; 127 power-domain-names = "psci"; 128 #cooling-cells = <2>; 129 l2_300: l2-cache { 130 compatible = "cache"; 131 cache-level = <2>; 132 cache-unified; 133 next-level-cache = <&l3_0>; 134 }; 135 }; 136 137 cpu4: cpu@400 { 138 device_type = "cpu"; 139 compatible = "arm,cortex-a78"; 140 reg = <0x0 0x400>; 141 clocks = <&cpufreq_hw 1>; 142 enable-method = "psci"; 143 next-level-cache = <&l2_400>; 144 qcom,freq-domain = <&cpufreq_hw 1>; 145 power-domains = <&cpu_pd4>; 146 power-domain-names = "psci"; 147 #cooling-cells = <2>; 148 l2_400: l2-cache { 149 compatible = "cache"; 150 cache-level = <2>; 151 cache-unified; 152 next-level-cache = <&l3_0>; 153 }; 154 }; 155 156 cpu5: cpu@500 { 157 device_type = "cpu"; 158 compatible = "arm,cortex-a78"; 159 reg = <0x0 0x500>; 160 clocks = <&cpufreq_hw 1>; 161 enable-method = "psci"; 162 next-level-cache = <&l2_500>; 163 qcom,freq-domain = <&cpufreq_hw 1>; 164 power-domains = <&cpu_pd5>; 165 power-domain-names = "psci"; 166 #cooling-cells = <2>; 167 l2_500: l2-cache { 168 compatible = "cache"; 169 cache-level = <2>; 170 cache-unified; 171 next-level-cache = <&l3_0>; 172 }; 173 }; 174 175 cpu6: cpu@600 { 176 device_type = "cpu"; 177 compatible = "arm,cortex-a78"; 178 reg = <0x0 0x600>; 179 clocks = <&cpufreq_hw 1>; 180 enable-method = "psci"; 181 next-level-cache = <&l2_600>; 182 qcom,freq-domain = <&cpufreq_hw 1>; 183 power-domains = <&cpu_pd6>; 184 power-domain-names = "psci"; 185 #cooling-cells = <2>; 186 l2_600: l2-cache { 187 compatible = "cache"; 188 cache-level = <2>; 189 cache-unified; 190 next-level-cache = <&l3_0>; 191 }; 192 }; 193 194 cpu7: cpu@700 { 195 device_type = "cpu"; 196 compatible = "arm,cortex-x1"; 197 reg = <0x0 0x700>; 198 clocks = <&cpufreq_hw 2>; 199 enable-method = "psci"; 200 next-level-cache = <&l2_700>; 201 qcom,freq-domain = <&cpufreq_hw 2>; 202 power-domains = <&cpu_pd7>; 203 power-domain-names = "psci"; 204 #cooling-cells = <2>; 205 l2_700: l2-cache { 206 compatible = "cache"; 207 cache-level = <2>; 208 cache-unified; 209 next-level-cache = <&l3_0>; 210 }; 211 }; 212 213 cpu-map { 214 cluster0 { 215 core0 { 216 cpu = <&cpu0>; 217 }; 218 219 core1 { 220 cpu = <&cpu1>; 221 }; 222 223 core2 { 224 cpu = <&cpu2>; 225 }; 226 227 core3 { 228 cpu = <&cpu3>; 229 }; 230 231 core4 { 232 cpu = <&cpu4>; 233 }; 234 235 core5 { 236 cpu = <&cpu5>; 237 }; 238 239 core6 { 240 cpu = <&cpu6>; 241 }; 242 243 core7 { 244 cpu = <&cpu7>; 245 }; 246 }; 247 }; 248 249 idle-states { 250 entry-method = "psci"; 251 252 little_cpu_sleep_0: cpu-sleep-0-0 { 253 compatible = "arm,idle-state"; 254 idle-state-name = "silver-rail-power-collapse"; 255 arm,psci-suspend-param = <0x40000004>; 256 entry-latency-us = <360>; 257 exit-latency-us = <531>; 258 min-residency-us = <3934>; 259 local-timer-stop; 260 }; 261 262 big_cpu_sleep_0: cpu-sleep-1-0 { 263 compatible = "arm,idle-state"; 264 idle-state-name = "gold-rail-power-collapse"; 265 arm,psci-suspend-param = <0x40000004>; 266 entry-latency-us = <702>; 267 exit-latency-us = <1061>; 268 min-residency-us = <4488>; 269 local-timer-stop; 270 }; 271 }; 272 273 domain-idle-states { 274 cluster_sleep_apss_off: cluster-sleep-0 { 275 compatible = "domain-idle-state"; 276 arm,psci-suspend-param = <0x41000044>; 277 entry-latency-us = <2752>; 278 exit-latency-us = <3048>; 279 min-residency-us = <6118>; 280 }; 281 282 cluster_sleep_aoss_sleep: cluster-sleep-1 { 283 compatible = "domain-idle-state"; 284 arm,psci-suspend-param = <0x4100c344>; 285 entry-latency-us = <3263>; 286 exit-latency-us = <6562>; 287 min-residency-us = <9987>; 288 }; 289 }; 290 }; 291 292 firmware { 293 scm: scm { 294 compatible = "qcom,scm-sm8350", "qcom,scm"; 295 qcom,dload-mode = <&tcsr 0x13000>; 296 #reset-cells = <1>; 297 }; 298 }; 299 300 memory@80000000 { 301 device_type = "memory"; 302 /* We expect the bootloader to fill in the size */ 303 reg = <0x0 0x80000000 0x0 0x0>; 304 }; 305 306 pmu-a55 { 307 compatible = "arm,cortex-a55-pmu"; 308 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 309 }; 310 311 pmu-a78 { 312 compatible = "arm,cortex-a78-pmu"; 313 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 314 }; 315 316 pmu-x1 { 317 compatible = "arm,cortex-x1-pmu"; 318 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 319 }; 320 321 psci { 322 compatible = "arm,psci-1.0"; 323 method = "smc"; 324 325 cpu_pd0: power-domain-cpu0 { 326 #power-domain-cells = <0>; 327 power-domains = <&cluster_pd>; 328 domain-idle-states = <&little_cpu_sleep_0>; 329 }; 330 331 cpu_pd1: power-domain-cpu1 { 332 #power-domain-cells = <0>; 333 power-domains = <&cluster_pd>; 334 domain-idle-states = <&little_cpu_sleep_0>; 335 }; 336 337 cpu_pd2: power-domain-cpu2 { 338 #power-domain-cells = <0>; 339 power-domains = <&cluster_pd>; 340 domain-idle-states = <&little_cpu_sleep_0>; 341 }; 342 343 cpu_pd3: power-domain-cpu3 { 344 #power-domain-cells = <0>; 345 power-domains = <&cluster_pd>; 346 domain-idle-states = <&little_cpu_sleep_0>; 347 }; 348 349 cpu_pd4: power-domain-cpu4 { 350 #power-domain-cells = <0>; 351 power-domains = <&cluster_pd>; 352 domain-idle-states = <&big_cpu_sleep_0>; 353 }; 354 355 cpu_pd5: power-domain-cpu5 { 356 #power-domain-cells = <0>; 357 power-domains = <&cluster_pd>; 358 domain-idle-states = <&big_cpu_sleep_0>; 359 }; 360 361 cpu_pd6: power-domain-cpu6 { 362 #power-domain-cells = <0>; 363 power-domains = <&cluster_pd>; 364 domain-idle-states = <&big_cpu_sleep_0>; 365 }; 366 367 cpu_pd7: power-domain-cpu7 { 368 #power-domain-cells = <0>; 369 power-domains = <&cluster_pd>; 370 domain-idle-states = <&big_cpu_sleep_0>; 371 }; 372 373 cluster_pd: power-domain-cpu-cluster0 { 374 #power-domain-cells = <0>; 375 domain-idle-states = <&cluster_sleep_apss_off &cluster_sleep_aoss_sleep>; 376 }; 377 }; 378 379 qup_opp_table_100mhz: opp-table-qup100mhz { 380 compatible = "operating-points-v2"; 381 382 opp-50000000 { 383 opp-hz = /bits/ 64 <50000000>; 384 required-opps = <&rpmhpd_opp_min_svs>; 385 }; 386 387 opp-75000000 { 388 opp-hz = /bits/ 64 <75000000>; 389 required-opps = <&rpmhpd_opp_low_svs>; 390 }; 391 392 opp-100000000 { 393 opp-hz = /bits/ 64 <100000000>; 394 required-opps = <&rpmhpd_opp_svs>; 395 }; 396 }; 397 398 qup_opp_table_120mhz: opp-table-qup120mhz { 399 compatible = "operating-points-v2"; 400 401 opp-50000000 { 402 opp-hz = /bits/ 64 <50000000>; 403 required-opps = <&rpmhpd_opp_min_svs>; 404 }; 405 406 opp-75000000 { 407 opp-hz = /bits/ 64 <75000000>; 408 required-opps = <&rpmhpd_opp_low_svs>; 409 }; 410 411 opp-120000000 { 412 opp-hz = /bits/ 64 <120000000>; 413 required-opps = <&rpmhpd_opp_svs>; 414 }; 415 }; 416 417 reserved_memory: reserved-memory { 418 #address-cells = <2>; 419 #size-cells = <2>; 420 ranges; 421 422 hyp_mem: memory@80000000 { 423 reg = <0x0 0x80000000 0x0 0x600000>; 424 no-map; 425 }; 426 427 xbl_aop_mem: memory@80700000 { 428 no-map; 429 reg = <0x0 0x80700000 0x0 0x160000>; 430 }; 431 432 cmd_db: memory@80860000 { 433 compatible = "qcom,cmd-db"; 434 reg = <0x0 0x80860000 0x0 0x20000>; 435 no-map; 436 }; 437 438 reserved_xbl_uefi_log: memory@80880000 { 439 reg = <0x0 0x80880000 0x0 0x14000>; 440 no-map; 441 }; 442 443 smem@80900000 { 444 compatible = "qcom,smem"; 445 reg = <0x0 0x80900000 0x0 0x200000>; 446 hwlocks = <&tcsr_mutex 3>; 447 no-map; 448 }; 449 450 cpucp_fw_mem: memory@80b00000 { 451 reg = <0x0 0x80b00000 0x0 0x100000>; 452 no-map; 453 }; 454 455 cdsp_secure_heap: memory@80c00000 { 456 reg = <0x0 0x80c00000 0x0 0x4600000>; 457 no-map; 458 }; 459 460 pil_camera_mem: memory@85200000 { 461 reg = <0x0 0x85200000 0x0 0x500000>; 462 no-map; 463 }; 464 465 pil_video_mem: memory@85700000 { 466 reg = <0x0 0x85700000 0x0 0x500000>; 467 no-map; 468 }; 469 470 pil_cvp_mem: memory@85c00000 { 471 reg = <0x0 0x85c00000 0x0 0x500000>; 472 no-map; 473 }; 474 475 pil_adsp_mem: memory@86100000 { 476 reg = <0x0 0x86100000 0x0 0x2100000>; 477 no-map; 478 }; 479 480 pil_slpi_mem: memory@88200000 { 481 reg = <0x0 0x88200000 0x0 0x1500000>; 482 no-map; 483 }; 484 485 pil_cdsp_mem: memory@89700000 { 486 reg = <0x0 0x89700000 0x0 0x1e00000>; 487 no-map; 488 }; 489 490 pil_ipa_fw_mem: memory@8b500000 { 491 reg = <0x0 0x8b500000 0x0 0x10000>; 492 no-map; 493 }; 494 495 pil_ipa_gsi_mem: memory@8b510000 { 496 reg = <0x0 0x8b510000 0x0 0xa000>; 497 no-map; 498 }; 499 500 pil_gpu_mem: memory@8b51a000 { 501 reg = <0x0 0x8b51a000 0x0 0x2000>; 502 no-map; 503 }; 504 505 pil_spss_mem: memory@8b600000 { 506 reg = <0x0 0x8b600000 0x0 0x100000>; 507 no-map; 508 }; 509 510 pil_modem_mem: memory@8b800000 { 511 reg = <0x0 0x8b800000 0x0 0x10000000>; 512 no-map; 513 }; 514 515 rmtfs_mem: memory@9b800000 { 516 compatible = "qcom,rmtfs-mem"; 517 reg = <0x0 0x9b800000 0x0 0x280000>; 518 no-map; 519 520 qcom,client-id = <1>; 521 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 522 }; 523 524 hyp_reserved_mem: memory@d0000000 { 525 reg = <0x0 0xd0000000 0x0 0x800000>; 526 no-map; 527 }; 528 529 pil_trustedvm_mem: memory@d0800000 { 530 reg = <0x0 0xd0800000 0x0 0x76f7000>; 531 no-map; 532 }; 533 534 qrtr_shbuf: memory@d7ef7000 { 535 reg = <0x0 0xd7ef7000 0x0 0x9000>; 536 no-map; 537 }; 538 539 chan0_shbuf: memory@d7f00000 { 540 reg = <0x0 0xd7f00000 0x0 0x80000>; 541 no-map; 542 }; 543 544 chan1_shbuf: memory@d7f80000 { 545 reg = <0x0 0xd7f80000 0x0 0x80000>; 546 no-map; 547 }; 548 549 removed_mem: memory@d8800000 { 550 reg = <0x0 0xd8800000 0x0 0x6800000>; 551 no-map; 552 }; 553 }; 554 555 smp2p-adsp { 556 compatible = "qcom,smp2p"; 557 qcom,smem = <443>, <429>; 558 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 559 IPCC_MPROC_SIGNAL_SMP2P 560 IRQ_TYPE_EDGE_RISING>; 561 mboxes = <&ipcc IPCC_CLIENT_LPASS 562 IPCC_MPROC_SIGNAL_SMP2P>; 563 564 qcom,local-pid = <0>; 565 qcom,remote-pid = <2>; 566 567 smp2p_adsp_out: master-kernel { 568 qcom,entry-name = "master-kernel"; 569 #qcom,smem-state-cells = <1>; 570 }; 571 572 smp2p_adsp_in: slave-kernel { 573 qcom,entry-name = "slave-kernel"; 574 interrupt-controller; 575 #interrupt-cells = <2>; 576 }; 577 }; 578 579 smp2p-cdsp { 580 compatible = "qcom,smp2p"; 581 qcom,smem = <94>, <432>; 582 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 583 IPCC_MPROC_SIGNAL_SMP2P 584 IRQ_TYPE_EDGE_RISING>; 585 mboxes = <&ipcc IPCC_CLIENT_CDSP 586 IPCC_MPROC_SIGNAL_SMP2P>; 587 588 qcom,local-pid = <0>; 589 qcom,remote-pid = <5>; 590 591 smp2p_cdsp_out: master-kernel { 592 qcom,entry-name = "master-kernel"; 593 #qcom,smem-state-cells = <1>; 594 }; 595 596 smp2p_cdsp_in: slave-kernel { 597 qcom,entry-name = "slave-kernel"; 598 interrupt-controller; 599 #interrupt-cells = <2>; 600 }; 601 }; 602 603 smp2p-modem { 604 compatible = "qcom,smp2p"; 605 qcom,smem = <435>, <428>; 606 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 607 IPCC_MPROC_SIGNAL_SMP2P 608 IRQ_TYPE_EDGE_RISING>; 609 mboxes = <&ipcc IPCC_CLIENT_MPSS 610 IPCC_MPROC_SIGNAL_SMP2P>; 611 612 qcom,local-pid = <0>; 613 qcom,remote-pid = <1>; 614 615 smp2p_modem_out: master-kernel { 616 qcom,entry-name = "master-kernel"; 617 #qcom,smem-state-cells = <1>; 618 }; 619 620 smp2p_modem_in: slave-kernel { 621 qcom,entry-name = "slave-kernel"; 622 interrupt-controller; 623 #interrupt-cells = <2>; 624 }; 625 626 ipa_smp2p_out: ipa-ap-to-modem { 627 qcom,entry-name = "ipa"; 628 #qcom,smem-state-cells = <1>; 629 }; 630 631 ipa_smp2p_in: ipa-modem-to-ap { 632 qcom,entry-name = "ipa"; 633 interrupt-controller; 634 #interrupt-cells = <2>; 635 }; 636 }; 637 638 smp2p-slpi { 639 compatible = "qcom,smp2p"; 640 qcom,smem = <481>, <430>; 641 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 642 IPCC_MPROC_SIGNAL_SMP2P 643 IRQ_TYPE_EDGE_RISING>; 644 mboxes = <&ipcc IPCC_CLIENT_SLPI 645 IPCC_MPROC_SIGNAL_SMP2P>; 646 647 qcom,local-pid = <0>; 648 qcom,remote-pid = <3>; 649 650 smp2p_slpi_out: master-kernel { 651 qcom,entry-name = "master-kernel"; 652 #qcom,smem-state-cells = <1>; 653 }; 654 655 smp2p_slpi_in: slave-kernel { 656 qcom,entry-name = "slave-kernel"; 657 interrupt-controller; 658 #interrupt-cells = <2>; 659 }; 660 }; 661 662 soc: soc@0 { 663 #address-cells = <2>; 664 #size-cells = <2>; 665 ranges = <0 0 0 0 0x10 0>; 666 dma-ranges = <0 0 0 0 0x10 0>; 667 compatible = "simple-bus"; 668 669 gcc: clock-controller@100000 { 670 compatible = "qcom,gcc-sm8350"; 671 reg = <0x0 0x00100000 0x0 0x1f0000>; 672 #clock-cells = <1>; 673 #reset-cells = <1>; 674 #power-domain-cells = <1>; 675 clock-names = "bi_tcxo", 676 "sleep_clk", 677 "pcie_0_pipe_clk", 678 "pcie_1_pipe_clk", 679 "ufs_card_rx_symbol_0_clk", 680 "ufs_card_rx_symbol_1_clk", 681 "ufs_card_tx_symbol_0_clk", 682 "ufs_phy_rx_symbol_0_clk", 683 "ufs_phy_rx_symbol_1_clk", 684 "ufs_phy_tx_symbol_0_clk", 685 "usb3_phy_wrapper_gcc_usb30_pipe_clk", 686 "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; 687 clocks = <&rpmhcc RPMH_CXO_CLK>, 688 <&sleep_clk>, 689 <&pcie0_phy>, 690 <&pcie1_phy>, 691 <0>, 692 <0>, 693 <0>, 694 <&ufs_mem_phy 0>, 695 <&ufs_mem_phy 1>, 696 <&ufs_mem_phy 2>, 697 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 698 <0>; 699 }; 700 701 ipcc: mailbox@408000 { 702 compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; 703 reg = <0 0x00408000 0 0x1000>; 704 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 705 interrupt-controller; 706 #interrupt-cells = <3>; 707 #mbox-cells = <2>; 708 }; 709 710 gpi_dma2: dma-controller@800000 { 711 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 712 reg = <0 0x00800000 0 0x60000>; 713 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 725 dma-channels = <12>; 726 dma-channel-mask = <0xff>; 727 iommus = <&apps_smmu 0x5f6 0x0>; 728 #dma-cells = <3>; 729 status = "disabled"; 730 }; 731 732 qupv3_id_2: geniqup@8c0000 { 733 compatible = "qcom,geni-se-qup"; 734 reg = <0x0 0x008c0000 0x0 0x6000>; 735 clock-names = "m-ahb", "s-ahb"; 736 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 737 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 738 iommus = <&apps_smmu 0x5e3 0x0>; 739 #address-cells = <2>; 740 #size-cells = <2>; 741 ranges; 742 status = "disabled"; 743 744 i2c14: i2c@880000 { 745 compatible = "qcom,geni-i2c"; 746 reg = <0 0x00880000 0 0x4000>; 747 clock-names = "se"; 748 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 749 pinctrl-names = "default"; 750 pinctrl-0 = <&qup_i2c14_default>; 751 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 752 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 753 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 754 dma-names = "tx", "rx"; 755 #address-cells = <1>; 756 #size-cells = <0>; 757 status = "disabled"; 758 }; 759 760 spi14: spi@880000 { 761 compatible = "qcom,geni-spi"; 762 reg = <0 0x00880000 0 0x4000>; 763 clock-names = "se"; 764 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 765 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 766 power-domains = <&rpmhpd RPMHPD_CX>; 767 operating-points-v2 = <&qup_opp_table_120mhz>; 768 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 769 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 770 dma-names = "tx", "rx"; 771 #address-cells = <1>; 772 #size-cells = <0>; 773 status = "disabled"; 774 }; 775 776 i2c15: i2c@884000 { 777 compatible = "qcom,geni-i2c"; 778 reg = <0 0x00884000 0 0x4000>; 779 clock-names = "se"; 780 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 781 pinctrl-names = "default"; 782 pinctrl-0 = <&qup_i2c15_default>; 783 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 784 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 785 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 786 dma-names = "tx", "rx"; 787 #address-cells = <1>; 788 #size-cells = <0>; 789 status = "disabled"; 790 }; 791 792 spi15: spi@884000 { 793 compatible = "qcom,geni-spi"; 794 reg = <0 0x00884000 0 0x4000>; 795 clock-names = "se"; 796 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 797 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 798 power-domains = <&rpmhpd RPMHPD_CX>; 799 operating-points-v2 = <&qup_opp_table_120mhz>; 800 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 801 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 802 dma-names = "tx", "rx"; 803 #address-cells = <1>; 804 #size-cells = <0>; 805 status = "disabled"; 806 }; 807 808 i2c16: i2c@888000 { 809 compatible = "qcom,geni-i2c"; 810 reg = <0 0x00888000 0 0x4000>; 811 clock-names = "se"; 812 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 813 pinctrl-names = "default"; 814 pinctrl-0 = <&qup_i2c16_default>; 815 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 816 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 817 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 818 dma-names = "tx", "rx"; 819 #address-cells = <1>; 820 #size-cells = <0>; 821 status = "disabled"; 822 }; 823 824 spi16: spi@888000 { 825 compatible = "qcom,geni-spi"; 826 reg = <0 0x00888000 0 0x4000>; 827 clock-names = "se"; 828 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 829 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 830 power-domains = <&rpmhpd RPMHPD_CX>; 831 operating-points-v2 = <&qup_opp_table_100mhz>; 832 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 833 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 834 dma-names = "tx", "rx"; 835 #address-cells = <1>; 836 #size-cells = <0>; 837 status = "disabled"; 838 }; 839 840 i2c17: i2c@88c000 { 841 compatible = "qcom,geni-i2c"; 842 reg = <0 0x0088c000 0 0x4000>; 843 clock-names = "se"; 844 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 845 pinctrl-names = "default"; 846 pinctrl-0 = <&qup_i2c17_default>; 847 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 848 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 849 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 850 dma-names = "tx", "rx"; 851 #address-cells = <1>; 852 #size-cells = <0>; 853 status = "disabled"; 854 }; 855 856 spi17: spi@88c000 { 857 compatible = "qcom,geni-spi"; 858 reg = <0 0x0088c000 0 0x4000>; 859 clock-names = "se"; 860 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 861 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 862 power-domains = <&rpmhpd RPMHPD_CX>; 863 operating-points-v2 = <&qup_opp_table_100mhz>; 864 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 865 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 866 dma-names = "tx", "rx"; 867 #address-cells = <1>; 868 #size-cells = <0>; 869 status = "disabled"; 870 }; 871 872 /* QUP no. 18 seems to be strictly SPI/UART-only */ 873 874 spi18: spi@890000 { 875 compatible = "qcom,geni-spi"; 876 reg = <0 0x00890000 0 0x4000>; 877 clock-names = "se"; 878 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 879 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 880 power-domains = <&rpmhpd RPMHPD_CX>; 881 operating-points-v2 = <&qup_opp_table_100mhz>; 882 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 883 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 884 dma-names = "tx", "rx"; 885 #address-cells = <1>; 886 #size-cells = <0>; 887 status = "disabled"; 888 }; 889 890 uart18: serial@890000 { 891 compatible = "qcom,geni-uart"; 892 reg = <0 0x00890000 0 0x4000>; 893 clock-names = "se"; 894 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 895 pinctrl-names = "default"; 896 pinctrl-0 = <&qup_uart18_default>; 897 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 898 power-domains = <&rpmhpd RPMHPD_CX>; 899 operating-points-v2 = <&qup_opp_table_100mhz>; 900 status = "disabled"; 901 }; 902 903 i2c19: i2c@894000 { 904 compatible = "qcom,geni-i2c"; 905 reg = <0 0x00894000 0 0x4000>; 906 clock-names = "se"; 907 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 908 pinctrl-names = "default"; 909 pinctrl-0 = <&qup_i2c19_default>; 910 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 911 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 912 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 913 dma-names = "tx", "rx"; 914 #address-cells = <1>; 915 #size-cells = <0>; 916 status = "disabled"; 917 }; 918 919 spi19: spi@894000 { 920 compatible = "qcom,geni-spi"; 921 reg = <0 0x00894000 0 0x4000>; 922 clock-names = "se"; 923 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 924 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 925 power-domains = <&rpmhpd RPMHPD_CX>; 926 operating-points-v2 = <&qup_opp_table_100mhz>; 927 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 928 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 929 dma-names = "tx", "rx"; 930 #address-cells = <1>; 931 #size-cells = <0>; 932 status = "disabled"; 933 }; 934 }; 935 936 gpi_dma0: dma-controller@900000 { 937 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 938 reg = <0 0x00900000 0 0x60000>; 939 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 951 dma-channels = <12>; 952 dma-channel-mask = <0x7e>; 953 iommus = <&apps_smmu 0x5b6 0x0>; 954 #dma-cells = <3>; 955 status = "disabled"; 956 }; 957 958 qupv3_id_0: geniqup@9c0000 { 959 compatible = "qcom,geni-se-qup"; 960 reg = <0x0 0x009c0000 0x0 0x6000>; 961 clock-names = "m-ahb", "s-ahb"; 962 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 963 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 964 iommus = <&apps_smmu 0x5a3 0>; 965 #address-cells = <2>; 966 #size-cells = <2>; 967 ranges; 968 status = "disabled"; 969 970 i2c0: i2c@980000 { 971 compatible = "qcom,geni-i2c"; 972 reg = <0 0x00980000 0 0x4000>; 973 clock-names = "se"; 974 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 975 pinctrl-names = "default"; 976 pinctrl-0 = <&qup_i2c0_default>; 977 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 978 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 979 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 980 dma-names = "tx", "rx"; 981 #address-cells = <1>; 982 #size-cells = <0>; 983 status = "disabled"; 984 }; 985 986 spi0: spi@980000 { 987 compatible = "qcom,geni-spi"; 988 reg = <0 0x00980000 0 0x4000>; 989 clock-names = "se"; 990 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 991 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 992 power-domains = <&rpmhpd RPMHPD_CX>; 993 operating-points-v2 = <&qup_opp_table_100mhz>; 994 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 995 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 996 dma-names = "tx", "rx"; 997 #address-cells = <1>; 998 #size-cells = <0>; 999 status = "disabled"; 1000 }; 1001 1002 i2c1: i2c@984000 { 1003 compatible = "qcom,geni-i2c"; 1004 reg = <0 0x00984000 0 0x4000>; 1005 clock-names = "se"; 1006 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1007 pinctrl-names = "default"; 1008 pinctrl-0 = <&qup_i2c1_default>; 1009 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1010 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1011 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1012 dma-names = "tx", "rx"; 1013 #address-cells = <1>; 1014 #size-cells = <0>; 1015 status = "disabled"; 1016 }; 1017 1018 spi1: spi@984000 { 1019 compatible = "qcom,geni-spi"; 1020 reg = <0 0x00984000 0 0x4000>; 1021 clock-names = "se"; 1022 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1023 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1024 power-domains = <&rpmhpd RPMHPD_CX>; 1025 operating-points-v2 = <&qup_opp_table_100mhz>; 1026 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1027 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1028 dma-names = "tx", "rx"; 1029 #address-cells = <1>; 1030 #size-cells = <0>; 1031 status = "disabled"; 1032 }; 1033 1034 i2c2: i2c@988000 { 1035 compatible = "qcom,geni-i2c"; 1036 reg = <0 0x00988000 0 0x4000>; 1037 clock-names = "se"; 1038 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1039 pinctrl-names = "default"; 1040 pinctrl-0 = <&qup_i2c2_default>; 1041 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1042 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1043 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1044 dma-names = "tx", "rx"; 1045 #address-cells = <1>; 1046 #size-cells = <0>; 1047 status = "disabled"; 1048 }; 1049 1050 spi2: spi@988000 { 1051 compatible = "qcom,geni-spi"; 1052 reg = <0 0x00988000 0 0x4000>; 1053 clock-names = "se"; 1054 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1055 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1056 power-domains = <&rpmhpd RPMHPD_CX>; 1057 operating-points-v2 = <&qup_opp_table_100mhz>; 1058 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1059 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1060 dma-names = "tx", "rx"; 1061 #address-cells = <1>; 1062 #size-cells = <0>; 1063 status = "disabled"; 1064 }; 1065 1066 uart2: serial@98c000 { 1067 compatible = "qcom,geni-debug-uart"; 1068 reg = <0 0x0098c000 0 0x4000>; 1069 clock-names = "se"; 1070 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1071 pinctrl-names = "default"; 1072 pinctrl-0 = <&qup_uart3_default_state>; 1073 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1074 power-domains = <&rpmhpd RPMHPD_CX>; 1075 operating-points-v2 = <&qup_opp_table_100mhz>; 1076 status = "disabled"; 1077 }; 1078 1079 /* QUP no. 3 seems to be strictly SPI-only */ 1080 1081 spi3: spi@98c000 { 1082 compatible = "qcom,geni-spi"; 1083 reg = <0 0x0098c000 0 0x4000>; 1084 clock-names = "se"; 1085 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1086 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1087 power-domains = <&rpmhpd RPMHPD_CX>; 1088 operating-points-v2 = <&qup_opp_table_100mhz>; 1089 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1090 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1091 dma-names = "tx", "rx"; 1092 #address-cells = <1>; 1093 #size-cells = <0>; 1094 status = "disabled"; 1095 }; 1096 1097 i2c4: i2c@990000 { 1098 compatible = "qcom,geni-i2c"; 1099 reg = <0 0x00990000 0 0x4000>; 1100 clock-names = "se"; 1101 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1102 pinctrl-names = "default"; 1103 pinctrl-0 = <&qup_i2c4_default>; 1104 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1105 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1106 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1107 dma-names = "tx", "rx"; 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 status = "disabled"; 1111 }; 1112 1113 spi4: spi@990000 { 1114 compatible = "qcom,geni-spi"; 1115 reg = <0 0x00990000 0 0x4000>; 1116 clock-names = "se"; 1117 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1118 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1119 power-domains = <&rpmhpd RPMHPD_CX>; 1120 operating-points-v2 = <&qup_opp_table_100mhz>; 1121 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1122 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1123 dma-names = "tx", "rx"; 1124 #address-cells = <1>; 1125 #size-cells = <0>; 1126 status = "disabled"; 1127 }; 1128 1129 i2c5: i2c@994000 { 1130 compatible = "qcom,geni-i2c"; 1131 reg = <0 0x00994000 0 0x4000>; 1132 clock-names = "se"; 1133 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1134 pinctrl-names = "default"; 1135 pinctrl-0 = <&qup_i2c5_default>; 1136 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1137 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1138 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1139 dma-names = "tx", "rx"; 1140 #address-cells = <1>; 1141 #size-cells = <0>; 1142 status = "disabled"; 1143 }; 1144 1145 spi5: spi@994000 { 1146 compatible = "qcom,geni-spi"; 1147 reg = <0 0x00994000 0 0x4000>; 1148 clock-names = "se"; 1149 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1150 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1151 power-domains = <&rpmhpd RPMHPD_CX>; 1152 operating-points-v2 = <&qup_opp_table_100mhz>; 1153 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1154 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1155 dma-names = "tx", "rx"; 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 status = "disabled"; 1159 }; 1160 1161 i2c6: i2c@998000 { 1162 compatible = "qcom,geni-i2c"; 1163 reg = <0 0x00998000 0 0x4000>; 1164 clock-names = "se"; 1165 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1166 pinctrl-names = "default"; 1167 pinctrl-0 = <&qup_i2c6_default>; 1168 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1169 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1170 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1171 dma-names = "tx", "rx"; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 status = "disabled"; 1175 }; 1176 1177 spi6: spi@998000 { 1178 compatible = "qcom,geni-spi"; 1179 reg = <0 0x00998000 0 0x4000>; 1180 clock-names = "se"; 1181 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1182 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1183 power-domains = <&rpmhpd RPMHPD_CX>; 1184 operating-points-v2 = <&qup_opp_table_100mhz>; 1185 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1186 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1187 dma-names = "tx", "rx"; 1188 #address-cells = <1>; 1189 #size-cells = <0>; 1190 status = "disabled"; 1191 }; 1192 1193 uart6: serial@998000 { 1194 compatible = "qcom,geni-uart"; 1195 reg = <0 0x00998000 0 0x4000>; 1196 clock-names = "se"; 1197 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1198 pinctrl-names = "default"; 1199 pinctrl-0 = <&qup_uart6_default>; 1200 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1201 power-domains = <&rpmhpd RPMHPD_CX>; 1202 operating-points-v2 = <&qup_opp_table_100mhz>; 1203 status = "disabled"; 1204 }; 1205 1206 i2c7: i2c@99c000 { 1207 compatible = "qcom,geni-i2c"; 1208 reg = <0 0x0099c000 0 0x4000>; 1209 clock-names = "se"; 1210 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1211 pinctrl-names = "default"; 1212 pinctrl-0 = <&qup_i2c7_default>; 1213 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1214 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1215 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1216 dma-names = "tx", "rx"; 1217 #address-cells = <1>; 1218 #size-cells = <0>; 1219 status = "disabled"; 1220 }; 1221 1222 spi7: spi@99c000 { 1223 compatible = "qcom,geni-spi"; 1224 reg = <0 0x0099c000 0 0x4000>; 1225 clock-names = "se"; 1226 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1227 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1228 power-domains = <&rpmhpd RPMHPD_CX>; 1229 operating-points-v2 = <&qup_opp_table_100mhz>; 1230 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1231 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1232 dma-names = "tx", "rx"; 1233 #address-cells = <1>; 1234 #size-cells = <0>; 1235 status = "disabled"; 1236 }; 1237 }; 1238 1239 gpi_dma1: dma-controller@a00000 { 1240 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 1241 reg = <0 0x00a00000 0 0x60000>; 1242 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1254 dma-channels = <12>; 1255 dma-channel-mask = <0xff>; 1256 iommus = <&apps_smmu 0x56 0x0>; 1257 #dma-cells = <3>; 1258 status = "disabled"; 1259 }; 1260 1261 qupv3_id_1: geniqup@ac0000 { 1262 compatible = "qcom,geni-se-qup"; 1263 reg = <0x0 0x00ac0000 0x0 0x6000>; 1264 clock-names = "m-ahb", "s-ahb"; 1265 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1266 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1267 iommus = <&apps_smmu 0x43 0>; 1268 #address-cells = <2>; 1269 #size-cells = <2>; 1270 ranges; 1271 status = "disabled"; 1272 1273 i2c8: i2c@a80000 { 1274 compatible = "qcom,geni-i2c"; 1275 reg = <0 0x00a80000 0 0x4000>; 1276 clock-names = "se"; 1277 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1278 pinctrl-names = "default"; 1279 pinctrl-0 = <&qup_i2c8_default>; 1280 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1281 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1282 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1283 dma-names = "tx", "rx"; 1284 #address-cells = <1>; 1285 #size-cells = <0>; 1286 status = "disabled"; 1287 }; 1288 1289 spi8: spi@a80000 { 1290 compatible = "qcom,geni-spi"; 1291 reg = <0 0x00a80000 0 0x4000>; 1292 clock-names = "se"; 1293 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1294 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1295 power-domains = <&rpmhpd RPMHPD_CX>; 1296 operating-points-v2 = <&qup_opp_table_120mhz>; 1297 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1298 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1299 dma-names = "tx", "rx"; 1300 #address-cells = <1>; 1301 #size-cells = <0>; 1302 status = "disabled"; 1303 }; 1304 1305 i2c9: i2c@a84000 { 1306 compatible = "qcom,geni-i2c"; 1307 reg = <0 0x00a84000 0 0x4000>; 1308 clock-names = "se"; 1309 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1310 pinctrl-names = "default"; 1311 pinctrl-0 = <&qup_i2c9_default>; 1312 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1313 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1314 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1315 dma-names = "tx", "rx"; 1316 #address-cells = <1>; 1317 #size-cells = <0>; 1318 status = "disabled"; 1319 }; 1320 1321 spi9: spi@a84000 { 1322 compatible = "qcom,geni-spi"; 1323 reg = <0 0x00a84000 0 0x4000>; 1324 clock-names = "se"; 1325 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1326 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1327 power-domains = <&rpmhpd RPMHPD_CX>; 1328 operating-points-v2 = <&qup_opp_table_100mhz>; 1329 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1330 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1331 dma-names = "tx", "rx"; 1332 #address-cells = <1>; 1333 #size-cells = <0>; 1334 status = "disabled"; 1335 }; 1336 1337 i2c10: i2c@a88000 { 1338 compatible = "qcom,geni-i2c"; 1339 reg = <0 0x00a88000 0 0x4000>; 1340 clock-names = "se"; 1341 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1342 pinctrl-names = "default"; 1343 pinctrl-0 = <&qup_i2c10_default>; 1344 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1345 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1346 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1347 dma-names = "tx", "rx"; 1348 #address-cells = <1>; 1349 #size-cells = <0>; 1350 status = "disabled"; 1351 }; 1352 1353 spi10: spi@a88000 { 1354 compatible = "qcom,geni-spi"; 1355 reg = <0 0x00a88000 0 0x4000>; 1356 clock-names = "se"; 1357 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1358 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1359 power-domains = <&rpmhpd RPMHPD_CX>; 1360 operating-points-v2 = <&qup_opp_table_100mhz>; 1361 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1362 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1363 dma-names = "tx", "rx"; 1364 #address-cells = <1>; 1365 #size-cells = <0>; 1366 status = "disabled"; 1367 }; 1368 1369 i2c11: i2c@a8c000 { 1370 compatible = "qcom,geni-i2c"; 1371 reg = <0 0x00a8c000 0 0x4000>; 1372 clock-names = "se"; 1373 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1374 pinctrl-names = "default"; 1375 pinctrl-0 = <&qup_i2c11_default>; 1376 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1377 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1378 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1379 dma-names = "tx", "rx"; 1380 #address-cells = <1>; 1381 #size-cells = <0>; 1382 status = "disabled"; 1383 }; 1384 1385 spi11: spi@a8c000 { 1386 compatible = "qcom,geni-spi"; 1387 reg = <0 0x00a8c000 0 0x4000>; 1388 clock-names = "se"; 1389 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1390 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1391 power-domains = <&rpmhpd RPMHPD_CX>; 1392 operating-points-v2 = <&qup_opp_table_100mhz>; 1393 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1394 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1395 dma-names = "tx", "rx"; 1396 #address-cells = <1>; 1397 #size-cells = <0>; 1398 status = "disabled"; 1399 }; 1400 1401 i2c12: i2c@a90000 { 1402 compatible = "qcom,geni-i2c"; 1403 reg = <0 0x00a90000 0 0x4000>; 1404 clock-names = "se"; 1405 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1406 pinctrl-names = "default"; 1407 pinctrl-0 = <&qup_i2c12_default>; 1408 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1409 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1410 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1411 dma-names = "tx", "rx"; 1412 #address-cells = <1>; 1413 #size-cells = <0>; 1414 status = "disabled"; 1415 }; 1416 1417 spi12: spi@a90000 { 1418 compatible = "qcom,geni-spi"; 1419 reg = <0 0x00a90000 0 0x4000>; 1420 clock-names = "se"; 1421 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1422 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1423 power-domains = <&rpmhpd RPMHPD_CX>; 1424 operating-points-v2 = <&qup_opp_table_100mhz>; 1425 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1426 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1427 dma-names = "tx", "rx"; 1428 #address-cells = <1>; 1429 #size-cells = <0>; 1430 status = "disabled"; 1431 }; 1432 1433 i2c13: i2c@a94000 { 1434 compatible = "qcom,geni-i2c"; 1435 reg = <0 0x00a94000 0 0x4000>; 1436 clock-names = "se"; 1437 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1438 pinctrl-names = "default"; 1439 pinctrl-0 = <&qup_i2c13_default>; 1440 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1441 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1442 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1443 dma-names = "tx", "rx"; 1444 #address-cells = <1>; 1445 #size-cells = <0>; 1446 status = "disabled"; 1447 }; 1448 1449 spi13: spi@a94000 { 1450 compatible = "qcom,geni-spi"; 1451 reg = <0 0x00a94000 0 0x4000>; 1452 clock-names = "se"; 1453 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1454 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1455 power-domains = <&rpmhpd RPMHPD_CX>; 1456 operating-points-v2 = <&qup_opp_table_100mhz>; 1457 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1458 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1459 dma-names = "tx", "rx"; 1460 #address-cells = <1>; 1461 #size-cells = <0>; 1462 status = "disabled"; 1463 }; 1464 }; 1465 1466 rng: rng@10d3000 { 1467 compatible = "qcom,prng-ee"; 1468 reg = <0 0x010d3000 0 0x1000>; 1469 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1470 clock-names = "core"; 1471 }; 1472 1473 config_noc: interconnect@1500000 { 1474 compatible = "qcom,sm8350-config-noc"; 1475 reg = <0 0x01500000 0 0xa580>; 1476 #interconnect-cells = <2>; 1477 qcom,bcm-voters = <&apps_bcm_voter>; 1478 }; 1479 1480 mc_virt: interconnect@1580000 { 1481 compatible = "qcom,sm8350-mc-virt"; 1482 reg = <0 0x01580000 0 0x1000>; 1483 #interconnect-cells = <2>; 1484 qcom,bcm-voters = <&apps_bcm_voter>; 1485 }; 1486 1487 system_noc: interconnect@1680000 { 1488 compatible = "qcom,sm8350-system-noc"; 1489 reg = <0 0x01680000 0 0x1c200>; 1490 #interconnect-cells = <2>; 1491 qcom,bcm-voters = <&apps_bcm_voter>; 1492 }; 1493 1494 aggre1_noc: interconnect@16e0000 { 1495 compatible = "qcom,sm8350-aggre1-noc"; 1496 reg = <0 0x016e0000 0 0x1f180>; 1497 #interconnect-cells = <2>; 1498 qcom,bcm-voters = <&apps_bcm_voter>; 1499 }; 1500 1501 aggre2_noc: interconnect@1700000 { 1502 compatible = "qcom,sm8350-aggre2-noc"; 1503 reg = <0 0x01700000 0 0x33000>; 1504 #interconnect-cells = <2>; 1505 qcom,bcm-voters = <&apps_bcm_voter>; 1506 }; 1507 1508 mmss_noc: interconnect@1740000 { 1509 compatible = "qcom,sm8350-mmss-noc"; 1510 reg = <0 0x01740000 0 0x1f080>; 1511 #interconnect-cells = <2>; 1512 qcom,bcm-voters = <&apps_bcm_voter>; 1513 }; 1514 1515 pcie0: pcie@1c00000 { 1516 compatible = "qcom,pcie-sm8350"; 1517 reg = <0 0x01c00000 0 0x3000>, 1518 <0 0x60000000 0 0xf1d>, 1519 <0 0x60000f20 0 0xa8>, 1520 <0 0x60001000 0 0x1000>, 1521 <0 0x60100000 0 0x100000>; 1522 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1523 device_type = "pci"; 1524 linux,pci-domain = <0>; 1525 bus-range = <0x00 0xff>; 1526 num-lanes = <1>; 1527 1528 #address-cells = <3>; 1529 #size-cells = <2>; 1530 1531 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1532 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1533 1534 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1540 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1541 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1542 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1543 interrupt-names = "msi0", 1544 "msi1", 1545 "msi2", 1546 "msi3", 1547 "msi4", 1548 "msi5", 1549 "msi6", 1550 "msi7", 1551 "global"; 1552 #interrupt-cells = <1>; 1553 interrupt-map-mask = <0 0 0 0x7>; 1554 interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1555 <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1556 <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1557 <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1558 1559 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1560 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1561 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1562 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1563 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1564 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1565 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1566 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1567 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; 1568 clock-names = "aux", 1569 "cfg", 1570 "bus_master", 1571 "bus_slave", 1572 "slave_q2a", 1573 "tbu", 1574 "ddrss_sf_tbu", 1575 "aggre1", 1576 "aggre0"; 1577 1578 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1579 <0x100 &apps_smmu 0x1c01 0x1>; 1580 1581 resets = <&gcc GCC_PCIE_0_BCR>; 1582 reset-names = "pci"; 1583 1584 power-domains = <&gcc PCIE_0_GDSC>; 1585 1586 phys = <&pcie0_phy>; 1587 phy-names = "pciephy"; 1588 1589 status = "disabled"; 1590 1591 pcie@0 { 1592 device_type = "pci"; 1593 reg = <0x0 0x0 0x0 0x0 0x0>; 1594 bus-range = <0x01 0xff>; 1595 1596 #address-cells = <3>; 1597 #size-cells = <2>; 1598 ranges; 1599 }; 1600 }; 1601 1602 pcie0_phy: phy@1c06000 { 1603 compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy"; 1604 reg = <0 0x01c06000 0 0x2000>; 1605 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1606 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1607 <&gcc GCC_PCIE_0_CLKREF_EN>, 1608 <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, 1609 <&gcc GCC_PCIE_0_PIPE_CLK>; 1610 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1611 1612 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1613 reset-names = "phy"; 1614 1615 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>; 1616 assigned-clock-rates = <100000000>; 1617 1618 #clock-cells = <0>; 1619 clock-output-names = "pcie_0_pipe_clk"; 1620 1621 #phy-cells = <0>; 1622 1623 status = "disabled"; 1624 }; 1625 1626 pcie1: pcie@1c08000 { 1627 compatible = "qcom,pcie-sm8350"; 1628 reg = <0 0x01c08000 0 0x3000>, 1629 <0 0x40000000 0 0xf1d>, 1630 <0 0x40000f20 0 0xa8>, 1631 <0 0x40001000 0 0x1000>, 1632 <0 0x40100000 0 0x100000>; 1633 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1634 device_type = "pci"; 1635 linux,pci-domain = <1>; 1636 bus-range = <0x00 0xff>; 1637 num-lanes = <2>; 1638 1639 #address-cells = <3>; 1640 #size-cells = <2>; 1641 1642 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1643 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1644 1645 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1647 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1648 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1649 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1650 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1651 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 1652 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 1653 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 1654 interrupt-names = "msi0", 1655 "msi1", 1656 "msi2", 1657 "msi3", 1658 "msi4", 1659 "msi5", 1660 "msi6", 1661 "msi7", 1662 "global"; 1663 #interrupt-cells = <1>; 1664 interrupt-map-mask = <0 0 0 0x7>; 1665 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1666 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1667 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1668 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1669 1670 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1671 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1672 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1673 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1674 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1675 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1676 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1677 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1678 clock-names = "aux", 1679 "cfg", 1680 "bus_master", 1681 "bus_slave", 1682 "slave_q2a", 1683 "tbu", 1684 "ddrss_sf_tbu", 1685 "aggre1"; 1686 1687 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1688 <0x100 &apps_smmu 0x1c81 0x1>; 1689 1690 resets = <&gcc GCC_PCIE_1_BCR>; 1691 reset-names = "pci"; 1692 1693 power-domains = <&gcc PCIE_1_GDSC>; 1694 1695 phys = <&pcie1_phy>; 1696 phy-names = "pciephy"; 1697 1698 status = "disabled"; 1699 1700 pcie@0 { 1701 device_type = "pci"; 1702 reg = <0x0 0x0 0x0 0x0 0x0>; 1703 bus-range = <0x01 0xff>; 1704 1705 #address-cells = <3>; 1706 #size-cells = <2>; 1707 ranges; 1708 }; 1709 }; 1710 1711 pcie1_phy: phy@1c0e000 { 1712 compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy"; 1713 reg = <0 0x01c0e000 0 0x2000>; 1714 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1715 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1716 <&gcc GCC_PCIE_1_CLKREF_EN>, 1717 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, 1718 <&gcc GCC_PCIE_1_PIPE_CLK>; 1719 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1720 1721 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1722 reset-names = "phy"; 1723 1724 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1725 assigned-clock-rates = <100000000>; 1726 1727 #clock-cells = <0>; 1728 clock-output-names = "pcie_1_pipe_clk"; 1729 1730 #phy-cells = <0>; 1731 1732 status = "disabled"; 1733 }; 1734 1735 ufs_mem_hc: ufshc@1d84000 { 1736 compatible = "qcom,sm8350-ufshc", "qcom,ufshc", 1737 "jedec,ufs-2.0"; 1738 reg = <0 0x01d84000 0 0x3000>; 1739 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1740 phys = <&ufs_mem_phy>; 1741 phy-names = "ufsphy"; 1742 lanes-per-direction = <2>; 1743 #reset-cells = <1>; 1744 resets = <&gcc GCC_UFS_PHY_BCR>; 1745 reset-names = "rst"; 1746 1747 power-domains = <&gcc UFS_PHY_GDSC>; 1748 1749 iommus = <&apps_smmu 0xe0 0x0>; 1750 dma-coherent; 1751 1752 clock-names = 1753 "core_clk", 1754 "bus_aggr_clk", 1755 "iface_clk", 1756 "core_clk_unipro", 1757 "ref_clk", 1758 "tx_lane0_sync_clk", 1759 "rx_lane0_sync_clk", 1760 "rx_lane1_sync_clk"; 1761 clocks = 1762 <&gcc GCC_UFS_PHY_AXI_CLK>, 1763 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1764 <&gcc GCC_UFS_PHY_AHB_CLK>, 1765 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1766 <&rpmhcc RPMH_CXO_CLK>, 1767 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1768 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1769 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1770 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 1771 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1772 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1773 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 1774 interconnect-names = "ufs-ddr", "cpu-ufs"; 1775 freq-table-hz = 1776 <75000000 300000000>, 1777 <0 0>, 1778 <0 0>, 1779 <75000000 300000000>, 1780 <0 0>, 1781 <0 0>, 1782 <0 0>, 1783 <0 0>; 1784 status = "disabled"; 1785 }; 1786 1787 ufs_mem_phy: phy@1d87000 { 1788 compatible = "qcom,sm8350-qmp-ufs-phy"; 1789 reg = <0 0x01d87000 0 0x1000>; 1790 1791 clocks = <&rpmhcc RPMH_CXO_CLK>, 1792 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1793 <&gcc GCC_UFS_1_CLKREF_EN>; 1794 clock-names = "ref", 1795 "ref_aux", 1796 "qref"; 1797 1798 power-domains = <&gcc UFS_PHY_GDSC>; 1799 1800 resets = <&ufs_mem_hc 0>; 1801 reset-names = "ufsphy"; 1802 1803 #clock-cells = <1>; 1804 #phy-cells = <0>; 1805 1806 status = "disabled"; 1807 }; 1808 1809 cryptobam: dma-controller@1dc4000 { 1810 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1811 reg = <0 0x01dc4000 0 0x24000>; 1812 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1813 #dma-cells = <1>; 1814 qcom,ee = <0>; 1815 qcom,num-ees = <4>; 1816 num-channels = <16>; 1817 qcom,controlled-remotely; 1818 iommus = <&apps_smmu 0x594 0x0011>, 1819 <&apps_smmu 0x596 0x0011>; 1820 }; 1821 1822 crypto: crypto@1dfa000 { 1823 compatible = "qcom,sm8350-qce", "qcom,sm8150-qce", "qcom,qce"; 1824 reg = <0 0x01dfa000 0 0x6000>; 1825 dmas = <&cryptobam 4>, <&cryptobam 5>; 1826 dma-names = "rx", "tx"; 1827 iommus = <&apps_smmu 0x594 0x0011>, 1828 <&apps_smmu 0x596 0x0011>; 1829 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 1830 interconnect-names = "memory"; 1831 }; 1832 1833 ipa: ipa@1e40000 { 1834 compatible = "qcom,sm8350-ipa"; 1835 1836 iommus = <&apps_smmu 0x5c0 0x0>, 1837 <&apps_smmu 0x5c2 0x0>; 1838 reg = <0 0x01e40000 0 0x8000>, 1839 <0 0x01e50000 0 0x4b20>, 1840 <0 0x01e04000 0 0x23000>; 1841 reg-names = "ipa-reg", 1842 "ipa-shared", 1843 "gsi"; 1844 1845 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, 1846 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1847 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1848 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1849 interrupt-names = "ipa", 1850 "gsi", 1851 "ipa-clock-query", 1852 "ipa-setup-ready"; 1853 1854 clocks = <&rpmhcc RPMH_IPA_CLK>; 1855 clock-names = "core"; 1856 1857 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1858 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1859 interconnect-names = "memory", 1860 "config"; 1861 1862 qcom,qmp = <&aoss_qmp>; 1863 1864 qcom,smem-states = <&ipa_smp2p_out 0>, 1865 <&ipa_smp2p_out 1>; 1866 qcom,smem-state-names = "ipa-clock-enabled-valid", 1867 "ipa-clock-enabled"; 1868 1869 status = "disabled"; 1870 }; 1871 1872 tcsr_mutex: hwlock@1f40000 { 1873 compatible = "qcom,tcsr-mutex"; 1874 reg = <0x0 0x01f40000 0x0 0x40000>; 1875 #hwlock-cells = <1>; 1876 }; 1877 1878 tcsr: syscon@1fc0000 { 1879 compatible = "qcom,sm8350-tcsr", "syscon"; 1880 reg = <0x0 0x1fc0000 0x0 0x30000>; 1881 }; 1882 1883 adsp: remoteproc@3000000 { 1884 compatible = "qcom,sm8350-adsp-pas"; 1885 reg = <0x0 0x03000000 0x0 0x10000>; 1886 1887 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 1888 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1889 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1890 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1891 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1892 interrupt-names = "wdog", "fatal", "ready", 1893 "handover", "stop-ack"; 1894 1895 clocks = <&rpmhcc RPMH_CXO_CLK>; 1896 clock-names = "xo"; 1897 1898 power-domains = <&rpmhpd RPMHPD_LCX>, 1899 <&rpmhpd RPMHPD_LMX>; 1900 power-domain-names = "lcx", "lmx"; 1901 1902 memory-region = <&pil_adsp_mem>; 1903 1904 qcom,qmp = <&aoss_qmp>; 1905 1906 qcom,smem-states = <&smp2p_adsp_out 0>; 1907 qcom,smem-state-names = "stop"; 1908 1909 status = "disabled"; 1910 1911 glink-edge { 1912 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1913 IPCC_MPROC_SIGNAL_GLINK_QMP 1914 IRQ_TYPE_EDGE_RISING>; 1915 mboxes = <&ipcc IPCC_CLIENT_LPASS 1916 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1917 1918 label = "lpass"; 1919 qcom,remote-pid = <2>; 1920 1921 apr { 1922 compatible = "qcom,apr-v2"; 1923 qcom,glink-channels = "apr_audio_svc"; 1924 qcom,domain = <APR_DOMAIN_ADSP>; 1925 #address-cells = <1>; 1926 #size-cells = <0>; 1927 1928 service@3 { 1929 reg = <APR_SVC_ADSP_CORE>; 1930 compatible = "qcom,q6core"; 1931 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1932 }; 1933 1934 q6afe: service@4 { 1935 compatible = "qcom,q6afe"; 1936 reg = <APR_SVC_AFE>; 1937 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1938 1939 q6afedai: dais { 1940 compatible = "qcom,q6afe-dais"; 1941 #address-cells = <1>; 1942 #size-cells = <0>; 1943 #sound-dai-cells = <1>; 1944 }; 1945 1946 q6afecc: clock-controller { 1947 compatible = "qcom,q6afe-clocks"; 1948 #clock-cells = <2>; 1949 }; 1950 }; 1951 1952 q6asm: service@7 { 1953 compatible = "qcom,q6asm"; 1954 reg = <APR_SVC_ASM>; 1955 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1956 1957 q6asmdai: dais { 1958 compatible = "qcom,q6asm-dais"; 1959 #address-cells = <1>; 1960 #size-cells = <0>; 1961 #sound-dai-cells = <1>; 1962 iommus = <&apps_smmu 0x1801 0x0>; 1963 1964 dai@0 { 1965 reg = <MSM_FRONTEND_DAI_MULTIMEDIA1>; 1966 }; 1967 1968 dai@1 { 1969 reg = <MSM_FRONTEND_DAI_MULTIMEDIA2>; 1970 }; 1971 1972 dai@2 { 1973 reg = <MSM_FRONTEND_DAI_MULTIMEDIA3>; 1974 }; 1975 }; 1976 }; 1977 1978 q6adm: service@8 { 1979 compatible = "qcom,q6adm"; 1980 reg = <APR_SVC_ADM>; 1981 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1982 1983 q6routing: routing { 1984 compatible = "qcom,q6adm-routing"; 1985 #sound-dai-cells = <0>; 1986 }; 1987 }; 1988 }; 1989 1990 fastrpc { 1991 compatible = "qcom,fastrpc"; 1992 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1993 label = "adsp"; 1994 qcom,non-secure-domain; 1995 #address-cells = <1>; 1996 #size-cells = <0>; 1997 1998 compute-cb@3 { 1999 compatible = "qcom,fastrpc-compute-cb"; 2000 reg = <3>; 2001 iommus = <&apps_smmu 0x1803 0x0>; 2002 }; 2003 2004 compute-cb@4 { 2005 compatible = "qcom,fastrpc-compute-cb"; 2006 reg = <4>; 2007 iommus = <&apps_smmu 0x1804 0x0>; 2008 }; 2009 2010 compute-cb@5 { 2011 compatible = "qcom,fastrpc-compute-cb"; 2012 reg = <5>; 2013 iommus = <&apps_smmu 0x1805 0x0>; 2014 }; 2015 }; 2016 }; 2017 }; 2018 2019 lpass_tlmm: pinctrl@33c0000 { 2020 compatible = "qcom,sm8350-lpass-lpi-pinctrl"; 2021 reg = <0 0x033c0000 0 0x20000>, 2022 <0 0x03550000 0 0x10000>; 2023 2024 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2025 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2026 clock-names = "core", "audio"; 2027 2028 gpio-controller; 2029 #gpio-cells = <2>; 2030 gpio-ranges = <&lpass_tlmm 0 0 15>; 2031 }; 2032 2033 gpu: gpu@3d00000 { 2034 compatible = "qcom,adreno-660.1", "qcom,adreno"; 2035 2036 reg = <0 0x03d00000 0 0x40000>, 2037 <0 0x03d9e000 0 0x1000>, 2038 <0 0x03d61000 0 0x800>; 2039 reg-names = "kgsl_3d0_reg_memory", 2040 "cx_mem", 2041 "cx_dbgc"; 2042 2043 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2044 2045 iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>; 2046 2047 operating-points-v2 = <&gpu_opp_table>; 2048 2049 qcom,gmu = <&gmu>; 2050 #cooling-cells = <2>; 2051 2052 status = "disabled"; 2053 2054 zap-shader { 2055 memory-region = <&pil_gpu_mem>; 2056 }; 2057 2058 /* note: downstream checks gpu binning for 670 Mhz */ 2059 gpu_opp_table: opp-table { 2060 compatible = "operating-points-v2"; 2061 2062 opp-840000000 { 2063 opp-hz = /bits/ 64 <840000000>; 2064 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2065 }; 2066 2067 opp-778000000 { 2068 opp-hz = /bits/ 64 <778000000>; 2069 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2070 }; 2071 2072 opp-738000000 { 2073 opp-hz = /bits/ 64 <738000000>; 2074 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2075 }; 2076 2077 opp-676000000 { 2078 opp-hz = /bits/ 64 <676000000>; 2079 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2080 }; 2081 2082 opp-608000000 { 2083 opp-hz = /bits/ 64 <608000000>; 2084 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2085 }; 2086 2087 opp-540000000 { 2088 opp-hz = /bits/ 64 <540000000>; 2089 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2090 }; 2091 2092 opp-491000000 { 2093 opp-hz = /bits/ 64 <491000000>; 2094 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2095 }; 2096 2097 opp-443000000 { 2098 opp-hz = /bits/ 64 <443000000>; 2099 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2100 }; 2101 2102 opp-379000000 { 2103 opp-hz = /bits/ 64 <379000000>; 2104 opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>; 2105 }; 2106 2107 opp-315000000 { 2108 opp-hz = /bits/ 64 <315000000>; 2109 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2110 }; 2111 }; 2112 }; 2113 2114 gmu: gmu@3d6a000 { 2115 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu"; 2116 2117 reg = <0 0x03d6a000 0 0x34000>, 2118 <0 0x03de0000 0 0x10000>, 2119 <0 0x0b290000 0 0x10000>; 2120 reg-names = "gmu", "rscc", "gmu_pdc"; 2121 2122 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2123 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2124 interrupt-names = "hfi", "gmu"; 2125 2126 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2127 <&gpucc GPU_CC_CXO_CLK>, 2128 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2129 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2130 <&gpucc GPU_CC_AHB_CLK>, 2131 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2132 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2133 clock-names = "gmu", 2134 "cxo", 2135 "axi", 2136 "memnoc", 2137 "ahb", 2138 "hub", 2139 "smmu_vote"; 2140 2141 power-domains = <&gpucc GPU_CX_GDSC>, 2142 <&gpucc GPU_GX_GDSC>; 2143 power-domain-names = "cx", 2144 "gx"; 2145 2146 iommus = <&adreno_smmu 5 0x400>; 2147 2148 operating-points-v2 = <&gmu_opp_table>; 2149 2150 gmu_opp_table: opp-table { 2151 compatible = "operating-points-v2"; 2152 2153 opp-200000000 { 2154 opp-hz = /bits/ 64 <200000000>; 2155 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2156 }; 2157 }; 2158 }; 2159 2160 gpucc: clock-controller@3d90000 { 2161 compatible = "qcom,sm8350-gpucc"; 2162 reg = <0 0x03d90000 0 0x9000>; 2163 clocks = <&rpmhcc RPMH_CXO_CLK>, 2164 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2165 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2166 clock-names = "bi_tcxo", 2167 "gcc_gpu_gpll0_clk_src", 2168 "gcc_gpu_gpll0_div_clk_src"; 2169 #clock-cells = <1>; 2170 #reset-cells = <1>; 2171 #power-domain-cells = <1>; 2172 }; 2173 2174 adreno_smmu: iommu@3da0000 { 2175 compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu", 2176 "qcom,smmu-500", "arm,mmu-500"; 2177 reg = <0 0x03da0000 0 0x20000>; 2178 #iommu-cells = <2>; 2179 #global-interrupts = <2>; 2180 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2181 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2182 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2183 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2184 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2185 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2186 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2187 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2188 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2189 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2190 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2191 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2192 2193 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2194 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2195 <&gpucc GPU_CC_AHB_CLK>, 2196 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2197 <&gpucc GPU_CC_CX_GMU_CLK>, 2198 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2199 <&gpucc GPU_CC_HUB_AON_CLK>; 2200 clock-names = "bus", 2201 "iface", 2202 "ahb", 2203 "hlos1_vote_gpu_smmu", 2204 "cx_gmu", 2205 "hub_cx_int", 2206 "hub_aon"; 2207 2208 power-domains = <&gpucc GPU_CX_GDSC>; 2209 dma-coherent; 2210 }; 2211 2212 lpass_ag_noc: interconnect@3c40000 { 2213 compatible = "qcom,sm8350-lpass-ag-noc"; 2214 reg = <0 0x03c40000 0 0xf080>; 2215 #interconnect-cells = <2>; 2216 qcom,bcm-voters = <&apps_bcm_voter>; 2217 }; 2218 2219 mpss: remoteproc@4080000 { 2220 compatible = "qcom,sm8350-mpss-pas"; 2221 reg = <0x0 0x04080000 0x0 0x10000>; 2222 2223 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2224 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2225 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2226 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2227 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2228 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2229 interrupt-names = "wdog", "fatal", "ready", "handover", 2230 "stop-ack", "shutdown-ack"; 2231 2232 clocks = <&rpmhcc RPMH_CXO_CLK>; 2233 clock-names = "xo"; 2234 2235 power-domains = <&rpmhpd RPMHPD_CX>, 2236 <&rpmhpd RPMHPD_MSS>; 2237 power-domain-names = "cx", "mss"; 2238 2239 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2240 2241 memory-region = <&pil_modem_mem>; 2242 2243 qcom,qmp = <&aoss_qmp>; 2244 2245 qcom,smem-states = <&smp2p_modem_out 0>; 2246 qcom,smem-state-names = "stop"; 2247 2248 status = "disabled"; 2249 2250 glink-edge { 2251 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2252 IPCC_MPROC_SIGNAL_GLINK_QMP 2253 IRQ_TYPE_EDGE_RISING>; 2254 mboxes = <&ipcc IPCC_CLIENT_MPSS 2255 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2256 label = "modem"; 2257 qcom,remote-pid = <1>; 2258 }; 2259 }; 2260 2261 slpi: remoteproc@5c00000 { 2262 compatible = "qcom,sm8350-slpi-pas"; 2263 reg = <0 0x05c00000 0 0x4000>; 2264 2265 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2266 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2267 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2268 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2269 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2270 interrupt-names = "wdog", "fatal", "ready", 2271 "handover", "stop-ack"; 2272 2273 clocks = <&rpmhcc RPMH_CXO_CLK>; 2274 clock-names = "xo"; 2275 2276 power-domains = <&rpmhpd RPMHPD_LCX>, 2277 <&rpmhpd RPMHPD_LMX>; 2278 power-domain-names = "lcx", "lmx"; 2279 2280 memory-region = <&pil_slpi_mem>; 2281 2282 qcom,qmp = <&aoss_qmp>; 2283 2284 qcom,smem-states = <&smp2p_slpi_out 0>; 2285 qcom,smem-state-names = "stop"; 2286 2287 status = "disabled"; 2288 2289 glink-edge { 2290 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2291 IPCC_MPROC_SIGNAL_GLINK_QMP 2292 IRQ_TYPE_EDGE_RISING>; 2293 mboxes = <&ipcc IPCC_CLIENT_SLPI 2294 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2295 2296 label = "slpi"; 2297 qcom,remote-pid = <3>; 2298 2299 fastrpc { 2300 compatible = "qcom,fastrpc"; 2301 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2302 label = "sdsp"; 2303 qcom,non-secure-domain; 2304 #address-cells = <1>; 2305 #size-cells = <0>; 2306 2307 compute-cb@1 { 2308 compatible = "qcom,fastrpc-compute-cb"; 2309 reg = <1>; 2310 iommus = <&apps_smmu 0x0541 0x0>; 2311 }; 2312 2313 compute-cb@2 { 2314 compatible = "qcom,fastrpc-compute-cb"; 2315 reg = <2>; 2316 iommus = <&apps_smmu 0x0542 0x0>; 2317 }; 2318 2319 compute-cb@3 { 2320 compatible = "qcom,fastrpc-compute-cb"; 2321 reg = <3>; 2322 iommus = <&apps_smmu 0x0543 0x0>; 2323 /* note: shared-cb = <4> in downstream */ 2324 }; 2325 }; 2326 }; 2327 }; 2328 2329 sdhc_2: mmc@8804000 { 2330 compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5"; 2331 reg = <0 0x08804000 0 0x1000>; 2332 2333 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2334 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2335 interrupt-names = "hc_irq", "pwr_irq"; 2336 2337 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2338 <&gcc GCC_SDCC2_APPS_CLK>, 2339 <&rpmhcc RPMH_CXO_CLK>; 2340 clock-names = "iface", "core", "xo"; 2341 resets = <&gcc GCC_SDCC2_BCR>; 2342 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2343 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2344 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2345 iommus = <&apps_smmu 0x4a0 0x0>; 2346 power-domains = <&rpmhpd RPMHPD_CX>; 2347 operating-points-v2 = <&sdhc2_opp_table>; 2348 bus-width = <4>; 2349 dma-coherent; 2350 2351 status = "disabled"; 2352 2353 sdhc2_opp_table: opp-table { 2354 compatible = "operating-points-v2"; 2355 2356 opp-100000000 { 2357 opp-hz = /bits/ 64 <100000000>; 2358 required-opps = <&rpmhpd_opp_low_svs>; 2359 }; 2360 2361 opp-202000000 { 2362 opp-hz = /bits/ 64 <202000000>; 2363 required-opps = <&rpmhpd_opp_svs_l1>; 2364 }; 2365 }; 2366 }; 2367 2368 usb_1_hsphy: phy@88e3000 { 2369 compatible = "qcom,sm8350-usb-hs-phy", 2370 "qcom,usb-snps-hs-7nm-phy"; 2371 reg = <0 0x088e3000 0 0x400>; 2372 status = "disabled"; 2373 #phy-cells = <0>; 2374 2375 clocks = <&rpmhcc RPMH_CXO_CLK>; 2376 clock-names = "ref"; 2377 2378 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2379 }; 2380 2381 usb_2_hsphy: phy@88e4000 { 2382 compatible = "qcom,sm8250-usb-hs-phy", 2383 "qcom,usb-snps-hs-7nm-phy"; 2384 reg = <0 0x088e4000 0 0x400>; 2385 status = "disabled"; 2386 #phy-cells = <0>; 2387 2388 clocks = <&rpmhcc RPMH_CXO_CLK>; 2389 clock-names = "ref"; 2390 2391 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2392 }; 2393 2394 refgen: regulator@88e7000 { 2395 compatible = "qcom,sm8350-refgen-regulator", 2396 "qcom,sm8250-refgen-regulator"; 2397 reg = <0x0 0x088e7000 0x0 0x84>; 2398 }; 2399 2400 usb_1_qmpphy: phy@88e8000 { 2401 compatible = "qcom,sm8350-qmp-usb3-dp-phy"; 2402 reg = <0 0x088e8000 0 0x3000>; 2403 2404 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2405 <&rpmhcc RPMH_CXO_CLK>, 2406 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2407 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2408 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2409 2410 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2411 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2412 reset-names = "phy", "common"; 2413 2414 #clock-cells = <1>; 2415 #phy-cells = <1>; 2416 2417 orientation-switch; 2418 2419 status = "disabled"; 2420 2421 ports { 2422 #address-cells = <1>; 2423 #size-cells = <0>; 2424 2425 port@0 { 2426 reg = <0>; 2427 2428 usb_1_qmpphy_out: endpoint { 2429 }; 2430 }; 2431 2432 port@1 { 2433 reg = <1>; 2434 2435 usb_1_qmpphy_usb_ss_in: endpoint { 2436 remote-endpoint = <&usb_1_dwc3_ss>; 2437 }; 2438 }; 2439 2440 port@2 { 2441 reg = <2>; 2442 2443 usb_1_qmpphy_dp_in: endpoint { 2444 remote-endpoint = <&mdss_dp_out>; 2445 }; 2446 }; 2447 }; 2448 }; 2449 2450 usb_2_qmpphy: phy@88eb000 { 2451 compatible = "qcom,sm8350-qmp-usb3-uni-phy"; 2452 reg = <0 0x088eb000 0 0x2000>; 2453 status = "disabled"; 2454 2455 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2456 <&gcc GCC_USB3_SEC_CLKREF_EN>, 2457 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2458 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2459 clock-names = "aux", 2460 "ref", 2461 "com_aux", 2462 "pipe"; 2463 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2464 #clock-cells = <0>; 2465 #phy-cells = <0>; 2466 2467 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2468 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 2469 reset-names = "phy", 2470 "phy_phy"; 2471 }; 2472 2473 dc_noc: interconnect@90c0000 { 2474 compatible = "qcom,sm8350-dc-noc"; 2475 reg = <0 0x090c0000 0 0x4200>; 2476 #interconnect-cells = <2>; 2477 qcom,bcm-voters = <&apps_bcm_voter>; 2478 }; 2479 2480 gem_noc: interconnect@9100000 { 2481 compatible = "qcom,sm8350-gem-noc"; 2482 reg = <0 0x09100000 0 0xb4000>; 2483 #interconnect-cells = <2>; 2484 qcom,bcm-voters = <&apps_bcm_voter>; 2485 }; 2486 2487 system-cache-controller@9200000 { 2488 compatible = "qcom,sm8350-llcc"; 2489 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 2490 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 2491 <0 0x09600000 0 0x58000>; 2492 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2493 "llcc3_base", "llcc_broadcast_base"; 2494 }; 2495 2496 compute_noc: interconnect@a0c0000 { 2497 compatible = "qcom,sm8350-compute-noc"; 2498 reg = <0 0x0a0c0000 0 0xa180>; 2499 #interconnect-cells = <2>; 2500 qcom,bcm-voters = <&apps_bcm_voter>; 2501 }; 2502 2503 cdsp: remoteproc@a300000 { 2504 compatible = "qcom,sm8350-cdsp-pas"; 2505 reg = <0x0 0x0a300000 0x0 0x10000>; 2506 2507 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2508 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2509 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2510 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2511 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 2512 interrupt-names = "wdog", "fatal", "ready", 2513 "handover", "stop-ack"; 2514 2515 clocks = <&rpmhcc RPMH_CXO_CLK>; 2516 clock-names = "xo"; 2517 2518 power-domains = <&rpmhpd RPMHPD_CX>, 2519 <&rpmhpd RPMHPD_MXC>; 2520 power-domain-names = "cx", "mxc"; 2521 2522 interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 2523 2524 memory-region = <&pil_cdsp_mem>; 2525 2526 qcom,qmp = <&aoss_qmp>; 2527 2528 qcom,smem-states = <&smp2p_cdsp_out 0>; 2529 qcom,smem-state-names = "stop"; 2530 2531 status = "disabled"; 2532 2533 glink-edge { 2534 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2535 IPCC_MPROC_SIGNAL_GLINK_QMP 2536 IRQ_TYPE_EDGE_RISING>; 2537 mboxes = <&ipcc IPCC_CLIENT_CDSP 2538 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2539 2540 label = "cdsp"; 2541 qcom,remote-pid = <5>; 2542 2543 fastrpc { 2544 compatible = "qcom,fastrpc"; 2545 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2546 label = "cdsp"; 2547 qcom,non-secure-domain; 2548 #address-cells = <1>; 2549 #size-cells = <0>; 2550 2551 compute-cb@1 { 2552 compatible = "qcom,fastrpc-compute-cb"; 2553 reg = <1>; 2554 iommus = <&apps_smmu 0x2161 0x0400>, 2555 <&apps_smmu 0x1181 0x0420>; 2556 }; 2557 2558 compute-cb@2 { 2559 compatible = "qcom,fastrpc-compute-cb"; 2560 reg = <2>; 2561 iommus = <&apps_smmu 0x2162 0x0400>, 2562 <&apps_smmu 0x1182 0x0420>; 2563 }; 2564 2565 compute-cb@3 { 2566 compatible = "qcom,fastrpc-compute-cb"; 2567 reg = <3>; 2568 iommus = <&apps_smmu 0x2163 0x0400>, 2569 <&apps_smmu 0x1183 0x0420>; 2570 }; 2571 2572 compute-cb@4 { 2573 compatible = "qcom,fastrpc-compute-cb"; 2574 reg = <4>; 2575 iommus = <&apps_smmu 0x2164 0x0400>, 2576 <&apps_smmu 0x1184 0x0420>; 2577 }; 2578 2579 compute-cb@5 { 2580 compatible = "qcom,fastrpc-compute-cb"; 2581 reg = <5>; 2582 iommus = <&apps_smmu 0x2165 0x0400>, 2583 <&apps_smmu 0x1185 0x0420>; 2584 }; 2585 2586 compute-cb@6 { 2587 compatible = "qcom,fastrpc-compute-cb"; 2588 reg = <6>; 2589 iommus = <&apps_smmu 0x2166 0x0400>, 2590 <&apps_smmu 0x1186 0x0420>; 2591 }; 2592 2593 compute-cb@7 { 2594 compatible = "qcom,fastrpc-compute-cb"; 2595 reg = <7>; 2596 iommus = <&apps_smmu 0x2167 0x0400>, 2597 <&apps_smmu 0x1187 0x0420>; 2598 }; 2599 2600 compute-cb@8 { 2601 compatible = "qcom,fastrpc-compute-cb"; 2602 reg = <8>; 2603 iommus = <&apps_smmu 0x2168 0x0400>, 2604 <&apps_smmu 0x1188 0x0420>; 2605 }; 2606 2607 /* note: secure cb9 in downstream */ 2608 }; 2609 }; 2610 }; 2611 2612 usb_1: usb@a6f8800 { 2613 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2614 reg = <0 0x0a6f8800 0 0x400>; 2615 status = "disabled"; 2616 #address-cells = <2>; 2617 #size-cells = <2>; 2618 ranges; 2619 2620 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2621 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2622 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2623 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2624 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 2625 clock-names = "cfg_noc", 2626 "core", 2627 "iface", 2628 "sleep", 2629 "mock_utmi"; 2630 2631 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2632 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2633 assigned-clock-rates = <19200000>, <200000000>; 2634 2635 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2636 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2637 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2638 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2639 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2640 interrupt-names = "pwr_event", 2641 "hs_phy_irq", 2642 "dp_hs_phy_irq", 2643 "dm_hs_phy_irq", 2644 "ss_phy_irq"; 2645 2646 power-domains = <&gcc USB30_PRIM_GDSC>; 2647 2648 resets = <&gcc GCC_USB30_PRIM_BCR>; 2649 2650 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2651 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 2652 interconnect-names = "usb-ddr", "apps-usb"; 2653 2654 usb_1_dwc3: usb@a600000 { 2655 compatible = "snps,dwc3"; 2656 reg = <0 0x0a600000 0 0xcd00>; 2657 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2658 iommus = <&apps_smmu 0x0 0x0>; 2659 snps,dis_u2_susphy_quirk; 2660 snps,dis_u3_susphy_quirk; 2661 snps,dis_enblslpm_quirk; 2662 snps,dis-u1-entry-quirk; 2663 snps,dis-u2-entry-quirk; 2664 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 2665 phy-names = "usb2-phy", "usb3-phy"; 2666 2667 ports { 2668 #address-cells = <1>; 2669 #size-cells = <0>; 2670 2671 port@0 { 2672 reg = <0>; 2673 2674 usb_1_dwc3_hs: endpoint { 2675 }; 2676 }; 2677 2678 port@1 { 2679 reg = <1>; 2680 2681 usb_1_dwc3_ss: endpoint { 2682 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 2683 }; 2684 }; 2685 }; 2686 }; 2687 }; 2688 2689 usb_2: usb@a8f8800 { 2690 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2691 reg = <0 0x0a8f8800 0 0x400>; 2692 status = "disabled"; 2693 #address-cells = <2>; 2694 #size-cells = <2>; 2695 ranges; 2696 2697 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2698 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2699 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2700 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2701 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2702 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2703 clock-names = "cfg_noc", 2704 "core", 2705 "iface", 2706 "sleep", 2707 "mock_utmi", 2708 "xo"; 2709 2710 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2711 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2712 assigned-clock-rates = <19200000>, <200000000>; 2713 2714 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 2715 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2716 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 2717 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 2718 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 2719 interrupt-names = "pwr_event", 2720 "hs_phy_irq", 2721 "dp_hs_phy_irq", 2722 "dm_hs_phy_irq", 2723 "ss_phy_irq"; 2724 2725 power-domains = <&gcc USB30_SEC_GDSC>; 2726 2727 resets = <&gcc GCC_USB30_SEC_BCR>; 2728 2729 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 2730 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 2731 interconnect-names = "usb-ddr", "apps-usb"; 2732 2733 usb_2_dwc3: usb@a800000 { 2734 compatible = "snps,dwc3"; 2735 reg = <0 0x0a800000 0 0xcd00>; 2736 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2737 iommus = <&apps_smmu 0x20 0x0>; 2738 snps,dis_u2_susphy_quirk; 2739 snps,dis_u3_susphy_quirk; 2740 snps,dis_enblslpm_quirk; 2741 snps,dis-u1-entry-quirk; 2742 snps,dis-u2-entry-quirk; 2743 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>; 2744 phy-names = "usb2-phy", "usb3-phy"; 2745 }; 2746 }; 2747 2748 mdss: display-subsystem@ae00000 { 2749 compatible = "qcom,sm8350-mdss"; 2750 reg = <0 0x0ae00000 0 0x1000>; 2751 reg-names = "mdss"; 2752 2753 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 2754 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>, 2755 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2756 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 2757 interconnect-names = "mdp0-mem", 2758 "mdp1-mem", 2759 "cpu-cfg"; 2760 2761 power-domains = <&dispcc MDSS_GDSC>; 2762 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2763 2764 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2765 <&gcc GCC_DISP_HF_AXI_CLK>, 2766 <&gcc GCC_DISP_SF_AXI_CLK>, 2767 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2768 clock-names = "iface", "bus", "nrt_bus", "core"; 2769 2770 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2771 interrupt-controller; 2772 #interrupt-cells = <1>; 2773 2774 iommus = <&apps_smmu 0x820 0x402>; 2775 2776 status = "disabled"; 2777 2778 #address-cells = <2>; 2779 #size-cells = <2>; 2780 ranges; 2781 2782 mdss_mdp: display-controller@ae01000 { 2783 compatible = "qcom,sm8350-dpu"; 2784 reg = <0 0x0ae01000 0 0x8f000>, 2785 <0 0x0aeb0000 0 0x3000>; 2786 reg-names = "mdp", "vbif"; 2787 2788 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2789 <&gcc GCC_DISP_SF_AXI_CLK>, 2790 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2791 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2792 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2793 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2794 clock-names = "bus", 2795 "nrt_bus", 2796 "iface", 2797 "lut", 2798 "core", 2799 "vsync"; 2800 2801 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2802 assigned-clock-rates = <19200000>; 2803 2804 operating-points-v2 = <&dpu_opp_table>; 2805 power-domains = <&rpmhpd RPMHPD_MMCX>; 2806 2807 interrupt-parent = <&mdss>; 2808 interrupts = <0>; 2809 2810 dpu_opp_table: opp-table { 2811 compatible = "operating-points-v2"; 2812 2813 /* TODO: opp-200000000 should work with 2814 * &rpmhpd_opp_low_svs, but one some of 2815 * sm8350_hdk boards reboot using this 2816 * opp. 2817 */ 2818 opp-200000000 { 2819 opp-hz = /bits/ 64 <200000000>; 2820 required-opps = <&rpmhpd_opp_svs>; 2821 }; 2822 2823 opp-300000000 { 2824 opp-hz = /bits/ 64 <300000000>; 2825 required-opps = <&rpmhpd_opp_svs>; 2826 }; 2827 2828 opp-345000000 { 2829 opp-hz = /bits/ 64 <345000000>; 2830 required-opps = <&rpmhpd_opp_svs_l1>; 2831 }; 2832 2833 opp-460000000 { 2834 opp-hz = /bits/ 64 <460000000>; 2835 required-opps = <&rpmhpd_opp_nom>; 2836 }; 2837 }; 2838 2839 ports { 2840 #address-cells = <1>; 2841 #size-cells = <0>; 2842 2843 port@0 { 2844 reg = <0>; 2845 dpu_intf1_out: endpoint { 2846 remote-endpoint = <&mdss_dsi0_in>; 2847 }; 2848 }; 2849 2850 port@1 { 2851 reg = <1>; 2852 dpu_intf2_out: endpoint { 2853 remote-endpoint = <&mdss_dsi1_in>; 2854 }; 2855 }; 2856 2857 port@2 { 2858 reg = <2>; 2859 dpu_intf0_out: endpoint { 2860 remote-endpoint = <&mdss_dp_in>; 2861 }; 2862 }; 2863 }; 2864 }; 2865 2866 mdss_dp: displayport-controller@ae90000 { 2867 compatible = "qcom,sm8350-dp"; 2868 reg = <0 0xae90000 0 0x200>, 2869 <0 0xae90200 0 0x200>, 2870 <0 0xae90400 0 0x600>, 2871 <0 0xae91000 0 0x400>, 2872 <0 0xae91400 0 0x400>; 2873 interrupt-parent = <&mdss>; 2874 interrupts = <12>; 2875 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2876 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 2877 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 2878 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 2879 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, 2880 <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; 2881 clock-names = "core_iface", 2882 "core_aux", 2883 "ctrl_link", 2884 "ctrl_link_iface", 2885 "stream_pixel", 2886 "stream_1_pixel"; 2887 2888 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 2889 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, 2890 <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; 2891 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2892 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 2893 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2894 2895 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 2896 phy-names = "dp"; 2897 2898 #sound-dai-cells = <0>; 2899 2900 operating-points-v2 = <&dp_opp_table>; 2901 power-domains = <&rpmhpd RPMHPD_MMCX>; 2902 2903 status = "disabled"; 2904 2905 ports { 2906 #address-cells = <1>; 2907 #size-cells = <0>; 2908 2909 port@0 { 2910 reg = <0>; 2911 mdss_dp_in: endpoint { 2912 remote-endpoint = <&dpu_intf0_out>; 2913 }; 2914 }; 2915 2916 port@1 { 2917 reg = <1>; 2918 2919 mdss_dp_out: endpoint { 2920 remote-endpoint = <&usb_1_qmpphy_dp_in>; 2921 }; 2922 }; 2923 }; 2924 2925 dp_opp_table: opp-table { 2926 compatible = "operating-points-v2"; 2927 2928 opp-160000000 { 2929 opp-hz = /bits/ 64 <160000000>; 2930 required-opps = <&rpmhpd_opp_low_svs>; 2931 }; 2932 2933 opp-270000000 { 2934 opp-hz = /bits/ 64 <270000000>; 2935 required-opps = <&rpmhpd_opp_svs>; 2936 }; 2937 2938 opp-540000000 { 2939 opp-hz = /bits/ 64 <540000000>; 2940 required-opps = <&rpmhpd_opp_svs_l1>; 2941 }; 2942 2943 opp-810000000 { 2944 opp-hz = /bits/ 64 <810000000>; 2945 required-opps = <&rpmhpd_opp_nom>; 2946 }; 2947 }; 2948 }; 2949 2950 mdss_dsi0: dsi@ae94000 { 2951 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2952 reg = <0 0x0ae94000 0 0x400>; 2953 reg-names = "dsi_ctrl"; 2954 2955 interrupt-parent = <&mdss>; 2956 interrupts = <4>; 2957 2958 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2959 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2960 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2961 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2962 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2963 <&gcc GCC_DISP_HF_AXI_CLK>; 2964 clock-names = "byte", 2965 "byte_intf", 2966 "pixel", 2967 "core", 2968 "iface", 2969 "bus"; 2970 2971 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2972 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2973 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2974 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 2975 2976 operating-points-v2 = <&dsi0_opp_table>; 2977 power-domains = <&rpmhpd RPMHPD_MMCX>; 2978 refgen-supply = <&refgen>; 2979 2980 phys = <&mdss_dsi0_phy>; 2981 2982 #address-cells = <1>; 2983 #size-cells = <0>; 2984 2985 status = "disabled"; 2986 2987 dsi0_opp_table: opp-table { 2988 compatible = "operating-points-v2"; 2989 2990 /* TODO: opp-187500000 should work with 2991 * &rpmhpd_opp_low_svs, but one some of 2992 * sm8350_hdk boards reboot using this 2993 * opp. 2994 */ 2995 opp-187500000 { 2996 opp-hz = /bits/ 64 <187500000>; 2997 required-opps = <&rpmhpd_opp_svs>; 2998 }; 2999 3000 opp-300000000 { 3001 opp-hz = /bits/ 64 <300000000>; 3002 required-opps = <&rpmhpd_opp_svs>; 3003 }; 3004 3005 opp-358000000 { 3006 opp-hz = /bits/ 64 <358000000>; 3007 required-opps = <&rpmhpd_opp_svs_l1>; 3008 }; 3009 }; 3010 3011 ports { 3012 #address-cells = <1>; 3013 #size-cells = <0>; 3014 3015 port@0 { 3016 reg = <0>; 3017 mdss_dsi0_in: endpoint { 3018 remote-endpoint = <&dpu_intf1_out>; 3019 }; 3020 }; 3021 3022 port@1 { 3023 reg = <1>; 3024 mdss_dsi0_out: endpoint { 3025 }; 3026 }; 3027 }; 3028 }; 3029 3030 mdss_dsi0_phy: phy@ae94400 { 3031 compatible = "qcom,sm8350-dsi-phy-5nm"; 3032 reg = <0 0x0ae94400 0 0x200>, 3033 <0 0x0ae94600 0 0x280>, 3034 <0 0x0ae94900 0 0x27c>; 3035 reg-names = "dsi_phy", 3036 "dsi_phy_lane", 3037 "dsi_pll"; 3038 3039 #clock-cells = <1>; 3040 #phy-cells = <0>; 3041 3042 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3043 <&rpmhcc RPMH_CXO_CLK>; 3044 clock-names = "iface", "ref"; 3045 3046 status = "disabled"; 3047 }; 3048 3049 mdss_dsi1: dsi@ae96000 { 3050 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3051 reg = <0 0x0ae96000 0 0x400>; 3052 reg-names = "dsi_ctrl"; 3053 3054 interrupt-parent = <&mdss>; 3055 interrupts = <5>; 3056 3057 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3058 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3059 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3060 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3061 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3062 <&gcc GCC_DISP_HF_AXI_CLK>; 3063 clock-names = "byte", 3064 "byte_intf", 3065 "pixel", 3066 "core", 3067 "iface", 3068 "bus"; 3069 3070 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 3071 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3072 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 3073 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 3074 3075 operating-points-v2 = <&dsi1_opp_table>; 3076 power-domains = <&rpmhpd RPMHPD_MMCX>; 3077 refgen-supply = <&refgen>; 3078 3079 phys = <&mdss_dsi1_phy>; 3080 3081 #address-cells = <1>; 3082 #size-cells = <0>; 3083 3084 status = "disabled"; 3085 3086 dsi1_opp_table: opp-table { 3087 compatible = "operating-points-v2"; 3088 3089 /* TODO: opp-187500000 should work with 3090 * &rpmhpd_opp_low_svs, but one some of 3091 * sm8350_hdk boards reboot using this 3092 * opp. 3093 */ 3094 opp-187500000 { 3095 opp-hz = /bits/ 64 <187500000>; 3096 required-opps = <&rpmhpd_opp_svs>; 3097 }; 3098 3099 opp-300000000 { 3100 opp-hz = /bits/ 64 <300000000>; 3101 required-opps = <&rpmhpd_opp_svs>; 3102 }; 3103 3104 opp-358000000 { 3105 opp-hz = /bits/ 64 <358000000>; 3106 required-opps = <&rpmhpd_opp_svs_l1>; 3107 }; 3108 }; 3109 3110 ports { 3111 #address-cells = <1>; 3112 #size-cells = <0>; 3113 3114 port@0 { 3115 reg = <0>; 3116 mdss_dsi1_in: endpoint { 3117 remote-endpoint = <&dpu_intf2_out>; 3118 }; 3119 }; 3120 3121 port@1 { 3122 reg = <1>; 3123 mdss_dsi1_out: endpoint { 3124 }; 3125 }; 3126 }; 3127 }; 3128 3129 mdss_dsi1_phy: phy@ae96400 { 3130 compatible = "qcom,sm8350-dsi-phy-5nm"; 3131 reg = <0 0x0ae96400 0 0x200>, 3132 <0 0x0ae96600 0 0x280>, 3133 <0 0x0ae96900 0 0x27c>; 3134 reg-names = "dsi_phy", 3135 "dsi_phy_lane", 3136 "dsi_pll"; 3137 3138 #clock-cells = <1>; 3139 #phy-cells = <0>; 3140 3141 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3142 <&rpmhcc RPMH_CXO_CLK>; 3143 clock-names = "iface", "ref"; 3144 3145 status = "disabled"; 3146 }; 3147 }; 3148 3149 dispcc: clock-controller@af00000 { 3150 compatible = "qcom,sm8350-dispcc"; 3151 reg = <0 0x0af00000 0 0x10000>; 3152 clocks = <&rpmhcc RPMH_CXO_CLK>, 3153 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 3154 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 3155 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 3156 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 3157 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3158 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3159 clock-names = "bi_tcxo", 3160 "dsi0_phy_pll_out_byteclk", 3161 "dsi0_phy_pll_out_dsiclk", 3162 "dsi1_phy_pll_out_byteclk", 3163 "dsi1_phy_pll_out_dsiclk", 3164 "dp_phy_pll_link_clk", 3165 "dp_phy_pll_vco_div_clk"; 3166 #clock-cells = <1>; 3167 #reset-cells = <1>; 3168 #power-domain-cells = <1>; 3169 3170 power-domains = <&rpmhpd RPMHPD_MMCX>; 3171 }; 3172 3173 pdc: interrupt-controller@b220000 { 3174 compatible = "qcom,sm8350-pdc", "qcom,pdc"; 3175 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 3176 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, 3177 <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, 3178 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, 3179 <156 716 12>; 3180 #interrupt-cells = <2>; 3181 interrupt-parent = <&intc>; 3182 interrupt-controller; 3183 }; 3184 3185 tsens0: thermal-sensor@c263000 { 3186 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 3187 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3188 <0 0x0c222000 0 0x8>; /* SROT */ 3189 #qcom,sensors = <15>; 3190 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 3191 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 3192 interrupt-names = "uplow", "critical"; 3193 #thermal-sensor-cells = <1>; 3194 }; 3195 3196 tsens1: thermal-sensor@c265000 { 3197 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 3198 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3199 <0 0x0c223000 0 0x8>; /* SROT */ 3200 #qcom,sensors = <14>; 3201 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 3202 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 3203 interrupt-names = "uplow", "critical"; 3204 #thermal-sensor-cells = <1>; 3205 }; 3206 3207 aoss_qmp: power-management@c300000 { 3208 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; 3209 reg = <0 0x0c300000 0 0x400>; 3210 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 3211 IRQ_TYPE_EDGE_RISING>; 3212 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3213 3214 #clock-cells = <0>; 3215 }; 3216 3217 sram@c3f0000 { 3218 compatible = "qcom,rpmh-stats"; 3219 reg = <0 0x0c3f0000 0 0x400>; 3220 }; 3221 3222 spmi_bus: spmi@c440000 { 3223 compatible = "qcom,spmi-pmic-arb"; 3224 reg = <0x0 0x0c440000 0x0 0x1100>, 3225 <0x0 0x0c600000 0x0 0x2000000>, 3226 <0x0 0x0e600000 0x0 0x100000>, 3227 <0x0 0x0e700000 0x0 0xa0000>, 3228 <0x0 0x0c40a000 0x0 0x26000>; 3229 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3230 interrupt-names = "periph_irq"; 3231 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3232 qcom,ee = <0>; 3233 qcom,channel = <0>; 3234 #address-cells = <2>; 3235 #size-cells = <0>; 3236 interrupt-controller; 3237 #interrupt-cells = <4>; 3238 }; 3239 3240 tlmm: pinctrl@f100000 { 3241 compatible = "qcom,sm8350-tlmm"; 3242 reg = <0 0x0f100000 0 0x300000>; 3243 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3244 gpio-controller; 3245 #gpio-cells = <2>; 3246 interrupt-controller; 3247 #interrupt-cells = <2>; 3248 gpio-ranges = <&tlmm 0 0 204>; 3249 wakeup-parent = <&pdc>; 3250 3251 sdc2_default_state: sdc2-default-state { 3252 clk-pins { 3253 pins = "sdc2_clk"; 3254 drive-strength = <16>; 3255 bias-disable; 3256 }; 3257 3258 cmd-pins { 3259 pins = "sdc2_cmd"; 3260 drive-strength = <16>; 3261 bias-pull-up; 3262 }; 3263 3264 data-pins { 3265 pins = "sdc2_data"; 3266 drive-strength = <16>; 3267 bias-pull-up; 3268 }; 3269 }; 3270 3271 sdc2_sleep_state: sdc2-sleep-state { 3272 clk-pins { 3273 pins = "sdc2_clk"; 3274 drive-strength = <2>; 3275 bias-disable; 3276 }; 3277 3278 cmd-pins { 3279 pins = "sdc2_cmd"; 3280 drive-strength = <2>; 3281 bias-pull-up; 3282 }; 3283 3284 data-pins { 3285 pins = "sdc2_data"; 3286 drive-strength = <2>; 3287 bias-pull-up; 3288 }; 3289 }; 3290 3291 qup_uart3_default_state: qup-uart3-default-state { 3292 rx-pins { 3293 pins = "gpio18"; 3294 function = "qup3"; 3295 }; 3296 tx-pins { 3297 pins = "gpio19"; 3298 function = "qup3"; 3299 }; 3300 }; 3301 3302 qup_uart6_default: qup-uart6-default-state { 3303 pins = "gpio30", "gpio31"; 3304 function = "qup6"; 3305 drive-strength = <2>; 3306 bias-disable; 3307 }; 3308 3309 qup_uart18_default: qup-uart18-default-state { 3310 pins = "gpio68", "gpio69"; 3311 function = "qup18"; 3312 drive-strength = <2>; 3313 bias-disable; 3314 }; 3315 3316 qup_i2c0_default: qup-i2c0-default-state { 3317 pins = "gpio4", "gpio5"; 3318 function = "qup0"; 3319 drive-strength = <2>; 3320 bias-pull-up; 3321 }; 3322 3323 qup_i2c1_default: qup-i2c1-default-state { 3324 pins = "gpio8", "gpio9"; 3325 function = "qup1"; 3326 drive-strength = <2>; 3327 bias-pull-up; 3328 }; 3329 3330 qup_i2c2_default: qup-i2c2-default-state { 3331 pins = "gpio12", "gpio13"; 3332 function = "qup2"; 3333 drive-strength = <2>; 3334 bias-pull-up; 3335 }; 3336 3337 qup_i2c4_default: qup-i2c4-default-state { 3338 pins = "gpio20", "gpio21"; 3339 function = "qup4"; 3340 drive-strength = <2>; 3341 bias-pull-up; 3342 }; 3343 3344 qup_i2c5_default: qup-i2c5-default-state { 3345 pins = "gpio24", "gpio25"; 3346 function = "qup5"; 3347 drive-strength = <2>; 3348 bias-pull-up; 3349 }; 3350 3351 qup_i2c6_default: qup-i2c6-default-state { 3352 pins = "gpio28", "gpio29"; 3353 function = "qup6"; 3354 drive-strength = <2>; 3355 bias-pull-up; 3356 }; 3357 3358 qup_i2c7_default: qup-i2c7-default-state { 3359 pins = "gpio32", "gpio33"; 3360 function = "qup7"; 3361 drive-strength = <2>; 3362 bias-disable; 3363 }; 3364 3365 qup_i2c8_default: qup-i2c8-default-state { 3366 pins = "gpio36", "gpio37"; 3367 function = "qup8"; 3368 drive-strength = <2>; 3369 bias-pull-up; 3370 }; 3371 3372 qup_i2c9_default: qup-i2c9-default-state { 3373 pins = "gpio40", "gpio41"; 3374 function = "qup9"; 3375 drive-strength = <2>; 3376 bias-pull-up; 3377 }; 3378 3379 qup_i2c10_default: qup-i2c10-default-state { 3380 pins = "gpio44", "gpio45"; 3381 function = "qup10"; 3382 drive-strength = <2>; 3383 bias-pull-up; 3384 }; 3385 3386 qup_i2c11_default: qup-i2c11-default-state { 3387 pins = "gpio48", "gpio49"; 3388 function = "qup11"; 3389 drive-strength = <2>; 3390 bias-pull-up; 3391 }; 3392 3393 qup_i2c12_default: qup-i2c12-default-state { 3394 pins = "gpio52", "gpio53"; 3395 function = "qup12"; 3396 drive-strength = <2>; 3397 bias-pull-up; 3398 }; 3399 3400 qup_i2c13_default: qup-i2c13-default-state { 3401 pins = "gpio0", "gpio1"; 3402 function = "qup13"; 3403 drive-strength = <2>; 3404 bias-pull-up; 3405 }; 3406 3407 qup_i2c14_default: qup-i2c14-default-state { 3408 pins = "gpio56", "gpio57"; 3409 function = "qup14"; 3410 drive-strength = <2>; 3411 bias-disable; 3412 }; 3413 3414 qup_i2c15_default: qup-i2c15-default-state { 3415 pins = "gpio60", "gpio61"; 3416 function = "qup15"; 3417 drive-strength = <2>; 3418 bias-disable; 3419 }; 3420 3421 qup_i2c16_default: qup-i2c16-default-state { 3422 pins = "gpio64", "gpio65"; 3423 function = "qup16"; 3424 drive-strength = <2>; 3425 bias-disable; 3426 }; 3427 3428 qup_i2c17_default: qup-i2c17-default-state { 3429 pins = "gpio72", "gpio73"; 3430 function = "qup17"; 3431 drive-strength = <2>; 3432 bias-disable; 3433 }; 3434 3435 qup_i2c19_default: qup-i2c19-default-state { 3436 pins = "gpio76", "gpio77"; 3437 function = "qup19"; 3438 drive-strength = <2>; 3439 bias-disable; 3440 }; 3441 }; 3442 3443 apps_smmu: iommu@15000000 { 3444 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; 3445 reg = <0 0x15000000 0 0x100000>; 3446 #iommu-cells = <2>; 3447 #global-interrupts = <2>; 3448 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 3449 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3450 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3451 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3452 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3453 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3454 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3455 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3456 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3457 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3458 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3459 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3460 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3461 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3462 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3463 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3464 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3465 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3466 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3467 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3468 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3469 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3470 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3471 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3472 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3473 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3474 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3475 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3476 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3477 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3478 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3479 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3480 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3481 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3482 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3483 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3484 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3485 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3486 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3487 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3488 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3489 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3490 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3491 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3492 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3493 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3494 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3495 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3496 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3497 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3498 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3499 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3500 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3501 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3502 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3503 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3504 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3505 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3506 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3507 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3508 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3509 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3510 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3511 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3512 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3513 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3514 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3515 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3516 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3517 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3518 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3519 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3520 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3521 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3522 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3523 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3524 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3525 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3526 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3527 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3528 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3529 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3530 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3531 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3532 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3533 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3534 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3535 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3536 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3537 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3538 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3539 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3540 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3541 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3542 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3543 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3544 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 3545 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 3546 dma-coherent; 3547 }; 3548 3549 intc: interrupt-controller@17a00000 { 3550 compatible = "arm,gic-v3"; 3551 #address-cells = <0>; 3552 #interrupt-cells = <3>; 3553 interrupt-controller; 3554 #redistributor-regions = <1>; 3555 redistributor-stride = <0 0x20000>; 3556 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3557 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3558 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3559 }; 3560 3561 timer@17c20000 { 3562 compatible = "arm,armv7-timer-mem"; 3563 #address-cells = <1>; 3564 #size-cells = <1>; 3565 ranges = <0 0 0 0x20000000>; 3566 reg = <0x0 0x17c20000 0x0 0x1000>; 3567 clock-frequency = <19200000>; 3568 3569 frame@17c21000 { 3570 frame-number = <0>; 3571 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3572 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3573 reg = <0x17c21000 0x1000>, 3574 <0x17c22000 0x1000>; 3575 }; 3576 3577 frame@17c23000 { 3578 frame-number = <1>; 3579 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3580 reg = <0x17c23000 0x1000>; 3581 status = "disabled"; 3582 }; 3583 3584 frame@17c25000 { 3585 frame-number = <2>; 3586 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3587 reg = <0x17c25000 0x1000>; 3588 status = "disabled"; 3589 }; 3590 3591 frame@17c27000 { 3592 frame-number = <3>; 3593 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3594 reg = <0x17c27000 0x1000>; 3595 status = "disabled"; 3596 }; 3597 3598 frame@17c29000 { 3599 frame-number = <4>; 3600 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3601 reg = <0x17c29000 0x1000>; 3602 status = "disabled"; 3603 }; 3604 3605 frame@17c2b000 { 3606 frame-number = <5>; 3607 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3608 reg = <0x17c2b000 0x1000>; 3609 status = "disabled"; 3610 }; 3611 3612 frame@17c2d000 { 3613 frame-number = <6>; 3614 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3615 reg = <0x17c2d000 0x1000>; 3616 status = "disabled"; 3617 }; 3618 }; 3619 3620 apps_rsc: rsc@18200000 { 3621 label = "apps_rsc"; 3622 compatible = "qcom,rpmh-rsc"; 3623 reg = <0x0 0x18200000 0x0 0x10000>, 3624 <0x0 0x18210000 0x0 0x10000>, 3625 <0x0 0x18220000 0x0 0x10000>; 3626 reg-names = "drv-0", "drv-1", "drv-2"; 3627 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3628 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3629 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3630 qcom,tcs-offset = <0xd00>; 3631 qcom,drv-id = <2>; 3632 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 3633 <WAKE_TCS 3>, <CONTROL_TCS 0>; 3634 power-domains = <&cluster_pd>; 3635 3636 rpmhcc: clock-controller { 3637 compatible = "qcom,sm8350-rpmh-clk"; 3638 #clock-cells = <1>; 3639 clock-names = "xo"; 3640 clocks = <&xo_board>; 3641 }; 3642 3643 rpmhpd: power-controller { 3644 compatible = "qcom,sm8350-rpmhpd"; 3645 #power-domain-cells = <1>; 3646 operating-points-v2 = <&rpmhpd_opp_table>; 3647 3648 rpmhpd_opp_table: opp-table { 3649 compatible = "operating-points-v2"; 3650 3651 rpmhpd_opp_ret: opp1 { 3652 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3653 }; 3654 3655 rpmhpd_opp_min_svs: opp2 { 3656 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3657 }; 3658 3659 rpmhpd_opp_low_svs: opp3 { 3660 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3661 }; 3662 3663 rpmhpd_opp_svs: opp4 { 3664 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3665 }; 3666 3667 rpmhpd_opp_svs_l1: opp5 { 3668 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3669 }; 3670 3671 rpmhpd_opp_nom: opp6 { 3672 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3673 }; 3674 3675 rpmhpd_opp_nom_l1: opp7 { 3676 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3677 }; 3678 3679 rpmhpd_opp_nom_l2: opp8 { 3680 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3681 }; 3682 3683 rpmhpd_opp_turbo: opp9 { 3684 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3685 }; 3686 3687 rpmhpd_opp_turbo_l1: opp10 { 3688 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3689 }; 3690 }; 3691 }; 3692 3693 apps_bcm_voter: bcm-voter { 3694 compatible = "qcom,bcm-voter"; 3695 }; 3696 }; 3697 3698 cpufreq_hw: cpufreq@18591000 { 3699 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss"; 3700 reg = <0 0x18591000 0 0x1000>, 3701 <0 0x18592000 0 0x1000>, 3702 <0 0x18593000 0 0x1000>; 3703 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3704 3705 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 3706 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3707 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 3708 interrupt-names = "dcvsh-irq-0", 3709 "dcvsh-irq-1", 3710 "dcvsh-irq-2"; 3711 3712 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3713 clock-names = "xo", "alternate"; 3714 3715 #freq-domain-cells = <1>; 3716 #clock-cells = <1>; 3717 }; 3718 }; 3719 3720 thermal_zones: thermal-zones { 3721 cpu0-thermal { 3722 polling-delay-passive = <250>; 3723 3724 thermal-sensors = <&tsens0 1>; 3725 3726 trips { 3727 cpu0_alert0: trip-point0 { 3728 temperature = <90000>; 3729 hysteresis = <2000>; 3730 type = "passive"; 3731 }; 3732 3733 cpu0_alert1: trip-point1 { 3734 temperature = <95000>; 3735 hysteresis = <2000>; 3736 type = "passive"; 3737 }; 3738 3739 cpu0_crit: cpu-crit { 3740 temperature = <110000>; 3741 hysteresis = <1000>; 3742 type = "critical"; 3743 }; 3744 }; 3745 3746 cooling-maps { 3747 map0 { 3748 trip = <&cpu0_alert0>; 3749 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3750 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3751 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3752 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3753 }; 3754 map1 { 3755 trip = <&cpu0_alert1>; 3756 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3757 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3758 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3759 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3760 }; 3761 }; 3762 }; 3763 3764 cpu1-thermal { 3765 polling-delay-passive = <250>; 3766 3767 thermal-sensors = <&tsens0 2>; 3768 3769 trips { 3770 cpu1_alert0: trip-point0 { 3771 temperature = <90000>; 3772 hysteresis = <2000>; 3773 type = "passive"; 3774 }; 3775 3776 cpu1_alert1: trip-point1 { 3777 temperature = <95000>; 3778 hysteresis = <2000>; 3779 type = "passive"; 3780 }; 3781 3782 cpu1_crit: cpu-crit { 3783 temperature = <110000>; 3784 hysteresis = <1000>; 3785 type = "critical"; 3786 }; 3787 }; 3788 3789 cooling-maps { 3790 map0 { 3791 trip = <&cpu1_alert0>; 3792 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3793 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3794 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3795 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3796 }; 3797 map1 { 3798 trip = <&cpu1_alert1>; 3799 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3800 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3801 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3802 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3803 }; 3804 }; 3805 }; 3806 3807 cpu2-thermal { 3808 polling-delay-passive = <250>; 3809 3810 thermal-sensors = <&tsens0 3>; 3811 3812 trips { 3813 cpu2_alert0: trip-point0 { 3814 temperature = <90000>; 3815 hysteresis = <2000>; 3816 type = "passive"; 3817 }; 3818 3819 cpu2_alert1: trip-point1 { 3820 temperature = <95000>; 3821 hysteresis = <2000>; 3822 type = "passive"; 3823 }; 3824 3825 cpu2_crit: cpu-crit { 3826 temperature = <110000>; 3827 hysteresis = <1000>; 3828 type = "critical"; 3829 }; 3830 }; 3831 3832 cooling-maps { 3833 map0 { 3834 trip = <&cpu2_alert0>; 3835 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3836 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3837 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3838 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3839 }; 3840 map1 { 3841 trip = <&cpu2_alert1>; 3842 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3843 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3844 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3845 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3846 }; 3847 }; 3848 }; 3849 3850 cpu3-thermal { 3851 polling-delay-passive = <250>; 3852 3853 thermal-sensors = <&tsens0 4>; 3854 3855 trips { 3856 cpu3_alert0: trip-point0 { 3857 temperature = <90000>; 3858 hysteresis = <2000>; 3859 type = "passive"; 3860 }; 3861 3862 cpu3_alert1: trip-point1 { 3863 temperature = <95000>; 3864 hysteresis = <2000>; 3865 type = "passive"; 3866 }; 3867 3868 cpu3_crit: cpu-crit { 3869 temperature = <110000>; 3870 hysteresis = <1000>; 3871 type = "critical"; 3872 }; 3873 }; 3874 3875 cooling-maps { 3876 map0 { 3877 trip = <&cpu3_alert0>; 3878 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3879 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3880 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3881 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3882 }; 3883 map1 { 3884 trip = <&cpu3_alert1>; 3885 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3886 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3887 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3888 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3889 }; 3890 }; 3891 }; 3892 3893 cpu4-top-thermal { 3894 polling-delay-passive = <250>; 3895 3896 thermal-sensors = <&tsens0 7>; 3897 3898 trips { 3899 cpu4_top_alert0: trip-point0 { 3900 temperature = <90000>; 3901 hysteresis = <2000>; 3902 type = "passive"; 3903 }; 3904 3905 cpu4_top_alert1: trip-point1 { 3906 temperature = <95000>; 3907 hysteresis = <2000>; 3908 type = "passive"; 3909 }; 3910 3911 cpu4_top_crit: cpu-crit { 3912 temperature = <110000>; 3913 hysteresis = <1000>; 3914 type = "critical"; 3915 }; 3916 }; 3917 3918 cooling-maps { 3919 map0 { 3920 trip = <&cpu4_top_alert0>; 3921 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3922 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3923 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3924 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3925 }; 3926 map1 { 3927 trip = <&cpu4_top_alert1>; 3928 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3929 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3930 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3931 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3932 }; 3933 }; 3934 }; 3935 3936 cpu5-top-thermal { 3937 polling-delay-passive = <250>; 3938 3939 thermal-sensors = <&tsens0 8>; 3940 3941 trips { 3942 cpu5_top_alert0: trip-point0 { 3943 temperature = <90000>; 3944 hysteresis = <2000>; 3945 type = "passive"; 3946 }; 3947 3948 cpu5_top_alert1: trip-point1 { 3949 temperature = <95000>; 3950 hysteresis = <2000>; 3951 type = "passive"; 3952 }; 3953 3954 cpu5_top_crit: cpu-crit { 3955 temperature = <110000>; 3956 hysteresis = <1000>; 3957 type = "critical"; 3958 }; 3959 }; 3960 3961 cooling-maps { 3962 map0 { 3963 trip = <&cpu5_top_alert0>; 3964 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3965 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3966 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3967 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3968 }; 3969 map1 { 3970 trip = <&cpu5_top_alert1>; 3971 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3972 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3973 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3974 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3975 }; 3976 }; 3977 }; 3978 3979 cpu6-top-thermal { 3980 polling-delay-passive = <250>; 3981 3982 thermal-sensors = <&tsens0 9>; 3983 3984 trips { 3985 cpu6_top_alert0: trip-point0 { 3986 temperature = <90000>; 3987 hysteresis = <2000>; 3988 type = "passive"; 3989 }; 3990 3991 cpu6_top_alert1: trip-point1 { 3992 temperature = <95000>; 3993 hysteresis = <2000>; 3994 type = "passive"; 3995 }; 3996 3997 cpu6_top_crit: cpu-crit { 3998 temperature = <110000>; 3999 hysteresis = <1000>; 4000 type = "critical"; 4001 }; 4002 }; 4003 4004 cooling-maps { 4005 map0 { 4006 trip = <&cpu6_top_alert0>; 4007 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4008 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4009 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4010 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4011 }; 4012 map1 { 4013 trip = <&cpu6_top_alert1>; 4014 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4015 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4016 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4017 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4018 }; 4019 }; 4020 }; 4021 4022 cpu7-top-thermal { 4023 polling-delay-passive = <250>; 4024 4025 thermal-sensors = <&tsens0 10>; 4026 4027 trips { 4028 cpu7_top_alert0: trip-point0 { 4029 temperature = <90000>; 4030 hysteresis = <2000>; 4031 type = "passive"; 4032 }; 4033 4034 cpu7_top_alert1: trip-point1 { 4035 temperature = <95000>; 4036 hysteresis = <2000>; 4037 type = "passive"; 4038 }; 4039 4040 cpu7_top_crit: cpu-crit { 4041 temperature = <110000>; 4042 hysteresis = <1000>; 4043 type = "critical"; 4044 }; 4045 }; 4046 4047 cooling-maps { 4048 map0 { 4049 trip = <&cpu7_top_alert0>; 4050 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4051 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4052 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4053 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4054 }; 4055 map1 { 4056 trip = <&cpu7_top_alert1>; 4057 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4058 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4059 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4060 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4061 }; 4062 }; 4063 }; 4064 4065 cpu4-bottom-thermal { 4066 polling-delay-passive = <250>; 4067 4068 thermal-sensors = <&tsens0 11>; 4069 4070 trips { 4071 cpu4_bottom_alert0: trip-point0 { 4072 temperature = <90000>; 4073 hysteresis = <2000>; 4074 type = "passive"; 4075 }; 4076 4077 cpu4_bottom_alert1: trip-point1 { 4078 temperature = <95000>; 4079 hysteresis = <2000>; 4080 type = "passive"; 4081 }; 4082 4083 cpu4_bottom_crit: cpu-crit { 4084 temperature = <110000>; 4085 hysteresis = <1000>; 4086 type = "critical"; 4087 }; 4088 }; 4089 4090 cooling-maps { 4091 map0 { 4092 trip = <&cpu4_bottom_alert0>; 4093 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4094 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4095 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4096 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4097 }; 4098 map1 { 4099 trip = <&cpu4_bottom_alert1>; 4100 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4101 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4102 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4103 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4104 }; 4105 }; 4106 }; 4107 4108 cpu5-bottom-thermal { 4109 polling-delay-passive = <250>; 4110 4111 thermal-sensors = <&tsens0 12>; 4112 4113 trips { 4114 cpu5_bottom_alert0: trip-point0 { 4115 temperature = <90000>; 4116 hysteresis = <2000>; 4117 type = "passive"; 4118 }; 4119 4120 cpu5_bottom_alert1: trip-point1 { 4121 temperature = <95000>; 4122 hysteresis = <2000>; 4123 type = "passive"; 4124 }; 4125 4126 cpu5_bottom_crit: cpu-crit { 4127 temperature = <110000>; 4128 hysteresis = <1000>; 4129 type = "critical"; 4130 }; 4131 }; 4132 4133 cooling-maps { 4134 map0 { 4135 trip = <&cpu5_bottom_alert0>; 4136 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4137 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4138 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4139 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4140 }; 4141 map1 { 4142 trip = <&cpu5_bottom_alert1>; 4143 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4144 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4145 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4146 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4147 }; 4148 }; 4149 }; 4150 4151 cpu6-bottom-thermal { 4152 polling-delay-passive = <250>; 4153 4154 thermal-sensors = <&tsens0 13>; 4155 4156 trips { 4157 cpu6_bottom_alert0: trip-point0 { 4158 temperature = <90000>; 4159 hysteresis = <2000>; 4160 type = "passive"; 4161 }; 4162 4163 cpu6_bottom_alert1: trip-point1 { 4164 temperature = <95000>; 4165 hysteresis = <2000>; 4166 type = "passive"; 4167 }; 4168 4169 cpu6_bottom_crit: cpu-crit { 4170 temperature = <110000>; 4171 hysteresis = <1000>; 4172 type = "critical"; 4173 }; 4174 }; 4175 4176 cooling-maps { 4177 map0 { 4178 trip = <&cpu6_bottom_alert0>; 4179 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4180 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4181 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4182 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4183 }; 4184 map1 { 4185 trip = <&cpu6_bottom_alert1>; 4186 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4187 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4188 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4189 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4190 }; 4191 }; 4192 }; 4193 4194 cpu7-bottom-thermal { 4195 polling-delay-passive = <250>; 4196 4197 thermal-sensors = <&tsens0 14>; 4198 4199 trips { 4200 cpu7_bottom_alert0: trip-point0 { 4201 temperature = <90000>; 4202 hysteresis = <2000>; 4203 type = "passive"; 4204 }; 4205 4206 cpu7_bottom_alert1: trip-point1 { 4207 temperature = <95000>; 4208 hysteresis = <2000>; 4209 type = "passive"; 4210 }; 4211 4212 cpu7_bottom_crit: cpu-crit { 4213 temperature = <110000>; 4214 hysteresis = <1000>; 4215 type = "critical"; 4216 }; 4217 }; 4218 4219 cooling-maps { 4220 map0 { 4221 trip = <&cpu7_bottom_alert0>; 4222 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4223 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4224 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4225 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4226 }; 4227 map1 { 4228 trip = <&cpu7_bottom_alert1>; 4229 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4230 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4231 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4232 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4233 }; 4234 }; 4235 }; 4236 4237 aoss0-thermal { 4238 polling-delay-passive = <250>; 4239 4240 thermal-sensors = <&tsens0 0>; 4241 4242 trips { 4243 aoss0_alert0: trip-point0 { 4244 temperature = <90000>; 4245 hysteresis = <2000>; 4246 type = "hot"; 4247 }; 4248 }; 4249 }; 4250 4251 cluster0-thermal { 4252 polling-delay-passive = <250>; 4253 4254 thermal-sensors = <&tsens0 5>; 4255 4256 trips { 4257 cluster0_alert0: trip-point0 { 4258 temperature = <90000>; 4259 hysteresis = <2000>; 4260 type = "hot"; 4261 }; 4262 cluster0_crit: cluster0-crit { 4263 temperature = <110000>; 4264 hysteresis = <2000>; 4265 type = "critical"; 4266 }; 4267 }; 4268 }; 4269 4270 cluster1-thermal { 4271 polling-delay-passive = <250>; 4272 4273 thermal-sensors = <&tsens0 6>; 4274 4275 trips { 4276 cluster1_alert0: trip-point0 { 4277 temperature = <90000>; 4278 hysteresis = <2000>; 4279 type = "hot"; 4280 }; 4281 cluster1_crit: cluster1-crit { 4282 temperature = <110000>; 4283 hysteresis = <2000>; 4284 type = "critical"; 4285 }; 4286 }; 4287 }; 4288 4289 aoss1-thermal { 4290 polling-delay-passive = <250>; 4291 4292 thermal-sensors = <&tsens1 0>; 4293 4294 trips { 4295 aoss1_alert0: trip-point0 { 4296 temperature = <90000>; 4297 hysteresis = <2000>; 4298 type = "hot"; 4299 }; 4300 }; 4301 }; 4302 4303 gpu-top-thermal { 4304 polling-delay-passive = <250>; 4305 4306 thermal-sensors = <&tsens1 1>; 4307 4308 cooling-maps { 4309 map0 { 4310 trip = <&gpu_top_alert0>; 4311 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4312 }; 4313 }; 4314 4315 trips { 4316 gpu_top_alert0: trip-point0 { 4317 temperature = <85000>; 4318 hysteresis = <1000>; 4319 type = "passive"; 4320 }; 4321 4322 trip-point1 { 4323 temperature = <90000>; 4324 hysteresis = <1000>; 4325 type = "hot"; 4326 }; 4327 4328 trip-point2 { 4329 temperature = <110000>; 4330 hysteresis = <1000>; 4331 type = "critical"; 4332 }; 4333 }; 4334 }; 4335 4336 gpu-bottom-thermal { 4337 polling-delay-passive = <250>; 4338 4339 thermal-sensors = <&tsens1 2>; 4340 4341 cooling-maps { 4342 map0 { 4343 trip = <&gpu_bottom_alert0>; 4344 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4345 }; 4346 }; 4347 4348 trips { 4349 gpu_bottom_alert0: trip-point0 { 4350 temperature = <85000>; 4351 hysteresis = <1000>; 4352 type = "passive"; 4353 }; 4354 4355 trip-point1 { 4356 temperature = <90000>; 4357 hysteresis = <1000>; 4358 type = "hot"; 4359 }; 4360 4361 trip-point2 { 4362 temperature = <110000>; 4363 hysteresis = <1000>; 4364 type = "critical"; 4365 }; 4366 }; 4367 }; 4368 4369 nspss1-thermal { 4370 polling-delay-passive = <250>; 4371 4372 thermal-sensors = <&tsens1 3>; 4373 4374 trips { 4375 nspss1_alert0: trip-point0 { 4376 temperature = <90000>; 4377 hysteresis = <1000>; 4378 type = "hot"; 4379 }; 4380 }; 4381 }; 4382 4383 nspss2-thermal { 4384 polling-delay-passive = <250>; 4385 4386 thermal-sensors = <&tsens1 4>; 4387 4388 trips { 4389 nspss2_alert0: trip-point0 { 4390 temperature = <90000>; 4391 hysteresis = <1000>; 4392 type = "hot"; 4393 }; 4394 }; 4395 }; 4396 4397 nspss3-thermal { 4398 polling-delay-passive = <250>; 4399 4400 thermal-sensors = <&tsens1 5>; 4401 4402 trips { 4403 nspss3_alert0: trip-point0 { 4404 temperature = <90000>; 4405 hysteresis = <1000>; 4406 type = "hot"; 4407 }; 4408 }; 4409 }; 4410 4411 video-thermal { 4412 polling-delay-passive = <250>; 4413 4414 thermal-sensors = <&tsens1 6>; 4415 4416 trips { 4417 video_alert0: trip-point0 { 4418 temperature = <90000>; 4419 hysteresis = <2000>; 4420 type = "hot"; 4421 }; 4422 }; 4423 }; 4424 4425 mem-thermal { 4426 polling-delay-passive = <250>; 4427 4428 thermal-sensors = <&tsens1 7>; 4429 4430 trips { 4431 mem_alert0: trip-point0 { 4432 temperature = <90000>; 4433 hysteresis = <2000>; 4434 type = "hot"; 4435 }; 4436 }; 4437 }; 4438 4439 modem1-top-thermal { 4440 polling-delay-passive = <250>; 4441 4442 thermal-sensors = <&tsens1 8>; 4443 4444 trips { 4445 modem1_alert0: trip-point0 { 4446 temperature = <90000>; 4447 hysteresis = <2000>; 4448 type = "hot"; 4449 }; 4450 }; 4451 }; 4452 4453 modem2-top-thermal { 4454 polling-delay-passive = <250>; 4455 4456 thermal-sensors = <&tsens1 9>; 4457 4458 trips { 4459 modem2_alert0: trip-point0 { 4460 temperature = <90000>; 4461 hysteresis = <2000>; 4462 type = "hot"; 4463 }; 4464 }; 4465 }; 4466 4467 modem3-top-thermal { 4468 polling-delay-passive = <250>; 4469 4470 thermal-sensors = <&tsens1 10>; 4471 4472 trips { 4473 modem3_alert0: trip-point0 { 4474 temperature = <90000>; 4475 hysteresis = <2000>; 4476 type = "hot"; 4477 }; 4478 }; 4479 }; 4480 4481 modem4-top-thermal { 4482 polling-delay-passive = <250>; 4483 4484 thermal-sensors = <&tsens1 11>; 4485 4486 trips { 4487 modem4_alert0: trip-point0 { 4488 temperature = <90000>; 4489 hysteresis = <2000>; 4490 type = "hot"; 4491 }; 4492 }; 4493 }; 4494 4495 camera-top-thermal { 4496 polling-delay-passive = <250>; 4497 4498 thermal-sensors = <&tsens1 12>; 4499 4500 trips { 4501 camera1_alert0: trip-point0 { 4502 temperature = <90000>; 4503 hysteresis = <2000>; 4504 type = "hot"; 4505 }; 4506 }; 4507 }; 4508 4509 cam-bottom-thermal { 4510 polling-delay-passive = <250>; 4511 4512 thermal-sensors = <&tsens1 13>; 4513 4514 trips { 4515 camera2_alert0: trip-point0 { 4516 temperature = <90000>; 4517 hysteresis = <2000>; 4518 type = "hot"; 4519 }; 4520 }; 4521 }; 4522 }; 4523 4524 timer { 4525 compatible = "arm,armv8-timer"; 4526 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4527 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4528 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4529 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4530 }; 4531}; 4532