1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Linaro Limited 4 */ 5 6#include <dt-bindings/interconnect/qcom,sm8350.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/qcom,dispcc-sm8350.h> 9#include <dt-bindings/clock/qcom,gcc-sm8350.h> 10#include <dt-bindings/clock/qcom,gpucc-sm8350.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/firmware/qcom,scm.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interconnect/qcom,icc.h> 16#include <dt-bindings/interconnect/qcom,sm8350.h> 17#include <dt-bindings/mailbox/qcom-ipcc.h> 18#include <dt-bindings/phy/phy-qcom-qmp.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/power/qcom,rpmhpd.h> 21#include <dt-bindings/soc/qcom,apr.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23#include <dt-bindings/sound/qcom,q6afe.h> 24#include <dt-bindings/thermal/thermal.h> 25#include <dt-bindings/interconnect/qcom,sm8350.h> 26 27/ { 28 interrupt-parent = <&intc>; 29 30 #address-cells = <2>; 31 #size-cells = <2>; 32 33 chosen { }; 34 35 clocks { 36 xo_board: xo-board { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <38400000>; 40 clock-output-names = "xo_board"; 41 }; 42 43 sleep_clk: sleep-clk { 44 compatible = "fixed-clock"; 45 clock-frequency = <32000>; 46 #clock-cells = <0>; 47 }; 48 }; 49 50 cpus { 51 #address-cells = <2>; 52 #size-cells = <0>; 53 54 CPU0: cpu@0 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a55"; 57 reg = <0x0 0x0>; 58 clocks = <&cpufreq_hw 0>; 59 enable-method = "psci"; 60 next-level-cache = <&L2_0>; 61 qcom,freq-domain = <&cpufreq_hw 0>; 62 power-domains = <&CPU_PD0>; 63 power-domain-names = "psci"; 64 #cooling-cells = <2>; 65 L2_0: l2-cache { 66 compatible = "cache"; 67 cache-level = <2>; 68 cache-unified; 69 next-level-cache = <&L3_0>; 70 L3_0: l3-cache { 71 compatible = "cache"; 72 cache-level = <3>; 73 cache-unified; 74 }; 75 }; 76 }; 77 78 CPU1: cpu@100 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a55"; 81 reg = <0x0 0x100>; 82 clocks = <&cpufreq_hw 0>; 83 enable-method = "psci"; 84 next-level-cache = <&L2_100>; 85 qcom,freq-domain = <&cpufreq_hw 0>; 86 power-domains = <&CPU_PD1>; 87 power-domain-names = "psci"; 88 #cooling-cells = <2>; 89 L2_100: l2-cache { 90 compatible = "cache"; 91 cache-level = <2>; 92 cache-unified; 93 next-level-cache = <&L3_0>; 94 }; 95 }; 96 97 CPU2: cpu@200 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a55"; 100 reg = <0x0 0x200>; 101 clocks = <&cpufreq_hw 0>; 102 enable-method = "psci"; 103 next-level-cache = <&L2_200>; 104 qcom,freq-domain = <&cpufreq_hw 0>; 105 power-domains = <&CPU_PD2>; 106 power-domain-names = "psci"; 107 #cooling-cells = <2>; 108 L2_200: l2-cache { 109 compatible = "cache"; 110 cache-level = <2>; 111 cache-unified; 112 next-level-cache = <&L3_0>; 113 }; 114 }; 115 116 CPU3: cpu@300 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a55"; 119 reg = <0x0 0x300>; 120 clocks = <&cpufreq_hw 0>; 121 enable-method = "psci"; 122 next-level-cache = <&L2_300>; 123 qcom,freq-domain = <&cpufreq_hw 0>; 124 power-domains = <&CPU_PD3>; 125 power-domain-names = "psci"; 126 #cooling-cells = <2>; 127 L2_300: l2-cache { 128 compatible = "cache"; 129 cache-level = <2>; 130 cache-unified; 131 next-level-cache = <&L3_0>; 132 }; 133 }; 134 135 CPU4: cpu@400 { 136 device_type = "cpu"; 137 compatible = "arm,cortex-a78"; 138 reg = <0x0 0x400>; 139 clocks = <&cpufreq_hw 1>; 140 enable-method = "psci"; 141 next-level-cache = <&L2_400>; 142 qcom,freq-domain = <&cpufreq_hw 1>; 143 power-domains = <&CPU_PD4>; 144 power-domain-names = "psci"; 145 #cooling-cells = <2>; 146 L2_400: l2-cache { 147 compatible = "cache"; 148 cache-level = <2>; 149 cache-unified; 150 next-level-cache = <&L3_0>; 151 }; 152 }; 153 154 CPU5: cpu@500 { 155 device_type = "cpu"; 156 compatible = "arm,cortex-a78"; 157 reg = <0x0 0x500>; 158 clocks = <&cpufreq_hw 1>; 159 enable-method = "psci"; 160 next-level-cache = <&L2_500>; 161 qcom,freq-domain = <&cpufreq_hw 1>; 162 power-domains = <&CPU_PD5>; 163 power-domain-names = "psci"; 164 #cooling-cells = <2>; 165 L2_500: l2-cache { 166 compatible = "cache"; 167 cache-level = <2>; 168 cache-unified; 169 next-level-cache = <&L3_0>; 170 }; 171 }; 172 173 CPU6: cpu@600 { 174 device_type = "cpu"; 175 compatible = "arm,cortex-a78"; 176 reg = <0x0 0x600>; 177 clocks = <&cpufreq_hw 1>; 178 enable-method = "psci"; 179 next-level-cache = <&L2_600>; 180 qcom,freq-domain = <&cpufreq_hw 1>; 181 power-domains = <&CPU_PD6>; 182 power-domain-names = "psci"; 183 #cooling-cells = <2>; 184 L2_600: l2-cache { 185 compatible = "cache"; 186 cache-level = <2>; 187 cache-unified; 188 next-level-cache = <&L3_0>; 189 }; 190 }; 191 192 CPU7: cpu@700 { 193 device_type = "cpu"; 194 compatible = "arm,cortex-x1"; 195 reg = <0x0 0x700>; 196 clocks = <&cpufreq_hw 2>; 197 enable-method = "psci"; 198 next-level-cache = <&L2_700>; 199 qcom,freq-domain = <&cpufreq_hw 2>; 200 power-domains = <&CPU_PD7>; 201 power-domain-names = "psci"; 202 #cooling-cells = <2>; 203 L2_700: l2-cache { 204 compatible = "cache"; 205 cache-level = <2>; 206 cache-unified; 207 next-level-cache = <&L3_0>; 208 }; 209 }; 210 211 cpu-map { 212 cluster0 { 213 core0 { 214 cpu = <&CPU0>; 215 }; 216 217 core1 { 218 cpu = <&CPU1>; 219 }; 220 221 core2 { 222 cpu = <&CPU2>; 223 }; 224 225 core3 { 226 cpu = <&CPU3>; 227 }; 228 229 core4 { 230 cpu = <&CPU4>; 231 }; 232 233 core5 { 234 cpu = <&CPU5>; 235 }; 236 237 core6 { 238 cpu = <&CPU6>; 239 }; 240 241 core7 { 242 cpu = <&CPU7>; 243 }; 244 }; 245 }; 246 247 idle-states { 248 entry-method = "psci"; 249 250 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 251 compatible = "arm,idle-state"; 252 idle-state-name = "silver-rail-power-collapse"; 253 arm,psci-suspend-param = <0x40000004>; 254 entry-latency-us = <360>; 255 exit-latency-us = <531>; 256 min-residency-us = <3934>; 257 local-timer-stop; 258 }; 259 260 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 261 compatible = "arm,idle-state"; 262 idle-state-name = "gold-rail-power-collapse"; 263 arm,psci-suspend-param = <0x40000004>; 264 entry-latency-us = <702>; 265 exit-latency-us = <1061>; 266 min-residency-us = <4488>; 267 local-timer-stop; 268 }; 269 }; 270 271 domain-idle-states { 272 CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { 273 compatible = "domain-idle-state"; 274 arm,psci-suspend-param = <0x41000044>; 275 entry-latency-us = <2752>; 276 exit-latency-us = <3048>; 277 min-residency-us = <6118>; 278 }; 279 280 CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 { 281 compatible = "domain-idle-state"; 282 arm,psci-suspend-param = <0x4100c344>; 283 entry-latency-us = <3263>; 284 exit-latency-us = <6562>; 285 min-residency-us = <9987>; 286 }; 287 }; 288 }; 289 290 firmware { 291 scm: scm { 292 compatible = "qcom,scm-sm8350", "qcom,scm"; 293 qcom,dload-mode = <&tcsr 0x13000>; 294 #reset-cells = <1>; 295 }; 296 }; 297 298 memory@80000000 { 299 device_type = "memory"; 300 /* We expect the bootloader to fill in the size */ 301 reg = <0x0 0x80000000 0x0 0x0>; 302 }; 303 304 pmu-a55 { 305 compatible = "arm,cortex-a55-pmu"; 306 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 307 }; 308 309 pmu-a78 { 310 compatible = "arm,cortex-a78-pmu"; 311 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 312 }; 313 314 pmu-x1 { 315 compatible = "arm,cortex-x1-pmu"; 316 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 317 }; 318 319 psci { 320 compatible = "arm,psci-1.0"; 321 method = "smc"; 322 323 CPU_PD0: power-domain-cpu0 { 324 #power-domain-cells = <0>; 325 power-domains = <&CLUSTER_PD>; 326 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 327 }; 328 329 CPU_PD1: power-domain-cpu1 { 330 #power-domain-cells = <0>; 331 power-domains = <&CLUSTER_PD>; 332 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 333 }; 334 335 CPU_PD2: power-domain-cpu2 { 336 #power-domain-cells = <0>; 337 power-domains = <&CLUSTER_PD>; 338 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 339 }; 340 341 CPU_PD3: power-domain-cpu3 { 342 #power-domain-cells = <0>; 343 power-domains = <&CLUSTER_PD>; 344 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 345 }; 346 347 CPU_PD4: power-domain-cpu4 { 348 #power-domain-cells = <0>; 349 power-domains = <&CLUSTER_PD>; 350 domain-idle-states = <&BIG_CPU_SLEEP_0>; 351 }; 352 353 CPU_PD5: power-domain-cpu5 { 354 #power-domain-cells = <0>; 355 power-domains = <&CLUSTER_PD>; 356 domain-idle-states = <&BIG_CPU_SLEEP_0>; 357 }; 358 359 CPU_PD6: power-domain-cpu6 { 360 #power-domain-cells = <0>; 361 power-domains = <&CLUSTER_PD>; 362 domain-idle-states = <&BIG_CPU_SLEEP_0>; 363 }; 364 365 CPU_PD7: power-domain-cpu7 { 366 #power-domain-cells = <0>; 367 power-domains = <&CLUSTER_PD>; 368 domain-idle-states = <&BIG_CPU_SLEEP_0>; 369 }; 370 371 CLUSTER_PD: power-domain-cpu-cluster0 { 372 #power-domain-cells = <0>; 373 domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLEEP>; 374 }; 375 }; 376 377 qup_opp_table_100mhz: opp-table-qup100mhz { 378 compatible = "operating-points-v2"; 379 380 opp-50000000 { 381 opp-hz = /bits/ 64 <50000000>; 382 required-opps = <&rpmhpd_opp_min_svs>; 383 }; 384 385 opp-75000000 { 386 opp-hz = /bits/ 64 <75000000>; 387 required-opps = <&rpmhpd_opp_low_svs>; 388 }; 389 390 opp-100000000 { 391 opp-hz = /bits/ 64 <100000000>; 392 required-opps = <&rpmhpd_opp_svs>; 393 }; 394 }; 395 396 qup_opp_table_120mhz: opp-table-qup120mhz { 397 compatible = "operating-points-v2"; 398 399 opp-50000000 { 400 opp-hz = /bits/ 64 <50000000>; 401 required-opps = <&rpmhpd_opp_min_svs>; 402 }; 403 404 opp-75000000 { 405 opp-hz = /bits/ 64 <75000000>; 406 required-opps = <&rpmhpd_opp_low_svs>; 407 }; 408 409 opp-120000000 { 410 opp-hz = /bits/ 64 <120000000>; 411 required-opps = <&rpmhpd_opp_svs>; 412 }; 413 }; 414 415 reserved_memory: reserved-memory { 416 #address-cells = <2>; 417 #size-cells = <2>; 418 ranges; 419 420 hyp_mem: memory@80000000 { 421 reg = <0x0 0x80000000 0x0 0x600000>; 422 no-map; 423 }; 424 425 xbl_aop_mem: memory@80700000 { 426 no-map; 427 reg = <0x0 0x80700000 0x0 0x160000>; 428 }; 429 430 cmd_db: memory@80860000 { 431 compatible = "qcom,cmd-db"; 432 reg = <0x0 0x80860000 0x0 0x20000>; 433 no-map; 434 }; 435 436 reserved_xbl_uefi_log: memory@80880000 { 437 reg = <0x0 0x80880000 0x0 0x14000>; 438 no-map; 439 }; 440 441 smem@80900000 { 442 compatible = "qcom,smem"; 443 reg = <0x0 0x80900000 0x0 0x200000>; 444 hwlocks = <&tcsr_mutex 3>; 445 no-map; 446 }; 447 448 cpucp_fw_mem: memory@80b00000 { 449 reg = <0x0 0x80b00000 0x0 0x100000>; 450 no-map; 451 }; 452 453 cdsp_secure_heap: memory@80c00000 { 454 reg = <0x0 0x80c00000 0x0 0x4600000>; 455 no-map; 456 }; 457 458 pil_camera_mem: mmeory@85200000 { 459 reg = <0x0 0x85200000 0x0 0x500000>; 460 no-map; 461 }; 462 463 pil_video_mem: memory@85700000 { 464 reg = <0x0 0x85700000 0x0 0x500000>; 465 no-map; 466 }; 467 468 pil_cvp_mem: memory@85c00000 { 469 reg = <0x0 0x85c00000 0x0 0x500000>; 470 no-map; 471 }; 472 473 pil_adsp_mem: memory@86100000 { 474 reg = <0x0 0x86100000 0x0 0x2100000>; 475 no-map; 476 }; 477 478 pil_slpi_mem: memory@88200000 { 479 reg = <0x0 0x88200000 0x0 0x1500000>; 480 no-map; 481 }; 482 483 pil_cdsp_mem: memory@89700000 { 484 reg = <0x0 0x89700000 0x0 0x1e00000>; 485 no-map; 486 }; 487 488 pil_ipa_fw_mem: memory@8b500000 { 489 reg = <0x0 0x8b500000 0x0 0x10000>; 490 no-map; 491 }; 492 493 pil_ipa_gsi_mem: memory@8b510000 { 494 reg = <0x0 0x8b510000 0x0 0xa000>; 495 no-map; 496 }; 497 498 pil_gpu_mem: memory@8b51a000 { 499 reg = <0x0 0x8b51a000 0x0 0x2000>; 500 no-map; 501 }; 502 503 pil_spss_mem: memory@8b600000 { 504 reg = <0x0 0x8b600000 0x0 0x100000>; 505 no-map; 506 }; 507 508 pil_modem_mem: memory@8b800000 { 509 reg = <0x0 0x8b800000 0x0 0x10000000>; 510 no-map; 511 }; 512 513 rmtfs_mem: memory@9b800000 { 514 compatible = "qcom,rmtfs-mem"; 515 reg = <0x0 0x9b800000 0x0 0x280000>; 516 no-map; 517 518 qcom,client-id = <1>; 519 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 520 }; 521 522 hyp_reserved_mem: memory@d0000000 { 523 reg = <0x0 0xd0000000 0x0 0x800000>; 524 no-map; 525 }; 526 527 pil_trustedvm_mem: memory@d0800000 { 528 reg = <0x0 0xd0800000 0x0 0x76f7000>; 529 no-map; 530 }; 531 532 qrtr_shbuf: memory@d7ef7000 { 533 reg = <0x0 0xd7ef7000 0x0 0x9000>; 534 no-map; 535 }; 536 537 chan0_shbuf: memory@d7f00000 { 538 reg = <0x0 0xd7f00000 0x0 0x80000>; 539 no-map; 540 }; 541 542 chan1_shbuf: memory@d7f80000 { 543 reg = <0x0 0xd7f80000 0x0 0x80000>; 544 no-map; 545 }; 546 547 removed_mem: memory@d8800000 { 548 reg = <0x0 0xd8800000 0x0 0x6800000>; 549 no-map; 550 }; 551 }; 552 553 smp2p-adsp { 554 compatible = "qcom,smp2p"; 555 qcom,smem = <443>, <429>; 556 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 557 IPCC_MPROC_SIGNAL_SMP2P 558 IRQ_TYPE_EDGE_RISING>; 559 mboxes = <&ipcc IPCC_CLIENT_LPASS 560 IPCC_MPROC_SIGNAL_SMP2P>; 561 562 qcom,local-pid = <0>; 563 qcom,remote-pid = <2>; 564 565 smp2p_adsp_out: master-kernel { 566 qcom,entry-name = "master-kernel"; 567 #qcom,smem-state-cells = <1>; 568 }; 569 570 smp2p_adsp_in: slave-kernel { 571 qcom,entry-name = "slave-kernel"; 572 interrupt-controller; 573 #interrupt-cells = <2>; 574 }; 575 }; 576 577 smp2p-cdsp { 578 compatible = "qcom,smp2p"; 579 qcom,smem = <94>, <432>; 580 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 581 IPCC_MPROC_SIGNAL_SMP2P 582 IRQ_TYPE_EDGE_RISING>; 583 mboxes = <&ipcc IPCC_CLIENT_CDSP 584 IPCC_MPROC_SIGNAL_SMP2P>; 585 586 qcom,local-pid = <0>; 587 qcom,remote-pid = <5>; 588 589 smp2p_cdsp_out: master-kernel { 590 qcom,entry-name = "master-kernel"; 591 #qcom,smem-state-cells = <1>; 592 }; 593 594 smp2p_cdsp_in: slave-kernel { 595 qcom,entry-name = "slave-kernel"; 596 interrupt-controller; 597 #interrupt-cells = <2>; 598 }; 599 }; 600 601 smp2p-modem { 602 compatible = "qcom,smp2p"; 603 qcom,smem = <435>, <428>; 604 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 605 IPCC_MPROC_SIGNAL_SMP2P 606 IRQ_TYPE_EDGE_RISING>; 607 mboxes = <&ipcc IPCC_CLIENT_MPSS 608 IPCC_MPROC_SIGNAL_SMP2P>; 609 610 qcom,local-pid = <0>; 611 qcom,remote-pid = <1>; 612 613 smp2p_modem_out: master-kernel { 614 qcom,entry-name = "master-kernel"; 615 #qcom,smem-state-cells = <1>; 616 }; 617 618 smp2p_modem_in: slave-kernel { 619 qcom,entry-name = "slave-kernel"; 620 interrupt-controller; 621 #interrupt-cells = <2>; 622 }; 623 624 ipa_smp2p_out: ipa-ap-to-modem { 625 qcom,entry-name = "ipa"; 626 #qcom,smem-state-cells = <1>; 627 }; 628 629 ipa_smp2p_in: ipa-modem-to-ap { 630 qcom,entry-name = "ipa"; 631 interrupt-controller; 632 #interrupt-cells = <2>; 633 }; 634 }; 635 636 smp2p-slpi { 637 compatible = "qcom,smp2p"; 638 qcom,smem = <481>, <430>; 639 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 640 IPCC_MPROC_SIGNAL_SMP2P 641 IRQ_TYPE_EDGE_RISING>; 642 mboxes = <&ipcc IPCC_CLIENT_SLPI 643 IPCC_MPROC_SIGNAL_SMP2P>; 644 645 qcom,local-pid = <0>; 646 qcom,remote-pid = <3>; 647 648 smp2p_slpi_out: master-kernel { 649 qcom,entry-name = "master-kernel"; 650 #qcom,smem-state-cells = <1>; 651 }; 652 653 smp2p_slpi_in: slave-kernel { 654 qcom,entry-name = "slave-kernel"; 655 interrupt-controller; 656 #interrupt-cells = <2>; 657 }; 658 }; 659 660 soc: soc@0 { 661 #address-cells = <2>; 662 #size-cells = <2>; 663 ranges = <0 0 0 0 0x10 0>; 664 dma-ranges = <0 0 0 0 0x10 0>; 665 compatible = "simple-bus"; 666 667 gcc: clock-controller@100000 { 668 compatible = "qcom,gcc-sm8350"; 669 reg = <0x0 0x00100000 0x0 0x1f0000>; 670 #clock-cells = <1>; 671 #reset-cells = <1>; 672 #power-domain-cells = <1>; 673 clock-names = "bi_tcxo", 674 "sleep_clk", 675 "pcie_0_pipe_clk", 676 "pcie_1_pipe_clk", 677 "ufs_card_rx_symbol_0_clk", 678 "ufs_card_rx_symbol_1_clk", 679 "ufs_card_tx_symbol_0_clk", 680 "ufs_phy_rx_symbol_0_clk", 681 "ufs_phy_rx_symbol_1_clk", 682 "ufs_phy_tx_symbol_0_clk", 683 "usb3_phy_wrapper_gcc_usb30_pipe_clk", 684 "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; 685 clocks = <&rpmhcc RPMH_CXO_CLK>, 686 <&sleep_clk>, 687 <&pcie0_phy>, 688 <&pcie1_phy>, 689 <0>, 690 <0>, 691 <0>, 692 <&ufs_mem_phy 0>, 693 <&ufs_mem_phy 1>, 694 <&ufs_mem_phy 2>, 695 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 696 <0>; 697 }; 698 699 ipcc: mailbox@408000 { 700 compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; 701 reg = <0 0x00408000 0 0x1000>; 702 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 703 interrupt-controller; 704 #interrupt-cells = <3>; 705 #mbox-cells = <2>; 706 }; 707 708 gpi_dma2: dma-controller@800000 { 709 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 710 reg = <0 0x00800000 0 0x60000>; 711 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 723 dma-channels = <12>; 724 dma-channel-mask = <0xff>; 725 iommus = <&apps_smmu 0x5f6 0x0>; 726 #dma-cells = <3>; 727 status = "disabled"; 728 }; 729 730 qupv3_id_2: geniqup@8c0000 { 731 compatible = "qcom,geni-se-qup"; 732 reg = <0x0 0x008c0000 0x0 0x6000>; 733 clock-names = "m-ahb", "s-ahb"; 734 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 735 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 736 iommus = <&apps_smmu 0x5e3 0x0>; 737 #address-cells = <2>; 738 #size-cells = <2>; 739 ranges; 740 status = "disabled"; 741 742 i2c14: i2c@880000 { 743 compatible = "qcom,geni-i2c"; 744 reg = <0 0x00880000 0 0x4000>; 745 clock-names = "se"; 746 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 747 pinctrl-names = "default"; 748 pinctrl-0 = <&qup_i2c14_default>; 749 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 750 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 751 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 752 dma-names = "tx", "rx"; 753 #address-cells = <1>; 754 #size-cells = <0>; 755 status = "disabled"; 756 }; 757 758 spi14: spi@880000 { 759 compatible = "qcom,geni-spi"; 760 reg = <0 0x00880000 0 0x4000>; 761 clock-names = "se"; 762 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 763 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 764 power-domains = <&rpmhpd RPMHPD_CX>; 765 operating-points-v2 = <&qup_opp_table_120mhz>; 766 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 767 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 768 dma-names = "tx", "rx"; 769 #address-cells = <1>; 770 #size-cells = <0>; 771 status = "disabled"; 772 }; 773 774 i2c15: i2c@884000 { 775 compatible = "qcom,geni-i2c"; 776 reg = <0 0x00884000 0 0x4000>; 777 clock-names = "se"; 778 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 779 pinctrl-names = "default"; 780 pinctrl-0 = <&qup_i2c15_default>; 781 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 782 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 783 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 784 dma-names = "tx", "rx"; 785 #address-cells = <1>; 786 #size-cells = <0>; 787 status = "disabled"; 788 }; 789 790 spi15: spi@884000 { 791 compatible = "qcom,geni-spi"; 792 reg = <0 0x00884000 0 0x4000>; 793 clock-names = "se"; 794 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 795 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 796 power-domains = <&rpmhpd RPMHPD_CX>; 797 operating-points-v2 = <&qup_opp_table_120mhz>; 798 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 799 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 800 dma-names = "tx", "rx"; 801 #address-cells = <1>; 802 #size-cells = <0>; 803 status = "disabled"; 804 }; 805 806 i2c16: i2c@888000 { 807 compatible = "qcom,geni-i2c"; 808 reg = <0 0x00888000 0 0x4000>; 809 clock-names = "se"; 810 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 811 pinctrl-names = "default"; 812 pinctrl-0 = <&qup_i2c16_default>; 813 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 814 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 815 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 816 dma-names = "tx", "rx"; 817 #address-cells = <1>; 818 #size-cells = <0>; 819 status = "disabled"; 820 }; 821 822 spi16: spi@888000 { 823 compatible = "qcom,geni-spi"; 824 reg = <0 0x00888000 0 0x4000>; 825 clock-names = "se"; 826 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 827 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 828 power-domains = <&rpmhpd RPMHPD_CX>; 829 operating-points-v2 = <&qup_opp_table_100mhz>; 830 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 831 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 832 dma-names = "tx", "rx"; 833 #address-cells = <1>; 834 #size-cells = <0>; 835 status = "disabled"; 836 }; 837 838 i2c17: i2c@88c000 { 839 compatible = "qcom,geni-i2c"; 840 reg = <0 0x0088c000 0 0x4000>; 841 clock-names = "se"; 842 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 843 pinctrl-names = "default"; 844 pinctrl-0 = <&qup_i2c17_default>; 845 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 846 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 847 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 848 dma-names = "tx", "rx"; 849 #address-cells = <1>; 850 #size-cells = <0>; 851 status = "disabled"; 852 }; 853 854 spi17: spi@88c000 { 855 compatible = "qcom,geni-spi"; 856 reg = <0 0x0088c000 0 0x4000>; 857 clock-names = "se"; 858 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 859 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 860 power-domains = <&rpmhpd RPMHPD_CX>; 861 operating-points-v2 = <&qup_opp_table_100mhz>; 862 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 863 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 864 dma-names = "tx", "rx"; 865 #address-cells = <1>; 866 #size-cells = <0>; 867 status = "disabled"; 868 }; 869 870 /* QUP no. 18 seems to be strictly SPI/UART-only */ 871 872 spi18: spi@890000 { 873 compatible = "qcom,geni-spi"; 874 reg = <0 0x00890000 0 0x4000>; 875 clock-names = "se"; 876 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 877 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 878 power-domains = <&rpmhpd RPMHPD_CX>; 879 operating-points-v2 = <&qup_opp_table_100mhz>; 880 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 881 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 882 dma-names = "tx", "rx"; 883 #address-cells = <1>; 884 #size-cells = <0>; 885 status = "disabled"; 886 }; 887 888 uart18: serial@890000 { 889 compatible = "qcom,geni-uart"; 890 reg = <0 0x00890000 0 0x4000>; 891 clock-names = "se"; 892 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 893 pinctrl-names = "default"; 894 pinctrl-0 = <&qup_uart18_default>; 895 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 896 power-domains = <&rpmhpd RPMHPD_CX>; 897 operating-points-v2 = <&qup_opp_table_100mhz>; 898 status = "disabled"; 899 }; 900 901 i2c19: i2c@894000 { 902 compatible = "qcom,geni-i2c"; 903 reg = <0 0x00894000 0 0x4000>; 904 clock-names = "se"; 905 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 906 pinctrl-names = "default"; 907 pinctrl-0 = <&qup_i2c19_default>; 908 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 909 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 910 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 911 dma-names = "tx", "rx"; 912 #address-cells = <1>; 913 #size-cells = <0>; 914 status = "disabled"; 915 }; 916 917 spi19: spi@894000 { 918 compatible = "qcom,geni-spi"; 919 reg = <0 0x00894000 0 0x4000>; 920 clock-names = "se"; 921 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 922 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 923 power-domains = <&rpmhpd RPMHPD_CX>; 924 operating-points-v2 = <&qup_opp_table_100mhz>; 925 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 926 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 927 dma-names = "tx", "rx"; 928 #address-cells = <1>; 929 #size-cells = <0>; 930 status = "disabled"; 931 }; 932 }; 933 934 gpi_dma0: dma-controller@900000 { 935 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 936 reg = <0 0x00900000 0 0x60000>; 937 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 949 dma-channels = <12>; 950 dma-channel-mask = <0x7e>; 951 iommus = <&apps_smmu 0x5b6 0x0>; 952 #dma-cells = <3>; 953 status = "disabled"; 954 }; 955 956 qupv3_id_0: geniqup@9c0000 { 957 compatible = "qcom,geni-se-qup"; 958 reg = <0x0 0x009c0000 0x0 0x6000>; 959 clock-names = "m-ahb", "s-ahb"; 960 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 961 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 962 iommus = <&apps_smmu 0x5a3 0>; 963 #address-cells = <2>; 964 #size-cells = <2>; 965 ranges; 966 status = "disabled"; 967 968 i2c0: i2c@980000 { 969 compatible = "qcom,geni-i2c"; 970 reg = <0 0x00980000 0 0x4000>; 971 clock-names = "se"; 972 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 973 pinctrl-names = "default"; 974 pinctrl-0 = <&qup_i2c0_default>; 975 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 976 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 977 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 978 dma-names = "tx", "rx"; 979 #address-cells = <1>; 980 #size-cells = <0>; 981 status = "disabled"; 982 }; 983 984 spi0: spi@980000 { 985 compatible = "qcom,geni-spi"; 986 reg = <0 0x00980000 0 0x4000>; 987 clock-names = "se"; 988 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 989 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 990 power-domains = <&rpmhpd RPMHPD_CX>; 991 operating-points-v2 = <&qup_opp_table_100mhz>; 992 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 993 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 994 dma-names = "tx", "rx"; 995 #address-cells = <1>; 996 #size-cells = <0>; 997 status = "disabled"; 998 }; 999 1000 i2c1: i2c@984000 { 1001 compatible = "qcom,geni-i2c"; 1002 reg = <0 0x00984000 0 0x4000>; 1003 clock-names = "se"; 1004 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1005 pinctrl-names = "default"; 1006 pinctrl-0 = <&qup_i2c1_default>; 1007 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1008 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1009 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1010 dma-names = "tx", "rx"; 1011 #address-cells = <1>; 1012 #size-cells = <0>; 1013 status = "disabled"; 1014 }; 1015 1016 spi1: spi@984000 { 1017 compatible = "qcom,geni-spi"; 1018 reg = <0 0x00984000 0 0x4000>; 1019 clock-names = "se"; 1020 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1021 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1022 power-domains = <&rpmhpd RPMHPD_CX>; 1023 operating-points-v2 = <&qup_opp_table_100mhz>; 1024 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1025 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1026 dma-names = "tx", "rx"; 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 status = "disabled"; 1030 }; 1031 1032 i2c2: i2c@988000 { 1033 compatible = "qcom,geni-i2c"; 1034 reg = <0 0x00988000 0 0x4000>; 1035 clock-names = "se"; 1036 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1037 pinctrl-names = "default"; 1038 pinctrl-0 = <&qup_i2c2_default>; 1039 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1040 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1041 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1042 dma-names = "tx", "rx"; 1043 #address-cells = <1>; 1044 #size-cells = <0>; 1045 status = "disabled"; 1046 }; 1047 1048 spi2: spi@988000 { 1049 compatible = "qcom,geni-spi"; 1050 reg = <0 0x00988000 0 0x4000>; 1051 clock-names = "se"; 1052 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1053 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1054 power-domains = <&rpmhpd RPMHPD_CX>; 1055 operating-points-v2 = <&qup_opp_table_100mhz>; 1056 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1057 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1058 dma-names = "tx", "rx"; 1059 #address-cells = <1>; 1060 #size-cells = <0>; 1061 status = "disabled"; 1062 }; 1063 1064 uart2: serial@98c000 { 1065 compatible = "qcom,geni-debug-uart"; 1066 reg = <0 0x0098c000 0 0x4000>; 1067 clock-names = "se"; 1068 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1069 pinctrl-names = "default"; 1070 pinctrl-0 = <&qup_uart3_default_state>; 1071 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1072 power-domains = <&rpmhpd RPMHPD_CX>; 1073 operating-points-v2 = <&qup_opp_table_100mhz>; 1074 status = "disabled"; 1075 }; 1076 1077 /* QUP no. 3 seems to be strictly SPI-only */ 1078 1079 spi3: spi@98c000 { 1080 compatible = "qcom,geni-spi"; 1081 reg = <0 0x0098c000 0 0x4000>; 1082 clock-names = "se"; 1083 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1084 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1085 power-domains = <&rpmhpd RPMHPD_CX>; 1086 operating-points-v2 = <&qup_opp_table_100mhz>; 1087 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1088 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1089 dma-names = "tx", "rx"; 1090 #address-cells = <1>; 1091 #size-cells = <0>; 1092 status = "disabled"; 1093 }; 1094 1095 i2c4: i2c@990000 { 1096 compatible = "qcom,geni-i2c"; 1097 reg = <0 0x00990000 0 0x4000>; 1098 clock-names = "se"; 1099 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1100 pinctrl-names = "default"; 1101 pinctrl-0 = <&qup_i2c4_default>; 1102 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1103 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1104 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1105 dma-names = "tx", "rx"; 1106 #address-cells = <1>; 1107 #size-cells = <0>; 1108 status = "disabled"; 1109 }; 1110 1111 spi4: spi@990000 { 1112 compatible = "qcom,geni-spi"; 1113 reg = <0 0x00990000 0 0x4000>; 1114 clock-names = "se"; 1115 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1116 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1117 power-domains = <&rpmhpd RPMHPD_CX>; 1118 operating-points-v2 = <&qup_opp_table_100mhz>; 1119 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1120 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1121 dma-names = "tx", "rx"; 1122 #address-cells = <1>; 1123 #size-cells = <0>; 1124 status = "disabled"; 1125 }; 1126 1127 i2c5: i2c@994000 { 1128 compatible = "qcom,geni-i2c"; 1129 reg = <0 0x00994000 0 0x4000>; 1130 clock-names = "se"; 1131 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1132 pinctrl-names = "default"; 1133 pinctrl-0 = <&qup_i2c5_default>; 1134 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1135 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1136 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1137 dma-names = "tx", "rx"; 1138 #address-cells = <1>; 1139 #size-cells = <0>; 1140 status = "disabled"; 1141 }; 1142 1143 spi5: spi@994000 { 1144 compatible = "qcom,geni-spi"; 1145 reg = <0 0x00994000 0 0x4000>; 1146 clock-names = "se"; 1147 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1148 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1149 power-domains = <&rpmhpd RPMHPD_CX>; 1150 operating-points-v2 = <&qup_opp_table_100mhz>; 1151 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1152 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1153 dma-names = "tx", "rx"; 1154 #address-cells = <1>; 1155 #size-cells = <0>; 1156 status = "disabled"; 1157 }; 1158 1159 i2c6: i2c@998000 { 1160 compatible = "qcom,geni-i2c"; 1161 reg = <0 0x00998000 0 0x4000>; 1162 clock-names = "se"; 1163 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1164 pinctrl-names = "default"; 1165 pinctrl-0 = <&qup_i2c6_default>; 1166 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1167 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1168 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1169 dma-names = "tx", "rx"; 1170 #address-cells = <1>; 1171 #size-cells = <0>; 1172 status = "disabled"; 1173 }; 1174 1175 spi6: spi@998000 { 1176 compatible = "qcom,geni-spi"; 1177 reg = <0 0x00998000 0 0x4000>; 1178 clock-names = "se"; 1179 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1180 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1181 power-domains = <&rpmhpd RPMHPD_CX>; 1182 operating-points-v2 = <&qup_opp_table_100mhz>; 1183 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1184 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1185 dma-names = "tx", "rx"; 1186 #address-cells = <1>; 1187 #size-cells = <0>; 1188 status = "disabled"; 1189 }; 1190 1191 uart6: serial@998000 { 1192 compatible = "qcom,geni-uart"; 1193 reg = <0 0x00998000 0 0x4000>; 1194 clock-names = "se"; 1195 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1196 pinctrl-names = "default"; 1197 pinctrl-0 = <&qup_uart6_default>; 1198 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1199 power-domains = <&rpmhpd RPMHPD_CX>; 1200 operating-points-v2 = <&qup_opp_table_100mhz>; 1201 status = "disabled"; 1202 }; 1203 1204 i2c7: i2c@99c000 { 1205 compatible = "qcom,geni-i2c"; 1206 reg = <0 0x0099c000 0 0x4000>; 1207 clock-names = "se"; 1208 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1209 pinctrl-names = "default"; 1210 pinctrl-0 = <&qup_i2c7_default>; 1211 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1212 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1213 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1214 dma-names = "tx", "rx"; 1215 #address-cells = <1>; 1216 #size-cells = <0>; 1217 status = "disabled"; 1218 }; 1219 1220 spi7: spi@99c000 { 1221 compatible = "qcom,geni-spi"; 1222 reg = <0 0x0099c000 0 0x4000>; 1223 clock-names = "se"; 1224 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1225 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1226 power-domains = <&rpmhpd RPMHPD_CX>; 1227 operating-points-v2 = <&qup_opp_table_100mhz>; 1228 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1229 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1230 dma-names = "tx", "rx"; 1231 #address-cells = <1>; 1232 #size-cells = <0>; 1233 status = "disabled"; 1234 }; 1235 }; 1236 1237 gpi_dma1: dma-controller@a00000 { 1238 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 1239 reg = <0 0x00a00000 0 0x60000>; 1240 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1252 dma-channels = <12>; 1253 dma-channel-mask = <0xff>; 1254 iommus = <&apps_smmu 0x56 0x0>; 1255 #dma-cells = <3>; 1256 status = "disabled"; 1257 }; 1258 1259 qupv3_id_1: geniqup@ac0000 { 1260 compatible = "qcom,geni-se-qup"; 1261 reg = <0x0 0x00ac0000 0x0 0x6000>; 1262 clock-names = "m-ahb", "s-ahb"; 1263 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1264 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1265 iommus = <&apps_smmu 0x43 0>; 1266 #address-cells = <2>; 1267 #size-cells = <2>; 1268 ranges; 1269 status = "disabled"; 1270 1271 i2c8: i2c@a80000 { 1272 compatible = "qcom,geni-i2c"; 1273 reg = <0 0x00a80000 0 0x4000>; 1274 clock-names = "se"; 1275 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1276 pinctrl-names = "default"; 1277 pinctrl-0 = <&qup_i2c8_default>; 1278 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1279 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1280 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1281 dma-names = "tx", "rx"; 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 status = "disabled"; 1285 }; 1286 1287 spi8: spi@a80000 { 1288 compatible = "qcom,geni-spi"; 1289 reg = <0 0x00a80000 0 0x4000>; 1290 clock-names = "se"; 1291 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1292 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1293 power-domains = <&rpmhpd RPMHPD_CX>; 1294 operating-points-v2 = <&qup_opp_table_120mhz>; 1295 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1296 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1297 dma-names = "tx", "rx"; 1298 #address-cells = <1>; 1299 #size-cells = <0>; 1300 status = "disabled"; 1301 }; 1302 1303 i2c9: i2c@a84000 { 1304 compatible = "qcom,geni-i2c"; 1305 reg = <0 0x00a84000 0 0x4000>; 1306 clock-names = "se"; 1307 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1308 pinctrl-names = "default"; 1309 pinctrl-0 = <&qup_i2c9_default>; 1310 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1311 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1312 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1313 dma-names = "tx", "rx"; 1314 #address-cells = <1>; 1315 #size-cells = <0>; 1316 status = "disabled"; 1317 }; 1318 1319 spi9: spi@a84000 { 1320 compatible = "qcom,geni-spi"; 1321 reg = <0 0x00a84000 0 0x4000>; 1322 clock-names = "se"; 1323 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1324 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1325 power-domains = <&rpmhpd RPMHPD_CX>; 1326 operating-points-v2 = <&qup_opp_table_100mhz>; 1327 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1328 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1329 dma-names = "tx", "rx"; 1330 #address-cells = <1>; 1331 #size-cells = <0>; 1332 status = "disabled"; 1333 }; 1334 1335 i2c10: i2c@a88000 { 1336 compatible = "qcom,geni-i2c"; 1337 reg = <0 0x00a88000 0 0x4000>; 1338 clock-names = "se"; 1339 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1340 pinctrl-names = "default"; 1341 pinctrl-0 = <&qup_i2c10_default>; 1342 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1343 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1344 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1345 dma-names = "tx", "rx"; 1346 #address-cells = <1>; 1347 #size-cells = <0>; 1348 status = "disabled"; 1349 }; 1350 1351 spi10: spi@a88000 { 1352 compatible = "qcom,geni-spi"; 1353 reg = <0 0x00a88000 0 0x4000>; 1354 clock-names = "se"; 1355 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1356 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1357 power-domains = <&rpmhpd RPMHPD_CX>; 1358 operating-points-v2 = <&qup_opp_table_100mhz>; 1359 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1360 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1361 dma-names = "tx", "rx"; 1362 #address-cells = <1>; 1363 #size-cells = <0>; 1364 status = "disabled"; 1365 }; 1366 1367 i2c11: i2c@a8c000 { 1368 compatible = "qcom,geni-i2c"; 1369 reg = <0 0x00a8c000 0 0x4000>; 1370 clock-names = "se"; 1371 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1372 pinctrl-names = "default"; 1373 pinctrl-0 = <&qup_i2c11_default>; 1374 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1375 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1376 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1377 dma-names = "tx", "rx"; 1378 #address-cells = <1>; 1379 #size-cells = <0>; 1380 status = "disabled"; 1381 }; 1382 1383 spi11: spi@a8c000 { 1384 compatible = "qcom,geni-spi"; 1385 reg = <0 0x00a8c000 0 0x4000>; 1386 clock-names = "se"; 1387 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1388 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1389 power-domains = <&rpmhpd RPMHPD_CX>; 1390 operating-points-v2 = <&qup_opp_table_100mhz>; 1391 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1392 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1393 dma-names = "tx", "rx"; 1394 #address-cells = <1>; 1395 #size-cells = <0>; 1396 status = "disabled"; 1397 }; 1398 1399 i2c12: i2c@a90000 { 1400 compatible = "qcom,geni-i2c"; 1401 reg = <0 0x00a90000 0 0x4000>; 1402 clock-names = "se"; 1403 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1404 pinctrl-names = "default"; 1405 pinctrl-0 = <&qup_i2c12_default>; 1406 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1407 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1408 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1409 dma-names = "tx", "rx"; 1410 #address-cells = <1>; 1411 #size-cells = <0>; 1412 status = "disabled"; 1413 }; 1414 1415 spi12: spi@a90000 { 1416 compatible = "qcom,geni-spi"; 1417 reg = <0 0x00a90000 0 0x4000>; 1418 clock-names = "se"; 1419 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1420 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1421 power-domains = <&rpmhpd RPMHPD_CX>; 1422 operating-points-v2 = <&qup_opp_table_100mhz>; 1423 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1424 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1425 dma-names = "tx", "rx"; 1426 #address-cells = <1>; 1427 #size-cells = <0>; 1428 status = "disabled"; 1429 }; 1430 1431 i2c13: i2c@a94000 { 1432 compatible = "qcom,geni-i2c"; 1433 reg = <0 0x00a94000 0 0x4000>; 1434 clock-names = "se"; 1435 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1436 pinctrl-names = "default"; 1437 pinctrl-0 = <&qup_i2c13_default>; 1438 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1439 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1440 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1441 dma-names = "tx", "rx"; 1442 #address-cells = <1>; 1443 #size-cells = <0>; 1444 status = "disabled"; 1445 }; 1446 1447 spi13: spi@a94000 { 1448 compatible = "qcom,geni-spi"; 1449 reg = <0 0x00a94000 0 0x4000>; 1450 clock-names = "se"; 1451 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1452 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1453 power-domains = <&rpmhpd RPMHPD_CX>; 1454 operating-points-v2 = <&qup_opp_table_100mhz>; 1455 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1456 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1457 dma-names = "tx", "rx"; 1458 #address-cells = <1>; 1459 #size-cells = <0>; 1460 status = "disabled"; 1461 }; 1462 }; 1463 1464 rng: rng@10d3000 { 1465 compatible = "qcom,prng-ee"; 1466 reg = <0 0x010d3000 0 0x1000>; 1467 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1468 clock-names = "core"; 1469 }; 1470 1471 config_noc: interconnect@1500000 { 1472 compatible = "qcom,sm8350-config-noc"; 1473 reg = <0 0x01500000 0 0xa580>; 1474 #interconnect-cells = <2>; 1475 qcom,bcm-voters = <&apps_bcm_voter>; 1476 }; 1477 1478 mc_virt: interconnect@1580000 { 1479 compatible = "qcom,sm8350-mc-virt"; 1480 reg = <0 0x01580000 0 0x1000>; 1481 #interconnect-cells = <2>; 1482 qcom,bcm-voters = <&apps_bcm_voter>; 1483 }; 1484 1485 system_noc: interconnect@1680000 { 1486 compatible = "qcom,sm8350-system-noc"; 1487 reg = <0 0x01680000 0 0x1c200>; 1488 #interconnect-cells = <2>; 1489 qcom,bcm-voters = <&apps_bcm_voter>; 1490 }; 1491 1492 aggre1_noc: interconnect@16e0000 { 1493 compatible = "qcom,sm8350-aggre1-noc"; 1494 reg = <0 0x016e0000 0 0x1f180>; 1495 #interconnect-cells = <2>; 1496 qcom,bcm-voters = <&apps_bcm_voter>; 1497 }; 1498 1499 aggre2_noc: interconnect@1700000 { 1500 compatible = "qcom,sm8350-aggre2-noc"; 1501 reg = <0 0x01700000 0 0x33000>; 1502 #interconnect-cells = <2>; 1503 qcom,bcm-voters = <&apps_bcm_voter>; 1504 }; 1505 1506 mmss_noc: interconnect@1740000 { 1507 compatible = "qcom,sm8350-mmss-noc"; 1508 reg = <0 0x01740000 0 0x1f080>; 1509 #interconnect-cells = <2>; 1510 qcom,bcm-voters = <&apps_bcm_voter>; 1511 }; 1512 1513 pcie0: pcie@1c00000 { 1514 compatible = "qcom,pcie-sm8350"; 1515 reg = <0 0x01c00000 0 0x3000>, 1516 <0 0x60000000 0 0xf1d>, 1517 <0 0x60000f20 0 0xa8>, 1518 <0 0x60001000 0 0x1000>, 1519 <0 0x60100000 0 0x100000>; 1520 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1521 device_type = "pci"; 1522 linux,pci-domain = <0>; 1523 bus-range = <0x00 0xff>; 1524 num-lanes = <1>; 1525 1526 #address-cells = <3>; 1527 #size-cells = <2>; 1528 1529 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1530 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1531 1532 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1540 interrupt-names = "msi0", 1541 "msi1", 1542 "msi2", 1543 "msi3", 1544 "msi4", 1545 "msi5", 1546 "msi6", 1547 "msi7"; 1548 #interrupt-cells = <1>; 1549 interrupt-map-mask = <0 0 0 0x7>; 1550 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1551 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1552 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1553 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1554 1555 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1556 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1557 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1558 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1559 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1560 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1561 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1562 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1563 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; 1564 clock-names = "aux", 1565 "cfg", 1566 "bus_master", 1567 "bus_slave", 1568 "slave_q2a", 1569 "tbu", 1570 "ddrss_sf_tbu", 1571 "aggre1", 1572 "aggre0"; 1573 1574 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1575 <0x100 &apps_smmu 0x1c01 0x1>; 1576 1577 resets = <&gcc GCC_PCIE_0_BCR>; 1578 reset-names = "pci"; 1579 1580 power-domains = <&gcc PCIE_0_GDSC>; 1581 1582 phys = <&pcie0_phy>; 1583 phy-names = "pciephy"; 1584 1585 status = "disabled"; 1586 1587 pcie@0 { 1588 device_type = "pci"; 1589 reg = <0x0 0x0 0x0 0x0 0x0>; 1590 bus-range = <0x01 0xff>; 1591 1592 #address-cells = <3>; 1593 #size-cells = <2>; 1594 ranges; 1595 }; 1596 }; 1597 1598 pcie0_phy: phy@1c06000 { 1599 compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy"; 1600 reg = <0 0x01c06000 0 0x2000>; 1601 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1602 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1603 <&gcc GCC_PCIE_0_CLKREF_EN>, 1604 <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, 1605 <&gcc GCC_PCIE_0_PIPE_CLK>; 1606 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1607 1608 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1609 reset-names = "phy"; 1610 1611 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>; 1612 assigned-clock-rates = <100000000>; 1613 1614 #clock-cells = <0>; 1615 clock-output-names = "pcie_0_pipe_clk"; 1616 1617 #phy-cells = <0>; 1618 1619 status = "disabled"; 1620 }; 1621 1622 pcie1: pcie@1c08000 { 1623 compatible = "qcom,pcie-sm8350"; 1624 reg = <0 0x01c08000 0 0x3000>, 1625 <0 0x40000000 0 0xf1d>, 1626 <0 0x40000f20 0 0xa8>, 1627 <0 0x40001000 0 0x1000>, 1628 <0 0x40100000 0 0x100000>; 1629 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1630 device_type = "pci"; 1631 linux,pci-domain = <1>; 1632 bus-range = <0x00 0xff>; 1633 num-lanes = <2>; 1634 1635 #address-cells = <3>; 1636 #size-cells = <2>; 1637 1638 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1639 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1640 1641 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1643 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1644 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1645 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1647 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 1648 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1649 interrupt-names = "msi0", 1650 "msi1", 1651 "msi2", 1652 "msi3", 1653 "msi4", 1654 "msi5", 1655 "msi6", 1656 "msi7"; 1657 #interrupt-cells = <1>; 1658 interrupt-map-mask = <0 0 0 0x7>; 1659 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1660 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1661 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1662 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1663 1664 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1665 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1666 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1667 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1668 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1669 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1670 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1671 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1672 clock-names = "aux", 1673 "cfg", 1674 "bus_master", 1675 "bus_slave", 1676 "slave_q2a", 1677 "tbu", 1678 "ddrss_sf_tbu", 1679 "aggre1"; 1680 1681 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1682 <0x100 &apps_smmu 0x1c81 0x1>; 1683 1684 resets = <&gcc GCC_PCIE_1_BCR>; 1685 reset-names = "pci"; 1686 1687 power-domains = <&gcc PCIE_1_GDSC>; 1688 1689 phys = <&pcie1_phy>; 1690 phy-names = "pciephy"; 1691 1692 status = "disabled"; 1693 1694 pcie@0 { 1695 device_type = "pci"; 1696 reg = <0x0 0x0 0x0 0x0 0x0>; 1697 bus-range = <0x01 0xff>; 1698 1699 #address-cells = <3>; 1700 #size-cells = <2>; 1701 ranges; 1702 }; 1703 }; 1704 1705 pcie1_phy: phy@1c0e000 { 1706 compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy"; 1707 reg = <0 0x01c0e000 0 0x2000>; 1708 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1709 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1710 <&gcc GCC_PCIE_1_CLKREF_EN>, 1711 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, 1712 <&gcc GCC_PCIE_1_PIPE_CLK>; 1713 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1714 1715 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1716 reset-names = "phy"; 1717 1718 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1719 assigned-clock-rates = <100000000>; 1720 1721 #clock-cells = <0>; 1722 clock-output-names = "pcie_1_pipe_clk"; 1723 1724 #phy-cells = <0>; 1725 1726 status = "disabled"; 1727 }; 1728 1729 ufs_mem_hc: ufshc@1d84000 { 1730 compatible = "qcom,sm8350-ufshc", "qcom,ufshc", 1731 "jedec,ufs-2.0"; 1732 reg = <0 0x01d84000 0 0x3000>; 1733 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1734 phys = <&ufs_mem_phy>; 1735 phy-names = "ufsphy"; 1736 lanes-per-direction = <2>; 1737 #reset-cells = <1>; 1738 resets = <&gcc GCC_UFS_PHY_BCR>; 1739 reset-names = "rst"; 1740 1741 power-domains = <&gcc UFS_PHY_GDSC>; 1742 1743 iommus = <&apps_smmu 0xe0 0x0>; 1744 dma-coherent; 1745 1746 clock-names = 1747 "core_clk", 1748 "bus_aggr_clk", 1749 "iface_clk", 1750 "core_clk_unipro", 1751 "ref_clk", 1752 "tx_lane0_sync_clk", 1753 "rx_lane0_sync_clk", 1754 "rx_lane1_sync_clk"; 1755 clocks = 1756 <&gcc GCC_UFS_PHY_AXI_CLK>, 1757 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1758 <&gcc GCC_UFS_PHY_AHB_CLK>, 1759 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1760 <&rpmhcc RPMH_CXO_CLK>, 1761 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1762 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1763 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1764 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 1765 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1766 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1767 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 1768 interconnect-names = "ufs-ddr", "cpu-ufs"; 1769 freq-table-hz = 1770 <75000000 300000000>, 1771 <0 0>, 1772 <0 0>, 1773 <75000000 300000000>, 1774 <0 0>, 1775 <0 0>, 1776 <0 0>, 1777 <0 0>; 1778 status = "disabled"; 1779 }; 1780 1781 ufs_mem_phy: phy@1d87000 { 1782 compatible = "qcom,sm8350-qmp-ufs-phy"; 1783 reg = <0 0x01d87000 0 0x1000>; 1784 1785 clocks = <&rpmhcc RPMH_CXO_CLK>, 1786 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1787 <&gcc GCC_UFS_1_CLKREF_EN>; 1788 clock-names = "ref", 1789 "ref_aux", 1790 "qref"; 1791 1792 power-domains = <&gcc UFS_PHY_GDSC>; 1793 1794 resets = <&ufs_mem_hc 0>; 1795 reset-names = "ufsphy"; 1796 1797 #clock-cells = <1>; 1798 #phy-cells = <0>; 1799 1800 status = "disabled"; 1801 }; 1802 1803 cryptobam: dma-controller@1dc4000 { 1804 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1805 reg = <0 0x01dc4000 0 0x24000>; 1806 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1807 #dma-cells = <1>; 1808 qcom,ee = <0>; 1809 qcom,controlled-remotely; 1810 iommus = <&apps_smmu 0x594 0x0011>, 1811 <&apps_smmu 0x596 0x0011>; 1812 /* FIXME: Probing BAM DMA causes some abort and system hang */ 1813 status = "fail"; 1814 }; 1815 1816 crypto: crypto@1dfa000 { 1817 compatible = "qcom,sm8350-qce", "qcom,sm8150-qce", "qcom,qce"; 1818 reg = <0 0x01dfa000 0 0x6000>; 1819 dmas = <&cryptobam 4>, <&cryptobam 5>; 1820 dma-names = "rx", "tx"; 1821 iommus = <&apps_smmu 0x594 0x0011>, 1822 <&apps_smmu 0x596 0x0011>; 1823 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 1824 interconnect-names = "memory"; 1825 /* FIXME: dependency BAM DMA is disabled */ 1826 status = "disabled"; 1827 }; 1828 1829 ipa: ipa@1e40000 { 1830 compatible = "qcom,sm8350-ipa"; 1831 1832 iommus = <&apps_smmu 0x5c0 0x0>, 1833 <&apps_smmu 0x5c2 0x0>; 1834 reg = <0 0x01e40000 0 0x8000>, 1835 <0 0x01e50000 0 0x4b20>, 1836 <0 0x01e04000 0 0x23000>; 1837 reg-names = "ipa-reg", 1838 "ipa-shared", 1839 "gsi"; 1840 1841 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, 1842 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1843 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1844 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1845 interrupt-names = "ipa", 1846 "gsi", 1847 "ipa-clock-query", 1848 "ipa-setup-ready"; 1849 1850 clocks = <&rpmhcc RPMH_IPA_CLK>; 1851 clock-names = "core"; 1852 1853 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1854 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1855 interconnect-names = "memory", 1856 "config"; 1857 1858 qcom,qmp = <&aoss_qmp>; 1859 1860 qcom,smem-states = <&ipa_smp2p_out 0>, 1861 <&ipa_smp2p_out 1>; 1862 qcom,smem-state-names = "ipa-clock-enabled-valid", 1863 "ipa-clock-enabled"; 1864 1865 status = "disabled"; 1866 }; 1867 1868 tcsr_mutex: hwlock@1f40000 { 1869 compatible = "qcom,tcsr-mutex"; 1870 reg = <0x0 0x01f40000 0x0 0x40000>; 1871 #hwlock-cells = <1>; 1872 }; 1873 1874 tcsr: syscon@1fc0000 { 1875 compatible = "qcom,sm8350-tcsr", "syscon"; 1876 reg = <0x0 0x1fc0000 0x0 0x30000>; 1877 }; 1878 1879 lpass_tlmm: pinctrl@33c0000 { 1880 compatible = "qcom,sm8350-lpass-lpi-pinctrl"; 1881 reg = <0 0x033c0000 0 0x20000>, 1882 <0 0x03550000 0 0x10000>; 1883 1884 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1885 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1886 clock-names = "core", "audio"; 1887 1888 gpio-controller; 1889 #gpio-cells = <2>; 1890 gpio-ranges = <&lpass_tlmm 0 0 15>; 1891 }; 1892 1893 gpu: gpu@3d00000 { 1894 compatible = "qcom,adreno-660.1", "qcom,adreno"; 1895 1896 reg = <0 0x03d00000 0 0x40000>, 1897 <0 0x03d9e000 0 0x1000>, 1898 <0 0x03d61000 0 0x800>; 1899 reg-names = "kgsl_3d0_reg_memory", 1900 "cx_mem", 1901 "cx_dbgc"; 1902 1903 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1904 1905 iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>; 1906 1907 operating-points-v2 = <&gpu_opp_table>; 1908 1909 qcom,gmu = <&gmu>; 1910 #cooling-cells = <2>; 1911 1912 status = "disabled"; 1913 1914 zap-shader { 1915 memory-region = <&pil_gpu_mem>; 1916 }; 1917 1918 /* note: downstream checks gpu binning for 670 Mhz */ 1919 gpu_opp_table: opp-table { 1920 compatible = "operating-points-v2"; 1921 1922 opp-840000000 { 1923 opp-hz = /bits/ 64 <840000000>; 1924 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1925 }; 1926 1927 opp-778000000 { 1928 opp-hz = /bits/ 64 <778000000>; 1929 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1930 }; 1931 1932 opp-738000000 { 1933 opp-hz = /bits/ 64 <738000000>; 1934 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1935 }; 1936 1937 opp-676000000 { 1938 opp-hz = /bits/ 64 <676000000>; 1939 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1940 }; 1941 1942 opp-608000000 { 1943 opp-hz = /bits/ 64 <608000000>; 1944 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1945 }; 1946 1947 opp-540000000 { 1948 opp-hz = /bits/ 64 <540000000>; 1949 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1950 }; 1951 1952 opp-491000000 { 1953 opp-hz = /bits/ 64 <491000000>; 1954 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 1955 }; 1956 1957 opp-443000000 { 1958 opp-hz = /bits/ 64 <443000000>; 1959 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1960 }; 1961 1962 opp-379000000 { 1963 opp-hz = /bits/ 64 <379000000>; 1964 opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>; 1965 }; 1966 1967 opp-315000000 { 1968 opp-hz = /bits/ 64 <315000000>; 1969 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1970 }; 1971 }; 1972 }; 1973 1974 gmu: gmu@3d6a000 { 1975 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu"; 1976 1977 reg = <0 0x03d6a000 0 0x34000>, 1978 <0 0x03de0000 0 0x10000>, 1979 <0 0x0b290000 0 0x10000>; 1980 reg-names = "gmu", "rscc", "gmu_pdc"; 1981 1982 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1983 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1984 interrupt-names = "hfi", "gmu"; 1985 1986 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 1987 <&gpucc GPU_CC_CXO_CLK>, 1988 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1989 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1990 <&gpucc GPU_CC_AHB_CLK>, 1991 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 1992 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 1993 clock-names = "gmu", 1994 "cxo", 1995 "axi", 1996 "memnoc", 1997 "ahb", 1998 "hub", 1999 "smmu_vote"; 2000 2001 power-domains = <&gpucc GPU_CX_GDSC>, 2002 <&gpucc GPU_GX_GDSC>; 2003 power-domain-names = "cx", 2004 "gx"; 2005 2006 iommus = <&adreno_smmu 5 0x400>; 2007 2008 operating-points-v2 = <&gmu_opp_table>; 2009 2010 gmu_opp_table: opp-table { 2011 compatible = "operating-points-v2"; 2012 2013 opp-200000000 { 2014 opp-hz = /bits/ 64 <200000000>; 2015 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2016 }; 2017 }; 2018 }; 2019 2020 gpucc: clock-controller@3d90000 { 2021 compatible = "qcom,sm8350-gpucc"; 2022 reg = <0 0x03d90000 0 0x9000>; 2023 clocks = <&rpmhcc RPMH_CXO_CLK>, 2024 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2025 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2026 clock-names = "bi_tcxo", 2027 "gcc_gpu_gpll0_clk_src", 2028 "gcc_gpu_gpll0_div_clk_src"; 2029 #clock-cells = <1>; 2030 #reset-cells = <1>; 2031 #power-domain-cells = <1>; 2032 }; 2033 2034 adreno_smmu: iommu@3da0000 { 2035 compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu", 2036 "qcom,smmu-500", "arm,mmu-500"; 2037 reg = <0 0x03da0000 0 0x20000>; 2038 #iommu-cells = <2>; 2039 #global-interrupts = <2>; 2040 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2041 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2042 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2043 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2044 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2045 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2046 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2047 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2048 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2049 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2050 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2051 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2052 2053 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2054 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2055 <&gpucc GPU_CC_AHB_CLK>, 2056 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2057 <&gpucc GPU_CC_CX_GMU_CLK>, 2058 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2059 <&gpucc GPU_CC_HUB_AON_CLK>; 2060 clock-names = "bus", 2061 "iface", 2062 "ahb", 2063 "hlos1_vote_gpu_smmu", 2064 "cx_gmu", 2065 "hub_cx_int", 2066 "hub_aon"; 2067 2068 power-domains = <&gpucc GPU_CX_GDSC>; 2069 dma-coherent; 2070 }; 2071 2072 lpass_ag_noc: interconnect@3c40000 { 2073 compatible = "qcom,sm8350-lpass-ag-noc"; 2074 reg = <0 0x03c40000 0 0xf080>; 2075 #interconnect-cells = <2>; 2076 qcom,bcm-voters = <&apps_bcm_voter>; 2077 }; 2078 2079 mpss: remoteproc@4080000 { 2080 compatible = "qcom,sm8350-mpss-pas"; 2081 reg = <0x0 0x04080000 0x0 0x4040>; 2082 2083 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2084 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2085 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2086 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2087 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2088 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2089 interrupt-names = "wdog", "fatal", "ready", "handover", 2090 "stop-ack", "shutdown-ack"; 2091 2092 clocks = <&rpmhcc RPMH_CXO_CLK>; 2093 clock-names = "xo"; 2094 2095 power-domains = <&rpmhpd RPMHPD_CX>, 2096 <&rpmhpd RPMHPD_MSS>; 2097 power-domain-names = "cx", "mss"; 2098 2099 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2100 2101 memory-region = <&pil_modem_mem>; 2102 2103 qcom,qmp = <&aoss_qmp>; 2104 2105 qcom,smem-states = <&smp2p_modem_out 0>; 2106 qcom,smem-state-names = "stop"; 2107 2108 status = "disabled"; 2109 2110 glink-edge { 2111 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2112 IPCC_MPROC_SIGNAL_GLINK_QMP 2113 IRQ_TYPE_EDGE_RISING>; 2114 mboxes = <&ipcc IPCC_CLIENT_MPSS 2115 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2116 label = "modem"; 2117 qcom,remote-pid = <1>; 2118 }; 2119 }; 2120 2121 slpi: remoteproc@5c00000 { 2122 compatible = "qcom,sm8350-slpi-pas"; 2123 reg = <0 0x05c00000 0 0x4000>; 2124 2125 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2126 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2127 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2128 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2129 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2130 interrupt-names = "wdog", "fatal", "ready", 2131 "handover", "stop-ack"; 2132 2133 clocks = <&rpmhcc RPMH_CXO_CLK>; 2134 clock-names = "xo"; 2135 2136 power-domains = <&rpmhpd RPMHPD_LCX>, 2137 <&rpmhpd RPMHPD_LMX>; 2138 power-domain-names = "lcx", "lmx"; 2139 2140 memory-region = <&pil_slpi_mem>; 2141 2142 qcom,qmp = <&aoss_qmp>; 2143 2144 qcom,smem-states = <&smp2p_slpi_out 0>; 2145 qcom,smem-state-names = "stop"; 2146 2147 status = "disabled"; 2148 2149 glink-edge { 2150 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2151 IPCC_MPROC_SIGNAL_GLINK_QMP 2152 IRQ_TYPE_EDGE_RISING>; 2153 mboxes = <&ipcc IPCC_CLIENT_SLPI 2154 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2155 2156 label = "slpi"; 2157 qcom,remote-pid = <3>; 2158 2159 fastrpc { 2160 compatible = "qcom,fastrpc"; 2161 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2162 label = "sdsp"; 2163 qcom,non-secure-domain; 2164 #address-cells = <1>; 2165 #size-cells = <0>; 2166 2167 compute-cb@1 { 2168 compatible = "qcom,fastrpc-compute-cb"; 2169 reg = <1>; 2170 iommus = <&apps_smmu 0x0541 0x0>; 2171 }; 2172 2173 compute-cb@2 { 2174 compatible = "qcom,fastrpc-compute-cb"; 2175 reg = <2>; 2176 iommus = <&apps_smmu 0x0542 0x0>; 2177 }; 2178 2179 compute-cb@3 { 2180 compatible = "qcom,fastrpc-compute-cb"; 2181 reg = <3>; 2182 iommus = <&apps_smmu 0x0543 0x0>; 2183 /* note: shared-cb = <4> in downstream */ 2184 }; 2185 }; 2186 }; 2187 }; 2188 2189 sdhc_2: mmc@8804000 { 2190 compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5"; 2191 reg = <0 0x08804000 0 0x1000>; 2192 2193 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2194 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2195 interrupt-names = "hc_irq", "pwr_irq"; 2196 2197 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2198 <&gcc GCC_SDCC2_APPS_CLK>, 2199 <&rpmhcc RPMH_CXO_CLK>; 2200 clock-names = "iface", "core", "xo"; 2201 resets = <&gcc GCC_SDCC2_BCR>; 2202 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2203 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2204 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2205 iommus = <&apps_smmu 0x4a0 0x0>; 2206 power-domains = <&rpmhpd RPMHPD_CX>; 2207 operating-points-v2 = <&sdhc2_opp_table>; 2208 bus-width = <4>; 2209 dma-coherent; 2210 2211 status = "disabled"; 2212 2213 sdhc2_opp_table: opp-table { 2214 compatible = "operating-points-v2"; 2215 2216 opp-100000000 { 2217 opp-hz = /bits/ 64 <100000000>; 2218 required-opps = <&rpmhpd_opp_low_svs>; 2219 }; 2220 2221 opp-202000000 { 2222 opp-hz = /bits/ 64 <202000000>; 2223 required-opps = <&rpmhpd_opp_svs_l1>; 2224 }; 2225 }; 2226 }; 2227 2228 usb_1_hsphy: phy@88e3000 { 2229 compatible = "qcom,sm8350-usb-hs-phy", 2230 "qcom,usb-snps-hs-7nm-phy"; 2231 reg = <0 0x088e3000 0 0x400>; 2232 status = "disabled"; 2233 #phy-cells = <0>; 2234 2235 clocks = <&rpmhcc RPMH_CXO_CLK>; 2236 clock-names = "ref"; 2237 2238 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2239 }; 2240 2241 usb_2_hsphy: phy@88e4000 { 2242 compatible = "qcom,sm8250-usb-hs-phy", 2243 "qcom,usb-snps-hs-7nm-phy"; 2244 reg = <0 0x088e4000 0 0x400>; 2245 status = "disabled"; 2246 #phy-cells = <0>; 2247 2248 clocks = <&rpmhcc RPMH_CXO_CLK>; 2249 clock-names = "ref"; 2250 2251 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2252 }; 2253 2254 usb_1_qmpphy: phy@88e8000 { 2255 compatible = "qcom,sm8350-qmp-usb3-dp-phy"; 2256 reg = <0 0x088e8000 0 0x3000>; 2257 2258 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2259 <&rpmhcc RPMH_CXO_CLK>, 2260 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2261 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2262 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2263 2264 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2265 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2266 reset-names = "phy", "common"; 2267 2268 #clock-cells = <1>; 2269 #phy-cells = <1>; 2270 2271 orientation-switch; 2272 2273 status = "disabled"; 2274 2275 ports { 2276 #address-cells = <1>; 2277 #size-cells = <0>; 2278 2279 port@0 { 2280 reg = <0>; 2281 2282 usb_1_qmpphy_out: endpoint { 2283 }; 2284 }; 2285 2286 port@1 { 2287 reg = <1>; 2288 2289 usb_1_qmpphy_usb_ss_in: endpoint { 2290 remote-endpoint = <&usb_1_dwc3_ss>; 2291 }; 2292 }; 2293 2294 port@2 { 2295 reg = <2>; 2296 2297 usb_1_qmpphy_dp_in: endpoint { 2298 remote-endpoint = <&mdss_dp_out>; 2299 }; 2300 }; 2301 }; 2302 }; 2303 2304 usb_2_qmpphy: phy@88eb000 { 2305 compatible = "qcom,sm8350-qmp-usb3-uni-phy"; 2306 reg = <0 0x088eb000 0 0x2000>; 2307 status = "disabled"; 2308 2309 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2310 <&gcc GCC_USB3_SEC_CLKREF_EN>, 2311 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2312 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2313 clock-names = "aux", 2314 "ref", 2315 "com_aux", 2316 "pipe"; 2317 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2318 #clock-cells = <0>; 2319 #phy-cells = <0>; 2320 2321 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2322 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 2323 reset-names = "phy", 2324 "phy_phy"; 2325 }; 2326 2327 dc_noc: interconnect@90c0000 { 2328 compatible = "qcom,sm8350-dc-noc"; 2329 reg = <0 0x090c0000 0 0x4200>; 2330 #interconnect-cells = <2>; 2331 qcom,bcm-voters = <&apps_bcm_voter>; 2332 }; 2333 2334 gem_noc: interconnect@9100000 { 2335 compatible = "qcom,sm8350-gem-noc"; 2336 reg = <0 0x09100000 0 0xb4000>; 2337 #interconnect-cells = <2>; 2338 qcom,bcm-voters = <&apps_bcm_voter>; 2339 }; 2340 2341 system-cache-controller@9200000 { 2342 compatible = "qcom,sm8350-llcc"; 2343 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 2344 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 2345 <0 0x09600000 0 0x58000>; 2346 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2347 "llcc3_base", "llcc_broadcast_base"; 2348 }; 2349 2350 compute_noc: interconnect@a0c0000 { 2351 compatible = "qcom,sm8350-compute-noc"; 2352 reg = <0 0x0a0c0000 0 0xa180>; 2353 #interconnect-cells = <2>; 2354 qcom,bcm-voters = <&apps_bcm_voter>; 2355 }; 2356 2357 usb_1: usb@a6f8800 { 2358 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2359 reg = <0 0x0a6f8800 0 0x400>; 2360 status = "disabled"; 2361 #address-cells = <2>; 2362 #size-cells = <2>; 2363 ranges; 2364 2365 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2366 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2367 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2368 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2369 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 2370 clock-names = "cfg_noc", 2371 "core", 2372 "iface", 2373 "sleep", 2374 "mock_utmi"; 2375 2376 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2377 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2378 assigned-clock-rates = <19200000>, <200000000>; 2379 2380 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2381 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2382 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2383 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2384 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2385 interrupt-names = "pwr_event", 2386 "hs_phy_irq", 2387 "dp_hs_phy_irq", 2388 "dm_hs_phy_irq", 2389 "ss_phy_irq"; 2390 2391 power-domains = <&gcc USB30_PRIM_GDSC>; 2392 2393 resets = <&gcc GCC_USB30_PRIM_BCR>; 2394 2395 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2396 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 2397 interconnect-names = "usb-ddr", "apps-usb"; 2398 2399 usb_1_dwc3: usb@a600000 { 2400 compatible = "snps,dwc3"; 2401 reg = <0 0x0a600000 0 0xcd00>; 2402 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2403 iommus = <&apps_smmu 0x0 0x0>; 2404 snps,dis_u2_susphy_quirk; 2405 snps,dis_enblslpm_quirk; 2406 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 2407 phy-names = "usb2-phy", "usb3-phy"; 2408 2409 ports { 2410 #address-cells = <1>; 2411 #size-cells = <0>; 2412 2413 port@0 { 2414 reg = <0>; 2415 2416 usb_1_dwc3_hs: endpoint { 2417 }; 2418 }; 2419 2420 port@1 { 2421 reg = <1>; 2422 2423 usb_1_dwc3_ss: endpoint { 2424 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 2425 }; 2426 }; 2427 }; 2428 }; 2429 }; 2430 2431 usb_2: usb@a8f8800 { 2432 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2433 reg = <0 0x0a8f8800 0 0x400>; 2434 status = "disabled"; 2435 #address-cells = <2>; 2436 #size-cells = <2>; 2437 ranges; 2438 2439 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2440 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2441 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2442 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2443 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2444 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2445 clock-names = "cfg_noc", 2446 "core", 2447 "iface", 2448 "sleep", 2449 "mock_utmi", 2450 "xo"; 2451 2452 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2453 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2454 assigned-clock-rates = <19200000>, <200000000>; 2455 2456 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 2457 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2458 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 2459 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 2460 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 2461 interrupt-names = "pwr_event", 2462 "hs_phy_irq", 2463 "dp_hs_phy_irq", 2464 "dm_hs_phy_irq", 2465 "ss_phy_irq"; 2466 2467 power-domains = <&gcc USB30_SEC_GDSC>; 2468 2469 resets = <&gcc GCC_USB30_SEC_BCR>; 2470 2471 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 2472 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 2473 interconnect-names = "usb-ddr", "apps-usb"; 2474 2475 usb_2_dwc3: usb@a800000 { 2476 compatible = "snps,dwc3"; 2477 reg = <0 0x0a800000 0 0xcd00>; 2478 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2479 iommus = <&apps_smmu 0x20 0x0>; 2480 snps,dis_u2_susphy_quirk; 2481 snps,dis_enblslpm_quirk; 2482 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>; 2483 phy-names = "usb2-phy", "usb3-phy"; 2484 }; 2485 }; 2486 2487 mdss: display-subsystem@ae00000 { 2488 compatible = "qcom,sm8350-mdss"; 2489 reg = <0 0x0ae00000 0 0x1000>; 2490 reg-names = "mdss"; 2491 2492 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 2493 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 2494 interconnect-names = "mdp0-mem", "mdp1-mem"; 2495 2496 power-domains = <&dispcc MDSS_GDSC>; 2497 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2498 2499 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2500 <&gcc GCC_DISP_HF_AXI_CLK>, 2501 <&gcc GCC_DISP_SF_AXI_CLK>, 2502 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2503 clock-names = "iface", "bus", "nrt_bus", "core"; 2504 2505 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2506 interrupt-controller; 2507 #interrupt-cells = <1>; 2508 2509 iommus = <&apps_smmu 0x820 0x402>; 2510 2511 status = "disabled"; 2512 2513 #address-cells = <2>; 2514 #size-cells = <2>; 2515 ranges; 2516 2517 mdss_mdp: display-controller@ae01000 { 2518 compatible = "qcom,sm8350-dpu"; 2519 reg = <0 0x0ae01000 0 0x8f000>, 2520 <0 0x0aeb0000 0 0x2008>; 2521 reg-names = "mdp", "vbif"; 2522 2523 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2524 <&gcc GCC_DISP_SF_AXI_CLK>, 2525 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2526 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2527 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2528 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2529 clock-names = "bus", 2530 "nrt_bus", 2531 "iface", 2532 "lut", 2533 "core", 2534 "vsync"; 2535 2536 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2537 assigned-clock-rates = <19200000>; 2538 2539 operating-points-v2 = <&dpu_opp_table>; 2540 power-domains = <&rpmhpd RPMHPD_MMCX>; 2541 2542 interrupt-parent = <&mdss>; 2543 interrupts = <0>; 2544 2545 dpu_opp_table: opp-table { 2546 compatible = "operating-points-v2"; 2547 2548 /* TODO: opp-200000000 should work with 2549 * &rpmhpd_opp_low_svs, but one some of 2550 * sm8350_hdk boards reboot using this 2551 * opp. 2552 */ 2553 opp-200000000 { 2554 opp-hz = /bits/ 64 <200000000>; 2555 required-opps = <&rpmhpd_opp_svs>; 2556 }; 2557 2558 opp-300000000 { 2559 opp-hz = /bits/ 64 <300000000>; 2560 required-opps = <&rpmhpd_opp_svs>; 2561 }; 2562 2563 opp-345000000 { 2564 opp-hz = /bits/ 64 <345000000>; 2565 required-opps = <&rpmhpd_opp_svs_l1>; 2566 }; 2567 2568 opp-460000000 { 2569 opp-hz = /bits/ 64 <460000000>; 2570 required-opps = <&rpmhpd_opp_nom>; 2571 }; 2572 }; 2573 2574 ports { 2575 #address-cells = <1>; 2576 #size-cells = <0>; 2577 2578 port@0 { 2579 reg = <0>; 2580 dpu_intf1_out: endpoint { 2581 remote-endpoint = <&mdss_dsi0_in>; 2582 }; 2583 }; 2584 2585 port@1 { 2586 reg = <1>; 2587 dpu_intf2_out: endpoint { 2588 remote-endpoint = <&mdss_dsi1_in>; 2589 }; 2590 }; 2591 2592 port@2 { 2593 reg = <2>; 2594 dpu_intf0_out: endpoint { 2595 remote-endpoint = <&mdss_dp_in>; 2596 }; 2597 }; 2598 }; 2599 }; 2600 2601 mdss_dp: displayport-controller@ae90000 { 2602 compatible = "qcom,sm8350-dp"; 2603 reg = <0 0xae90000 0 0x200>, 2604 <0 0xae90200 0 0x200>, 2605 <0 0xae90400 0 0x600>, 2606 <0 0xae91000 0 0x400>, 2607 <0 0xae91400 0 0x400>; 2608 interrupt-parent = <&mdss>; 2609 interrupts = <12>; 2610 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2611 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 2612 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 2613 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 2614 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 2615 clock-names = "core_iface", 2616 "core_aux", 2617 "ctrl_link", 2618 "ctrl_link_iface", 2619 "stream_pixel"; 2620 2621 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 2622 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 2623 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2624 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2625 2626 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 2627 phy-names = "dp"; 2628 2629 #sound-dai-cells = <0>; 2630 2631 operating-points-v2 = <&dp_opp_table>; 2632 power-domains = <&rpmhpd RPMHPD_MMCX>; 2633 2634 status = "disabled"; 2635 2636 ports { 2637 #address-cells = <1>; 2638 #size-cells = <0>; 2639 2640 port@0 { 2641 reg = <0>; 2642 mdss_dp_in: endpoint { 2643 remote-endpoint = <&dpu_intf0_out>; 2644 }; 2645 }; 2646 2647 port@1 { 2648 reg = <1>; 2649 2650 mdss_dp_out: endpoint { 2651 remote-endpoint = <&usb_1_qmpphy_dp_in>; 2652 }; 2653 }; 2654 }; 2655 2656 dp_opp_table: opp-table { 2657 compatible = "operating-points-v2"; 2658 2659 opp-160000000 { 2660 opp-hz = /bits/ 64 <160000000>; 2661 required-opps = <&rpmhpd_opp_low_svs>; 2662 }; 2663 2664 opp-270000000 { 2665 opp-hz = /bits/ 64 <270000000>; 2666 required-opps = <&rpmhpd_opp_svs>; 2667 }; 2668 2669 opp-540000000 { 2670 opp-hz = /bits/ 64 <540000000>; 2671 required-opps = <&rpmhpd_opp_svs_l1>; 2672 }; 2673 2674 opp-810000000 { 2675 opp-hz = /bits/ 64 <810000000>; 2676 required-opps = <&rpmhpd_opp_nom>; 2677 }; 2678 }; 2679 }; 2680 2681 mdss_dsi0: dsi@ae94000 { 2682 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2683 reg = <0 0x0ae94000 0 0x400>; 2684 reg-names = "dsi_ctrl"; 2685 2686 interrupt-parent = <&mdss>; 2687 interrupts = <4>; 2688 2689 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2690 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2691 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2692 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2693 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2694 <&gcc GCC_DISP_HF_AXI_CLK>; 2695 clock-names = "byte", 2696 "byte_intf", 2697 "pixel", 2698 "core", 2699 "iface", 2700 "bus"; 2701 2702 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2703 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2704 assigned-clock-parents = <&mdss_dsi0_phy 0>, 2705 <&mdss_dsi0_phy 1>; 2706 2707 operating-points-v2 = <&dsi0_opp_table>; 2708 power-domains = <&rpmhpd RPMHPD_MMCX>; 2709 2710 phys = <&mdss_dsi0_phy>; 2711 2712 #address-cells = <1>; 2713 #size-cells = <0>; 2714 2715 status = "disabled"; 2716 2717 dsi0_opp_table: opp-table { 2718 compatible = "operating-points-v2"; 2719 2720 /* TODO: opp-187500000 should work with 2721 * &rpmhpd_opp_low_svs, but one some of 2722 * sm8350_hdk boards reboot using this 2723 * opp. 2724 */ 2725 opp-187500000 { 2726 opp-hz = /bits/ 64 <187500000>; 2727 required-opps = <&rpmhpd_opp_svs>; 2728 }; 2729 2730 opp-300000000 { 2731 opp-hz = /bits/ 64 <300000000>; 2732 required-opps = <&rpmhpd_opp_svs>; 2733 }; 2734 2735 opp-358000000 { 2736 opp-hz = /bits/ 64 <358000000>; 2737 required-opps = <&rpmhpd_opp_svs_l1>; 2738 }; 2739 }; 2740 2741 ports { 2742 #address-cells = <1>; 2743 #size-cells = <0>; 2744 2745 port@0 { 2746 reg = <0>; 2747 mdss_dsi0_in: endpoint { 2748 remote-endpoint = <&dpu_intf1_out>; 2749 }; 2750 }; 2751 2752 port@1 { 2753 reg = <1>; 2754 mdss_dsi0_out: endpoint { 2755 }; 2756 }; 2757 }; 2758 }; 2759 2760 mdss_dsi0_phy: phy@ae94400 { 2761 compatible = "qcom,sm8350-dsi-phy-5nm"; 2762 reg = <0 0x0ae94400 0 0x200>, 2763 <0 0x0ae94600 0 0x280>, 2764 <0 0x0ae94900 0 0x27c>; 2765 reg-names = "dsi_phy", 2766 "dsi_phy_lane", 2767 "dsi_pll"; 2768 2769 #clock-cells = <1>; 2770 #phy-cells = <0>; 2771 2772 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2773 <&rpmhcc RPMH_CXO_CLK>; 2774 clock-names = "iface", "ref"; 2775 2776 status = "disabled"; 2777 }; 2778 2779 mdss_dsi1: dsi@ae96000 { 2780 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2781 reg = <0 0x0ae96000 0 0x400>; 2782 reg-names = "dsi_ctrl"; 2783 2784 interrupt-parent = <&mdss>; 2785 interrupts = <5>; 2786 2787 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2788 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2789 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2790 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2791 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2792 <&gcc GCC_DISP_HF_AXI_CLK>; 2793 clock-names = "byte", 2794 "byte_intf", 2795 "pixel", 2796 "core", 2797 "iface", 2798 "bus"; 2799 2800 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 2801 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2802 assigned-clock-parents = <&mdss_dsi1_phy 0>, 2803 <&mdss_dsi1_phy 1>; 2804 2805 operating-points-v2 = <&dsi1_opp_table>; 2806 power-domains = <&rpmhpd RPMHPD_MMCX>; 2807 2808 phys = <&mdss_dsi1_phy>; 2809 2810 #address-cells = <1>; 2811 #size-cells = <0>; 2812 2813 status = "disabled"; 2814 2815 dsi1_opp_table: opp-table { 2816 compatible = "operating-points-v2"; 2817 2818 /* TODO: opp-187500000 should work with 2819 * &rpmhpd_opp_low_svs, but one some of 2820 * sm8350_hdk boards reboot using this 2821 * opp. 2822 */ 2823 opp-187500000 { 2824 opp-hz = /bits/ 64 <187500000>; 2825 required-opps = <&rpmhpd_opp_svs>; 2826 }; 2827 2828 opp-300000000 { 2829 opp-hz = /bits/ 64 <300000000>; 2830 required-opps = <&rpmhpd_opp_svs>; 2831 }; 2832 2833 opp-358000000 { 2834 opp-hz = /bits/ 64 <358000000>; 2835 required-opps = <&rpmhpd_opp_svs_l1>; 2836 }; 2837 }; 2838 2839 ports { 2840 #address-cells = <1>; 2841 #size-cells = <0>; 2842 2843 port@0 { 2844 reg = <0>; 2845 mdss_dsi1_in: endpoint { 2846 remote-endpoint = <&dpu_intf2_out>; 2847 }; 2848 }; 2849 2850 port@1 { 2851 reg = <1>; 2852 mdss_dsi1_out: endpoint { 2853 }; 2854 }; 2855 }; 2856 }; 2857 2858 mdss_dsi1_phy: phy@ae96400 { 2859 compatible = "qcom,sm8350-dsi-phy-5nm"; 2860 reg = <0 0x0ae96400 0 0x200>, 2861 <0 0x0ae96600 0 0x280>, 2862 <0 0x0ae96900 0 0x27c>; 2863 reg-names = "dsi_phy", 2864 "dsi_phy_lane", 2865 "dsi_pll"; 2866 2867 #clock-cells = <1>; 2868 #phy-cells = <0>; 2869 2870 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2871 <&rpmhcc RPMH_CXO_CLK>; 2872 clock-names = "iface", "ref"; 2873 2874 status = "disabled"; 2875 }; 2876 }; 2877 2878 dispcc: clock-controller@af00000 { 2879 compatible = "qcom,sm8350-dispcc"; 2880 reg = <0 0x0af00000 0 0x10000>; 2881 clocks = <&rpmhcc RPMH_CXO_CLK>, 2882 <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, 2883 <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, 2884 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2885 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2886 clock-names = "bi_tcxo", 2887 "dsi0_phy_pll_out_byteclk", 2888 "dsi0_phy_pll_out_dsiclk", 2889 "dsi1_phy_pll_out_byteclk", 2890 "dsi1_phy_pll_out_dsiclk", 2891 "dp_phy_pll_link_clk", 2892 "dp_phy_pll_vco_div_clk"; 2893 #clock-cells = <1>; 2894 #reset-cells = <1>; 2895 #power-domain-cells = <1>; 2896 2897 power-domains = <&rpmhpd RPMHPD_MMCX>; 2898 }; 2899 2900 pdc: interrupt-controller@b220000 { 2901 compatible = "qcom,sm8350-pdc", "qcom,pdc"; 2902 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 2903 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, 2904 <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, 2905 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, 2906 <156 716 12>; 2907 #interrupt-cells = <2>; 2908 interrupt-parent = <&intc>; 2909 interrupt-controller; 2910 }; 2911 2912 tsens0: thermal-sensor@c263000 { 2913 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 2914 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2915 <0 0x0c222000 0 0x8>; /* SROT */ 2916 #qcom,sensors = <15>; 2917 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 2918 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 2919 interrupt-names = "uplow", "critical"; 2920 #thermal-sensor-cells = <1>; 2921 }; 2922 2923 tsens1: thermal-sensor@c265000 { 2924 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 2925 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2926 <0 0x0c223000 0 0x8>; /* SROT */ 2927 #qcom,sensors = <14>; 2928 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 2929 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 2930 interrupt-names = "uplow", "critical"; 2931 #thermal-sensor-cells = <1>; 2932 }; 2933 2934 aoss_qmp: power-management@c300000 { 2935 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; 2936 reg = <0 0x0c300000 0 0x400>; 2937 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2938 IRQ_TYPE_EDGE_RISING>; 2939 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2940 2941 #clock-cells = <0>; 2942 }; 2943 2944 sram@c3f0000 { 2945 compatible = "qcom,rpmh-stats"; 2946 reg = <0 0x0c3f0000 0 0x400>; 2947 }; 2948 2949 spmi_bus: spmi@c440000 { 2950 compatible = "qcom,spmi-pmic-arb"; 2951 reg = <0x0 0x0c440000 0x0 0x1100>, 2952 <0x0 0x0c600000 0x0 0x2000000>, 2953 <0x0 0x0e600000 0x0 0x100000>, 2954 <0x0 0x0e700000 0x0 0xa0000>, 2955 <0x0 0x0c40a000 0x0 0x26000>; 2956 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2957 interrupt-names = "periph_irq"; 2958 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2959 qcom,ee = <0>; 2960 qcom,channel = <0>; 2961 #address-cells = <2>; 2962 #size-cells = <0>; 2963 interrupt-controller; 2964 #interrupt-cells = <4>; 2965 }; 2966 2967 tlmm: pinctrl@f100000 { 2968 compatible = "qcom,sm8350-tlmm"; 2969 reg = <0 0x0f100000 0 0x300000>; 2970 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2971 gpio-controller; 2972 #gpio-cells = <2>; 2973 interrupt-controller; 2974 #interrupt-cells = <2>; 2975 gpio-ranges = <&tlmm 0 0 204>; 2976 wakeup-parent = <&pdc>; 2977 2978 sdc2_default_state: sdc2-default-state { 2979 clk-pins { 2980 pins = "sdc2_clk"; 2981 drive-strength = <16>; 2982 bias-disable; 2983 }; 2984 2985 cmd-pins { 2986 pins = "sdc2_cmd"; 2987 drive-strength = <16>; 2988 bias-pull-up; 2989 }; 2990 2991 data-pins { 2992 pins = "sdc2_data"; 2993 drive-strength = <16>; 2994 bias-pull-up; 2995 }; 2996 }; 2997 2998 sdc2_sleep_state: sdc2-sleep-state { 2999 clk-pins { 3000 pins = "sdc2_clk"; 3001 drive-strength = <2>; 3002 bias-disable; 3003 }; 3004 3005 cmd-pins { 3006 pins = "sdc2_cmd"; 3007 drive-strength = <2>; 3008 bias-pull-up; 3009 }; 3010 3011 data-pins { 3012 pins = "sdc2_data"; 3013 drive-strength = <2>; 3014 bias-pull-up; 3015 }; 3016 }; 3017 3018 qup_uart3_default_state: qup-uart3-default-state { 3019 rx-pins { 3020 pins = "gpio18"; 3021 function = "qup3"; 3022 }; 3023 tx-pins { 3024 pins = "gpio19"; 3025 function = "qup3"; 3026 }; 3027 }; 3028 3029 qup_uart6_default: qup-uart6-default-state { 3030 pins = "gpio30", "gpio31"; 3031 function = "qup6"; 3032 drive-strength = <2>; 3033 bias-disable; 3034 }; 3035 3036 qup_uart18_default: qup-uart18-default-state { 3037 pins = "gpio68", "gpio69"; 3038 function = "qup18"; 3039 drive-strength = <2>; 3040 bias-disable; 3041 }; 3042 3043 qup_i2c0_default: qup-i2c0-default-state { 3044 pins = "gpio4", "gpio5"; 3045 function = "qup0"; 3046 drive-strength = <2>; 3047 bias-pull-up; 3048 }; 3049 3050 qup_i2c1_default: qup-i2c1-default-state { 3051 pins = "gpio8", "gpio9"; 3052 function = "qup1"; 3053 drive-strength = <2>; 3054 bias-pull-up; 3055 }; 3056 3057 qup_i2c2_default: qup-i2c2-default-state { 3058 pins = "gpio12", "gpio13"; 3059 function = "qup2"; 3060 drive-strength = <2>; 3061 bias-pull-up; 3062 }; 3063 3064 qup_i2c4_default: qup-i2c4-default-state { 3065 pins = "gpio20", "gpio21"; 3066 function = "qup4"; 3067 drive-strength = <2>; 3068 bias-pull-up; 3069 }; 3070 3071 qup_i2c5_default: qup-i2c5-default-state { 3072 pins = "gpio24", "gpio25"; 3073 function = "qup5"; 3074 drive-strength = <2>; 3075 bias-pull-up; 3076 }; 3077 3078 qup_i2c6_default: qup-i2c6-default-state { 3079 pins = "gpio28", "gpio29"; 3080 function = "qup6"; 3081 drive-strength = <2>; 3082 bias-pull-up; 3083 }; 3084 3085 qup_i2c7_default: qup-i2c7-default-state { 3086 pins = "gpio32", "gpio33"; 3087 function = "qup7"; 3088 drive-strength = <2>; 3089 bias-disable; 3090 }; 3091 3092 qup_i2c8_default: qup-i2c8-default-state { 3093 pins = "gpio36", "gpio37"; 3094 function = "qup8"; 3095 drive-strength = <2>; 3096 bias-pull-up; 3097 }; 3098 3099 qup_i2c9_default: qup-i2c9-default-state { 3100 pins = "gpio40", "gpio41"; 3101 function = "qup9"; 3102 drive-strength = <2>; 3103 bias-pull-up; 3104 }; 3105 3106 qup_i2c10_default: qup-i2c10-default-state { 3107 pins = "gpio44", "gpio45"; 3108 function = "qup10"; 3109 drive-strength = <2>; 3110 bias-pull-up; 3111 }; 3112 3113 qup_i2c11_default: qup-i2c11-default-state { 3114 pins = "gpio48", "gpio49"; 3115 function = "qup11"; 3116 drive-strength = <2>; 3117 bias-pull-up; 3118 }; 3119 3120 qup_i2c12_default: qup-i2c12-default-state { 3121 pins = "gpio52", "gpio53"; 3122 function = "qup12"; 3123 drive-strength = <2>; 3124 bias-pull-up; 3125 }; 3126 3127 qup_i2c13_default: qup-i2c13-default-state { 3128 pins = "gpio0", "gpio1"; 3129 function = "qup13"; 3130 drive-strength = <2>; 3131 bias-pull-up; 3132 }; 3133 3134 qup_i2c14_default: qup-i2c14-default-state { 3135 pins = "gpio56", "gpio57"; 3136 function = "qup14"; 3137 drive-strength = <2>; 3138 bias-disable; 3139 }; 3140 3141 qup_i2c15_default: qup-i2c15-default-state { 3142 pins = "gpio60", "gpio61"; 3143 function = "qup15"; 3144 drive-strength = <2>; 3145 bias-disable; 3146 }; 3147 3148 qup_i2c16_default: qup-i2c16-default-state { 3149 pins = "gpio64", "gpio65"; 3150 function = "qup16"; 3151 drive-strength = <2>; 3152 bias-disable; 3153 }; 3154 3155 qup_i2c17_default: qup-i2c17-default-state { 3156 pins = "gpio72", "gpio73"; 3157 function = "qup17"; 3158 drive-strength = <2>; 3159 bias-disable; 3160 }; 3161 3162 qup_i2c19_default: qup-i2c19-default-state { 3163 pins = "gpio76", "gpio77"; 3164 function = "qup19"; 3165 drive-strength = <2>; 3166 bias-disable; 3167 }; 3168 }; 3169 3170 apps_smmu: iommu@15000000 { 3171 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; 3172 reg = <0 0x15000000 0 0x100000>; 3173 #iommu-cells = <2>; 3174 #global-interrupts = <2>; 3175 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 3176 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3177 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3178 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3179 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3180 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3181 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3182 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3183 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3184 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3185 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3186 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3187 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3188 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3189 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3190 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3191 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3192 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3193 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3194 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3195 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3196 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3197 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3198 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3199 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3200 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3201 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3202 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3203 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3204 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3205 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3206 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3207 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3208 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3209 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3210 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3211 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3212 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3213 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3214 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3215 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3216 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3217 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3218 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3219 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3220 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3221 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3222 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3223 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3224 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3225 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3226 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3227 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3228 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3229 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3230 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3231 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3232 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3233 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3234 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3235 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3236 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3237 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3238 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3239 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3240 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3241 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3242 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3243 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3244 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3245 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3246 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3247 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3248 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3249 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3250 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3251 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3252 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3253 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3254 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3255 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3256 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3257 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3258 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3259 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3260 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3261 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3262 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3263 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3264 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3265 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3266 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3267 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3268 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3269 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3270 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3271 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 3272 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 3273 }; 3274 3275 adsp: remoteproc@17300000 { 3276 compatible = "qcom,sm8350-adsp-pas"; 3277 reg = <0 0x17300000 0 0x100>; 3278 3279 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 3280 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3281 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3282 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3283 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 3284 interrupt-names = "wdog", "fatal", "ready", 3285 "handover", "stop-ack"; 3286 3287 clocks = <&rpmhcc RPMH_CXO_CLK>; 3288 clock-names = "xo"; 3289 3290 power-domains = <&rpmhpd RPMHPD_LCX>, 3291 <&rpmhpd RPMHPD_LMX>; 3292 power-domain-names = "lcx", "lmx"; 3293 3294 memory-region = <&pil_adsp_mem>; 3295 3296 qcom,qmp = <&aoss_qmp>; 3297 3298 qcom,smem-states = <&smp2p_adsp_out 0>; 3299 qcom,smem-state-names = "stop"; 3300 3301 status = "disabled"; 3302 3303 glink-edge { 3304 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3305 IPCC_MPROC_SIGNAL_GLINK_QMP 3306 IRQ_TYPE_EDGE_RISING>; 3307 mboxes = <&ipcc IPCC_CLIENT_LPASS 3308 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3309 3310 label = "lpass"; 3311 qcom,remote-pid = <2>; 3312 3313 apr { 3314 compatible = "qcom,apr-v2"; 3315 qcom,glink-channels = "apr_audio_svc"; 3316 qcom,domain = <APR_DOMAIN_ADSP>; 3317 #address-cells = <1>; 3318 #size-cells = <0>; 3319 3320 service@3 { 3321 reg = <APR_SVC_ADSP_CORE>; 3322 compatible = "qcom,q6core"; 3323 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3324 }; 3325 3326 q6afe: service@4 { 3327 compatible = "qcom,q6afe"; 3328 reg = <APR_SVC_AFE>; 3329 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3330 3331 q6afedai: dais { 3332 compatible = "qcom,q6afe-dais"; 3333 #address-cells = <1>; 3334 #size-cells = <0>; 3335 #sound-dai-cells = <1>; 3336 }; 3337 3338 q6afecc: clock-controller { 3339 compatible = "qcom,q6afe-clocks"; 3340 #clock-cells = <2>; 3341 }; 3342 }; 3343 3344 q6asm: service@7 { 3345 compatible = "qcom,q6asm"; 3346 reg = <APR_SVC_ASM>; 3347 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3348 3349 q6asmdai: dais { 3350 compatible = "qcom,q6asm-dais"; 3351 #address-cells = <1>; 3352 #size-cells = <0>; 3353 #sound-dai-cells = <1>; 3354 iommus = <&apps_smmu 0x1801 0x0>; 3355 3356 dai@0 { 3357 reg = <0>; 3358 }; 3359 3360 dai@1 { 3361 reg = <1>; 3362 }; 3363 3364 dai@2 { 3365 reg = <2>; 3366 }; 3367 }; 3368 }; 3369 3370 q6adm: service@8 { 3371 compatible = "qcom,q6adm"; 3372 reg = <APR_SVC_ADM>; 3373 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3374 3375 q6routing: routing { 3376 compatible = "qcom,q6adm-routing"; 3377 #sound-dai-cells = <0>; 3378 }; 3379 }; 3380 }; 3381 3382 fastrpc { 3383 compatible = "qcom,fastrpc"; 3384 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3385 label = "adsp"; 3386 qcom,non-secure-domain; 3387 #address-cells = <1>; 3388 #size-cells = <0>; 3389 3390 compute-cb@3 { 3391 compatible = "qcom,fastrpc-compute-cb"; 3392 reg = <3>; 3393 iommus = <&apps_smmu 0x1803 0x0>; 3394 }; 3395 3396 compute-cb@4 { 3397 compatible = "qcom,fastrpc-compute-cb"; 3398 reg = <4>; 3399 iommus = <&apps_smmu 0x1804 0x0>; 3400 }; 3401 3402 compute-cb@5 { 3403 compatible = "qcom,fastrpc-compute-cb"; 3404 reg = <5>; 3405 iommus = <&apps_smmu 0x1805 0x0>; 3406 }; 3407 }; 3408 }; 3409 }; 3410 3411 intc: interrupt-controller@17a00000 { 3412 compatible = "arm,gic-v3"; 3413 #interrupt-cells = <3>; 3414 interrupt-controller; 3415 #redistributor-regions = <1>; 3416 redistributor-stride = <0 0x20000>; 3417 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3418 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3419 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3420 }; 3421 3422 timer@17c20000 { 3423 compatible = "arm,armv7-timer-mem"; 3424 #address-cells = <1>; 3425 #size-cells = <1>; 3426 ranges = <0 0 0 0x20000000>; 3427 reg = <0x0 0x17c20000 0x0 0x1000>; 3428 clock-frequency = <19200000>; 3429 3430 frame@17c21000 { 3431 frame-number = <0>; 3432 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3433 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3434 reg = <0x17c21000 0x1000>, 3435 <0x17c22000 0x1000>; 3436 }; 3437 3438 frame@17c23000 { 3439 frame-number = <1>; 3440 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3441 reg = <0x17c23000 0x1000>; 3442 status = "disabled"; 3443 }; 3444 3445 frame@17c25000 { 3446 frame-number = <2>; 3447 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3448 reg = <0x17c25000 0x1000>; 3449 status = "disabled"; 3450 }; 3451 3452 frame@17c27000 { 3453 frame-number = <3>; 3454 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3455 reg = <0x17c27000 0x1000>; 3456 status = "disabled"; 3457 }; 3458 3459 frame@17c29000 { 3460 frame-number = <4>; 3461 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3462 reg = <0x17c29000 0x1000>; 3463 status = "disabled"; 3464 }; 3465 3466 frame@17c2b000 { 3467 frame-number = <5>; 3468 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3469 reg = <0x17c2b000 0x1000>; 3470 status = "disabled"; 3471 }; 3472 3473 frame@17c2d000 { 3474 frame-number = <6>; 3475 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3476 reg = <0x17c2d000 0x1000>; 3477 status = "disabled"; 3478 }; 3479 }; 3480 3481 apps_rsc: rsc@18200000 { 3482 label = "apps_rsc"; 3483 compatible = "qcom,rpmh-rsc"; 3484 reg = <0x0 0x18200000 0x0 0x10000>, 3485 <0x0 0x18210000 0x0 0x10000>, 3486 <0x0 0x18220000 0x0 0x10000>; 3487 reg-names = "drv-0", "drv-1", "drv-2"; 3488 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3489 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3490 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3491 qcom,tcs-offset = <0xd00>; 3492 qcom,drv-id = <2>; 3493 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 3494 <WAKE_TCS 3>, <CONTROL_TCS 0>; 3495 power-domains = <&CLUSTER_PD>; 3496 3497 rpmhcc: clock-controller { 3498 compatible = "qcom,sm8350-rpmh-clk"; 3499 #clock-cells = <1>; 3500 clock-names = "xo"; 3501 clocks = <&xo_board>; 3502 }; 3503 3504 rpmhpd: power-controller { 3505 compatible = "qcom,sm8350-rpmhpd"; 3506 #power-domain-cells = <1>; 3507 operating-points-v2 = <&rpmhpd_opp_table>; 3508 3509 rpmhpd_opp_table: opp-table { 3510 compatible = "operating-points-v2"; 3511 3512 rpmhpd_opp_ret: opp1 { 3513 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3514 }; 3515 3516 rpmhpd_opp_min_svs: opp2 { 3517 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3518 }; 3519 3520 rpmhpd_opp_low_svs: opp3 { 3521 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3522 }; 3523 3524 rpmhpd_opp_svs: opp4 { 3525 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3526 }; 3527 3528 rpmhpd_opp_svs_l1: opp5 { 3529 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3530 }; 3531 3532 rpmhpd_opp_nom: opp6 { 3533 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3534 }; 3535 3536 rpmhpd_opp_nom_l1: opp7 { 3537 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3538 }; 3539 3540 rpmhpd_opp_nom_l2: opp8 { 3541 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3542 }; 3543 3544 rpmhpd_opp_turbo: opp9 { 3545 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3546 }; 3547 3548 rpmhpd_opp_turbo_l1: opp10 { 3549 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3550 }; 3551 }; 3552 }; 3553 3554 apps_bcm_voter: bcm-voter { 3555 compatible = "qcom,bcm-voter"; 3556 }; 3557 }; 3558 3559 cpufreq_hw: cpufreq@18591000 { 3560 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss"; 3561 reg = <0 0x18591000 0 0x1000>, 3562 <0 0x18592000 0 0x1000>, 3563 <0 0x18593000 0 0x1000>; 3564 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3565 3566 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 3567 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3568 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 3569 interrupt-names = "dcvsh-irq-0", 3570 "dcvsh-irq-1", 3571 "dcvsh-irq-2"; 3572 3573 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3574 clock-names = "xo", "alternate"; 3575 3576 #freq-domain-cells = <1>; 3577 #clock-cells = <1>; 3578 }; 3579 3580 cdsp: remoteproc@98900000 { 3581 compatible = "qcom,sm8350-cdsp-pas"; 3582 reg = <0 0x98900000 0 0x1400000>; 3583 3584 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3585 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3586 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3587 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3588 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3589 interrupt-names = "wdog", "fatal", "ready", 3590 "handover", "stop-ack"; 3591 3592 clocks = <&rpmhcc RPMH_CXO_CLK>; 3593 clock-names = "xo"; 3594 3595 power-domains = <&rpmhpd RPMHPD_CX>, 3596 <&rpmhpd RPMHPD_MXC>; 3597 power-domain-names = "cx", "mxc"; 3598 3599 interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 3600 3601 memory-region = <&pil_cdsp_mem>; 3602 3603 qcom,qmp = <&aoss_qmp>; 3604 3605 qcom,smem-states = <&smp2p_cdsp_out 0>; 3606 qcom,smem-state-names = "stop"; 3607 3608 status = "disabled"; 3609 3610 glink-edge { 3611 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3612 IPCC_MPROC_SIGNAL_GLINK_QMP 3613 IRQ_TYPE_EDGE_RISING>; 3614 mboxes = <&ipcc IPCC_CLIENT_CDSP 3615 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3616 3617 label = "cdsp"; 3618 qcom,remote-pid = <5>; 3619 3620 fastrpc { 3621 compatible = "qcom,fastrpc"; 3622 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3623 label = "cdsp"; 3624 qcom,non-secure-domain; 3625 #address-cells = <1>; 3626 #size-cells = <0>; 3627 3628 compute-cb@1 { 3629 compatible = "qcom,fastrpc-compute-cb"; 3630 reg = <1>; 3631 iommus = <&apps_smmu 0x2161 0x0400>, 3632 <&apps_smmu 0x1181 0x0420>; 3633 }; 3634 3635 compute-cb@2 { 3636 compatible = "qcom,fastrpc-compute-cb"; 3637 reg = <2>; 3638 iommus = <&apps_smmu 0x2162 0x0400>, 3639 <&apps_smmu 0x1182 0x0420>; 3640 }; 3641 3642 compute-cb@3 { 3643 compatible = "qcom,fastrpc-compute-cb"; 3644 reg = <3>; 3645 iommus = <&apps_smmu 0x2163 0x0400>, 3646 <&apps_smmu 0x1183 0x0420>; 3647 }; 3648 3649 compute-cb@4 { 3650 compatible = "qcom,fastrpc-compute-cb"; 3651 reg = <4>; 3652 iommus = <&apps_smmu 0x2164 0x0400>, 3653 <&apps_smmu 0x1184 0x0420>; 3654 }; 3655 3656 compute-cb@5 { 3657 compatible = "qcom,fastrpc-compute-cb"; 3658 reg = <5>; 3659 iommus = <&apps_smmu 0x2165 0x0400>, 3660 <&apps_smmu 0x1185 0x0420>; 3661 }; 3662 3663 compute-cb@6 { 3664 compatible = "qcom,fastrpc-compute-cb"; 3665 reg = <6>; 3666 iommus = <&apps_smmu 0x2166 0x0400>, 3667 <&apps_smmu 0x1186 0x0420>; 3668 }; 3669 3670 compute-cb@7 { 3671 compatible = "qcom,fastrpc-compute-cb"; 3672 reg = <7>; 3673 iommus = <&apps_smmu 0x2167 0x0400>, 3674 <&apps_smmu 0x1187 0x0420>; 3675 }; 3676 3677 compute-cb@8 { 3678 compatible = "qcom,fastrpc-compute-cb"; 3679 reg = <8>; 3680 iommus = <&apps_smmu 0x2168 0x0400>, 3681 <&apps_smmu 0x1188 0x0420>; 3682 }; 3683 3684 /* note: secure cb9 in downstream */ 3685 }; 3686 }; 3687 }; 3688 }; 3689 3690 thermal_zones: thermal-zones { 3691 cpu0-thermal { 3692 polling-delay-passive = <250>; 3693 3694 thermal-sensors = <&tsens0 1>; 3695 3696 trips { 3697 cpu0_alert0: trip-point0 { 3698 temperature = <90000>; 3699 hysteresis = <2000>; 3700 type = "passive"; 3701 }; 3702 3703 cpu0_alert1: trip-point1 { 3704 temperature = <95000>; 3705 hysteresis = <2000>; 3706 type = "passive"; 3707 }; 3708 3709 cpu0_crit: cpu-crit { 3710 temperature = <110000>; 3711 hysteresis = <1000>; 3712 type = "critical"; 3713 }; 3714 }; 3715 3716 cooling-maps { 3717 map0 { 3718 trip = <&cpu0_alert0>; 3719 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3720 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3721 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3722 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3723 }; 3724 map1 { 3725 trip = <&cpu0_alert1>; 3726 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3727 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3728 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3729 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3730 }; 3731 }; 3732 }; 3733 3734 cpu1-thermal { 3735 polling-delay-passive = <250>; 3736 3737 thermal-sensors = <&tsens0 2>; 3738 3739 trips { 3740 cpu1_alert0: trip-point0 { 3741 temperature = <90000>; 3742 hysteresis = <2000>; 3743 type = "passive"; 3744 }; 3745 3746 cpu1_alert1: trip-point1 { 3747 temperature = <95000>; 3748 hysteresis = <2000>; 3749 type = "passive"; 3750 }; 3751 3752 cpu1_crit: cpu-crit { 3753 temperature = <110000>; 3754 hysteresis = <1000>; 3755 type = "critical"; 3756 }; 3757 }; 3758 3759 cooling-maps { 3760 map0 { 3761 trip = <&cpu1_alert0>; 3762 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3763 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3764 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3765 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3766 }; 3767 map1 { 3768 trip = <&cpu1_alert1>; 3769 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3770 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3771 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3772 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3773 }; 3774 }; 3775 }; 3776 3777 cpu2-thermal { 3778 polling-delay-passive = <250>; 3779 3780 thermal-sensors = <&tsens0 3>; 3781 3782 trips { 3783 cpu2_alert0: trip-point0 { 3784 temperature = <90000>; 3785 hysteresis = <2000>; 3786 type = "passive"; 3787 }; 3788 3789 cpu2_alert1: trip-point1 { 3790 temperature = <95000>; 3791 hysteresis = <2000>; 3792 type = "passive"; 3793 }; 3794 3795 cpu2_crit: cpu-crit { 3796 temperature = <110000>; 3797 hysteresis = <1000>; 3798 type = "critical"; 3799 }; 3800 }; 3801 3802 cooling-maps { 3803 map0 { 3804 trip = <&cpu2_alert0>; 3805 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3806 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3807 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3808 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3809 }; 3810 map1 { 3811 trip = <&cpu2_alert1>; 3812 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3813 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3814 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3815 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3816 }; 3817 }; 3818 }; 3819 3820 cpu3-thermal { 3821 polling-delay-passive = <250>; 3822 3823 thermal-sensors = <&tsens0 4>; 3824 3825 trips { 3826 cpu3_alert0: trip-point0 { 3827 temperature = <90000>; 3828 hysteresis = <2000>; 3829 type = "passive"; 3830 }; 3831 3832 cpu3_alert1: trip-point1 { 3833 temperature = <95000>; 3834 hysteresis = <2000>; 3835 type = "passive"; 3836 }; 3837 3838 cpu3_crit: cpu-crit { 3839 temperature = <110000>; 3840 hysteresis = <1000>; 3841 type = "critical"; 3842 }; 3843 }; 3844 3845 cooling-maps { 3846 map0 { 3847 trip = <&cpu3_alert0>; 3848 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3849 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3850 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3851 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3852 }; 3853 map1 { 3854 trip = <&cpu3_alert1>; 3855 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3856 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3857 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3858 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3859 }; 3860 }; 3861 }; 3862 3863 cpu4-top-thermal { 3864 polling-delay-passive = <250>; 3865 3866 thermal-sensors = <&tsens0 7>; 3867 3868 trips { 3869 cpu4_top_alert0: trip-point0 { 3870 temperature = <90000>; 3871 hysteresis = <2000>; 3872 type = "passive"; 3873 }; 3874 3875 cpu4_top_alert1: trip-point1 { 3876 temperature = <95000>; 3877 hysteresis = <2000>; 3878 type = "passive"; 3879 }; 3880 3881 cpu4_top_crit: cpu-crit { 3882 temperature = <110000>; 3883 hysteresis = <1000>; 3884 type = "critical"; 3885 }; 3886 }; 3887 3888 cooling-maps { 3889 map0 { 3890 trip = <&cpu4_top_alert0>; 3891 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3892 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3893 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3894 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3895 }; 3896 map1 { 3897 trip = <&cpu4_top_alert1>; 3898 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3899 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3900 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3901 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3902 }; 3903 }; 3904 }; 3905 3906 cpu5-top-thermal { 3907 polling-delay-passive = <250>; 3908 3909 thermal-sensors = <&tsens0 8>; 3910 3911 trips { 3912 cpu5_top_alert0: trip-point0 { 3913 temperature = <90000>; 3914 hysteresis = <2000>; 3915 type = "passive"; 3916 }; 3917 3918 cpu5_top_alert1: trip-point1 { 3919 temperature = <95000>; 3920 hysteresis = <2000>; 3921 type = "passive"; 3922 }; 3923 3924 cpu5_top_crit: cpu-crit { 3925 temperature = <110000>; 3926 hysteresis = <1000>; 3927 type = "critical"; 3928 }; 3929 }; 3930 3931 cooling-maps { 3932 map0 { 3933 trip = <&cpu5_top_alert0>; 3934 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3935 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3936 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3937 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3938 }; 3939 map1 { 3940 trip = <&cpu5_top_alert1>; 3941 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3942 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3943 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3944 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3945 }; 3946 }; 3947 }; 3948 3949 cpu6-top-thermal { 3950 polling-delay-passive = <250>; 3951 3952 thermal-sensors = <&tsens0 9>; 3953 3954 trips { 3955 cpu6_top_alert0: trip-point0 { 3956 temperature = <90000>; 3957 hysteresis = <2000>; 3958 type = "passive"; 3959 }; 3960 3961 cpu6_top_alert1: trip-point1 { 3962 temperature = <95000>; 3963 hysteresis = <2000>; 3964 type = "passive"; 3965 }; 3966 3967 cpu6_top_crit: cpu-crit { 3968 temperature = <110000>; 3969 hysteresis = <1000>; 3970 type = "critical"; 3971 }; 3972 }; 3973 3974 cooling-maps { 3975 map0 { 3976 trip = <&cpu6_top_alert0>; 3977 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3978 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3979 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3980 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3981 }; 3982 map1 { 3983 trip = <&cpu6_top_alert1>; 3984 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3985 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3986 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3987 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3988 }; 3989 }; 3990 }; 3991 3992 cpu7-top-thermal { 3993 polling-delay-passive = <250>; 3994 3995 thermal-sensors = <&tsens0 10>; 3996 3997 trips { 3998 cpu7_top_alert0: trip-point0 { 3999 temperature = <90000>; 4000 hysteresis = <2000>; 4001 type = "passive"; 4002 }; 4003 4004 cpu7_top_alert1: trip-point1 { 4005 temperature = <95000>; 4006 hysteresis = <2000>; 4007 type = "passive"; 4008 }; 4009 4010 cpu7_top_crit: cpu-crit { 4011 temperature = <110000>; 4012 hysteresis = <1000>; 4013 type = "critical"; 4014 }; 4015 }; 4016 4017 cooling-maps { 4018 map0 { 4019 trip = <&cpu7_top_alert0>; 4020 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4021 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4022 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4023 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4024 }; 4025 map1 { 4026 trip = <&cpu7_top_alert1>; 4027 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4028 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4029 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4030 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4031 }; 4032 }; 4033 }; 4034 4035 cpu4-bottom-thermal { 4036 polling-delay-passive = <250>; 4037 4038 thermal-sensors = <&tsens0 11>; 4039 4040 trips { 4041 cpu4_bottom_alert0: trip-point0 { 4042 temperature = <90000>; 4043 hysteresis = <2000>; 4044 type = "passive"; 4045 }; 4046 4047 cpu4_bottom_alert1: trip-point1 { 4048 temperature = <95000>; 4049 hysteresis = <2000>; 4050 type = "passive"; 4051 }; 4052 4053 cpu4_bottom_crit: cpu-crit { 4054 temperature = <110000>; 4055 hysteresis = <1000>; 4056 type = "critical"; 4057 }; 4058 }; 4059 4060 cooling-maps { 4061 map0 { 4062 trip = <&cpu4_bottom_alert0>; 4063 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4064 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4065 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4066 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4067 }; 4068 map1 { 4069 trip = <&cpu4_bottom_alert1>; 4070 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4071 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4072 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4073 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4074 }; 4075 }; 4076 }; 4077 4078 cpu5-bottom-thermal { 4079 polling-delay-passive = <250>; 4080 4081 thermal-sensors = <&tsens0 12>; 4082 4083 trips { 4084 cpu5_bottom_alert0: trip-point0 { 4085 temperature = <90000>; 4086 hysteresis = <2000>; 4087 type = "passive"; 4088 }; 4089 4090 cpu5_bottom_alert1: trip-point1 { 4091 temperature = <95000>; 4092 hysteresis = <2000>; 4093 type = "passive"; 4094 }; 4095 4096 cpu5_bottom_crit: cpu-crit { 4097 temperature = <110000>; 4098 hysteresis = <1000>; 4099 type = "critical"; 4100 }; 4101 }; 4102 4103 cooling-maps { 4104 map0 { 4105 trip = <&cpu5_bottom_alert0>; 4106 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4107 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4108 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4109 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4110 }; 4111 map1 { 4112 trip = <&cpu5_bottom_alert1>; 4113 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4114 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4115 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4116 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4117 }; 4118 }; 4119 }; 4120 4121 cpu6-bottom-thermal { 4122 polling-delay-passive = <250>; 4123 4124 thermal-sensors = <&tsens0 13>; 4125 4126 trips { 4127 cpu6_bottom_alert0: trip-point0 { 4128 temperature = <90000>; 4129 hysteresis = <2000>; 4130 type = "passive"; 4131 }; 4132 4133 cpu6_bottom_alert1: trip-point1 { 4134 temperature = <95000>; 4135 hysteresis = <2000>; 4136 type = "passive"; 4137 }; 4138 4139 cpu6_bottom_crit: cpu-crit { 4140 temperature = <110000>; 4141 hysteresis = <1000>; 4142 type = "critical"; 4143 }; 4144 }; 4145 4146 cooling-maps { 4147 map0 { 4148 trip = <&cpu6_bottom_alert0>; 4149 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4150 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4151 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4152 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4153 }; 4154 map1 { 4155 trip = <&cpu6_bottom_alert1>; 4156 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4157 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4158 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4159 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4160 }; 4161 }; 4162 }; 4163 4164 cpu7-bottom-thermal { 4165 polling-delay-passive = <250>; 4166 4167 thermal-sensors = <&tsens0 14>; 4168 4169 trips { 4170 cpu7_bottom_alert0: trip-point0 { 4171 temperature = <90000>; 4172 hysteresis = <2000>; 4173 type = "passive"; 4174 }; 4175 4176 cpu7_bottom_alert1: trip-point1 { 4177 temperature = <95000>; 4178 hysteresis = <2000>; 4179 type = "passive"; 4180 }; 4181 4182 cpu7_bottom_crit: cpu-crit { 4183 temperature = <110000>; 4184 hysteresis = <1000>; 4185 type = "critical"; 4186 }; 4187 }; 4188 4189 cooling-maps { 4190 map0 { 4191 trip = <&cpu7_bottom_alert0>; 4192 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4193 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4194 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4195 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4196 }; 4197 map1 { 4198 trip = <&cpu7_bottom_alert1>; 4199 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4200 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4201 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4202 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4203 }; 4204 }; 4205 }; 4206 4207 aoss0-thermal { 4208 polling-delay-passive = <250>; 4209 4210 thermal-sensors = <&tsens0 0>; 4211 4212 trips { 4213 aoss0_alert0: trip-point0 { 4214 temperature = <90000>; 4215 hysteresis = <2000>; 4216 type = "hot"; 4217 }; 4218 }; 4219 }; 4220 4221 cluster0-thermal { 4222 polling-delay-passive = <250>; 4223 4224 thermal-sensors = <&tsens0 5>; 4225 4226 trips { 4227 cluster0_alert0: trip-point0 { 4228 temperature = <90000>; 4229 hysteresis = <2000>; 4230 type = "hot"; 4231 }; 4232 cluster0_crit: cluster0-crit { 4233 temperature = <110000>; 4234 hysteresis = <2000>; 4235 type = "critical"; 4236 }; 4237 }; 4238 }; 4239 4240 cluster1-thermal { 4241 polling-delay-passive = <250>; 4242 4243 thermal-sensors = <&tsens0 6>; 4244 4245 trips { 4246 cluster1_alert0: trip-point0 { 4247 temperature = <90000>; 4248 hysteresis = <2000>; 4249 type = "hot"; 4250 }; 4251 cluster1_crit: cluster1-crit { 4252 temperature = <110000>; 4253 hysteresis = <2000>; 4254 type = "critical"; 4255 }; 4256 }; 4257 }; 4258 4259 aoss1-thermal { 4260 polling-delay-passive = <250>; 4261 4262 thermal-sensors = <&tsens1 0>; 4263 4264 trips { 4265 aoss1_alert0: trip-point0 { 4266 temperature = <90000>; 4267 hysteresis = <2000>; 4268 type = "hot"; 4269 }; 4270 }; 4271 }; 4272 4273 gpu-top-thermal { 4274 polling-delay-passive = <250>; 4275 4276 thermal-sensors = <&tsens1 1>; 4277 4278 cooling-maps { 4279 map0 { 4280 trip = <&gpu_top_alert0>; 4281 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4282 }; 4283 }; 4284 4285 trips { 4286 gpu_top_alert0: trip-point0 { 4287 temperature = <85000>; 4288 hysteresis = <1000>; 4289 type = "passive"; 4290 }; 4291 4292 trip-point1 { 4293 temperature = <90000>; 4294 hysteresis = <1000>; 4295 type = "hot"; 4296 }; 4297 4298 trip-point2 { 4299 temperature = <110000>; 4300 hysteresis = <1000>; 4301 type = "critical"; 4302 }; 4303 }; 4304 }; 4305 4306 gpu-bottom-thermal { 4307 polling-delay-passive = <250>; 4308 4309 thermal-sensors = <&tsens1 2>; 4310 4311 cooling-maps { 4312 map0 { 4313 trip = <&gpu_bottom_alert0>; 4314 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4315 }; 4316 }; 4317 4318 trips { 4319 gpu_bottom_alert0: trip-point0 { 4320 temperature = <85000>; 4321 hysteresis = <1000>; 4322 type = "passive"; 4323 }; 4324 4325 trip-point1 { 4326 temperature = <90000>; 4327 hysteresis = <1000>; 4328 type = "hot"; 4329 }; 4330 4331 trip-point2 { 4332 temperature = <110000>; 4333 hysteresis = <1000>; 4334 type = "critical"; 4335 }; 4336 }; 4337 }; 4338 4339 nspss1-thermal { 4340 polling-delay-passive = <250>; 4341 4342 thermal-sensors = <&tsens1 3>; 4343 4344 trips { 4345 nspss1_alert0: trip-point0 { 4346 temperature = <90000>; 4347 hysteresis = <1000>; 4348 type = "hot"; 4349 }; 4350 }; 4351 }; 4352 4353 nspss2-thermal { 4354 polling-delay-passive = <250>; 4355 4356 thermal-sensors = <&tsens1 4>; 4357 4358 trips { 4359 nspss2_alert0: trip-point0 { 4360 temperature = <90000>; 4361 hysteresis = <1000>; 4362 type = "hot"; 4363 }; 4364 }; 4365 }; 4366 4367 nspss3-thermal { 4368 polling-delay-passive = <250>; 4369 4370 thermal-sensors = <&tsens1 5>; 4371 4372 trips { 4373 nspss3_alert0: trip-point0 { 4374 temperature = <90000>; 4375 hysteresis = <1000>; 4376 type = "hot"; 4377 }; 4378 }; 4379 }; 4380 4381 video-thermal { 4382 polling-delay-passive = <250>; 4383 4384 thermal-sensors = <&tsens1 6>; 4385 4386 trips { 4387 video_alert0: trip-point0 { 4388 temperature = <90000>; 4389 hysteresis = <2000>; 4390 type = "hot"; 4391 }; 4392 }; 4393 }; 4394 4395 mem-thermal { 4396 polling-delay-passive = <250>; 4397 4398 thermal-sensors = <&tsens1 7>; 4399 4400 trips { 4401 mem_alert0: trip-point0 { 4402 temperature = <90000>; 4403 hysteresis = <2000>; 4404 type = "hot"; 4405 }; 4406 }; 4407 }; 4408 4409 modem1-top-thermal { 4410 polling-delay-passive = <250>; 4411 4412 thermal-sensors = <&tsens1 8>; 4413 4414 trips { 4415 modem1_alert0: trip-point0 { 4416 temperature = <90000>; 4417 hysteresis = <2000>; 4418 type = "hot"; 4419 }; 4420 }; 4421 }; 4422 4423 modem2-top-thermal { 4424 polling-delay-passive = <250>; 4425 4426 thermal-sensors = <&tsens1 9>; 4427 4428 trips { 4429 modem2_alert0: trip-point0 { 4430 temperature = <90000>; 4431 hysteresis = <2000>; 4432 type = "hot"; 4433 }; 4434 }; 4435 }; 4436 4437 modem3-top-thermal { 4438 polling-delay-passive = <250>; 4439 4440 thermal-sensors = <&tsens1 10>; 4441 4442 trips { 4443 modem3_alert0: trip-point0 { 4444 temperature = <90000>; 4445 hysteresis = <2000>; 4446 type = "hot"; 4447 }; 4448 }; 4449 }; 4450 4451 modem4-top-thermal { 4452 polling-delay-passive = <250>; 4453 4454 thermal-sensors = <&tsens1 11>; 4455 4456 trips { 4457 modem4_alert0: trip-point0 { 4458 temperature = <90000>; 4459 hysteresis = <2000>; 4460 type = "hot"; 4461 }; 4462 }; 4463 }; 4464 4465 camera-top-thermal { 4466 polling-delay-passive = <250>; 4467 4468 thermal-sensors = <&tsens1 12>; 4469 4470 trips { 4471 camera1_alert0: trip-point0 { 4472 temperature = <90000>; 4473 hysteresis = <2000>; 4474 type = "hot"; 4475 }; 4476 }; 4477 }; 4478 4479 cam-bottom-thermal { 4480 polling-delay-passive = <250>; 4481 4482 thermal-sensors = <&tsens1 13>; 4483 4484 trips { 4485 camera2_alert0: trip-point0 { 4486 temperature = <90000>; 4487 hysteresis = <2000>; 4488 type = "hot"; 4489 }; 4490 }; 4491 }; 4492 }; 4493 4494 timer { 4495 compatible = "arm,armv8-timer"; 4496 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4497 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4498 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4499 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4500 }; 4501}; 4502