1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Linaro Limited 4 */ 5 6#include <dt-bindings/interconnect/qcom,sm8350.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/qcom,dispcc-sm8350.h> 9#include <dt-bindings/clock/qcom,gcc-sm8350.h> 10#include <dt-bindings/clock/qcom,gpucc-sm8350.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/firmware/qcom,scm.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interconnect/qcom,icc.h> 16#include <dt-bindings/interconnect/qcom,sm8350.h> 17#include <dt-bindings/mailbox/qcom-ipcc.h> 18#include <dt-bindings/phy/phy-qcom-qmp.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/power/qcom,rpmhpd.h> 21#include <dt-bindings/soc/qcom,apr.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23#include <dt-bindings/sound/qcom,q6afe.h> 24#include <dt-bindings/thermal/thermal.h> 25#include <dt-bindings/interconnect/qcom,sm8350.h> 26 27/ { 28 interrupt-parent = <&intc>; 29 30 #address-cells = <2>; 31 #size-cells = <2>; 32 33 chosen { }; 34 35 clocks { 36 xo_board: xo-board { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <38400000>; 40 clock-output-names = "xo_board"; 41 }; 42 43 sleep_clk: sleep-clk { 44 compatible = "fixed-clock"; 45 clock-frequency = <32000>; 46 #clock-cells = <0>; 47 }; 48 }; 49 50 cpus { 51 #address-cells = <2>; 52 #size-cells = <0>; 53 54 CPU0: cpu@0 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a55"; 57 reg = <0x0 0x0>; 58 clocks = <&cpufreq_hw 0>; 59 enable-method = "psci"; 60 next-level-cache = <&L2_0>; 61 qcom,freq-domain = <&cpufreq_hw 0>; 62 power-domains = <&CPU_PD0>; 63 power-domain-names = "psci"; 64 #cooling-cells = <2>; 65 L2_0: l2-cache { 66 compatible = "cache"; 67 cache-level = <2>; 68 cache-unified; 69 next-level-cache = <&L3_0>; 70 L3_0: l3-cache { 71 compatible = "cache"; 72 cache-level = <3>; 73 cache-unified; 74 }; 75 }; 76 }; 77 78 CPU1: cpu@100 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a55"; 81 reg = <0x0 0x100>; 82 clocks = <&cpufreq_hw 0>; 83 enable-method = "psci"; 84 next-level-cache = <&L2_100>; 85 qcom,freq-domain = <&cpufreq_hw 0>; 86 power-domains = <&CPU_PD1>; 87 power-domain-names = "psci"; 88 #cooling-cells = <2>; 89 L2_100: l2-cache { 90 compatible = "cache"; 91 cache-level = <2>; 92 cache-unified; 93 next-level-cache = <&L3_0>; 94 }; 95 }; 96 97 CPU2: cpu@200 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a55"; 100 reg = <0x0 0x200>; 101 clocks = <&cpufreq_hw 0>; 102 enable-method = "psci"; 103 next-level-cache = <&L2_200>; 104 qcom,freq-domain = <&cpufreq_hw 0>; 105 power-domains = <&CPU_PD2>; 106 power-domain-names = "psci"; 107 #cooling-cells = <2>; 108 L2_200: l2-cache { 109 compatible = "cache"; 110 cache-level = <2>; 111 cache-unified; 112 next-level-cache = <&L3_0>; 113 }; 114 }; 115 116 CPU3: cpu@300 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a55"; 119 reg = <0x0 0x300>; 120 clocks = <&cpufreq_hw 0>; 121 enable-method = "psci"; 122 next-level-cache = <&L2_300>; 123 qcom,freq-domain = <&cpufreq_hw 0>; 124 power-domains = <&CPU_PD3>; 125 power-domain-names = "psci"; 126 #cooling-cells = <2>; 127 L2_300: l2-cache { 128 compatible = "cache"; 129 cache-level = <2>; 130 cache-unified; 131 next-level-cache = <&L3_0>; 132 }; 133 }; 134 135 CPU4: cpu@400 { 136 device_type = "cpu"; 137 compatible = "arm,cortex-a78"; 138 reg = <0x0 0x400>; 139 clocks = <&cpufreq_hw 1>; 140 enable-method = "psci"; 141 next-level-cache = <&L2_400>; 142 qcom,freq-domain = <&cpufreq_hw 1>; 143 power-domains = <&CPU_PD4>; 144 power-domain-names = "psci"; 145 #cooling-cells = <2>; 146 L2_400: l2-cache { 147 compatible = "cache"; 148 cache-level = <2>; 149 cache-unified; 150 next-level-cache = <&L3_0>; 151 }; 152 }; 153 154 CPU5: cpu@500 { 155 device_type = "cpu"; 156 compatible = "arm,cortex-a78"; 157 reg = <0x0 0x500>; 158 clocks = <&cpufreq_hw 1>; 159 enable-method = "psci"; 160 next-level-cache = <&L2_500>; 161 qcom,freq-domain = <&cpufreq_hw 1>; 162 power-domains = <&CPU_PD5>; 163 power-domain-names = "psci"; 164 #cooling-cells = <2>; 165 L2_500: l2-cache { 166 compatible = "cache"; 167 cache-level = <2>; 168 cache-unified; 169 next-level-cache = <&L3_0>; 170 }; 171 }; 172 173 CPU6: cpu@600 { 174 device_type = "cpu"; 175 compatible = "arm,cortex-a78"; 176 reg = <0x0 0x600>; 177 clocks = <&cpufreq_hw 1>; 178 enable-method = "psci"; 179 next-level-cache = <&L2_600>; 180 qcom,freq-domain = <&cpufreq_hw 1>; 181 power-domains = <&CPU_PD6>; 182 power-domain-names = "psci"; 183 #cooling-cells = <2>; 184 L2_600: l2-cache { 185 compatible = "cache"; 186 cache-level = <2>; 187 cache-unified; 188 next-level-cache = <&L3_0>; 189 }; 190 }; 191 192 CPU7: cpu@700 { 193 device_type = "cpu"; 194 compatible = "arm,cortex-x1"; 195 reg = <0x0 0x700>; 196 clocks = <&cpufreq_hw 2>; 197 enable-method = "psci"; 198 next-level-cache = <&L2_700>; 199 qcom,freq-domain = <&cpufreq_hw 2>; 200 power-domains = <&CPU_PD7>; 201 power-domain-names = "psci"; 202 #cooling-cells = <2>; 203 L2_700: l2-cache { 204 compatible = "cache"; 205 cache-level = <2>; 206 cache-unified; 207 next-level-cache = <&L3_0>; 208 }; 209 }; 210 211 cpu-map { 212 cluster0 { 213 core0 { 214 cpu = <&CPU0>; 215 }; 216 217 core1 { 218 cpu = <&CPU1>; 219 }; 220 221 core2 { 222 cpu = <&CPU2>; 223 }; 224 225 core3 { 226 cpu = <&CPU3>; 227 }; 228 229 core4 { 230 cpu = <&CPU4>; 231 }; 232 233 core5 { 234 cpu = <&CPU5>; 235 }; 236 237 core6 { 238 cpu = <&CPU6>; 239 }; 240 241 core7 { 242 cpu = <&CPU7>; 243 }; 244 }; 245 }; 246 247 idle-states { 248 entry-method = "psci"; 249 250 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 251 compatible = "arm,idle-state"; 252 idle-state-name = "silver-rail-power-collapse"; 253 arm,psci-suspend-param = <0x40000004>; 254 entry-latency-us = <360>; 255 exit-latency-us = <531>; 256 min-residency-us = <3934>; 257 local-timer-stop; 258 }; 259 260 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 261 compatible = "arm,idle-state"; 262 idle-state-name = "gold-rail-power-collapse"; 263 arm,psci-suspend-param = <0x40000004>; 264 entry-latency-us = <702>; 265 exit-latency-us = <1061>; 266 min-residency-us = <4488>; 267 local-timer-stop; 268 }; 269 }; 270 271 domain-idle-states { 272 CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { 273 compatible = "domain-idle-state"; 274 arm,psci-suspend-param = <0x41000044>; 275 entry-latency-us = <2752>; 276 exit-latency-us = <3048>; 277 min-residency-us = <6118>; 278 }; 279 280 CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 { 281 compatible = "domain-idle-state"; 282 arm,psci-suspend-param = <0x4100c344>; 283 entry-latency-us = <3263>; 284 exit-latency-us = <6562>; 285 min-residency-us = <9987>; 286 }; 287 }; 288 }; 289 290 firmware { 291 scm: scm { 292 compatible = "qcom,scm-sm8350", "qcom,scm"; 293 qcom,dload-mode = <&tcsr 0x13000>; 294 #reset-cells = <1>; 295 }; 296 }; 297 298 memory@80000000 { 299 device_type = "memory"; 300 /* We expect the bootloader to fill in the size */ 301 reg = <0x0 0x80000000 0x0 0x0>; 302 }; 303 304 pmu { 305 compatible = "arm,armv8-pmuv3"; 306 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 307 }; 308 309 psci { 310 compatible = "arm,psci-1.0"; 311 method = "smc"; 312 313 CPU_PD0: power-domain-cpu0 { 314 #power-domain-cells = <0>; 315 power-domains = <&CLUSTER_PD>; 316 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 317 }; 318 319 CPU_PD1: power-domain-cpu1 { 320 #power-domain-cells = <0>; 321 power-domains = <&CLUSTER_PD>; 322 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 323 }; 324 325 CPU_PD2: power-domain-cpu2 { 326 #power-domain-cells = <0>; 327 power-domains = <&CLUSTER_PD>; 328 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 329 }; 330 331 CPU_PD3: power-domain-cpu3 { 332 #power-domain-cells = <0>; 333 power-domains = <&CLUSTER_PD>; 334 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 335 }; 336 337 CPU_PD4: power-domain-cpu4 { 338 #power-domain-cells = <0>; 339 power-domains = <&CLUSTER_PD>; 340 domain-idle-states = <&BIG_CPU_SLEEP_0>; 341 }; 342 343 CPU_PD5: power-domain-cpu5 { 344 #power-domain-cells = <0>; 345 power-domains = <&CLUSTER_PD>; 346 domain-idle-states = <&BIG_CPU_SLEEP_0>; 347 }; 348 349 CPU_PD6: power-domain-cpu6 { 350 #power-domain-cells = <0>; 351 power-domains = <&CLUSTER_PD>; 352 domain-idle-states = <&BIG_CPU_SLEEP_0>; 353 }; 354 355 CPU_PD7: power-domain-cpu7 { 356 #power-domain-cells = <0>; 357 power-domains = <&CLUSTER_PD>; 358 domain-idle-states = <&BIG_CPU_SLEEP_0>; 359 }; 360 361 CLUSTER_PD: power-domain-cpu-cluster0 { 362 #power-domain-cells = <0>; 363 domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLEEP>; 364 }; 365 }; 366 367 qup_opp_table_100mhz: opp-table-qup100mhz { 368 compatible = "operating-points-v2"; 369 370 opp-50000000 { 371 opp-hz = /bits/ 64 <50000000>; 372 required-opps = <&rpmhpd_opp_min_svs>; 373 }; 374 375 opp-75000000 { 376 opp-hz = /bits/ 64 <75000000>; 377 required-opps = <&rpmhpd_opp_low_svs>; 378 }; 379 380 opp-100000000 { 381 opp-hz = /bits/ 64 <100000000>; 382 required-opps = <&rpmhpd_opp_svs>; 383 }; 384 }; 385 386 qup_opp_table_120mhz: opp-table-qup120mhz { 387 compatible = "operating-points-v2"; 388 389 opp-50000000 { 390 opp-hz = /bits/ 64 <50000000>; 391 required-opps = <&rpmhpd_opp_min_svs>; 392 }; 393 394 opp-75000000 { 395 opp-hz = /bits/ 64 <75000000>; 396 required-opps = <&rpmhpd_opp_low_svs>; 397 }; 398 399 opp-120000000 { 400 opp-hz = /bits/ 64 <120000000>; 401 required-opps = <&rpmhpd_opp_svs>; 402 }; 403 }; 404 405 reserved_memory: reserved-memory { 406 #address-cells = <2>; 407 #size-cells = <2>; 408 ranges; 409 410 hyp_mem: memory@80000000 { 411 reg = <0x0 0x80000000 0x0 0x600000>; 412 no-map; 413 }; 414 415 xbl_aop_mem: memory@80700000 { 416 no-map; 417 reg = <0x0 0x80700000 0x0 0x160000>; 418 }; 419 420 cmd_db: memory@80860000 { 421 compatible = "qcom,cmd-db"; 422 reg = <0x0 0x80860000 0x0 0x20000>; 423 no-map; 424 }; 425 426 reserved_xbl_uefi_log: memory@80880000 { 427 reg = <0x0 0x80880000 0x0 0x14000>; 428 no-map; 429 }; 430 431 smem@80900000 { 432 compatible = "qcom,smem"; 433 reg = <0x0 0x80900000 0x0 0x200000>; 434 hwlocks = <&tcsr_mutex 3>; 435 no-map; 436 }; 437 438 cpucp_fw_mem: memory@80b00000 { 439 reg = <0x0 0x80b00000 0x0 0x100000>; 440 no-map; 441 }; 442 443 cdsp_secure_heap: memory@80c00000 { 444 reg = <0x0 0x80c00000 0x0 0x4600000>; 445 no-map; 446 }; 447 448 pil_camera_mem: mmeory@85200000 { 449 reg = <0x0 0x85200000 0x0 0x500000>; 450 no-map; 451 }; 452 453 pil_video_mem: memory@85700000 { 454 reg = <0x0 0x85700000 0x0 0x500000>; 455 no-map; 456 }; 457 458 pil_cvp_mem: memory@85c00000 { 459 reg = <0x0 0x85c00000 0x0 0x500000>; 460 no-map; 461 }; 462 463 pil_adsp_mem: memory@86100000 { 464 reg = <0x0 0x86100000 0x0 0x2100000>; 465 no-map; 466 }; 467 468 pil_slpi_mem: memory@88200000 { 469 reg = <0x0 0x88200000 0x0 0x1500000>; 470 no-map; 471 }; 472 473 pil_cdsp_mem: memory@89700000 { 474 reg = <0x0 0x89700000 0x0 0x1e00000>; 475 no-map; 476 }; 477 478 pil_ipa_fw_mem: memory@8b500000 { 479 reg = <0x0 0x8b500000 0x0 0x10000>; 480 no-map; 481 }; 482 483 pil_ipa_gsi_mem: memory@8b510000 { 484 reg = <0x0 0x8b510000 0x0 0xa000>; 485 no-map; 486 }; 487 488 pil_gpu_mem: memory@8b51a000 { 489 reg = <0x0 0x8b51a000 0x0 0x2000>; 490 no-map; 491 }; 492 493 pil_spss_mem: memory@8b600000 { 494 reg = <0x0 0x8b600000 0x0 0x100000>; 495 no-map; 496 }; 497 498 pil_modem_mem: memory@8b800000 { 499 reg = <0x0 0x8b800000 0x0 0x10000000>; 500 no-map; 501 }; 502 503 rmtfs_mem: memory@9b800000 { 504 compatible = "qcom,rmtfs-mem"; 505 reg = <0x0 0x9b800000 0x0 0x280000>; 506 no-map; 507 508 qcom,client-id = <1>; 509 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 510 }; 511 512 hyp_reserved_mem: memory@d0000000 { 513 reg = <0x0 0xd0000000 0x0 0x800000>; 514 no-map; 515 }; 516 517 pil_trustedvm_mem: memory@d0800000 { 518 reg = <0x0 0xd0800000 0x0 0x76f7000>; 519 no-map; 520 }; 521 522 qrtr_shbuf: memory@d7ef7000 { 523 reg = <0x0 0xd7ef7000 0x0 0x9000>; 524 no-map; 525 }; 526 527 chan0_shbuf: memory@d7f00000 { 528 reg = <0x0 0xd7f00000 0x0 0x80000>; 529 no-map; 530 }; 531 532 chan1_shbuf: memory@d7f80000 { 533 reg = <0x0 0xd7f80000 0x0 0x80000>; 534 no-map; 535 }; 536 537 removed_mem: memory@d8800000 { 538 reg = <0x0 0xd8800000 0x0 0x6800000>; 539 no-map; 540 }; 541 }; 542 543 smp2p-adsp { 544 compatible = "qcom,smp2p"; 545 qcom,smem = <443>, <429>; 546 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 547 IPCC_MPROC_SIGNAL_SMP2P 548 IRQ_TYPE_EDGE_RISING>; 549 mboxes = <&ipcc IPCC_CLIENT_LPASS 550 IPCC_MPROC_SIGNAL_SMP2P>; 551 552 qcom,local-pid = <0>; 553 qcom,remote-pid = <2>; 554 555 smp2p_adsp_out: master-kernel { 556 qcom,entry-name = "master-kernel"; 557 #qcom,smem-state-cells = <1>; 558 }; 559 560 smp2p_adsp_in: slave-kernel { 561 qcom,entry-name = "slave-kernel"; 562 interrupt-controller; 563 #interrupt-cells = <2>; 564 }; 565 }; 566 567 smp2p-cdsp { 568 compatible = "qcom,smp2p"; 569 qcom,smem = <94>, <432>; 570 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 571 IPCC_MPROC_SIGNAL_SMP2P 572 IRQ_TYPE_EDGE_RISING>; 573 mboxes = <&ipcc IPCC_CLIENT_CDSP 574 IPCC_MPROC_SIGNAL_SMP2P>; 575 576 qcom,local-pid = <0>; 577 qcom,remote-pid = <5>; 578 579 smp2p_cdsp_out: master-kernel { 580 qcom,entry-name = "master-kernel"; 581 #qcom,smem-state-cells = <1>; 582 }; 583 584 smp2p_cdsp_in: slave-kernel { 585 qcom,entry-name = "slave-kernel"; 586 interrupt-controller; 587 #interrupt-cells = <2>; 588 }; 589 }; 590 591 smp2p-modem { 592 compatible = "qcom,smp2p"; 593 qcom,smem = <435>, <428>; 594 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 595 IPCC_MPROC_SIGNAL_SMP2P 596 IRQ_TYPE_EDGE_RISING>; 597 mboxes = <&ipcc IPCC_CLIENT_MPSS 598 IPCC_MPROC_SIGNAL_SMP2P>; 599 600 qcom,local-pid = <0>; 601 qcom,remote-pid = <1>; 602 603 smp2p_modem_out: master-kernel { 604 qcom,entry-name = "master-kernel"; 605 #qcom,smem-state-cells = <1>; 606 }; 607 608 smp2p_modem_in: slave-kernel { 609 qcom,entry-name = "slave-kernel"; 610 interrupt-controller; 611 #interrupt-cells = <2>; 612 }; 613 614 ipa_smp2p_out: ipa-ap-to-modem { 615 qcom,entry-name = "ipa"; 616 #qcom,smem-state-cells = <1>; 617 }; 618 619 ipa_smp2p_in: ipa-modem-to-ap { 620 qcom,entry-name = "ipa"; 621 interrupt-controller; 622 #interrupt-cells = <2>; 623 }; 624 }; 625 626 smp2p-slpi { 627 compatible = "qcom,smp2p"; 628 qcom,smem = <481>, <430>; 629 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 630 IPCC_MPROC_SIGNAL_SMP2P 631 IRQ_TYPE_EDGE_RISING>; 632 mboxes = <&ipcc IPCC_CLIENT_SLPI 633 IPCC_MPROC_SIGNAL_SMP2P>; 634 635 qcom,local-pid = <0>; 636 qcom,remote-pid = <3>; 637 638 smp2p_slpi_out: master-kernel { 639 qcom,entry-name = "master-kernel"; 640 #qcom,smem-state-cells = <1>; 641 }; 642 643 smp2p_slpi_in: slave-kernel { 644 qcom,entry-name = "slave-kernel"; 645 interrupt-controller; 646 #interrupt-cells = <2>; 647 }; 648 }; 649 650 soc: soc@0 { 651 #address-cells = <2>; 652 #size-cells = <2>; 653 ranges = <0 0 0 0 0x10 0>; 654 dma-ranges = <0 0 0 0 0x10 0>; 655 compatible = "simple-bus"; 656 657 gcc: clock-controller@100000 { 658 compatible = "qcom,gcc-sm8350"; 659 reg = <0x0 0x00100000 0x0 0x1f0000>; 660 #clock-cells = <1>; 661 #reset-cells = <1>; 662 #power-domain-cells = <1>; 663 clock-names = "bi_tcxo", 664 "sleep_clk", 665 "pcie_0_pipe_clk", 666 "pcie_1_pipe_clk", 667 "ufs_card_rx_symbol_0_clk", 668 "ufs_card_rx_symbol_1_clk", 669 "ufs_card_tx_symbol_0_clk", 670 "ufs_phy_rx_symbol_0_clk", 671 "ufs_phy_rx_symbol_1_clk", 672 "ufs_phy_tx_symbol_0_clk", 673 "usb3_phy_wrapper_gcc_usb30_pipe_clk", 674 "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; 675 clocks = <&rpmhcc RPMH_CXO_CLK>, 676 <&sleep_clk>, 677 <&pcie0_phy>, 678 <&pcie1_phy>, 679 <0>, 680 <0>, 681 <0>, 682 <&ufs_mem_phy 0>, 683 <&ufs_mem_phy 1>, 684 <&ufs_mem_phy 2>, 685 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 686 <0>; 687 }; 688 689 ipcc: mailbox@408000 { 690 compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; 691 reg = <0 0x00408000 0 0x1000>; 692 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 693 interrupt-controller; 694 #interrupt-cells = <3>; 695 #mbox-cells = <2>; 696 }; 697 698 gpi_dma2: dma-controller@800000 { 699 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 700 reg = <0 0x00800000 0 0x60000>; 701 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 713 dma-channels = <12>; 714 dma-channel-mask = <0xff>; 715 iommus = <&apps_smmu 0x5f6 0x0>; 716 #dma-cells = <3>; 717 status = "disabled"; 718 }; 719 720 qupv3_id_2: geniqup@8c0000 { 721 compatible = "qcom,geni-se-qup"; 722 reg = <0x0 0x008c0000 0x0 0x6000>; 723 clock-names = "m-ahb", "s-ahb"; 724 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 725 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 726 iommus = <&apps_smmu 0x5e3 0x0>; 727 #address-cells = <2>; 728 #size-cells = <2>; 729 ranges; 730 status = "disabled"; 731 732 i2c14: i2c@880000 { 733 compatible = "qcom,geni-i2c"; 734 reg = <0 0x00880000 0 0x4000>; 735 clock-names = "se"; 736 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 737 pinctrl-names = "default"; 738 pinctrl-0 = <&qup_i2c14_default>; 739 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 740 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 741 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 742 dma-names = "tx", "rx"; 743 #address-cells = <1>; 744 #size-cells = <0>; 745 status = "disabled"; 746 }; 747 748 spi14: spi@880000 { 749 compatible = "qcom,geni-spi"; 750 reg = <0 0x00880000 0 0x4000>; 751 clock-names = "se"; 752 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 753 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 754 power-domains = <&rpmhpd RPMHPD_CX>; 755 operating-points-v2 = <&qup_opp_table_120mhz>; 756 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 757 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 758 dma-names = "tx", "rx"; 759 #address-cells = <1>; 760 #size-cells = <0>; 761 status = "disabled"; 762 }; 763 764 i2c15: i2c@884000 { 765 compatible = "qcom,geni-i2c"; 766 reg = <0 0x00884000 0 0x4000>; 767 clock-names = "se"; 768 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 769 pinctrl-names = "default"; 770 pinctrl-0 = <&qup_i2c15_default>; 771 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 772 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 773 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 774 dma-names = "tx", "rx"; 775 #address-cells = <1>; 776 #size-cells = <0>; 777 status = "disabled"; 778 }; 779 780 spi15: spi@884000 { 781 compatible = "qcom,geni-spi"; 782 reg = <0 0x00884000 0 0x4000>; 783 clock-names = "se"; 784 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 785 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 786 power-domains = <&rpmhpd RPMHPD_CX>; 787 operating-points-v2 = <&qup_opp_table_120mhz>; 788 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 789 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 790 dma-names = "tx", "rx"; 791 #address-cells = <1>; 792 #size-cells = <0>; 793 status = "disabled"; 794 }; 795 796 i2c16: i2c@888000 { 797 compatible = "qcom,geni-i2c"; 798 reg = <0 0x00888000 0 0x4000>; 799 clock-names = "se"; 800 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 801 pinctrl-names = "default"; 802 pinctrl-0 = <&qup_i2c16_default>; 803 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 804 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 805 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 806 dma-names = "tx", "rx"; 807 #address-cells = <1>; 808 #size-cells = <0>; 809 status = "disabled"; 810 }; 811 812 spi16: spi@888000 { 813 compatible = "qcom,geni-spi"; 814 reg = <0 0x00888000 0 0x4000>; 815 clock-names = "se"; 816 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 817 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 818 power-domains = <&rpmhpd RPMHPD_CX>; 819 operating-points-v2 = <&qup_opp_table_100mhz>; 820 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 821 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 822 dma-names = "tx", "rx"; 823 #address-cells = <1>; 824 #size-cells = <0>; 825 status = "disabled"; 826 }; 827 828 i2c17: i2c@88c000 { 829 compatible = "qcom,geni-i2c"; 830 reg = <0 0x0088c000 0 0x4000>; 831 clock-names = "se"; 832 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 833 pinctrl-names = "default"; 834 pinctrl-0 = <&qup_i2c17_default>; 835 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 836 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 837 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 838 dma-names = "tx", "rx"; 839 #address-cells = <1>; 840 #size-cells = <0>; 841 status = "disabled"; 842 }; 843 844 spi17: spi@88c000 { 845 compatible = "qcom,geni-spi"; 846 reg = <0 0x0088c000 0 0x4000>; 847 clock-names = "se"; 848 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 849 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 850 power-domains = <&rpmhpd RPMHPD_CX>; 851 operating-points-v2 = <&qup_opp_table_100mhz>; 852 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 853 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 854 dma-names = "tx", "rx"; 855 #address-cells = <1>; 856 #size-cells = <0>; 857 status = "disabled"; 858 }; 859 860 /* QUP no. 18 seems to be strictly SPI/UART-only */ 861 862 spi18: spi@890000 { 863 compatible = "qcom,geni-spi"; 864 reg = <0 0x00890000 0 0x4000>; 865 clock-names = "se"; 866 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 867 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 868 power-domains = <&rpmhpd RPMHPD_CX>; 869 operating-points-v2 = <&qup_opp_table_100mhz>; 870 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 871 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 872 dma-names = "tx", "rx"; 873 #address-cells = <1>; 874 #size-cells = <0>; 875 status = "disabled"; 876 }; 877 878 uart18: serial@890000 { 879 compatible = "qcom,geni-uart"; 880 reg = <0 0x00890000 0 0x4000>; 881 clock-names = "se"; 882 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 883 pinctrl-names = "default"; 884 pinctrl-0 = <&qup_uart18_default>; 885 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 886 power-domains = <&rpmhpd RPMHPD_CX>; 887 operating-points-v2 = <&qup_opp_table_100mhz>; 888 status = "disabled"; 889 }; 890 891 i2c19: i2c@894000 { 892 compatible = "qcom,geni-i2c"; 893 reg = <0 0x00894000 0 0x4000>; 894 clock-names = "se"; 895 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 896 pinctrl-names = "default"; 897 pinctrl-0 = <&qup_i2c19_default>; 898 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 899 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 900 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 901 dma-names = "tx", "rx"; 902 #address-cells = <1>; 903 #size-cells = <0>; 904 status = "disabled"; 905 }; 906 907 spi19: spi@894000 { 908 compatible = "qcom,geni-spi"; 909 reg = <0 0x00894000 0 0x4000>; 910 clock-names = "se"; 911 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 912 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 913 power-domains = <&rpmhpd RPMHPD_CX>; 914 operating-points-v2 = <&qup_opp_table_100mhz>; 915 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 916 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 917 dma-names = "tx", "rx"; 918 #address-cells = <1>; 919 #size-cells = <0>; 920 status = "disabled"; 921 }; 922 }; 923 924 gpi_dma0: dma-controller@900000 { 925 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 926 reg = <0 0x00900000 0 0x60000>; 927 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 939 dma-channels = <12>; 940 dma-channel-mask = <0x7e>; 941 iommus = <&apps_smmu 0x5b6 0x0>; 942 #dma-cells = <3>; 943 status = "disabled"; 944 }; 945 946 qupv3_id_0: geniqup@9c0000 { 947 compatible = "qcom,geni-se-qup"; 948 reg = <0x0 0x009c0000 0x0 0x6000>; 949 clock-names = "m-ahb", "s-ahb"; 950 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 951 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 952 iommus = <&apps_smmu 0x5a3 0>; 953 #address-cells = <2>; 954 #size-cells = <2>; 955 ranges; 956 status = "disabled"; 957 958 i2c0: i2c@980000 { 959 compatible = "qcom,geni-i2c"; 960 reg = <0 0x00980000 0 0x4000>; 961 clock-names = "se"; 962 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 963 pinctrl-names = "default"; 964 pinctrl-0 = <&qup_i2c0_default>; 965 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 966 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 967 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 968 dma-names = "tx", "rx"; 969 #address-cells = <1>; 970 #size-cells = <0>; 971 status = "disabled"; 972 }; 973 974 spi0: spi@980000 { 975 compatible = "qcom,geni-spi"; 976 reg = <0 0x00980000 0 0x4000>; 977 clock-names = "se"; 978 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 979 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 980 power-domains = <&rpmhpd RPMHPD_CX>; 981 operating-points-v2 = <&qup_opp_table_100mhz>; 982 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 983 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 984 dma-names = "tx", "rx"; 985 #address-cells = <1>; 986 #size-cells = <0>; 987 status = "disabled"; 988 }; 989 990 i2c1: i2c@984000 { 991 compatible = "qcom,geni-i2c"; 992 reg = <0 0x00984000 0 0x4000>; 993 clock-names = "se"; 994 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 995 pinctrl-names = "default"; 996 pinctrl-0 = <&qup_i2c1_default>; 997 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 998 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 999 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1000 dma-names = "tx", "rx"; 1001 #address-cells = <1>; 1002 #size-cells = <0>; 1003 status = "disabled"; 1004 }; 1005 1006 spi1: spi@984000 { 1007 compatible = "qcom,geni-spi"; 1008 reg = <0 0x00984000 0 0x4000>; 1009 clock-names = "se"; 1010 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1011 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1012 power-domains = <&rpmhpd RPMHPD_CX>; 1013 operating-points-v2 = <&qup_opp_table_100mhz>; 1014 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1015 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1016 dma-names = "tx", "rx"; 1017 #address-cells = <1>; 1018 #size-cells = <0>; 1019 status = "disabled"; 1020 }; 1021 1022 i2c2: i2c@988000 { 1023 compatible = "qcom,geni-i2c"; 1024 reg = <0 0x00988000 0 0x4000>; 1025 clock-names = "se"; 1026 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1027 pinctrl-names = "default"; 1028 pinctrl-0 = <&qup_i2c2_default>; 1029 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1030 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1031 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1032 dma-names = "tx", "rx"; 1033 #address-cells = <1>; 1034 #size-cells = <0>; 1035 status = "disabled"; 1036 }; 1037 1038 spi2: spi@988000 { 1039 compatible = "qcom,geni-spi"; 1040 reg = <0 0x00988000 0 0x4000>; 1041 clock-names = "se"; 1042 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1043 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1044 power-domains = <&rpmhpd RPMHPD_CX>; 1045 operating-points-v2 = <&qup_opp_table_100mhz>; 1046 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1047 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1048 dma-names = "tx", "rx"; 1049 #address-cells = <1>; 1050 #size-cells = <0>; 1051 status = "disabled"; 1052 }; 1053 1054 uart2: serial@98c000 { 1055 compatible = "qcom,geni-debug-uart"; 1056 reg = <0 0x0098c000 0 0x4000>; 1057 clock-names = "se"; 1058 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1059 pinctrl-names = "default"; 1060 pinctrl-0 = <&qup_uart3_default_state>; 1061 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1062 power-domains = <&rpmhpd RPMHPD_CX>; 1063 operating-points-v2 = <&qup_opp_table_100mhz>; 1064 status = "disabled"; 1065 }; 1066 1067 /* QUP no. 3 seems to be strictly SPI-only */ 1068 1069 spi3: spi@98c000 { 1070 compatible = "qcom,geni-spi"; 1071 reg = <0 0x0098c000 0 0x4000>; 1072 clock-names = "se"; 1073 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1074 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1075 power-domains = <&rpmhpd RPMHPD_CX>; 1076 operating-points-v2 = <&qup_opp_table_100mhz>; 1077 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1078 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1079 dma-names = "tx", "rx"; 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 status = "disabled"; 1083 }; 1084 1085 i2c4: i2c@990000 { 1086 compatible = "qcom,geni-i2c"; 1087 reg = <0 0x00990000 0 0x4000>; 1088 clock-names = "se"; 1089 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1090 pinctrl-names = "default"; 1091 pinctrl-0 = <&qup_i2c4_default>; 1092 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1093 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1094 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1095 dma-names = "tx", "rx"; 1096 #address-cells = <1>; 1097 #size-cells = <0>; 1098 status = "disabled"; 1099 }; 1100 1101 spi4: spi@990000 { 1102 compatible = "qcom,geni-spi"; 1103 reg = <0 0x00990000 0 0x4000>; 1104 clock-names = "se"; 1105 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1106 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1107 power-domains = <&rpmhpd RPMHPD_CX>; 1108 operating-points-v2 = <&qup_opp_table_100mhz>; 1109 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1110 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1111 dma-names = "tx", "rx"; 1112 #address-cells = <1>; 1113 #size-cells = <0>; 1114 status = "disabled"; 1115 }; 1116 1117 i2c5: i2c@994000 { 1118 compatible = "qcom,geni-i2c"; 1119 reg = <0 0x00994000 0 0x4000>; 1120 clock-names = "se"; 1121 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1122 pinctrl-names = "default"; 1123 pinctrl-0 = <&qup_i2c5_default>; 1124 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1125 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1126 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1127 dma-names = "tx", "rx"; 1128 #address-cells = <1>; 1129 #size-cells = <0>; 1130 status = "disabled"; 1131 }; 1132 1133 spi5: spi@994000 { 1134 compatible = "qcom,geni-spi"; 1135 reg = <0 0x00994000 0 0x4000>; 1136 clock-names = "se"; 1137 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1138 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1139 power-domains = <&rpmhpd RPMHPD_CX>; 1140 operating-points-v2 = <&qup_opp_table_100mhz>; 1141 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1142 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1143 dma-names = "tx", "rx"; 1144 #address-cells = <1>; 1145 #size-cells = <0>; 1146 status = "disabled"; 1147 }; 1148 1149 i2c6: i2c@998000 { 1150 compatible = "qcom,geni-i2c"; 1151 reg = <0 0x00998000 0 0x4000>; 1152 clock-names = "se"; 1153 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1154 pinctrl-names = "default"; 1155 pinctrl-0 = <&qup_i2c6_default>; 1156 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1157 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1158 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1159 dma-names = "tx", "rx"; 1160 #address-cells = <1>; 1161 #size-cells = <0>; 1162 status = "disabled"; 1163 }; 1164 1165 spi6: spi@998000 { 1166 compatible = "qcom,geni-spi"; 1167 reg = <0 0x00998000 0 0x4000>; 1168 clock-names = "se"; 1169 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1170 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1171 power-domains = <&rpmhpd RPMHPD_CX>; 1172 operating-points-v2 = <&qup_opp_table_100mhz>; 1173 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1174 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1175 dma-names = "tx", "rx"; 1176 #address-cells = <1>; 1177 #size-cells = <0>; 1178 status = "disabled"; 1179 }; 1180 1181 uart6: serial@998000 { 1182 compatible = "qcom,geni-uart"; 1183 reg = <0 0x00998000 0 0x4000>; 1184 clock-names = "se"; 1185 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1186 pinctrl-names = "default"; 1187 pinctrl-0 = <&qup_uart6_default>; 1188 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1189 power-domains = <&rpmhpd RPMHPD_CX>; 1190 operating-points-v2 = <&qup_opp_table_100mhz>; 1191 status = "disabled"; 1192 }; 1193 1194 i2c7: i2c@99c000 { 1195 compatible = "qcom,geni-i2c"; 1196 reg = <0 0x0099c000 0 0x4000>; 1197 clock-names = "se"; 1198 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1199 pinctrl-names = "default"; 1200 pinctrl-0 = <&qup_i2c7_default>; 1201 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1202 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1203 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1204 dma-names = "tx", "rx"; 1205 #address-cells = <1>; 1206 #size-cells = <0>; 1207 status = "disabled"; 1208 }; 1209 1210 spi7: spi@99c000 { 1211 compatible = "qcom,geni-spi"; 1212 reg = <0 0x0099c000 0 0x4000>; 1213 clock-names = "se"; 1214 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1215 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1216 power-domains = <&rpmhpd RPMHPD_CX>; 1217 operating-points-v2 = <&qup_opp_table_100mhz>; 1218 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1219 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1220 dma-names = "tx", "rx"; 1221 #address-cells = <1>; 1222 #size-cells = <0>; 1223 status = "disabled"; 1224 }; 1225 }; 1226 1227 gpi_dma1: dma-controller@a00000 { 1228 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 1229 reg = <0 0x00a00000 0 0x60000>; 1230 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1242 dma-channels = <12>; 1243 dma-channel-mask = <0xff>; 1244 iommus = <&apps_smmu 0x56 0x0>; 1245 #dma-cells = <3>; 1246 status = "disabled"; 1247 }; 1248 1249 qupv3_id_1: geniqup@ac0000 { 1250 compatible = "qcom,geni-se-qup"; 1251 reg = <0x0 0x00ac0000 0x0 0x6000>; 1252 clock-names = "m-ahb", "s-ahb"; 1253 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1254 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1255 iommus = <&apps_smmu 0x43 0>; 1256 #address-cells = <2>; 1257 #size-cells = <2>; 1258 ranges; 1259 status = "disabled"; 1260 1261 i2c8: i2c@a80000 { 1262 compatible = "qcom,geni-i2c"; 1263 reg = <0 0x00a80000 0 0x4000>; 1264 clock-names = "se"; 1265 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1266 pinctrl-names = "default"; 1267 pinctrl-0 = <&qup_i2c8_default>; 1268 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1269 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1270 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1271 dma-names = "tx", "rx"; 1272 #address-cells = <1>; 1273 #size-cells = <0>; 1274 status = "disabled"; 1275 }; 1276 1277 spi8: spi@a80000 { 1278 compatible = "qcom,geni-spi"; 1279 reg = <0 0x00a80000 0 0x4000>; 1280 clock-names = "se"; 1281 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1282 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1283 power-domains = <&rpmhpd RPMHPD_CX>; 1284 operating-points-v2 = <&qup_opp_table_120mhz>; 1285 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1286 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1287 dma-names = "tx", "rx"; 1288 #address-cells = <1>; 1289 #size-cells = <0>; 1290 status = "disabled"; 1291 }; 1292 1293 i2c9: i2c@a84000 { 1294 compatible = "qcom,geni-i2c"; 1295 reg = <0 0x00a84000 0 0x4000>; 1296 clock-names = "se"; 1297 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1298 pinctrl-names = "default"; 1299 pinctrl-0 = <&qup_i2c9_default>; 1300 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1301 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1302 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1303 dma-names = "tx", "rx"; 1304 #address-cells = <1>; 1305 #size-cells = <0>; 1306 status = "disabled"; 1307 }; 1308 1309 spi9: spi@a84000 { 1310 compatible = "qcom,geni-spi"; 1311 reg = <0 0x00a84000 0 0x4000>; 1312 clock-names = "se"; 1313 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1314 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1315 power-domains = <&rpmhpd RPMHPD_CX>; 1316 operating-points-v2 = <&qup_opp_table_100mhz>; 1317 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1318 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1319 dma-names = "tx", "rx"; 1320 #address-cells = <1>; 1321 #size-cells = <0>; 1322 status = "disabled"; 1323 }; 1324 1325 i2c10: i2c@a88000 { 1326 compatible = "qcom,geni-i2c"; 1327 reg = <0 0x00a88000 0 0x4000>; 1328 clock-names = "se"; 1329 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1330 pinctrl-names = "default"; 1331 pinctrl-0 = <&qup_i2c10_default>; 1332 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1333 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1334 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1335 dma-names = "tx", "rx"; 1336 #address-cells = <1>; 1337 #size-cells = <0>; 1338 status = "disabled"; 1339 }; 1340 1341 spi10: spi@a88000 { 1342 compatible = "qcom,geni-spi"; 1343 reg = <0 0x00a88000 0 0x4000>; 1344 clock-names = "se"; 1345 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1346 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1347 power-domains = <&rpmhpd RPMHPD_CX>; 1348 operating-points-v2 = <&qup_opp_table_100mhz>; 1349 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1350 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1351 dma-names = "tx", "rx"; 1352 #address-cells = <1>; 1353 #size-cells = <0>; 1354 status = "disabled"; 1355 }; 1356 1357 i2c11: i2c@a8c000 { 1358 compatible = "qcom,geni-i2c"; 1359 reg = <0 0x00a8c000 0 0x4000>; 1360 clock-names = "se"; 1361 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1362 pinctrl-names = "default"; 1363 pinctrl-0 = <&qup_i2c11_default>; 1364 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1365 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1366 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1367 dma-names = "tx", "rx"; 1368 #address-cells = <1>; 1369 #size-cells = <0>; 1370 status = "disabled"; 1371 }; 1372 1373 spi11: spi@a8c000 { 1374 compatible = "qcom,geni-spi"; 1375 reg = <0 0x00a8c000 0 0x4000>; 1376 clock-names = "se"; 1377 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1378 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1379 power-domains = <&rpmhpd RPMHPD_CX>; 1380 operating-points-v2 = <&qup_opp_table_100mhz>; 1381 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1382 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1383 dma-names = "tx", "rx"; 1384 #address-cells = <1>; 1385 #size-cells = <0>; 1386 status = "disabled"; 1387 }; 1388 1389 i2c12: i2c@a90000 { 1390 compatible = "qcom,geni-i2c"; 1391 reg = <0 0x00a90000 0 0x4000>; 1392 clock-names = "se"; 1393 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1394 pinctrl-names = "default"; 1395 pinctrl-0 = <&qup_i2c12_default>; 1396 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1397 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1398 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1399 dma-names = "tx", "rx"; 1400 #address-cells = <1>; 1401 #size-cells = <0>; 1402 status = "disabled"; 1403 }; 1404 1405 spi12: spi@a90000 { 1406 compatible = "qcom,geni-spi"; 1407 reg = <0 0x00a90000 0 0x4000>; 1408 clock-names = "se"; 1409 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1410 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1411 power-domains = <&rpmhpd RPMHPD_CX>; 1412 operating-points-v2 = <&qup_opp_table_100mhz>; 1413 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1414 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1415 dma-names = "tx", "rx"; 1416 #address-cells = <1>; 1417 #size-cells = <0>; 1418 status = "disabled"; 1419 }; 1420 1421 i2c13: i2c@a94000 { 1422 compatible = "qcom,geni-i2c"; 1423 reg = <0 0x00a94000 0 0x4000>; 1424 clock-names = "se"; 1425 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1426 pinctrl-names = "default"; 1427 pinctrl-0 = <&qup_i2c13_default>; 1428 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1429 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1430 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1431 dma-names = "tx", "rx"; 1432 #address-cells = <1>; 1433 #size-cells = <0>; 1434 status = "disabled"; 1435 }; 1436 1437 spi13: spi@a94000 { 1438 compatible = "qcom,geni-spi"; 1439 reg = <0 0x00a94000 0 0x4000>; 1440 clock-names = "se"; 1441 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1442 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1443 power-domains = <&rpmhpd RPMHPD_CX>; 1444 operating-points-v2 = <&qup_opp_table_100mhz>; 1445 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1446 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1447 dma-names = "tx", "rx"; 1448 #address-cells = <1>; 1449 #size-cells = <0>; 1450 status = "disabled"; 1451 }; 1452 }; 1453 1454 rng: rng@10d3000 { 1455 compatible = "qcom,prng-ee"; 1456 reg = <0 0x010d3000 0 0x1000>; 1457 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1458 clock-names = "core"; 1459 }; 1460 1461 config_noc: interconnect@1500000 { 1462 compatible = "qcom,sm8350-config-noc"; 1463 reg = <0 0x01500000 0 0xa580>; 1464 #interconnect-cells = <2>; 1465 qcom,bcm-voters = <&apps_bcm_voter>; 1466 }; 1467 1468 mc_virt: interconnect@1580000 { 1469 compatible = "qcom,sm8350-mc-virt"; 1470 reg = <0 0x01580000 0 0x1000>; 1471 #interconnect-cells = <2>; 1472 qcom,bcm-voters = <&apps_bcm_voter>; 1473 }; 1474 1475 system_noc: interconnect@1680000 { 1476 compatible = "qcom,sm8350-system-noc"; 1477 reg = <0 0x01680000 0 0x1c200>; 1478 #interconnect-cells = <2>; 1479 qcom,bcm-voters = <&apps_bcm_voter>; 1480 }; 1481 1482 aggre1_noc: interconnect@16e0000 { 1483 compatible = "qcom,sm8350-aggre1-noc"; 1484 reg = <0 0x016e0000 0 0x1f180>; 1485 #interconnect-cells = <2>; 1486 qcom,bcm-voters = <&apps_bcm_voter>; 1487 }; 1488 1489 aggre2_noc: interconnect@1700000 { 1490 compatible = "qcom,sm8350-aggre2-noc"; 1491 reg = <0 0x01700000 0 0x33000>; 1492 #interconnect-cells = <2>; 1493 qcom,bcm-voters = <&apps_bcm_voter>; 1494 }; 1495 1496 mmss_noc: interconnect@1740000 { 1497 compatible = "qcom,sm8350-mmss-noc"; 1498 reg = <0 0x01740000 0 0x1f080>; 1499 #interconnect-cells = <2>; 1500 qcom,bcm-voters = <&apps_bcm_voter>; 1501 }; 1502 1503 pcie0: pcie@1c00000 { 1504 compatible = "qcom,pcie-sm8350"; 1505 reg = <0 0x01c00000 0 0x3000>, 1506 <0 0x60000000 0 0xf1d>, 1507 <0 0x60000f20 0 0xa8>, 1508 <0 0x60001000 0 0x1000>, 1509 <0 0x60100000 0 0x100000>; 1510 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1511 device_type = "pci"; 1512 linux,pci-domain = <0>; 1513 bus-range = <0x00 0xff>; 1514 num-lanes = <1>; 1515 1516 #address-cells = <3>; 1517 #size-cells = <2>; 1518 1519 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1520 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1521 1522 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1530 interrupt-names = "msi0", 1531 "msi1", 1532 "msi2", 1533 "msi3", 1534 "msi4", 1535 "msi5", 1536 "msi6", 1537 "msi7"; 1538 #interrupt-cells = <1>; 1539 interrupt-map-mask = <0 0 0 0x7>; 1540 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1541 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1542 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1543 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1544 1545 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1546 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1547 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1548 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1549 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1550 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1551 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1552 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1553 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; 1554 clock-names = "aux", 1555 "cfg", 1556 "bus_master", 1557 "bus_slave", 1558 "slave_q2a", 1559 "tbu", 1560 "ddrss_sf_tbu", 1561 "aggre1", 1562 "aggre0"; 1563 1564 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1565 <0x100 &apps_smmu 0x1c01 0x1>; 1566 1567 resets = <&gcc GCC_PCIE_0_BCR>; 1568 reset-names = "pci"; 1569 1570 power-domains = <&gcc PCIE_0_GDSC>; 1571 1572 phys = <&pcie0_phy>; 1573 phy-names = "pciephy"; 1574 1575 status = "disabled"; 1576 1577 pcie@0 { 1578 device_type = "pci"; 1579 reg = <0x0 0x0 0x0 0x0 0x0>; 1580 bus-range = <0x01 0xff>; 1581 1582 #address-cells = <3>; 1583 #size-cells = <2>; 1584 ranges; 1585 }; 1586 }; 1587 1588 pcie0_phy: phy@1c06000 { 1589 compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy"; 1590 reg = <0 0x01c06000 0 0x2000>; 1591 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1592 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1593 <&gcc GCC_PCIE_0_CLKREF_EN>, 1594 <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, 1595 <&gcc GCC_PCIE_0_PIPE_CLK>; 1596 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1597 1598 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1599 reset-names = "phy"; 1600 1601 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>; 1602 assigned-clock-rates = <100000000>; 1603 1604 #clock-cells = <0>; 1605 clock-output-names = "pcie_0_pipe_clk"; 1606 1607 #phy-cells = <0>; 1608 1609 status = "disabled"; 1610 }; 1611 1612 pcie1: pcie@1c08000 { 1613 compatible = "qcom,pcie-sm8350"; 1614 reg = <0 0x01c08000 0 0x3000>, 1615 <0 0x40000000 0 0xf1d>, 1616 <0 0x40000f20 0 0xa8>, 1617 <0 0x40001000 0 0x1000>, 1618 <0 0x40100000 0 0x100000>; 1619 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1620 device_type = "pci"; 1621 linux,pci-domain = <1>; 1622 bus-range = <0x00 0xff>; 1623 num-lanes = <2>; 1624 1625 #address-cells = <3>; 1626 #size-cells = <2>; 1627 1628 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1629 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1630 1631 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1632 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1633 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1634 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1636 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1637 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 1638 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1639 interrupt-names = "msi0", 1640 "msi1", 1641 "msi2", 1642 "msi3", 1643 "msi4", 1644 "msi5", 1645 "msi6", 1646 "msi7"; 1647 #interrupt-cells = <1>; 1648 interrupt-map-mask = <0 0 0 0x7>; 1649 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1650 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1651 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1652 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1653 1654 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1655 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1656 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1657 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1658 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1659 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1660 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1661 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1662 clock-names = "aux", 1663 "cfg", 1664 "bus_master", 1665 "bus_slave", 1666 "slave_q2a", 1667 "tbu", 1668 "ddrss_sf_tbu", 1669 "aggre1"; 1670 1671 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1672 <0x100 &apps_smmu 0x1c81 0x1>; 1673 1674 resets = <&gcc GCC_PCIE_1_BCR>; 1675 reset-names = "pci"; 1676 1677 power-domains = <&gcc PCIE_1_GDSC>; 1678 1679 phys = <&pcie1_phy>; 1680 phy-names = "pciephy"; 1681 1682 status = "disabled"; 1683 1684 pcie@0 { 1685 device_type = "pci"; 1686 reg = <0x0 0x0 0x0 0x0 0x0>; 1687 bus-range = <0x01 0xff>; 1688 1689 #address-cells = <3>; 1690 #size-cells = <2>; 1691 ranges; 1692 }; 1693 }; 1694 1695 pcie1_phy: phy@1c0e000 { 1696 compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy"; 1697 reg = <0 0x01c0e000 0 0x2000>; 1698 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1699 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1700 <&gcc GCC_PCIE_1_CLKREF_EN>, 1701 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, 1702 <&gcc GCC_PCIE_1_PIPE_CLK>; 1703 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1704 1705 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1706 reset-names = "phy"; 1707 1708 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1709 assigned-clock-rates = <100000000>; 1710 1711 #clock-cells = <0>; 1712 clock-output-names = "pcie_1_pipe_clk"; 1713 1714 #phy-cells = <0>; 1715 1716 status = "disabled"; 1717 }; 1718 1719 ufs_mem_hc: ufshc@1d84000 { 1720 compatible = "qcom,sm8350-ufshc", "qcom,ufshc", 1721 "jedec,ufs-2.0"; 1722 reg = <0 0x01d84000 0 0x3000>; 1723 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1724 phys = <&ufs_mem_phy>; 1725 phy-names = "ufsphy"; 1726 lanes-per-direction = <2>; 1727 #reset-cells = <1>; 1728 resets = <&gcc GCC_UFS_PHY_BCR>; 1729 reset-names = "rst"; 1730 1731 power-domains = <&gcc UFS_PHY_GDSC>; 1732 1733 iommus = <&apps_smmu 0xe0 0x0>; 1734 dma-coherent; 1735 1736 clock-names = 1737 "core_clk", 1738 "bus_aggr_clk", 1739 "iface_clk", 1740 "core_clk_unipro", 1741 "ref_clk", 1742 "tx_lane0_sync_clk", 1743 "rx_lane0_sync_clk", 1744 "rx_lane1_sync_clk"; 1745 clocks = 1746 <&gcc GCC_UFS_PHY_AXI_CLK>, 1747 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1748 <&gcc GCC_UFS_PHY_AHB_CLK>, 1749 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1750 <&rpmhcc RPMH_CXO_CLK>, 1751 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1752 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1753 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1754 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 1755 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1756 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1757 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 1758 interconnect-names = "ufs-ddr", "cpu-ufs"; 1759 freq-table-hz = 1760 <75000000 300000000>, 1761 <0 0>, 1762 <0 0>, 1763 <75000000 300000000>, 1764 <0 0>, 1765 <0 0>, 1766 <0 0>, 1767 <0 0>; 1768 status = "disabled"; 1769 }; 1770 1771 ufs_mem_phy: phy@1d87000 { 1772 compatible = "qcom,sm8350-qmp-ufs-phy"; 1773 reg = <0 0x01d87000 0 0x1000>; 1774 1775 clocks = <&rpmhcc RPMH_CXO_CLK>, 1776 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1777 <&gcc GCC_UFS_1_CLKREF_EN>; 1778 clock-names = "ref", 1779 "ref_aux", 1780 "qref"; 1781 1782 resets = <&ufs_mem_hc 0>; 1783 reset-names = "ufsphy"; 1784 1785 #clock-cells = <1>; 1786 #phy-cells = <0>; 1787 1788 status = "disabled"; 1789 }; 1790 1791 cryptobam: dma-controller@1dc4000 { 1792 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1793 reg = <0 0x01dc4000 0 0x24000>; 1794 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1795 #dma-cells = <1>; 1796 qcom,ee = <0>; 1797 qcom,controlled-remotely; 1798 iommus = <&apps_smmu 0x594 0x0011>, 1799 <&apps_smmu 0x596 0x0011>; 1800 /* FIXME: Probing BAM DMA causes some abort and system hang */ 1801 status = "fail"; 1802 }; 1803 1804 crypto: crypto@1dfa000 { 1805 compatible = "qcom,sm8350-qce", "qcom,sm8150-qce", "qcom,qce"; 1806 reg = <0 0x01dfa000 0 0x6000>; 1807 dmas = <&cryptobam 4>, <&cryptobam 5>; 1808 dma-names = "rx", "tx"; 1809 iommus = <&apps_smmu 0x594 0x0011>, 1810 <&apps_smmu 0x596 0x0011>; 1811 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 1812 interconnect-names = "memory"; 1813 /* FIXME: dependency BAM DMA is disabled */ 1814 status = "disabled"; 1815 }; 1816 1817 ipa: ipa@1e40000 { 1818 compatible = "qcom,sm8350-ipa"; 1819 1820 iommus = <&apps_smmu 0x5c0 0x0>, 1821 <&apps_smmu 0x5c2 0x0>; 1822 reg = <0 0x01e40000 0 0x8000>, 1823 <0 0x01e50000 0 0x4b20>, 1824 <0 0x01e04000 0 0x23000>; 1825 reg-names = "ipa-reg", 1826 "ipa-shared", 1827 "gsi"; 1828 1829 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, 1830 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1831 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1832 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1833 interrupt-names = "ipa", 1834 "gsi", 1835 "ipa-clock-query", 1836 "ipa-setup-ready"; 1837 1838 clocks = <&rpmhcc RPMH_IPA_CLK>; 1839 clock-names = "core"; 1840 1841 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1842 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1843 interconnect-names = "memory", 1844 "config"; 1845 1846 qcom,qmp = <&aoss_qmp>; 1847 1848 qcom,smem-states = <&ipa_smp2p_out 0>, 1849 <&ipa_smp2p_out 1>; 1850 qcom,smem-state-names = "ipa-clock-enabled-valid", 1851 "ipa-clock-enabled"; 1852 1853 status = "disabled"; 1854 }; 1855 1856 tcsr_mutex: hwlock@1f40000 { 1857 compatible = "qcom,tcsr-mutex"; 1858 reg = <0x0 0x01f40000 0x0 0x40000>; 1859 #hwlock-cells = <1>; 1860 }; 1861 1862 tcsr: syscon@1fc0000 { 1863 compatible = "qcom,sm8350-tcsr", "syscon"; 1864 reg = <0x0 0x1fc0000 0x0 0x30000>; 1865 }; 1866 1867 lpass_tlmm: pinctrl@33c0000 { 1868 compatible = "qcom,sm8350-lpass-lpi-pinctrl"; 1869 reg = <0 0x033c0000 0 0x20000>, 1870 <0 0x03550000 0 0x10000>; 1871 1872 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 1873 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 1874 clock-names = "core", "audio"; 1875 1876 gpio-controller; 1877 #gpio-cells = <2>; 1878 gpio-ranges = <&lpass_tlmm 0 0 15>; 1879 }; 1880 1881 gpu: gpu@3d00000 { 1882 compatible = "qcom,adreno-660.1", "qcom,adreno"; 1883 1884 reg = <0 0x03d00000 0 0x40000>, 1885 <0 0x03d9e000 0 0x1000>, 1886 <0 0x03d61000 0 0x800>; 1887 reg-names = "kgsl_3d0_reg_memory", 1888 "cx_mem", 1889 "cx_dbgc"; 1890 1891 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1892 1893 iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>; 1894 1895 operating-points-v2 = <&gpu_opp_table>; 1896 1897 qcom,gmu = <&gmu>; 1898 #cooling-cells = <2>; 1899 1900 status = "disabled"; 1901 1902 zap-shader { 1903 memory-region = <&pil_gpu_mem>; 1904 }; 1905 1906 /* note: downstream checks gpu binning for 670 Mhz */ 1907 gpu_opp_table: opp-table { 1908 compatible = "operating-points-v2"; 1909 1910 opp-840000000 { 1911 opp-hz = /bits/ 64 <840000000>; 1912 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1913 }; 1914 1915 opp-778000000 { 1916 opp-hz = /bits/ 64 <778000000>; 1917 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1918 }; 1919 1920 opp-738000000 { 1921 opp-hz = /bits/ 64 <738000000>; 1922 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1923 }; 1924 1925 opp-676000000 { 1926 opp-hz = /bits/ 64 <676000000>; 1927 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1928 }; 1929 1930 opp-608000000 { 1931 opp-hz = /bits/ 64 <608000000>; 1932 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1933 }; 1934 1935 opp-540000000 { 1936 opp-hz = /bits/ 64 <540000000>; 1937 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1938 }; 1939 1940 opp-491000000 { 1941 opp-hz = /bits/ 64 <491000000>; 1942 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 1943 }; 1944 1945 opp-443000000 { 1946 opp-hz = /bits/ 64 <443000000>; 1947 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1948 }; 1949 1950 opp-379000000 { 1951 opp-hz = /bits/ 64 <379000000>; 1952 opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>; 1953 }; 1954 1955 opp-315000000 { 1956 opp-hz = /bits/ 64 <315000000>; 1957 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1958 }; 1959 }; 1960 }; 1961 1962 gmu: gmu@3d6a000 { 1963 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu"; 1964 1965 reg = <0 0x03d6a000 0 0x34000>, 1966 <0 0x03de0000 0 0x10000>, 1967 <0 0x0b290000 0 0x10000>; 1968 reg-names = "gmu", "rscc", "gmu_pdc"; 1969 1970 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1971 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1972 interrupt-names = "hfi", "gmu"; 1973 1974 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 1975 <&gpucc GPU_CC_CXO_CLK>, 1976 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1977 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1978 <&gpucc GPU_CC_AHB_CLK>, 1979 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 1980 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 1981 clock-names = "gmu", 1982 "cxo", 1983 "axi", 1984 "memnoc", 1985 "ahb", 1986 "hub", 1987 "smmu_vote"; 1988 1989 power-domains = <&gpucc GPU_CX_GDSC>, 1990 <&gpucc GPU_GX_GDSC>; 1991 power-domain-names = "cx", 1992 "gx"; 1993 1994 iommus = <&adreno_smmu 5 0x400>; 1995 1996 operating-points-v2 = <&gmu_opp_table>; 1997 1998 gmu_opp_table: opp-table { 1999 compatible = "operating-points-v2"; 2000 2001 opp-200000000 { 2002 opp-hz = /bits/ 64 <200000000>; 2003 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2004 }; 2005 }; 2006 }; 2007 2008 gpucc: clock-controller@3d90000 { 2009 compatible = "qcom,sm8350-gpucc"; 2010 reg = <0 0x03d90000 0 0x9000>; 2011 clocks = <&rpmhcc RPMH_CXO_CLK>, 2012 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2013 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2014 clock-names = "bi_tcxo", 2015 "gcc_gpu_gpll0_clk_src", 2016 "gcc_gpu_gpll0_div_clk_src"; 2017 #clock-cells = <1>; 2018 #reset-cells = <1>; 2019 #power-domain-cells = <1>; 2020 }; 2021 2022 adreno_smmu: iommu@3da0000 { 2023 compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu", 2024 "qcom,smmu-500", "arm,mmu-500"; 2025 reg = <0 0x03da0000 0 0x20000>; 2026 #iommu-cells = <2>; 2027 #global-interrupts = <2>; 2028 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2029 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2030 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2031 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2032 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2033 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2034 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2035 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2036 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2037 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2038 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2039 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2040 2041 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2042 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2043 <&gpucc GPU_CC_AHB_CLK>, 2044 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2045 <&gpucc GPU_CC_CX_GMU_CLK>, 2046 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2047 <&gpucc GPU_CC_HUB_AON_CLK>; 2048 clock-names = "bus", 2049 "iface", 2050 "ahb", 2051 "hlos1_vote_gpu_smmu", 2052 "cx_gmu", 2053 "hub_cx_int", 2054 "hub_aon"; 2055 2056 power-domains = <&gpucc GPU_CX_GDSC>; 2057 dma-coherent; 2058 }; 2059 2060 lpass_ag_noc: interconnect@3c40000 { 2061 compatible = "qcom,sm8350-lpass-ag-noc"; 2062 reg = <0 0x03c40000 0 0xf080>; 2063 #interconnect-cells = <2>; 2064 qcom,bcm-voters = <&apps_bcm_voter>; 2065 }; 2066 2067 mpss: remoteproc@4080000 { 2068 compatible = "qcom,sm8350-mpss-pas"; 2069 reg = <0x0 0x04080000 0x0 0x4040>; 2070 2071 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2072 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2073 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2074 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2075 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2076 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2077 interrupt-names = "wdog", "fatal", "ready", "handover", 2078 "stop-ack", "shutdown-ack"; 2079 2080 clocks = <&rpmhcc RPMH_CXO_CLK>; 2081 clock-names = "xo"; 2082 2083 power-domains = <&rpmhpd RPMHPD_CX>, 2084 <&rpmhpd RPMHPD_MSS>; 2085 power-domain-names = "cx", "mss"; 2086 2087 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2088 2089 memory-region = <&pil_modem_mem>; 2090 2091 qcom,qmp = <&aoss_qmp>; 2092 2093 qcom,smem-states = <&smp2p_modem_out 0>; 2094 qcom,smem-state-names = "stop"; 2095 2096 status = "disabled"; 2097 2098 glink-edge { 2099 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2100 IPCC_MPROC_SIGNAL_GLINK_QMP 2101 IRQ_TYPE_EDGE_RISING>; 2102 mboxes = <&ipcc IPCC_CLIENT_MPSS 2103 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2104 label = "modem"; 2105 qcom,remote-pid = <1>; 2106 }; 2107 }; 2108 2109 slpi: remoteproc@5c00000 { 2110 compatible = "qcom,sm8350-slpi-pas"; 2111 reg = <0 0x05c00000 0 0x4000>; 2112 2113 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2114 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2115 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2116 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2117 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2118 interrupt-names = "wdog", "fatal", "ready", 2119 "handover", "stop-ack"; 2120 2121 clocks = <&rpmhcc RPMH_CXO_CLK>; 2122 clock-names = "xo"; 2123 2124 power-domains = <&rpmhpd RPMHPD_LCX>, 2125 <&rpmhpd RPMHPD_LMX>; 2126 power-domain-names = "lcx", "lmx"; 2127 2128 memory-region = <&pil_slpi_mem>; 2129 2130 qcom,qmp = <&aoss_qmp>; 2131 2132 qcom,smem-states = <&smp2p_slpi_out 0>; 2133 qcom,smem-state-names = "stop"; 2134 2135 status = "disabled"; 2136 2137 glink-edge { 2138 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2139 IPCC_MPROC_SIGNAL_GLINK_QMP 2140 IRQ_TYPE_EDGE_RISING>; 2141 mboxes = <&ipcc IPCC_CLIENT_SLPI 2142 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2143 2144 label = "slpi"; 2145 qcom,remote-pid = <3>; 2146 2147 fastrpc { 2148 compatible = "qcom,fastrpc"; 2149 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2150 label = "sdsp"; 2151 qcom,non-secure-domain; 2152 #address-cells = <1>; 2153 #size-cells = <0>; 2154 2155 compute-cb@1 { 2156 compatible = "qcom,fastrpc-compute-cb"; 2157 reg = <1>; 2158 iommus = <&apps_smmu 0x0541 0x0>; 2159 }; 2160 2161 compute-cb@2 { 2162 compatible = "qcom,fastrpc-compute-cb"; 2163 reg = <2>; 2164 iommus = <&apps_smmu 0x0542 0x0>; 2165 }; 2166 2167 compute-cb@3 { 2168 compatible = "qcom,fastrpc-compute-cb"; 2169 reg = <3>; 2170 iommus = <&apps_smmu 0x0543 0x0>; 2171 /* note: shared-cb = <4> in downstream */ 2172 }; 2173 }; 2174 }; 2175 }; 2176 2177 sdhc_2: mmc@8804000 { 2178 compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5"; 2179 reg = <0 0x08804000 0 0x1000>; 2180 2181 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2182 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2183 interrupt-names = "hc_irq", "pwr_irq"; 2184 2185 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2186 <&gcc GCC_SDCC2_APPS_CLK>, 2187 <&rpmhcc RPMH_CXO_CLK>; 2188 clock-names = "iface", "core", "xo"; 2189 resets = <&gcc GCC_SDCC2_BCR>; 2190 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2191 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2192 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2193 iommus = <&apps_smmu 0x4a0 0x0>; 2194 power-domains = <&rpmhpd RPMHPD_CX>; 2195 operating-points-v2 = <&sdhc2_opp_table>; 2196 bus-width = <4>; 2197 dma-coherent; 2198 2199 status = "disabled"; 2200 2201 sdhc2_opp_table: opp-table { 2202 compatible = "operating-points-v2"; 2203 2204 opp-100000000 { 2205 opp-hz = /bits/ 64 <100000000>; 2206 required-opps = <&rpmhpd_opp_low_svs>; 2207 }; 2208 2209 opp-202000000 { 2210 opp-hz = /bits/ 64 <202000000>; 2211 required-opps = <&rpmhpd_opp_svs_l1>; 2212 }; 2213 }; 2214 }; 2215 2216 usb_1_hsphy: phy@88e3000 { 2217 compatible = "qcom,sm8350-usb-hs-phy", 2218 "qcom,usb-snps-hs-7nm-phy"; 2219 reg = <0 0x088e3000 0 0x400>; 2220 status = "disabled"; 2221 #phy-cells = <0>; 2222 2223 clocks = <&rpmhcc RPMH_CXO_CLK>; 2224 clock-names = "ref"; 2225 2226 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2227 }; 2228 2229 usb_2_hsphy: phy@88e4000 { 2230 compatible = "qcom,sm8250-usb-hs-phy", 2231 "qcom,usb-snps-hs-7nm-phy"; 2232 reg = <0 0x088e4000 0 0x400>; 2233 status = "disabled"; 2234 #phy-cells = <0>; 2235 2236 clocks = <&rpmhcc RPMH_CXO_CLK>; 2237 clock-names = "ref"; 2238 2239 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2240 }; 2241 2242 usb_1_qmpphy: phy@88e8000 { 2243 compatible = "qcom,sm8350-qmp-usb3-dp-phy"; 2244 reg = <0 0x088e8000 0 0x3000>; 2245 2246 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2247 <&rpmhcc RPMH_CXO_CLK>, 2248 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2249 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2250 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2251 2252 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2253 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2254 reset-names = "phy", "common"; 2255 2256 #clock-cells = <1>; 2257 #phy-cells = <1>; 2258 2259 status = "disabled"; 2260 2261 ports { 2262 #address-cells = <1>; 2263 #size-cells = <0>; 2264 2265 port@0 { 2266 reg = <0>; 2267 2268 usb_1_qmpphy_out: endpoint { 2269 }; 2270 }; 2271 2272 port@1 { 2273 reg = <1>; 2274 2275 usb_1_qmpphy_usb_ss_in: endpoint { 2276 }; 2277 }; 2278 2279 port@2 { 2280 reg = <2>; 2281 2282 usb_1_qmpphy_dp_in: endpoint { 2283 }; 2284 }; 2285 }; 2286 }; 2287 2288 usb_2_qmpphy: phy@88eb000 { 2289 compatible = "qcom,sm8350-qmp-usb3-uni-phy"; 2290 reg = <0 0x088eb000 0 0x2000>; 2291 status = "disabled"; 2292 2293 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2294 <&gcc GCC_USB3_SEC_CLKREF_EN>, 2295 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2296 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2297 clock-names = "aux", 2298 "ref", 2299 "com_aux", 2300 "pipe"; 2301 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2302 #clock-cells = <0>; 2303 #phy-cells = <0>; 2304 2305 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2306 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 2307 reset-names = "phy", 2308 "phy_phy"; 2309 }; 2310 2311 dc_noc: interconnect@90c0000 { 2312 compatible = "qcom,sm8350-dc-noc"; 2313 reg = <0 0x090c0000 0 0x4200>; 2314 #interconnect-cells = <2>; 2315 qcom,bcm-voters = <&apps_bcm_voter>; 2316 }; 2317 2318 gem_noc: interconnect@9100000 { 2319 compatible = "qcom,sm8350-gem-noc"; 2320 reg = <0 0x09100000 0 0xb4000>; 2321 #interconnect-cells = <2>; 2322 qcom,bcm-voters = <&apps_bcm_voter>; 2323 }; 2324 2325 system-cache-controller@9200000 { 2326 compatible = "qcom,sm8350-llcc"; 2327 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 2328 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 2329 <0 0x09600000 0 0x58000>; 2330 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2331 "llcc3_base", "llcc_broadcast_base"; 2332 }; 2333 2334 compute_noc: interconnect@a0c0000 { 2335 compatible = "qcom,sm8350-compute-noc"; 2336 reg = <0 0x0a0c0000 0 0xa180>; 2337 #interconnect-cells = <2>; 2338 qcom,bcm-voters = <&apps_bcm_voter>; 2339 }; 2340 2341 usb_1: usb@a6f8800 { 2342 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2343 reg = <0 0x0a6f8800 0 0x400>; 2344 status = "disabled"; 2345 #address-cells = <2>; 2346 #size-cells = <2>; 2347 ranges; 2348 2349 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2350 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2351 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2352 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2353 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 2354 clock-names = "cfg_noc", 2355 "core", 2356 "iface", 2357 "sleep", 2358 "mock_utmi"; 2359 2360 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2361 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2362 assigned-clock-rates = <19200000>, <200000000>; 2363 2364 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2365 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2366 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2367 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2368 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2369 interrupt-names = "pwr_event", 2370 "hs_phy_irq", 2371 "dp_hs_phy_irq", 2372 "dm_hs_phy_irq", 2373 "ss_phy_irq"; 2374 2375 power-domains = <&gcc USB30_PRIM_GDSC>; 2376 2377 resets = <&gcc GCC_USB30_PRIM_BCR>; 2378 2379 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2380 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 2381 interconnect-names = "usb-ddr", "apps-usb"; 2382 2383 usb_1_dwc3: usb@a600000 { 2384 compatible = "snps,dwc3"; 2385 reg = <0 0x0a600000 0 0xcd00>; 2386 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2387 iommus = <&apps_smmu 0x0 0x0>; 2388 snps,dis_u2_susphy_quirk; 2389 snps,dis_enblslpm_quirk; 2390 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 2391 phy-names = "usb2-phy", "usb3-phy"; 2392 2393 ports { 2394 #address-cells = <1>; 2395 #size-cells = <0>; 2396 2397 port@0 { 2398 reg = <0>; 2399 2400 usb_1_dwc3_hs: endpoint { 2401 }; 2402 }; 2403 2404 port@1 { 2405 reg = <1>; 2406 2407 usb_1_dwc3_ss: endpoint { 2408 }; 2409 }; 2410 }; 2411 }; 2412 }; 2413 2414 usb_2: usb@a8f8800 { 2415 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2416 reg = <0 0x0a8f8800 0 0x400>; 2417 status = "disabled"; 2418 #address-cells = <2>; 2419 #size-cells = <2>; 2420 ranges; 2421 2422 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2423 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2424 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2425 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2426 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2427 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2428 clock-names = "cfg_noc", 2429 "core", 2430 "iface", 2431 "sleep", 2432 "mock_utmi", 2433 "xo"; 2434 2435 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2436 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2437 assigned-clock-rates = <19200000>, <200000000>; 2438 2439 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 2440 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2441 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 2442 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 2443 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 2444 interrupt-names = "pwr_event", 2445 "hs_phy_irq", 2446 "dp_hs_phy_irq", 2447 "dm_hs_phy_irq", 2448 "ss_phy_irq"; 2449 2450 power-domains = <&gcc USB30_SEC_GDSC>; 2451 2452 resets = <&gcc GCC_USB30_SEC_BCR>; 2453 2454 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 2455 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 2456 interconnect-names = "usb-ddr", "apps-usb"; 2457 2458 usb_2_dwc3: usb@a800000 { 2459 compatible = "snps,dwc3"; 2460 reg = <0 0x0a800000 0 0xcd00>; 2461 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2462 iommus = <&apps_smmu 0x20 0x0>; 2463 snps,dis_u2_susphy_quirk; 2464 snps,dis_enblslpm_quirk; 2465 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>; 2466 phy-names = "usb2-phy", "usb3-phy"; 2467 }; 2468 }; 2469 2470 mdss: display-subsystem@ae00000 { 2471 compatible = "qcom,sm8350-mdss"; 2472 reg = <0 0x0ae00000 0 0x1000>; 2473 reg-names = "mdss"; 2474 2475 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 2476 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 2477 interconnect-names = "mdp0-mem", "mdp1-mem"; 2478 2479 power-domains = <&dispcc MDSS_GDSC>; 2480 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2481 2482 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2483 <&gcc GCC_DISP_HF_AXI_CLK>, 2484 <&gcc GCC_DISP_SF_AXI_CLK>, 2485 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2486 clock-names = "iface", "bus", "nrt_bus", "core"; 2487 2488 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2489 interrupt-controller; 2490 #interrupt-cells = <1>; 2491 2492 iommus = <&apps_smmu 0x820 0x402>; 2493 2494 status = "disabled"; 2495 2496 #address-cells = <2>; 2497 #size-cells = <2>; 2498 ranges; 2499 2500 mdss_mdp: display-controller@ae01000 { 2501 compatible = "qcom,sm8350-dpu"; 2502 reg = <0 0x0ae01000 0 0x8f000>, 2503 <0 0x0aeb0000 0 0x2008>; 2504 reg-names = "mdp", "vbif"; 2505 2506 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2507 <&gcc GCC_DISP_SF_AXI_CLK>, 2508 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2509 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2510 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2511 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2512 clock-names = "bus", 2513 "nrt_bus", 2514 "iface", 2515 "lut", 2516 "core", 2517 "vsync"; 2518 2519 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2520 assigned-clock-rates = <19200000>; 2521 2522 operating-points-v2 = <&dpu_opp_table>; 2523 power-domains = <&rpmhpd RPMHPD_MMCX>; 2524 2525 interrupt-parent = <&mdss>; 2526 interrupts = <0>; 2527 2528 dpu_opp_table: opp-table { 2529 compatible = "operating-points-v2"; 2530 2531 /* TODO: opp-200000000 should work with 2532 * &rpmhpd_opp_low_svs, but one some of 2533 * sm8350_hdk boards reboot using this 2534 * opp. 2535 */ 2536 opp-200000000 { 2537 opp-hz = /bits/ 64 <200000000>; 2538 required-opps = <&rpmhpd_opp_svs>; 2539 }; 2540 2541 opp-300000000 { 2542 opp-hz = /bits/ 64 <300000000>; 2543 required-opps = <&rpmhpd_opp_svs>; 2544 }; 2545 2546 opp-345000000 { 2547 opp-hz = /bits/ 64 <345000000>; 2548 required-opps = <&rpmhpd_opp_svs_l1>; 2549 }; 2550 2551 opp-460000000 { 2552 opp-hz = /bits/ 64 <460000000>; 2553 required-opps = <&rpmhpd_opp_nom>; 2554 }; 2555 }; 2556 2557 ports { 2558 #address-cells = <1>; 2559 #size-cells = <0>; 2560 2561 port@0 { 2562 reg = <0>; 2563 dpu_intf1_out: endpoint { 2564 remote-endpoint = <&mdss_dsi0_in>; 2565 }; 2566 }; 2567 2568 port@1 { 2569 reg = <1>; 2570 dpu_intf2_out: endpoint { 2571 remote-endpoint = <&mdss_dsi1_in>; 2572 }; 2573 }; 2574 2575 port@2 { 2576 reg = <2>; 2577 dpu_intf0_out: endpoint { 2578 remote-endpoint = <&mdss_dp_in>; 2579 }; 2580 }; 2581 }; 2582 }; 2583 2584 mdss_dp: displayport-controller@ae90000 { 2585 compatible = "qcom,sm8350-dp"; 2586 reg = <0 0xae90000 0 0x200>, 2587 <0 0xae90200 0 0x200>, 2588 <0 0xae90400 0 0x600>, 2589 <0 0xae91000 0 0x400>, 2590 <0 0xae91400 0 0x400>; 2591 interrupt-parent = <&mdss>; 2592 interrupts = <12>; 2593 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2594 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 2595 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 2596 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 2597 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 2598 clock-names = "core_iface", 2599 "core_aux", 2600 "ctrl_link", 2601 "ctrl_link_iface", 2602 "stream_pixel"; 2603 2604 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 2605 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 2606 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2607 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2608 2609 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 2610 phy-names = "dp"; 2611 2612 #sound-dai-cells = <0>; 2613 2614 operating-points-v2 = <&dp_opp_table>; 2615 power-domains = <&rpmhpd RPMHPD_MMCX>; 2616 2617 status = "disabled"; 2618 2619 ports { 2620 #address-cells = <1>; 2621 #size-cells = <0>; 2622 2623 port@0 { 2624 reg = <0>; 2625 mdss_dp_in: endpoint { 2626 remote-endpoint = <&dpu_intf0_out>; 2627 }; 2628 }; 2629 }; 2630 2631 dp_opp_table: opp-table { 2632 compatible = "operating-points-v2"; 2633 2634 opp-160000000 { 2635 opp-hz = /bits/ 64 <160000000>; 2636 required-opps = <&rpmhpd_opp_low_svs>; 2637 }; 2638 2639 opp-270000000 { 2640 opp-hz = /bits/ 64 <270000000>; 2641 required-opps = <&rpmhpd_opp_svs>; 2642 }; 2643 2644 opp-540000000 { 2645 opp-hz = /bits/ 64 <540000000>; 2646 required-opps = <&rpmhpd_opp_svs_l1>; 2647 }; 2648 2649 opp-810000000 { 2650 opp-hz = /bits/ 64 <810000000>; 2651 required-opps = <&rpmhpd_opp_nom>; 2652 }; 2653 }; 2654 }; 2655 2656 mdss_dsi0: dsi@ae94000 { 2657 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2658 reg = <0 0x0ae94000 0 0x400>; 2659 reg-names = "dsi_ctrl"; 2660 2661 interrupt-parent = <&mdss>; 2662 interrupts = <4>; 2663 2664 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2665 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2666 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2667 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2668 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2669 <&gcc GCC_DISP_HF_AXI_CLK>; 2670 clock-names = "byte", 2671 "byte_intf", 2672 "pixel", 2673 "core", 2674 "iface", 2675 "bus"; 2676 2677 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2678 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2679 assigned-clock-parents = <&mdss_dsi0_phy 0>, 2680 <&mdss_dsi0_phy 1>; 2681 2682 operating-points-v2 = <&dsi0_opp_table>; 2683 power-domains = <&rpmhpd RPMHPD_MMCX>; 2684 2685 phys = <&mdss_dsi0_phy>; 2686 2687 #address-cells = <1>; 2688 #size-cells = <0>; 2689 2690 status = "disabled"; 2691 2692 dsi0_opp_table: opp-table { 2693 compatible = "operating-points-v2"; 2694 2695 /* TODO: opp-187500000 should work with 2696 * &rpmhpd_opp_low_svs, but one some of 2697 * sm8350_hdk boards reboot using this 2698 * opp. 2699 */ 2700 opp-187500000 { 2701 opp-hz = /bits/ 64 <187500000>; 2702 required-opps = <&rpmhpd_opp_svs>; 2703 }; 2704 2705 opp-300000000 { 2706 opp-hz = /bits/ 64 <300000000>; 2707 required-opps = <&rpmhpd_opp_svs>; 2708 }; 2709 2710 opp-358000000 { 2711 opp-hz = /bits/ 64 <358000000>; 2712 required-opps = <&rpmhpd_opp_svs_l1>; 2713 }; 2714 }; 2715 2716 ports { 2717 #address-cells = <1>; 2718 #size-cells = <0>; 2719 2720 port@0 { 2721 reg = <0>; 2722 mdss_dsi0_in: endpoint { 2723 remote-endpoint = <&dpu_intf1_out>; 2724 }; 2725 }; 2726 2727 port@1 { 2728 reg = <1>; 2729 mdss_dsi0_out: endpoint { 2730 }; 2731 }; 2732 }; 2733 }; 2734 2735 mdss_dsi0_phy: phy@ae94400 { 2736 compatible = "qcom,sm8350-dsi-phy-5nm"; 2737 reg = <0 0x0ae94400 0 0x200>, 2738 <0 0x0ae94600 0 0x280>, 2739 <0 0x0ae94900 0 0x27c>; 2740 reg-names = "dsi_phy", 2741 "dsi_phy_lane", 2742 "dsi_pll"; 2743 2744 #clock-cells = <1>; 2745 #phy-cells = <0>; 2746 2747 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2748 <&rpmhcc RPMH_CXO_CLK>; 2749 clock-names = "iface", "ref"; 2750 2751 status = "disabled"; 2752 }; 2753 2754 mdss_dsi1: dsi@ae96000 { 2755 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2756 reg = <0 0x0ae96000 0 0x400>; 2757 reg-names = "dsi_ctrl"; 2758 2759 interrupt-parent = <&mdss>; 2760 interrupts = <5>; 2761 2762 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2763 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2764 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2765 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2766 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2767 <&gcc GCC_DISP_HF_AXI_CLK>; 2768 clock-names = "byte", 2769 "byte_intf", 2770 "pixel", 2771 "core", 2772 "iface", 2773 "bus"; 2774 2775 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 2776 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2777 assigned-clock-parents = <&mdss_dsi1_phy 0>, 2778 <&mdss_dsi1_phy 1>; 2779 2780 operating-points-v2 = <&dsi1_opp_table>; 2781 power-domains = <&rpmhpd RPMHPD_MMCX>; 2782 2783 phys = <&mdss_dsi1_phy>; 2784 2785 #address-cells = <1>; 2786 #size-cells = <0>; 2787 2788 status = "disabled"; 2789 2790 dsi1_opp_table: opp-table { 2791 compatible = "operating-points-v2"; 2792 2793 /* TODO: opp-187500000 should work with 2794 * &rpmhpd_opp_low_svs, but one some of 2795 * sm8350_hdk boards reboot using this 2796 * opp. 2797 */ 2798 opp-187500000 { 2799 opp-hz = /bits/ 64 <187500000>; 2800 required-opps = <&rpmhpd_opp_svs>; 2801 }; 2802 2803 opp-300000000 { 2804 opp-hz = /bits/ 64 <300000000>; 2805 required-opps = <&rpmhpd_opp_svs>; 2806 }; 2807 2808 opp-358000000 { 2809 opp-hz = /bits/ 64 <358000000>; 2810 required-opps = <&rpmhpd_opp_svs_l1>; 2811 }; 2812 }; 2813 2814 ports { 2815 #address-cells = <1>; 2816 #size-cells = <0>; 2817 2818 port@0 { 2819 reg = <0>; 2820 mdss_dsi1_in: endpoint { 2821 remote-endpoint = <&dpu_intf2_out>; 2822 }; 2823 }; 2824 2825 port@1 { 2826 reg = <1>; 2827 mdss_dsi1_out: endpoint { 2828 }; 2829 }; 2830 }; 2831 }; 2832 2833 mdss_dsi1_phy: phy@ae96400 { 2834 compatible = "qcom,sm8350-dsi-phy-5nm"; 2835 reg = <0 0x0ae96400 0 0x200>, 2836 <0 0x0ae96600 0 0x280>, 2837 <0 0x0ae96900 0 0x27c>; 2838 reg-names = "dsi_phy", 2839 "dsi_phy_lane", 2840 "dsi_pll"; 2841 2842 #clock-cells = <1>; 2843 #phy-cells = <0>; 2844 2845 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2846 <&rpmhcc RPMH_CXO_CLK>; 2847 clock-names = "iface", "ref"; 2848 2849 status = "disabled"; 2850 }; 2851 }; 2852 2853 dispcc: clock-controller@af00000 { 2854 compatible = "qcom,sm8350-dispcc"; 2855 reg = <0 0x0af00000 0 0x10000>; 2856 clocks = <&rpmhcc RPMH_CXO_CLK>, 2857 <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, 2858 <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, 2859 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2860 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2861 clock-names = "bi_tcxo", 2862 "dsi0_phy_pll_out_byteclk", 2863 "dsi0_phy_pll_out_dsiclk", 2864 "dsi1_phy_pll_out_byteclk", 2865 "dsi1_phy_pll_out_dsiclk", 2866 "dp_phy_pll_link_clk", 2867 "dp_phy_pll_vco_div_clk"; 2868 #clock-cells = <1>; 2869 #reset-cells = <1>; 2870 #power-domain-cells = <1>; 2871 2872 power-domains = <&rpmhpd RPMHPD_MMCX>; 2873 }; 2874 2875 pdc: interrupt-controller@b220000 { 2876 compatible = "qcom,sm8350-pdc", "qcom,pdc"; 2877 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 2878 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, 2879 <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, 2880 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, 2881 <156 716 12>; 2882 #interrupt-cells = <2>; 2883 interrupt-parent = <&intc>; 2884 interrupt-controller; 2885 }; 2886 2887 tsens0: thermal-sensor@c263000 { 2888 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 2889 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2890 <0 0x0c222000 0 0x8>; /* SROT */ 2891 #qcom,sensors = <15>; 2892 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 2893 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 2894 interrupt-names = "uplow", "critical"; 2895 #thermal-sensor-cells = <1>; 2896 }; 2897 2898 tsens1: thermal-sensor@c265000 { 2899 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 2900 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2901 <0 0x0c223000 0 0x8>; /* SROT */ 2902 #qcom,sensors = <14>; 2903 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 2904 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 2905 interrupt-names = "uplow", "critical"; 2906 #thermal-sensor-cells = <1>; 2907 }; 2908 2909 aoss_qmp: power-management@c300000 { 2910 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; 2911 reg = <0 0x0c300000 0 0x400>; 2912 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2913 IRQ_TYPE_EDGE_RISING>; 2914 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2915 2916 #clock-cells = <0>; 2917 }; 2918 2919 sram@c3f0000 { 2920 compatible = "qcom,rpmh-stats"; 2921 reg = <0 0x0c3f0000 0 0x400>; 2922 }; 2923 2924 spmi_bus: spmi@c440000 { 2925 compatible = "qcom,spmi-pmic-arb"; 2926 reg = <0x0 0x0c440000 0x0 0x1100>, 2927 <0x0 0x0c600000 0x0 0x2000000>, 2928 <0x0 0x0e600000 0x0 0x100000>, 2929 <0x0 0x0e700000 0x0 0xa0000>, 2930 <0x0 0x0c40a000 0x0 0x26000>; 2931 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2932 interrupt-names = "periph_irq"; 2933 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2934 qcom,ee = <0>; 2935 qcom,channel = <0>; 2936 #address-cells = <2>; 2937 #size-cells = <0>; 2938 interrupt-controller; 2939 #interrupt-cells = <4>; 2940 }; 2941 2942 tlmm: pinctrl@f100000 { 2943 compatible = "qcom,sm8350-tlmm"; 2944 reg = <0 0x0f100000 0 0x300000>; 2945 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2946 gpio-controller; 2947 #gpio-cells = <2>; 2948 interrupt-controller; 2949 #interrupt-cells = <2>; 2950 gpio-ranges = <&tlmm 0 0 204>; 2951 wakeup-parent = <&pdc>; 2952 2953 sdc2_default_state: sdc2-default-state { 2954 clk-pins { 2955 pins = "sdc2_clk"; 2956 drive-strength = <16>; 2957 bias-disable; 2958 }; 2959 2960 cmd-pins { 2961 pins = "sdc2_cmd"; 2962 drive-strength = <16>; 2963 bias-pull-up; 2964 }; 2965 2966 data-pins { 2967 pins = "sdc2_data"; 2968 drive-strength = <16>; 2969 bias-pull-up; 2970 }; 2971 }; 2972 2973 sdc2_sleep_state: sdc2-sleep-state { 2974 clk-pins { 2975 pins = "sdc2_clk"; 2976 drive-strength = <2>; 2977 bias-disable; 2978 }; 2979 2980 cmd-pins { 2981 pins = "sdc2_cmd"; 2982 drive-strength = <2>; 2983 bias-pull-up; 2984 }; 2985 2986 data-pins { 2987 pins = "sdc2_data"; 2988 drive-strength = <2>; 2989 bias-pull-up; 2990 }; 2991 }; 2992 2993 qup_uart3_default_state: qup-uart3-default-state { 2994 rx-pins { 2995 pins = "gpio18"; 2996 function = "qup3"; 2997 }; 2998 tx-pins { 2999 pins = "gpio19"; 3000 function = "qup3"; 3001 }; 3002 }; 3003 3004 qup_uart6_default: qup-uart6-default-state { 3005 pins = "gpio30", "gpio31"; 3006 function = "qup6"; 3007 drive-strength = <2>; 3008 bias-disable; 3009 }; 3010 3011 qup_uart18_default: qup-uart18-default-state { 3012 pins = "gpio68", "gpio69"; 3013 function = "qup18"; 3014 drive-strength = <2>; 3015 bias-disable; 3016 }; 3017 3018 qup_i2c0_default: qup-i2c0-default-state { 3019 pins = "gpio4", "gpio5"; 3020 function = "qup0"; 3021 drive-strength = <2>; 3022 bias-pull-up; 3023 }; 3024 3025 qup_i2c1_default: qup-i2c1-default-state { 3026 pins = "gpio8", "gpio9"; 3027 function = "qup1"; 3028 drive-strength = <2>; 3029 bias-pull-up; 3030 }; 3031 3032 qup_i2c2_default: qup-i2c2-default-state { 3033 pins = "gpio12", "gpio13"; 3034 function = "qup2"; 3035 drive-strength = <2>; 3036 bias-pull-up; 3037 }; 3038 3039 qup_i2c4_default: qup-i2c4-default-state { 3040 pins = "gpio20", "gpio21"; 3041 function = "qup4"; 3042 drive-strength = <2>; 3043 bias-pull-up; 3044 }; 3045 3046 qup_i2c5_default: qup-i2c5-default-state { 3047 pins = "gpio24", "gpio25"; 3048 function = "qup5"; 3049 drive-strength = <2>; 3050 bias-pull-up; 3051 }; 3052 3053 qup_i2c6_default: qup-i2c6-default-state { 3054 pins = "gpio28", "gpio29"; 3055 function = "qup6"; 3056 drive-strength = <2>; 3057 bias-pull-up; 3058 }; 3059 3060 qup_i2c7_default: qup-i2c7-default-state { 3061 pins = "gpio32", "gpio33"; 3062 function = "qup7"; 3063 drive-strength = <2>; 3064 bias-disable; 3065 }; 3066 3067 qup_i2c8_default: qup-i2c8-default-state { 3068 pins = "gpio36", "gpio37"; 3069 function = "qup8"; 3070 drive-strength = <2>; 3071 bias-pull-up; 3072 }; 3073 3074 qup_i2c9_default: qup-i2c9-default-state { 3075 pins = "gpio40", "gpio41"; 3076 function = "qup9"; 3077 drive-strength = <2>; 3078 bias-pull-up; 3079 }; 3080 3081 qup_i2c10_default: qup-i2c10-default-state { 3082 pins = "gpio44", "gpio45"; 3083 function = "qup10"; 3084 drive-strength = <2>; 3085 bias-pull-up; 3086 }; 3087 3088 qup_i2c11_default: qup-i2c11-default-state { 3089 pins = "gpio48", "gpio49"; 3090 function = "qup11"; 3091 drive-strength = <2>; 3092 bias-pull-up; 3093 }; 3094 3095 qup_i2c12_default: qup-i2c12-default-state { 3096 pins = "gpio52", "gpio53"; 3097 function = "qup12"; 3098 drive-strength = <2>; 3099 bias-pull-up; 3100 }; 3101 3102 qup_i2c13_default: qup-i2c13-default-state { 3103 pins = "gpio0", "gpio1"; 3104 function = "qup13"; 3105 drive-strength = <2>; 3106 bias-pull-up; 3107 }; 3108 3109 qup_i2c14_default: qup-i2c14-default-state { 3110 pins = "gpio56", "gpio57"; 3111 function = "qup14"; 3112 drive-strength = <2>; 3113 bias-disable; 3114 }; 3115 3116 qup_i2c15_default: qup-i2c15-default-state { 3117 pins = "gpio60", "gpio61"; 3118 function = "qup15"; 3119 drive-strength = <2>; 3120 bias-disable; 3121 }; 3122 3123 qup_i2c16_default: qup-i2c16-default-state { 3124 pins = "gpio64", "gpio65"; 3125 function = "qup16"; 3126 drive-strength = <2>; 3127 bias-disable; 3128 }; 3129 3130 qup_i2c17_default: qup-i2c17-default-state { 3131 pins = "gpio72", "gpio73"; 3132 function = "qup17"; 3133 drive-strength = <2>; 3134 bias-disable; 3135 }; 3136 3137 qup_i2c19_default: qup-i2c19-default-state { 3138 pins = "gpio76", "gpio77"; 3139 function = "qup19"; 3140 drive-strength = <2>; 3141 bias-disable; 3142 }; 3143 }; 3144 3145 apps_smmu: iommu@15000000 { 3146 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; 3147 reg = <0 0x15000000 0 0x100000>; 3148 #iommu-cells = <2>; 3149 #global-interrupts = <2>; 3150 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 3151 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3152 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3153 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3154 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3155 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3156 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3157 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3158 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3159 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3160 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3161 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3162 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3163 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3164 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3165 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3166 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3167 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3168 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3169 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3170 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3171 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3172 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3173 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3174 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3175 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3176 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3177 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3178 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3179 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3180 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3181 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3182 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3183 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3184 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3185 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3186 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3187 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3188 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3189 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3190 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3191 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3192 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3193 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3194 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3195 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3196 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3197 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3198 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3199 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3200 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3201 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3202 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3203 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3204 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3205 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3206 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3207 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3208 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3209 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3210 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3211 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3212 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3213 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3214 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3215 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3216 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3217 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3218 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3219 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3220 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3221 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3222 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3223 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3224 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3225 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3226 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3227 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3228 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3229 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3230 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3231 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3232 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3233 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3234 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3235 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3236 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3237 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3238 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3239 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3240 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3241 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3242 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3243 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3244 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3245 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3246 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 3247 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 3248 }; 3249 3250 adsp: remoteproc@17300000 { 3251 compatible = "qcom,sm8350-adsp-pas"; 3252 reg = <0 0x17300000 0 0x100>; 3253 3254 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 3255 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 3256 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 3257 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 3258 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 3259 interrupt-names = "wdog", "fatal", "ready", 3260 "handover", "stop-ack"; 3261 3262 clocks = <&rpmhcc RPMH_CXO_CLK>; 3263 clock-names = "xo"; 3264 3265 power-domains = <&rpmhpd RPMHPD_LCX>, 3266 <&rpmhpd RPMHPD_LMX>; 3267 power-domain-names = "lcx", "lmx"; 3268 3269 memory-region = <&pil_adsp_mem>; 3270 3271 qcom,qmp = <&aoss_qmp>; 3272 3273 qcom,smem-states = <&smp2p_adsp_out 0>; 3274 qcom,smem-state-names = "stop"; 3275 3276 status = "disabled"; 3277 3278 glink-edge { 3279 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3280 IPCC_MPROC_SIGNAL_GLINK_QMP 3281 IRQ_TYPE_EDGE_RISING>; 3282 mboxes = <&ipcc IPCC_CLIENT_LPASS 3283 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3284 3285 label = "lpass"; 3286 qcom,remote-pid = <2>; 3287 3288 apr { 3289 compatible = "qcom,apr-v2"; 3290 qcom,glink-channels = "apr_audio_svc"; 3291 qcom,domain = <APR_DOMAIN_ADSP>; 3292 #address-cells = <1>; 3293 #size-cells = <0>; 3294 3295 service@3 { 3296 reg = <APR_SVC_ADSP_CORE>; 3297 compatible = "qcom,q6core"; 3298 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3299 }; 3300 3301 q6afe: service@4 { 3302 compatible = "qcom,q6afe"; 3303 reg = <APR_SVC_AFE>; 3304 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3305 3306 q6afedai: dais { 3307 compatible = "qcom,q6afe-dais"; 3308 #address-cells = <1>; 3309 #size-cells = <0>; 3310 #sound-dai-cells = <1>; 3311 }; 3312 3313 q6afecc: clock-controller { 3314 compatible = "qcom,q6afe-clocks"; 3315 #clock-cells = <2>; 3316 }; 3317 }; 3318 3319 q6asm: service@7 { 3320 compatible = "qcom,q6asm"; 3321 reg = <APR_SVC_ASM>; 3322 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3323 3324 q6asmdai: dais { 3325 compatible = "qcom,q6asm-dais"; 3326 #address-cells = <1>; 3327 #size-cells = <0>; 3328 #sound-dai-cells = <1>; 3329 iommus = <&apps_smmu 0x1801 0x0>; 3330 3331 dai@0 { 3332 reg = <0>; 3333 }; 3334 3335 dai@1 { 3336 reg = <1>; 3337 }; 3338 3339 dai@2 { 3340 reg = <2>; 3341 }; 3342 }; 3343 }; 3344 3345 q6adm: service@8 { 3346 compatible = "qcom,q6adm"; 3347 reg = <APR_SVC_ADM>; 3348 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3349 3350 q6routing: routing { 3351 compatible = "qcom,q6adm-routing"; 3352 #sound-dai-cells = <0>; 3353 }; 3354 }; 3355 }; 3356 3357 fastrpc { 3358 compatible = "qcom,fastrpc"; 3359 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3360 label = "adsp"; 3361 qcom,non-secure-domain; 3362 #address-cells = <1>; 3363 #size-cells = <0>; 3364 3365 compute-cb@3 { 3366 compatible = "qcom,fastrpc-compute-cb"; 3367 reg = <3>; 3368 iommus = <&apps_smmu 0x1803 0x0>; 3369 }; 3370 3371 compute-cb@4 { 3372 compatible = "qcom,fastrpc-compute-cb"; 3373 reg = <4>; 3374 iommus = <&apps_smmu 0x1804 0x0>; 3375 }; 3376 3377 compute-cb@5 { 3378 compatible = "qcom,fastrpc-compute-cb"; 3379 reg = <5>; 3380 iommus = <&apps_smmu 0x1805 0x0>; 3381 }; 3382 }; 3383 }; 3384 }; 3385 3386 intc: interrupt-controller@17a00000 { 3387 compatible = "arm,gic-v3"; 3388 #interrupt-cells = <3>; 3389 interrupt-controller; 3390 #redistributor-regions = <1>; 3391 redistributor-stride = <0 0x20000>; 3392 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3393 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3394 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3395 }; 3396 3397 timer@17c20000 { 3398 compatible = "arm,armv7-timer-mem"; 3399 #address-cells = <1>; 3400 #size-cells = <1>; 3401 ranges = <0 0 0 0x20000000>; 3402 reg = <0x0 0x17c20000 0x0 0x1000>; 3403 clock-frequency = <19200000>; 3404 3405 frame@17c21000 { 3406 frame-number = <0>; 3407 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3408 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3409 reg = <0x17c21000 0x1000>, 3410 <0x17c22000 0x1000>; 3411 }; 3412 3413 frame@17c23000 { 3414 frame-number = <1>; 3415 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3416 reg = <0x17c23000 0x1000>; 3417 status = "disabled"; 3418 }; 3419 3420 frame@17c25000 { 3421 frame-number = <2>; 3422 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3423 reg = <0x17c25000 0x1000>; 3424 status = "disabled"; 3425 }; 3426 3427 frame@17c27000 { 3428 frame-number = <3>; 3429 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3430 reg = <0x17c27000 0x1000>; 3431 status = "disabled"; 3432 }; 3433 3434 frame@17c29000 { 3435 frame-number = <4>; 3436 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3437 reg = <0x17c29000 0x1000>; 3438 status = "disabled"; 3439 }; 3440 3441 frame@17c2b000 { 3442 frame-number = <5>; 3443 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3444 reg = <0x17c2b000 0x1000>; 3445 status = "disabled"; 3446 }; 3447 3448 frame@17c2d000 { 3449 frame-number = <6>; 3450 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3451 reg = <0x17c2d000 0x1000>; 3452 status = "disabled"; 3453 }; 3454 }; 3455 3456 apps_rsc: rsc@18200000 { 3457 label = "apps_rsc"; 3458 compatible = "qcom,rpmh-rsc"; 3459 reg = <0x0 0x18200000 0x0 0x10000>, 3460 <0x0 0x18210000 0x0 0x10000>, 3461 <0x0 0x18220000 0x0 0x10000>; 3462 reg-names = "drv-0", "drv-1", "drv-2"; 3463 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3464 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3465 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3466 qcom,tcs-offset = <0xd00>; 3467 qcom,drv-id = <2>; 3468 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 3469 <WAKE_TCS 3>, <CONTROL_TCS 0>; 3470 power-domains = <&CLUSTER_PD>; 3471 3472 rpmhcc: clock-controller { 3473 compatible = "qcom,sm8350-rpmh-clk"; 3474 #clock-cells = <1>; 3475 clock-names = "xo"; 3476 clocks = <&xo_board>; 3477 }; 3478 3479 rpmhpd: power-controller { 3480 compatible = "qcom,sm8350-rpmhpd"; 3481 #power-domain-cells = <1>; 3482 operating-points-v2 = <&rpmhpd_opp_table>; 3483 3484 rpmhpd_opp_table: opp-table { 3485 compatible = "operating-points-v2"; 3486 3487 rpmhpd_opp_ret: opp1 { 3488 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3489 }; 3490 3491 rpmhpd_opp_min_svs: opp2 { 3492 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3493 }; 3494 3495 rpmhpd_opp_low_svs: opp3 { 3496 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3497 }; 3498 3499 rpmhpd_opp_svs: opp4 { 3500 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3501 }; 3502 3503 rpmhpd_opp_svs_l1: opp5 { 3504 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3505 }; 3506 3507 rpmhpd_opp_nom: opp6 { 3508 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3509 }; 3510 3511 rpmhpd_opp_nom_l1: opp7 { 3512 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3513 }; 3514 3515 rpmhpd_opp_nom_l2: opp8 { 3516 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3517 }; 3518 3519 rpmhpd_opp_turbo: opp9 { 3520 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3521 }; 3522 3523 rpmhpd_opp_turbo_l1: opp10 { 3524 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3525 }; 3526 }; 3527 }; 3528 3529 apps_bcm_voter: bcm-voter { 3530 compatible = "qcom,bcm-voter"; 3531 }; 3532 }; 3533 3534 cpufreq_hw: cpufreq@18591000 { 3535 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss"; 3536 reg = <0 0x18591000 0 0x1000>, 3537 <0 0x18592000 0 0x1000>, 3538 <0 0x18593000 0 0x1000>; 3539 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3540 3541 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 3542 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3543 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 3544 interrupt-names = "dcvsh-irq-0", 3545 "dcvsh-irq-1", 3546 "dcvsh-irq-2"; 3547 3548 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3549 clock-names = "xo", "alternate"; 3550 3551 #freq-domain-cells = <1>; 3552 #clock-cells = <1>; 3553 }; 3554 3555 cdsp: remoteproc@98900000 { 3556 compatible = "qcom,sm8350-cdsp-pas"; 3557 reg = <0 0x98900000 0 0x1400000>; 3558 3559 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3560 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3561 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3562 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3563 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3564 interrupt-names = "wdog", "fatal", "ready", 3565 "handover", "stop-ack"; 3566 3567 clocks = <&rpmhcc RPMH_CXO_CLK>; 3568 clock-names = "xo"; 3569 3570 power-domains = <&rpmhpd RPMHPD_CX>, 3571 <&rpmhpd RPMHPD_MXC>; 3572 power-domain-names = "cx", "mxc"; 3573 3574 interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 3575 3576 memory-region = <&pil_cdsp_mem>; 3577 3578 qcom,qmp = <&aoss_qmp>; 3579 3580 qcom,smem-states = <&smp2p_cdsp_out 0>; 3581 qcom,smem-state-names = "stop"; 3582 3583 status = "disabled"; 3584 3585 glink-edge { 3586 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3587 IPCC_MPROC_SIGNAL_GLINK_QMP 3588 IRQ_TYPE_EDGE_RISING>; 3589 mboxes = <&ipcc IPCC_CLIENT_CDSP 3590 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3591 3592 label = "cdsp"; 3593 qcom,remote-pid = <5>; 3594 3595 fastrpc { 3596 compatible = "qcom,fastrpc"; 3597 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3598 label = "cdsp"; 3599 qcom,non-secure-domain; 3600 #address-cells = <1>; 3601 #size-cells = <0>; 3602 3603 compute-cb@1 { 3604 compatible = "qcom,fastrpc-compute-cb"; 3605 reg = <1>; 3606 iommus = <&apps_smmu 0x2161 0x0400>, 3607 <&apps_smmu 0x1181 0x0420>; 3608 }; 3609 3610 compute-cb@2 { 3611 compatible = "qcom,fastrpc-compute-cb"; 3612 reg = <2>; 3613 iommus = <&apps_smmu 0x2162 0x0400>, 3614 <&apps_smmu 0x1182 0x0420>; 3615 }; 3616 3617 compute-cb@3 { 3618 compatible = "qcom,fastrpc-compute-cb"; 3619 reg = <3>; 3620 iommus = <&apps_smmu 0x2163 0x0400>, 3621 <&apps_smmu 0x1183 0x0420>; 3622 }; 3623 3624 compute-cb@4 { 3625 compatible = "qcom,fastrpc-compute-cb"; 3626 reg = <4>; 3627 iommus = <&apps_smmu 0x2164 0x0400>, 3628 <&apps_smmu 0x1184 0x0420>; 3629 }; 3630 3631 compute-cb@5 { 3632 compatible = "qcom,fastrpc-compute-cb"; 3633 reg = <5>; 3634 iommus = <&apps_smmu 0x2165 0x0400>, 3635 <&apps_smmu 0x1185 0x0420>; 3636 }; 3637 3638 compute-cb@6 { 3639 compatible = "qcom,fastrpc-compute-cb"; 3640 reg = <6>; 3641 iommus = <&apps_smmu 0x2166 0x0400>, 3642 <&apps_smmu 0x1186 0x0420>; 3643 }; 3644 3645 compute-cb@7 { 3646 compatible = "qcom,fastrpc-compute-cb"; 3647 reg = <7>; 3648 iommus = <&apps_smmu 0x2167 0x0400>, 3649 <&apps_smmu 0x1187 0x0420>; 3650 }; 3651 3652 compute-cb@8 { 3653 compatible = "qcom,fastrpc-compute-cb"; 3654 reg = <8>; 3655 iommus = <&apps_smmu 0x2168 0x0400>, 3656 <&apps_smmu 0x1188 0x0420>; 3657 }; 3658 3659 /* note: secure cb9 in downstream */ 3660 }; 3661 }; 3662 }; 3663 }; 3664 3665 thermal_zones: thermal-zones { 3666 cpu0-thermal { 3667 polling-delay-passive = <250>; 3668 polling-delay = <1000>; 3669 3670 thermal-sensors = <&tsens0 1>; 3671 3672 trips { 3673 cpu0_alert0: trip-point0 { 3674 temperature = <90000>; 3675 hysteresis = <2000>; 3676 type = "passive"; 3677 }; 3678 3679 cpu0_alert1: trip-point1 { 3680 temperature = <95000>; 3681 hysteresis = <2000>; 3682 type = "passive"; 3683 }; 3684 3685 cpu0_crit: cpu-crit { 3686 temperature = <110000>; 3687 hysteresis = <1000>; 3688 type = "critical"; 3689 }; 3690 }; 3691 3692 cooling-maps { 3693 map0 { 3694 trip = <&cpu0_alert0>; 3695 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3696 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3697 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3698 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3699 }; 3700 map1 { 3701 trip = <&cpu0_alert1>; 3702 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3703 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3704 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3705 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3706 }; 3707 }; 3708 }; 3709 3710 cpu1-thermal { 3711 polling-delay-passive = <250>; 3712 polling-delay = <1000>; 3713 3714 thermal-sensors = <&tsens0 2>; 3715 3716 trips { 3717 cpu1_alert0: trip-point0 { 3718 temperature = <90000>; 3719 hysteresis = <2000>; 3720 type = "passive"; 3721 }; 3722 3723 cpu1_alert1: trip-point1 { 3724 temperature = <95000>; 3725 hysteresis = <2000>; 3726 type = "passive"; 3727 }; 3728 3729 cpu1_crit: cpu-crit { 3730 temperature = <110000>; 3731 hysteresis = <1000>; 3732 type = "critical"; 3733 }; 3734 }; 3735 3736 cooling-maps { 3737 map0 { 3738 trip = <&cpu1_alert0>; 3739 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3740 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3741 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3742 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3743 }; 3744 map1 { 3745 trip = <&cpu1_alert1>; 3746 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3747 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3748 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3749 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3750 }; 3751 }; 3752 }; 3753 3754 cpu2-thermal { 3755 polling-delay-passive = <250>; 3756 polling-delay = <1000>; 3757 3758 thermal-sensors = <&tsens0 3>; 3759 3760 trips { 3761 cpu2_alert0: trip-point0 { 3762 temperature = <90000>; 3763 hysteresis = <2000>; 3764 type = "passive"; 3765 }; 3766 3767 cpu2_alert1: trip-point1 { 3768 temperature = <95000>; 3769 hysteresis = <2000>; 3770 type = "passive"; 3771 }; 3772 3773 cpu2_crit: cpu-crit { 3774 temperature = <110000>; 3775 hysteresis = <1000>; 3776 type = "critical"; 3777 }; 3778 }; 3779 3780 cooling-maps { 3781 map0 { 3782 trip = <&cpu2_alert0>; 3783 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3784 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3785 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3786 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3787 }; 3788 map1 { 3789 trip = <&cpu2_alert1>; 3790 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3791 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3792 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3793 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3794 }; 3795 }; 3796 }; 3797 3798 cpu3-thermal { 3799 polling-delay-passive = <250>; 3800 polling-delay = <1000>; 3801 3802 thermal-sensors = <&tsens0 4>; 3803 3804 trips { 3805 cpu3_alert0: trip-point0 { 3806 temperature = <90000>; 3807 hysteresis = <2000>; 3808 type = "passive"; 3809 }; 3810 3811 cpu3_alert1: trip-point1 { 3812 temperature = <95000>; 3813 hysteresis = <2000>; 3814 type = "passive"; 3815 }; 3816 3817 cpu3_crit: cpu-crit { 3818 temperature = <110000>; 3819 hysteresis = <1000>; 3820 type = "critical"; 3821 }; 3822 }; 3823 3824 cooling-maps { 3825 map0 { 3826 trip = <&cpu3_alert0>; 3827 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3828 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3829 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3830 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3831 }; 3832 map1 { 3833 trip = <&cpu3_alert1>; 3834 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3835 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3836 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3837 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3838 }; 3839 }; 3840 }; 3841 3842 cpu4-top-thermal { 3843 polling-delay-passive = <250>; 3844 polling-delay = <1000>; 3845 3846 thermal-sensors = <&tsens0 7>; 3847 3848 trips { 3849 cpu4_top_alert0: trip-point0 { 3850 temperature = <90000>; 3851 hysteresis = <2000>; 3852 type = "passive"; 3853 }; 3854 3855 cpu4_top_alert1: trip-point1 { 3856 temperature = <95000>; 3857 hysteresis = <2000>; 3858 type = "passive"; 3859 }; 3860 3861 cpu4_top_crit: cpu-crit { 3862 temperature = <110000>; 3863 hysteresis = <1000>; 3864 type = "critical"; 3865 }; 3866 }; 3867 3868 cooling-maps { 3869 map0 { 3870 trip = <&cpu4_top_alert0>; 3871 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3872 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3873 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3874 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3875 }; 3876 map1 { 3877 trip = <&cpu4_top_alert1>; 3878 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3879 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3880 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3881 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3882 }; 3883 }; 3884 }; 3885 3886 cpu5-top-thermal { 3887 polling-delay-passive = <250>; 3888 polling-delay = <1000>; 3889 3890 thermal-sensors = <&tsens0 8>; 3891 3892 trips { 3893 cpu5_top_alert0: trip-point0 { 3894 temperature = <90000>; 3895 hysteresis = <2000>; 3896 type = "passive"; 3897 }; 3898 3899 cpu5_top_alert1: trip-point1 { 3900 temperature = <95000>; 3901 hysteresis = <2000>; 3902 type = "passive"; 3903 }; 3904 3905 cpu5_top_crit: cpu-crit { 3906 temperature = <110000>; 3907 hysteresis = <1000>; 3908 type = "critical"; 3909 }; 3910 }; 3911 3912 cooling-maps { 3913 map0 { 3914 trip = <&cpu5_top_alert0>; 3915 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3916 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3917 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3918 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3919 }; 3920 map1 { 3921 trip = <&cpu5_top_alert1>; 3922 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3923 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3924 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3925 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3926 }; 3927 }; 3928 }; 3929 3930 cpu6-top-thermal { 3931 polling-delay-passive = <250>; 3932 polling-delay = <1000>; 3933 3934 thermal-sensors = <&tsens0 9>; 3935 3936 trips { 3937 cpu6_top_alert0: trip-point0 { 3938 temperature = <90000>; 3939 hysteresis = <2000>; 3940 type = "passive"; 3941 }; 3942 3943 cpu6_top_alert1: trip-point1 { 3944 temperature = <95000>; 3945 hysteresis = <2000>; 3946 type = "passive"; 3947 }; 3948 3949 cpu6_top_crit: cpu-crit { 3950 temperature = <110000>; 3951 hysteresis = <1000>; 3952 type = "critical"; 3953 }; 3954 }; 3955 3956 cooling-maps { 3957 map0 { 3958 trip = <&cpu6_top_alert0>; 3959 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3960 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3961 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3962 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3963 }; 3964 map1 { 3965 trip = <&cpu6_top_alert1>; 3966 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3967 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3968 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3969 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3970 }; 3971 }; 3972 }; 3973 3974 cpu7-top-thermal { 3975 polling-delay-passive = <250>; 3976 polling-delay = <1000>; 3977 3978 thermal-sensors = <&tsens0 10>; 3979 3980 trips { 3981 cpu7_top_alert0: trip-point0 { 3982 temperature = <90000>; 3983 hysteresis = <2000>; 3984 type = "passive"; 3985 }; 3986 3987 cpu7_top_alert1: trip-point1 { 3988 temperature = <95000>; 3989 hysteresis = <2000>; 3990 type = "passive"; 3991 }; 3992 3993 cpu7_top_crit: cpu-crit { 3994 temperature = <110000>; 3995 hysteresis = <1000>; 3996 type = "critical"; 3997 }; 3998 }; 3999 4000 cooling-maps { 4001 map0 { 4002 trip = <&cpu7_top_alert0>; 4003 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4004 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4005 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4006 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4007 }; 4008 map1 { 4009 trip = <&cpu7_top_alert1>; 4010 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4011 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4012 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4013 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4014 }; 4015 }; 4016 }; 4017 4018 cpu4-bottom-thermal { 4019 polling-delay-passive = <250>; 4020 polling-delay = <1000>; 4021 4022 thermal-sensors = <&tsens0 11>; 4023 4024 trips { 4025 cpu4_bottom_alert0: trip-point0 { 4026 temperature = <90000>; 4027 hysteresis = <2000>; 4028 type = "passive"; 4029 }; 4030 4031 cpu4_bottom_alert1: trip-point1 { 4032 temperature = <95000>; 4033 hysteresis = <2000>; 4034 type = "passive"; 4035 }; 4036 4037 cpu4_bottom_crit: cpu-crit { 4038 temperature = <110000>; 4039 hysteresis = <1000>; 4040 type = "critical"; 4041 }; 4042 }; 4043 4044 cooling-maps { 4045 map0 { 4046 trip = <&cpu4_bottom_alert0>; 4047 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4048 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4049 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4050 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4051 }; 4052 map1 { 4053 trip = <&cpu4_bottom_alert1>; 4054 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4055 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4056 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4057 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4058 }; 4059 }; 4060 }; 4061 4062 cpu5-bottom-thermal { 4063 polling-delay-passive = <250>; 4064 polling-delay = <1000>; 4065 4066 thermal-sensors = <&tsens0 12>; 4067 4068 trips { 4069 cpu5_bottom_alert0: trip-point0 { 4070 temperature = <90000>; 4071 hysteresis = <2000>; 4072 type = "passive"; 4073 }; 4074 4075 cpu5_bottom_alert1: trip-point1 { 4076 temperature = <95000>; 4077 hysteresis = <2000>; 4078 type = "passive"; 4079 }; 4080 4081 cpu5_bottom_crit: cpu-crit { 4082 temperature = <110000>; 4083 hysteresis = <1000>; 4084 type = "critical"; 4085 }; 4086 }; 4087 4088 cooling-maps { 4089 map0 { 4090 trip = <&cpu5_bottom_alert0>; 4091 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4092 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4093 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4094 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4095 }; 4096 map1 { 4097 trip = <&cpu5_bottom_alert1>; 4098 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4099 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4100 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4101 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4102 }; 4103 }; 4104 }; 4105 4106 cpu6-bottom-thermal { 4107 polling-delay-passive = <250>; 4108 polling-delay = <1000>; 4109 4110 thermal-sensors = <&tsens0 13>; 4111 4112 trips { 4113 cpu6_bottom_alert0: trip-point0 { 4114 temperature = <90000>; 4115 hysteresis = <2000>; 4116 type = "passive"; 4117 }; 4118 4119 cpu6_bottom_alert1: trip-point1 { 4120 temperature = <95000>; 4121 hysteresis = <2000>; 4122 type = "passive"; 4123 }; 4124 4125 cpu6_bottom_crit: cpu-crit { 4126 temperature = <110000>; 4127 hysteresis = <1000>; 4128 type = "critical"; 4129 }; 4130 }; 4131 4132 cooling-maps { 4133 map0 { 4134 trip = <&cpu6_bottom_alert0>; 4135 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4136 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4137 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4138 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4139 }; 4140 map1 { 4141 trip = <&cpu6_bottom_alert1>; 4142 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4143 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4144 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4145 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4146 }; 4147 }; 4148 }; 4149 4150 cpu7-bottom-thermal { 4151 polling-delay-passive = <250>; 4152 polling-delay = <1000>; 4153 4154 thermal-sensors = <&tsens0 14>; 4155 4156 trips { 4157 cpu7_bottom_alert0: trip-point0 { 4158 temperature = <90000>; 4159 hysteresis = <2000>; 4160 type = "passive"; 4161 }; 4162 4163 cpu7_bottom_alert1: trip-point1 { 4164 temperature = <95000>; 4165 hysteresis = <2000>; 4166 type = "passive"; 4167 }; 4168 4169 cpu7_bottom_crit: cpu-crit { 4170 temperature = <110000>; 4171 hysteresis = <1000>; 4172 type = "critical"; 4173 }; 4174 }; 4175 4176 cooling-maps { 4177 map0 { 4178 trip = <&cpu7_bottom_alert0>; 4179 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4180 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4181 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4182 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4183 }; 4184 map1 { 4185 trip = <&cpu7_bottom_alert1>; 4186 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4187 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4188 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4189 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4190 }; 4191 }; 4192 }; 4193 4194 aoss0-thermal { 4195 polling-delay-passive = <250>; 4196 polling-delay = <1000>; 4197 4198 thermal-sensors = <&tsens0 0>; 4199 4200 trips { 4201 aoss0_alert0: trip-point0 { 4202 temperature = <90000>; 4203 hysteresis = <2000>; 4204 type = "hot"; 4205 }; 4206 }; 4207 }; 4208 4209 cluster0-thermal { 4210 polling-delay-passive = <250>; 4211 polling-delay = <1000>; 4212 4213 thermal-sensors = <&tsens0 5>; 4214 4215 trips { 4216 cluster0_alert0: trip-point0 { 4217 temperature = <90000>; 4218 hysteresis = <2000>; 4219 type = "hot"; 4220 }; 4221 cluster0_crit: cluster0-crit { 4222 temperature = <110000>; 4223 hysteresis = <2000>; 4224 type = "critical"; 4225 }; 4226 }; 4227 }; 4228 4229 cluster1-thermal { 4230 polling-delay-passive = <250>; 4231 polling-delay = <1000>; 4232 4233 thermal-sensors = <&tsens0 6>; 4234 4235 trips { 4236 cluster1_alert0: trip-point0 { 4237 temperature = <90000>; 4238 hysteresis = <2000>; 4239 type = "hot"; 4240 }; 4241 cluster1_crit: cluster1-crit { 4242 temperature = <110000>; 4243 hysteresis = <2000>; 4244 type = "critical"; 4245 }; 4246 }; 4247 }; 4248 4249 aoss1-thermal { 4250 polling-delay-passive = <250>; 4251 polling-delay = <1000>; 4252 4253 thermal-sensors = <&tsens1 0>; 4254 4255 trips { 4256 aoss1_alert0: trip-point0 { 4257 temperature = <90000>; 4258 hysteresis = <2000>; 4259 type = "hot"; 4260 }; 4261 }; 4262 }; 4263 4264 gpu-top-thermal { 4265 polling-delay-passive = <250>; 4266 polling-delay = <1000>; 4267 4268 thermal-sensors = <&tsens1 1>; 4269 4270 cooling-maps { 4271 map0 { 4272 trip = <&gpu_top_alert0>; 4273 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4274 }; 4275 }; 4276 4277 trips { 4278 gpu_top_alert0: trip-point0 { 4279 temperature = <90000>; 4280 hysteresis = <1000>; 4281 type = "hot"; 4282 }; 4283 }; 4284 }; 4285 4286 gpu-bottom-thermal { 4287 polling-delay-passive = <250>; 4288 polling-delay = <1000>; 4289 4290 thermal-sensors = <&tsens1 2>; 4291 4292 cooling-maps { 4293 map0 { 4294 trip = <&gpu_bottom_alert0>; 4295 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4296 }; 4297 }; 4298 4299 trips { 4300 gpu_bottom_alert0: trip-point0 { 4301 temperature = <90000>; 4302 hysteresis = <1000>; 4303 type = "hot"; 4304 }; 4305 }; 4306 }; 4307 4308 nspss1-thermal { 4309 polling-delay-passive = <250>; 4310 polling-delay = <1000>; 4311 4312 thermal-sensors = <&tsens1 3>; 4313 4314 trips { 4315 nspss1_alert0: trip-point0 { 4316 temperature = <90000>; 4317 hysteresis = <1000>; 4318 type = "hot"; 4319 }; 4320 }; 4321 }; 4322 4323 nspss2-thermal { 4324 polling-delay-passive = <250>; 4325 polling-delay = <1000>; 4326 4327 thermal-sensors = <&tsens1 4>; 4328 4329 trips { 4330 nspss2_alert0: trip-point0 { 4331 temperature = <90000>; 4332 hysteresis = <1000>; 4333 type = "hot"; 4334 }; 4335 }; 4336 }; 4337 4338 nspss3-thermal { 4339 polling-delay-passive = <250>; 4340 polling-delay = <1000>; 4341 4342 thermal-sensors = <&tsens1 5>; 4343 4344 trips { 4345 nspss3_alert0: trip-point0 { 4346 temperature = <90000>; 4347 hysteresis = <1000>; 4348 type = "hot"; 4349 }; 4350 }; 4351 }; 4352 4353 video-thermal { 4354 polling-delay-passive = <250>; 4355 polling-delay = <1000>; 4356 4357 thermal-sensors = <&tsens1 6>; 4358 4359 trips { 4360 video_alert0: trip-point0 { 4361 temperature = <90000>; 4362 hysteresis = <2000>; 4363 type = "hot"; 4364 }; 4365 }; 4366 }; 4367 4368 mem-thermal { 4369 polling-delay-passive = <250>; 4370 polling-delay = <1000>; 4371 4372 thermal-sensors = <&tsens1 7>; 4373 4374 trips { 4375 mem_alert0: trip-point0 { 4376 temperature = <90000>; 4377 hysteresis = <2000>; 4378 type = "hot"; 4379 }; 4380 }; 4381 }; 4382 4383 modem1-top-thermal { 4384 polling-delay-passive = <250>; 4385 polling-delay = <1000>; 4386 4387 thermal-sensors = <&tsens1 8>; 4388 4389 trips { 4390 modem1_alert0: trip-point0 { 4391 temperature = <90000>; 4392 hysteresis = <2000>; 4393 type = "hot"; 4394 }; 4395 }; 4396 }; 4397 4398 modem2-top-thermal { 4399 polling-delay-passive = <250>; 4400 polling-delay = <1000>; 4401 4402 thermal-sensors = <&tsens1 9>; 4403 4404 trips { 4405 modem2_alert0: trip-point0 { 4406 temperature = <90000>; 4407 hysteresis = <2000>; 4408 type = "hot"; 4409 }; 4410 }; 4411 }; 4412 4413 modem3-top-thermal { 4414 polling-delay-passive = <250>; 4415 polling-delay = <1000>; 4416 4417 thermal-sensors = <&tsens1 10>; 4418 4419 trips { 4420 modem3_alert0: trip-point0 { 4421 temperature = <90000>; 4422 hysteresis = <2000>; 4423 type = "hot"; 4424 }; 4425 }; 4426 }; 4427 4428 modem4-top-thermal { 4429 polling-delay-passive = <250>; 4430 polling-delay = <1000>; 4431 4432 thermal-sensors = <&tsens1 11>; 4433 4434 trips { 4435 modem4_alert0: trip-point0 { 4436 temperature = <90000>; 4437 hysteresis = <2000>; 4438 type = "hot"; 4439 }; 4440 }; 4441 }; 4442 4443 camera-top-thermal { 4444 polling-delay-passive = <250>; 4445 polling-delay = <1000>; 4446 4447 thermal-sensors = <&tsens1 12>; 4448 4449 trips { 4450 camera1_alert0: trip-point0 { 4451 temperature = <90000>; 4452 hysteresis = <2000>; 4453 type = "hot"; 4454 }; 4455 }; 4456 }; 4457 4458 cam-bottom-thermal { 4459 polling-delay-passive = <250>; 4460 polling-delay = <1000>; 4461 4462 thermal-sensors = <&tsens1 13>; 4463 4464 trips { 4465 camera2_alert0: trip-point0 { 4466 temperature = <90000>; 4467 hysteresis = <2000>; 4468 type = "hot"; 4469 }; 4470 }; 4471 }; 4472 }; 4473 4474 timer { 4475 compatible = "arm,armv8-timer"; 4476 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4477 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4478 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4479 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4480 }; 4481}; 4482