1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 9#include <dt-bindings/clock/qcom,gcc-sm8250.h> 10#include <dt-bindings/clock/qcom,gpucc-sm8250.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interconnect/qcom,osm-l3.h> 15#include <dt-bindings/interconnect/qcom,sm8250.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/phy/phy-qcom-qmp.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/power/qcom,rpmhpd.h> 20#include <dt-bindings/soc/qcom,apr.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/sound/qcom,q6afe.h> 23#include <dt-bindings/thermal/thermal.h> 24#include <dt-bindings/clock/qcom,camcc-sm8250.h> 25#include <dt-bindings/clock/qcom,videocc-sm8250.h> 26 27/ { 28 interrupt-parent = <&intc>; 29 30 #address-cells = <2>; 31 #size-cells = <2>; 32 33 aliases { 34 i2c0 = &i2c0; 35 i2c1 = &i2c1; 36 i2c2 = &i2c2; 37 i2c3 = &i2c3; 38 i2c4 = &i2c4; 39 i2c5 = &i2c5; 40 i2c6 = &i2c6; 41 i2c7 = &i2c7; 42 i2c8 = &i2c8; 43 i2c9 = &i2c9; 44 i2c10 = &i2c10; 45 i2c11 = &i2c11; 46 i2c12 = &i2c12; 47 i2c13 = &i2c13; 48 i2c14 = &i2c14; 49 i2c15 = &i2c15; 50 i2c16 = &i2c16; 51 i2c17 = &i2c17; 52 i2c18 = &i2c18; 53 i2c19 = &i2c19; 54 spi0 = &spi0; 55 spi1 = &spi1; 56 spi2 = &spi2; 57 spi3 = &spi3; 58 spi4 = &spi4; 59 spi5 = &spi5; 60 spi6 = &spi6; 61 spi7 = &spi7; 62 spi8 = &spi8; 63 spi9 = &spi9; 64 spi10 = &spi10; 65 spi11 = &spi11; 66 spi12 = &spi12; 67 spi13 = &spi13; 68 spi14 = &spi14; 69 spi15 = &spi15; 70 spi16 = &spi16; 71 spi17 = &spi17; 72 spi18 = &spi18; 73 spi19 = &spi19; 74 }; 75 76 chosen { }; 77 78 clocks { 79 xo_board: xo-board { 80 compatible = "fixed-clock"; 81 #clock-cells = <0>; 82 clock-frequency = <38400000>; 83 clock-output-names = "xo_board"; 84 }; 85 86 sleep_clk: sleep-clk { 87 compatible = "fixed-clock"; 88 clock-frequency = <32764>; 89 #clock-cells = <0>; 90 }; 91 }; 92 93 cpus { 94 #address-cells = <2>; 95 #size-cells = <0>; 96 97 cpu0: cpu@0 { 98 device_type = "cpu"; 99 compatible = "qcom,kryo485"; 100 reg = <0x0 0x0>; 101 clocks = <&cpufreq_hw 0>; 102 enable-method = "psci"; 103 capacity-dmips-mhz = <448>; 104 dynamic-power-coefficient = <105>; 105 next-level-cache = <&l2_0>; 106 power-domains = <&cpu_pd0>; 107 power-domain-names = "psci"; 108 qcom,freq-domain = <&cpufreq_hw 0>; 109 operating-points-v2 = <&cpu0_opp_table>; 110 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 111 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 112 #cooling-cells = <2>; 113 l2_0: l2-cache { 114 compatible = "cache"; 115 cache-level = <2>; 116 cache-size = <0x20000>; 117 cache-unified; 118 next-level-cache = <&l3_0>; 119 l3_0: l3-cache { 120 compatible = "cache"; 121 cache-level = <3>; 122 cache-size = <0x400000>; 123 cache-unified; 124 }; 125 }; 126 }; 127 128 cpu1: cpu@100 { 129 device_type = "cpu"; 130 compatible = "qcom,kryo485"; 131 reg = <0x0 0x100>; 132 clocks = <&cpufreq_hw 0>; 133 enable-method = "psci"; 134 capacity-dmips-mhz = <448>; 135 dynamic-power-coefficient = <105>; 136 next-level-cache = <&l2_100>; 137 power-domains = <&cpu_pd1>; 138 power-domain-names = "psci"; 139 qcom,freq-domain = <&cpufreq_hw 0>; 140 operating-points-v2 = <&cpu0_opp_table>; 141 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 142 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 143 #cooling-cells = <2>; 144 l2_100: l2-cache { 145 compatible = "cache"; 146 cache-level = <2>; 147 cache-size = <0x20000>; 148 cache-unified; 149 next-level-cache = <&l3_0>; 150 }; 151 }; 152 153 cpu2: cpu@200 { 154 device_type = "cpu"; 155 compatible = "qcom,kryo485"; 156 reg = <0x0 0x200>; 157 clocks = <&cpufreq_hw 0>; 158 enable-method = "psci"; 159 capacity-dmips-mhz = <448>; 160 dynamic-power-coefficient = <105>; 161 next-level-cache = <&l2_200>; 162 power-domains = <&cpu_pd2>; 163 power-domain-names = "psci"; 164 qcom,freq-domain = <&cpufreq_hw 0>; 165 operating-points-v2 = <&cpu0_opp_table>; 166 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 167 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 168 #cooling-cells = <2>; 169 l2_200: l2-cache { 170 compatible = "cache"; 171 cache-level = <2>; 172 cache-size = <0x20000>; 173 cache-unified; 174 next-level-cache = <&l3_0>; 175 }; 176 }; 177 178 cpu3: cpu@300 { 179 device_type = "cpu"; 180 compatible = "qcom,kryo485"; 181 reg = <0x0 0x300>; 182 clocks = <&cpufreq_hw 0>; 183 enable-method = "psci"; 184 capacity-dmips-mhz = <448>; 185 dynamic-power-coefficient = <105>; 186 next-level-cache = <&l2_300>; 187 power-domains = <&cpu_pd3>; 188 power-domain-names = "psci"; 189 qcom,freq-domain = <&cpufreq_hw 0>; 190 operating-points-v2 = <&cpu0_opp_table>; 191 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 192 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 193 #cooling-cells = <2>; 194 l2_300: l2-cache { 195 compatible = "cache"; 196 cache-level = <2>; 197 cache-size = <0x20000>; 198 cache-unified; 199 next-level-cache = <&l3_0>; 200 }; 201 }; 202 203 cpu4: cpu@400 { 204 device_type = "cpu"; 205 compatible = "qcom,kryo485"; 206 reg = <0x0 0x400>; 207 clocks = <&cpufreq_hw 1>; 208 enable-method = "psci"; 209 capacity-dmips-mhz = <1024>; 210 dynamic-power-coefficient = <379>; 211 next-level-cache = <&l2_400>; 212 power-domains = <&cpu_pd4>; 213 power-domain-names = "psci"; 214 qcom,freq-domain = <&cpufreq_hw 1>; 215 operating-points-v2 = <&cpu4_opp_table>; 216 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 217 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 218 #cooling-cells = <2>; 219 l2_400: l2-cache { 220 compatible = "cache"; 221 cache-level = <2>; 222 cache-size = <0x40000>; 223 cache-unified; 224 next-level-cache = <&l3_0>; 225 }; 226 }; 227 228 cpu5: cpu@500 { 229 device_type = "cpu"; 230 compatible = "qcom,kryo485"; 231 reg = <0x0 0x500>; 232 clocks = <&cpufreq_hw 1>; 233 enable-method = "psci"; 234 capacity-dmips-mhz = <1024>; 235 dynamic-power-coefficient = <379>; 236 next-level-cache = <&l2_500>; 237 power-domains = <&cpu_pd5>; 238 power-domain-names = "psci"; 239 qcom,freq-domain = <&cpufreq_hw 1>; 240 operating-points-v2 = <&cpu4_opp_table>; 241 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 242 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 243 #cooling-cells = <2>; 244 l2_500: l2-cache { 245 compatible = "cache"; 246 cache-level = <2>; 247 cache-size = <0x40000>; 248 cache-unified; 249 next-level-cache = <&l3_0>; 250 }; 251 }; 252 253 cpu6: cpu@600 { 254 device_type = "cpu"; 255 compatible = "qcom,kryo485"; 256 reg = <0x0 0x600>; 257 clocks = <&cpufreq_hw 1>; 258 enable-method = "psci"; 259 capacity-dmips-mhz = <1024>; 260 dynamic-power-coefficient = <379>; 261 next-level-cache = <&l2_600>; 262 power-domains = <&cpu_pd6>; 263 power-domain-names = "psci"; 264 qcom,freq-domain = <&cpufreq_hw 1>; 265 operating-points-v2 = <&cpu4_opp_table>; 266 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 267 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 268 #cooling-cells = <2>; 269 l2_600: l2-cache { 270 compatible = "cache"; 271 cache-level = <2>; 272 cache-size = <0x40000>; 273 cache-unified; 274 next-level-cache = <&l3_0>; 275 }; 276 }; 277 278 cpu7: cpu@700 { 279 device_type = "cpu"; 280 compatible = "qcom,kryo485"; 281 reg = <0x0 0x700>; 282 clocks = <&cpufreq_hw 2>; 283 enable-method = "psci"; 284 capacity-dmips-mhz = <1024>; 285 dynamic-power-coefficient = <444>; 286 next-level-cache = <&l2_700>; 287 power-domains = <&cpu_pd7>; 288 power-domain-names = "psci"; 289 qcom,freq-domain = <&cpufreq_hw 2>; 290 operating-points-v2 = <&cpu7_opp_table>; 291 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 292 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 293 #cooling-cells = <2>; 294 l2_700: l2-cache { 295 compatible = "cache"; 296 cache-level = <2>; 297 cache-size = <0x80000>; 298 cache-unified; 299 next-level-cache = <&l3_0>; 300 }; 301 }; 302 303 cpu-map { 304 cluster0 { 305 core0 { 306 cpu = <&cpu0>; 307 }; 308 309 core1 { 310 cpu = <&cpu1>; 311 }; 312 313 core2 { 314 cpu = <&cpu2>; 315 }; 316 317 core3 { 318 cpu = <&cpu3>; 319 }; 320 321 core4 { 322 cpu = <&cpu4>; 323 }; 324 325 core5 { 326 cpu = <&cpu5>; 327 }; 328 329 core6 { 330 cpu = <&cpu6>; 331 }; 332 333 core7 { 334 cpu = <&cpu7>; 335 }; 336 }; 337 }; 338 339 idle-states { 340 entry-method = "psci"; 341 342 little_cpu_sleep_0: cpu-sleep-0-0 { 343 compatible = "arm,idle-state"; 344 idle-state-name = "silver-rail-power-collapse"; 345 arm,psci-suspend-param = <0x40000004>; 346 entry-latency-us = <360>; 347 exit-latency-us = <531>; 348 min-residency-us = <3934>; 349 local-timer-stop; 350 }; 351 352 big_cpu_sleep_0: cpu-sleep-1-0 { 353 compatible = "arm,idle-state"; 354 idle-state-name = "gold-rail-power-collapse"; 355 arm,psci-suspend-param = <0x40000004>; 356 entry-latency-us = <702>; 357 exit-latency-us = <1061>; 358 min-residency-us = <4488>; 359 local-timer-stop; 360 }; 361 }; 362 363 domain-idle-states { 364 cluster_sleep_0: cluster-sleep-0 { 365 compatible = "domain-idle-state"; 366 arm,psci-suspend-param = <0x4100c244>; 367 entry-latency-us = <3264>; 368 exit-latency-us = <6562>; 369 min-residency-us = <9987>; 370 }; 371 }; 372 }; 373 374 qup_virt: interconnect-qup-virt { 375 compatible = "qcom,sm8250-qup-virt"; 376 #interconnect-cells = <2>; 377 qcom,bcm-voters = <&apps_bcm_voter>; 378 }; 379 380 cpu0_opp_table: opp-table-cpu0 { 381 compatible = "operating-points-v2"; 382 opp-shared; 383 384 cpu0_opp1: opp-300000000 { 385 opp-hz = /bits/ 64 <300000000>; 386 opp-peak-kBps = <800000 9600000>; 387 }; 388 389 cpu0_opp2: opp-403200000 { 390 opp-hz = /bits/ 64 <403200000>; 391 opp-peak-kBps = <800000 9600000>; 392 }; 393 394 cpu0_opp3: opp-518400000 { 395 opp-hz = /bits/ 64 <518400000>; 396 opp-peak-kBps = <800000 16588800>; 397 }; 398 399 cpu0_opp4: opp-614400000 { 400 opp-hz = /bits/ 64 <614400000>; 401 opp-peak-kBps = <800000 16588800>; 402 }; 403 404 cpu0_opp5: opp-691200000 { 405 opp-hz = /bits/ 64 <691200000>; 406 opp-peak-kBps = <800000 19660800>; 407 }; 408 409 cpu0_opp6: opp-787200000 { 410 opp-hz = /bits/ 64 <787200000>; 411 opp-peak-kBps = <1804000 19660800>; 412 }; 413 414 cpu0_opp7: opp-883200000 { 415 opp-hz = /bits/ 64 <883200000>; 416 opp-peak-kBps = <1804000 23347200>; 417 }; 418 419 cpu0_opp8: opp-979200000 { 420 opp-hz = /bits/ 64 <979200000>; 421 opp-peak-kBps = <1804000 26419200>; 422 }; 423 424 cpu0_opp9: opp-1075200000 { 425 opp-hz = /bits/ 64 <1075200000>; 426 opp-peak-kBps = <1804000 29491200>; 427 }; 428 429 cpu0_opp10: opp-1171200000 { 430 opp-hz = /bits/ 64 <1171200000>; 431 opp-peak-kBps = <1804000 32563200>; 432 }; 433 434 cpu0_opp11: opp-1248000000 { 435 opp-hz = /bits/ 64 <1248000000>; 436 opp-peak-kBps = <1804000 36249600>; 437 }; 438 439 cpu0_opp12: opp-1344000000 { 440 opp-hz = /bits/ 64 <1344000000>; 441 opp-peak-kBps = <2188000 36249600>; 442 }; 443 444 cpu0_opp13: opp-1420800000 { 445 opp-hz = /bits/ 64 <1420800000>; 446 opp-peak-kBps = <2188000 39321600>; 447 }; 448 449 cpu0_opp14: opp-1516800000 { 450 opp-hz = /bits/ 64 <1516800000>; 451 opp-peak-kBps = <3072000 42393600>; 452 }; 453 454 cpu0_opp15: opp-1612800000 { 455 opp-hz = /bits/ 64 <1612800000>; 456 opp-peak-kBps = <3072000 42393600>; 457 }; 458 459 cpu0_opp16: opp-1708800000 { 460 opp-hz = /bits/ 64 <1708800000>; 461 opp-peak-kBps = <4068000 42393600>; 462 }; 463 464 cpu0_opp17: opp-1804800000 { 465 opp-hz = /bits/ 64 <1804800000>; 466 opp-peak-kBps = <4068000 42393600>; 467 }; 468 }; 469 470 cpu4_opp_table: opp-table-cpu4 { 471 compatible = "operating-points-v2"; 472 opp-shared; 473 474 cpu4_opp1: opp-710400000 { 475 opp-hz = /bits/ 64 <710400000>; 476 opp-peak-kBps = <1804000 19660800>; 477 }; 478 479 cpu4_opp2: opp-825600000 { 480 opp-hz = /bits/ 64 <825600000>; 481 opp-peak-kBps = <2188000 23347200>; 482 }; 483 484 cpu4_opp3: opp-940800000 { 485 opp-hz = /bits/ 64 <940800000>; 486 opp-peak-kBps = <2188000 26419200>; 487 }; 488 489 cpu4_opp4: opp-1056000000 { 490 opp-hz = /bits/ 64 <1056000000>; 491 opp-peak-kBps = <3072000 26419200>; 492 }; 493 494 cpu4_opp5: opp-1171200000 { 495 opp-hz = /bits/ 64 <1171200000>; 496 opp-peak-kBps = <3072000 29491200>; 497 }; 498 499 cpu4_opp6: opp-1286400000 { 500 opp-hz = /bits/ 64 <1286400000>; 501 opp-peak-kBps = <4068000 29491200>; 502 }; 503 504 cpu4_opp7: opp-1382400000 { 505 opp-hz = /bits/ 64 <1382400000>; 506 opp-peak-kBps = <4068000 32563200>; 507 }; 508 509 cpu4_opp8: opp-1478400000 { 510 opp-hz = /bits/ 64 <1478400000>; 511 opp-peak-kBps = <4068000 32563200>; 512 }; 513 514 cpu4_opp9: opp-1574400000 { 515 opp-hz = /bits/ 64 <1574400000>; 516 opp-peak-kBps = <5412000 39321600>; 517 }; 518 519 cpu4_opp10: opp-1670400000 { 520 opp-hz = /bits/ 64 <1670400000>; 521 opp-peak-kBps = <5412000 42393600>; 522 }; 523 524 cpu4_opp11: opp-1766400000 { 525 opp-hz = /bits/ 64 <1766400000>; 526 opp-peak-kBps = <5412000 45465600>; 527 }; 528 529 cpu4_opp12: opp-1862400000 { 530 opp-hz = /bits/ 64 <1862400000>; 531 opp-peak-kBps = <6220000 45465600>; 532 }; 533 534 cpu4_opp13: opp-1958400000 { 535 opp-hz = /bits/ 64 <1958400000>; 536 opp-peak-kBps = <6220000 48537600>; 537 }; 538 539 cpu4_opp14: opp-2054400000 { 540 opp-hz = /bits/ 64 <2054400000>; 541 opp-peak-kBps = <7216000 48537600>; 542 }; 543 544 cpu4_opp15: opp-2150400000 { 545 opp-hz = /bits/ 64 <2150400000>; 546 opp-peak-kBps = <7216000 51609600>; 547 }; 548 549 cpu4_opp16: opp-2246400000 { 550 opp-hz = /bits/ 64 <2246400000>; 551 opp-peak-kBps = <7216000 51609600>; 552 }; 553 554 cpu4_opp17: opp-2342400000 { 555 opp-hz = /bits/ 64 <2342400000>; 556 opp-peak-kBps = <8368000 51609600>; 557 }; 558 559 cpu4_opp18: opp-2419200000 { 560 opp-hz = /bits/ 64 <2419200000>; 561 opp-peak-kBps = <8368000 51609600>; 562 }; 563 }; 564 565 cpu7_opp_table: opp-table-cpu7 { 566 compatible = "operating-points-v2"; 567 opp-shared; 568 569 cpu7_opp1: opp-844800000 { 570 opp-hz = /bits/ 64 <844800000>; 571 opp-peak-kBps = <2188000 19660800>; 572 }; 573 574 cpu7_opp2: opp-960000000 { 575 opp-hz = /bits/ 64 <960000000>; 576 opp-peak-kBps = <2188000 26419200>; 577 }; 578 579 cpu7_opp3: opp-1075200000 { 580 opp-hz = /bits/ 64 <1075200000>; 581 opp-peak-kBps = <3072000 26419200>; 582 }; 583 584 cpu7_opp4: opp-1190400000 { 585 opp-hz = /bits/ 64 <1190400000>; 586 opp-peak-kBps = <3072000 29491200>; 587 }; 588 589 cpu7_opp5: opp-1305600000 { 590 opp-hz = /bits/ 64 <1305600000>; 591 opp-peak-kBps = <4068000 32563200>; 592 }; 593 594 cpu7_opp6: opp-1401600000 { 595 opp-hz = /bits/ 64 <1401600000>; 596 opp-peak-kBps = <4068000 32563200>; 597 }; 598 599 cpu7_opp7: opp-1516800000 { 600 opp-hz = /bits/ 64 <1516800000>; 601 opp-peak-kBps = <4068000 36249600>; 602 }; 603 604 cpu7_opp8: opp-1632000000 { 605 opp-hz = /bits/ 64 <1632000000>; 606 opp-peak-kBps = <5412000 39321600>; 607 }; 608 609 cpu7_opp9: opp-1747200000 { 610 opp-hz = /bits/ 64 <1747200000>; 611 opp-peak-kBps = <5412000 42393600>; 612 }; 613 614 cpu7_opp10: opp-1862400000 { 615 opp-hz = /bits/ 64 <1862400000>; 616 opp-peak-kBps = <6220000 45465600>; 617 }; 618 619 cpu7_opp11: opp-1977600000 { 620 opp-hz = /bits/ 64 <1977600000>; 621 opp-peak-kBps = <6220000 48537600>; 622 }; 623 624 cpu7_opp12: opp-2073600000 { 625 opp-hz = /bits/ 64 <2073600000>; 626 opp-peak-kBps = <7216000 48537600>; 627 }; 628 629 cpu7_opp13: opp-2169600000 { 630 opp-hz = /bits/ 64 <2169600000>; 631 opp-peak-kBps = <7216000 51609600>; 632 }; 633 634 cpu7_opp14: opp-2265600000 { 635 opp-hz = /bits/ 64 <2265600000>; 636 opp-peak-kBps = <7216000 51609600>; 637 }; 638 639 cpu7_opp15: opp-2361600000 { 640 opp-hz = /bits/ 64 <2361600000>; 641 opp-peak-kBps = <8368000 51609600>; 642 }; 643 644 cpu7_opp16: opp-2457600000 { 645 opp-hz = /bits/ 64 <2457600000>; 646 opp-peak-kBps = <8368000 51609600>; 647 }; 648 649 cpu7_opp17: opp-2553600000 { 650 opp-hz = /bits/ 64 <2553600000>; 651 opp-peak-kBps = <8368000 51609600>; 652 }; 653 654 cpu7_opp18: opp-2649600000 { 655 opp-hz = /bits/ 64 <2649600000>; 656 opp-peak-kBps = <8368000 51609600>; 657 }; 658 659 cpu7_opp19: opp-2745600000 { 660 opp-hz = /bits/ 64 <2745600000>; 661 opp-peak-kBps = <8368000 51609600>; 662 }; 663 664 cpu7_opp20: opp-2841600000 { 665 opp-hz = /bits/ 64 <2841600000>; 666 opp-peak-kBps = <8368000 51609600>; 667 }; 668 669 cpu7_opp21: opp-3091200000 { 670 opp-hz = /bits/ 64 <3091200000>; 671 opp-peak-kBps = <8368000 51609600>; 672 }; 673 }; 674 675 firmware { 676 scm: scm { 677 compatible = "qcom,scm-sm8250", "qcom,scm"; 678 qcom,dload-mode = <&tcsr 0x13000>; 679 #reset-cells = <1>; 680 }; 681 }; 682 683 memory@80000000 { 684 device_type = "memory"; 685 /* We expect the bootloader to fill in the size */ 686 reg = <0x0 0x80000000 0x0 0x0>; 687 }; 688 689 pmu { 690 compatible = "arm,armv8-pmuv3"; 691 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 692 }; 693 694 psci { 695 compatible = "arm,psci-1.0"; 696 method = "smc"; 697 698 cpu_pd0: power-domain-cpu0 { 699 #power-domain-cells = <0>; 700 power-domains = <&cluster_pd>; 701 domain-idle-states = <&little_cpu_sleep_0>; 702 }; 703 704 cpu_pd1: power-domain-cpu1 { 705 #power-domain-cells = <0>; 706 power-domains = <&cluster_pd>; 707 domain-idle-states = <&little_cpu_sleep_0>; 708 }; 709 710 cpu_pd2: power-domain-cpu2 { 711 #power-domain-cells = <0>; 712 power-domains = <&cluster_pd>; 713 domain-idle-states = <&little_cpu_sleep_0>; 714 }; 715 716 cpu_pd3: power-domain-cpu3 { 717 #power-domain-cells = <0>; 718 power-domains = <&cluster_pd>; 719 domain-idle-states = <&little_cpu_sleep_0>; 720 }; 721 722 cpu_pd4: power-domain-cpu4 { 723 #power-domain-cells = <0>; 724 power-domains = <&cluster_pd>; 725 domain-idle-states = <&big_cpu_sleep_0>; 726 }; 727 728 cpu_pd5: power-domain-cpu5 { 729 #power-domain-cells = <0>; 730 power-domains = <&cluster_pd>; 731 domain-idle-states = <&big_cpu_sleep_0>; 732 }; 733 734 cpu_pd6: power-domain-cpu6 { 735 #power-domain-cells = <0>; 736 power-domains = <&cluster_pd>; 737 domain-idle-states = <&big_cpu_sleep_0>; 738 }; 739 740 cpu_pd7: power-domain-cpu7 { 741 #power-domain-cells = <0>; 742 power-domains = <&cluster_pd>; 743 domain-idle-states = <&big_cpu_sleep_0>; 744 }; 745 746 cluster_pd: power-domain-cpu-cluster0 { 747 #power-domain-cells = <0>; 748 domain-idle-states = <&cluster_sleep_0>; 749 }; 750 }; 751 752 qup_opp_table: opp-table-qup { 753 compatible = "operating-points-v2"; 754 755 opp-50000000 { 756 opp-hz = /bits/ 64 <50000000>; 757 required-opps = <&rpmhpd_opp_min_svs>; 758 }; 759 760 opp-75000000 { 761 opp-hz = /bits/ 64 <75000000>; 762 required-opps = <&rpmhpd_opp_low_svs>; 763 }; 764 765 opp-120000000 { 766 opp-hz = /bits/ 64 <120000000>; 767 required-opps = <&rpmhpd_opp_svs>; 768 }; 769 }; 770 771 reserved-memory { 772 #address-cells = <2>; 773 #size-cells = <2>; 774 ranges; 775 776 hyp_mem: memory@80000000 { 777 reg = <0x0 0x80000000 0x0 0x600000>; 778 no-map; 779 }; 780 781 xbl_aop_mem: memory@80700000 { 782 reg = <0x0 0x80700000 0x0 0x160000>; 783 no-map; 784 }; 785 786 cmd_db: memory@80860000 { 787 compatible = "qcom,cmd-db"; 788 reg = <0x0 0x80860000 0x0 0x20000>; 789 no-map; 790 }; 791 792 smem_mem: memory@80900000 { 793 reg = <0x0 0x80900000 0x0 0x200000>; 794 no-map; 795 }; 796 797 removed_mem: memory@80b00000 { 798 reg = <0x0 0x80b00000 0x0 0x5300000>; 799 no-map; 800 }; 801 802 camera_mem: memory@86200000 { 803 reg = <0x0 0x86200000 0x0 0x500000>; 804 no-map; 805 }; 806 807 wlan_mem: memory@86700000 { 808 reg = <0x0 0x86700000 0x0 0x100000>; 809 no-map; 810 }; 811 812 ipa_fw_mem: memory@86800000 { 813 reg = <0x0 0x86800000 0x0 0x10000>; 814 no-map; 815 }; 816 817 ipa_gsi_mem: memory@86810000 { 818 reg = <0x0 0x86810000 0x0 0xa000>; 819 no-map; 820 }; 821 822 gpu_mem: memory@8681a000 { 823 reg = <0x0 0x8681a000 0x0 0x2000>; 824 no-map; 825 }; 826 827 npu_mem: memory@86900000 { 828 reg = <0x0 0x86900000 0x0 0x500000>; 829 no-map; 830 }; 831 832 video_mem: memory@86e00000 { 833 reg = <0x0 0x86e00000 0x0 0x500000>; 834 no-map; 835 }; 836 837 cvp_mem: memory@87300000 { 838 reg = <0x0 0x87300000 0x0 0x500000>; 839 no-map; 840 }; 841 842 cdsp_mem: memory@87800000 { 843 reg = <0x0 0x87800000 0x0 0x1400000>; 844 no-map; 845 }; 846 847 slpi_mem: memory@88c00000 { 848 reg = <0x0 0x88c00000 0x0 0x1500000>; 849 no-map; 850 }; 851 852 adsp_mem: memory@8a100000 { 853 reg = <0x0 0x8a100000 0x0 0x1d00000>; 854 no-map; 855 }; 856 857 spss_mem: memory@8be00000 { 858 reg = <0x0 0x8be00000 0x0 0x100000>; 859 no-map; 860 }; 861 862 cdsp_secure_heap: memory@8bf00000 { 863 reg = <0x0 0x8bf00000 0x0 0x4600000>; 864 no-map; 865 }; 866 }; 867 868 smem { 869 compatible = "qcom,smem"; 870 memory-region = <&smem_mem>; 871 hwlocks = <&tcsr_mutex 3>; 872 }; 873 874 smp2p-adsp { 875 compatible = "qcom,smp2p"; 876 qcom,smem = <443>, <429>; 877 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 878 IPCC_MPROC_SIGNAL_SMP2P 879 IRQ_TYPE_EDGE_RISING>; 880 mboxes = <&ipcc IPCC_CLIENT_LPASS 881 IPCC_MPROC_SIGNAL_SMP2P>; 882 883 qcom,local-pid = <0>; 884 qcom,remote-pid = <2>; 885 886 smp2p_adsp_out: master-kernel { 887 qcom,entry-name = "master-kernel"; 888 #qcom,smem-state-cells = <1>; 889 }; 890 891 smp2p_adsp_in: slave-kernel { 892 qcom,entry-name = "slave-kernel"; 893 interrupt-controller; 894 #interrupt-cells = <2>; 895 }; 896 }; 897 898 smp2p-cdsp { 899 compatible = "qcom,smp2p"; 900 qcom,smem = <94>, <432>; 901 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 902 IPCC_MPROC_SIGNAL_SMP2P 903 IRQ_TYPE_EDGE_RISING>; 904 mboxes = <&ipcc IPCC_CLIENT_CDSP 905 IPCC_MPROC_SIGNAL_SMP2P>; 906 907 qcom,local-pid = <0>; 908 qcom,remote-pid = <5>; 909 910 smp2p_cdsp_out: master-kernel { 911 qcom,entry-name = "master-kernel"; 912 #qcom,smem-state-cells = <1>; 913 }; 914 915 smp2p_cdsp_in: slave-kernel { 916 qcom,entry-name = "slave-kernel"; 917 interrupt-controller; 918 #interrupt-cells = <2>; 919 }; 920 }; 921 922 smp2p-slpi { 923 compatible = "qcom,smp2p"; 924 qcom,smem = <481>, <430>; 925 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 926 IPCC_MPROC_SIGNAL_SMP2P 927 IRQ_TYPE_EDGE_RISING>; 928 mboxes = <&ipcc IPCC_CLIENT_SLPI 929 IPCC_MPROC_SIGNAL_SMP2P>; 930 931 qcom,local-pid = <0>; 932 qcom,remote-pid = <3>; 933 934 smp2p_slpi_out: master-kernel { 935 qcom,entry-name = "master-kernel"; 936 #qcom,smem-state-cells = <1>; 937 }; 938 939 smp2p_slpi_in: slave-kernel { 940 qcom,entry-name = "slave-kernel"; 941 interrupt-controller; 942 #interrupt-cells = <2>; 943 }; 944 }; 945 946 soc: soc@0 { 947 #address-cells = <2>; 948 #size-cells = <2>; 949 ranges = <0 0 0 0 0x10 0>; 950 dma-ranges = <0 0 0 0 0x10 0>; 951 compatible = "simple-bus"; 952 953 gcc: clock-controller@100000 { 954 compatible = "qcom,gcc-sm8250"; 955 reg = <0x0 0x00100000 0x0 0x1f0000>; 956 #clock-cells = <1>; 957 #reset-cells = <1>; 958 #power-domain-cells = <1>; 959 clock-names = "bi_tcxo", 960 "bi_tcxo_ao", 961 "sleep_clk"; 962 clocks = <&rpmhcc RPMH_CXO_CLK>, 963 <&rpmhcc RPMH_CXO_CLK_A>, 964 <&sleep_clk>; 965 }; 966 967 ipcc: mailbox@408000 { 968 compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; 969 reg = <0 0x00408000 0 0x1000>; 970 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 971 interrupt-controller; 972 #interrupt-cells = <3>; 973 #mbox-cells = <2>; 974 }; 975 976 qfprom: efuse@784000 { 977 compatible = "qcom,sm8250-qfprom", "qcom,qfprom"; 978 reg = <0 0x00784000 0 0x8ff>; 979 #address-cells = <1>; 980 #size-cells = <1>; 981 982 gpu_speed_bin: gpu-speed-bin@19b { 983 reg = <0x19b 0x1>; 984 bits = <5 3>; 985 }; 986 }; 987 988 rng: rng@793000 { 989 compatible = "qcom,prng-ee"; 990 reg = <0 0x00793000 0 0x1000>; 991 clocks = <&gcc GCC_PRNG_AHB_CLK>; 992 clock-names = "core"; 993 }; 994 995 gpi_dma2: dma-controller@800000 { 996 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 997 reg = <0 0x00800000 0 0x70000>; 998 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 999 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 1000 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 1001 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1002 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 1003 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 1004 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1005 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1006 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1007 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; 1008 dma-channels = <10>; 1009 dma-channel-mask = <0x3f>; 1010 iommus = <&apps_smmu 0x76 0x0>; 1011 #dma-cells = <3>; 1012 status = "disabled"; 1013 }; 1014 1015 qupv3_id_2: geniqup@8c0000 { 1016 compatible = "qcom,geni-se-qup"; 1017 reg = <0x0 0x008c0000 0x0 0x6000>; 1018 clock-names = "m-ahb", "s-ahb"; 1019 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1020 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1021 #address-cells = <2>; 1022 #size-cells = <2>; 1023 iommus = <&apps_smmu 0x63 0x0>; 1024 ranges; 1025 status = "disabled"; 1026 1027 i2c14: i2c@880000 { 1028 compatible = "qcom,geni-i2c"; 1029 reg = <0 0x00880000 0 0x4000>; 1030 clock-names = "se"; 1031 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1032 pinctrl-names = "default"; 1033 pinctrl-0 = <&qup_i2c14_default>; 1034 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1035 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1036 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1037 dma-names = "tx", "rx"; 1038 power-domains = <&rpmhpd RPMHPD_CX>; 1039 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1040 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1041 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1042 interconnect-names = "qup-core", 1043 "qup-config", 1044 "qup-memory"; 1045 #address-cells = <1>; 1046 #size-cells = <0>; 1047 status = "disabled"; 1048 }; 1049 1050 spi14: spi@880000 { 1051 compatible = "qcom,geni-spi"; 1052 reg = <0 0x00880000 0 0x4000>; 1053 clock-names = "se"; 1054 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1055 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1056 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1057 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1058 dma-names = "tx", "rx"; 1059 power-domains = <&rpmhpd RPMHPD_CX>; 1060 operating-points-v2 = <&qup_opp_table>; 1061 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1062 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1063 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1064 interconnect-names = "qup-core", 1065 "qup-config", 1066 "qup-memory"; 1067 #address-cells = <1>; 1068 #size-cells = <0>; 1069 status = "disabled"; 1070 }; 1071 1072 i2c15: i2c@884000 { 1073 compatible = "qcom,geni-i2c"; 1074 reg = <0 0x00884000 0 0x4000>; 1075 clock-names = "se"; 1076 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1077 pinctrl-names = "default"; 1078 pinctrl-0 = <&qup_i2c15_default>; 1079 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1080 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1081 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1082 dma-names = "tx", "rx"; 1083 power-domains = <&rpmhpd RPMHPD_CX>; 1084 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1085 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1086 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1087 interconnect-names = "qup-core", 1088 "qup-config", 1089 "qup-memory"; 1090 #address-cells = <1>; 1091 #size-cells = <0>; 1092 status = "disabled"; 1093 }; 1094 1095 spi15: spi@884000 { 1096 compatible = "qcom,geni-spi"; 1097 reg = <0 0x00884000 0 0x4000>; 1098 clock-names = "se"; 1099 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1100 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1101 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1102 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1103 dma-names = "tx", "rx"; 1104 power-domains = <&rpmhpd RPMHPD_CX>; 1105 operating-points-v2 = <&qup_opp_table>; 1106 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1107 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1108 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1109 interconnect-names = "qup-core", 1110 "qup-config", 1111 "qup-memory"; 1112 #address-cells = <1>; 1113 #size-cells = <0>; 1114 status = "disabled"; 1115 }; 1116 1117 i2c16: i2c@888000 { 1118 compatible = "qcom,geni-i2c"; 1119 reg = <0 0x00888000 0 0x4000>; 1120 clock-names = "se"; 1121 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1122 pinctrl-names = "default"; 1123 pinctrl-0 = <&qup_i2c16_default>; 1124 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1125 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1126 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1127 dma-names = "tx", "rx"; 1128 power-domains = <&rpmhpd RPMHPD_CX>; 1129 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1130 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1131 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1132 interconnect-names = "qup-core", 1133 "qup-config", 1134 "qup-memory"; 1135 #address-cells = <1>; 1136 #size-cells = <0>; 1137 status = "disabled"; 1138 }; 1139 1140 spi16: spi@888000 { 1141 compatible = "qcom,geni-spi"; 1142 reg = <0 0x00888000 0 0x4000>; 1143 clock-names = "se"; 1144 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1145 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1146 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1147 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1148 dma-names = "tx", "rx"; 1149 power-domains = <&rpmhpd RPMHPD_CX>; 1150 operating-points-v2 = <&qup_opp_table>; 1151 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1152 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1153 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1154 interconnect-names = "qup-core", 1155 "qup-config", 1156 "qup-memory"; 1157 #address-cells = <1>; 1158 #size-cells = <0>; 1159 status = "disabled"; 1160 }; 1161 1162 i2c17: i2c@88c000 { 1163 compatible = "qcom,geni-i2c"; 1164 reg = <0 0x0088c000 0 0x4000>; 1165 clock-names = "se"; 1166 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1167 pinctrl-names = "default"; 1168 pinctrl-0 = <&qup_i2c17_default>; 1169 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1170 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1171 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1172 dma-names = "tx", "rx"; 1173 power-domains = <&rpmhpd RPMHPD_CX>; 1174 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1175 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1176 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1177 interconnect-names = "qup-core", 1178 "qup-config", 1179 "qup-memory"; 1180 #address-cells = <1>; 1181 #size-cells = <0>; 1182 status = "disabled"; 1183 }; 1184 1185 spi17: spi@88c000 { 1186 compatible = "qcom,geni-spi"; 1187 reg = <0 0x0088c000 0 0x4000>; 1188 clock-names = "se"; 1189 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1190 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1191 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1192 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1193 dma-names = "tx", "rx"; 1194 power-domains = <&rpmhpd RPMHPD_CX>; 1195 operating-points-v2 = <&qup_opp_table>; 1196 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1197 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1198 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1199 interconnect-names = "qup-core", 1200 "qup-config", 1201 "qup-memory"; 1202 #address-cells = <1>; 1203 #size-cells = <0>; 1204 status = "disabled"; 1205 }; 1206 1207 uart17: serial@88c000 { 1208 compatible = "qcom,geni-uart"; 1209 reg = <0 0x0088c000 0 0x4000>; 1210 clock-names = "se"; 1211 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1212 pinctrl-names = "default"; 1213 pinctrl-0 = <&qup_uart17_default>; 1214 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1215 power-domains = <&rpmhpd RPMHPD_CX>; 1216 operating-points-v2 = <&qup_opp_table>; 1217 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1218 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1219 interconnect-names = "qup-core", 1220 "qup-config"; 1221 status = "disabled"; 1222 }; 1223 1224 i2c18: i2c@890000 { 1225 compatible = "qcom,geni-i2c"; 1226 reg = <0 0x00890000 0 0x4000>; 1227 clock-names = "se"; 1228 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1229 pinctrl-names = "default"; 1230 pinctrl-0 = <&qup_i2c18_default>; 1231 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1232 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1233 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1234 dma-names = "tx", "rx"; 1235 power-domains = <&rpmhpd RPMHPD_CX>; 1236 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1237 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1238 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1239 interconnect-names = "qup-core", 1240 "qup-config", 1241 "qup-memory"; 1242 #address-cells = <1>; 1243 #size-cells = <0>; 1244 status = "disabled"; 1245 }; 1246 1247 spi18: spi@890000 { 1248 compatible = "qcom,geni-spi"; 1249 reg = <0 0x00890000 0 0x4000>; 1250 clock-names = "se"; 1251 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1252 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1253 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1254 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1255 dma-names = "tx", "rx"; 1256 power-domains = <&rpmhpd RPMHPD_CX>; 1257 operating-points-v2 = <&qup_opp_table>; 1258 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1259 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1260 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1261 interconnect-names = "qup-core", 1262 "qup-config", 1263 "qup-memory"; 1264 #address-cells = <1>; 1265 #size-cells = <0>; 1266 status = "disabled"; 1267 }; 1268 1269 uart18: serial@890000 { 1270 compatible = "qcom,geni-uart"; 1271 reg = <0 0x00890000 0 0x4000>; 1272 clock-names = "se"; 1273 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1274 pinctrl-names = "default"; 1275 pinctrl-0 = <&qup_uart18_default>; 1276 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1277 power-domains = <&rpmhpd RPMHPD_CX>; 1278 operating-points-v2 = <&qup_opp_table>; 1279 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1280 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1281 interconnect-names = "qup-core", 1282 "qup-config"; 1283 status = "disabled"; 1284 }; 1285 1286 i2c19: i2c@894000 { 1287 compatible = "qcom,geni-i2c"; 1288 reg = <0 0x00894000 0 0x4000>; 1289 clock-names = "se"; 1290 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1291 pinctrl-names = "default"; 1292 pinctrl-0 = <&qup_i2c19_default>; 1293 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1294 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1295 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1296 dma-names = "tx", "rx"; 1297 power-domains = <&rpmhpd RPMHPD_CX>; 1298 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1299 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1300 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1301 interconnect-names = "qup-core", 1302 "qup-config", 1303 "qup-memory"; 1304 #address-cells = <1>; 1305 #size-cells = <0>; 1306 status = "disabled"; 1307 }; 1308 1309 spi19: spi@894000 { 1310 compatible = "qcom,geni-spi"; 1311 reg = <0 0x00894000 0 0x4000>; 1312 clock-names = "se"; 1313 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1314 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1315 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1316 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1317 dma-names = "tx", "rx"; 1318 power-domains = <&rpmhpd RPMHPD_CX>; 1319 operating-points-v2 = <&qup_opp_table>; 1320 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1321 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1322 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1323 interconnect-names = "qup-core", 1324 "qup-config", 1325 "qup-memory"; 1326 #address-cells = <1>; 1327 #size-cells = <0>; 1328 status = "disabled"; 1329 }; 1330 }; 1331 1332 gpi_dma0: dma-controller@900000 { 1333 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 1334 reg = <0 0x00900000 0 0x70000>; 1335 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1336 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1337 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1338 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1339 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1340 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1341 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1342 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1343 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1344 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1345 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1346 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1347 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1348 dma-channels = <15>; 1349 dma-channel-mask = <0x7ff>; 1350 iommus = <&apps_smmu 0x5b6 0x0>; 1351 #dma-cells = <3>; 1352 status = "disabled"; 1353 }; 1354 1355 qupv3_id_0: geniqup@9c0000 { 1356 compatible = "qcom,geni-se-qup"; 1357 reg = <0x0 0x009c0000 0x0 0x6000>; 1358 clock-names = "m-ahb", "s-ahb"; 1359 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1360 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1361 #address-cells = <2>; 1362 #size-cells = <2>; 1363 iommus = <&apps_smmu 0x5a3 0x0>; 1364 ranges; 1365 status = "disabled"; 1366 1367 i2c0: i2c@980000 { 1368 compatible = "qcom,geni-i2c"; 1369 reg = <0 0x00980000 0 0x4000>; 1370 clock-names = "se"; 1371 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1372 pinctrl-names = "default"; 1373 pinctrl-0 = <&qup_i2c0_default>; 1374 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1375 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1376 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1377 dma-names = "tx", "rx"; 1378 power-domains = <&rpmhpd RPMHPD_CX>; 1379 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1380 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1381 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1382 interconnect-names = "qup-core", 1383 "qup-config", 1384 "qup-memory"; 1385 #address-cells = <1>; 1386 #size-cells = <0>; 1387 status = "disabled"; 1388 }; 1389 1390 spi0: spi@980000 { 1391 compatible = "qcom,geni-spi"; 1392 reg = <0 0x00980000 0 0x4000>; 1393 clock-names = "se"; 1394 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1395 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1396 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1397 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1398 dma-names = "tx", "rx"; 1399 power-domains = <&rpmhpd RPMHPD_CX>; 1400 operating-points-v2 = <&qup_opp_table>; 1401 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1402 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1403 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1404 interconnect-names = "qup-core", 1405 "qup-config", 1406 "qup-memory"; 1407 #address-cells = <1>; 1408 #size-cells = <0>; 1409 status = "disabled"; 1410 }; 1411 1412 i2c1: i2c@984000 { 1413 compatible = "qcom,geni-i2c"; 1414 reg = <0 0x00984000 0 0x4000>; 1415 clock-names = "se"; 1416 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1417 pinctrl-names = "default"; 1418 pinctrl-0 = <&qup_i2c1_default>; 1419 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1420 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1421 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1422 dma-names = "tx", "rx"; 1423 power-domains = <&rpmhpd RPMHPD_CX>; 1424 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1425 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1426 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1427 interconnect-names = "qup-core", 1428 "qup-config", 1429 "qup-memory"; 1430 #address-cells = <1>; 1431 #size-cells = <0>; 1432 status = "disabled"; 1433 }; 1434 1435 spi1: spi@984000 { 1436 compatible = "qcom,geni-spi"; 1437 reg = <0 0x00984000 0 0x4000>; 1438 clock-names = "se"; 1439 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1440 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1441 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1442 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1443 dma-names = "tx", "rx"; 1444 power-domains = <&rpmhpd RPMHPD_CX>; 1445 operating-points-v2 = <&qup_opp_table>; 1446 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1447 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1448 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1449 interconnect-names = "qup-core", 1450 "qup-config", 1451 "qup-memory"; 1452 #address-cells = <1>; 1453 #size-cells = <0>; 1454 status = "disabled"; 1455 }; 1456 1457 i2c2: i2c@988000 { 1458 compatible = "qcom,geni-i2c"; 1459 reg = <0 0x00988000 0 0x4000>; 1460 clock-names = "se"; 1461 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1462 pinctrl-names = "default"; 1463 pinctrl-0 = <&qup_i2c2_default>; 1464 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1465 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1466 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1467 dma-names = "tx", "rx"; 1468 power-domains = <&rpmhpd RPMHPD_CX>; 1469 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1470 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1471 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1472 interconnect-names = "qup-core", 1473 "qup-config", 1474 "qup-memory"; 1475 #address-cells = <1>; 1476 #size-cells = <0>; 1477 status = "disabled"; 1478 }; 1479 1480 spi2: spi@988000 { 1481 compatible = "qcom,geni-spi"; 1482 reg = <0 0x00988000 0 0x4000>; 1483 clock-names = "se"; 1484 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1485 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1486 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1487 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1488 dma-names = "tx", "rx"; 1489 power-domains = <&rpmhpd RPMHPD_CX>; 1490 operating-points-v2 = <&qup_opp_table>; 1491 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1492 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1493 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1494 interconnect-names = "qup-core", 1495 "qup-config", 1496 "qup-memory"; 1497 #address-cells = <1>; 1498 #size-cells = <0>; 1499 status = "disabled"; 1500 }; 1501 1502 uart2: serial@988000 { 1503 compatible = "qcom,geni-debug-uart"; 1504 reg = <0 0x00988000 0 0x4000>; 1505 clock-names = "se"; 1506 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1507 pinctrl-names = "default"; 1508 pinctrl-0 = <&qup_uart2_default>; 1509 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1510 power-domains = <&rpmhpd RPMHPD_CX>; 1511 operating-points-v2 = <&qup_opp_table>; 1512 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1513 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1514 interconnect-names = "qup-core", 1515 "qup-config"; 1516 status = "disabled"; 1517 }; 1518 1519 i2c3: i2c@98c000 { 1520 compatible = "qcom,geni-i2c"; 1521 reg = <0 0x0098c000 0 0x4000>; 1522 clock-names = "se"; 1523 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1524 pinctrl-names = "default"; 1525 pinctrl-0 = <&qup_i2c3_default>; 1526 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1527 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1528 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1529 dma-names = "tx", "rx"; 1530 power-domains = <&rpmhpd RPMHPD_CX>; 1531 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1532 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1533 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1534 interconnect-names = "qup-core", 1535 "qup-config", 1536 "qup-memory"; 1537 #address-cells = <1>; 1538 #size-cells = <0>; 1539 status = "disabled"; 1540 }; 1541 1542 spi3: spi@98c000 { 1543 compatible = "qcom,geni-spi"; 1544 reg = <0 0x0098c000 0 0x4000>; 1545 clock-names = "se"; 1546 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1547 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1548 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1549 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1550 dma-names = "tx", "rx"; 1551 power-domains = <&rpmhpd RPMHPD_CX>; 1552 operating-points-v2 = <&qup_opp_table>; 1553 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1554 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1555 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1556 interconnect-names = "qup-core", 1557 "qup-config", 1558 "qup-memory"; 1559 #address-cells = <1>; 1560 #size-cells = <0>; 1561 status = "disabled"; 1562 }; 1563 1564 i2c4: i2c@990000 { 1565 compatible = "qcom,geni-i2c"; 1566 reg = <0 0x00990000 0 0x4000>; 1567 clock-names = "se"; 1568 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1569 pinctrl-names = "default"; 1570 pinctrl-0 = <&qup_i2c4_default>; 1571 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1572 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1573 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1574 dma-names = "tx", "rx"; 1575 power-domains = <&rpmhpd RPMHPD_CX>; 1576 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1577 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1578 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1579 interconnect-names = "qup-core", 1580 "qup-config", 1581 "qup-memory"; 1582 #address-cells = <1>; 1583 #size-cells = <0>; 1584 status = "disabled"; 1585 }; 1586 1587 spi4: spi@990000 { 1588 compatible = "qcom,geni-spi"; 1589 reg = <0 0x00990000 0 0x4000>; 1590 clock-names = "se"; 1591 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1592 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1593 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1594 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1595 dma-names = "tx", "rx"; 1596 power-domains = <&rpmhpd RPMHPD_CX>; 1597 operating-points-v2 = <&qup_opp_table>; 1598 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1599 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1600 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1601 interconnect-names = "qup-core", 1602 "qup-config", 1603 "qup-memory"; 1604 #address-cells = <1>; 1605 #size-cells = <0>; 1606 status = "disabled"; 1607 }; 1608 1609 i2c5: i2c@994000 { 1610 compatible = "qcom,geni-i2c"; 1611 reg = <0 0x00994000 0 0x4000>; 1612 clock-names = "se"; 1613 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1614 pinctrl-names = "default"; 1615 pinctrl-0 = <&qup_i2c5_default>; 1616 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1617 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1618 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1619 dma-names = "tx", "rx"; 1620 power-domains = <&rpmhpd RPMHPD_CX>; 1621 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1622 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1623 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1624 interconnect-names = "qup-core", 1625 "qup-config", 1626 "qup-memory"; 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 status = "disabled"; 1630 }; 1631 1632 spi5: spi@994000 { 1633 compatible = "qcom,geni-spi"; 1634 reg = <0 0x00994000 0 0x4000>; 1635 clock-names = "se"; 1636 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1637 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1638 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1639 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1640 dma-names = "tx", "rx"; 1641 power-domains = <&rpmhpd RPMHPD_CX>; 1642 operating-points-v2 = <&qup_opp_table>; 1643 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1644 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1645 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1646 interconnect-names = "qup-core", 1647 "qup-config", 1648 "qup-memory"; 1649 #address-cells = <1>; 1650 #size-cells = <0>; 1651 status = "disabled"; 1652 }; 1653 1654 i2c6: i2c@998000 { 1655 compatible = "qcom,geni-i2c"; 1656 reg = <0 0x00998000 0 0x4000>; 1657 clock-names = "se"; 1658 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1659 pinctrl-names = "default"; 1660 pinctrl-0 = <&qup_i2c6_default>; 1661 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1662 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1663 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1664 dma-names = "tx", "rx"; 1665 power-domains = <&rpmhpd RPMHPD_CX>; 1666 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1667 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1668 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1669 interconnect-names = "qup-core", 1670 "qup-config", 1671 "qup-memory"; 1672 #address-cells = <1>; 1673 #size-cells = <0>; 1674 status = "disabled"; 1675 }; 1676 1677 spi6: spi@998000 { 1678 compatible = "qcom,geni-spi"; 1679 reg = <0 0x00998000 0 0x4000>; 1680 clock-names = "se"; 1681 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1682 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1683 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1684 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1685 dma-names = "tx", "rx"; 1686 power-domains = <&rpmhpd RPMHPD_CX>; 1687 operating-points-v2 = <&qup_opp_table>; 1688 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1689 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1690 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1691 interconnect-names = "qup-core", 1692 "qup-config", 1693 "qup-memory"; 1694 #address-cells = <1>; 1695 #size-cells = <0>; 1696 status = "disabled"; 1697 }; 1698 1699 uart6: serial@998000 { 1700 compatible = "qcom,geni-uart"; 1701 reg = <0 0x00998000 0 0x4000>; 1702 clock-names = "se"; 1703 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1704 pinctrl-names = "default"; 1705 pinctrl-0 = <&qup_uart6_default>; 1706 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1707 power-domains = <&rpmhpd RPMHPD_CX>; 1708 operating-points-v2 = <&qup_opp_table>; 1709 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1710 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1711 interconnect-names = "qup-core", 1712 "qup-config"; 1713 status = "disabled"; 1714 }; 1715 1716 i2c7: i2c@99c000 { 1717 compatible = "qcom,geni-i2c"; 1718 reg = <0 0x0099c000 0 0x4000>; 1719 clock-names = "se"; 1720 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1721 pinctrl-names = "default"; 1722 pinctrl-0 = <&qup_i2c7_default>; 1723 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1724 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1725 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1726 dma-names = "tx", "rx"; 1727 power-domains = <&rpmhpd RPMHPD_CX>; 1728 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1729 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1730 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1731 interconnect-names = "qup-core", 1732 "qup-config", 1733 "qup-memory"; 1734 #address-cells = <1>; 1735 #size-cells = <0>; 1736 status = "disabled"; 1737 }; 1738 1739 spi7: spi@99c000 { 1740 compatible = "qcom,geni-spi"; 1741 reg = <0 0x0099c000 0 0x4000>; 1742 clock-names = "se"; 1743 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1744 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1745 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1746 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1747 dma-names = "tx", "rx"; 1748 power-domains = <&rpmhpd RPMHPD_CX>; 1749 operating-points-v2 = <&qup_opp_table>; 1750 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1751 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1752 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1753 interconnect-names = "qup-core", 1754 "qup-config", 1755 "qup-memory"; 1756 #address-cells = <1>; 1757 #size-cells = <0>; 1758 status = "disabled"; 1759 }; 1760 }; 1761 1762 gpi_dma1: dma-controller@a00000 { 1763 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 1764 reg = <0 0x00a00000 0 0x70000>; 1765 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1770 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1771 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1772 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1773 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1774 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; 1775 dma-channels = <10>; 1776 dma-channel-mask = <0x3f>; 1777 iommus = <&apps_smmu 0x56 0x0>; 1778 #dma-cells = <3>; 1779 status = "disabled"; 1780 }; 1781 1782 qupv3_id_1: geniqup@ac0000 { 1783 compatible = "qcom,geni-se-qup"; 1784 reg = <0x0 0x00ac0000 0x0 0x6000>; 1785 clock-names = "m-ahb", "s-ahb"; 1786 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1787 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1788 #address-cells = <2>; 1789 #size-cells = <2>; 1790 iommus = <&apps_smmu 0x43 0x0>; 1791 ranges; 1792 status = "disabled"; 1793 1794 i2c8: i2c@a80000 { 1795 compatible = "qcom,geni-i2c"; 1796 reg = <0 0x00a80000 0 0x4000>; 1797 clock-names = "se"; 1798 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1799 pinctrl-names = "default"; 1800 pinctrl-0 = <&qup_i2c8_default>; 1801 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1802 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1803 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1804 dma-names = "tx", "rx"; 1805 power-domains = <&rpmhpd RPMHPD_CX>; 1806 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1807 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1808 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1809 interconnect-names = "qup-core", 1810 "qup-config", 1811 "qup-memory"; 1812 #address-cells = <1>; 1813 #size-cells = <0>; 1814 status = "disabled"; 1815 }; 1816 1817 spi8: spi@a80000 { 1818 compatible = "qcom,geni-spi"; 1819 reg = <0 0x00a80000 0 0x4000>; 1820 clock-names = "se"; 1821 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1822 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1823 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1824 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1825 dma-names = "tx", "rx"; 1826 power-domains = <&rpmhpd RPMHPD_CX>; 1827 operating-points-v2 = <&qup_opp_table>; 1828 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1829 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1830 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1831 interconnect-names = "qup-core", 1832 "qup-config", 1833 "qup-memory"; 1834 #address-cells = <1>; 1835 #size-cells = <0>; 1836 status = "disabled"; 1837 }; 1838 1839 i2c9: i2c@a84000 { 1840 compatible = "qcom,geni-i2c"; 1841 reg = <0 0x00a84000 0 0x4000>; 1842 clock-names = "se"; 1843 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1844 pinctrl-names = "default"; 1845 pinctrl-0 = <&qup_i2c9_default>; 1846 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1847 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1848 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1849 dma-names = "tx", "rx"; 1850 power-domains = <&rpmhpd RPMHPD_CX>; 1851 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1852 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1853 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1854 interconnect-names = "qup-core", 1855 "qup-config", 1856 "qup-memory"; 1857 #address-cells = <1>; 1858 #size-cells = <0>; 1859 status = "disabled"; 1860 }; 1861 1862 spi9: spi@a84000 { 1863 compatible = "qcom,geni-spi"; 1864 reg = <0 0x00a84000 0 0x4000>; 1865 clock-names = "se"; 1866 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1867 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1868 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1869 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1870 dma-names = "tx", "rx"; 1871 power-domains = <&rpmhpd RPMHPD_CX>; 1872 operating-points-v2 = <&qup_opp_table>; 1873 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1874 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1875 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1876 interconnect-names = "qup-core", 1877 "qup-config", 1878 "qup-memory"; 1879 #address-cells = <1>; 1880 #size-cells = <0>; 1881 status = "disabled"; 1882 }; 1883 1884 i2c10: i2c@a88000 { 1885 compatible = "qcom,geni-i2c"; 1886 reg = <0 0x00a88000 0 0x4000>; 1887 clock-names = "se"; 1888 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1889 pinctrl-names = "default"; 1890 pinctrl-0 = <&qup_i2c10_default>; 1891 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1892 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1893 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1894 dma-names = "tx", "rx"; 1895 power-domains = <&rpmhpd RPMHPD_CX>; 1896 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1897 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1898 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1899 interconnect-names = "qup-core", 1900 "qup-config", 1901 "qup-memory"; 1902 #address-cells = <1>; 1903 #size-cells = <0>; 1904 status = "disabled"; 1905 }; 1906 1907 spi10: spi@a88000 { 1908 compatible = "qcom,geni-spi"; 1909 reg = <0 0x00a88000 0 0x4000>; 1910 clock-names = "se"; 1911 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1912 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1913 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1914 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1915 dma-names = "tx", "rx"; 1916 power-domains = <&rpmhpd RPMHPD_CX>; 1917 operating-points-v2 = <&qup_opp_table>; 1918 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1919 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1920 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1921 interconnect-names = "qup-core", 1922 "qup-config", 1923 "qup-memory"; 1924 #address-cells = <1>; 1925 #size-cells = <0>; 1926 status = "disabled"; 1927 }; 1928 1929 i2c11: i2c@a8c000 { 1930 compatible = "qcom,geni-i2c"; 1931 reg = <0 0x00a8c000 0 0x4000>; 1932 clock-names = "se"; 1933 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1934 pinctrl-names = "default"; 1935 pinctrl-0 = <&qup_i2c11_default>; 1936 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1937 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1938 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1939 dma-names = "tx", "rx"; 1940 power-domains = <&rpmhpd RPMHPD_CX>; 1941 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1942 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1943 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1944 interconnect-names = "qup-core", 1945 "qup-config", 1946 "qup-memory"; 1947 #address-cells = <1>; 1948 #size-cells = <0>; 1949 status = "disabled"; 1950 }; 1951 1952 spi11: spi@a8c000 { 1953 compatible = "qcom,geni-spi"; 1954 reg = <0 0x00a8c000 0 0x4000>; 1955 clock-names = "se"; 1956 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1957 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1958 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1959 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1960 dma-names = "tx", "rx"; 1961 power-domains = <&rpmhpd RPMHPD_CX>; 1962 operating-points-v2 = <&qup_opp_table>; 1963 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1964 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1965 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1966 interconnect-names = "qup-core", 1967 "qup-config", 1968 "qup-memory"; 1969 #address-cells = <1>; 1970 #size-cells = <0>; 1971 status = "disabled"; 1972 }; 1973 1974 i2c12: i2c@a90000 { 1975 compatible = "qcom,geni-i2c"; 1976 reg = <0 0x00a90000 0 0x4000>; 1977 clock-names = "se"; 1978 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1979 pinctrl-names = "default"; 1980 pinctrl-0 = <&qup_i2c12_default>; 1981 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1982 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1983 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1984 dma-names = "tx", "rx"; 1985 power-domains = <&rpmhpd RPMHPD_CX>; 1986 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1987 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1988 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1989 interconnect-names = "qup-core", 1990 "qup-config", 1991 "qup-memory"; 1992 #address-cells = <1>; 1993 #size-cells = <0>; 1994 status = "disabled"; 1995 }; 1996 1997 spi12: spi@a90000 { 1998 compatible = "qcom,geni-spi"; 1999 reg = <0 0x00a90000 0 0x4000>; 2000 clock-names = "se"; 2001 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2002 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2003 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 2004 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 2005 dma-names = "tx", "rx"; 2006 power-domains = <&rpmhpd RPMHPD_CX>; 2007 operating-points-v2 = <&qup_opp_table>; 2008 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 2009 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 2010 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 2011 interconnect-names = "qup-core", 2012 "qup-config", 2013 "qup-memory"; 2014 #address-cells = <1>; 2015 #size-cells = <0>; 2016 status = "disabled"; 2017 }; 2018 2019 uart12: serial@a90000 { 2020 compatible = "qcom,geni-debug-uart"; 2021 reg = <0x0 0x00a90000 0x0 0x4000>; 2022 clock-names = "se"; 2023 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2024 pinctrl-names = "default"; 2025 pinctrl-0 = <&qup_uart12_default>; 2026 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2027 power-domains = <&rpmhpd RPMHPD_CX>; 2028 operating-points-v2 = <&qup_opp_table>; 2029 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 2030 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 2031 interconnect-names = "qup-core", 2032 "qup-config"; 2033 status = "disabled"; 2034 }; 2035 2036 i2c13: i2c@a94000 { 2037 compatible = "qcom,geni-i2c"; 2038 reg = <0 0x00a94000 0 0x4000>; 2039 clock-names = "se"; 2040 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2041 pinctrl-names = "default"; 2042 pinctrl-0 = <&qup_i2c13_default>; 2043 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2044 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 2045 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 2046 dma-names = "tx", "rx"; 2047 power-domains = <&rpmhpd RPMHPD_CX>; 2048 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 2049 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 2050 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 2051 interconnect-names = "qup-core", 2052 "qup-config", 2053 "qup-memory"; 2054 #address-cells = <1>; 2055 #size-cells = <0>; 2056 status = "disabled"; 2057 }; 2058 2059 spi13: spi@a94000 { 2060 compatible = "qcom,geni-spi"; 2061 reg = <0 0x00a94000 0 0x4000>; 2062 clock-names = "se"; 2063 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2064 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2065 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 2066 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 2067 dma-names = "tx", "rx"; 2068 power-domains = <&rpmhpd RPMHPD_CX>; 2069 operating-points-v2 = <&qup_opp_table>; 2070 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 2071 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 2072 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 2073 interconnect-names = "qup-core", 2074 "qup-config", 2075 "qup-memory"; 2076 #address-cells = <1>; 2077 #size-cells = <0>; 2078 status = "disabled"; 2079 }; 2080 }; 2081 2082 config_noc: interconnect@1500000 { 2083 compatible = "qcom,sm8250-config-noc"; 2084 reg = <0 0x01500000 0 0xa580>; 2085 #interconnect-cells = <2>; 2086 qcom,bcm-voters = <&apps_bcm_voter>; 2087 }; 2088 2089 system_noc: interconnect@1620000 { 2090 compatible = "qcom,sm8250-system-noc"; 2091 reg = <0 0x01620000 0 0x1c200>; 2092 #interconnect-cells = <2>; 2093 qcom,bcm-voters = <&apps_bcm_voter>; 2094 }; 2095 2096 mc_virt: interconnect@163d000 { 2097 compatible = "qcom,sm8250-mc-virt"; 2098 reg = <0 0x0163d000 0 0x1000>; 2099 #interconnect-cells = <2>; 2100 qcom,bcm-voters = <&apps_bcm_voter>; 2101 }; 2102 2103 aggre1_noc: interconnect@16e0000 { 2104 compatible = "qcom,sm8250-aggre1-noc"; 2105 reg = <0 0x016e0000 0 0x1f180>; 2106 #interconnect-cells = <2>; 2107 qcom,bcm-voters = <&apps_bcm_voter>; 2108 }; 2109 2110 aggre2_noc: interconnect@1700000 { 2111 compatible = "qcom,sm8250-aggre2-noc"; 2112 reg = <0 0x01700000 0 0x33000>; 2113 #interconnect-cells = <2>; 2114 qcom,bcm-voters = <&apps_bcm_voter>; 2115 }; 2116 2117 compute_noc: interconnect@1733000 { 2118 compatible = "qcom,sm8250-compute-noc"; 2119 reg = <0 0x01733000 0 0xa180>; 2120 #interconnect-cells = <2>; 2121 qcom,bcm-voters = <&apps_bcm_voter>; 2122 }; 2123 2124 mmss_noc: interconnect@1740000 { 2125 compatible = "qcom,sm8250-mmss-noc"; 2126 reg = <0 0x01740000 0 0x1f080>; 2127 #interconnect-cells = <2>; 2128 qcom,bcm-voters = <&apps_bcm_voter>; 2129 }; 2130 2131 pcie0: pcie@1c00000 { 2132 compatible = "qcom,pcie-sm8250"; 2133 reg = <0 0x01c00000 0 0x3000>, 2134 <0 0x60000000 0 0xf1d>, 2135 <0 0x60000f20 0 0xa8>, 2136 <0 0x60001000 0 0x1000>, 2137 <0 0x60100000 0 0x100000>, 2138 <0 0x01c03000 0 0x1000>; 2139 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2140 device_type = "pci"; 2141 linux,pci-domain = <0>; 2142 bus-range = <0x00 0xff>; 2143 num-lanes = <1>; 2144 2145 #address-cells = <3>; 2146 #size-cells = <2>; 2147 2148 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 2149 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 2150 2151 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2152 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2153 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2154 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2155 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2156 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2157 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2158 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2159 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2160 interrupt-names = "msi0", 2161 "msi1", 2162 "msi2", 2163 "msi3", 2164 "msi4", 2165 "msi5", 2166 "msi6", 2167 "msi7", 2168 "global"; 2169 #interrupt-cells = <1>; 2170 interrupt-map-mask = <0 0 0 0x7>; 2171 interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2172 <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2173 <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2174 <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2175 2176 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 2177 <&gcc GCC_PCIE_0_AUX_CLK>, 2178 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2179 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2180 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2181 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2182 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2183 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 2184 clock-names = "pipe", 2185 "aux", 2186 "cfg", 2187 "bus_master", 2188 "bus_slave", 2189 "slave_q2a", 2190 "tbu", 2191 "ddrss_sf_tbu"; 2192 2193 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 2194 <0x100 &apps_smmu 0x1c01 0x1>; 2195 2196 resets = <&gcc GCC_PCIE_0_BCR>; 2197 reset-names = "pci"; 2198 2199 power-domains = <&gcc PCIE_0_GDSC>; 2200 2201 phys = <&pcie0_phy>; 2202 phy-names = "pciephy"; 2203 2204 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; 2205 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; 2206 2207 pinctrl-names = "default"; 2208 pinctrl-0 = <&pcie0_default_state>; 2209 dma-coherent; 2210 2211 status = "disabled"; 2212 2213 pcieport0: pcie@0 { 2214 device_type = "pci"; 2215 reg = <0x0 0x0 0x0 0x0 0x0>; 2216 bus-range = <0x01 0xff>; 2217 2218 #address-cells = <3>; 2219 #size-cells = <2>; 2220 ranges; 2221 }; 2222 }; 2223 2224 pcie0_phy: phy@1c06000 { 2225 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; 2226 reg = <0 0x01c06000 0 0x1000>; 2227 2228 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2229 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2230 <&gcc GCC_PCIE_WIFI_CLKREF_EN>, 2231 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, 2232 <&gcc GCC_PCIE_0_PIPE_CLK>; 2233 clock-names = "aux", 2234 "cfg_ahb", 2235 "ref", 2236 "refgen", 2237 "pipe"; 2238 2239 clock-output-names = "pcie_0_pipe_clk"; 2240 #clock-cells = <0>; 2241 2242 #phy-cells = <0>; 2243 2244 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2245 reset-names = "phy"; 2246 2247 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 2248 assigned-clock-rates = <100000000>; 2249 2250 status = "disabled"; 2251 }; 2252 2253 pcie1: pcie@1c08000 { 2254 compatible = "qcom,pcie-sm8250"; 2255 reg = <0 0x01c08000 0 0x3000>, 2256 <0 0x40000000 0 0xf1d>, 2257 <0 0x40000f20 0 0xa8>, 2258 <0 0x40001000 0 0x1000>, 2259 <0 0x40100000 0 0x100000>, 2260 <0 0x01c0b000 0 0x1000>; 2261 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2262 device_type = "pci"; 2263 linux,pci-domain = <1>; 2264 bus-range = <0x00 0xff>; 2265 num-lanes = <2>; 2266 2267 #address-cells = <3>; 2268 #size-cells = <2>; 2269 2270 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2271 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2272 2273 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2274 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2275 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2276 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2277 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2278 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2279 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2280 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2281 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 2282 interrupt-names = "msi0", 2283 "msi1", 2284 "msi2", 2285 "msi3", 2286 "msi4", 2287 "msi5", 2288 "msi6", 2289 "msi7", 2290 "global"; 2291 #interrupt-cells = <1>; 2292 interrupt-map-mask = <0 0 0 0x7>; 2293 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2294 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2295 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2296 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2297 2298 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2299 <&gcc GCC_PCIE_1_AUX_CLK>, 2300 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2301 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2302 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2303 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2304 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 2305 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2306 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 2307 clock-names = "pipe", 2308 "aux", 2309 "cfg", 2310 "bus_master", 2311 "bus_slave", 2312 "slave_q2a", 2313 "ref", 2314 "tbu", 2315 "ddrss_sf_tbu"; 2316 2317 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2318 assigned-clock-rates = <19200000>; 2319 2320 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2321 <0x100 &apps_smmu 0x1c81 0x1>; 2322 2323 resets = <&gcc GCC_PCIE_1_BCR>; 2324 reset-names = "pci"; 2325 2326 power-domains = <&gcc PCIE_1_GDSC>; 2327 2328 phys = <&pcie1_phy>; 2329 phy-names = "pciephy"; 2330 2331 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; 2332 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>; 2333 2334 pinctrl-names = "default"; 2335 pinctrl-0 = <&pcie1_default_state>; 2336 dma-coherent; 2337 2338 status = "disabled"; 2339 2340 pcie@0 { 2341 device_type = "pci"; 2342 reg = <0x0 0x0 0x0 0x0 0x0>; 2343 bus-range = <0x01 0xff>; 2344 2345 #address-cells = <3>; 2346 #size-cells = <2>; 2347 ranges; 2348 }; 2349 }; 2350 2351 pcie1_phy: phy@1c0e000 { 2352 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2353 reg = <0 0x01c0e000 0 0x1000>; 2354 2355 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2356 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2357 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 2358 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, 2359 <&gcc GCC_PCIE_1_PIPE_CLK>; 2360 clock-names = "aux", 2361 "cfg_ahb", 2362 "ref", 2363 "refgen", 2364 "pipe"; 2365 2366 clock-output-names = "pcie_1_pipe_clk"; 2367 #clock-cells = <0>; 2368 2369 #phy-cells = <0>; 2370 2371 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2372 reset-names = "phy"; 2373 2374 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2375 assigned-clock-rates = <100000000>; 2376 2377 status = "disabled"; 2378 }; 2379 2380 pcie2: pcie@1c10000 { 2381 compatible = "qcom,pcie-sm8250"; 2382 reg = <0 0x01c10000 0 0x3000>, 2383 <0 0x64000000 0 0xf1d>, 2384 <0 0x64000f20 0 0xa8>, 2385 <0 0x64001000 0 0x1000>, 2386 <0 0x64100000 0 0x100000>, 2387 <0 0x01c13000 0 0x1000>; 2388 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2389 device_type = "pci"; 2390 linux,pci-domain = <2>; 2391 bus-range = <0x00 0xff>; 2392 num-lanes = <2>; 2393 2394 #address-cells = <3>; 2395 #size-cells = <2>; 2396 2397 ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>, 2398 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; 2399 2400 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, 2401 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2402 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2403 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2404 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 2405 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 2406 <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 2407 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 2408 <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 2409 interrupt-names = "msi0", 2410 "msi1", 2411 "msi2", 2412 "msi3", 2413 "msi4", 2414 "msi5", 2415 "msi6", 2416 "msi7", 2417 "global"; 2418 #interrupt-cells = <1>; 2419 interrupt-map-mask = <0 0 0 0x7>; 2420 interrupt-map = <0 0 0 1 &intc GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2421 <0 0 0 2 &intc GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2422 <0 0 0 3 &intc GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2423 <0 0 0 4 &intc GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2424 2425 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2426 <&gcc GCC_PCIE_2_AUX_CLK>, 2427 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2428 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2429 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 2430 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 2431 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2432 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2433 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 2434 clock-names = "pipe", 2435 "aux", 2436 "cfg", 2437 "bus_master", 2438 "bus_slave", 2439 "slave_q2a", 2440 "ref", 2441 "tbu", 2442 "ddrss_sf_tbu"; 2443 2444 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 2445 assigned-clock-rates = <19200000>; 2446 2447 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 2448 <0x100 &apps_smmu 0x1d01 0x1>; 2449 2450 resets = <&gcc GCC_PCIE_2_BCR>; 2451 reset-names = "pci"; 2452 2453 power-domains = <&gcc PCIE_2_GDSC>; 2454 2455 phys = <&pcie2_phy>; 2456 phy-names = "pciephy"; 2457 2458 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; 2459 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; 2460 2461 pinctrl-names = "default"; 2462 pinctrl-0 = <&pcie2_default_state>; 2463 dma-coherent; 2464 2465 status = "disabled"; 2466 2467 pcie@0 { 2468 device_type = "pci"; 2469 reg = <0x0 0x0 0x0 0x0 0x0>; 2470 bus-range = <0x01 0xff>; 2471 2472 #address-cells = <3>; 2473 #size-cells = <2>; 2474 ranges; 2475 }; 2476 }; 2477 2478 pcie2_phy: phy@1c16000 { 2479 compatible = "qcom,sm8250-qmp-modem-pcie-phy"; 2480 reg = <0 0x01c16000 0 0x1000>; 2481 2482 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2483 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2484 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2485 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>, 2486 <&gcc GCC_PCIE_2_PIPE_CLK>; 2487 clock-names = "aux", 2488 "cfg_ahb", 2489 "ref", 2490 "refgen", 2491 "pipe"; 2492 2493 clock-output-names = "pcie_2_pipe_clk"; 2494 #clock-cells = <0>; 2495 2496 #phy-cells = <0>; 2497 2498 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 2499 reset-names = "phy"; 2500 2501 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2502 assigned-clock-rates = <100000000>; 2503 2504 status = "disabled"; 2505 }; 2506 2507 ufs_mem_hc: ufshc@1d84000 { 2508 compatible = "qcom,sm8250-ufshc", "qcom,ufshc", 2509 "jedec,ufs-2.0"; 2510 reg = <0 0x01d84000 0 0x3000>; 2511 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2512 phys = <&ufs_mem_phy>; 2513 phy-names = "ufsphy"; 2514 lanes-per-direction = <2>; 2515 #reset-cells = <1>; 2516 resets = <&gcc GCC_UFS_PHY_BCR>; 2517 reset-names = "rst"; 2518 2519 power-domains = <&gcc UFS_PHY_GDSC>; 2520 2521 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; 2522 2523 clock-names = 2524 "core_clk", 2525 "bus_aggr_clk", 2526 "iface_clk", 2527 "core_clk_unipro", 2528 "ref_clk", 2529 "tx_lane0_sync_clk", 2530 "rx_lane0_sync_clk", 2531 "rx_lane1_sync_clk"; 2532 clocks = 2533 <&gcc GCC_UFS_PHY_AXI_CLK>, 2534 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2535 <&gcc GCC_UFS_PHY_AHB_CLK>, 2536 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2537 <&rpmhcc RPMH_CXO_CLK>, 2538 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2539 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2540 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2541 2542 operating-points-v2 = <&ufs_opp_table>; 2543 2544 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI_CH0 0>, 2545 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 2546 interconnect-names = "ufs-ddr", "cpu-ufs"; 2547 2548 status = "disabled"; 2549 2550 ufs_opp_table: opp-table { 2551 compatible = "operating-points-v2"; 2552 2553 opp-37500000 { 2554 opp-hz = /bits/ 64 <37500000>, 2555 /bits/ 64 <0>, 2556 /bits/ 64 <0>, 2557 /bits/ 64 <37500000>, 2558 /bits/ 64 <0>, 2559 /bits/ 64 <0>, 2560 /bits/ 64 <0>, 2561 /bits/ 64 <0>; 2562 required-opps = <&rpmhpd_opp_low_svs>; 2563 }; 2564 2565 opp-300000000 { 2566 opp-hz = /bits/ 64 <300000000>, 2567 /bits/ 64 <0>, 2568 /bits/ 64 <0>, 2569 /bits/ 64 <300000000>, 2570 /bits/ 64 <0>, 2571 /bits/ 64 <0>, 2572 /bits/ 64 <0>, 2573 /bits/ 64 <0>; 2574 required-opps = <&rpmhpd_opp_nom>; 2575 }; 2576 }; 2577 }; 2578 2579 ufs_mem_phy: phy@1d87000 { 2580 compatible = "qcom,sm8250-qmp-ufs-phy"; 2581 reg = <0 0x01d87000 0 0x1000>; 2582 2583 clocks = <&rpmhcc RPMH_CXO_CLK>, 2584 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2585 <&gcc GCC_UFS_1X_CLKREF_EN>; 2586 clock-names = "ref", 2587 "ref_aux", 2588 "qref"; 2589 2590 resets = <&ufs_mem_hc 0>; 2591 reset-names = "ufsphy"; 2592 2593 power-domains = <&gcc UFS_PHY_GDSC>; 2594 2595 #phy-cells = <0>; 2596 2597 status = "disabled"; 2598 }; 2599 2600 cryptobam: dma-controller@1dc4000 { 2601 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2602 reg = <0 0x01dc4000 0 0x24000>; 2603 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2604 #dma-cells = <1>; 2605 qcom,ee = <0>; 2606 qcom,controlled-remotely; 2607 num-channels = <8>; 2608 qcom,num-ees = <2>; 2609 iommus = <&apps_smmu 0x592 0x0000>, 2610 <&apps_smmu 0x598 0x0000>, 2611 <&apps_smmu 0x599 0x0000>, 2612 <&apps_smmu 0x59f 0x0000>, 2613 <&apps_smmu 0x586 0x0011>, 2614 <&apps_smmu 0x596 0x0011>; 2615 }; 2616 2617 crypto: crypto@1dfa000 { 2618 compatible = "qcom,sm8250-qce", "qcom,sm8150-qce", "qcom,qce"; 2619 reg = <0 0x01dfa000 0 0x6000>; 2620 dmas = <&cryptobam 4>, <&cryptobam 5>; 2621 dma-names = "rx", "tx"; 2622 iommus = <&apps_smmu 0x592 0x0000>, 2623 <&apps_smmu 0x598 0x0000>, 2624 <&apps_smmu 0x599 0x0000>, 2625 <&apps_smmu 0x59f 0x0000>, 2626 <&apps_smmu 0x586 0x0011>, 2627 <&apps_smmu 0x596 0x0011>; 2628 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>; 2629 interconnect-names = "memory"; 2630 }; 2631 2632 tcsr_mutex: hwlock@1f40000 { 2633 compatible = "qcom,tcsr-mutex"; 2634 reg = <0x0 0x01f40000 0x0 0x40000>; 2635 #hwlock-cells = <1>; 2636 }; 2637 2638 tcsr: syscon@1fc0000 { 2639 compatible = "qcom,sm8250-tcsr", "syscon"; 2640 reg = <0x0 0x1fc0000 0x0 0x30000>; 2641 }; 2642 2643 wsamacro: codec@3240000 { 2644 compatible = "qcom,sm8250-lpass-wsa-macro"; 2645 reg = <0 0x03240000 0 0x1000>; 2646 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2647 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2648 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2649 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2650 <&vamacro>; 2651 2652 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2653 2654 #clock-cells = <0>; 2655 clock-output-names = "mclk"; 2656 #sound-dai-cells = <1>; 2657 2658 pinctrl-names = "default"; 2659 pinctrl-0 = <&wsa_swr_active>; 2660 2661 status = "disabled"; 2662 }; 2663 2664 swr0: soundwire@3250000 { 2665 reg = <0 0x03250000 0 0x2000>; 2666 compatible = "qcom,soundwire-v1.5.1"; 2667 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 2668 clocks = <&wsamacro>; 2669 clock-names = "iface"; 2670 2671 qcom,din-ports = <2>; 2672 qcom,dout-ports = <6>; 2673 2674 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2675 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2676 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2677 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; 2678 2679 #sound-dai-cells = <1>; 2680 #address-cells = <2>; 2681 #size-cells = <0>; 2682 2683 status = "disabled"; 2684 }; 2685 2686 vamacro: codec@3370000 { 2687 compatible = "qcom,sm8250-lpass-va-macro"; 2688 reg = <0 0x03370000 0 0x1000>; 2689 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2690 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2691 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2692 2693 clock-names = "mclk", "macro", "dcodec"; 2694 2695 #clock-cells = <0>; 2696 clock-output-names = "fsgen"; 2697 #sound-dai-cells = <1>; 2698 }; 2699 2700 rxmacro: rxmacro@3200000 { 2701 pinctrl-names = "default"; 2702 pinctrl-0 = <&rx_swr_active>; 2703 compatible = "qcom,sm8250-lpass-rx-macro"; 2704 reg = <0 0x03200000 0 0x1000>; 2705 status = "disabled"; 2706 2707 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2708 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2709 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2710 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2711 <&vamacro>; 2712 2713 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2714 2715 #clock-cells = <0>; 2716 clock-output-names = "mclk"; 2717 #sound-dai-cells = <1>; 2718 }; 2719 2720 swr1: soundwire@3210000 { 2721 reg = <0 0x03210000 0 0x2000>; 2722 compatible = "qcom,soundwire-v1.5.1"; 2723 status = "disabled"; 2724 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 2725 clocks = <&rxmacro>; 2726 clock-names = "iface"; 2727 label = "RX"; 2728 qcom,din-ports = <0>; 2729 qcom,dout-ports = <5>; 2730 2731 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2732 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; 2733 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2734 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2735 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2736 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2737 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2738 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2739 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2740 2741 #sound-dai-cells = <1>; 2742 #address-cells = <2>; 2743 #size-cells = <0>; 2744 }; 2745 2746 txmacro: txmacro@3220000 { 2747 pinctrl-names = "default"; 2748 pinctrl-0 = <&tx_swr_active>; 2749 compatible = "qcom,sm8250-lpass-tx-macro"; 2750 reg = <0 0x03220000 0 0x1000>; 2751 status = "disabled"; 2752 2753 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2754 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2755 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2756 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2757 <&vamacro>; 2758 2759 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2760 2761 #clock-cells = <0>; 2762 clock-output-names = "mclk"; 2763 #sound-dai-cells = <1>; 2764 }; 2765 2766 /* tx macro */ 2767 swr2: soundwire@3230000 { 2768 reg = <0 0x03230000 0 0x2000>; 2769 compatible = "qcom,soundwire-v1.5.1"; 2770 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 2771 interrupt-names = "core"; 2772 status = "disabled"; 2773 2774 clocks = <&txmacro>; 2775 clock-names = "iface"; 2776 label = "TX"; 2777 2778 qcom,din-ports = <5>; 2779 qcom,dout-ports = <0>; 2780 qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>; 2781 qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>; 2782 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>; 2783 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2784 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2785 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2786 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2787 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2788 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>; 2789 #sound-dai-cells = <1>; 2790 #address-cells = <2>; 2791 #size-cells = <0>; 2792 }; 2793 2794 lpass_tlmm: pinctrl@33c0000 { 2795 compatible = "qcom,sm8250-lpass-lpi-pinctrl"; 2796 reg = <0 0x033c0000 0x0 0x20000>, 2797 <0 0x03550000 0x0 0x10000>; 2798 gpio-controller; 2799 #gpio-cells = <2>; 2800 gpio-ranges = <&lpass_tlmm 0 0 14>; 2801 2802 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2803 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2804 clock-names = "core", "audio"; 2805 2806 wsa_swr_active: wsa-swr-active-state { 2807 clk-pins { 2808 pins = "gpio10"; 2809 function = "wsa_swr_clk"; 2810 drive-strength = <2>; 2811 slew-rate = <1>; 2812 bias-disable; 2813 }; 2814 2815 data-pins { 2816 pins = "gpio11"; 2817 function = "wsa_swr_data"; 2818 drive-strength = <2>; 2819 slew-rate = <1>; 2820 bias-bus-hold; 2821 }; 2822 }; 2823 2824 wsa_swr_sleep: wsa-swr-sleep-state { 2825 clk-pins { 2826 pins = "gpio10"; 2827 function = "wsa_swr_clk"; 2828 drive-strength = <2>; 2829 bias-pull-down; 2830 }; 2831 2832 data-pins { 2833 pins = "gpio11"; 2834 function = "wsa_swr_data"; 2835 drive-strength = <2>; 2836 bias-pull-down; 2837 }; 2838 }; 2839 2840 dmic01_active: dmic01-active-state { 2841 clk-pins { 2842 pins = "gpio6"; 2843 function = "dmic1_clk"; 2844 drive-strength = <8>; 2845 output-high; 2846 }; 2847 data-pins { 2848 pins = "gpio7"; 2849 function = "dmic1_data"; 2850 drive-strength = <8>; 2851 }; 2852 }; 2853 2854 dmic01_sleep: dmic01-sleep-state { 2855 clk-pins { 2856 pins = "gpio6"; 2857 function = "dmic1_clk"; 2858 drive-strength = <2>; 2859 bias-disable; 2860 output-low; 2861 }; 2862 2863 data-pins { 2864 pins = "gpio7"; 2865 function = "dmic1_data"; 2866 drive-strength = <2>; 2867 bias-pull-down; 2868 }; 2869 }; 2870 2871 rx_swr_active: rx-swr-active-state { 2872 clk-pins { 2873 pins = "gpio3"; 2874 function = "swr_rx_clk"; 2875 drive-strength = <2>; 2876 slew-rate = <1>; 2877 bias-disable; 2878 }; 2879 2880 data-pins { 2881 pins = "gpio4", "gpio5"; 2882 function = "swr_rx_data"; 2883 drive-strength = <2>; 2884 slew-rate = <1>; 2885 bias-bus-hold; 2886 }; 2887 }; 2888 2889 tx_swr_active: tx-swr-active-state { 2890 clk-pins { 2891 pins = "gpio0"; 2892 function = "swr_tx_clk"; 2893 drive-strength = <2>; 2894 slew-rate = <1>; 2895 bias-disable; 2896 }; 2897 2898 data-pins { 2899 pins = "gpio1", "gpio2"; 2900 function = "swr_tx_data"; 2901 drive-strength = <2>; 2902 slew-rate = <1>; 2903 bias-bus-hold; 2904 }; 2905 }; 2906 2907 tx_swr_sleep: tx-swr-sleep-state { 2908 clk-pins { 2909 pins = "gpio0"; 2910 function = "swr_tx_clk"; 2911 drive-strength = <2>; 2912 bias-pull-down; 2913 }; 2914 2915 data1-pins { 2916 pins = "gpio1"; 2917 function = "swr_tx_data"; 2918 drive-strength = <2>; 2919 bias-bus-hold; 2920 }; 2921 2922 data2-pins { 2923 pins = "gpio2"; 2924 function = "swr_tx_data"; 2925 drive-strength = <2>; 2926 bias-pull-down; 2927 }; 2928 }; 2929 }; 2930 2931 gpu: gpu@3d00000 { 2932 compatible = "qcom,adreno-650.2", 2933 "qcom,adreno"; 2934 2935 reg = <0 0x03d00000 0 0x40000>; 2936 reg-names = "kgsl_3d0_reg_memory"; 2937 2938 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2939 2940 iommus = <&adreno_smmu 0 0x401>; 2941 2942 operating-points-v2 = <&gpu_opp_table>; 2943 2944 qcom,gmu = <&gmu>; 2945 2946 nvmem-cells = <&gpu_speed_bin>; 2947 nvmem-cell-names = "speed_bin"; 2948 #cooling-cells = <2>; 2949 2950 status = "disabled"; 2951 2952 gpu_zap_shader: zap-shader { 2953 memory-region = <&gpu_mem>; 2954 }; 2955 2956 gpu_opp_table: opp-table { 2957 compatible = "operating-points-v2"; 2958 2959 opp-670000000 { 2960 opp-hz = /bits/ 64 <670000000>; 2961 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2962 opp-supported-hw = <0xa>; 2963 }; 2964 2965 opp-587000000 { 2966 opp-hz = /bits/ 64 <587000000>; 2967 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2968 opp-supported-hw = <0xb>; 2969 }; 2970 2971 opp-525000000 { 2972 opp-hz = /bits/ 64 <525000000>; 2973 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2974 opp-supported-hw = <0xf>; 2975 }; 2976 2977 opp-490000000 { 2978 opp-hz = /bits/ 64 <490000000>; 2979 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2980 opp-supported-hw = <0xf>; 2981 }; 2982 2983 opp-441600000 { 2984 opp-hz = /bits/ 64 <441600000>; 2985 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2986 opp-supported-hw = <0xf>; 2987 }; 2988 2989 opp-400000000 { 2990 opp-hz = /bits/ 64 <400000000>; 2991 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2992 opp-supported-hw = <0xf>; 2993 }; 2994 2995 opp-305000000 { 2996 opp-hz = /bits/ 64 <305000000>; 2997 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2998 opp-supported-hw = <0xf>; 2999 }; 3000 }; 3001 }; 3002 3003 gmu: gmu@3d6a000 { 3004 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; 3005 3006 reg = <0 0x03d6a000 0 0x30000>, 3007 <0 0x3de0000 0 0x10000>, 3008 <0 0xb290000 0 0x10000>, 3009 <0 0xb490000 0 0x10000>; 3010 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; 3011 3012 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 3013 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 3014 interrupt-names = "hfi", "gmu"; 3015 3016 clocks = <&gpucc GPU_CC_AHB_CLK>, 3017 <&gpucc GPU_CC_CX_GMU_CLK>, 3018 <&gpucc GPU_CC_CXO_CLK>, 3019 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 3020 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 3021 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 3022 3023 power-domains = <&gpucc GPU_CX_GDSC>, 3024 <&gpucc GPU_GX_GDSC>; 3025 power-domain-names = "cx", "gx"; 3026 3027 iommus = <&adreno_smmu 5 0x400>; 3028 3029 operating-points-v2 = <&gmu_opp_table>; 3030 3031 status = "disabled"; 3032 3033 gmu_opp_table: opp-table { 3034 compatible = "operating-points-v2"; 3035 3036 opp-200000000 { 3037 opp-hz = /bits/ 64 <200000000>; 3038 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3039 }; 3040 }; 3041 }; 3042 3043 gpucc: clock-controller@3d90000 { 3044 compatible = "qcom,sm8250-gpucc"; 3045 reg = <0 0x03d90000 0 0x9000>; 3046 clocks = <&rpmhcc RPMH_CXO_CLK>, 3047 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3048 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3049 clock-names = "bi_tcxo", 3050 "gcc_gpu_gpll0_clk_src", 3051 "gcc_gpu_gpll0_div_clk_src"; 3052 #clock-cells = <1>; 3053 #reset-cells = <1>; 3054 #power-domain-cells = <1>; 3055 }; 3056 3057 adreno_smmu: iommu@3da0000 { 3058 compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu", 3059 "qcom,smmu-500", "arm,mmu-500"; 3060 reg = <0 0x03da0000 0 0x10000>; 3061 #iommu-cells = <2>; 3062 #global-interrupts = <2>; 3063 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 3064 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 3065 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 3066 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 3067 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 3068 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 3069 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 3070 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 3071 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 3072 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; 3073 clocks = <&gpucc GPU_CC_AHB_CLK>, 3074 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3075 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 3076 clock-names = "ahb", "bus", "iface"; 3077 3078 power-domains = <&gpucc GPU_CX_GDSC>; 3079 dma-coherent; 3080 }; 3081 3082 slpi: remoteproc@5c00000 { 3083 compatible = "qcom,sm8250-slpi-pas"; 3084 reg = <0 0x05c00000 0 0x4000>; 3085 3086 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 3087 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 3088 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 3089 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 3090 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 3091 interrupt-names = "wdog", "fatal", "ready", 3092 "handover", "stop-ack"; 3093 3094 clocks = <&rpmhcc RPMH_CXO_CLK>; 3095 clock-names = "xo"; 3096 3097 power-domains = <&rpmhpd RPMHPD_LCX>, 3098 <&rpmhpd RPMHPD_LMX>; 3099 power-domain-names = "lcx", "lmx"; 3100 3101 memory-region = <&slpi_mem>; 3102 3103 qcom,qmp = <&aoss_qmp>; 3104 3105 qcom,smem-states = <&smp2p_slpi_out 0>; 3106 qcom,smem-state-names = "stop"; 3107 3108 status = "disabled"; 3109 3110 glink-edge { 3111 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 3112 IPCC_MPROC_SIGNAL_GLINK_QMP 3113 IRQ_TYPE_EDGE_RISING>; 3114 mboxes = <&ipcc IPCC_CLIENT_SLPI 3115 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3116 3117 label = "slpi"; 3118 qcom,remote-pid = <3>; 3119 3120 fastrpc { 3121 compatible = "qcom,fastrpc"; 3122 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3123 label = "sdsp"; 3124 qcom,non-secure-domain; 3125 #address-cells = <1>; 3126 #size-cells = <0>; 3127 3128 compute-cb@1 { 3129 compatible = "qcom,fastrpc-compute-cb"; 3130 reg = <1>; 3131 iommus = <&apps_smmu 0x0541 0x0>; 3132 }; 3133 3134 compute-cb@2 { 3135 compatible = "qcom,fastrpc-compute-cb"; 3136 reg = <2>; 3137 iommus = <&apps_smmu 0x0542 0x0>; 3138 }; 3139 3140 compute-cb@3 { 3141 compatible = "qcom,fastrpc-compute-cb"; 3142 reg = <3>; 3143 iommus = <&apps_smmu 0x0543 0x0>; 3144 /* note: shared-cb = <4> in downstream */ 3145 }; 3146 }; 3147 }; 3148 }; 3149 3150 stm@6002000 { 3151 compatible = "arm,coresight-stm", "arm,primecell"; 3152 reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>; 3153 reg-names = "stm-base", "stm-stimulus-base"; 3154 3155 clocks = <&aoss_qmp>; 3156 clock-names = "apb_pclk"; 3157 3158 out-ports { 3159 port { 3160 stm_out: endpoint { 3161 remote-endpoint = <&funnel0_in7>; 3162 }; 3163 }; 3164 }; 3165 }; 3166 3167 tpda@6004000 { 3168 compatible = "qcom,coresight-tpda", "arm,primecell"; 3169 reg = <0 0x06004000 0 0x1000>; 3170 3171 clocks = <&aoss_qmp>; 3172 clock-names = "apb_pclk"; 3173 3174 out-ports { 3175 3176 port { 3177 tpda_out_funnel_qatb: endpoint { 3178 remote-endpoint = <&funnel_qatb_in_tpda>; 3179 }; 3180 }; 3181 }; 3182 3183 in-ports { 3184 #address-cells = <1>; 3185 #size-cells = <0>; 3186 3187 port@9 { 3188 reg = <9>; 3189 tpda_9_in_tpdm_mm: endpoint { 3190 remote-endpoint = <&tpdm_mm_out_tpda9>; 3191 }; 3192 }; 3193 3194 port@17 { 3195 reg = <23>; 3196 tpda_23_in_tpdm_prng: endpoint { 3197 remote-endpoint = <&tpdm_prng_out_tpda_23>; 3198 }; 3199 }; 3200 }; 3201 }; 3202 3203 funnel@6005000 { 3204 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3205 reg = <0 0x06005000 0 0x1000>; 3206 3207 clocks = <&aoss_qmp>; 3208 clock-names = "apb_pclk"; 3209 3210 out-ports { 3211 port { 3212 funnel_qatb_out_funnel_in0: endpoint { 3213 remote-endpoint = <&funnel_in0_in_funnel_qatb>; 3214 }; 3215 }; 3216 }; 3217 3218 in-ports { 3219 port { 3220 funnel_qatb_in_tpda: endpoint { 3221 remote-endpoint = <&tpda_out_funnel_qatb>; 3222 }; 3223 }; 3224 }; 3225 }; 3226 3227 funnel@6041000 { 3228 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3229 reg = <0 0x06041000 0 0x1000>; 3230 3231 clocks = <&aoss_qmp>; 3232 clock-names = "apb_pclk"; 3233 3234 out-ports { 3235 port { 3236 funnel_in0_out_funnel_merg: endpoint { 3237 remote-endpoint = <&funnel_merg_in_funnel_in0>; 3238 }; 3239 }; 3240 }; 3241 3242 in-ports { 3243 #address-cells = <1>; 3244 #size-cells = <0>; 3245 3246 port@6 { 3247 reg = <6>; 3248 funnel_in0_in_funnel_qatb: endpoint { 3249 remote-endpoint = <&funnel_qatb_out_funnel_in0>; 3250 }; 3251 }; 3252 3253 port@7 { 3254 reg = <7>; 3255 funnel0_in7: endpoint { 3256 remote-endpoint = <&stm_out>; 3257 }; 3258 }; 3259 }; 3260 }; 3261 3262 funnel@6042000 { 3263 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3264 reg = <0 0x06042000 0 0x1000>; 3265 3266 clocks = <&aoss_qmp>; 3267 clock-names = "apb_pclk"; 3268 3269 out-ports { 3270 port { 3271 funnel_in1_out_funnel_merg: endpoint { 3272 remote-endpoint = <&funnel_merg_in_funnel_in1>; 3273 }; 3274 }; 3275 }; 3276 3277 in-ports { 3278 #address-cells = <1>; 3279 #size-cells = <0>; 3280 3281 port@4 { 3282 reg = <4>; 3283 funnel_in1_in_funnel_apss_merg: endpoint { 3284 remote-endpoint = <&funnel_apss_merg_out_funnel_in1>; 3285 }; 3286 }; 3287 }; 3288 }; 3289 3290 funnel@6045000 { 3291 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3292 reg = <0 0x06045000 0 0x1000>; 3293 3294 clocks = <&aoss_qmp>; 3295 clock-names = "apb_pclk"; 3296 3297 out-ports { 3298 port { 3299 funnel_merg_out_funnel_swao: endpoint { 3300 remote-endpoint = <&funnel_swao_in_funnel_merg>; 3301 }; 3302 }; 3303 }; 3304 3305 in-ports { 3306 #address-cells = <1>; 3307 #size-cells = <0>; 3308 3309 port@0 { 3310 reg = <0>; 3311 funnel_merg_in_funnel_in0: endpoint { 3312 remote-endpoint = <&funnel_in0_out_funnel_merg>; 3313 }; 3314 }; 3315 3316 port@1 { 3317 reg = <1>; 3318 funnel_merg_in_funnel_in1: endpoint { 3319 remote-endpoint = <&funnel_in1_out_funnel_merg>; 3320 }; 3321 }; 3322 }; 3323 }; 3324 3325 replicator@6046000 { 3326 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3327 reg = <0 0x06046000 0 0x1000>; 3328 3329 clocks = <&aoss_qmp>; 3330 clock-names = "apb_pclk"; 3331 3332 out-ports { 3333 port { 3334 replicator_out: endpoint { 3335 remote-endpoint = <&etr_in>; 3336 }; 3337 }; 3338 }; 3339 3340 in-ports { 3341 port { 3342 replicator_cx_in_swao_out: endpoint { 3343 remote-endpoint = <&replicator_swao_out_cx_in>; 3344 }; 3345 }; 3346 }; 3347 }; 3348 3349 etr@6048000 { 3350 compatible = "arm,coresight-tmc", "arm,primecell"; 3351 reg = <0 0x06048000 0 0x1000>; 3352 3353 clocks = <&aoss_qmp>; 3354 clock-names = "apb_pclk"; 3355 arm,scatter-gather; 3356 3357 in-ports { 3358 port { 3359 etr_in: endpoint { 3360 remote-endpoint = <&replicator_out>; 3361 }; 3362 }; 3363 }; 3364 }; 3365 3366 tpdm@684c000 { 3367 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3368 reg = <0 0x0684c000 0 0x1000>; 3369 3370 clocks = <&aoss_qmp>; 3371 clock-names = "apb_pclk"; 3372 3373 out-ports { 3374 port { 3375 tpdm_prng_out_tpda_23: endpoint { 3376 remote-endpoint = <&tpda_23_in_tpdm_prng>; 3377 }; 3378 }; 3379 }; 3380 }; 3381 3382 funnel@6b04000 { 3383 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3384 arm,primecell-periphid = <0x000bb908>; 3385 3386 reg = <0 0x06b04000 0 0x1000>; 3387 3388 clocks = <&aoss_qmp>; 3389 clock-names = "apb_pclk"; 3390 3391 out-ports { 3392 port { 3393 funnel_swao_out_etf: endpoint { 3394 remote-endpoint = <&etf_in_funnel_swao_out>; 3395 }; 3396 }; 3397 }; 3398 3399 in-ports { 3400 #address-cells = <1>; 3401 #size-cells = <0>; 3402 3403 port@7 { 3404 reg = <7>; 3405 funnel_swao_in_funnel_merg: endpoint { 3406 remote-endpoint = <&funnel_merg_out_funnel_swao>; 3407 }; 3408 }; 3409 }; 3410 }; 3411 3412 etf@6b05000 { 3413 compatible = "arm,coresight-tmc", "arm,primecell"; 3414 reg = <0 0x06b05000 0 0x1000>; 3415 3416 clocks = <&aoss_qmp>; 3417 clock-names = "apb_pclk"; 3418 3419 out-ports { 3420 port { 3421 etf_out: endpoint { 3422 remote-endpoint = <&replicator_in>; 3423 }; 3424 }; 3425 }; 3426 3427 in-ports { 3428 3429 port { 3430 etf_in_funnel_swao_out: endpoint { 3431 remote-endpoint = <&funnel_swao_out_etf>; 3432 }; 3433 }; 3434 }; 3435 }; 3436 3437 replicator@6b06000 { 3438 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3439 reg = <0 0x06b06000 0 0x1000>; 3440 3441 clocks = <&aoss_qmp>; 3442 clock-names = "apb_pclk"; 3443 3444 out-ports { 3445 port { 3446 replicator_swao_out_cx_in: endpoint { 3447 remote-endpoint = <&replicator_cx_in_swao_out>; 3448 }; 3449 }; 3450 }; 3451 3452 in-ports { 3453 port { 3454 replicator_in: endpoint { 3455 remote-endpoint = <&etf_out>; 3456 }; 3457 }; 3458 }; 3459 }; 3460 3461 tpdm@6c08000 { 3462 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3463 reg = <0 0x06c08000 0 0x1000>; 3464 3465 clocks = <&aoss_qmp>; 3466 clock-names = "apb_pclk"; 3467 3468 out-ports { 3469 port { 3470 tpdm_mm_out_funnel_dl_mm: endpoint { 3471 remote-endpoint = <&funnel_dl_mm_in_tpdm_mm>; 3472 }; 3473 }; 3474 }; 3475 }; 3476 3477 funnel@6c0b000 { 3478 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3479 reg = <0 0x06c0b000 0 0x1000>; 3480 3481 clocks = <&aoss_qmp>; 3482 clock-names = "apb_pclk"; 3483 3484 out-ports { 3485 port { 3486 funnel_dl_mm_out_funnel_dl_center: endpoint { 3487 remote-endpoint = <&funnel_dl_center_in_funnel_dl_mm>; 3488 }; 3489 }; 3490 }; 3491 3492 in-ports { 3493 #address-cells = <1>; 3494 #size-cells = <0>; 3495 3496 port@3 { 3497 reg = <3>; 3498 funnel_dl_mm_in_tpdm_mm: endpoint { 3499 remote-endpoint = <&tpdm_mm_out_funnel_dl_mm>; 3500 }; 3501 }; 3502 }; 3503 }; 3504 3505 funnel@6c2d000 { 3506 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3507 reg = <0 0x06c2d000 0 0x1000>; 3508 3509 clocks = <&aoss_qmp>; 3510 clock-names = "apb_pclk"; 3511 3512 out-ports { 3513 port { 3514 tpdm_mm_out_tpda9: endpoint { 3515 remote-endpoint = <&tpda_9_in_tpdm_mm>; 3516 }; 3517 }; 3518 }; 3519 3520 in-ports { 3521 #address-cells = <1>; 3522 #size-cells = <0>; 3523 3524 port@2 { 3525 reg = <2>; 3526 funnel_dl_center_in_funnel_dl_mm: endpoint { 3527 remote-endpoint = <&funnel_dl_mm_out_funnel_dl_center>; 3528 }; 3529 }; 3530 }; 3531 }; 3532 3533 etm@7040000 { 3534 compatible = "arm,coresight-etm4x", "arm,primecell"; 3535 reg = <0 0x07040000 0 0x1000>; 3536 3537 cpu = <&cpu0>; 3538 3539 clocks = <&aoss_qmp>; 3540 clock-names = "apb_pclk"; 3541 arm,coresight-loses-context-with-cpu; 3542 3543 out-ports { 3544 port { 3545 etm0_out: endpoint { 3546 remote-endpoint = <&apss_funnel_in0>; 3547 }; 3548 }; 3549 }; 3550 }; 3551 3552 etm@7140000 { 3553 compatible = "arm,coresight-etm4x", "arm,primecell"; 3554 reg = <0 0x07140000 0 0x1000>; 3555 3556 cpu = <&cpu1>; 3557 3558 clocks = <&aoss_qmp>; 3559 clock-names = "apb_pclk"; 3560 arm,coresight-loses-context-with-cpu; 3561 3562 out-ports { 3563 port { 3564 etm1_out: endpoint { 3565 remote-endpoint = <&apss_funnel_in1>; 3566 }; 3567 }; 3568 }; 3569 }; 3570 3571 etm@7240000 { 3572 compatible = "arm,coresight-etm4x", "arm,primecell"; 3573 reg = <0 0x07240000 0 0x1000>; 3574 3575 cpu = <&cpu2>; 3576 3577 clocks = <&aoss_qmp>; 3578 clock-names = "apb_pclk"; 3579 arm,coresight-loses-context-with-cpu; 3580 3581 out-ports { 3582 port { 3583 etm2_out: endpoint { 3584 remote-endpoint = <&apss_funnel_in2>; 3585 }; 3586 }; 3587 }; 3588 }; 3589 3590 etm@7340000 { 3591 compatible = "arm,coresight-etm4x", "arm,primecell"; 3592 reg = <0 0x07340000 0 0x1000>; 3593 3594 cpu = <&cpu3>; 3595 3596 clocks = <&aoss_qmp>; 3597 clock-names = "apb_pclk"; 3598 arm,coresight-loses-context-with-cpu; 3599 3600 out-ports { 3601 port { 3602 etm3_out: endpoint { 3603 remote-endpoint = <&apss_funnel_in3>; 3604 }; 3605 }; 3606 }; 3607 }; 3608 3609 etm@7440000 { 3610 compatible = "arm,coresight-etm4x", "arm,primecell"; 3611 reg = <0 0x07440000 0 0x1000>; 3612 3613 cpu = <&cpu4>; 3614 3615 clocks = <&aoss_qmp>; 3616 clock-names = "apb_pclk"; 3617 arm,coresight-loses-context-with-cpu; 3618 3619 out-ports { 3620 port { 3621 etm4_out: endpoint { 3622 remote-endpoint = <&apss_funnel_in4>; 3623 }; 3624 }; 3625 }; 3626 }; 3627 3628 etm@7540000 { 3629 compatible = "arm,coresight-etm4x", "arm,primecell"; 3630 reg = <0 0x07540000 0 0x1000>; 3631 3632 cpu = <&cpu5>; 3633 3634 clocks = <&aoss_qmp>; 3635 clock-names = "apb_pclk"; 3636 arm,coresight-loses-context-with-cpu; 3637 3638 out-ports { 3639 port { 3640 etm5_out: endpoint { 3641 remote-endpoint = <&apss_funnel_in5>; 3642 }; 3643 }; 3644 }; 3645 }; 3646 3647 etm@7640000 { 3648 compatible = "arm,coresight-etm4x", "arm,primecell"; 3649 reg = <0 0x07640000 0 0x1000>; 3650 3651 cpu = <&cpu6>; 3652 3653 clocks = <&aoss_qmp>; 3654 clock-names = "apb_pclk"; 3655 arm,coresight-loses-context-with-cpu; 3656 3657 out-ports { 3658 port { 3659 etm6_out: endpoint { 3660 remote-endpoint = <&apss_funnel_in6>; 3661 }; 3662 }; 3663 }; 3664 }; 3665 3666 etm@7740000 { 3667 compatible = "arm,coresight-etm4x", "arm,primecell"; 3668 reg = <0 0x07740000 0 0x1000>; 3669 3670 cpu = <&cpu7>; 3671 3672 clocks = <&aoss_qmp>; 3673 clock-names = "apb_pclk"; 3674 arm,coresight-loses-context-with-cpu; 3675 3676 out-ports { 3677 port { 3678 etm7_out: endpoint { 3679 remote-endpoint = <&apss_funnel_in7>; 3680 }; 3681 }; 3682 }; 3683 }; 3684 3685 funnel@7800000 { 3686 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3687 reg = <0 0x07800000 0 0x1000>; 3688 3689 clocks = <&aoss_qmp>; 3690 clock-names = "apb_pclk"; 3691 3692 out-ports { 3693 port { 3694 funnel_apss_out_funnel_apss_merg: endpoint { 3695 remote-endpoint = <&funnel_apss_merg_in_funnel_apss>; 3696 }; 3697 }; 3698 }; 3699 3700 in-ports { 3701 #address-cells = <1>; 3702 #size-cells = <0>; 3703 3704 port@0 { 3705 reg = <0>; 3706 apss_funnel_in0: endpoint { 3707 remote-endpoint = <&etm0_out>; 3708 }; 3709 }; 3710 3711 port@1 { 3712 reg = <1>; 3713 apss_funnel_in1: endpoint { 3714 remote-endpoint = <&etm1_out>; 3715 }; 3716 }; 3717 3718 port@2 { 3719 reg = <2>; 3720 apss_funnel_in2: endpoint { 3721 remote-endpoint = <&etm2_out>; 3722 }; 3723 }; 3724 3725 port@3 { 3726 reg = <3>; 3727 apss_funnel_in3: endpoint { 3728 remote-endpoint = <&etm3_out>; 3729 }; 3730 }; 3731 3732 port@4 { 3733 reg = <4>; 3734 apss_funnel_in4: endpoint { 3735 remote-endpoint = <&etm4_out>; 3736 }; 3737 }; 3738 3739 port@5 { 3740 reg = <5>; 3741 apss_funnel_in5: endpoint { 3742 remote-endpoint = <&etm5_out>; 3743 }; 3744 }; 3745 3746 port@6 { 3747 reg = <6>; 3748 apss_funnel_in6: endpoint { 3749 remote-endpoint = <&etm6_out>; 3750 }; 3751 }; 3752 3753 port@7 { 3754 reg = <7>; 3755 apss_funnel_in7: endpoint { 3756 remote-endpoint = <&etm7_out>; 3757 }; 3758 }; 3759 }; 3760 }; 3761 3762 funnel@7810000 { 3763 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3764 reg = <0 0x07810000 0 0x1000>; 3765 3766 clocks = <&aoss_qmp>; 3767 clock-names = "apb_pclk"; 3768 3769 out-ports { 3770 port { 3771 funnel_apss_merg_out_funnel_in1: endpoint { 3772 remote-endpoint = <&funnel_in1_in_funnel_apss_merg>; 3773 }; 3774 }; 3775 }; 3776 3777 in-ports { 3778 port { 3779 funnel_apss_merg_in_funnel_apss: endpoint { 3780 remote-endpoint = <&funnel_apss_out_funnel_apss_merg>; 3781 }; 3782 }; 3783 }; 3784 }; 3785 3786 cdsp: remoteproc@8300000 { 3787 compatible = "qcom,sm8250-cdsp-pas"; 3788 reg = <0 0x08300000 0 0x10000>; 3789 3790 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3791 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3792 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3793 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3794 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3795 interrupt-names = "wdog", "fatal", "ready", 3796 "handover", "stop-ack"; 3797 3798 clocks = <&rpmhcc RPMH_CXO_CLK>; 3799 clock-names = "xo"; 3800 3801 power-domains = <&rpmhpd RPMHPD_CX>; 3802 3803 memory-region = <&cdsp_mem>; 3804 3805 qcom,qmp = <&aoss_qmp>; 3806 3807 qcom,smem-states = <&smp2p_cdsp_out 0>; 3808 qcom,smem-state-names = "stop"; 3809 3810 status = "disabled"; 3811 3812 glink-edge { 3813 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3814 IPCC_MPROC_SIGNAL_GLINK_QMP 3815 IRQ_TYPE_EDGE_RISING>; 3816 mboxes = <&ipcc IPCC_CLIENT_CDSP 3817 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3818 3819 label = "cdsp"; 3820 qcom,remote-pid = <5>; 3821 3822 fastrpc { 3823 compatible = "qcom,fastrpc"; 3824 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3825 label = "cdsp"; 3826 qcom,non-secure-domain; 3827 #address-cells = <1>; 3828 #size-cells = <0>; 3829 3830 compute-cb@1 { 3831 compatible = "qcom,fastrpc-compute-cb"; 3832 reg = <1>; 3833 iommus = <&apps_smmu 0x1001 0x0460>; 3834 }; 3835 3836 compute-cb@2 { 3837 compatible = "qcom,fastrpc-compute-cb"; 3838 reg = <2>; 3839 iommus = <&apps_smmu 0x1002 0x0460>; 3840 }; 3841 3842 compute-cb@3 { 3843 compatible = "qcom,fastrpc-compute-cb"; 3844 reg = <3>; 3845 iommus = <&apps_smmu 0x1003 0x0460>; 3846 }; 3847 3848 compute-cb@4 { 3849 compatible = "qcom,fastrpc-compute-cb"; 3850 reg = <4>; 3851 iommus = <&apps_smmu 0x1004 0x0460>; 3852 }; 3853 3854 compute-cb@5 { 3855 compatible = "qcom,fastrpc-compute-cb"; 3856 reg = <5>; 3857 iommus = <&apps_smmu 0x1005 0x0460>; 3858 }; 3859 3860 compute-cb@6 { 3861 compatible = "qcom,fastrpc-compute-cb"; 3862 reg = <6>; 3863 iommus = <&apps_smmu 0x1006 0x0460>; 3864 }; 3865 3866 compute-cb@7 { 3867 compatible = "qcom,fastrpc-compute-cb"; 3868 reg = <7>; 3869 iommus = <&apps_smmu 0x1007 0x0460>; 3870 }; 3871 3872 compute-cb@8 { 3873 compatible = "qcom,fastrpc-compute-cb"; 3874 reg = <8>; 3875 iommus = <&apps_smmu 0x1008 0x0460>; 3876 }; 3877 3878 /* note: secure cb9 in downstream */ 3879 }; 3880 }; 3881 }; 3882 3883 usb_1_hsphy: phy@88e3000 { 3884 compatible = "qcom,sm8250-usb-hs-phy", 3885 "qcom,usb-snps-hs-7nm-phy"; 3886 reg = <0 0x088e3000 0 0x400>; 3887 status = "disabled"; 3888 #phy-cells = <0>; 3889 3890 clocks = <&rpmhcc RPMH_CXO_CLK>; 3891 clock-names = "ref"; 3892 3893 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3894 }; 3895 3896 usb_2_hsphy: phy@88e4000 { 3897 compatible = "qcom,sm8250-usb-hs-phy", 3898 "qcom,usb-snps-hs-7nm-phy"; 3899 reg = <0 0x088e4000 0 0x400>; 3900 status = "disabled"; 3901 #phy-cells = <0>; 3902 3903 clocks = <&rpmhcc RPMH_CXO_CLK>; 3904 clock-names = "ref"; 3905 3906 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3907 }; 3908 3909 refgen: regulator@88e7000 { 3910 compatible = "qcom,sm8250-refgen-regulator"; 3911 reg = <0x0 0x088e7000 0x0 0x84>; 3912 }; 3913 3914 usb_1_qmpphy: phy@88e8000 { 3915 compatible = "qcom,sm8250-qmp-usb3-dp-phy"; 3916 reg = <0 0x088e8000 0 0x3000>; 3917 status = "disabled"; 3918 3919 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3920 <&rpmhcc RPMH_CXO_CLK>, 3921 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3922 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3923 clock-names = "aux", 3924 "ref", 3925 "com_aux", 3926 "usb3_pipe"; 3927 3928 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3929 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3930 reset-names = "phy", "common"; 3931 3932 #clock-cells = <1>; 3933 #phy-cells = <1>; 3934 3935 orientation-switch; 3936 3937 ports { 3938 #address-cells = <1>; 3939 #size-cells = <0>; 3940 3941 port@0 { 3942 reg = <0>; 3943 usb_1_qmpphy_out: endpoint {}; 3944 }; 3945 3946 port@1 { 3947 reg = <1>; 3948 3949 usb_1_qmpphy_usb_ss_in: endpoint { 3950 remote-endpoint = <&usb_1_dwc3_ss_out>; 3951 }; 3952 }; 3953 3954 port@2 { 3955 reg = <2>; 3956 3957 usb_1_qmpphy_dp_in: endpoint {}; 3958 }; 3959 }; 3960 }; 3961 3962 usb_2_qmpphy: phy@88eb000 { 3963 compatible = "qcom,sm8250-qmp-usb3-uni-phy"; 3964 reg = <0 0x088eb000 0 0x1000>; 3965 3966 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3967 <&gcc GCC_USB3_SEC_CLKREF_EN>, 3968 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 3969 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3970 clock-names = "aux", 3971 "ref", 3972 "com_aux", 3973 "pipe"; 3974 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3975 #clock-cells = <0>; 3976 #phy-cells = <0>; 3977 3978 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 3979 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 3980 reset-names = "phy", 3981 "phy_phy"; 3982 3983 status = "disabled"; 3984 }; 3985 3986 sdhc_2: mmc@8804000 { 3987 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; 3988 reg = <0 0x08804000 0 0x1000>; 3989 3990 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3991 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3992 interrupt-names = "hc_irq", "pwr_irq"; 3993 3994 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3995 <&gcc GCC_SDCC2_APPS_CLK>, 3996 <&rpmhcc RPMH_CXO_CLK>; 3997 clock-names = "iface", "core", "xo"; 3998 iommus = <&apps_smmu 0x4a0 0x0>; 3999 qcom,dll-config = <0x0007642c>; 4000 qcom,ddr-config = <0x80040868>; 4001 power-domains = <&rpmhpd RPMHPD_CX>; 4002 operating-points-v2 = <&sdhc2_opp_table>; 4003 4004 status = "disabled"; 4005 4006 sdhc2_opp_table: opp-table { 4007 compatible = "operating-points-v2"; 4008 4009 opp-19200000 { 4010 opp-hz = /bits/ 64 <19200000>; 4011 required-opps = <&rpmhpd_opp_min_svs>; 4012 }; 4013 4014 opp-50000000 { 4015 opp-hz = /bits/ 64 <50000000>; 4016 required-opps = <&rpmhpd_opp_low_svs>; 4017 }; 4018 4019 opp-100000000 { 4020 opp-hz = /bits/ 64 <100000000>; 4021 required-opps = <&rpmhpd_opp_svs>; 4022 }; 4023 4024 opp-202000000 { 4025 opp-hz = /bits/ 64 <202000000>; 4026 required-opps = <&rpmhpd_opp_svs_l1>; 4027 }; 4028 }; 4029 }; 4030 4031 pmu@9091000 { 4032 compatible = "qcom,sm8250-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 4033 reg = <0 0x09091000 0 0x1000>; 4034 4035 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 4036 4037 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI_CH0 3>; 4038 4039 operating-points-v2 = <&llcc_bwmon_opp_table>; 4040 4041 llcc_bwmon_opp_table: opp-table { 4042 compatible = "operating-points-v2"; 4043 4044 opp-800000 { 4045 opp-peak-kBps = <(200 * 4 * 1000)>; 4046 }; 4047 4048 opp-1200000 { 4049 opp-peak-kBps = <(300 * 4 * 1000)>; 4050 }; 4051 4052 opp-1804000 { 4053 opp-peak-kBps = <(451 * 4 * 1000)>; 4054 }; 4055 4056 opp-2188000 { 4057 opp-peak-kBps = <(547 * 4 * 1000)>; 4058 }; 4059 4060 opp-2724000 { 4061 opp-peak-kBps = <(681 * 4 * 1000)>; 4062 }; 4063 4064 opp-3072000 { 4065 opp-peak-kBps = <(768 * 4 * 1000)>; 4066 }; 4067 4068 opp-4068000 { 4069 opp-peak-kBps = <(1017 * 4 * 1000)>; 4070 }; 4071 4072 /* 1353 MHz, LPDDR4X */ 4073 4074 opp-6220000 { 4075 opp-peak-kBps = <(1555 * 4 * 1000)>; 4076 }; 4077 4078 opp-7216000 { 4079 opp-peak-kBps = <(1804 * 4 * 1000)>; 4080 }; 4081 4082 opp-8368000 { 4083 opp-peak-kBps = <(2092 * 4 * 1000)>; 4084 }; 4085 4086 /* LPDDR5 */ 4087 opp-10944000 { 4088 opp-peak-kBps = <(2736 * 4 * 1000)>; 4089 }; 4090 }; 4091 }; 4092 4093 pmu@90b6400 { 4094 compatible = "qcom,sm8250-cpu-bwmon", "qcom,sdm845-bwmon"; 4095 reg = <0 0x090b6400 0 0x600>; 4096 4097 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4098 4099 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &gem_noc SLAVE_LLCC 3>; 4100 operating-points-v2 = <&cpu_bwmon_opp_table>; 4101 4102 cpu_bwmon_opp_table: opp-table { 4103 compatible = "operating-points-v2"; 4104 4105 opp-800000 { 4106 opp-peak-kBps = <(200 * 4 * 1000)>; 4107 }; 4108 4109 opp-1804000 { 4110 opp-peak-kBps = <(451 * 4 * 1000)>; 4111 }; 4112 4113 opp-2188000 { 4114 opp-peak-kBps = <(547 * 4 * 1000)>; 4115 }; 4116 4117 opp-2724000 { 4118 opp-peak-kBps = <(681 * 4 * 1000)>; 4119 }; 4120 4121 opp-3072000 { 4122 opp-peak-kBps = <(768 * 4 * 1000)>; 4123 }; 4124 4125 /* 1017MHz, 1353 MHz, LPDDR4X */ 4126 4127 opp-6220000 { 4128 opp-peak-kBps = <(1555 * 4 * 1000)>; 4129 }; 4130 4131 opp-6832000 { 4132 opp-peak-kBps = <(1708 * 4 * 1000)>; 4133 }; 4134 4135 opp-8368000 { 4136 opp-peak-kBps = <(2092 * 4 * 1000)>; 4137 }; 4138 4139 /* 2133MHz, LPDDR4X */ 4140 4141 /* LPDDR5 */ 4142 opp-10944000 { 4143 opp-peak-kBps = <(2736 * 4 * 1000)>; 4144 }; 4145 4146 /* LPDDR5 */ 4147 opp-12784000 { 4148 opp-peak-kBps = <(3196 * 4 * 1000)>; 4149 }; 4150 }; 4151 }; 4152 4153 dc_noc: interconnect@90c0000 { 4154 compatible = "qcom,sm8250-dc-noc"; 4155 reg = <0 0x090c0000 0 0x4200>; 4156 #interconnect-cells = <2>; 4157 qcom,bcm-voters = <&apps_bcm_voter>; 4158 }; 4159 4160 gem_noc: interconnect@9100000 { 4161 compatible = "qcom,sm8250-gem-noc"; 4162 reg = <0 0x09100000 0 0xb4000>; 4163 #interconnect-cells = <2>; 4164 qcom,bcm-voters = <&apps_bcm_voter>; 4165 }; 4166 4167 npu_noc: interconnect@9990000 { 4168 compatible = "qcom,sm8250-npu-noc"; 4169 reg = <0 0x09990000 0 0x1600>; 4170 #interconnect-cells = <2>; 4171 qcom,bcm-voters = <&apps_bcm_voter>; 4172 }; 4173 4174 usb_1: usb@a6f8800 { 4175 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 4176 reg = <0 0x0a6f8800 0 0x400>; 4177 status = "disabled"; 4178 #address-cells = <2>; 4179 #size-cells = <2>; 4180 ranges; 4181 dma-ranges; 4182 4183 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4184 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4185 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4186 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4187 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4188 <&gcc GCC_USB3_SEC_CLKREF_EN>; 4189 clock-names = "cfg_noc", 4190 "core", 4191 "iface", 4192 "sleep", 4193 "mock_utmi", 4194 "xo"; 4195 4196 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4197 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4198 assigned-clock-rates = <19200000>, <200000000>; 4199 4200 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4201 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4202 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4203 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4204 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 4205 interrupt-names = "pwr_event", 4206 "hs_phy_irq", 4207 "dp_hs_phy_irq", 4208 "dm_hs_phy_irq", 4209 "ss_phy_irq"; 4210 4211 power-domains = <&gcc USB30_PRIM_GDSC>; 4212 wakeup-source; 4213 4214 resets = <&gcc GCC_USB30_PRIM_BCR>; 4215 4216 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, 4217 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 4218 interconnect-names = "usb-ddr", "apps-usb"; 4219 4220 usb_1_dwc3: usb@a600000 { 4221 compatible = "snps,dwc3"; 4222 reg = <0 0x0a600000 0 0xcd00>; 4223 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4224 iommus = <&apps_smmu 0x0 0x0>; 4225 snps,dis_u2_susphy_quirk; 4226 snps,dis_enblslpm_quirk; 4227 snps,dis-u1-entry-quirk; 4228 snps,dis-u2-entry-quirk; 4229 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4230 phy-names = "usb2-phy", "usb3-phy"; 4231 4232 ports { 4233 #address-cells = <1>; 4234 #size-cells = <0>; 4235 4236 port@0 { 4237 reg = <0>; 4238 4239 usb_1_dwc3_hs_out: endpoint { 4240 }; 4241 }; 4242 4243 port@1 { 4244 reg = <1>; 4245 4246 usb_1_dwc3_ss_out: endpoint { 4247 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 4248 }; 4249 }; 4250 }; 4251 }; 4252 }; 4253 4254 system-cache-controller@9200000 { 4255 compatible = "qcom,sm8250-llcc"; 4256 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, 4257 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, 4258 <0 0x09600000 0 0x50000>; 4259 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 4260 "llcc3_base", "llcc_broadcast_base"; 4261 }; 4262 4263 usb_2: usb@a8f8800 { 4264 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 4265 reg = <0 0x0a8f8800 0 0x400>; 4266 status = "disabled"; 4267 #address-cells = <2>; 4268 #size-cells = <2>; 4269 ranges; 4270 dma-ranges; 4271 4272 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4273 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4274 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4275 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4276 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4277 <&gcc GCC_USB3_SEC_CLKREF_EN>; 4278 clock-names = "cfg_noc", 4279 "core", 4280 "iface", 4281 "sleep", 4282 "mock_utmi", 4283 "xo"; 4284 4285 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4286 <&gcc GCC_USB30_SEC_MASTER_CLK>; 4287 assigned-clock-rates = <19200000>, <200000000>; 4288 4289 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 4290 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 4291 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 4292 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 4293 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 4294 interrupt-names = "pwr_event", 4295 "hs_phy_irq", 4296 "dp_hs_phy_irq", 4297 "dm_hs_phy_irq", 4298 "ss_phy_irq"; 4299 4300 power-domains = <&gcc USB30_SEC_GDSC>; 4301 wakeup-source; 4302 4303 resets = <&gcc GCC_USB30_SEC_BCR>; 4304 4305 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, 4306 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; 4307 interconnect-names = "usb-ddr", "apps-usb"; 4308 4309 usb_2_dwc3: usb@a800000 { 4310 compatible = "snps,dwc3"; 4311 reg = <0 0x0a800000 0 0xcd00>; 4312 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 4313 iommus = <&apps_smmu 0x20 0>; 4314 snps,dis_u2_susphy_quirk; 4315 snps,dis_enblslpm_quirk; 4316 snps,dis-u1-entry-quirk; 4317 snps,dis-u2-entry-quirk; 4318 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>; 4319 phy-names = "usb2-phy", "usb3-phy"; 4320 }; 4321 }; 4322 4323 venus: video-codec@aa00000 { 4324 compatible = "qcom,sm8250-venus"; 4325 reg = <0 0x0aa00000 0 0x100000>; 4326 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4327 power-domains = <&videocc MVS0C_GDSC>, 4328 <&videocc MVS0_GDSC>, 4329 <&rpmhpd RPMHPD_MX>; 4330 power-domain-names = "venus", "vcodec0", "mx"; 4331 operating-points-v2 = <&venus_opp_table>; 4332 4333 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 4334 <&videocc VIDEO_CC_MVS0C_CLK>, 4335 <&videocc VIDEO_CC_MVS0_CLK>; 4336 clock-names = "iface", "core", "vcodec0_core"; 4337 4338 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_VENUS_CFG 0>, 4339 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI_CH0 0>; 4340 interconnect-names = "cpu-cfg", "video-mem"; 4341 4342 iommus = <&apps_smmu 0x2100 0x0400>; 4343 memory-region = <&video_mem>; 4344 4345 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 4346 <&videocc VIDEO_CC_MVS0C_CLK_ARES>; 4347 reset-names = "bus", "core"; 4348 4349 status = "disabled"; 4350 4351 venus_opp_table: opp-table { 4352 compatible = "operating-points-v2"; 4353 4354 opp-720000000 { 4355 opp-hz = /bits/ 64 <720000000>; 4356 required-opps = <&rpmhpd_opp_low_svs>; 4357 }; 4358 4359 opp-1014000000 { 4360 opp-hz = /bits/ 64 <1014000000>; 4361 required-opps = <&rpmhpd_opp_svs>; 4362 }; 4363 4364 opp-1098000000 { 4365 opp-hz = /bits/ 64 <1098000000>; 4366 required-opps = <&rpmhpd_opp_svs_l1>; 4367 }; 4368 4369 opp-1332000000 { 4370 opp-hz = /bits/ 64 <1332000000>; 4371 required-opps = <&rpmhpd_opp_nom>; 4372 }; 4373 }; 4374 }; 4375 4376 videocc: clock-controller@abf0000 { 4377 compatible = "qcom,sm8250-videocc"; 4378 reg = <0 0x0abf0000 0 0x10000>; 4379 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 4380 <&rpmhcc RPMH_CXO_CLK>, 4381 <&rpmhcc RPMH_CXO_CLK_A>; 4382 power-domains = <&rpmhpd RPMHPD_MMCX>; 4383 required-opps = <&rpmhpd_opp_low_svs>; 4384 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; 4385 #clock-cells = <1>; 4386 #reset-cells = <1>; 4387 #power-domain-cells = <1>; 4388 }; 4389 4390 cci0: cci@ac4f000 { 4391 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci"; 4392 #address-cells = <1>; 4393 #size-cells = <0>; 4394 4395 reg = <0 0x0ac4f000 0 0x1000>; 4396 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4397 power-domains = <&camcc TITAN_TOP_GDSC>; 4398 4399 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4400 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4401 <&camcc CAM_CC_CPAS_AHB_CLK>, 4402 <&camcc CAM_CC_CCI_0_CLK>, 4403 <&camcc CAM_CC_CCI_0_CLK_SRC>; 4404 clock-names = "camnoc_axi", 4405 "slow_ahb_src", 4406 "cpas_ahb", 4407 "cci", 4408 "cci_src"; 4409 4410 pinctrl-0 = <&cci0_default>; 4411 pinctrl-1 = <&cci0_sleep>; 4412 pinctrl-names = "default", "sleep"; 4413 4414 status = "disabled"; 4415 4416 cci0_i2c0: i2c-bus@0 { 4417 reg = <0>; 4418 clock-frequency = <1000000>; 4419 #address-cells = <1>; 4420 #size-cells = <0>; 4421 }; 4422 4423 cci0_i2c1: i2c-bus@1 { 4424 reg = <1>; 4425 clock-frequency = <1000000>; 4426 #address-cells = <1>; 4427 #size-cells = <0>; 4428 }; 4429 }; 4430 4431 cci1: cci@ac50000 { 4432 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci"; 4433 #address-cells = <1>; 4434 #size-cells = <0>; 4435 4436 reg = <0 0x0ac50000 0 0x1000>; 4437 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 4438 power-domains = <&camcc TITAN_TOP_GDSC>; 4439 4440 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4441 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4442 <&camcc CAM_CC_CPAS_AHB_CLK>, 4443 <&camcc CAM_CC_CCI_1_CLK>, 4444 <&camcc CAM_CC_CCI_1_CLK_SRC>; 4445 clock-names = "camnoc_axi", 4446 "slow_ahb_src", 4447 "cpas_ahb", 4448 "cci", 4449 "cci_src"; 4450 4451 pinctrl-0 = <&cci1_default>; 4452 pinctrl-1 = <&cci1_sleep>; 4453 pinctrl-names = "default", "sleep"; 4454 4455 status = "disabled"; 4456 4457 cci1_i2c0: i2c-bus@0 { 4458 reg = <0>; 4459 clock-frequency = <1000000>; 4460 #address-cells = <1>; 4461 #size-cells = <0>; 4462 }; 4463 4464 cci1_i2c1: i2c-bus@1 { 4465 reg = <1>; 4466 clock-frequency = <1000000>; 4467 #address-cells = <1>; 4468 #size-cells = <0>; 4469 }; 4470 }; 4471 4472 camss: camss@ac6a000 { 4473 compatible = "qcom,sm8250-camss"; 4474 status = "disabled"; 4475 4476 reg = <0 0x0ac6a000 0 0x2000>, 4477 <0 0x0ac6c000 0 0x2000>, 4478 <0 0x0ac6e000 0 0x1000>, 4479 <0 0x0ac70000 0 0x1000>, 4480 <0 0x0ac72000 0 0x1000>, 4481 <0 0x0ac74000 0 0x1000>, 4482 <0 0x0acb4000 0 0xd000>, 4483 <0 0x0acc3000 0 0xd000>, 4484 <0 0x0acd9000 0 0x2200>, 4485 <0 0x0acdb200 0 0x2200>; 4486 reg-names = "csiphy0", 4487 "csiphy1", 4488 "csiphy2", 4489 "csiphy3", 4490 "csiphy4", 4491 "csiphy5", 4492 "vfe0", 4493 "vfe1", 4494 "vfe_lite0", 4495 "vfe_lite1"; 4496 4497 interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 4498 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 4499 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 4500 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 4501 <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>, 4502 <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>, 4503 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 4504 <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, 4505 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 4506 <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, 4507 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 4508 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 4509 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, 4510 <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>; 4511 interrupt-names = "csiphy0", 4512 "csiphy1", 4513 "csiphy2", 4514 "csiphy3", 4515 "csiphy4", 4516 "csiphy5", 4517 "csid0", 4518 "csid1", 4519 "csid2", 4520 "csid3", 4521 "vfe0", 4522 "vfe1", 4523 "vfe_lite0", 4524 "vfe_lite1"; 4525 4526 power-domains = <&camcc IFE_0_GDSC>, 4527 <&camcc IFE_1_GDSC>, 4528 <&camcc TITAN_TOP_GDSC>; 4529 4530 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4531 <&gcc GCC_CAMERA_HF_AXI_CLK>, 4532 <&gcc GCC_CAMERA_SF_AXI_CLK>, 4533 <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4534 <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, 4535 <&camcc CAM_CC_CORE_AHB_CLK>, 4536 <&camcc CAM_CC_CPAS_AHB_CLK>, 4537 <&camcc CAM_CC_CSIPHY0_CLK>, 4538 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 4539 <&camcc CAM_CC_CSIPHY1_CLK>, 4540 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 4541 <&camcc CAM_CC_CSIPHY2_CLK>, 4542 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 4543 <&camcc CAM_CC_CSIPHY3_CLK>, 4544 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 4545 <&camcc CAM_CC_CSIPHY4_CLK>, 4546 <&camcc CAM_CC_CSI4PHYTIMER_CLK>, 4547 <&camcc CAM_CC_CSIPHY5_CLK>, 4548 <&camcc CAM_CC_CSI5PHYTIMER_CLK>, 4549 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4550 <&camcc CAM_CC_IFE_0_AHB_CLK>, 4551 <&camcc CAM_CC_IFE_0_AXI_CLK>, 4552 <&camcc CAM_CC_IFE_0_CLK>, 4553 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 4554 <&camcc CAM_CC_IFE_0_CSID_CLK>, 4555 <&camcc CAM_CC_IFE_0_AREG_CLK>, 4556 <&camcc CAM_CC_IFE_1_AHB_CLK>, 4557 <&camcc CAM_CC_IFE_1_AXI_CLK>, 4558 <&camcc CAM_CC_IFE_1_CLK>, 4559 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 4560 <&camcc CAM_CC_IFE_1_CSID_CLK>, 4561 <&camcc CAM_CC_IFE_1_AREG_CLK>, 4562 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 4563 <&camcc CAM_CC_IFE_LITE_AXI_CLK>, 4564 <&camcc CAM_CC_IFE_LITE_CLK>, 4565 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 4566 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 4567 4568 clock-names = "cam_ahb_clk", 4569 "cam_hf_axi", 4570 "cam_sf_axi", 4571 "camnoc_axi", 4572 "camnoc_axi_src", 4573 "core_ahb", 4574 "cpas_ahb", 4575 "csiphy0", 4576 "csiphy0_timer", 4577 "csiphy1", 4578 "csiphy1_timer", 4579 "csiphy2", 4580 "csiphy2_timer", 4581 "csiphy3", 4582 "csiphy3_timer", 4583 "csiphy4", 4584 "csiphy4_timer", 4585 "csiphy5", 4586 "csiphy5_timer", 4587 "slow_ahb_src", 4588 "vfe0_ahb", 4589 "vfe0_axi", 4590 "vfe0", 4591 "vfe0_cphy_rx", 4592 "vfe0_csid", 4593 "vfe0_areg", 4594 "vfe1_ahb", 4595 "vfe1_axi", 4596 "vfe1", 4597 "vfe1_cphy_rx", 4598 "vfe1_csid", 4599 "vfe1_areg", 4600 "vfe_lite_ahb", 4601 "vfe_lite_axi", 4602 "vfe_lite", 4603 "vfe_lite_cphy_rx", 4604 "vfe_lite_csid"; 4605 4606 iommus = <&apps_smmu 0x800 0x400>, 4607 <&apps_smmu 0x801 0x400>, 4608 <&apps_smmu 0x840 0x400>, 4609 <&apps_smmu 0x841 0x400>, 4610 <&apps_smmu 0xc00 0x400>, 4611 <&apps_smmu 0xc01 0x400>, 4612 <&apps_smmu 0xc40 0x400>, 4613 <&apps_smmu 0xc41 0x400>; 4614 4615 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_CAMERA_CFG 0>, 4616 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI_CH0 0>, 4617 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI_CH0 0>, 4618 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI_CH0 0>; 4619 interconnect-names = "cam_ahb", 4620 "cam_hf_0_mnoc", 4621 "cam_sf_0_mnoc", 4622 "cam_sf_icp_mnoc"; 4623 4624 ports { 4625 #address-cells = <1>; 4626 #size-cells = <0>; 4627 4628 port@0 { 4629 reg = <0>; 4630 }; 4631 4632 port@1 { 4633 reg = <1>; 4634 }; 4635 4636 port@2 { 4637 reg = <2>; 4638 }; 4639 4640 port@3 { 4641 reg = <3>; 4642 }; 4643 4644 port@4 { 4645 reg = <4>; 4646 }; 4647 4648 port@5 { 4649 reg = <5>; 4650 }; 4651 }; 4652 }; 4653 4654 camcc: clock-controller@ad00000 { 4655 compatible = "qcom,sm8250-camcc"; 4656 reg = <0 0x0ad00000 0 0x10000>; 4657 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4658 <&rpmhcc RPMH_CXO_CLK>, 4659 <&rpmhcc RPMH_CXO_CLK_A>, 4660 <&sleep_clk>; 4661 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 4662 power-domains = <&rpmhpd RPMHPD_MMCX>; 4663 required-opps = <&rpmhpd_opp_low_svs>; 4664 #clock-cells = <1>; 4665 #reset-cells = <1>; 4666 #power-domain-cells = <1>; 4667 }; 4668 4669 mdss: display-subsystem@ae00000 { 4670 compatible = "qcom,sm8250-mdss"; 4671 reg = <0 0x0ae00000 0 0x1000>; 4672 reg-names = "mdss"; 4673 4674 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>, 4675 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>; 4676 interconnect-names = "mdp0-mem", "mdp1-mem"; 4677 4678 power-domains = <&dispcc MDSS_GDSC>; 4679 4680 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4681 <&gcc GCC_DISP_HF_AXI_CLK>, 4682 <&gcc GCC_DISP_SF_AXI_CLK>, 4683 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4684 clock-names = "iface", "bus", "nrt_bus", "core"; 4685 4686 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4687 interrupt-controller; 4688 #interrupt-cells = <1>; 4689 4690 iommus = <&apps_smmu 0x820 0x402>; 4691 4692 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 4693 4694 status = "disabled"; 4695 4696 #address-cells = <2>; 4697 #size-cells = <2>; 4698 ranges; 4699 4700 mdss_mdp: display-controller@ae01000 { 4701 compatible = "qcom,sm8250-dpu"; 4702 reg = <0 0x0ae01000 0 0x8f000>, 4703 <0 0x0aeb0000 0 0x3000>; 4704 reg-names = "mdp", "vbif"; 4705 4706 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4707 <&gcc GCC_DISP_HF_AXI_CLK>, 4708 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4709 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4710 clock-names = "iface", "bus", "core", "vsync"; 4711 4712 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4713 assigned-clock-rates = <19200000>; 4714 4715 operating-points-v2 = <&mdp_opp_table>; 4716 power-domains = <&rpmhpd RPMHPD_MMCX>; 4717 4718 interrupt-parent = <&mdss>; 4719 interrupts = <0>; 4720 4721 ports { 4722 #address-cells = <1>; 4723 #size-cells = <0>; 4724 4725 port@0 { 4726 reg = <0>; 4727 dpu_intf1_out: endpoint { 4728 remote-endpoint = <&mdss_dsi0_in>; 4729 }; 4730 }; 4731 4732 port@1 { 4733 reg = <1>; 4734 dpu_intf2_out: endpoint { 4735 remote-endpoint = <&mdss_dsi1_in>; 4736 }; 4737 }; 4738 4739 port@2 { 4740 reg = <2>; 4741 4742 dpu_intf0_out: endpoint { 4743 remote-endpoint = <&mdss_dp_in>; 4744 }; 4745 }; 4746 }; 4747 4748 mdp_opp_table: opp-table { 4749 compatible = "operating-points-v2"; 4750 4751 opp-200000000 { 4752 opp-hz = /bits/ 64 <200000000>; 4753 required-opps = <&rpmhpd_opp_low_svs>; 4754 }; 4755 4756 opp-300000000 { 4757 opp-hz = /bits/ 64 <300000000>; 4758 required-opps = <&rpmhpd_opp_svs>; 4759 }; 4760 4761 opp-345000000 { 4762 opp-hz = /bits/ 64 <345000000>; 4763 required-opps = <&rpmhpd_opp_svs_l1>; 4764 }; 4765 4766 opp-460000000 { 4767 opp-hz = /bits/ 64 <460000000>; 4768 required-opps = <&rpmhpd_opp_nom>; 4769 }; 4770 }; 4771 }; 4772 4773 mdss_dp: displayport-controller@ae90000 { 4774 compatible = "qcom,sm8250-dp", "qcom,sm8350-dp"; 4775 reg = <0 0xae90000 0 0x200>, 4776 <0 0xae90200 0 0x200>, 4777 <0 0xae90400 0 0x600>, 4778 <0 0xae91000 0 0x400>, 4779 <0 0xae91400 0 0x400>; 4780 interrupt-parent = <&mdss>; 4781 interrupts = <12>; 4782 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4783 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4784 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4785 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4786 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, 4787 <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; 4788 clock-names = "core_iface", 4789 "core_aux", 4790 "ctrl_link", 4791 "ctrl_link_iface", 4792 "stream_pixel", 4793 "stream_1_pixel"; 4794 4795 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4796 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, 4797 <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; 4798 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4799 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4800 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4801 4802 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 4803 phy-names = "dp"; 4804 4805 #sound-dai-cells = <0>; 4806 4807 operating-points-v2 = <&dp_opp_table>; 4808 power-domains = <&rpmhpd RPMHPD_MMCX>; 4809 4810 status = "disabled"; 4811 4812 ports { 4813 #address-cells = <1>; 4814 #size-cells = <0>; 4815 4816 port@0 { 4817 reg = <0>; 4818 mdss_dp_in: endpoint { 4819 remote-endpoint = <&dpu_intf0_out>; 4820 }; 4821 }; 4822 4823 port@1 { 4824 reg = <1>; 4825 4826 mdss_dp_out: endpoint { 4827 }; 4828 }; 4829 }; 4830 4831 dp_opp_table: opp-table { 4832 compatible = "operating-points-v2"; 4833 4834 opp-162000000 { 4835 opp-hz = /bits/ 64 <162000000>; 4836 required-opps = <&rpmhpd_opp_low_svs>; 4837 }; 4838 4839 opp-270000000 { 4840 opp-hz = /bits/ 64 <270000000>; 4841 required-opps = <&rpmhpd_opp_svs>; 4842 }; 4843 4844 opp-540000000 { 4845 opp-hz = /bits/ 64 <540000000>; 4846 required-opps = <&rpmhpd_opp_svs_l1>; 4847 }; 4848 4849 opp-810000000 { 4850 opp-hz = /bits/ 64 <810000000>; 4851 required-opps = <&rpmhpd_opp_nom>; 4852 }; 4853 }; 4854 }; 4855 4856 mdss_dsi0: dsi@ae94000 { 4857 compatible = "qcom,sm8250-dsi-ctrl", 4858 "qcom,mdss-dsi-ctrl"; 4859 reg = <0 0x0ae94000 0 0x400>; 4860 reg-names = "dsi_ctrl"; 4861 4862 interrupt-parent = <&mdss>; 4863 interrupts = <4>; 4864 4865 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4866 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4867 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4868 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4869 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4870 <&gcc GCC_DISP_HF_AXI_CLK>; 4871 clock-names = "byte", 4872 "byte_intf", 4873 "pixel", 4874 "core", 4875 "iface", 4876 "bus"; 4877 4878 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 4879 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4880 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 4881 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 4882 4883 operating-points-v2 = <&dsi_opp_table>; 4884 power-domains = <&rpmhpd RPMHPD_MMCX>; 4885 4886 phys = <&mdss_dsi0_phy>; 4887 4888 refgen-supply = <&refgen>; 4889 4890 status = "disabled"; 4891 4892 #address-cells = <1>; 4893 #size-cells = <0>; 4894 4895 ports { 4896 #address-cells = <1>; 4897 #size-cells = <0>; 4898 4899 port@0 { 4900 reg = <0>; 4901 mdss_dsi0_in: endpoint { 4902 remote-endpoint = <&dpu_intf1_out>; 4903 }; 4904 }; 4905 4906 port@1 { 4907 reg = <1>; 4908 mdss_dsi0_out: endpoint { 4909 }; 4910 }; 4911 }; 4912 4913 dsi_opp_table: opp-table { 4914 compatible = "operating-points-v2"; 4915 4916 opp-187500000 { 4917 opp-hz = /bits/ 64 <187500000>; 4918 required-opps = <&rpmhpd_opp_low_svs>; 4919 }; 4920 4921 opp-300000000 { 4922 opp-hz = /bits/ 64 <300000000>; 4923 required-opps = <&rpmhpd_opp_svs>; 4924 }; 4925 4926 opp-358000000 { 4927 opp-hz = /bits/ 64 <358000000>; 4928 required-opps = <&rpmhpd_opp_svs_l1>; 4929 }; 4930 }; 4931 }; 4932 4933 mdss_dsi0_phy: phy@ae94400 { 4934 compatible = "qcom,dsi-phy-7nm"; 4935 reg = <0 0x0ae94400 0 0x200>, 4936 <0 0x0ae94600 0 0x280>, 4937 <0 0x0ae94900 0 0x260>; 4938 reg-names = "dsi_phy", 4939 "dsi_phy_lane", 4940 "dsi_pll"; 4941 4942 #clock-cells = <1>; 4943 #phy-cells = <0>; 4944 4945 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4946 <&rpmhcc RPMH_CXO_CLK>; 4947 clock-names = "iface", "ref"; 4948 4949 status = "disabled"; 4950 }; 4951 4952 mdss_dsi1: dsi@ae96000 { 4953 compatible = "qcom,sm8250-dsi-ctrl", 4954 "qcom,mdss-dsi-ctrl"; 4955 reg = <0 0x0ae96000 0 0x400>; 4956 reg-names = "dsi_ctrl"; 4957 4958 interrupt-parent = <&mdss>; 4959 interrupts = <5>; 4960 4961 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 4962 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 4963 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 4964 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 4965 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4966 <&gcc GCC_DISP_HF_AXI_CLK>; 4967 clock-names = "byte", 4968 "byte_intf", 4969 "pixel", 4970 "core", 4971 "iface", 4972 "bus"; 4973 4974 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 4975 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 4976 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 4977 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 4978 4979 operating-points-v2 = <&dsi_opp_table>; 4980 power-domains = <&rpmhpd RPMHPD_MMCX>; 4981 4982 phys = <&mdss_dsi1_phy>; 4983 4984 refgen-supply = <&refgen>; 4985 4986 status = "disabled"; 4987 4988 #address-cells = <1>; 4989 #size-cells = <0>; 4990 4991 ports { 4992 #address-cells = <1>; 4993 #size-cells = <0>; 4994 4995 port@0 { 4996 reg = <0>; 4997 mdss_dsi1_in: endpoint { 4998 remote-endpoint = <&dpu_intf2_out>; 4999 }; 5000 }; 5001 5002 port@1 { 5003 reg = <1>; 5004 mdss_dsi1_out: endpoint { 5005 }; 5006 }; 5007 }; 5008 }; 5009 5010 mdss_dsi1_phy: phy@ae96400 { 5011 compatible = "qcom,dsi-phy-7nm"; 5012 reg = <0 0x0ae96400 0 0x200>, 5013 <0 0x0ae96600 0 0x280>, 5014 <0 0x0ae96900 0 0x260>; 5015 reg-names = "dsi_phy", 5016 "dsi_phy_lane", 5017 "dsi_pll"; 5018 5019 #clock-cells = <1>; 5020 #phy-cells = <0>; 5021 5022 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5023 <&rpmhcc RPMH_CXO_CLK>; 5024 clock-names = "iface", "ref"; 5025 5026 status = "disabled"; 5027 }; 5028 }; 5029 5030 dispcc: clock-controller@af00000 { 5031 compatible = "qcom,sm8250-dispcc"; 5032 reg = <0 0x0af00000 0 0x10000>; 5033 power-domains = <&rpmhpd RPMHPD_MMCX>; 5034 required-opps = <&rpmhpd_opp_low_svs>; 5035 clocks = <&rpmhcc RPMH_CXO_CLK>, 5036 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 5037 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 5038 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 5039 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 5040 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5041 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5042 clock-names = "bi_tcxo", 5043 "dsi0_phy_pll_out_byteclk", 5044 "dsi0_phy_pll_out_dsiclk", 5045 "dsi1_phy_pll_out_byteclk", 5046 "dsi1_phy_pll_out_dsiclk", 5047 "dp_phy_pll_link_clk", 5048 "dp_phy_pll_vco_div_clk"; 5049 #clock-cells = <1>; 5050 #reset-cells = <1>; 5051 #power-domain-cells = <1>; 5052 }; 5053 5054 pdc: interrupt-controller@b220000 { 5055 compatible = "qcom,sm8250-pdc", "qcom,pdc"; 5056 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 5057 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 5058 <125 63 1>, <126 716 12>; 5059 #interrupt-cells = <2>; 5060 interrupt-parent = <&intc>; 5061 interrupt-controller; 5062 }; 5063 5064 tsens0: thermal-sensor@c263000 { 5065 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 5066 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 5067 <0 0x0c222000 0 0x1ff>; /* SROT */ 5068 #qcom,sensors = <16>; 5069 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 5070 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 5071 interrupt-names = "uplow", "critical"; 5072 #thermal-sensor-cells = <1>; 5073 }; 5074 5075 tsens1: thermal-sensor@c265000 { 5076 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 5077 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 5078 <0 0x0c223000 0 0x1ff>; /* SROT */ 5079 #qcom,sensors = <9>; 5080 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 5081 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 5082 interrupt-names = "uplow", "critical"; 5083 #thermal-sensor-cells = <1>; 5084 }; 5085 5086 aoss_qmp: power-management@c300000 { 5087 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp"; 5088 reg = <0 0x0c300000 0 0x400>; 5089 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 5090 IPCC_MPROC_SIGNAL_GLINK_QMP 5091 IRQ_TYPE_EDGE_RISING>; 5092 mboxes = <&ipcc IPCC_CLIENT_AOP 5093 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5094 5095 #clock-cells = <0>; 5096 }; 5097 5098 sram@c3f0000 { 5099 compatible = "qcom,rpmh-stats"; 5100 reg = <0 0x0c3f0000 0 0x400>; 5101 }; 5102 5103 spmi_bus: spmi@c440000 { 5104 compatible = "qcom,spmi-pmic-arb"; 5105 reg = <0x0 0x0c440000 0x0 0x0001100>, 5106 <0x0 0x0c600000 0x0 0x2000000>, 5107 <0x0 0x0e600000 0x0 0x0100000>, 5108 <0x0 0x0e700000 0x0 0x00a0000>, 5109 <0x0 0x0c40a000 0x0 0x0026000>; 5110 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 5111 interrupt-names = "periph_irq"; 5112 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5113 qcom,ee = <0>; 5114 qcom,channel = <0>; 5115 #address-cells = <2>; 5116 #size-cells = <0>; 5117 interrupt-controller; 5118 #interrupt-cells = <4>; 5119 }; 5120 5121 tlmm: pinctrl@f100000 { 5122 compatible = "qcom,sm8250-pinctrl"; 5123 reg = <0 0x0f100000 0 0x300000>, 5124 <0 0x0f500000 0 0x300000>, 5125 <0 0x0f900000 0 0x300000>; 5126 reg-names = "west", "south", "north"; 5127 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 5128 gpio-controller; 5129 #gpio-cells = <2>; 5130 interrupt-controller; 5131 #interrupt-cells = <2>; 5132 gpio-ranges = <&tlmm 0 0 181>; 5133 wakeup-parent = <&pdc>; 5134 5135 cam2_default: cam2-default-state { 5136 rst-pins { 5137 pins = "gpio78"; 5138 function = "gpio"; 5139 drive-strength = <2>; 5140 bias-disable; 5141 }; 5142 5143 mclk-pins { 5144 pins = "gpio96"; 5145 function = "cam_mclk"; 5146 drive-strength = <16>; 5147 bias-disable; 5148 }; 5149 }; 5150 5151 cam2_suspend: cam2-suspend-state { 5152 rst-pins { 5153 pins = "gpio78"; 5154 function = "gpio"; 5155 drive-strength = <2>; 5156 bias-pull-down; 5157 output-low; 5158 }; 5159 5160 mclk-pins { 5161 pins = "gpio96"; 5162 function = "cam_mclk"; 5163 drive-strength = <2>; 5164 bias-disable; 5165 }; 5166 }; 5167 5168 cci0_default: cci0-default-state { 5169 cci0_i2c0_default: cci0-i2c0-default-pins { 5170 /* SDA, SCL */ 5171 pins = "gpio101", "gpio102"; 5172 function = "cci_i2c"; 5173 5174 bias-pull-up; 5175 drive-strength = <2>; /* 2 mA */ 5176 }; 5177 5178 cci0_i2c1_default: cci0-i2c1-default-pins { 5179 /* SDA, SCL */ 5180 pins = "gpio103", "gpio104"; 5181 function = "cci_i2c"; 5182 5183 bias-pull-up; 5184 drive-strength = <2>; /* 2 mA */ 5185 }; 5186 }; 5187 5188 cci0_sleep: cci0-sleep-state { 5189 cci0_i2c0_sleep: cci0-i2c0-sleep-pins { 5190 /* SDA, SCL */ 5191 pins = "gpio101", "gpio102"; 5192 function = "cci_i2c"; 5193 5194 drive-strength = <2>; /* 2 mA */ 5195 bias-pull-down; 5196 }; 5197 5198 cci0_i2c1_sleep: cci0-i2c1-sleep-pins { 5199 /* SDA, SCL */ 5200 pins = "gpio103", "gpio104"; 5201 function = "cci_i2c"; 5202 5203 drive-strength = <2>; /* 2 mA */ 5204 bias-pull-down; 5205 }; 5206 }; 5207 5208 cci1_default: cci1-default-state { 5209 cci1_i2c0_default: cci1-i2c0-default-pins { 5210 /* SDA, SCL */ 5211 pins = "gpio105","gpio106"; 5212 function = "cci_i2c"; 5213 5214 bias-pull-up; 5215 drive-strength = <2>; /* 2 mA */ 5216 }; 5217 5218 cci1_i2c1_default: cci1-i2c1-default-pins { 5219 /* SDA, SCL */ 5220 pins = "gpio107","gpio108"; 5221 function = "cci_i2c"; 5222 5223 bias-pull-up; 5224 drive-strength = <2>; /* 2 mA */ 5225 }; 5226 }; 5227 5228 cci1_sleep: cci1-sleep-state { 5229 cci1_i2c0_sleep: cci1-i2c0-sleep-pins { 5230 /* SDA, SCL */ 5231 pins = "gpio105","gpio106"; 5232 function = "cci_i2c"; 5233 5234 bias-pull-down; 5235 drive-strength = <2>; /* 2 mA */ 5236 }; 5237 5238 cci1_i2c1_sleep: cci1-i2c1-sleep-pins { 5239 /* SDA, SCL */ 5240 pins = "gpio107","gpio108"; 5241 function = "cci_i2c"; 5242 5243 bias-pull-down; 5244 drive-strength = <2>; /* 2 mA */ 5245 }; 5246 }; 5247 5248 pri_mi2s_active: pri-mi2s-active-state { 5249 sclk-pins { 5250 pins = "gpio138"; 5251 function = "mi2s0_sck"; 5252 drive-strength = <8>; 5253 bias-disable; 5254 }; 5255 5256 ws-pins { 5257 pins = "gpio141"; 5258 function = "mi2s0_ws"; 5259 drive-strength = <8>; 5260 output-high; 5261 }; 5262 5263 data0-pins { 5264 pins = "gpio139"; 5265 function = "mi2s0_data0"; 5266 drive-strength = <8>; 5267 bias-disable; 5268 output-high; 5269 }; 5270 5271 data1-pins { 5272 pins = "gpio140"; 5273 function = "mi2s0_data1"; 5274 drive-strength = <8>; 5275 output-high; 5276 }; 5277 }; 5278 5279 qup_i2c0_default: qup-i2c0-default-state { 5280 pins = "gpio28", "gpio29"; 5281 function = "qup0"; 5282 drive-strength = <2>; 5283 bias-disable; 5284 }; 5285 5286 qup_i2c1_default: qup-i2c1-default-state { 5287 pins = "gpio4", "gpio5"; 5288 function = "qup1"; 5289 drive-strength = <2>; 5290 bias-disable; 5291 }; 5292 5293 qup_i2c2_default: qup-i2c2-default-state { 5294 pins = "gpio115", "gpio116"; 5295 function = "qup2"; 5296 drive-strength = <2>; 5297 bias-disable; 5298 }; 5299 5300 qup_i2c3_default: qup-i2c3-default-state { 5301 pins = "gpio119", "gpio120"; 5302 function = "qup3"; 5303 drive-strength = <2>; 5304 bias-disable; 5305 }; 5306 5307 qup_i2c4_default: qup-i2c4-default-state { 5308 pins = "gpio8", "gpio9"; 5309 function = "qup4"; 5310 drive-strength = <2>; 5311 bias-disable; 5312 }; 5313 5314 qup_i2c5_default: qup-i2c5-default-state { 5315 pins = "gpio12", "gpio13"; 5316 function = "qup5"; 5317 drive-strength = <2>; 5318 bias-disable; 5319 }; 5320 5321 qup_i2c6_default: qup-i2c6-default-state { 5322 pins = "gpio16", "gpio17"; 5323 function = "qup6"; 5324 drive-strength = <2>; 5325 bias-disable; 5326 }; 5327 5328 qup_i2c7_default: qup-i2c7-default-state { 5329 pins = "gpio20", "gpio21"; 5330 function = "qup7"; 5331 drive-strength = <2>; 5332 bias-disable; 5333 }; 5334 5335 qup_i2c8_default: qup-i2c8-default-state { 5336 pins = "gpio24", "gpio25"; 5337 function = "qup8"; 5338 drive-strength = <2>; 5339 bias-disable; 5340 }; 5341 5342 qup_i2c9_default: qup-i2c9-default-state { 5343 pins = "gpio125", "gpio126"; 5344 function = "qup9"; 5345 drive-strength = <2>; 5346 bias-disable; 5347 }; 5348 5349 qup_i2c10_default: qup-i2c10-default-state { 5350 pins = "gpio129", "gpio130"; 5351 function = "qup10"; 5352 drive-strength = <2>; 5353 bias-disable; 5354 }; 5355 5356 qup_i2c11_default: qup-i2c11-default-state { 5357 pins = "gpio60", "gpio61"; 5358 function = "qup11"; 5359 drive-strength = <2>; 5360 bias-disable; 5361 }; 5362 5363 qup_i2c12_default: qup-i2c12-default-state { 5364 pins = "gpio32", "gpio33"; 5365 function = "qup12"; 5366 drive-strength = <2>; 5367 bias-disable; 5368 }; 5369 5370 qup_i2c13_default: qup-i2c13-default-state { 5371 pins = "gpio36", "gpio37"; 5372 function = "qup13"; 5373 drive-strength = <2>; 5374 bias-disable; 5375 }; 5376 5377 qup_i2c14_default: qup-i2c14-default-state { 5378 pins = "gpio40", "gpio41"; 5379 function = "qup14"; 5380 drive-strength = <2>; 5381 bias-disable; 5382 }; 5383 5384 qup_i2c15_default: qup-i2c15-default-state { 5385 pins = "gpio44", "gpio45"; 5386 function = "qup15"; 5387 drive-strength = <2>; 5388 bias-disable; 5389 }; 5390 5391 qup_i2c16_default: qup-i2c16-default-state { 5392 pins = "gpio48", "gpio49"; 5393 function = "qup16"; 5394 drive-strength = <2>; 5395 bias-disable; 5396 }; 5397 5398 qup_i2c17_default: qup-i2c17-default-state { 5399 pins = "gpio52", "gpio53"; 5400 function = "qup17"; 5401 drive-strength = <2>; 5402 bias-disable; 5403 }; 5404 5405 qup_i2c18_default: qup-i2c18-default-state { 5406 pins = "gpio56", "gpio57"; 5407 function = "qup18"; 5408 drive-strength = <2>; 5409 bias-disable; 5410 }; 5411 5412 qup_i2c19_default: qup-i2c19-default-state { 5413 pins = "gpio0", "gpio1"; 5414 function = "qup19"; 5415 drive-strength = <2>; 5416 bias-disable; 5417 }; 5418 5419 qup_spi0_cs: qup-spi0-cs-state { 5420 pins = "gpio31"; 5421 function = "qup0"; 5422 }; 5423 5424 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 5425 pins = "gpio31"; 5426 function = "gpio"; 5427 }; 5428 5429 qup_spi0_data_clk: qup-spi0-data-clk-state { 5430 pins = "gpio28", "gpio29", 5431 "gpio30"; 5432 function = "qup0"; 5433 }; 5434 5435 qup_spi1_cs: qup-spi1-cs-state { 5436 pins = "gpio7"; 5437 function = "qup1"; 5438 }; 5439 5440 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 5441 pins = "gpio7"; 5442 function = "gpio"; 5443 }; 5444 5445 qup_spi1_data_clk: qup-spi1-data-clk-state { 5446 pins = "gpio4", "gpio5", 5447 "gpio6"; 5448 function = "qup1"; 5449 }; 5450 5451 qup_spi2_cs: qup-spi2-cs-state { 5452 pins = "gpio118"; 5453 function = "qup2"; 5454 }; 5455 5456 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 5457 pins = "gpio118"; 5458 function = "gpio"; 5459 }; 5460 5461 qup_spi2_data_clk: qup-spi2-data-clk-state { 5462 pins = "gpio115", "gpio116", 5463 "gpio117"; 5464 function = "qup2"; 5465 }; 5466 5467 qup_spi3_cs: qup-spi3-cs-state { 5468 pins = "gpio122"; 5469 function = "qup3"; 5470 }; 5471 5472 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 5473 pins = "gpio122"; 5474 function = "gpio"; 5475 }; 5476 5477 qup_spi3_data_clk: qup-spi3-data-clk-state { 5478 pins = "gpio119", "gpio120", 5479 "gpio121"; 5480 function = "qup3"; 5481 }; 5482 5483 qup_spi4_cs: qup-spi4-cs-state { 5484 pins = "gpio11"; 5485 function = "qup4"; 5486 }; 5487 5488 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 5489 pins = "gpio11"; 5490 function = "gpio"; 5491 }; 5492 5493 qup_spi4_data_clk: qup-spi4-data-clk-state { 5494 pins = "gpio8", "gpio9", 5495 "gpio10"; 5496 function = "qup4"; 5497 }; 5498 5499 qup_spi5_cs: qup-spi5-cs-state { 5500 pins = "gpio15"; 5501 function = "qup5"; 5502 }; 5503 5504 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 5505 pins = "gpio15"; 5506 function = "gpio"; 5507 }; 5508 5509 qup_spi5_data_clk: qup-spi5-data-clk-state { 5510 pins = "gpio12", "gpio13", 5511 "gpio14"; 5512 function = "qup5"; 5513 }; 5514 5515 qup_spi6_cs: qup-spi6-cs-state { 5516 pins = "gpio19"; 5517 function = "qup6"; 5518 }; 5519 5520 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 5521 pins = "gpio19"; 5522 function = "gpio"; 5523 }; 5524 5525 qup_spi6_data_clk: qup-spi6-data-clk-state { 5526 pins = "gpio16", "gpio17", 5527 "gpio18"; 5528 function = "qup6"; 5529 }; 5530 5531 qup_spi7_cs: qup-spi7-cs-state { 5532 pins = "gpio23"; 5533 function = "qup7"; 5534 }; 5535 5536 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 5537 pins = "gpio23"; 5538 function = "gpio"; 5539 }; 5540 5541 qup_spi7_data_clk: qup-spi7-data-clk-state { 5542 pins = "gpio20", "gpio21", 5543 "gpio22"; 5544 function = "qup7"; 5545 }; 5546 5547 qup_spi8_cs: qup-spi8-cs-state { 5548 pins = "gpio27"; 5549 function = "qup8"; 5550 }; 5551 5552 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 5553 pins = "gpio27"; 5554 function = "gpio"; 5555 }; 5556 5557 qup_spi8_data_clk: qup-spi8-data-clk-state { 5558 pins = "gpio24", "gpio25", 5559 "gpio26"; 5560 function = "qup8"; 5561 }; 5562 5563 qup_spi9_cs: qup-spi9-cs-state { 5564 pins = "gpio128"; 5565 function = "qup9"; 5566 }; 5567 5568 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 5569 pins = "gpio128"; 5570 function = "gpio"; 5571 }; 5572 5573 qup_spi9_data_clk: qup-spi9-data-clk-state { 5574 pins = "gpio125", "gpio126", 5575 "gpio127"; 5576 function = "qup9"; 5577 }; 5578 5579 qup_spi10_cs: qup-spi10-cs-state { 5580 pins = "gpio132"; 5581 function = "qup10"; 5582 }; 5583 5584 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 5585 pins = "gpio132"; 5586 function = "gpio"; 5587 }; 5588 5589 qup_spi10_data_clk: qup-spi10-data-clk-state { 5590 pins = "gpio129", "gpio130", 5591 "gpio131"; 5592 function = "qup10"; 5593 }; 5594 5595 qup_spi11_cs: qup-spi11-cs-state { 5596 pins = "gpio63"; 5597 function = "qup11"; 5598 }; 5599 5600 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 5601 pins = "gpio63"; 5602 function = "gpio"; 5603 }; 5604 5605 qup_spi11_data_clk: qup-spi11-data-clk-state { 5606 pins = "gpio60", "gpio61", 5607 "gpio62"; 5608 function = "qup11"; 5609 }; 5610 5611 qup_spi12_cs: qup-spi12-cs-state { 5612 pins = "gpio35"; 5613 function = "qup12"; 5614 }; 5615 5616 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 5617 pins = "gpio35"; 5618 function = "gpio"; 5619 }; 5620 5621 qup_spi12_data_clk: qup-spi12-data-clk-state { 5622 pins = "gpio32", "gpio33", 5623 "gpio34"; 5624 function = "qup12"; 5625 }; 5626 5627 qup_spi13_cs: qup-spi13-cs-state { 5628 pins = "gpio39"; 5629 function = "qup13"; 5630 }; 5631 5632 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 5633 pins = "gpio39"; 5634 function = "gpio"; 5635 }; 5636 5637 qup_spi13_data_clk: qup-spi13-data-clk-state { 5638 pins = "gpio36", "gpio37", 5639 "gpio38"; 5640 function = "qup13"; 5641 }; 5642 5643 qup_spi14_cs: qup-spi14-cs-state { 5644 pins = "gpio43"; 5645 function = "qup14"; 5646 }; 5647 5648 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 5649 pins = "gpio43"; 5650 function = "gpio"; 5651 }; 5652 5653 qup_spi14_data_clk: qup-spi14-data-clk-state { 5654 pins = "gpio40", "gpio41", 5655 "gpio42"; 5656 function = "qup14"; 5657 }; 5658 5659 qup_spi15_cs: qup-spi15-cs-state { 5660 pins = "gpio47"; 5661 function = "qup15"; 5662 }; 5663 5664 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 5665 pins = "gpio47"; 5666 function = "gpio"; 5667 }; 5668 5669 qup_spi15_data_clk: qup-spi15-data-clk-state { 5670 pins = "gpio44", "gpio45", 5671 "gpio46"; 5672 function = "qup15"; 5673 }; 5674 5675 qup_spi16_cs: qup-spi16-cs-state { 5676 pins = "gpio51"; 5677 function = "qup16"; 5678 }; 5679 5680 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state { 5681 pins = "gpio51"; 5682 function = "gpio"; 5683 }; 5684 5685 qup_spi16_data_clk: qup-spi16-data-clk-state { 5686 pins = "gpio48", "gpio49", 5687 "gpio50"; 5688 function = "qup16"; 5689 }; 5690 5691 qup_spi17_cs: qup-spi17-cs-state { 5692 pins = "gpio55"; 5693 function = "qup17"; 5694 }; 5695 5696 qup_spi17_cs_gpio: qup-spi17-cs-gpio-state { 5697 pins = "gpio55"; 5698 function = "gpio"; 5699 }; 5700 5701 qup_spi17_data_clk: qup-spi17-data-clk-state { 5702 pins = "gpio52", "gpio53", 5703 "gpio54"; 5704 function = "qup17"; 5705 }; 5706 5707 qup_spi18_cs: qup-spi18-cs-state { 5708 pins = "gpio59"; 5709 function = "qup18"; 5710 }; 5711 5712 qup_spi18_cs_gpio: qup-spi18-cs-gpio-state { 5713 pins = "gpio59"; 5714 function = "gpio"; 5715 }; 5716 5717 qup_spi18_data_clk: qup-spi18-data-clk-state { 5718 pins = "gpio56", "gpio57", 5719 "gpio58"; 5720 function = "qup18"; 5721 }; 5722 5723 qup_spi19_cs: qup-spi19-cs-state { 5724 pins = "gpio3"; 5725 function = "qup19"; 5726 }; 5727 5728 qup_spi19_cs_gpio: qup-spi19-cs-gpio-state { 5729 pins = "gpio3"; 5730 function = "gpio"; 5731 }; 5732 5733 qup_spi19_data_clk: qup-spi19-data-clk-state { 5734 pins = "gpio0", "gpio1", 5735 "gpio2"; 5736 function = "qup19"; 5737 }; 5738 5739 qup_uart2_default: qup-uart2-default-state { 5740 pins = "gpio117", "gpio118"; 5741 function = "qup2"; 5742 }; 5743 5744 qup_uart6_default: qup-uart6-default-state { 5745 pins = "gpio16", "gpio17", "gpio18", "gpio19"; 5746 function = "qup6"; 5747 }; 5748 5749 qup_uart12_default: qup-uart12-default-state { 5750 pins = "gpio34", "gpio35"; 5751 function = "qup12"; 5752 }; 5753 5754 qup_uart17_default: qup-uart17-default-state { 5755 pins = "gpio52", "gpio53", "gpio54", "gpio55"; 5756 function = "qup17"; 5757 }; 5758 5759 qup_uart18_default: qup-uart18-default-state { 5760 pins = "gpio58", "gpio59"; 5761 function = "qup18"; 5762 }; 5763 5764 tert_mi2s_active: tert-mi2s-active-state { 5765 sck-pins { 5766 pins = "gpio133"; 5767 function = "mi2s2_sck"; 5768 drive-strength = <8>; 5769 bias-disable; 5770 }; 5771 5772 data0-pins { 5773 pins = "gpio134"; 5774 function = "mi2s2_data0"; 5775 drive-strength = <8>; 5776 bias-disable; 5777 output-high; 5778 }; 5779 5780 ws-pins { 5781 pins = "gpio135"; 5782 function = "mi2s2_ws"; 5783 drive-strength = <8>; 5784 output-high; 5785 }; 5786 }; 5787 5788 sdc2_sleep_state: sdc2-sleep-state { 5789 clk-pins { 5790 pins = "sdc2_clk"; 5791 drive-strength = <2>; 5792 bias-disable; 5793 }; 5794 5795 cmd-pins { 5796 pins = "sdc2_cmd"; 5797 drive-strength = <2>; 5798 bias-pull-up; 5799 }; 5800 5801 data-pins { 5802 pins = "sdc2_data"; 5803 drive-strength = <2>; 5804 bias-pull-up; 5805 }; 5806 }; 5807 5808 pcie0_default_state: pcie0-default-state { 5809 perst-pins { 5810 pins = "gpio79"; 5811 function = "gpio"; 5812 drive-strength = <2>; 5813 bias-pull-down; 5814 }; 5815 5816 clkreq-pins { 5817 pins = "gpio80"; 5818 function = "pci_e0"; 5819 drive-strength = <2>; 5820 bias-pull-up; 5821 }; 5822 5823 wake-pins { 5824 pins = "gpio81"; 5825 function = "gpio"; 5826 drive-strength = <2>; 5827 bias-pull-up; 5828 }; 5829 }; 5830 5831 pcie1_default_state: pcie1-default-state { 5832 perst-pins { 5833 pins = "gpio82"; 5834 function = "gpio"; 5835 drive-strength = <2>; 5836 bias-pull-down; 5837 }; 5838 5839 clkreq-pins { 5840 pins = "gpio83"; 5841 function = "pci_e1"; 5842 drive-strength = <2>; 5843 bias-pull-up; 5844 }; 5845 5846 wake-pins { 5847 pins = "gpio84"; 5848 function = "gpio"; 5849 drive-strength = <2>; 5850 bias-pull-up; 5851 }; 5852 }; 5853 5854 pcie2_default_state: pcie2-default-state { 5855 perst-pins { 5856 pins = "gpio85"; 5857 function = "gpio"; 5858 drive-strength = <2>; 5859 bias-pull-down; 5860 }; 5861 5862 clkreq-pins { 5863 pins = "gpio86"; 5864 function = "pci_e2"; 5865 drive-strength = <2>; 5866 bias-pull-up; 5867 }; 5868 5869 wake-pins { 5870 pins = "gpio87"; 5871 function = "gpio"; 5872 drive-strength = <2>; 5873 bias-pull-up; 5874 }; 5875 }; 5876 }; 5877 5878 apps_smmu: iommu@15000000 { 5879 compatible = "qcom,sm8250-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 5880 reg = <0 0x15000000 0 0x100000>; 5881 #iommu-cells = <2>; 5882 #global-interrupts = <2>; 5883 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 5884 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5885 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5886 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5887 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5888 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5889 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5890 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5891 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5892 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5893 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5894 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5895 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5896 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5897 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5898 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5899 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5900 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5901 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5902 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5903 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5904 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5905 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5906 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5907 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5908 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5909 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5910 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5911 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5912 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5913 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5914 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5915 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5916 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5917 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5918 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5919 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5920 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5921 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5922 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5923 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5924 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5925 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5926 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5927 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5928 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5929 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5930 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5931 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5932 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5933 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5934 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5935 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5936 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5937 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5938 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5939 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5940 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5941 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5942 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5943 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5944 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5945 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5946 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5947 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5948 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5949 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5950 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5951 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5952 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5953 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5954 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5955 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5956 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5957 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5958 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5959 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5960 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5961 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5962 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5963 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5964 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5965 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5966 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5967 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5968 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5969 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5970 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5971 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5972 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5973 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5974 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5975 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5976 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5977 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5978 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5979 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 5980 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 5981 dma-coherent; 5982 }; 5983 5984 adsp: remoteproc@17300000 { 5985 compatible = "qcom,sm8250-adsp-pas"; 5986 reg = <0 0x17300000 0 0x100>; 5987 5988 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 5989 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 5990 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 5991 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 5992 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 5993 interrupt-names = "wdog", "fatal", "ready", 5994 "handover", "stop-ack"; 5995 5996 clocks = <&rpmhcc RPMH_CXO_CLK>; 5997 clock-names = "xo"; 5998 5999 power-domains = <&rpmhpd RPMHPD_LCX>, 6000 <&rpmhpd RPMHPD_LMX>; 6001 power-domain-names = "lcx", "lmx"; 6002 6003 memory-region = <&adsp_mem>; 6004 6005 qcom,qmp = <&aoss_qmp>; 6006 6007 qcom,smem-states = <&smp2p_adsp_out 0>; 6008 qcom,smem-state-names = "stop"; 6009 6010 status = "disabled"; 6011 6012 glink-edge { 6013 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 6014 IPCC_MPROC_SIGNAL_GLINK_QMP 6015 IRQ_TYPE_EDGE_RISING>; 6016 mboxes = <&ipcc IPCC_CLIENT_LPASS 6017 IPCC_MPROC_SIGNAL_GLINK_QMP>; 6018 6019 label = "lpass"; 6020 qcom,remote-pid = <2>; 6021 6022 apr { 6023 compatible = "qcom,apr-v2"; 6024 qcom,glink-channels = "apr_audio_svc"; 6025 qcom,domain = <APR_DOMAIN_ADSP>; 6026 #address-cells = <1>; 6027 #size-cells = <0>; 6028 6029 service@3 { 6030 reg = <APR_SVC_ADSP_CORE>; 6031 compatible = "qcom,q6core"; 6032 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 6033 }; 6034 6035 q6afe: service@4 { 6036 compatible = "qcom,q6afe"; 6037 reg = <APR_SVC_AFE>; 6038 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 6039 q6afedai: dais { 6040 compatible = "qcom,q6afe-dais"; 6041 #address-cells = <1>; 6042 #size-cells = <0>; 6043 #sound-dai-cells = <1>; 6044 }; 6045 6046 q6afecc: clock-controller { 6047 compatible = "qcom,q6afe-clocks"; 6048 #clock-cells = <2>; 6049 }; 6050 }; 6051 6052 q6asm: service@7 { 6053 compatible = "qcom,q6asm"; 6054 reg = <APR_SVC_ASM>; 6055 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 6056 q6asmdai: dais { 6057 compatible = "qcom,q6asm-dais"; 6058 #address-cells = <1>; 6059 #size-cells = <0>; 6060 #sound-dai-cells = <1>; 6061 iommus = <&apps_smmu 0x1801 0x0>; 6062 }; 6063 }; 6064 6065 q6adm: service@8 { 6066 compatible = "qcom,q6adm"; 6067 reg = <APR_SVC_ADM>; 6068 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 6069 q6routing: routing { 6070 compatible = "qcom,q6adm-routing"; 6071 #sound-dai-cells = <0>; 6072 }; 6073 }; 6074 }; 6075 6076 fastrpc { 6077 compatible = "qcom,fastrpc"; 6078 qcom,glink-channels = "fastrpcglink-apps-dsp"; 6079 label = "adsp"; 6080 qcom,non-secure-domain; 6081 #address-cells = <1>; 6082 #size-cells = <0>; 6083 6084 compute-cb@3 { 6085 compatible = "qcom,fastrpc-compute-cb"; 6086 reg = <3>; 6087 iommus = <&apps_smmu 0x1803 0x0>; 6088 }; 6089 6090 compute-cb@4 { 6091 compatible = "qcom,fastrpc-compute-cb"; 6092 reg = <4>; 6093 iommus = <&apps_smmu 0x1804 0x0>; 6094 }; 6095 6096 compute-cb@5 { 6097 compatible = "qcom,fastrpc-compute-cb"; 6098 reg = <5>; 6099 iommus = <&apps_smmu 0x1805 0x0>; 6100 }; 6101 }; 6102 }; 6103 }; 6104 6105 intc: interrupt-controller@17a00000 { 6106 compatible = "arm,gic-v3"; 6107 #address-cells = <0>; 6108 #interrupt-cells = <3>; 6109 interrupt-controller; 6110 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 6111 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 6112 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 6113 }; 6114 6115 watchdog@17c10000 { 6116 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; 6117 reg = <0 0x17c10000 0 0x1000>; 6118 clocks = <&sleep_clk>; 6119 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 6120 }; 6121 6122 timer@17c20000 { 6123 #address-cells = <1>; 6124 #size-cells = <1>; 6125 ranges = <0 0 0 0x20000000>; 6126 compatible = "arm,armv7-timer-mem"; 6127 reg = <0x0 0x17c20000 0x0 0x1000>; 6128 clock-frequency = <19200000>; 6129 6130 frame@17c21000 { 6131 frame-number = <0>; 6132 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 6133 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 6134 reg = <0x17c21000 0x1000>, 6135 <0x17c22000 0x1000>; 6136 }; 6137 6138 frame@17c23000 { 6139 frame-number = <1>; 6140 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 6141 reg = <0x17c23000 0x1000>; 6142 status = "disabled"; 6143 }; 6144 6145 frame@17c25000 { 6146 frame-number = <2>; 6147 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 6148 reg = <0x17c25000 0x1000>; 6149 status = "disabled"; 6150 }; 6151 6152 frame@17c27000 { 6153 frame-number = <3>; 6154 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 6155 reg = <0x17c27000 0x1000>; 6156 status = "disabled"; 6157 }; 6158 6159 frame@17c29000 { 6160 frame-number = <4>; 6161 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 6162 reg = <0x17c29000 0x1000>; 6163 status = "disabled"; 6164 }; 6165 6166 frame@17c2b000 { 6167 frame-number = <5>; 6168 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 6169 reg = <0x17c2b000 0x1000>; 6170 status = "disabled"; 6171 }; 6172 6173 frame@17c2d000 { 6174 frame-number = <6>; 6175 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 6176 reg = <0x17c2d000 0x1000>; 6177 status = "disabled"; 6178 }; 6179 }; 6180 6181 apps_rsc: rsc@18200000 { 6182 label = "apps_rsc"; 6183 compatible = "qcom,rpmh-rsc"; 6184 reg = <0x0 0x18200000 0x0 0x10000>, 6185 <0x0 0x18210000 0x0 0x10000>, 6186 <0x0 0x18220000 0x0 0x10000>; 6187 reg-names = "drv-0", "drv-1", "drv-2"; 6188 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 6189 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 6190 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 6191 qcom,tcs-offset = <0xd00>; 6192 qcom,drv-id = <2>; 6193 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 6194 <WAKE_TCS 3>, <CONTROL_TCS 1>; 6195 power-domains = <&cluster_pd>; 6196 6197 rpmhcc: clock-controller { 6198 compatible = "qcom,sm8250-rpmh-clk"; 6199 #clock-cells = <1>; 6200 clock-names = "xo"; 6201 clocks = <&xo_board>; 6202 }; 6203 6204 rpmhpd: power-controller { 6205 compatible = "qcom,sm8250-rpmhpd"; 6206 #power-domain-cells = <1>; 6207 operating-points-v2 = <&rpmhpd_opp_table>; 6208 6209 rpmhpd_opp_table: opp-table { 6210 compatible = "operating-points-v2"; 6211 6212 rpmhpd_opp_ret: opp1 { 6213 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 6214 }; 6215 6216 rpmhpd_opp_min_svs: opp2 { 6217 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 6218 }; 6219 6220 rpmhpd_opp_low_svs: opp3 { 6221 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 6222 }; 6223 6224 rpmhpd_opp_svs: opp4 { 6225 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 6226 }; 6227 6228 rpmhpd_opp_svs_l1: opp5 { 6229 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 6230 }; 6231 6232 rpmhpd_opp_nom: opp6 { 6233 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 6234 }; 6235 6236 rpmhpd_opp_nom_l1: opp7 { 6237 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 6238 }; 6239 6240 rpmhpd_opp_nom_l2: opp8 { 6241 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 6242 }; 6243 6244 rpmhpd_opp_turbo: opp9 { 6245 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 6246 }; 6247 6248 rpmhpd_opp_turbo_l1: opp10 { 6249 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 6250 }; 6251 }; 6252 }; 6253 6254 apps_bcm_voter: bcm-voter { 6255 compatible = "qcom,bcm-voter"; 6256 }; 6257 }; 6258 6259 epss_l3: interconnect@18590000 { 6260 compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3"; 6261 reg = <0 0x18590000 0 0x1000>; 6262 6263 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 6264 clock-names = "xo", "alternate"; 6265 6266 #interconnect-cells = <1>; 6267 }; 6268 6269 cpufreq_hw: cpufreq@18591000 { 6270 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; 6271 reg = <0 0x18591000 0 0x1000>, 6272 <0 0x18592000 0 0x1000>, 6273 <0 0x18593000 0 0x1000>; 6274 reg-names = "freq-domain0", "freq-domain1", 6275 "freq-domain2"; 6276 6277 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 6278 clock-names = "xo", "alternate"; 6279 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 6280 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 6281 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 6282 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 6283 #freq-domain-cells = <1>; 6284 #clock-cells = <1>; 6285 }; 6286 }; 6287 6288 sound: sound { 6289 }; 6290 6291 timer { 6292 compatible = "arm,armv8-timer"; 6293 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6294 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6295 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6296 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6297 }; 6298 6299 thermal-zones { 6300 cpu0-thermal { 6301 polling-delay-passive = <250>; 6302 6303 thermal-sensors = <&tsens0 1>; 6304 6305 trips { 6306 cpu0_alert0: trip-point0 { 6307 temperature = <90000>; 6308 hysteresis = <2000>; 6309 type = "passive"; 6310 }; 6311 6312 cpu0_alert1: trip-point1 { 6313 temperature = <95000>; 6314 hysteresis = <2000>; 6315 type = "passive"; 6316 }; 6317 6318 cpu0_crit: cpu-crit { 6319 temperature = <110000>; 6320 hysteresis = <1000>; 6321 type = "critical"; 6322 }; 6323 }; 6324 6325 cooling-maps { 6326 map0 { 6327 trip = <&cpu0_alert0>; 6328 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6329 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6330 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6331 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6332 }; 6333 map1 { 6334 trip = <&cpu0_alert1>; 6335 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6336 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6337 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6338 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6339 }; 6340 }; 6341 }; 6342 6343 cpu1-thermal { 6344 polling-delay-passive = <250>; 6345 6346 thermal-sensors = <&tsens0 2>; 6347 6348 trips { 6349 cpu1_alert0: trip-point0 { 6350 temperature = <90000>; 6351 hysteresis = <2000>; 6352 type = "passive"; 6353 }; 6354 6355 cpu1_alert1: trip-point1 { 6356 temperature = <95000>; 6357 hysteresis = <2000>; 6358 type = "passive"; 6359 }; 6360 6361 cpu1_crit: cpu-crit { 6362 temperature = <110000>; 6363 hysteresis = <1000>; 6364 type = "critical"; 6365 }; 6366 }; 6367 6368 cooling-maps { 6369 map0 { 6370 trip = <&cpu1_alert0>; 6371 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6372 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6373 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6374 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6375 }; 6376 map1 { 6377 trip = <&cpu1_alert1>; 6378 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6379 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6380 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6381 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6382 }; 6383 }; 6384 }; 6385 6386 cpu2-thermal { 6387 polling-delay-passive = <250>; 6388 6389 thermal-sensors = <&tsens0 3>; 6390 6391 trips { 6392 cpu2_alert0: trip-point0 { 6393 temperature = <90000>; 6394 hysteresis = <2000>; 6395 type = "passive"; 6396 }; 6397 6398 cpu2_alert1: trip-point1 { 6399 temperature = <95000>; 6400 hysteresis = <2000>; 6401 type = "passive"; 6402 }; 6403 6404 cpu2_crit: cpu-crit { 6405 temperature = <110000>; 6406 hysteresis = <1000>; 6407 type = "critical"; 6408 }; 6409 }; 6410 6411 cooling-maps { 6412 map0 { 6413 trip = <&cpu2_alert0>; 6414 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6415 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6416 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6417 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6418 }; 6419 map1 { 6420 trip = <&cpu2_alert1>; 6421 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6422 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6423 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6424 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6425 }; 6426 }; 6427 }; 6428 6429 cpu3-thermal { 6430 polling-delay-passive = <250>; 6431 6432 thermal-sensors = <&tsens0 4>; 6433 6434 trips { 6435 cpu3_alert0: trip-point0 { 6436 temperature = <90000>; 6437 hysteresis = <2000>; 6438 type = "passive"; 6439 }; 6440 6441 cpu3_alert1: trip-point1 { 6442 temperature = <95000>; 6443 hysteresis = <2000>; 6444 type = "passive"; 6445 }; 6446 6447 cpu3_crit: cpu-crit { 6448 temperature = <110000>; 6449 hysteresis = <1000>; 6450 type = "critical"; 6451 }; 6452 }; 6453 6454 cooling-maps { 6455 map0 { 6456 trip = <&cpu3_alert0>; 6457 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6458 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6459 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6460 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6461 }; 6462 map1 { 6463 trip = <&cpu3_alert1>; 6464 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6465 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6466 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6467 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6468 }; 6469 }; 6470 }; 6471 6472 cpu4-top-thermal { 6473 polling-delay-passive = <250>; 6474 6475 thermal-sensors = <&tsens0 7>; 6476 6477 trips { 6478 cpu4_top_alert0: trip-point0 { 6479 temperature = <90000>; 6480 hysteresis = <2000>; 6481 type = "passive"; 6482 }; 6483 6484 cpu4_top_alert1: trip-point1 { 6485 temperature = <95000>; 6486 hysteresis = <2000>; 6487 type = "passive"; 6488 }; 6489 6490 cpu4_top_crit: cpu-crit { 6491 temperature = <110000>; 6492 hysteresis = <1000>; 6493 type = "critical"; 6494 }; 6495 }; 6496 6497 cooling-maps { 6498 map0 { 6499 trip = <&cpu4_top_alert0>; 6500 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6501 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6502 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6503 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6504 }; 6505 map1 { 6506 trip = <&cpu4_top_alert1>; 6507 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6508 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6509 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6510 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6511 }; 6512 }; 6513 }; 6514 6515 cpu5-top-thermal { 6516 polling-delay-passive = <250>; 6517 6518 thermal-sensors = <&tsens0 8>; 6519 6520 trips { 6521 cpu5_top_alert0: trip-point0 { 6522 temperature = <90000>; 6523 hysteresis = <2000>; 6524 type = "passive"; 6525 }; 6526 6527 cpu5_top_alert1: trip-point1 { 6528 temperature = <95000>; 6529 hysteresis = <2000>; 6530 type = "passive"; 6531 }; 6532 6533 cpu5_top_crit: cpu-crit { 6534 temperature = <110000>; 6535 hysteresis = <1000>; 6536 type = "critical"; 6537 }; 6538 }; 6539 6540 cooling-maps { 6541 map0 { 6542 trip = <&cpu5_top_alert0>; 6543 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6544 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6545 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6546 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6547 }; 6548 map1 { 6549 trip = <&cpu5_top_alert1>; 6550 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6551 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6552 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6553 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6554 }; 6555 }; 6556 }; 6557 6558 cpu6-top-thermal { 6559 polling-delay-passive = <250>; 6560 6561 thermal-sensors = <&tsens0 9>; 6562 6563 trips { 6564 cpu6_top_alert0: trip-point0 { 6565 temperature = <90000>; 6566 hysteresis = <2000>; 6567 type = "passive"; 6568 }; 6569 6570 cpu6_top_alert1: trip-point1 { 6571 temperature = <95000>; 6572 hysteresis = <2000>; 6573 type = "passive"; 6574 }; 6575 6576 cpu6_top_crit: cpu-crit { 6577 temperature = <110000>; 6578 hysteresis = <1000>; 6579 type = "critical"; 6580 }; 6581 }; 6582 6583 cooling-maps { 6584 map0 { 6585 trip = <&cpu6_top_alert0>; 6586 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6587 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6588 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6589 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6590 }; 6591 map1 { 6592 trip = <&cpu6_top_alert1>; 6593 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6594 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6595 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6596 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6597 }; 6598 }; 6599 }; 6600 6601 cpu7-top-thermal { 6602 polling-delay-passive = <250>; 6603 6604 thermal-sensors = <&tsens0 10>; 6605 6606 trips { 6607 cpu7_top_alert0: trip-point0 { 6608 temperature = <90000>; 6609 hysteresis = <2000>; 6610 type = "passive"; 6611 }; 6612 6613 cpu7_top_alert1: trip-point1 { 6614 temperature = <95000>; 6615 hysteresis = <2000>; 6616 type = "passive"; 6617 }; 6618 6619 cpu7_top_crit: cpu-crit { 6620 temperature = <110000>; 6621 hysteresis = <1000>; 6622 type = "critical"; 6623 }; 6624 }; 6625 6626 cooling-maps { 6627 map0 { 6628 trip = <&cpu7_top_alert0>; 6629 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6630 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6631 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6632 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6633 }; 6634 map1 { 6635 trip = <&cpu7_top_alert1>; 6636 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6637 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6638 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6639 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6640 }; 6641 }; 6642 }; 6643 6644 cpu4-bottom-thermal { 6645 polling-delay-passive = <250>; 6646 6647 thermal-sensors = <&tsens0 11>; 6648 6649 trips { 6650 cpu4_bottom_alert0: trip-point0 { 6651 temperature = <90000>; 6652 hysteresis = <2000>; 6653 type = "passive"; 6654 }; 6655 6656 cpu4_bottom_alert1: trip-point1 { 6657 temperature = <95000>; 6658 hysteresis = <2000>; 6659 type = "passive"; 6660 }; 6661 6662 cpu4_bottom_crit: cpu-crit { 6663 temperature = <110000>; 6664 hysteresis = <1000>; 6665 type = "critical"; 6666 }; 6667 }; 6668 6669 cooling-maps { 6670 map0 { 6671 trip = <&cpu4_bottom_alert0>; 6672 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6673 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6674 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6675 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6676 }; 6677 map1 { 6678 trip = <&cpu4_bottom_alert1>; 6679 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6680 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6681 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6682 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6683 }; 6684 }; 6685 }; 6686 6687 cpu5-bottom-thermal { 6688 polling-delay-passive = <250>; 6689 6690 thermal-sensors = <&tsens0 12>; 6691 6692 trips { 6693 cpu5_bottom_alert0: trip-point0 { 6694 temperature = <90000>; 6695 hysteresis = <2000>; 6696 type = "passive"; 6697 }; 6698 6699 cpu5_bottom_alert1: trip-point1 { 6700 temperature = <95000>; 6701 hysteresis = <2000>; 6702 type = "passive"; 6703 }; 6704 6705 cpu5_bottom_crit: cpu-crit { 6706 temperature = <110000>; 6707 hysteresis = <1000>; 6708 type = "critical"; 6709 }; 6710 }; 6711 6712 cooling-maps { 6713 map0 { 6714 trip = <&cpu5_bottom_alert0>; 6715 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6716 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6717 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6718 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6719 }; 6720 map1 { 6721 trip = <&cpu5_bottom_alert1>; 6722 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6723 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6724 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6725 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6726 }; 6727 }; 6728 }; 6729 6730 cpu6-bottom-thermal { 6731 polling-delay-passive = <250>; 6732 6733 thermal-sensors = <&tsens0 13>; 6734 6735 trips { 6736 cpu6_bottom_alert0: trip-point0 { 6737 temperature = <90000>; 6738 hysteresis = <2000>; 6739 type = "passive"; 6740 }; 6741 6742 cpu6_bottom_alert1: trip-point1 { 6743 temperature = <95000>; 6744 hysteresis = <2000>; 6745 type = "passive"; 6746 }; 6747 6748 cpu6_bottom_crit: cpu-crit { 6749 temperature = <110000>; 6750 hysteresis = <1000>; 6751 type = "critical"; 6752 }; 6753 }; 6754 6755 cooling-maps { 6756 map0 { 6757 trip = <&cpu6_bottom_alert0>; 6758 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6759 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6760 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6761 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6762 }; 6763 map1 { 6764 trip = <&cpu6_bottom_alert1>; 6765 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6766 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6767 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6768 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6769 }; 6770 }; 6771 }; 6772 6773 cpu7-bottom-thermal { 6774 polling-delay-passive = <250>; 6775 6776 thermal-sensors = <&tsens0 14>; 6777 6778 trips { 6779 cpu7_bottom_alert0: trip-point0 { 6780 temperature = <90000>; 6781 hysteresis = <2000>; 6782 type = "passive"; 6783 }; 6784 6785 cpu7_bottom_alert1: trip-point1 { 6786 temperature = <95000>; 6787 hysteresis = <2000>; 6788 type = "passive"; 6789 }; 6790 6791 cpu7_bottom_crit: cpu-crit { 6792 temperature = <110000>; 6793 hysteresis = <1000>; 6794 type = "critical"; 6795 }; 6796 }; 6797 6798 cooling-maps { 6799 map0 { 6800 trip = <&cpu7_bottom_alert0>; 6801 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6802 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6803 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6804 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6805 }; 6806 map1 { 6807 trip = <&cpu7_bottom_alert1>; 6808 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6809 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6810 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6811 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6812 }; 6813 }; 6814 }; 6815 6816 aoss0-thermal { 6817 polling-delay-passive = <250>; 6818 6819 thermal-sensors = <&tsens0 0>; 6820 6821 trips { 6822 aoss0_alert0: trip-point0 { 6823 temperature = <90000>; 6824 hysteresis = <2000>; 6825 type = "hot"; 6826 }; 6827 }; 6828 }; 6829 6830 cluster0-thermal { 6831 polling-delay-passive = <250>; 6832 6833 thermal-sensors = <&tsens0 5>; 6834 6835 trips { 6836 cluster0_alert0: trip-point0 { 6837 temperature = <90000>; 6838 hysteresis = <2000>; 6839 type = "hot"; 6840 }; 6841 cluster0_crit: cluster0-crit { 6842 temperature = <110000>; 6843 hysteresis = <2000>; 6844 type = "critical"; 6845 }; 6846 }; 6847 }; 6848 6849 cluster1-thermal { 6850 polling-delay-passive = <250>; 6851 6852 thermal-sensors = <&tsens0 6>; 6853 6854 trips { 6855 cluster1_alert0: trip-point0 { 6856 temperature = <90000>; 6857 hysteresis = <2000>; 6858 type = "hot"; 6859 }; 6860 cluster1_crit: cluster1-crit { 6861 temperature = <110000>; 6862 hysteresis = <2000>; 6863 type = "critical"; 6864 }; 6865 }; 6866 }; 6867 6868 gpu-top-thermal { 6869 polling-delay-passive = <250>; 6870 6871 thermal-sensors = <&tsens0 15>; 6872 6873 cooling-maps { 6874 map0 { 6875 trip = <&gpu_top_alert0>; 6876 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6877 }; 6878 }; 6879 6880 trips { 6881 gpu_top_alert0: trip-point0 { 6882 temperature = <85000>; 6883 hysteresis = <1000>; 6884 type = "passive"; 6885 }; 6886 6887 trip-point1 { 6888 temperature = <90000>; 6889 hysteresis = <1000>; 6890 type = "hot"; 6891 }; 6892 6893 trip-point2 { 6894 temperature = <110000>; 6895 hysteresis = <1000>; 6896 type = "critical"; 6897 }; 6898 }; 6899 }; 6900 6901 aoss1-thermal { 6902 polling-delay-passive = <250>; 6903 6904 thermal-sensors = <&tsens1 0>; 6905 6906 trips { 6907 aoss1_alert0: trip-point0 { 6908 temperature = <90000>; 6909 hysteresis = <2000>; 6910 type = "hot"; 6911 }; 6912 }; 6913 }; 6914 6915 wlan-thermal { 6916 polling-delay-passive = <250>; 6917 6918 thermal-sensors = <&tsens1 1>; 6919 6920 trips { 6921 wlan_alert0: trip-point0 { 6922 temperature = <90000>; 6923 hysteresis = <2000>; 6924 type = "hot"; 6925 }; 6926 }; 6927 }; 6928 6929 video-thermal { 6930 polling-delay-passive = <250>; 6931 6932 thermal-sensors = <&tsens1 2>; 6933 6934 trips { 6935 video_alert0: trip-point0 { 6936 temperature = <90000>; 6937 hysteresis = <2000>; 6938 type = "hot"; 6939 }; 6940 }; 6941 }; 6942 6943 mem-thermal { 6944 polling-delay-passive = <250>; 6945 6946 thermal-sensors = <&tsens1 3>; 6947 6948 trips { 6949 mem_alert0: trip-point0 { 6950 temperature = <90000>; 6951 hysteresis = <2000>; 6952 type = "hot"; 6953 }; 6954 }; 6955 }; 6956 6957 q6-hvx-thermal { 6958 polling-delay-passive = <250>; 6959 6960 thermal-sensors = <&tsens1 4>; 6961 6962 trips { 6963 q6_hvx_alert0: trip-point0 { 6964 temperature = <90000>; 6965 hysteresis = <2000>; 6966 type = "hot"; 6967 }; 6968 }; 6969 }; 6970 6971 camera-thermal { 6972 polling-delay-passive = <250>; 6973 6974 thermal-sensors = <&tsens1 5>; 6975 6976 trips { 6977 camera_alert0: trip-point0 { 6978 temperature = <90000>; 6979 hysteresis = <2000>; 6980 type = "hot"; 6981 }; 6982 }; 6983 }; 6984 6985 compute-thermal { 6986 polling-delay-passive = <250>; 6987 6988 thermal-sensors = <&tsens1 6>; 6989 6990 trips { 6991 compute_alert0: trip-point0 { 6992 temperature = <90000>; 6993 hysteresis = <2000>; 6994 type = "hot"; 6995 }; 6996 }; 6997 }; 6998 6999 npu-thermal { 7000 polling-delay-passive = <250>; 7001 7002 thermal-sensors = <&tsens1 7>; 7003 7004 trips { 7005 npu_alert0: trip-point0 { 7006 temperature = <90000>; 7007 hysteresis = <2000>; 7008 type = "hot"; 7009 }; 7010 }; 7011 }; 7012 7013 gpu-bottom-thermal { 7014 polling-delay-passive = <250>; 7015 7016 thermal-sensors = <&tsens1 8>; 7017 7018 cooling-maps { 7019 map0 { 7020 trip = <&gpu_bottom_alert0>; 7021 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7022 }; 7023 }; 7024 7025 trips { 7026 gpu_bottom_alert0: trip-point0 { 7027 temperature = <85000>; 7028 hysteresis = <1000>; 7029 type = "passive"; 7030 }; 7031 7032 trip-point1 { 7033 temperature = <90000>; 7034 hysteresis = <1000>; 7035 type = "hot"; 7036 }; 7037 7038 trip-point2 { 7039 temperature = <110000>; 7040 hysteresis = <1000>; 7041 type = "critical"; 7042 }; 7043 }; 7044 }; 7045 }; 7046}; 7047