1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 9#include <dt-bindings/clock/qcom,gcc-sm8250.h> 10#include <dt-bindings/clock/qcom,gpucc-sm8250.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interconnect/qcom,osm-l3.h> 15#include <dt-bindings/interconnect/qcom,sm8250.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/phy/phy-qcom-qmp.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/power/qcom,rpmhpd.h> 20#include <dt-bindings/soc/qcom,apr.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/sound/qcom,q6afe.h> 23#include <dt-bindings/thermal/thermal.h> 24#include <dt-bindings/clock/qcom,camcc-sm8250.h> 25#include <dt-bindings/clock/qcom,videocc-sm8250.h> 26 27/ { 28 interrupt-parent = <&intc>; 29 30 #address-cells = <2>; 31 #size-cells = <2>; 32 33 aliases { 34 i2c0 = &i2c0; 35 i2c1 = &i2c1; 36 i2c2 = &i2c2; 37 i2c3 = &i2c3; 38 i2c4 = &i2c4; 39 i2c5 = &i2c5; 40 i2c6 = &i2c6; 41 i2c7 = &i2c7; 42 i2c8 = &i2c8; 43 i2c9 = &i2c9; 44 i2c10 = &i2c10; 45 i2c11 = &i2c11; 46 i2c12 = &i2c12; 47 i2c13 = &i2c13; 48 i2c14 = &i2c14; 49 i2c15 = &i2c15; 50 i2c16 = &i2c16; 51 i2c17 = &i2c17; 52 i2c18 = &i2c18; 53 i2c19 = &i2c19; 54 spi0 = &spi0; 55 spi1 = &spi1; 56 spi2 = &spi2; 57 spi3 = &spi3; 58 spi4 = &spi4; 59 spi5 = &spi5; 60 spi6 = &spi6; 61 spi7 = &spi7; 62 spi8 = &spi8; 63 spi9 = &spi9; 64 spi10 = &spi10; 65 spi11 = &spi11; 66 spi12 = &spi12; 67 spi13 = &spi13; 68 spi14 = &spi14; 69 spi15 = &spi15; 70 spi16 = &spi16; 71 spi17 = &spi17; 72 spi18 = &spi18; 73 spi19 = &spi19; 74 }; 75 76 chosen { }; 77 78 clocks { 79 xo_board: xo-board { 80 compatible = "fixed-clock"; 81 #clock-cells = <0>; 82 clock-frequency = <38400000>; 83 clock-output-names = "xo_board"; 84 }; 85 86 sleep_clk: sleep-clk { 87 compatible = "fixed-clock"; 88 clock-frequency = <32764>; 89 #clock-cells = <0>; 90 }; 91 }; 92 93 cpus { 94 #address-cells = <2>; 95 #size-cells = <0>; 96 97 cpu0: cpu@0 { 98 device_type = "cpu"; 99 compatible = "qcom,kryo485"; 100 reg = <0x0 0x0>; 101 clocks = <&cpufreq_hw 0>; 102 enable-method = "psci"; 103 capacity-dmips-mhz = <448>; 104 dynamic-power-coefficient = <105>; 105 next-level-cache = <&l2_0>; 106 power-domains = <&cpu_pd0>; 107 power-domain-names = "psci"; 108 qcom,freq-domain = <&cpufreq_hw 0>; 109 operating-points-v2 = <&cpu0_opp_table>; 110 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 111 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 112 #cooling-cells = <2>; 113 l2_0: l2-cache { 114 compatible = "cache"; 115 cache-level = <2>; 116 cache-size = <0x20000>; 117 cache-unified; 118 next-level-cache = <&l3_0>; 119 l3_0: l3-cache { 120 compatible = "cache"; 121 cache-level = <3>; 122 cache-size = <0x400000>; 123 cache-unified; 124 }; 125 }; 126 }; 127 128 cpu1: cpu@100 { 129 device_type = "cpu"; 130 compatible = "qcom,kryo485"; 131 reg = <0x0 0x100>; 132 clocks = <&cpufreq_hw 0>; 133 enable-method = "psci"; 134 capacity-dmips-mhz = <448>; 135 dynamic-power-coefficient = <105>; 136 next-level-cache = <&l2_100>; 137 power-domains = <&cpu_pd1>; 138 power-domain-names = "psci"; 139 qcom,freq-domain = <&cpufreq_hw 0>; 140 operating-points-v2 = <&cpu0_opp_table>; 141 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 142 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 143 #cooling-cells = <2>; 144 l2_100: l2-cache { 145 compatible = "cache"; 146 cache-level = <2>; 147 cache-size = <0x20000>; 148 cache-unified; 149 next-level-cache = <&l3_0>; 150 }; 151 }; 152 153 cpu2: cpu@200 { 154 device_type = "cpu"; 155 compatible = "qcom,kryo485"; 156 reg = <0x0 0x200>; 157 clocks = <&cpufreq_hw 0>; 158 enable-method = "psci"; 159 capacity-dmips-mhz = <448>; 160 dynamic-power-coefficient = <105>; 161 next-level-cache = <&l2_200>; 162 power-domains = <&cpu_pd2>; 163 power-domain-names = "psci"; 164 qcom,freq-domain = <&cpufreq_hw 0>; 165 operating-points-v2 = <&cpu0_opp_table>; 166 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 167 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 168 #cooling-cells = <2>; 169 l2_200: l2-cache { 170 compatible = "cache"; 171 cache-level = <2>; 172 cache-size = <0x20000>; 173 cache-unified; 174 next-level-cache = <&l3_0>; 175 }; 176 }; 177 178 cpu3: cpu@300 { 179 device_type = "cpu"; 180 compatible = "qcom,kryo485"; 181 reg = <0x0 0x300>; 182 clocks = <&cpufreq_hw 0>; 183 enable-method = "psci"; 184 capacity-dmips-mhz = <448>; 185 dynamic-power-coefficient = <105>; 186 next-level-cache = <&l2_300>; 187 power-domains = <&cpu_pd3>; 188 power-domain-names = "psci"; 189 qcom,freq-domain = <&cpufreq_hw 0>; 190 operating-points-v2 = <&cpu0_opp_table>; 191 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 192 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 193 #cooling-cells = <2>; 194 l2_300: l2-cache { 195 compatible = "cache"; 196 cache-level = <2>; 197 cache-size = <0x20000>; 198 cache-unified; 199 next-level-cache = <&l3_0>; 200 }; 201 }; 202 203 cpu4: cpu@400 { 204 device_type = "cpu"; 205 compatible = "qcom,kryo485"; 206 reg = <0x0 0x400>; 207 clocks = <&cpufreq_hw 1>; 208 enable-method = "psci"; 209 capacity-dmips-mhz = <1024>; 210 dynamic-power-coefficient = <379>; 211 next-level-cache = <&l2_400>; 212 power-domains = <&cpu_pd4>; 213 power-domain-names = "psci"; 214 qcom,freq-domain = <&cpufreq_hw 1>; 215 operating-points-v2 = <&cpu4_opp_table>; 216 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 217 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 218 #cooling-cells = <2>; 219 l2_400: l2-cache { 220 compatible = "cache"; 221 cache-level = <2>; 222 cache-size = <0x40000>; 223 cache-unified; 224 next-level-cache = <&l3_0>; 225 }; 226 }; 227 228 cpu5: cpu@500 { 229 device_type = "cpu"; 230 compatible = "qcom,kryo485"; 231 reg = <0x0 0x500>; 232 clocks = <&cpufreq_hw 1>; 233 enable-method = "psci"; 234 capacity-dmips-mhz = <1024>; 235 dynamic-power-coefficient = <379>; 236 next-level-cache = <&l2_500>; 237 power-domains = <&cpu_pd5>; 238 power-domain-names = "psci"; 239 qcom,freq-domain = <&cpufreq_hw 1>; 240 operating-points-v2 = <&cpu4_opp_table>; 241 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 242 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 243 #cooling-cells = <2>; 244 l2_500: l2-cache { 245 compatible = "cache"; 246 cache-level = <2>; 247 cache-size = <0x40000>; 248 cache-unified; 249 next-level-cache = <&l3_0>; 250 }; 251 }; 252 253 cpu6: cpu@600 { 254 device_type = "cpu"; 255 compatible = "qcom,kryo485"; 256 reg = <0x0 0x600>; 257 clocks = <&cpufreq_hw 1>; 258 enable-method = "psci"; 259 capacity-dmips-mhz = <1024>; 260 dynamic-power-coefficient = <379>; 261 next-level-cache = <&l2_600>; 262 power-domains = <&cpu_pd6>; 263 power-domain-names = "psci"; 264 qcom,freq-domain = <&cpufreq_hw 1>; 265 operating-points-v2 = <&cpu4_opp_table>; 266 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 267 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 268 #cooling-cells = <2>; 269 l2_600: l2-cache { 270 compatible = "cache"; 271 cache-level = <2>; 272 cache-size = <0x40000>; 273 cache-unified; 274 next-level-cache = <&l3_0>; 275 }; 276 }; 277 278 cpu7: cpu@700 { 279 device_type = "cpu"; 280 compatible = "qcom,kryo485"; 281 reg = <0x0 0x700>; 282 clocks = <&cpufreq_hw 2>; 283 enable-method = "psci"; 284 capacity-dmips-mhz = <1024>; 285 dynamic-power-coefficient = <444>; 286 next-level-cache = <&l2_700>; 287 power-domains = <&cpu_pd7>; 288 power-domain-names = "psci"; 289 qcom,freq-domain = <&cpufreq_hw 2>; 290 operating-points-v2 = <&cpu7_opp_table>; 291 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 292 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 293 #cooling-cells = <2>; 294 l2_700: l2-cache { 295 compatible = "cache"; 296 cache-level = <2>; 297 cache-size = <0x80000>; 298 cache-unified; 299 next-level-cache = <&l3_0>; 300 }; 301 }; 302 303 cpu-map { 304 cluster0 { 305 core0 { 306 cpu = <&cpu0>; 307 }; 308 309 core1 { 310 cpu = <&cpu1>; 311 }; 312 313 core2 { 314 cpu = <&cpu2>; 315 }; 316 317 core3 { 318 cpu = <&cpu3>; 319 }; 320 321 core4 { 322 cpu = <&cpu4>; 323 }; 324 325 core5 { 326 cpu = <&cpu5>; 327 }; 328 329 core6 { 330 cpu = <&cpu6>; 331 }; 332 333 core7 { 334 cpu = <&cpu7>; 335 }; 336 }; 337 }; 338 339 idle-states { 340 entry-method = "psci"; 341 342 little_cpu_sleep_0: cpu-sleep-0-0 { 343 compatible = "arm,idle-state"; 344 idle-state-name = "silver-rail-power-collapse"; 345 arm,psci-suspend-param = <0x40000004>; 346 entry-latency-us = <360>; 347 exit-latency-us = <531>; 348 min-residency-us = <3934>; 349 local-timer-stop; 350 }; 351 352 big_cpu_sleep_0: cpu-sleep-1-0 { 353 compatible = "arm,idle-state"; 354 idle-state-name = "gold-rail-power-collapse"; 355 arm,psci-suspend-param = <0x40000004>; 356 entry-latency-us = <702>; 357 exit-latency-us = <1061>; 358 min-residency-us = <4488>; 359 local-timer-stop; 360 }; 361 }; 362 363 domain-idle-states { 364 cluster_sleep_0: cluster-sleep-0 { 365 compatible = "domain-idle-state"; 366 arm,psci-suspend-param = <0x4100c244>; 367 entry-latency-us = <3264>; 368 exit-latency-us = <6562>; 369 min-residency-us = <9987>; 370 }; 371 }; 372 }; 373 374 qup_virt: interconnect-qup-virt { 375 compatible = "qcom,sm8250-qup-virt"; 376 #interconnect-cells = <2>; 377 qcom,bcm-voters = <&apps_bcm_voter>; 378 }; 379 380 cpu0_opp_table: opp-table-cpu0 { 381 compatible = "operating-points-v2"; 382 opp-shared; 383 384 cpu0_opp1: opp-300000000 { 385 opp-hz = /bits/ 64 <300000000>; 386 opp-peak-kBps = <800000 9600000>; 387 }; 388 389 cpu0_opp2: opp-403200000 { 390 opp-hz = /bits/ 64 <403200000>; 391 opp-peak-kBps = <800000 9600000>; 392 }; 393 394 cpu0_opp3: opp-518400000 { 395 opp-hz = /bits/ 64 <518400000>; 396 opp-peak-kBps = <800000 16588800>; 397 }; 398 399 cpu0_opp4: opp-614400000 { 400 opp-hz = /bits/ 64 <614400000>; 401 opp-peak-kBps = <800000 16588800>; 402 }; 403 404 cpu0_opp5: opp-691200000 { 405 opp-hz = /bits/ 64 <691200000>; 406 opp-peak-kBps = <800000 19660800>; 407 }; 408 409 cpu0_opp6: opp-787200000 { 410 opp-hz = /bits/ 64 <787200000>; 411 opp-peak-kBps = <1804000 19660800>; 412 }; 413 414 cpu0_opp7: opp-883200000 { 415 opp-hz = /bits/ 64 <883200000>; 416 opp-peak-kBps = <1804000 23347200>; 417 }; 418 419 cpu0_opp8: opp-979200000 { 420 opp-hz = /bits/ 64 <979200000>; 421 opp-peak-kBps = <1804000 26419200>; 422 }; 423 424 cpu0_opp9: opp-1075200000 { 425 opp-hz = /bits/ 64 <1075200000>; 426 opp-peak-kBps = <1804000 29491200>; 427 }; 428 429 cpu0_opp10: opp-1171200000 { 430 opp-hz = /bits/ 64 <1171200000>; 431 opp-peak-kBps = <1804000 32563200>; 432 }; 433 434 cpu0_opp11: opp-1248000000 { 435 opp-hz = /bits/ 64 <1248000000>; 436 opp-peak-kBps = <1804000 36249600>; 437 }; 438 439 cpu0_opp12: opp-1344000000 { 440 opp-hz = /bits/ 64 <1344000000>; 441 opp-peak-kBps = <2188000 36249600>; 442 }; 443 444 cpu0_opp13: opp-1420800000 { 445 opp-hz = /bits/ 64 <1420800000>; 446 opp-peak-kBps = <2188000 39321600>; 447 }; 448 449 cpu0_opp14: opp-1516800000 { 450 opp-hz = /bits/ 64 <1516800000>; 451 opp-peak-kBps = <3072000 42393600>; 452 }; 453 454 cpu0_opp15: opp-1612800000 { 455 opp-hz = /bits/ 64 <1612800000>; 456 opp-peak-kBps = <3072000 42393600>; 457 }; 458 459 cpu0_opp16: opp-1708800000 { 460 opp-hz = /bits/ 64 <1708800000>; 461 opp-peak-kBps = <4068000 42393600>; 462 }; 463 464 cpu0_opp17: opp-1804800000 { 465 opp-hz = /bits/ 64 <1804800000>; 466 opp-peak-kBps = <4068000 42393600>; 467 }; 468 }; 469 470 cpu4_opp_table: opp-table-cpu4 { 471 compatible = "operating-points-v2"; 472 opp-shared; 473 474 cpu4_opp1: opp-710400000 { 475 opp-hz = /bits/ 64 <710400000>; 476 opp-peak-kBps = <1804000 19660800>; 477 }; 478 479 cpu4_opp2: opp-825600000 { 480 opp-hz = /bits/ 64 <825600000>; 481 opp-peak-kBps = <2188000 23347200>; 482 }; 483 484 cpu4_opp3: opp-940800000 { 485 opp-hz = /bits/ 64 <940800000>; 486 opp-peak-kBps = <2188000 26419200>; 487 }; 488 489 cpu4_opp4: opp-1056000000 { 490 opp-hz = /bits/ 64 <1056000000>; 491 opp-peak-kBps = <3072000 26419200>; 492 }; 493 494 cpu4_opp5: opp-1171200000 { 495 opp-hz = /bits/ 64 <1171200000>; 496 opp-peak-kBps = <3072000 29491200>; 497 }; 498 499 cpu4_opp6: opp-1286400000 { 500 opp-hz = /bits/ 64 <1286400000>; 501 opp-peak-kBps = <4068000 29491200>; 502 }; 503 504 cpu4_opp7: opp-1382400000 { 505 opp-hz = /bits/ 64 <1382400000>; 506 opp-peak-kBps = <4068000 32563200>; 507 }; 508 509 cpu4_opp8: opp-1478400000 { 510 opp-hz = /bits/ 64 <1478400000>; 511 opp-peak-kBps = <4068000 32563200>; 512 }; 513 514 cpu4_opp9: opp-1574400000 { 515 opp-hz = /bits/ 64 <1574400000>; 516 opp-peak-kBps = <5412000 39321600>; 517 }; 518 519 cpu4_opp10: opp-1670400000 { 520 opp-hz = /bits/ 64 <1670400000>; 521 opp-peak-kBps = <5412000 42393600>; 522 }; 523 524 cpu4_opp11: opp-1766400000 { 525 opp-hz = /bits/ 64 <1766400000>; 526 opp-peak-kBps = <5412000 45465600>; 527 }; 528 529 cpu4_opp12: opp-1862400000 { 530 opp-hz = /bits/ 64 <1862400000>; 531 opp-peak-kBps = <6220000 45465600>; 532 }; 533 534 cpu4_opp13: opp-1958400000 { 535 opp-hz = /bits/ 64 <1958400000>; 536 opp-peak-kBps = <6220000 48537600>; 537 }; 538 539 cpu4_opp14: opp-2054400000 { 540 opp-hz = /bits/ 64 <2054400000>; 541 opp-peak-kBps = <7216000 48537600>; 542 }; 543 544 cpu4_opp15: opp-2150400000 { 545 opp-hz = /bits/ 64 <2150400000>; 546 opp-peak-kBps = <7216000 51609600>; 547 }; 548 549 cpu4_opp16: opp-2246400000 { 550 opp-hz = /bits/ 64 <2246400000>; 551 opp-peak-kBps = <7216000 51609600>; 552 }; 553 554 cpu4_opp17: opp-2342400000 { 555 opp-hz = /bits/ 64 <2342400000>; 556 opp-peak-kBps = <8368000 51609600>; 557 }; 558 559 cpu4_opp18: opp-2419200000 { 560 opp-hz = /bits/ 64 <2419200000>; 561 opp-peak-kBps = <8368000 51609600>; 562 }; 563 }; 564 565 cpu7_opp_table: opp-table-cpu7 { 566 compatible = "operating-points-v2"; 567 opp-shared; 568 569 cpu7_opp1: opp-844800000 { 570 opp-hz = /bits/ 64 <844800000>; 571 opp-peak-kBps = <2188000 19660800>; 572 }; 573 574 cpu7_opp2: opp-960000000 { 575 opp-hz = /bits/ 64 <960000000>; 576 opp-peak-kBps = <2188000 26419200>; 577 }; 578 579 cpu7_opp3: opp-1075200000 { 580 opp-hz = /bits/ 64 <1075200000>; 581 opp-peak-kBps = <3072000 26419200>; 582 }; 583 584 cpu7_opp4: opp-1190400000 { 585 opp-hz = /bits/ 64 <1190400000>; 586 opp-peak-kBps = <3072000 29491200>; 587 }; 588 589 cpu7_opp5: opp-1305600000 { 590 opp-hz = /bits/ 64 <1305600000>; 591 opp-peak-kBps = <4068000 32563200>; 592 }; 593 594 cpu7_opp6: opp-1401600000 { 595 opp-hz = /bits/ 64 <1401600000>; 596 opp-peak-kBps = <4068000 32563200>; 597 }; 598 599 cpu7_opp7: opp-1516800000 { 600 opp-hz = /bits/ 64 <1516800000>; 601 opp-peak-kBps = <4068000 36249600>; 602 }; 603 604 cpu7_opp8: opp-1632000000 { 605 opp-hz = /bits/ 64 <1632000000>; 606 opp-peak-kBps = <5412000 39321600>; 607 }; 608 609 cpu7_opp9: opp-1747200000 { 610 opp-hz = /bits/ 64 <1747200000>; 611 opp-peak-kBps = <5412000 42393600>; 612 }; 613 614 cpu7_opp10: opp-1862400000 { 615 opp-hz = /bits/ 64 <1862400000>; 616 opp-peak-kBps = <6220000 45465600>; 617 }; 618 619 cpu7_opp11: opp-1977600000 { 620 opp-hz = /bits/ 64 <1977600000>; 621 opp-peak-kBps = <6220000 48537600>; 622 }; 623 624 cpu7_opp12: opp-2073600000 { 625 opp-hz = /bits/ 64 <2073600000>; 626 opp-peak-kBps = <7216000 48537600>; 627 }; 628 629 cpu7_opp13: opp-2169600000 { 630 opp-hz = /bits/ 64 <2169600000>; 631 opp-peak-kBps = <7216000 51609600>; 632 }; 633 634 cpu7_opp14: opp-2265600000 { 635 opp-hz = /bits/ 64 <2265600000>; 636 opp-peak-kBps = <7216000 51609600>; 637 }; 638 639 cpu7_opp15: opp-2361600000 { 640 opp-hz = /bits/ 64 <2361600000>; 641 opp-peak-kBps = <8368000 51609600>; 642 }; 643 644 cpu7_opp16: opp-2457600000 { 645 opp-hz = /bits/ 64 <2457600000>; 646 opp-peak-kBps = <8368000 51609600>; 647 }; 648 649 cpu7_opp17: opp-2553600000 { 650 opp-hz = /bits/ 64 <2553600000>; 651 opp-peak-kBps = <8368000 51609600>; 652 }; 653 654 cpu7_opp18: opp-2649600000 { 655 opp-hz = /bits/ 64 <2649600000>; 656 opp-peak-kBps = <8368000 51609600>; 657 }; 658 659 cpu7_opp19: opp-2745600000 { 660 opp-hz = /bits/ 64 <2745600000>; 661 opp-peak-kBps = <8368000 51609600>; 662 }; 663 664 cpu7_opp20: opp-2841600000 { 665 opp-hz = /bits/ 64 <2841600000>; 666 opp-peak-kBps = <8368000 51609600>; 667 }; 668 }; 669 670 firmware { 671 scm: scm { 672 compatible = "qcom,scm-sm8250", "qcom,scm"; 673 qcom,dload-mode = <&tcsr 0x13000>; 674 #reset-cells = <1>; 675 }; 676 }; 677 678 memory@80000000 { 679 device_type = "memory"; 680 /* We expect the bootloader to fill in the size */ 681 reg = <0x0 0x80000000 0x0 0x0>; 682 }; 683 684 pmu { 685 compatible = "arm,armv8-pmuv3"; 686 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 687 }; 688 689 psci { 690 compatible = "arm,psci-1.0"; 691 method = "smc"; 692 693 cpu_pd0: power-domain-cpu0 { 694 #power-domain-cells = <0>; 695 power-domains = <&cluster_pd>; 696 domain-idle-states = <&little_cpu_sleep_0>; 697 }; 698 699 cpu_pd1: power-domain-cpu1 { 700 #power-domain-cells = <0>; 701 power-domains = <&cluster_pd>; 702 domain-idle-states = <&little_cpu_sleep_0>; 703 }; 704 705 cpu_pd2: power-domain-cpu2 { 706 #power-domain-cells = <0>; 707 power-domains = <&cluster_pd>; 708 domain-idle-states = <&little_cpu_sleep_0>; 709 }; 710 711 cpu_pd3: power-domain-cpu3 { 712 #power-domain-cells = <0>; 713 power-domains = <&cluster_pd>; 714 domain-idle-states = <&little_cpu_sleep_0>; 715 }; 716 717 cpu_pd4: power-domain-cpu4 { 718 #power-domain-cells = <0>; 719 power-domains = <&cluster_pd>; 720 domain-idle-states = <&big_cpu_sleep_0>; 721 }; 722 723 cpu_pd5: power-domain-cpu5 { 724 #power-domain-cells = <0>; 725 power-domains = <&cluster_pd>; 726 domain-idle-states = <&big_cpu_sleep_0>; 727 }; 728 729 cpu_pd6: power-domain-cpu6 { 730 #power-domain-cells = <0>; 731 power-domains = <&cluster_pd>; 732 domain-idle-states = <&big_cpu_sleep_0>; 733 }; 734 735 cpu_pd7: power-domain-cpu7 { 736 #power-domain-cells = <0>; 737 power-domains = <&cluster_pd>; 738 domain-idle-states = <&big_cpu_sleep_0>; 739 }; 740 741 cluster_pd: power-domain-cpu-cluster0 { 742 #power-domain-cells = <0>; 743 domain-idle-states = <&cluster_sleep_0>; 744 }; 745 }; 746 747 qup_opp_table: opp-table-qup { 748 compatible = "operating-points-v2"; 749 750 opp-50000000 { 751 opp-hz = /bits/ 64 <50000000>; 752 required-opps = <&rpmhpd_opp_min_svs>; 753 }; 754 755 opp-75000000 { 756 opp-hz = /bits/ 64 <75000000>; 757 required-opps = <&rpmhpd_opp_low_svs>; 758 }; 759 760 opp-120000000 { 761 opp-hz = /bits/ 64 <120000000>; 762 required-opps = <&rpmhpd_opp_svs>; 763 }; 764 }; 765 766 reserved-memory { 767 #address-cells = <2>; 768 #size-cells = <2>; 769 ranges; 770 771 hyp_mem: memory@80000000 { 772 reg = <0x0 0x80000000 0x0 0x600000>; 773 no-map; 774 }; 775 776 xbl_aop_mem: memory@80700000 { 777 reg = <0x0 0x80700000 0x0 0x160000>; 778 no-map; 779 }; 780 781 cmd_db: memory@80860000 { 782 compatible = "qcom,cmd-db"; 783 reg = <0x0 0x80860000 0x0 0x20000>; 784 no-map; 785 }; 786 787 smem_mem: memory@80900000 { 788 reg = <0x0 0x80900000 0x0 0x200000>; 789 no-map; 790 }; 791 792 removed_mem: memory@80b00000 { 793 reg = <0x0 0x80b00000 0x0 0x5300000>; 794 no-map; 795 }; 796 797 camera_mem: memory@86200000 { 798 reg = <0x0 0x86200000 0x0 0x500000>; 799 no-map; 800 }; 801 802 wlan_mem: memory@86700000 { 803 reg = <0x0 0x86700000 0x0 0x100000>; 804 no-map; 805 }; 806 807 ipa_fw_mem: memory@86800000 { 808 reg = <0x0 0x86800000 0x0 0x10000>; 809 no-map; 810 }; 811 812 ipa_gsi_mem: memory@86810000 { 813 reg = <0x0 0x86810000 0x0 0xa000>; 814 no-map; 815 }; 816 817 gpu_mem: memory@8681a000 { 818 reg = <0x0 0x8681a000 0x0 0x2000>; 819 no-map; 820 }; 821 822 npu_mem: memory@86900000 { 823 reg = <0x0 0x86900000 0x0 0x500000>; 824 no-map; 825 }; 826 827 video_mem: memory@86e00000 { 828 reg = <0x0 0x86e00000 0x0 0x500000>; 829 no-map; 830 }; 831 832 cvp_mem: memory@87300000 { 833 reg = <0x0 0x87300000 0x0 0x500000>; 834 no-map; 835 }; 836 837 cdsp_mem: memory@87800000 { 838 reg = <0x0 0x87800000 0x0 0x1400000>; 839 no-map; 840 }; 841 842 slpi_mem: memory@88c00000 { 843 reg = <0x0 0x88c00000 0x0 0x1500000>; 844 no-map; 845 }; 846 847 adsp_mem: memory@8a100000 { 848 reg = <0x0 0x8a100000 0x0 0x1d00000>; 849 no-map; 850 }; 851 852 spss_mem: memory@8be00000 { 853 reg = <0x0 0x8be00000 0x0 0x100000>; 854 no-map; 855 }; 856 857 cdsp_secure_heap: memory@8bf00000 { 858 reg = <0x0 0x8bf00000 0x0 0x4600000>; 859 no-map; 860 }; 861 }; 862 863 smem { 864 compatible = "qcom,smem"; 865 memory-region = <&smem_mem>; 866 hwlocks = <&tcsr_mutex 3>; 867 }; 868 869 smp2p-adsp { 870 compatible = "qcom,smp2p"; 871 qcom,smem = <443>, <429>; 872 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 873 IPCC_MPROC_SIGNAL_SMP2P 874 IRQ_TYPE_EDGE_RISING>; 875 mboxes = <&ipcc IPCC_CLIENT_LPASS 876 IPCC_MPROC_SIGNAL_SMP2P>; 877 878 qcom,local-pid = <0>; 879 qcom,remote-pid = <2>; 880 881 smp2p_adsp_out: master-kernel { 882 qcom,entry-name = "master-kernel"; 883 #qcom,smem-state-cells = <1>; 884 }; 885 886 smp2p_adsp_in: slave-kernel { 887 qcom,entry-name = "slave-kernel"; 888 interrupt-controller; 889 #interrupt-cells = <2>; 890 }; 891 }; 892 893 smp2p-cdsp { 894 compatible = "qcom,smp2p"; 895 qcom,smem = <94>, <432>; 896 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 897 IPCC_MPROC_SIGNAL_SMP2P 898 IRQ_TYPE_EDGE_RISING>; 899 mboxes = <&ipcc IPCC_CLIENT_CDSP 900 IPCC_MPROC_SIGNAL_SMP2P>; 901 902 qcom,local-pid = <0>; 903 qcom,remote-pid = <5>; 904 905 smp2p_cdsp_out: master-kernel { 906 qcom,entry-name = "master-kernel"; 907 #qcom,smem-state-cells = <1>; 908 }; 909 910 smp2p_cdsp_in: slave-kernel { 911 qcom,entry-name = "slave-kernel"; 912 interrupt-controller; 913 #interrupt-cells = <2>; 914 }; 915 }; 916 917 smp2p-slpi { 918 compatible = "qcom,smp2p"; 919 qcom,smem = <481>, <430>; 920 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 921 IPCC_MPROC_SIGNAL_SMP2P 922 IRQ_TYPE_EDGE_RISING>; 923 mboxes = <&ipcc IPCC_CLIENT_SLPI 924 IPCC_MPROC_SIGNAL_SMP2P>; 925 926 qcom,local-pid = <0>; 927 qcom,remote-pid = <3>; 928 929 smp2p_slpi_out: master-kernel { 930 qcom,entry-name = "master-kernel"; 931 #qcom,smem-state-cells = <1>; 932 }; 933 934 smp2p_slpi_in: slave-kernel { 935 qcom,entry-name = "slave-kernel"; 936 interrupt-controller; 937 #interrupt-cells = <2>; 938 }; 939 }; 940 941 soc: soc@0 { 942 #address-cells = <2>; 943 #size-cells = <2>; 944 ranges = <0 0 0 0 0x10 0>; 945 dma-ranges = <0 0 0 0 0x10 0>; 946 compatible = "simple-bus"; 947 948 gcc: clock-controller@100000 { 949 compatible = "qcom,gcc-sm8250"; 950 reg = <0x0 0x00100000 0x0 0x1f0000>; 951 #clock-cells = <1>; 952 #reset-cells = <1>; 953 #power-domain-cells = <1>; 954 clock-names = "bi_tcxo", 955 "bi_tcxo_ao", 956 "sleep_clk"; 957 clocks = <&rpmhcc RPMH_CXO_CLK>, 958 <&rpmhcc RPMH_CXO_CLK_A>, 959 <&sleep_clk>; 960 }; 961 962 ipcc: mailbox@408000 { 963 compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; 964 reg = <0 0x00408000 0 0x1000>; 965 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 966 interrupt-controller; 967 #interrupt-cells = <3>; 968 #mbox-cells = <2>; 969 }; 970 971 qfprom: efuse@784000 { 972 compatible = "qcom,sm8250-qfprom", "qcom,qfprom"; 973 reg = <0 0x00784000 0 0x8ff>; 974 #address-cells = <1>; 975 #size-cells = <1>; 976 977 gpu_speed_bin: gpu-speed-bin@19b { 978 reg = <0x19b 0x1>; 979 bits = <5 3>; 980 }; 981 }; 982 983 rng: rng@793000 { 984 compatible = "qcom,prng-ee"; 985 reg = <0 0x00793000 0 0x1000>; 986 clocks = <&gcc GCC_PRNG_AHB_CLK>; 987 clock-names = "core"; 988 }; 989 990 gpi_dma2: dma-controller@800000 { 991 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 992 reg = <0 0x00800000 0 0x70000>; 993 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 997 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 998 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 999 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1000 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1001 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1002 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; 1003 dma-channels = <10>; 1004 dma-channel-mask = <0x3f>; 1005 iommus = <&apps_smmu 0x76 0x0>; 1006 #dma-cells = <3>; 1007 status = "disabled"; 1008 }; 1009 1010 qupv3_id_2: geniqup@8c0000 { 1011 compatible = "qcom,geni-se-qup"; 1012 reg = <0x0 0x008c0000 0x0 0x6000>; 1013 clock-names = "m-ahb", "s-ahb"; 1014 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1015 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1016 #address-cells = <2>; 1017 #size-cells = <2>; 1018 iommus = <&apps_smmu 0x63 0x0>; 1019 ranges; 1020 status = "disabled"; 1021 1022 i2c14: i2c@880000 { 1023 compatible = "qcom,geni-i2c"; 1024 reg = <0 0x00880000 0 0x4000>; 1025 clock-names = "se"; 1026 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1027 pinctrl-names = "default"; 1028 pinctrl-0 = <&qup_i2c14_default>; 1029 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1030 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1031 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1032 dma-names = "tx", "rx"; 1033 power-domains = <&rpmhpd RPMHPD_CX>; 1034 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1035 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1036 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1037 interconnect-names = "qup-core", 1038 "qup-config", 1039 "qup-memory"; 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 status = "disabled"; 1043 }; 1044 1045 spi14: spi@880000 { 1046 compatible = "qcom,geni-spi"; 1047 reg = <0 0x00880000 0 0x4000>; 1048 clock-names = "se"; 1049 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1050 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1051 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1052 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1053 dma-names = "tx", "rx"; 1054 power-domains = <&rpmhpd RPMHPD_CX>; 1055 operating-points-v2 = <&qup_opp_table>; 1056 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1057 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1058 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1059 interconnect-names = "qup-core", 1060 "qup-config", 1061 "qup-memory"; 1062 #address-cells = <1>; 1063 #size-cells = <0>; 1064 status = "disabled"; 1065 }; 1066 1067 i2c15: i2c@884000 { 1068 compatible = "qcom,geni-i2c"; 1069 reg = <0 0x00884000 0 0x4000>; 1070 clock-names = "se"; 1071 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1072 pinctrl-names = "default"; 1073 pinctrl-0 = <&qup_i2c15_default>; 1074 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1075 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1076 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1077 dma-names = "tx", "rx"; 1078 power-domains = <&rpmhpd RPMHPD_CX>; 1079 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1080 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1081 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1082 interconnect-names = "qup-core", 1083 "qup-config", 1084 "qup-memory"; 1085 #address-cells = <1>; 1086 #size-cells = <0>; 1087 status = "disabled"; 1088 }; 1089 1090 spi15: spi@884000 { 1091 compatible = "qcom,geni-spi"; 1092 reg = <0 0x00884000 0 0x4000>; 1093 clock-names = "se"; 1094 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1095 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1096 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1097 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1098 dma-names = "tx", "rx"; 1099 power-domains = <&rpmhpd RPMHPD_CX>; 1100 operating-points-v2 = <&qup_opp_table>; 1101 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1102 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1103 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1104 interconnect-names = "qup-core", 1105 "qup-config", 1106 "qup-memory"; 1107 #address-cells = <1>; 1108 #size-cells = <0>; 1109 status = "disabled"; 1110 }; 1111 1112 i2c16: i2c@888000 { 1113 compatible = "qcom,geni-i2c"; 1114 reg = <0 0x00888000 0 0x4000>; 1115 clock-names = "se"; 1116 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1117 pinctrl-names = "default"; 1118 pinctrl-0 = <&qup_i2c16_default>; 1119 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1120 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1121 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1122 dma-names = "tx", "rx"; 1123 power-domains = <&rpmhpd RPMHPD_CX>; 1124 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1125 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1126 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1127 interconnect-names = "qup-core", 1128 "qup-config", 1129 "qup-memory"; 1130 #address-cells = <1>; 1131 #size-cells = <0>; 1132 status = "disabled"; 1133 }; 1134 1135 spi16: spi@888000 { 1136 compatible = "qcom,geni-spi"; 1137 reg = <0 0x00888000 0 0x4000>; 1138 clock-names = "se"; 1139 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1140 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1141 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1142 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1143 dma-names = "tx", "rx"; 1144 power-domains = <&rpmhpd RPMHPD_CX>; 1145 operating-points-v2 = <&qup_opp_table>; 1146 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1147 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1148 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1149 interconnect-names = "qup-core", 1150 "qup-config", 1151 "qup-memory"; 1152 #address-cells = <1>; 1153 #size-cells = <0>; 1154 status = "disabled"; 1155 }; 1156 1157 i2c17: i2c@88c000 { 1158 compatible = "qcom,geni-i2c"; 1159 reg = <0 0x0088c000 0 0x4000>; 1160 clock-names = "se"; 1161 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1162 pinctrl-names = "default"; 1163 pinctrl-0 = <&qup_i2c17_default>; 1164 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1165 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1166 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1167 dma-names = "tx", "rx"; 1168 power-domains = <&rpmhpd RPMHPD_CX>; 1169 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1170 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1171 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1172 interconnect-names = "qup-core", 1173 "qup-config", 1174 "qup-memory"; 1175 #address-cells = <1>; 1176 #size-cells = <0>; 1177 status = "disabled"; 1178 }; 1179 1180 spi17: spi@88c000 { 1181 compatible = "qcom,geni-spi"; 1182 reg = <0 0x0088c000 0 0x4000>; 1183 clock-names = "se"; 1184 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1185 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1186 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1187 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1188 dma-names = "tx", "rx"; 1189 power-domains = <&rpmhpd RPMHPD_CX>; 1190 operating-points-v2 = <&qup_opp_table>; 1191 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1192 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1193 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1194 interconnect-names = "qup-core", 1195 "qup-config", 1196 "qup-memory"; 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 status = "disabled"; 1200 }; 1201 1202 uart17: serial@88c000 { 1203 compatible = "qcom,geni-uart"; 1204 reg = <0 0x0088c000 0 0x4000>; 1205 clock-names = "se"; 1206 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1207 pinctrl-names = "default"; 1208 pinctrl-0 = <&qup_uart17_default>; 1209 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1210 power-domains = <&rpmhpd RPMHPD_CX>; 1211 operating-points-v2 = <&qup_opp_table>; 1212 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1213 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1214 interconnect-names = "qup-core", 1215 "qup-config"; 1216 status = "disabled"; 1217 }; 1218 1219 i2c18: i2c@890000 { 1220 compatible = "qcom,geni-i2c"; 1221 reg = <0 0x00890000 0 0x4000>; 1222 clock-names = "se"; 1223 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1224 pinctrl-names = "default"; 1225 pinctrl-0 = <&qup_i2c18_default>; 1226 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1227 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1228 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1229 dma-names = "tx", "rx"; 1230 power-domains = <&rpmhpd RPMHPD_CX>; 1231 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1232 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1233 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1234 interconnect-names = "qup-core", 1235 "qup-config", 1236 "qup-memory"; 1237 #address-cells = <1>; 1238 #size-cells = <0>; 1239 status = "disabled"; 1240 }; 1241 1242 spi18: spi@890000 { 1243 compatible = "qcom,geni-spi"; 1244 reg = <0 0x00890000 0 0x4000>; 1245 clock-names = "se"; 1246 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1247 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1248 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1249 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1250 dma-names = "tx", "rx"; 1251 power-domains = <&rpmhpd RPMHPD_CX>; 1252 operating-points-v2 = <&qup_opp_table>; 1253 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1254 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1255 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1256 interconnect-names = "qup-core", 1257 "qup-config", 1258 "qup-memory"; 1259 #address-cells = <1>; 1260 #size-cells = <0>; 1261 status = "disabled"; 1262 }; 1263 1264 uart18: serial@890000 { 1265 compatible = "qcom,geni-uart"; 1266 reg = <0 0x00890000 0 0x4000>; 1267 clock-names = "se"; 1268 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1269 pinctrl-names = "default"; 1270 pinctrl-0 = <&qup_uart18_default>; 1271 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1272 power-domains = <&rpmhpd RPMHPD_CX>; 1273 operating-points-v2 = <&qup_opp_table>; 1274 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1275 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1276 interconnect-names = "qup-core", 1277 "qup-config"; 1278 status = "disabled"; 1279 }; 1280 1281 i2c19: i2c@894000 { 1282 compatible = "qcom,geni-i2c"; 1283 reg = <0 0x00894000 0 0x4000>; 1284 clock-names = "se"; 1285 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1286 pinctrl-names = "default"; 1287 pinctrl-0 = <&qup_i2c19_default>; 1288 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1289 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1290 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1291 dma-names = "tx", "rx"; 1292 power-domains = <&rpmhpd RPMHPD_CX>; 1293 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1294 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1295 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1296 interconnect-names = "qup-core", 1297 "qup-config", 1298 "qup-memory"; 1299 #address-cells = <1>; 1300 #size-cells = <0>; 1301 status = "disabled"; 1302 }; 1303 1304 spi19: spi@894000 { 1305 compatible = "qcom,geni-spi"; 1306 reg = <0 0x00894000 0 0x4000>; 1307 clock-names = "se"; 1308 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1309 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1310 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1311 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1312 dma-names = "tx", "rx"; 1313 power-domains = <&rpmhpd RPMHPD_CX>; 1314 operating-points-v2 = <&qup_opp_table>; 1315 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1316 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1317 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1318 interconnect-names = "qup-core", 1319 "qup-config", 1320 "qup-memory"; 1321 #address-cells = <1>; 1322 #size-cells = <0>; 1323 status = "disabled"; 1324 }; 1325 }; 1326 1327 gpi_dma0: dma-controller@900000 { 1328 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 1329 reg = <0 0x00900000 0 0x70000>; 1330 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1331 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1332 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1333 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1334 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1335 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1336 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1337 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1338 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1339 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1340 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1341 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1342 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1343 dma-channels = <15>; 1344 dma-channel-mask = <0x7ff>; 1345 iommus = <&apps_smmu 0x5b6 0x0>; 1346 #dma-cells = <3>; 1347 status = "disabled"; 1348 }; 1349 1350 qupv3_id_0: geniqup@9c0000 { 1351 compatible = "qcom,geni-se-qup"; 1352 reg = <0x0 0x009c0000 0x0 0x6000>; 1353 clock-names = "m-ahb", "s-ahb"; 1354 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1355 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1356 #address-cells = <2>; 1357 #size-cells = <2>; 1358 iommus = <&apps_smmu 0x5a3 0x0>; 1359 ranges; 1360 status = "disabled"; 1361 1362 i2c0: i2c@980000 { 1363 compatible = "qcom,geni-i2c"; 1364 reg = <0 0x00980000 0 0x4000>; 1365 clock-names = "se"; 1366 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1367 pinctrl-names = "default"; 1368 pinctrl-0 = <&qup_i2c0_default>; 1369 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1370 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1371 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1372 dma-names = "tx", "rx"; 1373 power-domains = <&rpmhpd RPMHPD_CX>; 1374 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1375 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1376 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1377 interconnect-names = "qup-core", 1378 "qup-config", 1379 "qup-memory"; 1380 #address-cells = <1>; 1381 #size-cells = <0>; 1382 status = "disabled"; 1383 }; 1384 1385 spi0: spi@980000 { 1386 compatible = "qcom,geni-spi"; 1387 reg = <0 0x00980000 0 0x4000>; 1388 clock-names = "se"; 1389 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1390 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1391 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1392 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1393 dma-names = "tx", "rx"; 1394 power-domains = <&rpmhpd RPMHPD_CX>; 1395 operating-points-v2 = <&qup_opp_table>; 1396 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1397 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1398 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1399 interconnect-names = "qup-core", 1400 "qup-config", 1401 "qup-memory"; 1402 #address-cells = <1>; 1403 #size-cells = <0>; 1404 status = "disabled"; 1405 }; 1406 1407 i2c1: i2c@984000 { 1408 compatible = "qcom,geni-i2c"; 1409 reg = <0 0x00984000 0 0x4000>; 1410 clock-names = "se"; 1411 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1412 pinctrl-names = "default"; 1413 pinctrl-0 = <&qup_i2c1_default>; 1414 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1415 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1416 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1417 dma-names = "tx", "rx"; 1418 power-domains = <&rpmhpd RPMHPD_CX>; 1419 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1420 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1421 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1422 interconnect-names = "qup-core", 1423 "qup-config", 1424 "qup-memory"; 1425 #address-cells = <1>; 1426 #size-cells = <0>; 1427 status = "disabled"; 1428 }; 1429 1430 spi1: spi@984000 { 1431 compatible = "qcom,geni-spi"; 1432 reg = <0 0x00984000 0 0x4000>; 1433 clock-names = "se"; 1434 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1435 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1436 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1437 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1438 dma-names = "tx", "rx"; 1439 power-domains = <&rpmhpd RPMHPD_CX>; 1440 operating-points-v2 = <&qup_opp_table>; 1441 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1442 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1443 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1444 interconnect-names = "qup-core", 1445 "qup-config", 1446 "qup-memory"; 1447 #address-cells = <1>; 1448 #size-cells = <0>; 1449 status = "disabled"; 1450 }; 1451 1452 i2c2: i2c@988000 { 1453 compatible = "qcom,geni-i2c"; 1454 reg = <0 0x00988000 0 0x4000>; 1455 clock-names = "se"; 1456 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1457 pinctrl-names = "default"; 1458 pinctrl-0 = <&qup_i2c2_default>; 1459 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1460 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1461 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1462 dma-names = "tx", "rx"; 1463 power-domains = <&rpmhpd RPMHPD_CX>; 1464 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1465 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1466 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1467 interconnect-names = "qup-core", 1468 "qup-config", 1469 "qup-memory"; 1470 #address-cells = <1>; 1471 #size-cells = <0>; 1472 status = "disabled"; 1473 }; 1474 1475 spi2: spi@988000 { 1476 compatible = "qcom,geni-spi"; 1477 reg = <0 0x00988000 0 0x4000>; 1478 clock-names = "se"; 1479 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1480 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1481 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1482 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1483 dma-names = "tx", "rx"; 1484 power-domains = <&rpmhpd RPMHPD_CX>; 1485 operating-points-v2 = <&qup_opp_table>; 1486 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1487 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1488 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1489 interconnect-names = "qup-core", 1490 "qup-config", 1491 "qup-memory"; 1492 #address-cells = <1>; 1493 #size-cells = <0>; 1494 status = "disabled"; 1495 }; 1496 1497 uart2: serial@988000 { 1498 compatible = "qcom,geni-debug-uart"; 1499 reg = <0 0x00988000 0 0x4000>; 1500 clock-names = "se"; 1501 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1502 pinctrl-names = "default"; 1503 pinctrl-0 = <&qup_uart2_default>; 1504 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1505 power-domains = <&rpmhpd RPMHPD_CX>; 1506 operating-points-v2 = <&qup_opp_table>; 1507 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1508 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1509 interconnect-names = "qup-core", 1510 "qup-config"; 1511 status = "disabled"; 1512 }; 1513 1514 i2c3: i2c@98c000 { 1515 compatible = "qcom,geni-i2c"; 1516 reg = <0 0x0098c000 0 0x4000>; 1517 clock-names = "se"; 1518 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1519 pinctrl-names = "default"; 1520 pinctrl-0 = <&qup_i2c3_default>; 1521 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1522 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1523 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1524 dma-names = "tx", "rx"; 1525 power-domains = <&rpmhpd RPMHPD_CX>; 1526 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1527 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1528 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1529 interconnect-names = "qup-core", 1530 "qup-config", 1531 "qup-memory"; 1532 #address-cells = <1>; 1533 #size-cells = <0>; 1534 status = "disabled"; 1535 }; 1536 1537 spi3: spi@98c000 { 1538 compatible = "qcom,geni-spi"; 1539 reg = <0 0x0098c000 0 0x4000>; 1540 clock-names = "se"; 1541 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1542 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1543 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1544 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1545 dma-names = "tx", "rx"; 1546 power-domains = <&rpmhpd RPMHPD_CX>; 1547 operating-points-v2 = <&qup_opp_table>; 1548 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1549 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1550 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1551 interconnect-names = "qup-core", 1552 "qup-config", 1553 "qup-memory"; 1554 #address-cells = <1>; 1555 #size-cells = <0>; 1556 status = "disabled"; 1557 }; 1558 1559 i2c4: i2c@990000 { 1560 compatible = "qcom,geni-i2c"; 1561 reg = <0 0x00990000 0 0x4000>; 1562 clock-names = "se"; 1563 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1564 pinctrl-names = "default"; 1565 pinctrl-0 = <&qup_i2c4_default>; 1566 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1567 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1568 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1569 dma-names = "tx", "rx"; 1570 power-domains = <&rpmhpd RPMHPD_CX>; 1571 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1572 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1573 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1574 interconnect-names = "qup-core", 1575 "qup-config", 1576 "qup-memory"; 1577 #address-cells = <1>; 1578 #size-cells = <0>; 1579 status = "disabled"; 1580 }; 1581 1582 spi4: spi@990000 { 1583 compatible = "qcom,geni-spi"; 1584 reg = <0 0x00990000 0 0x4000>; 1585 clock-names = "se"; 1586 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1587 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1588 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1589 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1590 dma-names = "tx", "rx"; 1591 power-domains = <&rpmhpd RPMHPD_CX>; 1592 operating-points-v2 = <&qup_opp_table>; 1593 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1594 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1595 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1596 interconnect-names = "qup-core", 1597 "qup-config", 1598 "qup-memory"; 1599 #address-cells = <1>; 1600 #size-cells = <0>; 1601 status = "disabled"; 1602 }; 1603 1604 i2c5: i2c@994000 { 1605 compatible = "qcom,geni-i2c"; 1606 reg = <0 0x00994000 0 0x4000>; 1607 clock-names = "se"; 1608 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1609 pinctrl-names = "default"; 1610 pinctrl-0 = <&qup_i2c5_default>; 1611 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1612 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1613 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1614 dma-names = "tx", "rx"; 1615 power-domains = <&rpmhpd RPMHPD_CX>; 1616 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1617 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1618 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1619 interconnect-names = "qup-core", 1620 "qup-config", 1621 "qup-memory"; 1622 #address-cells = <1>; 1623 #size-cells = <0>; 1624 status = "disabled"; 1625 }; 1626 1627 spi5: spi@994000 { 1628 compatible = "qcom,geni-spi"; 1629 reg = <0 0x00994000 0 0x4000>; 1630 clock-names = "se"; 1631 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1632 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1633 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1634 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1635 dma-names = "tx", "rx"; 1636 power-domains = <&rpmhpd RPMHPD_CX>; 1637 operating-points-v2 = <&qup_opp_table>; 1638 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1639 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1640 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1641 interconnect-names = "qup-core", 1642 "qup-config", 1643 "qup-memory"; 1644 #address-cells = <1>; 1645 #size-cells = <0>; 1646 status = "disabled"; 1647 }; 1648 1649 i2c6: i2c@998000 { 1650 compatible = "qcom,geni-i2c"; 1651 reg = <0 0x00998000 0 0x4000>; 1652 clock-names = "se"; 1653 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1654 pinctrl-names = "default"; 1655 pinctrl-0 = <&qup_i2c6_default>; 1656 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1657 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1658 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1659 dma-names = "tx", "rx"; 1660 power-domains = <&rpmhpd RPMHPD_CX>; 1661 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1662 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1663 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1664 interconnect-names = "qup-core", 1665 "qup-config", 1666 "qup-memory"; 1667 #address-cells = <1>; 1668 #size-cells = <0>; 1669 status = "disabled"; 1670 }; 1671 1672 spi6: spi@998000 { 1673 compatible = "qcom,geni-spi"; 1674 reg = <0 0x00998000 0 0x4000>; 1675 clock-names = "se"; 1676 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1677 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1678 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1679 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1680 dma-names = "tx", "rx"; 1681 power-domains = <&rpmhpd RPMHPD_CX>; 1682 operating-points-v2 = <&qup_opp_table>; 1683 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1684 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1685 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1686 interconnect-names = "qup-core", 1687 "qup-config", 1688 "qup-memory"; 1689 #address-cells = <1>; 1690 #size-cells = <0>; 1691 status = "disabled"; 1692 }; 1693 1694 uart6: serial@998000 { 1695 compatible = "qcom,geni-uart"; 1696 reg = <0 0x00998000 0 0x4000>; 1697 clock-names = "se"; 1698 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1699 pinctrl-names = "default"; 1700 pinctrl-0 = <&qup_uart6_default>; 1701 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1702 power-domains = <&rpmhpd RPMHPD_CX>; 1703 operating-points-v2 = <&qup_opp_table>; 1704 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1705 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1706 interconnect-names = "qup-core", 1707 "qup-config"; 1708 status = "disabled"; 1709 }; 1710 1711 i2c7: i2c@99c000 { 1712 compatible = "qcom,geni-i2c"; 1713 reg = <0 0x0099c000 0 0x4000>; 1714 clock-names = "se"; 1715 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1716 pinctrl-names = "default"; 1717 pinctrl-0 = <&qup_i2c7_default>; 1718 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1719 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1720 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1721 dma-names = "tx", "rx"; 1722 power-domains = <&rpmhpd RPMHPD_CX>; 1723 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1724 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1725 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1726 interconnect-names = "qup-core", 1727 "qup-config", 1728 "qup-memory"; 1729 #address-cells = <1>; 1730 #size-cells = <0>; 1731 status = "disabled"; 1732 }; 1733 1734 spi7: spi@99c000 { 1735 compatible = "qcom,geni-spi"; 1736 reg = <0 0x0099c000 0 0x4000>; 1737 clock-names = "se"; 1738 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1739 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1740 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1741 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1742 dma-names = "tx", "rx"; 1743 power-domains = <&rpmhpd RPMHPD_CX>; 1744 operating-points-v2 = <&qup_opp_table>; 1745 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1746 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1747 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1748 interconnect-names = "qup-core", 1749 "qup-config", 1750 "qup-memory"; 1751 #address-cells = <1>; 1752 #size-cells = <0>; 1753 status = "disabled"; 1754 }; 1755 }; 1756 1757 gpi_dma1: dma-controller@a00000 { 1758 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 1759 reg = <0 0x00a00000 0 0x70000>; 1760 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; 1770 dma-channels = <10>; 1771 dma-channel-mask = <0x3f>; 1772 iommus = <&apps_smmu 0x56 0x0>; 1773 #dma-cells = <3>; 1774 status = "disabled"; 1775 }; 1776 1777 qupv3_id_1: geniqup@ac0000 { 1778 compatible = "qcom,geni-se-qup"; 1779 reg = <0x0 0x00ac0000 0x0 0x6000>; 1780 clock-names = "m-ahb", "s-ahb"; 1781 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1782 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1783 #address-cells = <2>; 1784 #size-cells = <2>; 1785 iommus = <&apps_smmu 0x43 0x0>; 1786 ranges; 1787 status = "disabled"; 1788 1789 i2c8: i2c@a80000 { 1790 compatible = "qcom,geni-i2c"; 1791 reg = <0 0x00a80000 0 0x4000>; 1792 clock-names = "se"; 1793 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1794 pinctrl-names = "default"; 1795 pinctrl-0 = <&qup_i2c8_default>; 1796 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1797 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1798 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1799 dma-names = "tx", "rx"; 1800 power-domains = <&rpmhpd RPMHPD_CX>; 1801 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1802 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1803 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1804 interconnect-names = "qup-core", 1805 "qup-config", 1806 "qup-memory"; 1807 #address-cells = <1>; 1808 #size-cells = <0>; 1809 status = "disabled"; 1810 }; 1811 1812 spi8: spi@a80000 { 1813 compatible = "qcom,geni-spi"; 1814 reg = <0 0x00a80000 0 0x4000>; 1815 clock-names = "se"; 1816 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1817 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1818 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1819 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1820 dma-names = "tx", "rx"; 1821 power-domains = <&rpmhpd RPMHPD_CX>; 1822 operating-points-v2 = <&qup_opp_table>; 1823 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1824 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1825 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1826 interconnect-names = "qup-core", 1827 "qup-config", 1828 "qup-memory"; 1829 #address-cells = <1>; 1830 #size-cells = <0>; 1831 status = "disabled"; 1832 }; 1833 1834 i2c9: i2c@a84000 { 1835 compatible = "qcom,geni-i2c"; 1836 reg = <0 0x00a84000 0 0x4000>; 1837 clock-names = "se"; 1838 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1839 pinctrl-names = "default"; 1840 pinctrl-0 = <&qup_i2c9_default>; 1841 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1842 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1843 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1844 dma-names = "tx", "rx"; 1845 power-domains = <&rpmhpd RPMHPD_CX>; 1846 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1847 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1848 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1849 interconnect-names = "qup-core", 1850 "qup-config", 1851 "qup-memory"; 1852 #address-cells = <1>; 1853 #size-cells = <0>; 1854 status = "disabled"; 1855 }; 1856 1857 spi9: spi@a84000 { 1858 compatible = "qcom,geni-spi"; 1859 reg = <0 0x00a84000 0 0x4000>; 1860 clock-names = "se"; 1861 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1862 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1863 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1864 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1865 dma-names = "tx", "rx"; 1866 power-domains = <&rpmhpd RPMHPD_CX>; 1867 operating-points-v2 = <&qup_opp_table>; 1868 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1869 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1870 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1871 interconnect-names = "qup-core", 1872 "qup-config", 1873 "qup-memory"; 1874 #address-cells = <1>; 1875 #size-cells = <0>; 1876 status = "disabled"; 1877 }; 1878 1879 i2c10: i2c@a88000 { 1880 compatible = "qcom,geni-i2c"; 1881 reg = <0 0x00a88000 0 0x4000>; 1882 clock-names = "se"; 1883 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1884 pinctrl-names = "default"; 1885 pinctrl-0 = <&qup_i2c10_default>; 1886 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1887 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1888 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1889 dma-names = "tx", "rx"; 1890 power-domains = <&rpmhpd RPMHPD_CX>; 1891 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1892 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1893 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1894 interconnect-names = "qup-core", 1895 "qup-config", 1896 "qup-memory"; 1897 #address-cells = <1>; 1898 #size-cells = <0>; 1899 status = "disabled"; 1900 }; 1901 1902 spi10: spi@a88000 { 1903 compatible = "qcom,geni-spi"; 1904 reg = <0 0x00a88000 0 0x4000>; 1905 clock-names = "se"; 1906 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1907 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1908 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1909 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1910 dma-names = "tx", "rx"; 1911 power-domains = <&rpmhpd RPMHPD_CX>; 1912 operating-points-v2 = <&qup_opp_table>; 1913 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1914 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1915 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1916 interconnect-names = "qup-core", 1917 "qup-config", 1918 "qup-memory"; 1919 #address-cells = <1>; 1920 #size-cells = <0>; 1921 status = "disabled"; 1922 }; 1923 1924 i2c11: i2c@a8c000 { 1925 compatible = "qcom,geni-i2c"; 1926 reg = <0 0x00a8c000 0 0x4000>; 1927 clock-names = "se"; 1928 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1929 pinctrl-names = "default"; 1930 pinctrl-0 = <&qup_i2c11_default>; 1931 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1932 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1933 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1934 dma-names = "tx", "rx"; 1935 power-domains = <&rpmhpd RPMHPD_CX>; 1936 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1937 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1938 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1939 interconnect-names = "qup-core", 1940 "qup-config", 1941 "qup-memory"; 1942 #address-cells = <1>; 1943 #size-cells = <0>; 1944 status = "disabled"; 1945 }; 1946 1947 spi11: spi@a8c000 { 1948 compatible = "qcom,geni-spi"; 1949 reg = <0 0x00a8c000 0 0x4000>; 1950 clock-names = "se"; 1951 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1952 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1953 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1954 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1955 dma-names = "tx", "rx"; 1956 power-domains = <&rpmhpd RPMHPD_CX>; 1957 operating-points-v2 = <&qup_opp_table>; 1958 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1959 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1960 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1961 interconnect-names = "qup-core", 1962 "qup-config", 1963 "qup-memory"; 1964 #address-cells = <1>; 1965 #size-cells = <0>; 1966 status = "disabled"; 1967 }; 1968 1969 i2c12: i2c@a90000 { 1970 compatible = "qcom,geni-i2c"; 1971 reg = <0 0x00a90000 0 0x4000>; 1972 clock-names = "se"; 1973 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1974 pinctrl-names = "default"; 1975 pinctrl-0 = <&qup_i2c12_default>; 1976 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1977 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1978 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1979 dma-names = "tx", "rx"; 1980 power-domains = <&rpmhpd RPMHPD_CX>; 1981 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1982 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1983 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1984 interconnect-names = "qup-core", 1985 "qup-config", 1986 "qup-memory"; 1987 #address-cells = <1>; 1988 #size-cells = <0>; 1989 status = "disabled"; 1990 }; 1991 1992 spi12: spi@a90000 { 1993 compatible = "qcom,geni-spi"; 1994 reg = <0 0x00a90000 0 0x4000>; 1995 clock-names = "se"; 1996 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1997 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1998 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1999 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 2000 dma-names = "tx", "rx"; 2001 power-domains = <&rpmhpd RPMHPD_CX>; 2002 operating-points-v2 = <&qup_opp_table>; 2003 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 2004 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 2005 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 2006 interconnect-names = "qup-core", 2007 "qup-config", 2008 "qup-memory"; 2009 #address-cells = <1>; 2010 #size-cells = <0>; 2011 status = "disabled"; 2012 }; 2013 2014 uart12: serial@a90000 { 2015 compatible = "qcom,geni-debug-uart"; 2016 reg = <0x0 0x00a90000 0x0 0x4000>; 2017 clock-names = "se"; 2018 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2019 pinctrl-names = "default"; 2020 pinctrl-0 = <&qup_uart12_default>; 2021 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2022 power-domains = <&rpmhpd RPMHPD_CX>; 2023 operating-points-v2 = <&qup_opp_table>; 2024 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 2025 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 2026 interconnect-names = "qup-core", 2027 "qup-config"; 2028 status = "disabled"; 2029 }; 2030 2031 i2c13: i2c@a94000 { 2032 compatible = "qcom,geni-i2c"; 2033 reg = <0 0x00a94000 0 0x4000>; 2034 clock-names = "se"; 2035 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2036 pinctrl-names = "default"; 2037 pinctrl-0 = <&qup_i2c13_default>; 2038 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2039 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 2040 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 2041 dma-names = "tx", "rx"; 2042 power-domains = <&rpmhpd RPMHPD_CX>; 2043 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 2044 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 2045 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 2046 interconnect-names = "qup-core", 2047 "qup-config", 2048 "qup-memory"; 2049 #address-cells = <1>; 2050 #size-cells = <0>; 2051 status = "disabled"; 2052 }; 2053 2054 spi13: spi@a94000 { 2055 compatible = "qcom,geni-spi"; 2056 reg = <0 0x00a94000 0 0x4000>; 2057 clock-names = "se"; 2058 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2059 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2060 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 2061 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 2062 dma-names = "tx", "rx"; 2063 power-domains = <&rpmhpd RPMHPD_CX>; 2064 operating-points-v2 = <&qup_opp_table>; 2065 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 2066 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 2067 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 2068 interconnect-names = "qup-core", 2069 "qup-config", 2070 "qup-memory"; 2071 #address-cells = <1>; 2072 #size-cells = <0>; 2073 status = "disabled"; 2074 }; 2075 }; 2076 2077 config_noc: interconnect@1500000 { 2078 compatible = "qcom,sm8250-config-noc"; 2079 reg = <0 0x01500000 0 0xa580>; 2080 #interconnect-cells = <2>; 2081 qcom,bcm-voters = <&apps_bcm_voter>; 2082 }; 2083 2084 system_noc: interconnect@1620000 { 2085 compatible = "qcom,sm8250-system-noc"; 2086 reg = <0 0x01620000 0 0x1c200>; 2087 #interconnect-cells = <2>; 2088 qcom,bcm-voters = <&apps_bcm_voter>; 2089 }; 2090 2091 mc_virt: interconnect@163d000 { 2092 compatible = "qcom,sm8250-mc-virt"; 2093 reg = <0 0x0163d000 0 0x1000>; 2094 #interconnect-cells = <2>; 2095 qcom,bcm-voters = <&apps_bcm_voter>; 2096 }; 2097 2098 aggre1_noc: interconnect@16e0000 { 2099 compatible = "qcom,sm8250-aggre1-noc"; 2100 reg = <0 0x016e0000 0 0x1f180>; 2101 #interconnect-cells = <2>; 2102 qcom,bcm-voters = <&apps_bcm_voter>; 2103 }; 2104 2105 aggre2_noc: interconnect@1700000 { 2106 compatible = "qcom,sm8250-aggre2-noc"; 2107 reg = <0 0x01700000 0 0x33000>; 2108 #interconnect-cells = <2>; 2109 qcom,bcm-voters = <&apps_bcm_voter>; 2110 }; 2111 2112 compute_noc: interconnect@1733000 { 2113 compatible = "qcom,sm8250-compute-noc"; 2114 reg = <0 0x01733000 0 0xa180>; 2115 #interconnect-cells = <2>; 2116 qcom,bcm-voters = <&apps_bcm_voter>; 2117 }; 2118 2119 mmss_noc: interconnect@1740000 { 2120 compatible = "qcom,sm8250-mmss-noc"; 2121 reg = <0 0x01740000 0 0x1f080>; 2122 #interconnect-cells = <2>; 2123 qcom,bcm-voters = <&apps_bcm_voter>; 2124 }; 2125 2126 pcie0: pcie@1c00000 { 2127 compatible = "qcom,pcie-sm8250"; 2128 reg = <0 0x01c00000 0 0x3000>, 2129 <0 0x60000000 0 0xf1d>, 2130 <0 0x60000f20 0 0xa8>, 2131 <0 0x60001000 0 0x1000>, 2132 <0 0x60100000 0 0x100000>, 2133 <0 0x01c03000 0 0x1000>; 2134 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2135 device_type = "pci"; 2136 linux,pci-domain = <0>; 2137 bus-range = <0x00 0xff>; 2138 num-lanes = <1>; 2139 2140 #address-cells = <3>; 2141 #size-cells = <2>; 2142 2143 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 2144 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 2145 2146 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2147 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2148 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2149 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2150 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2151 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2152 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2153 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2154 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2155 interrupt-names = "msi0", 2156 "msi1", 2157 "msi2", 2158 "msi3", 2159 "msi4", 2160 "msi5", 2161 "msi6", 2162 "msi7", 2163 "global"; 2164 #interrupt-cells = <1>; 2165 interrupt-map-mask = <0 0 0 0x7>; 2166 interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2167 <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2168 <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2169 <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2170 2171 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 2172 <&gcc GCC_PCIE_0_AUX_CLK>, 2173 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2174 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2175 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2176 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2177 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2178 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 2179 clock-names = "pipe", 2180 "aux", 2181 "cfg", 2182 "bus_master", 2183 "bus_slave", 2184 "slave_q2a", 2185 "tbu", 2186 "ddrss_sf_tbu"; 2187 2188 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 2189 <0x100 &apps_smmu 0x1c01 0x1>; 2190 2191 resets = <&gcc GCC_PCIE_0_BCR>; 2192 reset-names = "pci"; 2193 2194 power-domains = <&gcc PCIE_0_GDSC>; 2195 2196 phys = <&pcie0_phy>; 2197 phy-names = "pciephy"; 2198 2199 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; 2200 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; 2201 2202 pinctrl-names = "default"; 2203 pinctrl-0 = <&pcie0_default_state>; 2204 dma-coherent; 2205 2206 status = "disabled"; 2207 2208 pcieport0: pcie@0 { 2209 device_type = "pci"; 2210 reg = <0x0 0x0 0x0 0x0 0x0>; 2211 bus-range = <0x01 0xff>; 2212 2213 #address-cells = <3>; 2214 #size-cells = <2>; 2215 ranges; 2216 }; 2217 }; 2218 2219 pcie0_phy: phy@1c06000 { 2220 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; 2221 reg = <0 0x01c06000 0 0x1000>; 2222 2223 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2224 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2225 <&gcc GCC_PCIE_WIFI_CLKREF_EN>, 2226 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, 2227 <&gcc GCC_PCIE_0_PIPE_CLK>; 2228 clock-names = "aux", 2229 "cfg_ahb", 2230 "ref", 2231 "refgen", 2232 "pipe"; 2233 2234 clock-output-names = "pcie_0_pipe_clk"; 2235 #clock-cells = <0>; 2236 2237 #phy-cells = <0>; 2238 2239 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2240 reset-names = "phy"; 2241 2242 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 2243 assigned-clock-rates = <100000000>; 2244 2245 status = "disabled"; 2246 }; 2247 2248 pcie1: pcie@1c08000 { 2249 compatible = "qcom,pcie-sm8250"; 2250 reg = <0 0x01c08000 0 0x3000>, 2251 <0 0x40000000 0 0xf1d>, 2252 <0 0x40000f20 0 0xa8>, 2253 <0 0x40001000 0 0x1000>, 2254 <0 0x40100000 0 0x100000>, 2255 <0 0x01c0b000 0 0x1000>; 2256 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2257 device_type = "pci"; 2258 linux,pci-domain = <1>; 2259 bus-range = <0x00 0xff>; 2260 num-lanes = <2>; 2261 2262 #address-cells = <3>; 2263 #size-cells = <2>; 2264 2265 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2266 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2267 2268 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2269 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2270 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2271 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2272 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2273 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2274 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2275 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2276 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 2277 interrupt-names = "msi0", 2278 "msi1", 2279 "msi2", 2280 "msi3", 2281 "msi4", 2282 "msi5", 2283 "msi6", 2284 "msi7", 2285 "global"; 2286 #interrupt-cells = <1>; 2287 interrupt-map-mask = <0 0 0 0x7>; 2288 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2289 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2290 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2291 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2292 2293 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2294 <&gcc GCC_PCIE_1_AUX_CLK>, 2295 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2296 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2297 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2298 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2299 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 2300 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2301 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 2302 clock-names = "pipe", 2303 "aux", 2304 "cfg", 2305 "bus_master", 2306 "bus_slave", 2307 "slave_q2a", 2308 "ref", 2309 "tbu", 2310 "ddrss_sf_tbu"; 2311 2312 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2313 assigned-clock-rates = <19200000>; 2314 2315 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2316 <0x100 &apps_smmu 0x1c81 0x1>; 2317 2318 resets = <&gcc GCC_PCIE_1_BCR>; 2319 reset-names = "pci"; 2320 2321 power-domains = <&gcc PCIE_1_GDSC>; 2322 2323 phys = <&pcie1_phy>; 2324 phy-names = "pciephy"; 2325 2326 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; 2327 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>; 2328 2329 pinctrl-names = "default"; 2330 pinctrl-0 = <&pcie1_default_state>; 2331 dma-coherent; 2332 2333 status = "disabled"; 2334 2335 pcie@0 { 2336 device_type = "pci"; 2337 reg = <0x0 0x0 0x0 0x0 0x0>; 2338 bus-range = <0x01 0xff>; 2339 2340 #address-cells = <3>; 2341 #size-cells = <2>; 2342 ranges; 2343 }; 2344 }; 2345 2346 pcie1_phy: phy@1c0e000 { 2347 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2348 reg = <0 0x01c0e000 0 0x1000>; 2349 2350 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2351 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2352 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 2353 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, 2354 <&gcc GCC_PCIE_1_PIPE_CLK>; 2355 clock-names = "aux", 2356 "cfg_ahb", 2357 "ref", 2358 "refgen", 2359 "pipe"; 2360 2361 clock-output-names = "pcie_1_pipe_clk"; 2362 #clock-cells = <0>; 2363 2364 #phy-cells = <0>; 2365 2366 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2367 reset-names = "phy"; 2368 2369 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2370 assigned-clock-rates = <100000000>; 2371 2372 status = "disabled"; 2373 }; 2374 2375 pcie2: pcie@1c10000 { 2376 compatible = "qcom,pcie-sm8250"; 2377 reg = <0 0x01c10000 0 0x3000>, 2378 <0 0x64000000 0 0xf1d>, 2379 <0 0x64000f20 0 0xa8>, 2380 <0 0x64001000 0 0x1000>, 2381 <0 0x64100000 0 0x100000>, 2382 <0 0x01c13000 0 0x1000>; 2383 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2384 device_type = "pci"; 2385 linux,pci-domain = <2>; 2386 bus-range = <0x00 0xff>; 2387 num-lanes = <2>; 2388 2389 #address-cells = <3>; 2390 #size-cells = <2>; 2391 2392 ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>, 2393 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; 2394 2395 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, 2396 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2397 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2398 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2399 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 2400 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 2401 <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 2402 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 2403 <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 2404 interrupt-names = "msi0", 2405 "msi1", 2406 "msi2", 2407 "msi3", 2408 "msi4", 2409 "msi5", 2410 "msi6", 2411 "msi7", 2412 "global"; 2413 #interrupt-cells = <1>; 2414 interrupt-map-mask = <0 0 0 0x7>; 2415 interrupt-map = <0 0 0 1 &intc GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2416 <0 0 0 2 &intc GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2417 <0 0 0 3 &intc GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2418 <0 0 0 4 &intc GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2419 2420 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2421 <&gcc GCC_PCIE_2_AUX_CLK>, 2422 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2423 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2424 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 2425 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 2426 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2427 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2428 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 2429 clock-names = "pipe", 2430 "aux", 2431 "cfg", 2432 "bus_master", 2433 "bus_slave", 2434 "slave_q2a", 2435 "ref", 2436 "tbu", 2437 "ddrss_sf_tbu"; 2438 2439 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 2440 assigned-clock-rates = <19200000>; 2441 2442 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 2443 <0x100 &apps_smmu 0x1d01 0x1>; 2444 2445 resets = <&gcc GCC_PCIE_2_BCR>; 2446 reset-names = "pci"; 2447 2448 power-domains = <&gcc PCIE_2_GDSC>; 2449 2450 phys = <&pcie2_phy>; 2451 phy-names = "pciephy"; 2452 2453 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; 2454 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; 2455 2456 pinctrl-names = "default"; 2457 pinctrl-0 = <&pcie2_default_state>; 2458 dma-coherent; 2459 2460 status = "disabled"; 2461 2462 pcie@0 { 2463 device_type = "pci"; 2464 reg = <0x0 0x0 0x0 0x0 0x0>; 2465 bus-range = <0x01 0xff>; 2466 2467 #address-cells = <3>; 2468 #size-cells = <2>; 2469 ranges; 2470 }; 2471 }; 2472 2473 pcie2_phy: phy@1c16000 { 2474 compatible = "qcom,sm8250-qmp-modem-pcie-phy"; 2475 reg = <0 0x01c16000 0 0x1000>; 2476 2477 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2478 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2479 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2480 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>, 2481 <&gcc GCC_PCIE_2_PIPE_CLK>; 2482 clock-names = "aux", 2483 "cfg_ahb", 2484 "ref", 2485 "refgen", 2486 "pipe"; 2487 2488 clock-output-names = "pcie_2_pipe_clk"; 2489 #clock-cells = <0>; 2490 2491 #phy-cells = <0>; 2492 2493 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 2494 reset-names = "phy"; 2495 2496 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2497 assigned-clock-rates = <100000000>; 2498 2499 status = "disabled"; 2500 }; 2501 2502 ufs_mem_hc: ufshc@1d84000 { 2503 compatible = "qcom,sm8250-ufshc", "qcom,ufshc", 2504 "jedec,ufs-2.0"; 2505 reg = <0 0x01d84000 0 0x3000>; 2506 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2507 phys = <&ufs_mem_phy>; 2508 phy-names = "ufsphy"; 2509 lanes-per-direction = <2>; 2510 #reset-cells = <1>; 2511 resets = <&gcc GCC_UFS_PHY_BCR>; 2512 reset-names = "rst"; 2513 2514 power-domains = <&gcc UFS_PHY_GDSC>; 2515 2516 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; 2517 2518 clock-names = 2519 "core_clk", 2520 "bus_aggr_clk", 2521 "iface_clk", 2522 "core_clk_unipro", 2523 "ref_clk", 2524 "tx_lane0_sync_clk", 2525 "rx_lane0_sync_clk", 2526 "rx_lane1_sync_clk"; 2527 clocks = 2528 <&gcc GCC_UFS_PHY_AXI_CLK>, 2529 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2530 <&gcc GCC_UFS_PHY_AHB_CLK>, 2531 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2532 <&rpmhcc RPMH_CXO_CLK>, 2533 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2534 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2535 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2536 2537 operating-points-v2 = <&ufs_opp_table>; 2538 2539 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI_CH0 0>, 2540 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 2541 interconnect-names = "ufs-ddr", "cpu-ufs"; 2542 2543 status = "disabled"; 2544 2545 ufs_opp_table: opp-table { 2546 compatible = "operating-points-v2"; 2547 2548 opp-37500000 { 2549 opp-hz = /bits/ 64 <37500000>, 2550 /bits/ 64 <0>, 2551 /bits/ 64 <0>, 2552 /bits/ 64 <37500000>, 2553 /bits/ 64 <0>, 2554 /bits/ 64 <0>, 2555 /bits/ 64 <0>, 2556 /bits/ 64 <0>; 2557 required-opps = <&rpmhpd_opp_low_svs>; 2558 }; 2559 2560 opp-300000000 { 2561 opp-hz = /bits/ 64 <300000000>, 2562 /bits/ 64 <0>, 2563 /bits/ 64 <0>, 2564 /bits/ 64 <300000000>, 2565 /bits/ 64 <0>, 2566 /bits/ 64 <0>, 2567 /bits/ 64 <0>, 2568 /bits/ 64 <0>; 2569 required-opps = <&rpmhpd_opp_nom>; 2570 }; 2571 }; 2572 }; 2573 2574 ufs_mem_phy: phy@1d87000 { 2575 compatible = "qcom,sm8250-qmp-ufs-phy"; 2576 reg = <0 0x01d87000 0 0x1000>; 2577 2578 clocks = <&rpmhcc RPMH_CXO_CLK>, 2579 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2580 <&gcc GCC_UFS_1X_CLKREF_EN>; 2581 clock-names = "ref", 2582 "ref_aux", 2583 "qref"; 2584 2585 resets = <&ufs_mem_hc 0>; 2586 reset-names = "ufsphy"; 2587 2588 power-domains = <&gcc UFS_PHY_GDSC>; 2589 2590 #phy-cells = <0>; 2591 2592 status = "disabled"; 2593 }; 2594 2595 cryptobam: dma-controller@1dc4000 { 2596 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2597 reg = <0 0x01dc4000 0 0x24000>; 2598 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2599 #dma-cells = <1>; 2600 qcom,ee = <0>; 2601 qcom,controlled-remotely; 2602 num-channels = <8>; 2603 qcom,num-ees = <2>; 2604 iommus = <&apps_smmu 0x592 0x0000>, 2605 <&apps_smmu 0x598 0x0000>, 2606 <&apps_smmu 0x599 0x0000>, 2607 <&apps_smmu 0x59f 0x0000>, 2608 <&apps_smmu 0x586 0x0011>, 2609 <&apps_smmu 0x596 0x0011>; 2610 }; 2611 2612 crypto: crypto@1dfa000 { 2613 compatible = "qcom,sm8250-qce", "qcom,sm8150-qce", "qcom,qce"; 2614 reg = <0 0x01dfa000 0 0x6000>; 2615 dmas = <&cryptobam 4>, <&cryptobam 5>; 2616 dma-names = "rx", "tx"; 2617 iommus = <&apps_smmu 0x592 0x0000>, 2618 <&apps_smmu 0x598 0x0000>, 2619 <&apps_smmu 0x599 0x0000>, 2620 <&apps_smmu 0x59f 0x0000>, 2621 <&apps_smmu 0x586 0x0011>, 2622 <&apps_smmu 0x596 0x0011>; 2623 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>; 2624 interconnect-names = "memory"; 2625 }; 2626 2627 tcsr_mutex: hwlock@1f40000 { 2628 compatible = "qcom,tcsr-mutex"; 2629 reg = <0x0 0x01f40000 0x0 0x40000>; 2630 #hwlock-cells = <1>; 2631 }; 2632 2633 tcsr: syscon@1fc0000 { 2634 compatible = "qcom,sm8250-tcsr", "syscon"; 2635 reg = <0x0 0x1fc0000 0x0 0x30000>; 2636 }; 2637 2638 wsamacro: codec@3240000 { 2639 compatible = "qcom,sm8250-lpass-wsa-macro"; 2640 reg = <0 0x03240000 0 0x1000>; 2641 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2642 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2643 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2644 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2645 <&vamacro>; 2646 2647 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2648 2649 #clock-cells = <0>; 2650 clock-output-names = "mclk"; 2651 #sound-dai-cells = <1>; 2652 2653 pinctrl-names = "default"; 2654 pinctrl-0 = <&wsa_swr_active>; 2655 2656 status = "disabled"; 2657 }; 2658 2659 swr0: soundwire@3250000 { 2660 reg = <0 0x03250000 0 0x2000>; 2661 compatible = "qcom,soundwire-v1.5.1"; 2662 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 2663 clocks = <&wsamacro>; 2664 clock-names = "iface"; 2665 2666 qcom,din-ports = <2>; 2667 qcom,dout-ports = <6>; 2668 2669 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2670 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2671 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2672 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; 2673 2674 #sound-dai-cells = <1>; 2675 #address-cells = <2>; 2676 #size-cells = <0>; 2677 2678 status = "disabled"; 2679 }; 2680 2681 vamacro: codec@3370000 { 2682 compatible = "qcom,sm8250-lpass-va-macro"; 2683 reg = <0 0x03370000 0 0x1000>; 2684 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2685 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2686 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2687 2688 clock-names = "mclk", "macro", "dcodec"; 2689 2690 #clock-cells = <0>; 2691 clock-output-names = "fsgen"; 2692 #sound-dai-cells = <1>; 2693 }; 2694 2695 rxmacro: rxmacro@3200000 { 2696 pinctrl-names = "default"; 2697 pinctrl-0 = <&rx_swr_active>; 2698 compatible = "qcom,sm8250-lpass-rx-macro"; 2699 reg = <0 0x03200000 0 0x1000>; 2700 status = "disabled"; 2701 2702 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2703 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2704 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2705 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2706 <&vamacro>; 2707 2708 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2709 2710 #clock-cells = <0>; 2711 clock-output-names = "mclk"; 2712 #sound-dai-cells = <1>; 2713 }; 2714 2715 swr1: soundwire@3210000 { 2716 reg = <0 0x03210000 0 0x2000>; 2717 compatible = "qcom,soundwire-v1.5.1"; 2718 status = "disabled"; 2719 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 2720 clocks = <&rxmacro>; 2721 clock-names = "iface"; 2722 label = "RX"; 2723 qcom,din-ports = <0>; 2724 qcom,dout-ports = <5>; 2725 2726 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2727 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; 2728 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2729 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2730 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2731 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2732 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2733 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2734 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2735 2736 #sound-dai-cells = <1>; 2737 #address-cells = <2>; 2738 #size-cells = <0>; 2739 }; 2740 2741 txmacro: txmacro@3220000 { 2742 pinctrl-names = "default"; 2743 pinctrl-0 = <&tx_swr_active>; 2744 compatible = "qcom,sm8250-lpass-tx-macro"; 2745 reg = <0 0x03220000 0 0x1000>; 2746 status = "disabled"; 2747 2748 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2749 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2750 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2751 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2752 <&vamacro>; 2753 2754 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2755 2756 #clock-cells = <0>; 2757 clock-output-names = "mclk"; 2758 #sound-dai-cells = <1>; 2759 }; 2760 2761 /* tx macro */ 2762 swr2: soundwire@3230000 { 2763 reg = <0 0x03230000 0 0x2000>; 2764 compatible = "qcom,soundwire-v1.5.1"; 2765 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 2766 interrupt-names = "core"; 2767 status = "disabled"; 2768 2769 clocks = <&txmacro>; 2770 clock-names = "iface"; 2771 label = "TX"; 2772 2773 qcom,din-ports = <5>; 2774 qcom,dout-ports = <0>; 2775 qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>; 2776 qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>; 2777 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>; 2778 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2779 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2780 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2781 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2782 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2783 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>; 2784 #sound-dai-cells = <1>; 2785 #address-cells = <2>; 2786 #size-cells = <0>; 2787 }; 2788 2789 lpass_tlmm: pinctrl@33c0000 { 2790 compatible = "qcom,sm8250-lpass-lpi-pinctrl"; 2791 reg = <0 0x033c0000 0x0 0x20000>, 2792 <0 0x03550000 0x0 0x10000>; 2793 gpio-controller; 2794 #gpio-cells = <2>; 2795 gpio-ranges = <&lpass_tlmm 0 0 14>; 2796 2797 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2798 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2799 clock-names = "core", "audio"; 2800 2801 wsa_swr_active: wsa-swr-active-state { 2802 clk-pins { 2803 pins = "gpio10"; 2804 function = "wsa_swr_clk"; 2805 drive-strength = <2>; 2806 slew-rate = <1>; 2807 bias-disable; 2808 }; 2809 2810 data-pins { 2811 pins = "gpio11"; 2812 function = "wsa_swr_data"; 2813 drive-strength = <2>; 2814 slew-rate = <1>; 2815 bias-bus-hold; 2816 }; 2817 }; 2818 2819 wsa_swr_sleep: wsa-swr-sleep-state { 2820 clk-pins { 2821 pins = "gpio10"; 2822 function = "wsa_swr_clk"; 2823 drive-strength = <2>; 2824 bias-pull-down; 2825 }; 2826 2827 data-pins { 2828 pins = "gpio11"; 2829 function = "wsa_swr_data"; 2830 drive-strength = <2>; 2831 bias-pull-down; 2832 }; 2833 }; 2834 2835 dmic01_active: dmic01-active-state { 2836 clk-pins { 2837 pins = "gpio6"; 2838 function = "dmic1_clk"; 2839 drive-strength = <8>; 2840 output-high; 2841 }; 2842 data-pins { 2843 pins = "gpio7"; 2844 function = "dmic1_data"; 2845 drive-strength = <8>; 2846 }; 2847 }; 2848 2849 dmic01_sleep: dmic01-sleep-state { 2850 clk-pins { 2851 pins = "gpio6"; 2852 function = "dmic1_clk"; 2853 drive-strength = <2>; 2854 bias-disable; 2855 output-low; 2856 }; 2857 2858 data-pins { 2859 pins = "gpio7"; 2860 function = "dmic1_data"; 2861 drive-strength = <2>; 2862 bias-pull-down; 2863 }; 2864 }; 2865 2866 rx_swr_active: rx-swr-active-state { 2867 clk-pins { 2868 pins = "gpio3"; 2869 function = "swr_rx_clk"; 2870 drive-strength = <2>; 2871 slew-rate = <1>; 2872 bias-disable; 2873 }; 2874 2875 data-pins { 2876 pins = "gpio4", "gpio5"; 2877 function = "swr_rx_data"; 2878 drive-strength = <2>; 2879 slew-rate = <1>; 2880 bias-bus-hold; 2881 }; 2882 }; 2883 2884 tx_swr_active: tx-swr-active-state { 2885 clk-pins { 2886 pins = "gpio0"; 2887 function = "swr_tx_clk"; 2888 drive-strength = <2>; 2889 slew-rate = <1>; 2890 bias-disable; 2891 }; 2892 2893 data-pins { 2894 pins = "gpio1", "gpio2"; 2895 function = "swr_tx_data"; 2896 drive-strength = <2>; 2897 slew-rate = <1>; 2898 bias-bus-hold; 2899 }; 2900 }; 2901 2902 tx_swr_sleep: tx-swr-sleep-state { 2903 clk-pins { 2904 pins = "gpio0"; 2905 function = "swr_tx_clk"; 2906 drive-strength = <2>; 2907 bias-pull-down; 2908 }; 2909 2910 data1-pins { 2911 pins = "gpio1"; 2912 function = "swr_tx_data"; 2913 drive-strength = <2>; 2914 bias-bus-hold; 2915 }; 2916 2917 data2-pins { 2918 pins = "gpio2"; 2919 function = "swr_tx_data"; 2920 drive-strength = <2>; 2921 bias-pull-down; 2922 }; 2923 }; 2924 }; 2925 2926 gpu: gpu@3d00000 { 2927 compatible = "qcom,adreno-650.2", 2928 "qcom,adreno"; 2929 2930 reg = <0 0x03d00000 0 0x40000>; 2931 reg-names = "kgsl_3d0_reg_memory"; 2932 2933 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2934 2935 iommus = <&adreno_smmu 0 0x401>; 2936 2937 operating-points-v2 = <&gpu_opp_table>; 2938 2939 qcom,gmu = <&gmu>; 2940 2941 nvmem-cells = <&gpu_speed_bin>; 2942 nvmem-cell-names = "speed_bin"; 2943 #cooling-cells = <2>; 2944 2945 status = "disabled"; 2946 2947 zap-shader { 2948 memory-region = <&gpu_mem>; 2949 }; 2950 2951 gpu_opp_table: opp-table { 2952 compatible = "operating-points-v2"; 2953 2954 opp-670000000 { 2955 opp-hz = /bits/ 64 <670000000>; 2956 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2957 opp-supported-hw = <0xa>; 2958 }; 2959 2960 opp-587000000 { 2961 opp-hz = /bits/ 64 <587000000>; 2962 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2963 opp-supported-hw = <0xb>; 2964 }; 2965 2966 opp-525000000 { 2967 opp-hz = /bits/ 64 <525000000>; 2968 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2969 opp-supported-hw = <0xf>; 2970 }; 2971 2972 opp-490000000 { 2973 opp-hz = /bits/ 64 <490000000>; 2974 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2975 opp-supported-hw = <0xf>; 2976 }; 2977 2978 opp-441600000 { 2979 opp-hz = /bits/ 64 <441600000>; 2980 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2981 opp-supported-hw = <0xf>; 2982 }; 2983 2984 opp-400000000 { 2985 opp-hz = /bits/ 64 <400000000>; 2986 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2987 opp-supported-hw = <0xf>; 2988 }; 2989 2990 opp-305000000 { 2991 opp-hz = /bits/ 64 <305000000>; 2992 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2993 opp-supported-hw = <0xf>; 2994 }; 2995 }; 2996 }; 2997 2998 gmu: gmu@3d6a000 { 2999 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; 3000 3001 reg = <0 0x03d6a000 0 0x30000>, 3002 <0 0x3de0000 0 0x10000>, 3003 <0 0xb290000 0 0x10000>, 3004 <0 0xb490000 0 0x10000>; 3005 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; 3006 3007 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 3008 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 3009 interrupt-names = "hfi", "gmu"; 3010 3011 clocks = <&gpucc GPU_CC_AHB_CLK>, 3012 <&gpucc GPU_CC_CX_GMU_CLK>, 3013 <&gpucc GPU_CC_CXO_CLK>, 3014 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 3015 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 3016 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 3017 3018 power-domains = <&gpucc GPU_CX_GDSC>, 3019 <&gpucc GPU_GX_GDSC>; 3020 power-domain-names = "cx", "gx"; 3021 3022 iommus = <&adreno_smmu 5 0x400>; 3023 3024 operating-points-v2 = <&gmu_opp_table>; 3025 3026 status = "disabled"; 3027 3028 gmu_opp_table: opp-table { 3029 compatible = "operating-points-v2"; 3030 3031 opp-200000000 { 3032 opp-hz = /bits/ 64 <200000000>; 3033 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3034 }; 3035 }; 3036 }; 3037 3038 gpucc: clock-controller@3d90000 { 3039 compatible = "qcom,sm8250-gpucc"; 3040 reg = <0 0x03d90000 0 0x9000>; 3041 clocks = <&rpmhcc RPMH_CXO_CLK>, 3042 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3043 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3044 clock-names = "bi_tcxo", 3045 "gcc_gpu_gpll0_clk_src", 3046 "gcc_gpu_gpll0_div_clk_src"; 3047 #clock-cells = <1>; 3048 #reset-cells = <1>; 3049 #power-domain-cells = <1>; 3050 }; 3051 3052 adreno_smmu: iommu@3da0000 { 3053 compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu", 3054 "qcom,smmu-500", "arm,mmu-500"; 3055 reg = <0 0x03da0000 0 0x10000>; 3056 #iommu-cells = <2>; 3057 #global-interrupts = <2>; 3058 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 3059 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 3060 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 3061 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 3062 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 3063 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 3064 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 3065 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 3066 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 3067 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; 3068 clocks = <&gpucc GPU_CC_AHB_CLK>, 3069 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3070 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 3071 clock-names = "ahb", "bus", "iface"; 3072 3073 power-domains = <&gpucc GPU_CX_GDSC>; 3074 dma-coherent; 3075 }; 3076 3077 slpi: remoteproc@5c00000 { 3078 compatible = "qcom,sm8250-slpi-pas"; 3079 reg = <0 0x05c00000 0 0x4000>; 3080 3081 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 3082 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 3083 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 3084 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 3085 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 3086 interrupt-names = "wdog", "fatal", "ready", 3087 "handover", "stop-ack"; 3088 3089 clocks = <&rpmhcc RPMH_CXO_CLK>; 3090 clock-names = "xo"; 3091 3092 power-domains = <&rpmhpd RPMHPD_LCX>, 3093 <&rpmhpd RPMHPD_LMX>; 3094 power-domain-names = "lcx", "lmx"; 3095 3096 memory-region = <&slpi_mem>; 3097 3098 qcom,qmp = <&aoss_qmp>; 3099 3100 qcom,smem-states = <&smp2p_slpi_out 0>; 3101 qcom,smem-state-names = "stop"; 3102 3103 status = "disabled"; 3104 3105 glink-edge { 3106 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 3107 IPCC_MPROC_SIGNAL_GLINK_QMP 3108 IRQ_TYPE_EDGE_RISING>; 3109 mboxes = <&ipcc IPCC_CLIENT_SLPI 3110 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3111 3112 label = "slpi"; 3113 qcom,remote-pid = <3>; 3114 3115 fastrpc { 3116 compatible = "qcom,fastrpc"; 3117 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3118 label = "sdsp"; 3119 qcom,non-secure-domain; 3120 #address-cells = <1>; 3121 #size-cells = <0>; 3122 3123 compute-cb@1 { 3124 compatible = "qcom,fastrpc-compute-cb"; 3125 reg = <1>; 3126 iommus = <&apps_smmu 0x0541 0x0>; 3127 }; 3128 3129 compute-cb@2 { 3130 compatible = "qcom,fastrpc-compute-cb"; 3131 reg = <2>; 3132 iommus = <&apps_smmu 0x0542 0x0>; 3133 }; 3134 3135 compute-cb@3 { 3136 compatible = "qcom,fastrpc-compute-cb"; 3137 reg = <3>; 3138 iommus = <&apps_smmu 0x0543 0x0>; 3139 /* note: shared-cb = <4> in downstream */ 3140 }; 3141 }; 3142 }; 3143 }; 3144 3145 stm@6002000 { 3146 compatible = "arm,coresight-stm", "arm,primecell"; 3147 reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>; 3148 reg-names = "stm-base", "stm-stimulus-base"; 3149 3150 clocks = <&aoss_qmp>; 3151 clock-names = "apb_pclk"; 3152 3153 out-ports { 3154 port { 3155 stm_out: endpoint { 3156 remote-endpoint = <&funnel0_in7>; 3157 }; 3158 }; 3159 }; 3160 }; 3161 3162 tpda@6004000 { 3163 compatible = "qcom,coresight-tpda", "arm,primecell"; 3164 reg = <0 0x06004000 0 0x1000>; 3165 3166 clocks = <&aoss_qmp>; 3167 clock-names = "apb_pclk"; 3168 3169 out-ports { 3170 3171 port { 3172 tpda_out_funnel_qatb: endpoint { 3173 remote-endpoint = <&funnel_qatb_in_tpda>; 3174 }; 3175 }; 3176 }; 3177 3178 in-ports { 3179 #address-cells = <1>; 3180 #size-cells = <0>; 3181 3182 port@9 { 3183 reg = <9>; 3184 tpda_9_in_tpdm_mm: endpoint { 3185 remote-endpoint = <&tpdm_mm_out_tpda9>; 3186 }; 3187 }; 3188 3189 port@17 { 3190 reg = <23>; 3191 tpda_23_in_tpdm_prng: endpoint { 3192 remote-endpoint = <&tpdm_prng_out_tpda_23>; 3193 }; 3194 }; 3195 }; 3196 }; 3197 3198 funnel@6005000 { 3199 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3200 reg = <0 0x06005000 0 0x1000>; 3201 3202 clocks = <&aoss_qmp>; 3203 clock-names = "apb_pclk"; 3204 3205 out-ports { 3206 port { 3207 funnel_qatb_out_funnel_in0: endpoint { 3208 remote-endpoint = <&funnel_in0_in_funnel_qatb>; 3209 }; 3210 }; 3211 }; 3212 3213 in-ports { 3214 port { 3215 funnel_qatb_in_tpda: endpoint { 3216 remote-endpoint = <&tpda_out_funnel_qatb>; 3217 }; 3218 }; 3219 }; 3220 }; 3221 3222 funnel@6041000 { 3223 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3224 reg = <0 0x06041000 0 0x1000>; 3225 3226 clocks = <&aoss_qmp>; 3227 clock-names = "apb_pclk"; 3228 3229 out-ports { 3230 port { 3231 funnel_in0_out_funnel_merg: endpoint { 3232 remote-endpoint = <&funnel_merg_in_funnel_in0>; 3233 }; 3234 }; 3235 }; 3236 3237 in-ports { 3238 #address-cells = <1>; 3239 #size-cells = <0>; 3240 3241 port@6 { 3242 reg = <6>; 3243 funnel_in0_in_funnel_qatb: endpoint { 3244 remote-endpoint = <&funnel_qatb_out_funnel_in0>; 3245 }; 3246 }; 3247 3248 port@7 { 3249 reg = <7>; 3250 funnel0_in7: endpoint { 3251 remote-endpoint = <&stm_out>; 3252 }; 3253 }; 3254 }; 3255 }; 3256 3257 funnel@6042000 { 3258 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3259 reg = <0 0x06042000 0 0x1000>; 3260 3261 clocks = <&aoss_qmp>; 3262 clock-names = "apb_pclk"; 3263 3264 out-ports { 3265 port { 3266 funnel_in1_out_funnel_merg: endpoint { 3267 remote-endpoint = <&funnel_merg_in_funnel_in1>; 3268 }; 3269 }; 3270 }; 3271 3272 in-ports { 3273 #address-cells = <1>; 3274 #size-cells = <0>; 3275 3276 port@4 { 3277 reg = <4>; 3278 funnel_in1_in_funnel_apss_merg: endpoint { 3279 remote-endpoint = <&funnel_apss_merg_out_funnel_in1>; 3280 }; 3281 }; 3282 }; 3283 }; 3284 3285 funnel@6045000 { 3286 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3287 reg = <0 0x06045000 0 0x1000>; 3288 3289 clocks = <&aoss_qmp>; 3290 clock-names = "apb_pclk"; 3291 3292 out-ports { 3293 port { 3294 funnel_merg_out_funnel_swao: endpoint { 3295 remote-endpoint = <&funnel_swao_in_funnel_merg>; 3296 }; 3297 }; 3298 }; 3299 3300 in-ports { 3301 #address-cells = <1>; 3302 #size-cells = <0>; 3303 3304 port@0 { 3305 reg = <0>; 3306 funnel_merg_in_funnel_in0: endpoint { 3307 remote-endpoint = <&funnel_in0_out_funnel_merg>; 3308 }; 3309 }; 3310 3311 port@1 { 3312 reg = <1>; 3313 funnel_merg_in_funnel_in1: endpoint { 3314 remote-endpoint = <&funnel_in1_out_funnel_merg>; 3315 }; 3316 }; 3317 }; 3318 }; 3319 3320 replicator@6046000 { 3321 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3322 reg = <0 0x06046000 0 0x1000>; 3323 3324 clocks = <&aoss_qmp>; 3325 clock-names = "apb_pclk"; 3326 3327 out-ports { 3328 port { 3329 replicator_out: endpoint { 3330 remote-endpoint = <&etr_in>; 3331 }; 3332 }; 3333 }; 3334 3335 in-ports { 3336 port { 3337 replicator_cx_in_swao_out: endpoint { 3338 remote-endpoint = <&replicator_swao_out_cx_in>; 3339 }; 3340 }; 3341 }; 3342 }; 3343 3344 etr@6048000 { 3345 compatible = "arm,coresight-tmc", "arm,primecell"; 3346 reg = <0 0x06048000 0 0x1000>; 3347 3348 clocks = <&aoss_qmp>; 3349 clock-names = "apb_pclk"; 3350 arm,scatter-gather; 3351 3352 in-ports { 3353 port { 3354 etr_in: endpoint { 3355 remote-endpoint = <&replicator_out>; 3356 }; 3357 }; 3358 }; 3359 }; 3360 3361 tpdm@684c000 { 3362 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3363 reg = <0 0x0684c000 0 0x1000>; 3364 3365 clocks = <&aoss_qmp>; 3366 clock-names = "apb_pclk"; 3367 3368 out-ports { 3369 port { 3370 tpdm_prng_out_tpda_23: endpoint { 3371 remote-endpoint = <&tpda_23_in_tpdm_prng>; 3372 }; 3373 }; 3374 }; 3375 }; 3376 3377 funnel@6b04000 { 3378 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3379 arm,primecell-periphid = <0x000bb908>; 3380 3381 reg = <0 0x06b04000 0 0x1000>; 3382 3383 clocks = <&aoss_qmp>; 3384 clock-names = "apb_pclk"; 3385 3386 out-ports { 3387 port { 3388 funnel_swao_out_etf: endpoint { 3389 remote-endpoint = <&etf_in_funnel_swao_out>; 3390 }; 3391 }; 3392 }; 3393 3394 in-ports { 3395 #address-cells = <1>; 3396 #size-cells = <0>; 3397 3398 port@7 { 3399 reg = <7>; 3400 funnel_swao_in_funnel_merg: endpoint { 3401 remote-endpoint = <&funnel_merg_out_funnel_swao>; 3402 }; 3403 }; 3404 }; 3405 }; 3406 3407 etf@6b05000 { 3408 compatible = "arm,coresight-tmc", "arm,primecell"; 3409 reg = <0 0x06b05000 0 0x1000>; 3410 3411 clocks = <&aoss_qmp>; 3412 clock-names = "apb_pclk"; 3413 3414 out-ports { 3415 port { 3416 etf_out: endpoint { 3417 remote-endpoint = <&replicator_in>; 3418 }; 3419 }; 3420 }; 3421 3422 in-ports { 3423 3424 port { 3425 etf_in_funnel_swao_out: endpoint { 3426 remote-endpoint = <&funnel_swao_out_etf>; 3427 }; 3428 }; 3429 }; 3430 }; 3431 3432 replicator@6b06000 { 3433 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3434 reg = <0 0x06b06000 0 0x1000>; 3435 3436 clocks = <&aoss_qmp>; 3437 clock-names = "apb_pclk"; 3438 3439 out-ports { 3440 port { 3441 replicator_swao_out_cx_in: endpoint { 3442 remote-endpoint = <&replicator_cx_in_swao_out>; 3443 }; 3444 }; 3445 }; 3446 3447 in-ports { 3448 port { 3449 replicator_in: endpoint { 3450 remote-endpoint = <&etf_out>; 3451 }; 3452 }; 3453 }; 3454 }; 3455 3456 tpdm@6c08000 { 3457 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3458 reg = <0 0x06c08000 0 0x1000>; 3459 3460 clocks = <&aoss_qmp>; 3461 clock-names = "apb_pclk"; 3462 3463 out-ports { 3464 port { 3465 tpdm_mm_out_funnel_dl_mm: endpoint { 3466 remote-endpoint = <&funnel_dl_mm_in_tpdm_mm>; 3467 }; 3468 }; 3469 }; 3470 }; 3471 3472 funnel@6c0b000 { 3473 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3474 reg = <0 0x06c0b000 0 0x1000>; 3475 3476 clocks = <&aoss_qmp>; 3477 clock-names = "apb_pclk"; 3478 3479 out-ports { 3480 port { 3481 funnel_dl_mm_out_funnel_dl_center: endpoint { 3482 remote-endpoint = <&funnel_dl_center_in_funnel_dl_mm>; 3483 }; 3484 }; 3485 }; 3486 3487 in-ports { 3488 #address-cells = <1>; 3489 #size-cells = <0>; 3490 3491 port@3 { 3492 reg = <3>; 3493 funnel_dl_mm_in_tpdm_mm: endpoint { 3494 remote-endpoint = <&tpdm_mm_out_funnel_dl_mm>; 3495 }; 3496 }; 3497 }; 3498 }; 3499 3500 funnel@6c2d000 { 3501 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3502 reg = <0 0x06c2d000 0 0x1000>; 3503 3504 clocks = <&aoss_qmp>; 3505 clock-names = "apb_pclk"; 3506 3507 out-ports { 3508 port { 3509 tpdm_mm_out_tpda9: endpoint { 3510 remote-endpoint = <&tpda_9_in_tpdm_mm>; 3511 }; 3512 }; 3513 }; 3514 3515 in-ports { 3516 #address-cells = <1>; 3517 #size-cells = <0>; 3518 3519 port@2 { 3520 reg = <2>; 3521 funnel_dl_center_in_funnel_dl_mm: endpoint { 3522 remote-endpoint = <&funnel_dl_mm_out_funnel_dl_center>; 3523 }; 3524 }; 3525 }; 3526 }; 3527 3528 etm@7040000 { 3529 compatible = "arm,coresight-etm4x", "arm,primecell"; 3530 reg = <0 0x07040000 0 0x1000>; 3531 3532 cpu = <&cpu0>; 3533 3534 clocks = <&aoss_qmp>; 3535 clock-names = "apb_pclk"; 3536 arm,coresight-loses-context-with-cpu; 3537 3538 out-ports { 3539 port { 3540 etm0_out: endpoint { 3541 remote-endpoint = <&apss_funnel_in0>; 3542 }; 3543 }; 3544 }; 3545 }; 3546 3547 etm@7140000 { 3548 compatible = "arm,coresight-etm4x", "arm,primecell"; 3549 reg = <0 0x07140000 0 0x1000>; 3550 3551 cpu = <&cpu1>; 3552 3553 clocks = <&aoss_qmp>; 3554 clock-names = "apb_pclk"; 3555 arm,coresight-loses-context-with-cpu; 3556 3557 out-ports { 3558 port { 3559 etm1_out: endpoint { 3560 remote-endpoint = <&apss_funnel_in1>; 3561 }; 3562 }; 3563 }; 3564 }; 3565 3566 etm@7240000 { 3567 compatible = "arm,coresight-etm4x", "arm,primecell"; 3568 reg = <0 0x07240000 0 0x1000>; 3569 3570 cpu = <&cpu2>; 3571 3572 clocks = <&aoss_qmp>; 3573 clock-names = "apb_pclk"; 3574 arm,coresight-loses-context-with-cpu; 3575 3576 out-ports { 3577 port { 3578 etm2_out: endpoint { 3579 remote-endpoint = <&apss_funnel_in2>; 3580 }; 3581 }; 3582 }; 3583 }; 3584 3585 etm@7340000 { 3586 compatible = "arm,coresight-etm4x", "arm,primecell"; 3587 reg = <0 0x07340000 0 0x1000>; 3588 3589 cpu = <&cpu3>; 3590 3591 clocks = <&aoss_qmp>; 3592 clock-names = "apb_pclk"; 3593 arm,coresight-loses-context-with-cpu; 3594 3595 out-ports { 3596 port { 3597 etm3_out: endpoint { 3598 remote-endpoint = <&apss_funnel_in3>; 3599 }; 3600 }; 3601 }; 3602 }; 3603 3604 etm@7440000 { 3605 compatible = "arm,coresight-etm4x", "arm,primecell"; 3606 reg = <0 0x07440000 0 0x1000>; 3607 3608 cpu = <&cpu4>; 3609 3610 clocks = <&aoss_qmp>; 3611 clock-names = "apb_pclk"; 3612 arm,coresight-loses-context-with-cpu; 3613 3614 out-ports { 3615 port { 3616 etm4_out: endpoint { 3617 remote-endpoint = <&apss_funnel_in4>; 3618 }; 3619 }; 3620 }; 3621 }; 3622 3623 etm@7540000 { 3624 compatible = "arm,coresight-etm4x", "arm,primecell"; 3625 reg = <0 0x07540000 0 0x1000>; 3626 3627 cpu = <&cpu5>; 3628 3629 clocks = <&aoss_qmp>; 3630 clock-names = "apb_pclk"; 3631 arm,coresight-loses-context-with-cpu; 3632 3633 out-ports { 3634 port { 3635 etm5_out: endpoint { 3636 remote-endpoint = <&apss_funnel_in5>; 3637 }; 3638 }; 3639 }; 3640 }; 3641 3642 etm@7640000 { 3643 compatible = "arm,coresight-etm4x", "arm,primecell"; 3644 reg = <0 0x07640000 0 0x1000>; 3645 3646 cpu = <&cpu6>; 3647 3648 clocks = <&aoss_qmp>; 3649 clock-names = "apb_pclk"; 3650 arm,coresight-loses-context-with-cpu; 3651 3652 out-ports { 3653 port { 3654 etm6_out: endpoint { 3655 remote-endpoint = <&apss_funnel_in6>; 3656 }; 3657 }; 3658 }; 3659 }; 3660 3661 etm@7740000 { 3662 compatible = "arm,coresight-etm4x", "arm,primecell"; 3663 reg = <0 0x07740000 0 0x1000>; 3664 3665 cpu = <&cpu7>; 3666 3667 clocks = <&aoss_qmp>; 3668 clock-names = "apb_pclk"; 3669 arm,coresight-loses-context-with-cpu; 3670 3671 out-ports { 3672 port { 3673 etm7_out: endpoint { 3674 remote-endpoint = <&apss_funnel_in7>; 3675 }; 3676 }; 3677 }; 3678 }; 3679 3680 funnel@7800000 { 3681 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3682 reg = <0 0x07800000 0 0x1000>; 3683 3684 clocks = <&aoss_qmp>; 3685 clock-names = "apb_pclk"; 3686 3687 out-ports { 3688 port { 3689 funnel_apss_out_funnel_apss_merg: endpoint { 3690 remote-endpoint = <&funnel_apss_merg_in_funnel_apss>; 3691 }; 3692 }; 3693 }; 3694 3695 in-ports { 3696 #address-cells = <1>; 3697 #size-cells = <0>; 3698 3699 port@0 { 3700 reg = <0>; 3701 apss_funnel_in0: endpoint { 3702 remote-endpoint = <&etm0_out>; 3703 }; 3704 }; 3705 3706 port@1 { 3707 reg = <1>; 3708 apss_funnel_in1: endpoint { 3709 remote-endpoint = <&etm1_out>; 3710 }; 3711 }; 3712 3713 port@2 { 3714 reg = <2>; 3715 apss_funnel_in2: endpoint { 3716 remote-endpoint = <&etm2_out>; 3717 }; 3718 }; 3719 3720 port@3 { 3721 reg = <3>; 3722 apss_funnel_in3: endpoint { 3723 remote-endpoint = <&etm3_out>; 3724 }; 3725 }; 3726 3727 port@4 { 3728 reg = <4>; 3729 apss_funnel_in4: endpoint { 3730 remote-endpoint = <&etm4_out>; 3731 }; 3732 }; 3733 3734 port@5 { 3735 reg = <5>; 3736 apss_funnel_in5: endpoint { 3737 remote-endpoint = <&etm5_out>; 3738 }; 3739 }; 3740 3741 port@6 { 3742 reg = <6>; 3743 apss_funnel_in6: endpoint { 3744 remote-endpoint = <&etm6_out>; 3745 }; 3746 }; 3747 3748 port@7 { 3749 reg = <7>; 3750 apss_funnel_in7: endpoint { 3751 remote-endpoint = <&etm7_out>; 3752 }; 3753 }; 3754 }; 3755 }; 3756 3757 funnel@7810000 { 3758 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3759 reg = <0 0x07810000 0 0x1000>; 3760 3761 clocks = <&aoss_qmp>; 3762 clock-names = "apb_pclk"; 3763 3764 out-ports { 3765 port { 3766 funnel_apss_merg_out_funnel_in1: endpoint { 3767 remote-endpoint = <&funnel_in1_in_funnel_apss_merg>; 3768 }; 3769 }; 3770 }; 3771 3772 in-ports { 3773 port { 3774 funnel_apss_merg_in_funnel_apss: endpoint { 3775 remote-endpoint = <&funnel_apss_out_funnel_apss_merg>; 3776 }; 3777 }; 3778 }; 3779 }; 3780 3781 cdsp: remoteproc@8300000 { 3782 compatible = "qcom,sm8250-cdsp-pas"; 3783 reg = <0 0x08300000 0 0x10000>; 3784 3785 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3786 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3787 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3788 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3789 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3790 interrupt-names = "wdog", "fatal", "ready", 3791 "handover", "stop-ack"; 3792 3793 clocks = <&rpmhcc RPMH_CXO_CLK>; 3794 clock-names = "xo"; 3795 3796 power-domains = <&rpmhpd RPMHPD_CX>; 3797 3798 memory-region = <&cdsp_mem>; 3799 3800 qcom,qmp = <&aoss_qmp>; 3801 3802 qcom,smem-states = <&smp2p_cdsp_out 0>; 3803 qcom,smem-state-names = "stop"; 3804 3805 status = "disabled"; 3806 3807 glink-edge { 3808 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3809 IPCC_MPROC_SIGNAL_GLINK_QMP 3810 IRQ_TYPE_EDGE_RISING>; 3811 mboxes = <&ipcc IPCC_CLIENT_CDSP 3812 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3813 3814 label = "cdsp"; 3815 qcom,remote-pid = <5>; 3816 3817 fastrpc { 3818 compatible = "qcom,fastrpc"; 3819 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3820 label = "cdsp"; 3821 qcom,non-secure-domain; 3822 #address-cells = <1>; 3823 #size-cells = <0>; 3824 3825 compute-cb@1 { 3826 compatible = "qcom,fastrpc-compute-cb"; 3827 reg = <1>; 3828 iommus = <&apps_smmu 0x1001 0x0460>; 3829 }; 3830 3831 compute-cb@2 { 3832 compatible = "qcom,fastrpc-compute-cb"; 3833 reg = <2>; 3834 iommus = <&apps_smmu 0x1002 0x0460>; 3835 }; 3836 3837 compute-cb@3 { 3838 compatible = "qcom,fastrpc-compute-cb"; 3839 reg = <3>; 3840 iommus = <&apps_smmu 0x1003 0x0460>; 3841 }; 3842 3843 compute-cb@4 { 3844 compatible = "qcom,fastrpc-compute-cb"; 3845 reg = <4>; 3846 iommus = <&apps_smmu 0x1004 0x0460>; 3847 }; 3848 3849 compute-cb@5 { 3850 compatible = "qcom,fastrpc-compute-cb"; 3851 reg = <5>; 3852 iommus = <&apps_smmu 0x1005 0x0460>; 3853 }; 3854 3855 compute-cb@6 { 3856 compatible = "qcom,fastrpc-compute-cb"; 3857 reg = <6>; 3858 iommus = <&apps_smmu 0x1006 0x0460>; 3859 }; 3860 3861 compute-cb@7 { 3862 compatible = "qcom,fastrpc-compute-cb"; 3863 reg = <7>; 3864 iommus = <&apps_smmu 0x1007 0x0460>; 3865 }; 3866 3867 compute-cb@8 { 3868 compatible = "qcom,fastrpc-compute-cb"; 3869 reg = <8>; 3870 iommus = <&apps_smmu 0x1008 0x0460>; 3871 }; 3872 3873 /* note: secure cb9 in downstream */ 3874 }; 3875 }; 3876 }; 3877 3878 usb_1_hsphy: phy@88e3000 { 3879 compatible = "qcom,sm8250-usb-hs-phy", 3880 "qcom,usb-snps-hs-7nm-phy"; 3881 reg = <0 0x088e3000 0 0x400>; 3882 status = "disabled"; 3883 #phy-cells = <0>; 3884 3885 clocks = <&rpmhcc RPMH_CXO_CLK>; 3886 clock-names = "ref"; 3887 3888 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3889 }; 3890 3891 usb_2_hsphy: phy@88e4000 { 3892 compatible = "qcom,sm8250-usb-hs-phy", 3893 "qcom,usb-snps-hs-7nm-phy"; 3894 reg = <0 0x088e4000 0 0x400>; 3895 status = "disabled"; 3896 #phy-cells = <0>; 3897 3898 clocks = <&rpmhcc RPMH_CXO_CLK>; 3899 clock-names = "ref"; 3900 3901 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3902 }; 3903 3904 usb_1_qmpphy: phy@88e8000 { 3905 compatible = "qcom,sm8250-qmp-usb3-dp-phy"; 3906 reg = <0 0x088e8000 0 0x3000>; 3907 status = "disabled"; 3908 3909 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3910 <&rpmhcc RPMH_CXO_CLK>, 3911 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3912 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3913 clock-names = "aux", 3914 "ref", 3915 "com_aux", 3916 "usb3_pipe"; 3917 3918 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3919 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3920 reset-names = "phy", "common"; 3921 3922 #clock-cells = <1>; 3923 #phy-cells = <1>; 3924 3925 orientation-switch; 3926 3927 ports { 3928 #address-cells = <1>; 3929 #size-cells = <0>; 3930 3931 port@0 { 3932 reg = <0>; 3933 usb_1_qmpphy_out: endpoint {}; 3934 }; 3935 3936 port@1 { 3937 reg = <1>; 3938 3939 usb_1_qmpphy_usb_ss_in: endpoint { 3940 remote-endpoint = <&usb_1_dwc3_ss_out>; 3941 }; 3942 }; 3943 3944 port@2 { 3945 reg = <2>; 3946 3947 usb_1_qmpphy_dp_in: endpoint {}; 3948 }; 3949 }; 3950 }; 3951 3952 usb_2_qmpphy: phy@88eb000 { 3953 compatible = "qcom,sm8250-qmp-usb3-uni-phy"; 3954 reg = <0 0x088eb000 0 0x1000>; 3955 3956 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3957 <&gcc GCC_USB3_SEC_CLKREF_EN>, 3958 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 3959 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3960 clock-names = "aux", 3961 "ref", 3962 "com_aux", 3963 "pipe"; 3964 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3965 #clock-cells = <0>; 3966 #phy-cells = <0>; 3967 3968 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 3969 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 3970 reset-names = "phy", 3971 "phy_phy"; 3972 3973 status = "disabled"; 3974 }; 3975 3976 sdhc_2: mmc@8804000 { 3977 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; 3978 reg = <0 0x08804000 0 0x1000>; 3979 3980 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3981 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3982 interrupt-names = "hc_irq", "pwr_irq"; 3983 3984 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3985 <&gcc GCC_SDCC2_APPS_CLK>, 3986 <&rpmhcc RPMH_CXO_CLK>; 3987 clock-names = "iface", "core", "xo"; 3988 iommus = <&apps_smmu 0x4a0 0x0>; 3989 qcom,dll-config = <0x0007642c>; 3990 qcom,ddr-config = <0x80040868>; 3991 power-domains = <&rpmhpd RPMHPD_CX>; 3992 operating-points-v2 = <&sdhc2_opp_table>; 3993 3994 status = "disabled"; 3995 3996 sdhc2_opp_table: opp-table { 3997 compatible = "operating-points-v2"; 3998 3999 opp-19200000 { 4000 opp-hz = /bits/ 64 <19200000>; 4001 required-opps = <&rpmhpd_opp_min_svs>; 4002 }; 4003 4004 opp-50000000 { 4005 opp-hz = /bits/ 64 <50000000>; 4006 required-opps = <&rpmhpd_opp_low_svs>; 4007 }; 4008 4009 opp-100000000 { 4010 opp-hz = /bits/ 64 <100000000>; 4011 required-opps = <&rpmhpd_opp_svs>; 4012 }; 4013 4014 opp-202000000 { 4015 opp-hz = /bits/ 64 <202000000>; 4016 required-opps = <&rpmhpd_opp_svs_l1>; 4017 }; 4018 }; 4019 }; 4020 4021 pmu@9091000 { 4022 compatible = "qcom,sm8250-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 4023 reg = <0 0x09091000 0 0x1000>; 4024 4025 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 4026 4027 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI_CH0 3>; 4028 4029 operating-points-v2 = <&llcc_bwmon_opp_table>; 4030 4031 llcc_bwmon_opp_table: opp-table { 4032 compatible = "operating-points-v2"; 4033 4034 opp-800000 { 4035 opp-peak-kBps = <(200 * 4 * 1000)>; 4036 }; 4037 4038 opp-1200000 { 4039 opp-peak-kBps = <(300 * 4 * 1000)>; 4040 }; 4041 4042 opp-1804000 { 4043 opp-peak-kBps = <(451 * 4 * 1000)>; 4044 }; 4045 4046 opp-2188000 { 4047 opp-peak-kBps = <(547 * 4 * 1000)>; 4048 }; 4049 4050 opp-2724000 { 4051 opp-peak-kBps = <(681 * 4 * 1000)>; 4052 }; 4053 4054 opp-3072000 { 4055 opp-peak-kBps = <(768 * 4 * 1000)>; 4056 }; 4057 4058 opp-4068000 { 4059 opp-peak-kBps = <(1017 * 4 * 1000)>; 4060 }; 4061 4062 /* 1353 MHz, LPDDR4X */ 4063 4064 opp-6220000 { 4065 opp-peak-kBps = <(1555 * 4 * 1000)>; 4066 }; 4067 4068 opp-7216000 { 4069 opp-peak-kBps = <(1804 * 4 * 1000)>; 4070 }; 4071 4072 opp-8368000 { 4073 opp-peak-kBps = <(2092 * 4 * 1000)>; 4074 }; 4075 4076 /* LPDDR5 */ 4077 opp-10944000 { 4078 opp-peak-kBps = <(2736 * 4 * 1000)>; 4079 }; 4080 }; 4081 }; 4082 4083 pmu@90b6400 { 4084 compatible = "qcom,sm8250-cpu-bwmon", "qcom,sdm845-bwmon"; 4085 reg = <0 0x090b6400 0 0x600>; 4086 4087 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4088 4089 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &gem_noc SLAVE_LLCC 3>; 4090 operating-points-v2 = <&cpu_bwmon_opp_table>; 4091 4092 cpu_bwmon_opp_table: opp-table { 4093 compatible = "operating-points-v2"; 4094 4095 opp-800000 { 4096 opp-peak-kBps = <(200 * 4 * 1000)>; 4097 }; 4098 4099 opp-1804000 { 4100 opp-peak-kBps = <(451 * 4 * 1000)>; 4101 }; 4102 4103 opp-2188000 { 4104 opp-peak-kBps = <(547 * 4 * 1000)>; 4105 }; 4106 4107 opp-2724000 { 4108 opp-peak-kBps = <(681 * 4 * 1000)>; 4109 }; 4110 4111 opp-3072000 { 4112 opp-peak-kBps = <(768 * 4 * 1000)>; 4113 }; 4114 4115 /* 1017MHz, 1353 MHz, LPDDR4X */ 4116 4117 opp-6220000 { 4118 opp-peak-kBps = <(1555 * 4 * 1000)>; 4119 }; 4120 4121 opp-6832000 { 4122 opp-peak-kBps = <(1708 * 4 * 1000)>; 4123 }; 4124 4125 opp-8368000 { 4126 opp-peak-kBps = <(2092 * 4 * 1000)>; 4127 }; 4128 4129 /* 2133MHz, LPDDR4X */ 4130 4131 /* LPDDR5 */ 4132 opp-10944000 { 4133 opp-peak-kBps = <(2736 * 4 * 1000)>; 4134 }; 4135 4136 /* LPDDR5 */ 4137 opp-12784000 { 4138 opp-peak-kBps = <(3196 * 4 * 1000)>; 4139 }; 4140 }; 4141 }; 4142 4143 dc_noc: interconnect@90c0000 { 4144 compatible = "qcom,sm8250-dc-noc"; 4145 reg = <0 0x090c0000 0 0x4200>; 4146 #interconnect-cells = <2>; 4147 qcom,bcm-voters = <&apps_bcm_voter>; 4148 }; 4149 4150 gem_noc: interconnect@9100000 { 4151 compatible = "qcom,sm8250-gem-noc"; 4152 reg = <0 0x09100000 0 0xb4000>; 4153 #interconnect-cells = <2>; 4154 qcom,bcm-voters = <&apps_bcm_voter>; 4155 }; 4156 4157 npu_noc: interconnect@9990000 { 4158 compatible = "qcom,sm8250-npu-noc"; 4159 reg = <0 0x09990000 0 0x1600>; 4160 #interconnect-cells = <2>; 4161 qcom,bcm-voters = <&apps_bcm_voter>; 4162 }; 4163 4164 usb_1: usb@a6f8800 { 4165 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 4166 reg = <0 0x0a6f8800 0 0x400>; 4167 status = "disabled"; 4168 #address-cells = <2>; 4169 #size-cells = <2>; 4170 ranges; 4171 dma-ranges; 4172 4173 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4174 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4175 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4176 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4177 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4178 <&gcc GCC_USB3_SEC_CLKREF_EN>; 4179 clock-names = "cfg_noc", 4180 "core", 4181 "iface", 4182 "sleep", 4183 "mock_utmi", 4184 "xo"; 4185 4186 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4187 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4188 assigned-clock-rates = <19200000>, <200000000>; 4189 4190 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4191 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4192 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4193 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4194 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 4195 interrupt-names = "pwr_event", 4196 "hs_phy_irq", 4197 "dp_hs_phy_irq", 4198 "dm_hs_phy_irq", 4199 "ss_phy_irq"; 4200 4201 power-domains = <&gcc USB30_PRIM_GDSC>; 4202 wakeup-source; 4203 4204 resets = <&gcc GCC_USB30_PRIM_BCR>; 4205 4206 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, 4207 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 4208 interconnect-names = "usb-ddr", "apps-usb"; 4209 4210 usb_1_dwc3: usb@a600000 { 4211 compatible = "snps,dwc3"; 4212 reg = <0 0x0a600000 0 0xcd00>; 4213 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4214 iommus = <&apps_smmu 0x0 0x0>; 4215 snps,dis_u2_susphy_quirk; 4216 snps,dis_enblslpm_quirk; 4217 snps,dis-u1-entry-quirk; 4218 snps,dis-u2-entry-quirk; 4219 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4220 phy-names = "usb2-phy", "usb3-phy"; 4221 4222 ports { 4223 #address-cells = <1>; 4224 #size-cells = <0>; 4225 4226 port@0 { 4227 reg = <0>; 4228 4229 usb_1_dwc3_hs_out: endpoint { 4230 }; 4231 }; 4232 4233 port@1 { 4234 reg = <1>; 4235 4236 usb_1_dwc3_ss_out: endpoint { 4237 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 4238 }; 4239 }; 4240 }; 4241 }; 4242 }; 4243 4244 system-cache-controller@9200000 { 4245 compatible = "qcom,sm8250-llcc"; 4246 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, 4247 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, 4248 <0 0x09600000 0 0x50000>; 4249 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 4250 "llcc3_base", "llcc_broadcast_base"; 4251 }; 4252 4253 usb_2: usb@a8f8800 { 4254 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 4255 reg = <0 0x0a8f8800 0 0x400>; 4256 status = "disabled"; 4257 #address-cells = <2>; 4258 #size-cells = <2>; 4259 ranges; 4260 dma-ranges; 4261 4262 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4263 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4264 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4265 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4266 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4267 <&gcc GCC_USB3_SEC_CLKREF_EN>; 4268 clock-names = "cfg_noc", 4269 "core", 4270 "iface", 4271 "sleep", 4272 "mock_utmi", 4273 "xo"; 4274 4275 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4276 <&gcc GCC_USB30_SEC_MASTER_CLK>; 4277 assigned-clock-rates = <19200000>, <200000000>; 4278 4279 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 4280 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 4281 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 4282 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 4283 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 4284 interrupt-names = "pwr_event", 4285 "hs_phy_irq", 4286 "dp_hs_phy_irq", 4287 "dm_hs_phy_irq", 4288 "ss_phy_irq"; 4289 4290 power-domains = <&gcc USB30_SEC_GDSC>; 4291 wakeup-source; 4292 4293 resets = <&gcc GCC_USB30_SEC_BCR>; 4294 4295 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, 4296 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; 4297 interconnect-names = "usb-ddr", "apps-usb"; 4298 4299 usb_2_dwc3: usb@a800000 { 4300 compatible = "snps,dwc3"; 4301 reg = <0 0x0a800000 0 0xcd00>; 4302 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 4303 iommus = <&apps_smmu 0x20 0>; 4304 snps,dis_u2_susphy_quirk; 4305 snps,dis_enblslpm_quirk; 4306 snps,dis-u1-entry-quirk; 4307 snps,dis-u2-entry-quirk; 4308 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>; 4309 phy-names = "usb2-phy", "usb3-phy"; 4310 }; 4311 }; 4312 4313 venus: video-codec@aa00000 { 4314 compatible = "qcom,sm8250-venus"; 4315 reg = <0 0x0aa00000 0 0x100000>; 4316 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4317 power-domains = <&videocc MVS0C_GDSC>, 4318 <&videocc MVS0_GDSC>, 4319 <&rpmhpd RPMHPD_MX>; 4320 power-domain-names = "venus", "vcodec0", "mx"; 4321 operating-points-v2 = <&venus_opp_table>; 4322 4323 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 4324 <&videocc VIDEO_CC_MVS0C_CLK>, 4325 <&videocc VIDEO_CC_MVS0_CLK>; 4326 clock-names = "iface", "core", "vcodec0_core"; 4327 4328 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_VENUS_CFG 0>, 4329 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI_CH0 0>; 4330 interconnect-names = "cpu-cfg", "video-mem"; 4331 4332 iommus = <&apps_smmu 0x2100 0x0400>; 4333 memory-region = <&video_mem>; 4334 4335 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 4336 <&videocc VIDEO_CC_MVS0C_CLK_ARES>; 4337 reset-names = "bus", "core"; 4338 4339 status = "disabled"; 4340 4341 venus_opp_table: opp-table { 4342 compatible = "operating-points-v2"; 4343 4344 opp-720000000 { 4345 opp-hz = /bits/ 64 <720000000>; 4346 required-opps = <&rpmhpd_opp_low_svs>; 4347 }; 4348 4349 opp-1014000000 { 4350 opp-hz = /bits/ 64 <1014000000>; 4351 required-opps = <&rpmhpd_opp_svs>; 4352 }; 4353 4354 opp-1098000000 { 4355 opp-hz = /bits/ 64 <1098000000>; 4356 required-opps = <&rpmhpd_opp_svs_l1>; 4357 }; 4358 4359 opp-1332000000 { 4360 opp-hz = /bits/ 64 <1332000000>; 4361 required-opps = <&rpmhpd_opp_nom>; 4362 }; 4363 }; 4364 }; 4365 4366 videocc: clock-controller@abf0000 { 4367 compatible = "qcom,sm8250-videocc"; 4368 reg = <0 0x0abf0000 0 0x10000>; 4369 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 4370 <&rpmhcc RPMH_CXO_CLK>, 4371 <&rpmhcc RPMH_CXO_CLK_A>; 4372 power-domains = <&rpmhpd RPMHPD_MMCX>; 4373 required-opps = <&rpmhpd_opp_low_svs>; 4374 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; 4375 #clock-cells = <1>; 4376 #reset-cells = <1>; 4377 #power-domain-cells = <1>; 4378 }; 4379 4380 cci0: cci@ac4f000 { 4381 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci"; 4382 #address-cells = <1>; 4383 #size-cells = <0>; 4384 4385 reg = <0 0x0ac4f000 0 0x1000>; 4386 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4387 power-domains = <&camcc TITAN_TOP_GDSC>; 4388 4389 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4390 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4391 <&camcc CAM_CC_CPAS_AHB_CLK>, 4392 <&camcc CAM_CC_CCI_0_CLK>, 4393 <&camcc CAM_CC_CCI_0_CLK_SRC>; 4394 clock-names = "camnoc_axi", 4395 "slow_ahb_src", 4396 "cpas_ahb", 4397 "cci", 4398 "cci_src"; 4399 4400 pinctrl-0 = <&cci0_default>; 4401 pinctrl-1 = <&cci0_sleep>; 4402 pinctrl-names = "default", "sleep"; 4403 4404 status = "disabled"; 4405 4406 cci0_i2c0: i2c-bus@0 { 4407 reg = <0>; 4408 clock-frequency = <1000000>; 4409 #address-cells = <1>; 4410 #size-cells = <0>; 4411 }; 4412 4413 cci0_i2c1: i2c-bus@1 { 4414 reg = <1>; 4415 clock-frequency = <1000000>; 4416 #address-cells = <1>; 4417 #size-cells = <0>; 4418 }; 4419 }; 4420 4421 cci1: cci@ac50000 { 4422 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci"; 4423 #address-cells = <1>; 4424 #size-cells = <0>; 4425 4426 reg = <0 0x0ac50000 0 0x1000>; 4427 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 4428 power-domains = <&camcc TITAN_TOP_GDSC>; 4429 4430 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4431 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4432 <&camcc CAM_CC_CPAS_AHB_CLK>, 4433 <&camcc CAM_CC_CCI_1_CLK>, 4434 <&camcc CAM_CC_CCI_1_CLK_SRC>; 4435 clock-names = "camnoc_axi", 4436 "slow_ahb_src", 4437 "cpas_ahb", 4438 "cci", 4439 "cci_src"; 4440 4441 pinctrl-0 = <&cci1_default>; 4442 pinctrl-1 = <&cci1_sleep>; 4443 pinctrl-names = "default", "sleep"; 4444 4445 status = "disabled"; 4446 4447 cci1_i2c0: i2c-bus@0 { 4448 reg = <0>; 4449 clock-frequency = <1000000>; 4450 #address-cells = <1>; 4451 #size-cells = <0>; 4452 }; 4453 4454 cci1_i2c1: i2c-bus@1 { 4455 reg = <1>; 4456 clock-frequency = <1000000>; 4457 #address-cells = <1>; 4458 #size-cells = <0>; 4459 }; 4460 }; 4461 4462 camss: camss@ac6a000 { 4463 compatible = "qcom,sm8250-camss"; 4464 status = "disabled"; 4465 4466 reg = <0 0x0ac6a000 0 0x2000>, 4467 <0 0x0ac6c000 0 0x2000>, 4468 <0 0x0ac6e000 0 0x1000>, 4469 <0 0x0ac70000 0 0x1000>, 4470 <0 0x0ac72000 0 0x1000>, 4471 <0 0x0ac74000 0 0x1000>, 4472 <0 0x0acb4000 0 0xd000>, 4473 <0 0x0acc3000 0 0xd000>, 4474 <0 0x0acd9000 0 0x2200>, 4475 <0 0x0acdb200 0 0x2200>; 4476 reg-names = "csiphy0", 4477 "csiphy1", 4478 "csiphy2", 4479 "csiphy3", 4480 "csiphy4", 4481 "csiphy5", 4482 "vfe0", 4483 "vfe1", 4484 "vfe_lite0", 4485 "vfe_lite1"; 4486 4487 interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 4488 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 4489 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 4490 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 4491 <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>, 4492 <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>, 4493 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 4494 <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, 4495 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 4496 <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, 4497 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 4498 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 4499 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, 4500 <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>; 4501 interrupt-names = "csiphy0", 4502 "csiphy1", 4503 "csiphy2", 4504 "csiphy3", 4505 "csiphy4", 4506 "csiphy5", 4507 "csid0", 4508 "csid1", 4509 "csid2", 4510 "csid3", 4511 "vfe0", 4512 "vfe1", 4513 "vfe_lite0", 4514 "vfe_lite1"; 4515 4516 power-domains = <&camcc IFE_0_GDSC>, 4517 <&camcc IFE_1_GDSC>, 4518 <&camcc TITAN_TOP_GDSC>; 4519 4520 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4521 <&gcc GCC_CAMERA_HF_AXI_CLK>, 4522 <&gcc GCC_CAMERA_SF_AXI_CLK>, 4523 <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4524 <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, 4525 <&camcc CAM_CC_CORE_AHB_CLK>, 4526 <&camcc CAM_CC_CPAS_AHB_CLK>, 4527 <&camcc CAM_CC_CSIPHY0_CLK>, 4528 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 4529 <&camcc CAM_CC_CSIPHY1_CLK>, 4530 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 4531 <&camcc CAM_CC_CSIPHY2_CLK>, 4532 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 4533 <&camcc CAM_CC_CSIPHY3_CLK>, 4534 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 4535 <&camcc CAM_CC_CSIPHY4_CLK>, 4536 <&camcc CAM_CC_CSI4PHYTIMER_CLK>, 4537 <&camcc CAM_CC_CSIPHY5_CLK>, 4538 <&camcc CAM_CC_CSI5PHYTIMER_CLK>, 4539 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4540 <&camcc CAM_CC_IFE_0_AHB_CLK>, 4541 <&camcc CAM_CC_IFE_0_AXI_CLK>, 4542 <&camcc CAM_CC_IFE_0_CLK>, 4543 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 4544 <&camcc CAM_CC_IFE_0_CSID_CLK>, 4545 <&camcc CAM_CC_IFE_0_AREG_CLK>, 4546 <&camcc CAM_CC_IFE_1_AHB_CLK>, 4547 <&camcc CAM_CC_IFE_1_AXI_CLK>, 4548 <&camcc CAM_CC_IFE_1_CLK>, 4549 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 4550 <&camcc CAM_CC_IFE_1_CSID_CLK>, 4551 <&camcc CAM_CC_IFE_1_AREG_CLK>, 4552 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 4553 <&camcc CAM_CC_IFE_LITE_AXI_CLK>, 4554 <&camcc CAM_CC_IFE_LITE_CLK>, 4555 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 4556 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 4557 4558 clock-names = "cam_ahb_clk", 4559 "cam_hf_axi", 4560 "cam_sf_axi", 4561 "camnoc_axi", 4562 "camnoc_axi_src", 4563 "core_ahb", 4564 "cpas_ahb", 4565 "csiphy0", 4566 "csiphy0_timer", 4567 "csiphy1", 4568 "csiphy1_timer", 4569 "csiphy2", 4570 "csiphy2_timer", 4571 "csiphy3", 4572 "csiphy3_timer", 4573 "csiphy4", 4574 "csiphy4_timer", 4575 "csiphy5", 4576 "csiphy5_timer", 4577 "slow_ahb_src", 4578 "vfe0_ahb", 4579 "vfe0_axi", 4580 "vfe0", 4581 "vfe0_cphy_rx", 4582 "vfe0_csid", 4583 "vfe0_areg", 4584 "vfe1_ahb", 4585 "vfe1_axi", 4586 "vfe1", 4587 "vfe1_cphy_rx", 4588 "vfe1_csid", 4589 "vfe1_areg", 4590 "vfe_lite_ahb", 4591 "vfe_lite_axi", 4592 "vfe_lite", 4593 "vfe_lite_cphy_rx", 4594 "vfe_lite_csid"; 4595 4596 iommus = <&apps_smmu 0x800 0x400>, 4597 <&apps_smmu 0x801 0x400>, 4598 <&apps_smmu 0x840 0x400>, 4599 <&apps_smmu 0x841 0x400>, 4600 <&apps_smmu 0xc00 0x400>, 4601 <&apps_smmu 0xc01 0x400>, 4602 <&apps_smmu 0xc40 0x400>, 4603 <&apps_smmu 0xc41 0x400>; 4604 4605 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_CAMERA_CFG 0>, 4606 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI_CH0 0>, 4607 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI_CH0 0>, 4608 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI_CH0 0>; 4609 interconnect-names = "cam_ahb", 4610 "cam_hf_0_mnoc", 4611 "cam_sf_0_mnoc", 4612 "cam_sf_icp_mnoc"; 4613 4614 ports { 4615 #address-cells = <1>; 4616 #size-cells = <0>; 4617 4618 port@0 { 4619 reg = <0>; 4620 }; 4621 4622 port@1 { 4623 reg = <1>; 4624 }; 4625 4626 port@2 { 4627 reg = <2>; 4628 }; 4629 4630 port@3 { 4631 reg = <3>; 4632 }; 4633 4634 port@4 { 4635 reg = <4>; 4636 }; 4637 4638 port@5 { 4639 reg = <5>; 4640 }; 4641 }; 4642 }; 4643 4644 camcc: clock-controller@ad00000 { 4645 compatible = "qcom,sm8250-camcc"; 4646 reg = <0 0x0ad00000 0 0x10000>; 4647 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4648 <&rpmhcc RPMH_CXO_CLK>, 4649 <&rpmhcc RPMH_CXO_CLK_A>, 4650 <&sleep_clk>; 4651 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 4652 power-domains = <&rpmhpd RPMHPD_MMCX>; 4653 required-opps = <&rpmhpd_opp_low_svs>; 4654 #clock-cells = <1>; 4655 #reset-cells = <1>; 4656 #power-domain-cells = <1>; 4657 }; 4658 4659 mdss: display-subsystem@ae00000 { 4660 compatible = "qcom,sm8250-mdss"; 4661 reg = <0 0x0ae00000 0 0x1000>; 4662 reg-names = "mdss"; 4663 4664 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>, 4665 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>; 4666 interconnect-names = "mdp0-mem", "mdp1-mem"; 4667 4668 power-domains = <&dispcc MDSS_GDSC>; 4669 4670 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4671 <&gcc GCC_DISP_HF_AXI_CLK>, 4672 <&gcc GCC_DISP_SF_AXI_CLK>, 4673 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4674 clock-names = "iface", "bus", "nrt_bus", "core"; 4675 4676 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4677 interrupt-controller; 4678 #interrupt-cells = <1>; 4679 4680 iommus = <&apps_smmu 0x820 0x402>; 4681 4682 status = "disabled"; 4683 4684 #address-cells = <2>; 4685 #size-cells = <2>; 4686 ranges; 4687 4688 mdss_mdp: display-controller@ae01000 { 4689 compatible = "qcom,sm8250-dpu"; 4690 reg = <0 0x0ae01000 0 0x8f000>, 4691 <0 0x0aeb0000 0 0x3000>; 4692 reg-names = "mdp", "vbif"; 4693 4694 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4695 <&gcc GCC_DISP_HF_AXI_CLK>, 4696 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4697 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4698 clock-names = "iface", "bus", "core", "vsync"; 4699 4700 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4701 assigned-clock-rates = <19200000>; 4702 4703 operating-points-v2 = <&mdp_opp_table>; 4704 power-domains = <&rpmhpd RPMHPD_MMCX>; 4705 4706 interrupt-parent = <&mdss>; 4707 interrupts = <0>; 4708 4709 ports { 4710 #address-cells = <1>; 4711 #size-cells = <0>; 4712 4713 port@0 { 4714 reg = <0>; 4715 dpu_intf1_out: endpoint { 4716 remote-endpoint = <&mdss_dsi0_in>; 4717 }; 4718 }; 4719 4720 port@1 { 4721 reg = <1>; 4722 dpu_intf2_out: endpoint { 4723 remote-endpoint = <&mdss_dsi1_in>; 4724 }; 4725 }; 4726 4727 port@2 { 4728 reg = <2>; 4729 4730 dpu_intf0_out: endpoint { 4731 remote-endpoint = <&mdss_dp_in>; 4732 }; 4733 }; 4734 }; 4735 4736 mdp_opp_table: opp-table { 4737 compatible = "operating-points-v2"; 4738 4739 opp-200000000 { 4740 opp-hz = /bits/ 64 <200000000>; 4741 required-opps = <&rpmhpd_opp_low_svs>; 4742 }; 4743 4744 opp-300000000 { 4745 opp-hz = /bits/ 64 <300000000>; 4746 required-opps = <&rpmhpd_opp_svs>; 4747 }; 4748 4749 opp-345000000 { 4750 opp-hz = /bits/ 64 <345000000>; 4751 required-opps = <&rpmhpd_opp_svs_l1>; 4752 }; 4753 4754 opp-460000000 { 4755 opp-hz = /bits/ 64 <460000000>; 4756 required-opps = <&rpmhpd_opp_nom>; 4757 }; 4758 }; 4759 }; 4760 4761 mdss_dp: displayport-controller@ae90000 { 4762 compatible = "qcom,sm8250-dp", "qcom,sm8350-dp"; 4763 reg = <0 0xae90000 0 0x200>, 4764 <0 0xae90200 0 0x200>, 4765 <0 0xae90400 0 0x600>, 4766 <0 0xae91000 0 0x400>, 4767 <0 0xae91400 0 0x400>; 4768 interrupt-parent = <&mdss>; 4769 interrupts = <12>; 4770 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4771 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4772 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4773 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4774 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, 4775 <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; 4776 clock-names = "core_iface", 4777 "core_aux", 4778 "ctrl_link", 4779 "ctrl_link_iface", 4780 "stream_pixel", 4781 "stream_1_pixel"; 4782 4783 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4784 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, 4785 <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; 4786 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4787 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4788 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4789 4790 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 4791 phy-names = "dp"; 4792 4793 #sound-dai-cells = <0>; 4794 4795 operating-points-v2 = <&dp_opp_table>; 4796 power-domains = <&rpmhpd RPMHPD_MMCX>; 4797 4798 status = "disabled"; 4799 4800 ports { 4801 #address-cells = <1>; 4802 #size-cells = <0>; 4803 4804 port@0 { 4805 reg = <0>; 4806 mdss_dp_in: endpoint { 4807 remote-endpoint = <&dpu_intf0_out>; 4808 }; 4809 }; 4810 4811 port@1 { 4812 reg = <1>; 4813 4814 mdss_dp_out: endpoint { 4815 }; 4816 }; 4817 }; 4818 4819 dp_opp_table: opp-table { 4820 compatible = "operating-points-v2"; 4821 4822 opp-160000000 { 4823 opp-hz = /bits/ 64 <160000000>; 4824 required-opps = <&rpmhpd_opp_low_svs>; 4825 }; 4826 4827 opp-270000000 { 4828 opp-hz = /bits/ 64 <270000000>; 4829 required-opps = <&rpmhpd_opp_svs>; 4830 }; 4831 4832 opp-540000000 { 4833 opp-hz = /bits/ 64 <540000000>; 4834 required-opps = <&rpmhpd_opp_svs_l1>; 4835 }; 4836 4837 opp-810000000 { 4838 opp-hz = /bits/ 64 <810000000>; 4839 required-opps = <&rpmhpd_opp_nom>; 4840 }; 4841 }; 4842 }; 4843 4844 mdss_dsi0: dsi@ae94000 { 4845 compatible = "qcom,sm8250-dsi-ctrl", 4846 "qcom,mdss-dsi-ctrl"; 4847 reg = <0 0x0ae94000 0 0x400>; 4848 reg-names = "dsi_ctrl"; 4849 4850 interrupt-parent = <&mdss>; 4851 interrupts = <4>; 4852 4853 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4854 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4855 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4856 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4857 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4858 <&gcc GCC_DISP_HF_AXI_CLK>; 4859 clock-names = "byte", 4860 "byte_intf", 4861 "pixel", 4862 "core", 4863 "iface", 4864 "bus"; 4865 4866 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 4867 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4868 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 4869 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 4870 4871 operating-points-v2 = <&dsi_opp_table>; 4872 power-domains = <&rpmhpd RPMHPD_MMCX>; 4873 4874 phys = <&mdss_dsi0_phy>; 4875 4876 status = "disabled"; 4877 4878 #address-cells = <1>; 4879 #size-cells = <0>; 4880 4881 ports { 4882 #address-cells = <1>; 4883 #size-cells = <0>; 4884 4885 port@0 { 4886 reg = <0>; 4887 mdss_dsi0_in: endpoint { 4888 remote-endpoint = <&dpu_intf1_out>; 4889 }; 4890 }; 4891 4892 port@1 { 4893 reg = <1>; 4894 mdss_dsi0_out: endpoint { 4895 }; 4896 }; 4897 }; 4898 4899 dsi_opp_table: opp-table { 4900 compatible = "operating-points-v2"; 4901 4902 opp-187500000 { 4903 opp-hz = /bits/ 64 <187500000>; 4904 required-opps = <&rpmhpd_opp_low_svs>; 4905 }; 4906 4907 opp-300000000 { 4908 opp-hz = /bits/ 64 <300000000>; 4909 required-opps = <&rpmhpd_opp_svs>; 4910 }; 4911 4912 opp-358000000 { 4913 opp-hz = /bits/ 64 <358000000>; 4914 required-opps = <&rpmhpd_opp_svs_l1>; 4915 }; 4916 }; 4917 }; 4918 4919 mdss_dsi0_phy: phy@ae94400 { 4920 compatible = "qcom,dsi-phy-7nm"; 4921 reg = <0 0x0ae94400 0 0x200>, 4922 <0 0x0ae94600 0 0x280>, 4923 <0 0x0ae94900 0 0x260>; 4924 reg-names = "dsi_phy", 4925 "dsi_phy_lane", 4926 "dsi_pll"; 4927 4928 #clock-cells = <1>; 4929 #phy-cells = <0>; 4930 4931 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4932 <&rpmhcc RPMH_CXO_CLK>; 4933 clock-names = "iface", "ref"; 4934 4935 status = "disabled"; 4936 }; 4937 4938 mdss_dsi1: dsi@ae96000 { 4939 compatible = "qcom,sm8250-dsi-ctrl", 4940 "qcom,mdss-dsi-ctrl"; 4941 reg = <0 0x0ae96000 0 0x400>; 4942 reg-names = "dsi_ctrl"; 4943 4944 interrupt-parent = <&mdss>; 4945 interrupts = <5>; 4946 4947 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 4948 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 4949 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 4950 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 4951 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4952 <&gcc GCC_DISP_HF_AXI_CLK>; 4953 clock-names = "byte", 4954 "byte_intf", 4955 "pixel", 4956 "core", 4957 "iface", 4958 "bus"; 4959 4960 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 4961 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 4962 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 4963 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 4964 4965 operating-points-v2 = <&dsi_opp_table>; 4966 power-domains = <&rpmhpd RPMHPD_MMCX>; 4967 4968 phys = <&mdss_dsi1_phy>; 4969 4970 status = "disabled"; 4971 4972 #address-cells = <1>; 4973 #size-cells = <0>; 4974 4975 ports { 4976 #address-cells = <1>; 4977 #size-cells = <0>; 4978 4979 port@0 { 4980 reg = <0>; 4981 mdss_dsi1_in: endpoint { 4982 remote-endpoint = <&dpu_intf2_out>; 4983 }; 4984 }; 4985 4986 port@1 { 4987 reg = <1>; 4988 mdss_dsi1_out: endpoint { 4989 }; 4990 }; 4991 }; 4992 }; 4993 4994 mdss_dsi1_phy: phy@ae96400 { 4995 compatible = "qcom,dsi-phy-7nm"; 4996 reg = <0 0x0ae96400 0 0x200>, 4997 <0 0x0ae96600 0 0x280>, 4998 <0 0x0ae96900 0 0x260>; 4999 reg-names = "dsi_phy", 5000 "dsi_phy_lane", 5001 "dsi_pll"; 5002 5003 #clock-cells = <1>; 5004 #phy-cells = <0>; 5005 5006 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5007 <&rpmhcc RPMH_CXO_CLK>; 5008 clock-names = "iface", "ref"; 5009 5010 status = "disabled"; 5011 }; 5012 }; 5013 5014 dispcc: clock-controller@af00000 { 5015 compatible = "qcom,sm8250-dispcc"; 5016 reg = <0 0x0af00000 0 0x10000>; 5017 power-domains = <&rpmhpd RPMHPD_MMCX>; 5018 required-opps = <&rpmhpd_opp_low_svs>; 5019 clocks = <&rpmhcc RPMH_CXO_CLK>, 5020 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 5021 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 5022 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 5023 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 5024 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5025 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5026 clock-names = "bi_tcxo", 5027 "dsi0_phy_pll_out_byteclk", 5028 "dsi0_phy_pll_out_dsiclk", 5029 "dsi1_phy_pll_out_byteclk", 5030 "dsi1_phy_pll_out_dsiclk", 5031 "dp_phy_pll_link_clk", 5032 "dp_phy_pll_vco_div_clk"; 5033 #clock-cells = <1>; 5034 #reset-cells = <1>; 5035 #power-domain-cells = <1>; 5036 }; 5037 5038 pdc: interrupt-controller@b220000 { 5039 compatible = "qcom,sm8250-pdc", "qcom,pdc"; 5040 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 5041 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 5042 <125 63 1>, <126 716 12>; 5043 #interrupt-cells = <2>; 5044 interrupt-parent = <&intc>; 5045 interrupt-controller; 5046 }; 5047 5048 tsens0: thermal-sensor@c263000 { 5049 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 5050 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 5051 <0 0x0c222000 0 0x1ff>; /* SROT */ 5052 #qcom,sensors = <16>; 5053 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 5054 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 5055 interrupt-names = "uplow", "critical"; 5056 #thermal-sensor-cells = <1>; 5057 }; 5058 5059 tsens1: thermal-sensor@c265000 { 5060 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 5061 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 5062 <0 0x0c223000 0 0x1ff>; /* SROT */ 5063 #qcom,sensors = <9>; 5064 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 5065 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 5066 interrupt-names = "uplow", "critical"; 5067 #thermal-sensor-cells = <1>; 5068 }; 5069 5070 aoss_qmp: power-management@c300000 { 5071 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp"; 5072 reg = <0 0x0c300000 0 0x400>; 5073 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 5074 IPCC_MPROC_SIGNAL_GLINK_QMP 5075 IRQ_TYPE_EDGE_RISING>; 5076 mboxes = <&ipcc IPCC_CLIENT_AOP 5077 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5078 5079 #clock-cells = <0>; 5080 }; 5081 5082 sram@c3f0000 { 5083 compatible = "qcom,rpmh-stats"; 5084 reg = <0 0x0c3f0000 0 0x400>; 5085 }; 5086 5087 spmi_bus: spmi@c440000 { 5088 compatible = "qcom,spmi-pmic-arb"; 5089 reg = <0x0 0x0c440000 0x0 0x0001100>, 5090 <0x0 0x0c600000 0x0 0x2000000>, 5091 <0x0 0x0e600000 0x0 0x0100000>, 5092 <0x0 0x0e700000 0x0 0x00a0000>, 5093 <0x0 0x0c40a000 0x0 0x0026000>; 5094 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 5095 interrupt-names = "periph_irq"; 5096 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5097 qcom,ee = <0>; 5098 qcom,channel = <0>; 5099 #address-cells = <2>; 5100 #size-cells = <0>; 5101 interrupt-controller; 5102 #interrupt-cells = <4>; 5103 }; 5104 5105 tlmm: pinctrl@f100000 { 5106 compatible = "qcom,sm8250-pinctrl"; 5107 reg = <0 0x0f100000 0 0x300000>, 5108 <0 0x0f500000 0 0x300000>, 5109 <0 0x0f900000 0 0x300000>; 5110 reg-names = "west", "south", "north"; 5111 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 5112 gpio-controller; 5113 #gpio-cells = <2>; 5114 interrupt-controller; 5115 #interrupt-cells = <2>; 5116 gpio-ranges = <&tlmm 0 0 181>; 5117 wakeup-parent = <&pdc>; 5118 5119 cam2_default: cam2-default-state { 5120 rst-pins { 5121 pins = "gpio78"; 5122 function = "gpio"; 5123 drive-strength = <2>; 5124 bias-disable; 5125 }; 5126 5127 mclk-pins { 5128 pins = "gpio96"; 5129 function = "cam_mclk"; 5130 drive-strength = <16>; 5131 bias-disable; 5132 }; 5133 }; 5134 5135 cam2_suspend: cam2-suspend-state { 5136 rst-pins { 5137 pins = "gpio78"; 5138 function = "gpio"; 5139 drive-strength = <2>; 5140 bias-pull-down; 5141 output-low; 5142 }; 5143 5144 mclk-pins { 5145 pins = "gpio96"; 5146 function = "cam_mclk"; 5147 drive-strength = <2>; 5148 bias-disable; 5149 }; 5150 }; 5151 5152 cci0_default: cci0-default-state { 5153 cci0_i2c0_default: cci0-i2c0-default-pins { 5154 /* SDA, SCL */ 5155 pins = "gpio101", "gpio102"; 5156 function = "cci_i2c"; 5157 5158 bias-pull-up; 5159 drive-strength = <2>; /* 2 mA */ 5160 }; 5161 5162 cci0_i2c1_default: cci0-i2c1-default-pins { 5163 /* SDA, SCL */ 5164 pins = "gpio103", "gpio104"; 5165 function = "cci_i2c"; 5166 5167 bias-pull-up; 5168 drive-strength = <2>; /* 2 mA */ 5169 }; 5170 }; 5171 5172 cci0_sleep: cci0-sleep-state { 5173 cci0_i2c0_sleep: cci0-i2c0-sleep-pins { 5174 /* SDA, SCL */ 5175 pins = "gpio101", "gpio102"; 5176 function = "cci_i2c"; 5177 5178 drive-strength = <2>; /* 2 mA */ 5179 bias-pull-down; 5180 }; 5181 5182 cci0_i2c1_sleep: cci0-i2c1-sleep-pins { 5183 /* SDA, SCL */ 5184 pins = "gpio103", "gpio104"; 5185 function = "cci_i2c"; 5186 5187 drive-strength = <2>; /* 2 mA */ 5188 bias-pull-down; 5189 }; 5190 }; 5191 5192 cci1_default: cci1-default-state { 5193 cci1_i2c0_default: cci1-i2c0-default-pins { 5194 /* SDA, SCL */ 5195 pins = "gpio105","gpio106"; 5196 function = "cci_i2c"; 5197 5198 bias-pull-up; 5199 drive-strength = <2>; /* 2 mA */ 5200 }; 5201 5202 cci1_i2c1_default: cci1-i2c1-default-pins { 5203 /* SDA, SCL */ 5204 pins = "gpio107","gpio108"; 5205 function = "cci_i2c"; 5206 5207 bias-pull-up; 5208 drive-strength = <2>; /* 2 mA */ 5209 }; 5210 }; 5211 5212 cci1_sleep: cci1-sleep-state { 5213 cci1_i2c0_sleep: cci1-i2c0-sleep-pins { 5214 /* SDA, SCL */ 5215 pins = "gpio105","gpio106"; 5216 function = "cci_i2c"; 5217 5218 bias-pull-down; 5219 drive-strength = <2>; /* 2 mA */ 5220 }; 5221 5222 cci1_i2c1_sleep: cci1-i2c1-sleep-pins { 5223 /* SDA, SCL */ 5224 pins = "gpio107","gpio108"; 5225 function = "cci_i2c"; 5226 5227 bias-pull-down; 5228 drive-strength = <2>; /* 2 mA */ 5229 }; 5230 }; 5231 5232 pri_mi2s_active: pri-mi2s-active-state { 5233 sclk-pins { 5234 pins = "gpio138"; 5235 function = "mi2s0_sck"; 5236 drive-strength = <8>; 5237 bias-disable; 5238 }; 5239 5240 ws-pins { 5241 pins = "gpio141"; 5242 function = "mi2s0_ws"; 5243 drive-strength = <8>; 5244 output-high; 5245 }; 5246 5247 data0-pins { 5248 pins = "gpio139"; 5249 function = "mi2s0_data0"; 5250 drive-strength = <8>; 5251 bias-disable; 5252 output-high; 5253 }; 5254 5255 data1-pins { 5256 pins = "gpio140"; 5257 function = "mi2s0_data1"; 5258 drive-strength = <8>; 5259 output-high; 5260 }; 5261 }; 5262 5263 qup_i2c0_default: qup-i2c0-default-state { 5264 pins = "gpio28", "gpio29"; 5265 function = "qup0"; 5266 drive-strength = <2>; 5267 bias-disable; 5268 }; 5269 5270 qup_i2c1_default: qup-i2c1-default-state { 5271 pins = "gpio4", "gpio5"; 5272 function = "qup1"; 5273 drive-strength = <2>; 5274 bias-disable; 5275 }; 5276 5277 qup_i2c2_default: qup-i2c2-default-state { 5278 pins = "gpio115", "gpio116"; 5279 function = "qup2"; 5280 drive-strength = <2>; 5281 bias-disable; 5282 }; 5283 5284 qup_i2c3_default: qup-i2c3-default-state { 5285 pins = "gpio119", "gpio120"; 5286 function = "qup3"; 5287 drive-strength = <2>; 5288 bias-disable; 5289 }; 5290 5291 qup_i2c4_default: qup-i2c4-default-state { 5292 pins = "gpio8", "gpio9"; 5293 function = "qup4"; 5294 drive-strength = <2>; 5295 bias-disable; 5296 }; 5297 5298 qup_i2c5_default: qup-i2c5-default-state { 5299 pins = "gpio12", "gpio13"; 5300 function = "qup5"; 5301 drive-strength = <2>; 5302 bias-disable; 5303 }; 5304 5305 qup_i2c6_default: qup-i2c6-default-state { 5306 pins = "gpio16", "gpio17"; 5307 function = "qup6"; 5308 drive-strength = <2>; 5309 bias-disable; 5310 }; 5311 5312 qup_i2c7_default: qup-i2c7-default-state { 5313 pins = "gpio20", "gpio21"; 5314 function = "qup7"; 5315 drive-strength = <2>; 5316 bias-disable; 5317 }; 5318 5319 qup_i2c8_default: qup-i2c8-default-state { 5320 pins = "gpio24", "gpio25"; 5321 function = "qup8"; 5322 drive-strength = <2>; 5323 bias-disable; 5324 }; 5325 5326 qup_i2c9_default: qup-i2c9-default-state { 5327 pins = "gpio125", "gpio126"; 5328 function = "qup9"; 5329 drive-strength = <2>; 5330 bias-disable; 5331 }; 5332 5333 qup_i2c10_default: qup-i2c10-default-state { 5334 pins = "gpio129", "gpio130"; 5335 function = "qup10"; 5336 drive-strength = <2>; 5337 bias-disable; 5338 }; 5339 5340 qup_i2c11_default: qup-i2c11-default-state { 5341 pins = "gpio60", "gpio61"; 5342 function = "qup11"; 5343 drive-strength = <2>; 5344 bias-disable; 5345 }; 5346 5347 qup_i2c12_default: qup-i2c12-default-state { 5348 pins = "gpio32", "gpio33"; 5349 function = "qup12"; 5350 drive-strength = <2>; 5351 bias-disable; 5352 }; 5353 5354 qup_i2c13_default: qup-i2c13-default-state { 5355 pins = "gpio36", "gpio37"; 5356 function = "qup13"; 5357 drive-strength = <2>; 5358 bias-disable; 5359 }; 5360 5361 qup_i2c14_default: qup-i2c14-default-state { 5362 pins = "gpio40", "gpio41"; 5363 function = "qup14"; 5364 drive-strength = <2>; 5365 bias-disable; 5366 }; 5367 5368 qup_i2c15_default: qup-i2c15-default-state { 5369 pins = "gpio44", "gpio45"; 5370 function = "qup15"; 5371 drive-strength = <2>; 5372 bias-disable; 5373 }; 5374 5375 qup_i2c16_default: qup-i2c16-default-state { 5376 pins = "gpio48", "gpio49"; 5377 function = "qup16"; 5378 drive-strength = <2>; 5379 bias-disable; 5380 }; 5381 5382 qup_i2c17_default: qup-i2c17-default-state { 5383 pins = "gpio52", "gpio53"; 5384 function = "qup17"; 5385 drive-strength = <2>; 5386 bias-disable; 5387 }; 5388 5389 qup_i2c18_default: qup-i2c18-default-state { 5390 pins = "gpio56", "gpio57"; 5391 function = "qup18"; 5392 drive-strength = <2>; 5393 bias-disable; 5394 }; 5395 5396 qup_i2c19_default: qup-i2c19-default-state { 5397 pins = "gpio0", "gpio1"; 5398 function = "qup19"; 5399 drive-strength = <2>; 5400 bias-disable; 5401 }; 5402 5403 qup_spi0_cs: qup-spi0-cs-state { 5404 pins = "gpio31"; 5405 function = "qup0"; 5406 }; 5407 5408 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 5409 pins = "gpio31"; 5410 function = "gpio"; 5411 }; 5412 5413 qup_spi0_data_clk: qup-spi0-data-clk-state { 5414 pins = "gpio28", "gpio29", 5415 "gpio30"; 5416 function = "qup0"; 5417 }; 5418 5419 qup_spi1_cs: qup-spi1-cs-state { 5420 pins = "gpio7"; 5421 function = "qup1"; 5422 }; 5423 5424 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 5425 pins = "gpio7"; 5426 function = "gpio"; 5427 }; 5428 5429 qup_spi1_data_clk: qup-spi1-data-clk-state { 5430 pins = "gpio4", "gpio5", 5431 "gpio6"; 5432 function = "qup1"; 5433 }; 5434 5435 qup_spi2_cs: qup-spi2-cs-state { 5436 pins = "gpio118"; 5437 function = "qup2"; 5438 }; 5439 5440 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 5441 pins = "gpio118"; 5442 function = "gpio"; 5443 }; 5444 5445 qup_spi2_data_clk: qup-spi2-data-clk-state { 5446 pins = "gpio115", "gpio116", 5447 "gpio117"; 5448 function = "qup2"; 5449 }; 5450 5451 qup_spi3_cs: qup-spi3-cs-state { 5452 pins = "gpio122"; 5453 function = "qup3"; 5454 }; 5455 5456 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 5457 pins = "gpio122"; 5458 function = "gpio"; 5459 }; 5460 5461 qup_spi3_data_clk: qup-spi3-data-clk-state { 5462 pins = "gpio119", "gpio120", 5463 "gpio121"; 5464 function = "qup3"; 5465 }; 5466 5467 qup_spi4_cs: qup-spi4-cs-state { 5468 pins = "gpio11"; 5469 function = "qup4"; 5470 }; 5471 5472 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 5473 pins = "gpio11"; 5474 function = "gpio"; 5475 }; 5476 5477 qup_spi4_data_clk: qup-spi4-data-clk-state { 5478 pins = "gpio8", "gpio9", 5479 "gpio10"; 5480 function = "qup4"; 5481 }; 5482 5483 qup_spi5_cs: qup-spi5-cs-state { 5484 pins = "gpio15"; 5485 function = "qup5"; 5486 }; 5487 5488 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 5489 pins = "gpio15"; 5490 function = "gpio"; 5491 }; 5492 5493 qup_spi5_data_clk: qup-spi5-data-clk-state { 5494 pins = "gpio12", "gpio13", 5495 "gpio14"; 5496 function = "qup5"; 5497 }; 5498 5499 qup_spi6_cs: qup-spi6-cs-state { 5500 pins = "gpio19"; 5501 function = "qup6"; 5502 }; 5503 5504 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 5505 pins = "gpio19"; 5506 function = "gpio"; 5507 }; 5508 5509 qup_spi6_data_clk: qup-spi6-data-clk-state { 5510 pins = "gpio16", "gpio17", 5511 "gpio18"; 5512 function = "qup6"; 5513 }; 5514 5515 qup_spi7_cs: qup-spi7-cs-state { 5516 pins = "gpio23"; 5517 function = "qup7"; 5518 }; 5519 5520 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 5521 pins = "gpio23"; 5522 function = "gpio"; 5523 }; 5524 5525 qup_spi7_data_clk: qup-spi7-data-clk-state { 5526 pins = "gpio20", "gpio21", 5527 "gpio22"; 5528 function = "qup7"; 5529 }; 5530 5531 qup_spi8_cs: qup-spi8-cs-state { 5532 pins = "gpio27"; 5533 function = "qup8"; 5534 }; 5535 5536 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 5537 pins = "gpio27"; 5538 function = "gpio"; 5539 }; 5540 5541 qup_spi8_data_clk: qup-spi8-data-clk-state { 5542 pins = "gpio24", "gpio25", 5543 "gpio26"; 5544 function = "qup8"; 5545 }; 5546 5547 qup_spi9_cs: qup-spi9-cs-state { 5548 pins = "gpio128"; 5549 function = "qup9"; 5550 }; 5551 5552 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 5553 pins = "gpio128"; 5554 function = "gpio"; 5555 }; 5556 5557 qup_spi9_data_clk: qup-spi9-data-clk-state { 5558 pins = "gpio125", "gpio126", 5559 "gpio127"; 5560 function = "qup9"; 5561 }; 5562 5563 qup_spi10_cs: qup-spi10-cs-state { 5564 pins = "gpio132"; 5565 function = "qup10"; 5566 }; 5567 5568 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 5569 pins = "gpio132"; 5570 function = "gpio"; 5571 }; 5572 5573 qup_spi10_data_clk: qup-spi10-data-clk-state { 5574 pins = "gpio129", "gpio130", 5575 "gpio131"; 5576 function = "qup10"; 5577 }; 5578 5579 qup_spi11_cs: qup-spi11-cs-state { 5580 pins = "gpio63"; 5581 function = "qup11"; 5582 }; 5583 5584 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 5585 pins = "gpio63"; 5586 function = "gpio"; 5587 }; 5588 5589 qup_spi11_data_clk: qup-spi11-data-clk-state { 5590 pins = "gpio60", "gpio61", 5591 "gpio62"; 5592 function = "qup11"; 5593 }; 5594 5595 qup_spi12_cs: qup-spi12-cs-state { 5596 pins = "gpio35"; 5597 function = "qup12"; 5598 }; 5599 5600 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 5601 pins = "gpio35"; 5602 function = "gpio"; 5603 }; 5604 5605 qup_spi12_data_clk: qup-spi12-data-clk-state { 5606 pins = "gpio32", "gpio33", 5607 "gpio34"; 5608 function = "qup12"; 5609 }; 5610 5611 qup_spi13_cs: qup-spi13-cs-state { 5612 pins = "gpio39"; 5613 function = "qup13"; 5614 }; 5615 5616 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 5617 pins = "gpio39"; 5618 function = "gpio"; 5619 }; 5620 5621 qup_spi13_data_clk: qup-spi13-data-clk-state { 5622 pins = "gpio36", "gpio37", 5623 "gpio38"; 5624 function = "qup13"; 5625 }; 5626 5627 qup_spi14_cs: qup-spi14-cs-state { 5628 pins = "gpio43"; 5629 function = "qup14"; 5630 }; 5631 5632 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 5633 pins = "gpio43"; 5634 function = "gpio"; 5635 }; 5636 5637 qup_spi14_data_clk: qup-spi14-data-clk-state { 5638 pins = "gpio40", "gpio41", 5639 "gpio42"; 5640 function = "qup14"; 5641 }; 5642 5643 qup_spi15_cs: qup-spi15-cs-state { 5644 pins = "gpio47"; 5645 function = "qup15"; 5646 }; 5647 5648 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 5649 pins = "gpio47"; 5650 function = "gpio"; 5651 }; 5652 5653 qup_spi15_data_clk: qup-spi15-data-clk-state { 5654 pins = "gpio44", "gpio45", 5655 "gpio46"; 5656 function = "qup15"; 5657 }; 5658 5659 qup_spi16_cs: qup-spi16-cs-state { 5660 pins = "gpio51"; 5661 function = "qup16"; 5662 }; 5663 5664 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state { 5665 pins = "gpio51"; 5666 function = "gpio"; 5667 }; 5668 5669 qup_spi16_data_clk: qup-spi16-data-clk-state { 5670 pins = "gpio48", "gpio49", 5671 "gpio50"; 5672 function = "qup16"; 5673 }; 5674 5675 qup_spi17_cs: qup-spi17-cs-state { 5676 pins = "gpio55"; 5677 function = "qup17"; 5678 }; 5679 5680 qup_spi17_cs_gpio: qup-spi17-cs-gpio-state { 5681 pins = "gpio55"; 5682 function = "gpio"; 5683 }; 5684 5685 qup_spi17_data_clk: qup-spi17-data-clk-state { 5686 pins = "gpio52", "gpio53", 5687 "gpio54"; 5688 function = "qup17"; 5689 }; 5690 5691 qup_spi18_cs: qup-spi18-cs-state { 5692 pins = "gpio59"; 5693 function = "qup18"; 5694 }; 5695 5696 qup_spi18_cs_gpio: qup-spi18-cs-gpio-state { 5697 pins = "gpio59"; 5698 function = "gpio"; 5699 }; 5700 5701 qup_spi18_data_clk: qup-spi18-data-clk-state { 5702 pins = "gpio56", "gpio57", 5703 "gpio58"; 5704 function = "qup18"; 5705 }; 5706 5707 qup_spi19_cs: qup-spi19-cs-state { 5708 pins = "gpio3"; 5709 function = "qup19"; 5710 }; 5711 5712 qup_spi19_cs_gpio: qup-spi19-cs-gpio-state { 5713 pins = "gpio3"; 5714 function = "gpio"; 5715 }; 5716 5717 qup_spi19_data_clk: qup-spi19-data-clk-state { 5718 pins = "gpio0", "gpio1", 5719 "gpio2"; 5720 function = "qup19"; 5721 }; 5722 5723 qup_uart2_default: qup-uart2-default-state { 5724 pins = "gpio117", "gpio118"; 5725 function = "qup2"; 5726 }; 5727 5728 qup_uart6_default: qup-uart6-default-state { 5729 pins = "gpio16", "gpio17", "gpio18", "gpio19"; 5730 function = "qup6"; 5731 }; 5732 5733 qup_uart12_default: qup-uart12-default-state { 5734 pins = "gpio34", "gpio35"; 5735 function = "qup12"; 5736 }; 5737 5738 qup_uart17_default: qup-uart17-default-state { 5739 pins = "gpio52", "gpio53", "gpio54", "gpio55"; 5740 function = "qup17"; 5741 }; 5742 5743 qup_uart18_default: qup-uart18-default-state { 5744 pins = "gpio58", "gpio59"; 5745 function = "qup18"; 5746 }; 5747 5748 tert_mi2s_active: tert-mi2s-active-state { 5749 sck-pins { 5750 pins = "gpio133"; 5751 function = "mi2s2_sck"; 5752 drive-strength = <8>; 5753 bias-disable; 5754 }; 5755 5756 data0-pins { 5757 pins = "gpio134"; 5758 function = "mi2s2_data0"; 5759 drive-strength = <8>; 5760 bias-disable; 5761 output-high; 5762 }; 5763 5764 ws-pins { 5765 pins = "gpio135"; 5766 function = "mi2s2_ws"; 5767 drive-strength = <8>; 5768 output-high; 5769 }; 5770 }; 5771 5772 sdc2_sleep_state: sdc2-sleep-state { 5773 clk-pins { 5774 pins = "sdc2_clk"; 5775 drive-strength = <2>; 5776 bias-disable; 5777 }; 5778 5779 cmd-pins { 5780 pins = "sdc2_cmd"; 5781 drive-strength = <2>; 5782 bias-pull-up; 5783 }; 5784 5785 data-pins { 5786 pins = "sdc2_data"; 5787 drive-strength = <2>; 5788 bias-pull-up; 5789 }; 5790 }; 5791 5792 pcie0_default_state: pcie0-default-state { 5793 perst-pins { 5794 pins = "gpio79"; 5795 function = "gpio"; 5796 drive-strength = <2>; 5797 bias-pull-down; 5798 }; 5799 5800 clkreq-pins { 5801 pins = "gpio80"; 5802 function = "pci_e0"; 5803 drive-strength = <2>; 5804 bias-pull-up; 5805 }; 5806 5807 wake-pins { 5808 pins = "gpio81"; 5809 function = "gpio"; 5810 drive-strength = <2>; 5811 bias-pull-up; 5812 }; 5813 }; 5814 5815 pcie1_default_state: pcie1-default-state { 5816 perst-pins { 5817 pins = "gpio82"; 5818 function = "gpio"; 5819 drive-strength = <2>; 5820 bias-pull-down; 5821 }; 5822 5823 clkreq-pins { 5824 pins = "gpio83"; 5825 function = "pci_e1"; 5826 drive-strength = <2>; 5827 bias-pull-up; 5828 }; 5829 5830 wake-pins { 5831 pins = "gpio84"; 5832 function = "gpio"; 5833 drive-strength = <2>; 5834 bias-pull-up; 5835 }; 5836 }; 5837 5838 pcie2_default_state: pcie2-default-state { 5839 perst-pins { 5840 pins = "gpio85"; 5841 function = "gpio"; 5842 drive-strength = <2>; 5843 bias-pull-down; 5844 }; 5845 5846 clkreq-pins { 5847 pins = "gpio86"; 5848 function = "pci_e2"; 5849 drive-strength = <2>; 5850 bias-pull-up; 5851 }; 5852 5853 wake-pins { 5854 pins = "gpio87"; 5855 function = "gpio"; 5856 drive-strength = <2>; 5857 bias-pull-up; 5858 }; 5859 }; 5860 }; 5861 5862 apps_smmu: iommu@15000000 { 5863 compatible = "qcom,sm8250-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 5864 reg = <0 0x15000000 0 0x100000>; 5865 #iommu-cells = <2>; 5866 #global-interrupts = <2>; 5867 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 5868 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5869 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5870 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5871 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5872 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5873 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5874 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5875 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5876 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5877 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5878 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5879 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5880 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5881 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5882 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5883 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5884 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5885 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5886 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5887 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5888 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5889 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5890 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5891 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5892 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5893 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5894 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5895 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5896 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5897 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5898 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5899 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5900 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5901 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5902 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5903 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5904 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5905 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5906 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5907 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5908 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5909 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5910 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5911 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5912 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5913 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5914 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5915 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5916 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5917 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5918 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5919 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5920 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5921 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5922 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5923 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5924 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5925 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5926 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5927 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5928 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5929 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5930 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5931 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5932 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5933 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5934 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5935 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5936 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5937 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5938 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5939 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5940 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5941 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5942 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5943 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5944 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5945 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5946 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5947 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5948 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5949 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5950 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5951 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5952 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5953 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5954 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5955 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5956 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5957 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5958 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5959 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5960 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5961 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5962 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5963 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 5964 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 5965 dma-coherent; 5966 }; 5967 5968 adsp: remoteproc@17300000 { 5969 compatible = "qcom,sm8250-adsp-pas"; 5970 reg = <0 0x17300000 0 0x100>; 5971 5972 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 5973 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 5974 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 5975 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 5976 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 5977 interrupt-names = "wdog", "fatal", "ready", 5978 "handover", "stop-ack"; 5979 5980 clocks = <&rpmhcc RPMH_CXO_CLK>; 5981 clock-names = "xo"; 5982 5983 power-domains = <&rpmhpd RPMHPD_LCX>, 5984 <&rpmhpd RPMHPD_LMX>; 5985 power-domain-names = "lcx", "lmx"; 5986 5987 memory-region = <&adsp_mem>; 5988 5989 qcom,qmp = <&aoss_qmp>; 5990 5991 qcom,smem-states = <&smp2p_adsp_out 0>; 5992 qcom,smem-state-names = "stop"; 5993 5994 status = "disabled"; 5995 5996 glink-edge { 5997 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 5998 IPCC_MPROC_SIGNAL_GLINK_QMP 5999 IRQ_TYPE_EDGE_RISING>; 6000 mboxes = <&ipcc IPCC_CLIENT_LPASS 6001 IPCC_MPROC_SIGNAL_GLINK_QMP>; 6002 6003 label = "lpass"; 6004 qcom,remote-pid = <2>; 6005 6006 apr { 6007 compatible = "qcom,apr-v2"; 6008 qcom,glink-channels = "apr_audio_svc"; 6009 qcom,domain = <APR_DOMAIN_ADSP>; 6010 #address-cells = <1>; 6011 #size-cells = <0>; 6012 6013 service@3 { 6014 reg = <APR_SVC_ADSP_CORE>; 6015 compatible = "qcom,q6core"; 6016 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 6017 }; 6018 6019 q6afe: service@4 { 6020 compatible = "qcom,q6afe"; 6021 reg = <APR_SVC_AFE>; 6022 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 6023 q6afedai: dais { 6024 compatible = "qcom,q6afe-dais"; 6025 #address-cells = <1>; 6026 #size-cells = <0>; 6027 #sound-dai-cells = <1>; 6028 }; 6029 6030 q6afecc: clock-controller { 6031 compatible = "qcom,q6afe-clocks"; 6032 #clock-cells = <2>; 6033 }; 6034 }; 6035 6036 q6asm: service@7 { 6037 compatible = "qcom,q6asm"; 6038 reg = <APR_SVC_ASM>; 6039 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 6040 q6asmdai: dais { 6041 compatible = "qcom,q6asm-dais"; 6042 #address-cells = <1>; 6043 #size-cells = <0>; 6044 #sound-dai-cells = <1>; 6045 iommus = <&apps_smmu 0x1801 0x0>; 6046 }; 6047 }; 6048 6049 q6adm: service@8 { 6050 compatible = "qcom,q6adm"; 6051 reg = <APR_SVC_ADM>; 6052 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 6053 q6routing: routing { 6054 compatible = "qcom,q6adm-routing"; 6055 #sound-dai-cells = <0>; 6056 }; 6057 }; 6058 }; 6059 6060 fastrpc { 6061 compatible = "qcom,fastrpc"; 6062 qcom,glink-channels = "fastrpcglink-apps-dsp"; 6063 label = "adsp"; 6064 qcom,non-secure-domain; 6065 #address-cells = <1>; 6066 #size-cells = <0>; 6067 6068 compute-cb@3 { 6069 compatible = "qcom,fastrpc-compute-cb"; 6070 reg = <3>; 6071 iommus = <&apps_smmu 0x1803 0x0>; 6072 }; 6073 6074 compute-cb@4 { 6075 compatible = "qcom,fastrpc-compute-cb"; 6076 reg = <4>; 6077 iommus = <&apps_smmu 0x1804 0x0>; 6078 }; 6079 6080 compute-cb@5 { 6081 compatible = "qcom,fastrpc-compute-cb"; 6082 reg = <5>; 6083 iommus = <&apps_smmu 0x1805 0x0>; 6084 }; 6085 }; 6086 }; 6087 }; 6088 6089 intc: interrupt-controller@17a00000 { 6090 compatible = "arm,gic-v3"; 6091 #address-cells = <0>; 6092 #interrupt-cells = <3>; 6093 interrupt-controller; 6094 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 6095 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 6096 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 6097 }; 6098 6099 watchdog@17c10000 { 6100 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; 6101 reg = <0 0x17c10000 0 0x1000>; 6102 clocks = <&sleep_clk>; 6103 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 6104 }; 6105 6106 timer@17c20000 { 6107 #address-cells = <1>; 6108 #size-cells = <1>; 6109 ranges = <0 0 0 0x20000000>; 6110 compatible = "arm,armv7-timer-mem"; 6111 reg = <0x0 0x17c20000 0x0 0x1000>; 6112 clock-frequency = <19200000>; 6113 6114 frame@17c21000 { 6115 frame-number = <0>; 6116 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 6117 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 6118 reg = <0x17c21000 0x1000>, 6119 <0x17c22000 0x1000>; 6120 }; 6121 6122 frame@17c23000 { 6123 frame-number = <1>; 6124 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 6125 reg = <0x17c23000 0x1000>; 6126 status = "disabled"; 6127 }; 6128 6129 frame@17c25000 { 6130 frame-number = <2>; 6131 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 6132 reg = <0x17c25000 0x1000>; 6133 status = "disabled"; 6134 }; 6135 6136 frame@17c27000 { 6137 frame-number = <3>; 6138 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 6139 reg = <0x17c27000 0x1000>; 6140 status = "disabled"; 6141 }; 6142 6143 frame@17c29000 { 6144 frame-number = <4>; 6145 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 6146 reg = <0x17c29000 0x1000>; 6147 status = "disabled"; 6148 }; 6149 6150 frame@17c2b000 { 6151 frame-number = <5>; 6152 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 6153 reg = <0x17c2b000 0x1000>; 6154 status = "disabled"; 6155 }; 6156 6157 frame@17c2d000 { 6158 frame-number = <6>; 6159 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 6160 reg = <0x17c2d000 0x1000>; 6161 status = "disabled"; 6162 }; 6163 }; 6164 6165 apps_rsc: rsc@18200000 { 6166 label = "apps_rsc"; 6167 compatible = "qcom,rpmh-rsc"; 6168 reg = <0x0 0x18200000 0x0 0x10000>, 6169 <0x0 0x18210000 0x0 0x10000>, 6170 <0x0 0x18220000 0x0 0x10000>; 6171 reg-names = "drv-0", "drv-1", "drv-2"; 6172 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 6173 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 6174 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 6175 qcom,tcs-offset = <0xd00>; 6176 qcom,drv-id = <2>; 6177 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 6178 <WAKE_TCS 3>, <CONTROL_TCS 1>; 6179 power-domains = <&cluster_pd>; 6180 6181 rpmhcc: clock-controller { 6182 compatible = "qcom,sm8250-rpmh-clk"; 6183 #clock-cells = <1>; 6184 clock-names = "xo"; 6185 clocks = <&xo_board>; 6186 }; 6187 6188 rpmhpd: power-controller { 6189 compatible = "qcom,sm8250-rpmhpd"; 6190 #power-domain-cells = <1>; 6191 operating-points-v2 = <&rpmhpd_opp_table>; 6192 6193 rpmhpd_opp_table: opp-table { 6194 compatible = "operating-points-v2"; 6195 6196 rpmhpd_opp_ret: opp1 { 6197 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 6198 }; 6199 6200 rpmhpd_opp_min_svs: opp2 { 6201 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 6202 }; 6203 6204 rpmhpd_opp_low_svs: opp3 { 6205 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 6206 }; 6207 6208 rpmhpd_opp_svs: opp4 { 6209 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 6210 }; 6211 6212 rpmhpd_opp_svs_l1: opp5 { 6213 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 6214 }; 6215 6216 rpmhpd_opp_nom: opp6 { 6217 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 6218 }; 6219 6220 rpmhpd_opp_nom_l1: opp7 { 6221 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 6222 }; 6223 6224 rpmhpd_opp_nom_l2: opp8 { 6225 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 6226 }; 6227 6228 rpmhpd_opp_turbo: opp9 { 6229 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 6230 }; 6231 6232 rpmhpd_opp_turbo_l1: opp10 { 6233 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 6234 }; 6235 }; 6236 }; 6237 6238 apps_bcm_voter: bcm-voter { 6239 compatible = "qcom,bcm-voter"; 6240 }; 6241 }; 6242 6243 epss_l3: interconnect@18590000 { 6244 compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3"; 6245 reg = <0 0x18590000 0 0x1000>; 6246 6247 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 6248 clock-names = "xo", "alternate"; 6249 6250 #interconnect-cells = <1>; 6251 }; 6252 6253 cpufreq_hw: cpufreq@18591000 { 6254 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; 6255 reg = <0 0x18591000 0 0x1000>, 6256 <0 0x18592000 0 0x1000>, 6257 <0 0x18593000 0 0x1000>; 6258 reg-names = "freq-domain0", "freq-domain1", 6259 "freq-domain2"; 6260 6261 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 6262 clock-names = "xo", "alternate"; 6263 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 6264 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 6265 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 6266 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 6267 #freq-domain-cells = <1>; 6268 #clock-cells = <1>; 6269 }; 6270 }; 6271 6272 sound: sound { 6273 }; 6274 6275 timer { 6276 compatible = "arm,armv8-timer"; 6277 interrupts = <GIC_PPI 13 6278 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6279 <GIC_PPI 14 6280 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6281 <GIC_PPI 11 6282 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6283 <GIC_PPI 10 6284 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 6285 }; 6286 6287 thermal-zones { 6288 cpu0-thermal { 6289 polling-delay-passive = <250>; 6290 6291 thermal-sensors = <&tsens0 1>; 6292 6293 trips { 6294 cpu0_alert0: trip-point0 { 6295 temperature = <90000>; 6296 hysteresis = <2000>; 6297 type = "passive"; 6298 }; 6299 6300 cpu0_alert1: trip-point1 { 6301 temperature = <95000>; 6302 hysteresis = <2000>; 6303 type = "passive"; 6304 }; 6305 6306 cpu0_crit: cpu-crit { 6307 temperature = <110000>; 6308 hysteresis = <1000>; 6309 type = "critical"; 6310 }; 6311 }; 6312 6313 cooling-maps { 6314 map0 { 6315 trip = <&cpu0_alert0>; 6316 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6317 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6318 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6319 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6320 }; 6321 map1 { 6322 trip = <&cpu0_alert1>; 6323 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6324 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6325 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6326 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6327 }; 6328 }; 6329 }; 6330 6331 cpu1-thermal { 6332 polling-delay-passive = <250>; 6333 6334 thermal-sensors = <&tsens0 2>; 6335 6336 trips { 6337 cpu1_alert0: trip-point0 { 6338 temperature = <90000>; 6339 hysteresis = <2000>; 6340 type = "passive"; 6341 }; 6342 6343 cpu1_alert1: trip-point1 { 6344 temperature = <95000>; 6345 hysteresis = <2000>; 6346 type = "passive"; 6347 }; 6348 6349 cpu1_crit: cpu-crit { 6350 temperature = <110000>; 6351 hysteresis = <1000>; 6352 type = "critical"; 6353 }; 6354 }; 6355 6356 cooling-maps { 6357 map0 { 6358 trip = <&cpu1_alert0>; 6359 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6360 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6361 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6362 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6363 }; 6364 map1 { 6365 trip = <&cpu1_alert1>; 6366 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6367 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6368 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6369 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6370 }; 6371 }; 6372 }; 6373 6374 cpu2-thermal { 6375 polling-delay-passive = <250>; 6376 6377 thermal-sensors = <&tsens0 3>; 6378 6379 trips { 6380 cpu2_alert0: trip-point0 { 6381 temperature = <90000>; 6382 hysteresis = <2000>; 6383 type = "passive"; 6384 }; 6385 6386 cpu2_alert1: trip-point1 { 6387 temperature = <95000>; 6388 hysteresis = <2000>; 6389 type = "passive"; 6390 }; 6391 6392 cpu2_crit: cpu-crit { 6393 temperature = <110000>; 6394 hysteresis = <1000>; 6395 type = "critical"; 6396 }; 6397 }; 6398 6399 cooling-maps { 6400 map0 { 6401 trip = <&cpu2_alert0>; 6402 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6403 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6404 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6405 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6406 }; 6407 map1 { 6408 trip = <&cpu2_alert1>; 6409 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6410 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6411 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6412 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6413 }; 6414 }; 6415 }; 6416 6417 cpu3-thermal { 6418 polling-delay-passive = <250>; 6419 6420 thermal-sensors = <&tsens0 4>; 6421 6422 trips { 6423 cpu3_alert0: trip-point0 { 6424 temperature = <90000>; 6425 hysteresis = <2000>; 6426 type = "passive"; 6427 }; 6428 6429 cpu3_alert1: trip-point1 { 6430 temperature = <95000>; 6431 hysteresis = <2000>; 6432 type = "passive"; 6433 }; 6434 6435 cpu3_crit: cpu-crit { 6436 temperature = <110000>; 6437 hysteresis = <1000>; 6438 type = "critical"; 6439 }; 6440 }; 6441 6442 cooling-maps { 6443 map0 { 6444 trip = <&cpu3_alert0>; 6445 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6446 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6447 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6448 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6449 }; 6450 map1 { 6451 trip = <&cpu3_alert1>; 6452 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6453 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6454 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6455 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6456 }; 6457 }; 6458 }; 6459 6460 cpu4-top-thermal { 6461 polling-delay-passive = <250>; 6462 6463 thermal-sensors = <&tsens0 7>; 6464 6465 trips { 6466 cpu4_top_alert0: trip-point0 { 6467 temperature = <90000>; 6468 hysteresis = <2000>; 6469 type = "passive"; 6470 }; 6471 6472 cpu4_top_alert1: trip-point1 { 6473 temperature = <95000>; 6474 hysteresis = <2000>; 6475 type = "passive"; 6476 }; 6477 6478 cpu4_top_crit: cpu-crit { 6479 temperature = <110000>; 6480 hysteresis = <1000>; 6481 type = "critical"; 6482 }; 6483 }; 6484 6485 cooling-maps { 6486 map0 { 6487 trip = <&cpu4_top_alert0>; 6488 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6489 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6490 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6491 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6492 }; 6493 map1 { 6494 trip = <&cpu4_top_alert1>; 6495 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6496 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6497 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6498 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6499 }; 6500 }; 6501 }; 6502 6503 cpu5-top-thermal { 6504 polling-delay-passive = <250>; 6505 6506 thermal-sensors = <&tsens0 8>; 6507 6508 trips { 6509 cpu5_top_alert0: trip-point0 { 6510 temperature = <90000>; 6511 hysteresis = <2000>; 6512 type = "passive"; 6513 }; 6514 6515 cpu5_top_alert1: trip-point1 { 6516 temperature = <95000>; 6517 hysteresis = <2000>; 6518 type = "passive"; 6519 }; 6520 6521 cpu5_top_crit: cpu-crit { 6522 temperature = <110000>; 6523 hysteresis = <1000>; 6524 type = "critical"; 6525 }; 6526 }; 6527 6528 cooling-maps { 6529 map0 { 6530 trip = <&cpu5_top_alert0>; 6531 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6532 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6533 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6534 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6535 }; 6536 map1 { 6537 trip = <&cpu5_top_alert1>; 6538 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6539 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6540 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6541 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6542 }; 6543 }; 6544 }; 6545 6546 cpu6-top-thermal { 6547 polling-delay-passive = <250>; 6548 6549 thermal-sensors = <&tsens0 9>; 6550 6551 trips { 6552 cpu6_top_alert0: trip-point0 { 6553 temperature = <90000>; 6554 hysteresis = <2000>; 6555 type = "passive"; 6556 }; 6557 6558 cpu6_top_alert1: trip-point1 { 6559 temperature = <95000>; 6560 hysteresis = <2000>; 6561 type = "passive"; 6562 }; 6563 6564 cpu6_top_crit: cpu-crit { 6565 temperature = <110000>; 6566 hysteresis = <1000>; 6567 type = "critical"; 6568 }; 6569 }; 6570 6571 cooling-maps { 6572 map0 { 6573 trip = <&cpu6_top_alert0>; 6574 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6575 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6576 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6577 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6578 }; 6579 map1 { 6580 trip = <&cpu6_top_alert1>; 6581 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6582 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6583 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6584 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6585 }; 6586 }; 6587 }; 6588 6589 cpu7-top-thermal { 6590 polling-delay-passive = <250>; 6591 6592 thermal-sensors = <&tsens0 10>; 6593 6594 trips { 6595 cpu7_top_alert0: trip-point0 { 6596 temperature = <90000>; 6597 hysteresis = <2000>; 6598 type = "passive"; 6599 }; 6600 6601 cpu7_top_alert1: trip-point1 { 6602 temperature = <95000>; 6603 hysteresis = <2000>; 6604 type = "passive"; 6605 }; 6606 6607 cpu7_top_crit: cpu-crit { 6608 temperature = <110000>; 6609 hysteresis = <1000>; 6610 type = "critical"; 6611 }; 6612 }; 6613 6614 cooling-maps { 6615 map0 { 6616 trip = <&cpu7_top_alert0>; 6617 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6618 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6619 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6620 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6621 }; 6622 map1 { 6623 trip = <&cpu7_top_alert1>; 6624 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6625 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6626 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6627 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6628 }; 6629 }; 6630 }; 6631 6632 cpu4-bottom-thermal { 6633 polling-delay-passive = <250>; 6634 6635 thermal-sensors = <&tsens0 11>; 6636 6637 trips { 6638 cpu4_bottom_alert0: trip-point0 { 6639 temperature = <90000>; 6640 hysteresis = <2000>; 6641 type = "passive"; 6642 }; 6643 6644 cpu4_bottom_alert1: trip-point1 { 6645 temperature = <95000>; 6646 hysteresis = <2000>; 6647 type = "passive"; 6648 }; 6649 6650 cpu4_bottom_crit: cpu-crit { 6651 temperature = <110000>; 6652 hysteresis = <1000>; 6653 type = "critical"; 6654 }; 6655 }; 6656 6657 cooling-maps { 6658 map0 { 6659 trip = <&cpu4_bottom_alert0>; 6660 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6661 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6662 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6663 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6664 }; 6665 map1 { 6666 trip = <&cpu4_bottom_alert1>; 6667 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6668 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6669 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6670 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6671 }; 6672 }; 6673 }; 6674 6675 cpu5-bottom-thermal { 6676 polling-delay-passive = <250>; 6677 6678 thermal-sensors = <&tsens0 12>; 6679 6680 trips { 6681 cpu5_bottom_alert0: trip-point0 { 6682 temperature = <90000>; 6683 hysteresis = <2000>; 6684 type = "passive"; 6685 }; 6686 6687 cpu5_bottom_alert1: trip-point1 { 6688 temperature = <95000>; 6689 hysteresis = <2000>; 6690 type = "passive"; 6691 }; 6692 6693 cpu5_bottom_crit: cpu-crit { 6694 temperature = <110000>; 6695 hysteresis = <1000>; 6696 type = "critical"; 6697 }; 6698 }; 6699 6700 cooling-maps { 6701 map0 { 6702 trip = <&cpu5_bottom_alert0>; 6703 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6704 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6705 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6706 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6707 }; 6708 map1 { 6709 trip = <&cpu5_bottom_alert1>; 6710 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6711 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6712 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6713 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6714 }; 6715 }; 6716 }; 6717 6718 cpu6-bottom-thermal { 6719 polling-delay-passive = <250>; 6720 6721 thermal-sensors = <&tsens0 13>; 6722 6723 trips { 6724 cpu6_bottom_alert0: trip-point0 { 6725 temperature = <90000>; 6726 hysteresis = <2000>; 6727 type = "passive"; 6728 }; 6729 6730 cpu6_bottom_alert1: trip-point1 { 6731 temperature = <95000>; 6732 hysteresis = <2000>; 6733 type = "passive"; 6734 }; 6735 6736 cpu6_bottom_crit: cpu-crit { 6737 temperature = <110000>; 6738 hysteresis = <1000>; 6739 type = "critical"; 6740 }; 6741 }; 6742 6743 cooling-maps { 6744 map0 { 6745 trip = <&cpu6_bottom_alert0>; 6746 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6747 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6748 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6749 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6750 }; 6751 map1 { 6752 trip = <&cpu6_bottom_alert1>; 6753 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6754 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6755 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6756 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6757 }; 6758 }; 6759 }; 6760 6761 cpu7-bottom-thermal { 6762 polling-delay-passive = <250>; 6763 6764 thermal-sensors = <&tsens0 14>; 6765 6766 trips { 6767 cpu7_bottom_alert0: trip-point0 { 6768 temperature = <90000>; 6769 hysteresis = <2000>; 6770 type = "passive"; 6771 }; 6772 6773 cpu7_bottom_alert1: trip-point1 { 6774 temperature = <95000>; 6775 hysteresis = <2000>; 6776 type = "passive"; 6777 }; 6778 6779 cpu7_bottom_crit: cpu-crit { 6780 temperature = <110000>; 6781 hysteresis = <1000>; 6782 type = "critical"; 6783 }; 6784 }; 6785 6786 cooling-maps { 6787 map0 { 6788 trip = <&cpu7_bottom_alert0>; 6789 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6790 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6791 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6792 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6793 }; 6794 map1 { 6795 trip = <&cpu7_bottom_alert1>; 6796 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6797 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6798 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6799 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6800 }; 6801 }; 6802 }; 6803 6804 aoss0-thermal { 6805 polling-delay-passive = <250>; 6806 6807 thermal-sensors = <&tsens0 0>; 6808 6809 trips { 6810 aoss0_alert0: trip-point0 { 6811 temperature = <90000>; 6812 hysteresis = <2000>; 6813 type = "hot"; 6814 }; 6815 }; 6816 }; 6817 6818 cluster0-thermal { 6819 polling-delay-passive = <250>; 6820 6821 thermal-sensors = <&tsens0 5>; 6822 6823 trips { 6824 cluster0_alert0: trip-point0 { 6825 temperature = <90000>; 6826 hysteresis = <2000>; 6827 type = "hot"; 6828 }; 6829 cluster0_crit: cluster0-crit { 6830 temperature = <110000>; 6831 hysteresis = <2000>; 6832 type = "critical"; 6833 }; 6834 }; 6835 }; 6836 6837 cluster1-thermal { 6838 polling-delay-passive = <250>; 6839 6840 thermal-sensors = <&tsens0 6>; 6841 6842 trips { 6843 cluster1_alert0: trip-point0 { 6844 temperature = <90000>; 6845 hysteresis = <2000>; 6846 type = "hot"; 6847 }; 6848 cluster1_crit: cluster1-crit { 6849 temperature = <110000>; 6850 hysteresis = <2000>; 6851 type = "critical"; 6852 }; 6853 }; 6854 }; 6855 6856 gpu-top-thermal { 6857 polling-delay-passive = <250>; 6858 6859 thermal-sensors = <&tsens0 15>; 6860 6861 cooling-maps { 6862 map0 { 6863 trip = <&gpu_top_alert0>; 6864 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6865 }; 6866 }; 6867 6868 trips { 6869 gpu_top_alert0: trip-point0 { 6870 temperature = <85000>; 6871 hysteresis = <1000>; 6872 type = "passive"; 6873 }; 6874 6875 trip-point1 { 6876 temperature = <90000>; 6877 hysteresis = <1000>; 6878 type = "hot"; 6879 }; 6880 6881 trip-point2 { 6882 temperature = <110000>; 6883 hysteresis = <1000>; 6884 type = "critical"; 6885 }; 6886 }; 6887 }; 6888 6889 aoss1-thermal { 6890 polling-delay-passive = <250>; 6891 6892 thermal-sensors = <&tsens1 0>; 6893 6894 trips { 6895 aoss1_alert0: trip-point0 { 6896 temperature = <90000>; 6897 hysteresis = <2000>; 6898 type = "hot"; 6899 }; 6900 }; 6901 }; 6902 6903 wlan-thermal { 6904 polling-delay-passive = <250>; 6905 6906 thermal-sensors = <&tsens1 1>; 6907 6908 trips { 6909 wlan_alert0: trip-point0 { 6910 temperature = <90000>; 6911 hysteresis = <2000>; 6912 type = "hot"; 6913 }; 6914 }; 6915 }; 6916 6917 video-thermal { 6918 polling-delay-passive = <250>; 6919 6920 thermal-sensors = <&tsens1 2>; 6921 6922 trips { 6923 video_alert0: trip-point0 { 6924 temperature = <90000>; 6925 hysteresis = <2000>; 6926 type = "hot"; 6927 }; 6928 }; 6929 }; 6930 6931 mem-thermal { 6932 polling-delay-passive = <250>; 6933 6934 thermal-sensors = <&tsens1 3>; 6935 6936 trips { 6937 mem_alert0: trip-point0 { 6938 temperature = <90000>; 6939 hysteresis = <2000>; 6940 type = "hot"; 6941 }; 6942 }; 6943 }; 6944 6945 q6-hvx-thermal { 6946 polling-delay-passive = <250>; 6947 6948 thermal-sensors = <&tsens1 4>; 6949 6950 trips { 6951 q6_hvx_alert0: trip-point0 { 6952 temperature = <90000>; 6953 hysteresis = <2000>; 6954 type = "hot"; 6955 }; 6956 }; 6957 }; 6958 6959 camera-thermal { 6960 polling-delay-passive = <250>; 6961 6962 thermal-sensors = <&tsens1 5>; 6963 6964 trips { 6965 camera_alert0: trip-point0 { 6966 temperature = <90000>; 6967 hysteresis = <2000>; 6968 type = "hot"; 6969 }; 6970 }; 6971 }; 6972 6973 compute-thermal { 6974 polling-delay-passive = <250>; 6975 6976 thermal-sensors = <&tsens1 6>; 6977 6978 trips { 6979 compute_alert0: trip-point0 { 6980 temperature = <90000>; 6981 hysteresis = <2000>; 6982 type = "hot"; 6983 }; 6984 }; 6985 }; 6986 6987 npu-thermal { 6988 polling-delay-passive = <250>; 6989 6990 thermal-sensors = <&tsens1 7>; 6991 6992 trips { 6993 npu_alert0: trip-point0 { 6994 temperature = <90000>; 6995 hysteresis = <2000>; 6996 type = "hot"; 6997 }; 6998 }; 6999 }; 7000 7001 gpu-bottom-thermal { 7002 polling-delay-passive = <250>; 7003 7004 thermal-sensors = <&tsens1 8>; 7005 7006 cooling-maps { 7007 map0 { 7008 trip = <&gpu_bottom_alert0>; 7009 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7010 }; 7011 }; 7012 7013 trips { 7014 gpu_bottom_alert0: trip-point0 { 7015 temperature = <85000>; 7016 hysteresis = <1000>; 7017 type = "passive"; 7018 }; 7019 7020 trip-point1 { 7021 temperature = <90000>; 7022 hysteresis = <1000>; 7023 type = "hot"; 7024 }; 7025 7026 trip-point2 { 7027 temperature = <110000>; 7028 hysteresis = <1000>; 7029 type = "critical"; 7030 }; 7031 }; 7032 }; 7033 }; 7034}; 7035