1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,gcc-sm8250.h> 9#include <dt-bindings/clock/qcom,gpucc-sm8250.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h> 12#include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,sm8250.h> 17#include <dt-bindings/mailbox/qcom-ipcc.h> 18#include <dt-bindings/phy/phy-qcom-qmp.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/power/qcom,rpmhpd.h> 21#include <dt-bindings/soc/qcom,apr.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23#include <dt-bindings/sound/qcom,q6afe.h> 24#include <dt-bindings/thermal/thermal.h> 25#include <dt-bindings/clock/qcom,camcc-sm8250.h> 26#include <dt-bindings/clock/qcom,videocc-sm8250.h> 27 28/ { 29 interrupt-parent = <&intc>; 30 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 aliases { 35 i2c0 = &i2c0; 36 i2c1 = &i2c1; 37 i2c2 = &i2c2; 38 i2c3 = &i2c3; 39 i2c4 = &i2c4; 40 i2c5 = &i2c5; 41 i2c6 = &i2c6; 42 i2c7 = &i2c7; 43 i2c8 = &i2c8; 44 i2c9 = &i2c9; 45 i2c10 = &i2c10; 46 i2c11 = &i2c11; 47 i2c12 = &i2c12; 48 i2c13 = &i2c13; 49 i2c14 = &i2c14; 50 i2c15 = &i2c15; 51 i2c16 = &i2c16; 52 i2c17 = &i2c17; 53 i2c18 = &i2c18; 54 i2c19 = &i2c19; 55 spi0 = &spi0; 56 spi1 = &spi1; 57 spi2 = &spi2; 58 spi3 = &spi3; 59 spi4 = &spi4; 60 spi5 = &spi5; 61 spi6 = &spi6; 62 spi7 = &spi7; 63 spi8 = &spi8; 64 spi9 = &spi9; 65 spi10 = &spi10; 66 spi11 = &spi11; 67 spi12 = &spi12; 68 spi13 = &spi13; 69 spi14 = &spi14; 70 spi15 = &spi15; 71 spi16 = &spi16; 72 spi17 = &spi17; 73 spi18 = &spi18; 74 spi19 = &spi19; 75 }; 76 77 chosen { }; 78 79 clocks { 80 xo_board: xo-board { 81 compatible = "fixed-clock"; 82 #clock-cells = <0>; 83 clock-frequency = <38400000>; 84 clock-output-names = "xo_board"; 85 }; 86 87 sleep_clk: sleep-clk { 88 compatible = "fixed-clock"; 89 clock-frequency = <32768>; 90 #clock-cells = <0>; 91 }; 92 }; 93 94 cpus { 95 #address-cells = <2>; 96 #size-cells = <0>; 97 98 CPU0: cpu@0 { 99 device_type = "cpu"; 100 compatible = "qcom,kryo485"; 101 reg = <0x0 0x0>; 102 clocks = <&cpufreq_hw 0>; 103 enable-method = "psci"; 104 capacity-dmips-mhz = <448>; 105 dynamic-power-coefficient = <105>; 106 next-level-cache = <&L2_0>; 107 power-domains = <&CPU_PD0>; 108 power-domain-names = "psci"; 109 qcom,freq-domain = <&cpufreq_hw 0>; 110 operating-points-v2 = <&cpu0_opp_table>; 111 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 112 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 113 #cooling-cells = <2>; 114 L2_0: l2-cache { 115 compatible = "cache"; 116 cache-level = <2>; 117 cache-size = <0x20000>; 118 cache-unified; 119 next-level-cache = <&L3_0>; 120 L3_0: l3-cache { 121 compatible = "cache"; 122 cache-level = <3>; 123 cache-size = <0x400000>; 124 cache-unified; 125 }; 126 }; 127 }; 128 129 CPU1: cpu@100 { 130 device_type = "cpu"; 131 compatible = "qcom,kryo485"; 132 reg = <0x0 0x100>; 133 clocks = <&cpufreq_hw 0>; 134 enable-method = "psci"; 135 capacity-dmips-mhz = <448>; 136 dynamic-power-coefficient = <105>; 137 next-level-cache = <&L2_100>; 138 power-domains = <&CPU_PD1>; 139 power-domain-names = "psci"; 140 qcom,freq-domain = <&cpufreq_hw 0>; 141 operating-points-v2 = <&cpu0_opp_table>; 142 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 143 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 144 #cooling-cells = <2>; 145 L2_100: l2-cache { 146 compatible = "cache"; 147 cache-level = <2>; 148 cache-size = <0x20000>; 149 cache-unified; 150 next-level-cache = <&L3_0>; 151 }; 152 }; 153 154 CPU2: cpu@200 { 155 device_type = "cpu"; 156 compatible = "qcom,kryo485"; 157 reg = <0x0 0x200>; 158 clocks = <&cpufreq_hw 0>; 159 enable-method = "psci"; 160 capacity-dmips-mhz = <448>; 161 dynamic-power-coefficient = <105>; 162 next-level-cache = <&L2_200>; 163 power-domains = <&CPU_PD2>; 164 power-domain-names = "psci"; 165 qcom,freq-domain = <&cpufreq_hw 0>; 166 operating-points-v2 = <&cpu0_opp_table>; 167 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 168 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 169 #cooling-cells = <2>; 170 L2_200: l2-cache { 171 compatible = "cache"; 172 cache-level = <2>; 173 cache-size = <0x20000>; 174 cache-unified; 175 next-level-cache = <&L3_0>; 176 }; 177 }; 178 179 CPU3: cpu@300 { 180 device_type = "cpu"; 181 compatible = "qcom,kryo485"; 182 reg = <0x0 0x300>; 183 clocks = <&cpufreq_hw 0>; 184 enable-method = "psci"; 185 capacity-dmips-mhz = <448>; 186 dynamic-power-coefficient = <105>; 187 next-level-cache = <&L2_300>; 188 power-domains = <&CPU_PD3>; 189 power-domain-names = "psci"; 190 qcom,freq-domain = <&cpufreq_hw 0>; 191 operating-points-v2 = <&cpu0_opp_table>; 192 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 193 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 194 #cooling-cells = <2>; 195 L2_300: l2-cache { 196 compatible = "cache"; 197 cache-level = <2>; 198 cache-size = <0x20000>; 199 cache-unified; 200 next-level-cache = <&L3_0>; 201 }; 202 }; 203 204 CPU4: cpu@400 { 205 device_type = "cpu"; 206 compatible = "qcom,kryo485"; 207 reg = <0x0 0x400>; 208 clocks = <&cpufreq_hw 1>; 209 enable-method = "psci"; 210 capacity-dmips-mhz = <1024>; 211 dynamic-power-coefficient = <379>; 212 next-level-cache = <&L2_400>; 213 power-domains = <&CPU_PD4>; 214 power-domain-names = "psci"; 215 qcom,freq-domain = <&cpufreq_hw 1>; 216 operating-points-v2 = <&cpu4_opp_table>; 217 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 218 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 219 #cooling-cells = <2>; 220 L2_400: l2-cache { 221 compatible = "cache"; 222 cache-level = <2>; 223 cache-size = <0x40000>; 224 cache-unified; 225 next-level-cache = <&L3_0>; 226 }; 227 }; 228 229 CPU5: cpu@500 { 230 device_type = "cpu"; 231 compatible = "qcom,kryo485"; 232 reg = <0x0 0x500>; 233 clocks = <&cpufreq_hw 1>; 234 enable-method = "psci"; 235 capacity-dmips-mhz = <1024>; 236 dynamic-power-coefficient = <379>; 237 next-level-cache = <&L2_500>; 238 power-domains = <&CPU_PD5>; 239 power-domain-names = "psci"; 240 qcom,freq-domain = <&cpufreq_hw 1>; 241 operating-points-v2 = <&cpu4_opp_table>; 242 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 243 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 244 #cooling-cells = <2>; 245 L2_500: l2-cache { 246 compatible = "cache"; 247 cache-level = <2>; 248 cache-size = <0x40000>; 249 cache-unified; 250 next-level-cache = <&L3_0>; 251 }; 252 }; 253 254 CPU6: cpu@600 { 255 device_type = "cpu"; 256 compatible = "qcom,kryo485"; 257 reg = <0x0 0x600>; 258 clocks = <&cpufreq_hw 1>; 259 enable-method = "psci"; 260 capacity-dmips-mhz = <1024>; 261 dynamic-power-coefficient = <379>; 262 next-level-cache = <&L2_600>; 263 power-domains = <&CPU_PD6>; 264 power-domain-names = "psci"; 265 qcom,freq-domain = <&cpufreq_hw 1>; 266 operating-points-v2 = <&cpu4_opp_table>; 267 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 268 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 269 #cooling-cells = <2>; 270 L2_600: l2-cache { 271 compatible = "cache"; 272 cache-level = <2>; 273 cache-size = <0x40000>; 274 cache-unified; 275 next-level-cache = <&L3_0>; 276 }; 277 }; 278 279 CPU7: cpu@700 { 280 device_type = "cpu"; 281 compatible = "qcom,kryo485"; 282 reg = <0x0 0x700>; 283 clocks = <&cpufreq_hw 2>; 284 enable-method = "psci"; 285 capacity-dmips-mhz = <1024>; 286 dynamic-power-coefficient = <444>; 287 next-level-cache = <&L2_700>; 288 power-domains = <&CPU_PD7>; 289 power-domain-names = "psci"; 290 qcom,freq-domain = <&cpufreq_hw 2>; 291 operating-points-v2 = <&cpu7_opp_table>; 292 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 293 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 294 #cooling-cells = <2>; 295 L2_700: l2-cache { 296 compatible = "cache"; 297 cache-level = <2>; 298 cache-size = <0x80000>; 299 cache-unified; 300 next-level-cache = <&L3_0>; 301 }; 302 }; 303 304 cpu-map { 305 cluster0 { 306 core0 { 307 cpu = <&CPU0>; 308 }; 309 310 core1 { 311 cpu = <&CPU1>; 312 }; 313 314 core2 { 315 cpu = <&CPU2>; 316 }; 317 318 core3 { 319 cpu = <&CPU3>; 320 }; 321 322 core4 { 323 cpu = <&CPU4>; 324 }; 325 326 core5 { 327 cpu = <&CPU5>; 328 }; 329 330 core6 { 331 cpu = <&CPU6>; 332 }; 333 334 core7 { 335 cpu = <&CPU7>; 336 }; 337 }; 338 }; 339 340 idle-states { 341 entry-method = "psci"; 342 343 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 344 compatible = "arm,idle-state"; 345 idle-state-name = "silver-rail-power-collapse"; 346 arm,psci-suspend-param = <0x40000004>; 347 entry-latency-us = <360>; 348 exit-latency-us = <531>; 349 min-residency-us = <3934>; 350 local-timer-stop; 351 }; 352 353 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 354 compatible = "arm,idle-state"; 355 idle-state-name = "gold-rail-power-collapse"; 356 arm,psci-suspend-param = <0x40000004>; 357 entry-latency-us = <702>; 358 exit-latency-us = <1061>; 359 min-residency-us = <4488>; 360 local-timer-stop; 361 }; 362 }; 363 364 domain-idle-states { 365 CLUSTER_SLEEP_0: cluster-sleep-0 { 366 compatible = "domain-idle-state"; 367 arm,psci-suspend-param = <0x4100c244>; 368 entry-latency-us = <3264>; 369 exit-latency-us = <6562>; 370 min-residency-us = <9987>; 371 }; 372 }; 373 }; 374 375 qup_virt: interconnect-qup-virt { 376 compatible = "qcom,sm8250-qup-virt"; 377 #interconnect-cells = <2>; 378 qcom,bcm-voters = <&apps_bcm_voter>; 379 }; 380 381 cpu0_opp_table: opp-table-cpu0 { 382 compatible = "operating-points-v2"; 383 opp-shared; 384 385 cpu0_opp1: opp-300000000 { 386 opp-hz = /bits/ 64 <300000000>; 387 opp-peak-kBps = <800000 9600000>; 388 }; 389 390 cpu0_opp2: opp-403200000 { 391 opp-hz = /bits/ 64 <403200000>; 392 opp-peak-kBps = <800000 9600000>; 393 }; 394 395 cpu0_opp3: opp-518400000 { 396 opp-hz = /bits/ 64 <518400000>; 397 opp-peak-kBps = <800000 16588800>; 398 }; 399 400 cpu0_opp4: opp-614400000 { 401 opp-hz = /bits/ 64 <614400000>; 402 opp-peak-kBps = <800000 16588800>; 403 }; 404 405 cpu0_opp5: opp-691200000 { 406 opp-hz = /bits/ 64 <691200000>; 407 opp-peak-kBps = <800000 19660800>; 408 }; 409 410 cpu0_opp6: opp-787200000 { 411 opp-hz = /bits/ 64 <787200000>; 412 opp-peak-kBps = <1804000 19660800>; 413 }; 414 415 cpu0_opp7: opp-883200000 { 416 opp-hz = /bits/ 64 <883200000>; 417 opp-peak-kBps = <1804000 23347200>; 418 }; 419 420 cpu0_opp8: opp-979200000 { 421 opp-hz = /bits/ 64 <979200000>; 422 opp-peak-kBps = <1804000 26419200>; 423 }; 424 425 cpu0_opp9: opp-1075200000 { 426 opp-hz = /bits/ 64 <1075200000>; 427 opp-peak-kBps = <1804000 29491200>; 428 }; 429 430 cpu0_opp10: opp-1171200000 { 431 opp-hz = /bits/ 64 <1171200000>; 432 opp-peak-kBps = <1804000 32563200>; 433 }; 434 435 cpu0_opp11: opp-1248000000 { 436 opp-hz = /bits/ 64 <1248000000>; 437 opp-peak-kBps = <1804000 36249600>; 438 }; 439 440 cpu0_opp12: opp-1344000000 { 441 opp-hz = /bits/ 64 <1344000000>; 442 opp-peak-kBps = <2188000 36249600>; 443 }; 444 445 cpu0_opp13: opp-1420800000 { 446 opp-hz = /bits/ 64 <1420800000>; 447 opp-peak-kBps = <2188000 39321600>; 448 }; 449 450 cpu0_opp14: opp-1516800000 { 451 opp-hz = /bits/ 64 <1516800000>; 452 opp-peak-kBps = <3072000 42393600>; 453 }; 454 455 cpu0_opp15: opp-1612800000 { 456 opp-hz = /bits/ 64 <1612800000>; 457 opp-peak-kBps = <3072000 42393600>; 458 }; 459 460 cpu0_opp16: opp-1708800000 { 461 opp-hz = /bits/ 64 <1708800000>; 462 opp-peak-kBps = <4068000 42393600>; 463 }; 464 465 cpu0_opp17: opp-1804800000 { 466 opp-hz = /bits/ 64 <1804800000>; 467 opp-peak-kBps = <4068000 42393600>; 468 }; 469 }; 470 471 cpu4_opp_table: opp-table-cpu4 { 472 compatible = "operating-points-v2"; 473 opp-shared; 474 475 cpu4_opp1: opp-710400000 { 476 opp-hz = /bits/ 64 <710400000>; 477 opp-peak-kBps = <1804000 19660800>; 478 }; 479 480 cpu4_opp2: opp-825600000 { 481 opp-hz = /bits/ 64 <825600000>; 482 opp-peak-kBps = <2188000 23347200>; 483 }; 484 485 cpu4_opp3: opp-940800000 { 486 opp-hz = /bits/ 64 <940800000>; 487 opp-peak-kBps = <2188000 26419200>; 488 }; 489 490 cpu4_opp4: opp-1056000000 { 491 opp-hz = /bits/ 64 <1056000000>; 492 opp-peak-kBps = <3072000 26419200>; 493 }; 494 495 cpu4_opp5: opp-1171200000 { 496 opp-hz = /bits/ 64 <1171200000>; 497 opp-peak-kBps = <3072000 29491200>; 498 }; 499 500 cpu4_opp6: opp-1286400000 { 501 opp-hz = /bits/ 64 <1286400000>; 502 opp-peak-kBps = <4068000 29491200>; 503 }; 504 505 cpu4_opp7: opp-1382400000 { 506 opp-hz = /bits/ 64 <1382400000>; 507 opp-peak-kBps = <4068000 32563200>; 508 }; 509 510 cpu4_opp8: opp-1478400000 { 511 opp-hz = /bits/ 64 <1478400000>; 512 opp-peak-kBps = <4068000 32563200>; 513 }; 514 515 cpu4_opp9: opp-1574400000 { 516 opp-hz = /bits/ 64 <1574400000>; 517 opp-peak-kBps = <5412000 39321600>; 518 }; 519 520 cpu4_opp10: opp-1670400000 { 521 opp-hz = /bits/ 64 <1670400000>; 522 opp-peak-kBps = <5412000 42393600>; 523 }; 524 525 cpu4_opp11: opp-1766400000 { 526 opp-hz = /bits/ 64 <1766400000>; 527 opp-peak-kBps = <5412000 45465600>; 528 }; 529 530 cpu4_opp12: opp-1862400000 { 531 opp-hz = /bits/ 64 <1862400000>; 532 opp-peak-kBps = <6220000 45465600>; 533 }; 534 535 cpu4_opp13: opp-1958400000 { 536 opp-hz = /bits/ 64 <1958400000>; 537 opp-peak-kBps = <6220000 48537600>; 538 }; 539 540 cpu4_opp14: opp-2054400000 { 541 opp-hz = /bits/ 64 <2054400000>; 542 opp-peak-kBps = <7216000 48537600>; 543 }; 544 545 cpu4_opp15: opp-2150400000 { 546 opp-hz = /bits/ 64 <2150400000>; 547 opp-peak-kBps = <7216000 51609600>; 548 }; 549 550 cpu4_opp16: opp-2246400000 { 551 opp-hz = /bits/ 64 <2246400000>; 552 opp-peak-kBps = <7216000 51609600>; 553 }; 554 555 cpu4_opp17: opp-2342400000 { 556 opp-hz = /bits/ 64 <2342400000>; 557 opp-peak-kBps = <8368000 51609600>; 558 }; 559 560 cpu4_opp18: opp-2419200000 { 561 opp-hz = /bits/ 64 <2419200000>; 562 opp-peak-kBps = <8368000 51609600>; 563 }; 564 }; 565 566 cpu7_opp_table: opp-table-cpu7 { 567 compatible = "operating-points-v2"; 568 opp-shared; 569 570 cpu7_opp1: opp-844800000 { 571 opp-hz = /bits/ 64 <844800000>; 572 opp-peak-kBps = <2188000 19660800>; 573 }; 574 575 cpu7_opp2: opp-960000000 { 576 opp-hz = /bits/ 64 <960000000>; 577 opp-peak-kBps = <2188000 26419200>; 578 }; 579 580 cpu7_opp3: opp-1075200000 { 581 opp-hz = /bits/ 64 <1075200000>; 582 opp-peak-kBps = <3072000 26419200>; 583 }; 584 585 cpu7_opp4: opp-1190400000 { 586 opp-hz = /bits/ 64 <1190400000>; 587 opp-peak-kBps = <3072000 29491200>; 588 }; 589 590 cpu7_opp5: opp-1305600000 { 591 opp-hz = /bits/ 64 <1305600000>; 592 opp-peak-kBps = <4068000 32563200>; 593 }; 594 595 cpu7_opp6: opp-1401600000 { 596 opp-hz = /bits/ 64 <1401600000>; 597 opp-peak-kBps = <4068000 32563200>; 598 }; 599 600 cpu7_opp7: opp-1516800000 { 601 opp-hz = /bits/ 64 <1516800000>; 602 opp-peak-kBps = <4068000 36249600>; 603 }; 604 605 cpu7_opp8: opp-1632000000 { 606 opp-hz = /bits/ 64 <1632000000>; 607 opp-peak-kBps = <5412000 39321600>; 608 }; 609 610 cpu7_opp9: opp-1747200000 { 611 opp-hz = /bits/ 64 <1708800000>; 612 opp-peak-kBps = <5412000 42393600>; 613 }; 614 615 cpu7_opp10: opp-1862400000 { 616 opp-hz = /bits/ 64 <1862400000>; 617 opp-peak-kBps = <6220000 45465600>; 618 }; 619 620 cpu7_opp11: opp-1977600000 { 621 opp-hz = /bits/ 64 <1977600000>; 622 opp-peak-kBps = <6220000 48537600>; 623 }; 624 625 cpu7_opp12: opp-2073600000 { 626 opp-hz = /bits/ 64 <2073600000>; 627 opp-peak-kBps = <7216000 48537600>; 628 }; 629 630 cpu7_opp13: opp-2169600000 { 631 opp-hz = /bits/ 64 <2169600000>; 632 opp-peak-kBps = <7216000 51609600>; 633 }; 634 635 cpu7_opp14: opp-2265600000 { 636 opp-hz = /bits/ 64 <2265600000>; 637 opp-peak-kBps = <7216000 51609600>; 638 }; 639 640 cpu7_opp15: opp-2361600000 { 641 opp-hz = /bits/ 64 <2361600000>; 642 opp-peak-kBps = <8368000 51609600>; 643 }; 644 645 cpu7_opp16: opp-2457600000 { 646 opp-hz = /bits/ 64 <2457600000>; 647 opp-peak-kBps = <8368000 51609600>; 648 }; 649 650 cpu7_opp17: opp-2553600000 { 651 opp-hz = /bits/ 64 <2553600000>; 652 opp-peak-kBps = <8368000 51609600>; 653 }; 654 655 cpu7_opp18: opp-2649600000 { 656 opp-hz = /bits/ 64 <2649600000>; 657 opp-peak-kBps = <8368000 51609600>; 658 }; 659 660 cpu7_opp19: opp-2745600000 { 661 opp-hz = /bits/ 64 <2745600000>; 662 opp-peak-kBps = <8368000 51609600>; 663 }; 664 665 cpu7_opp20: opp-2841600000 { 666 opp-hz = /bits/ 64 <2841600000>; 667 opp-peak-kBps = <8368000 51609600>; 668 }; 669 }; 670 671 firmware { 672 scm: scm { 673 compatible = "qcom,scm-sm8250", "qcom,scm"; 674 qcom,dload-mode = <&tcsr 0x13000>; 675 #reset-cells = <1>; 676 }; 677 }; 678 679 memory@80000000 { 680 device_type = "memory"; 681 /* We expect the bootloader to fill in the size */ 682 reg = <0x0 0x80000000 0x0 0x0>; 683 }; 684 685 pmu { 686 compatible = "arm,armv8-pmuv3"; 687 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 688 }; 689 690 psci { 691 compatible = "arm,psci-1.0"; 692 method = "smc"; 693 694 CPU_PD0: power-domain-cpu0 { 695 #power-domain-cells = <0>; 696 power-domains = <&CLUSTER_PD>; 697 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 698 }; 699 700 CPU_PD1: power-domain-cpu1 { 701 #power-domain-cells = <0>; 702 power-domains = <&CLUSTER_PD>; 703 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 704 }; 705 706 CPU_PD2: power-domain-cpu2 { 707 #power-domain-cells = <0>; 708 power-domains = <&CLUSTER_PD>; 709 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 710 }; 711 712 CPU_PD3: power-domain-cpu3 { 713 #power-domain-cells = <0>; 714 power-domains = <&CLUSTER_PD>; 715 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 716 }; 717 718 CPU_PD4: power-domain-cpu4 { 719 #power-domain-cells = <0>; 720 power-domains = <&CLUSTER_PD>; 721 domain-idle-states = <&BIG_CPU_SLEEP_0>; 722 }; 723 724 CPU_PD5: power-domain-cpu5 { 725 #power-domain-cells = <0>; 726 power-domains = <&CLUSTER_PD>; 727 domain-idle-states = <&BIG_CPU_SLEEP_0>; 728 }; 729 730 CPU_PD6: power-domain-cpu6 { 731 #power-domain-cells = <0>; 732 power-domains = <&CLUSTER_PD>; 733 domain-idle-states = <&BIG_CPU_SLEEP_0>; 734 }; 735 736 CPU_PD7: power-domain-cpu7 { 737 #power-domain-cells = <0>; 738 power-domains = <&CLUSTER_PD>; 739 domain-idle-states = <&BIG_CPU_SLEEP_0>; 740 }; 741 742 CLUSTER_PD: power-domain-cpu-cluster0 { 743 #power-domain-cells = <0>; 744 domain-idle-states = <&CLUSTER_SLEEP_0>; 745 }; 746 }; 747 748 qup_opp_table: opp-table-qup { 749 compatible = "operating-points-v2"; 750 751 opp-50000000 { 752 opp-hz = /bits/ 64 <50000000>; 753 required-opps = <&rpmhpd_opp_min_svs>; 754 }; 755 756 opp-75000000 { 757 opp-hz = /bits/ 64 <75000000>; 758 required-opps = <&rpmhpd_opp_low_svs>; 759 }; 760 761 opp-120000000 { 762 opp-hz = /bits/ 64 <120000000>; 763 required-opps = <&rpmhpd_opp_svs>; 764 }; 765 }; 766 767 reserved-memory { 768 #address-cells = <2>; 769 #size-cells = <2>; 770 ranges; 771 772 hyp_mem: memory@80000000 { 773 reg = <0x0 0x80000000 0x0 0x600000>; 774 no-map; 775 }; 776 777 xbl_aop_mem: memory@80700000 { 778 reg = <0x0 0x80700000 0x0 0x160000>; 779 no-map; 780 }; 781 782 cmd_db: memory@80860000 { 783 compatible = "qcom,cmd-db"; 784 reg = <0x0 0x80860000 0x0 0x20000>; 785 no-map; 786 }; 787 788 smem_mem: memory@80900000 { 789 reg = <0x0 0x80900000 0x0 0x200000>; 790 no-map; 791 }; 792 793 removed_mem: memory@80b00000 { 794 reg = <0x0 0x80b00000 0x0 0x5300000>; 795 no-map; 796 }; 797 798 camera_mem: memory@86200000 { 799 reg = <0x0 0x86200000 0x0 0x500000>; 800 no-map; 801 }; 802 803 wlan_mem: memory@86700000 { 804 reg = <0x0 0x86700000 0x0 0x100000>; 805 no-map; 806 }; 807 808 ipa_fw_mem: memory@86800000 { 809 reg = <0x0 0x86800000 0x0 0x10000>; 810 no-map; 811 }; 812 813 ipa_gsi_mem: memory@86810000 { 814 reg = <0x0 0x86810000 0x0 0xa000>; 815 no-map; 816 }; 817 818 gpu_mem: memory@8681a000 { 819 reg = <0x0 0x8681a000 0x0 0x2000>; 820 no-map; 821 }; 822 823 npu_mem: memory@86900000 { 824 reg = <0x0 0x86900000 0x0 0x500000>; 825 no-map; 826 }; 827 828 video_mem: memory@86e00000 { 829 reg = <0x0 0x86e00000 0x0 0x500000>; 830 no-map; 831 }; 832 833 cvp_mem: memory@87300000 { 834 reg = <0x0 0x87300000 0x0 0x500000>; 835 no-map; 836 }; 837 838 cdsp_mem: memory@87800000 { 839 reg = <0x0 0x87800000 0x0 0x1400000>; 840 no-map; 841 }; 842 843 slpi_mem: memory@88c00000 { 844 reg = <0x0 0x88c00000 0x0 0x1500000>; 845 no-map; 846 }; 847 848 adsp_mem: memory@8a100000 { 849 reg = <0x0 0x8a100000 0x0 0x1d00000>; 850 no-map; 851 }; 852 853 spss_mem: memory@8be00000 { 854 reg = <0x0 0x8be00000 0x0 0x100000>; 855 no-map; 856 }; 857 858 cdsp_secure_heap: memory@8bf00000 { 859 reg = <0x0 0x8bf00000 0x0 0x4600000>; 860 no-map; 861 }; 862 }; 863 864 smem { 865 compatible = "qcom,smem"; 866 memory-region = <&smem_mem>; 867 hwlocks = <&tcsr_mutex 3>; 868 }; 869 870 smp2p-adsp { 871 compatible = "qcom,smp2p"; 872 qcom,smem = <443>, <429>; 873 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 874 IPCC_MPROC_SIGNAL_SMP2P 875 IRQ_TYPE_EDGE_RISING>; 876 mboxes = <&ipcc IPCC_CLIENT_LPASS 877 IPCC_MPROC_SIGNAL_SMP2P>; 878 879 qcom,local-pid = <0>; 880 qcom,remote-pid = <2>; 881 882 smp2p_adsp_out: master-kernel { 883 qcom,entry-name = "master-kernel"; 884 #qcom,smem-state-cells = <1>; 885 }; 886 887 smp2p_adsp_in: slave-kernel { 888 qcom,entry-name = "slave-kernel"; 889 interrupt-controller; 890 #interrupt-cells = <2>; 891 }; 892 }; 893 894 smp2p-cdsp { 895 compatible = "qcom,smp2p"; 896 qcom,smem = <94>, <432>; 897 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 898 IPCC_MPROC_SIGNAL_SMP2P 899 IRQ_TYPE_EDGE_RISING>; 900 mboxes = <&ipcc IPCC_CLIENT_CDSP 901 IPCC_MPROC_SIGNAL_SMP2P>; 902 903 qcom,local-pid = <0>; 904 qcom,remote-pid = <5>; 905 906 smp2p_cdsp_out: master-kernel { 907 qcom,entry-name = "master-kernel"; 908 #qcom,smem-state-cells = <1>; 909 }; 910 911 smp2p_cdsp_in: slave-kernel { 912 qcom,entry-name = "slave-kernel"; 913 interrupt-controller; 914 #interrupt-cells = <2>; 915 }; 916 }; 917 918 smp2p-slpi { 919 compatible = "qcom,smp2p"; 920 qcom,smem = <481>, <430>; 921 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 922 IPCC_MPROC_SIGNAL_SMP2P 923 IRQ_TYPE_EDGE_RISING>; 924 mboxes = <&ipcc IPCC_CLIENT_SLPI 925 IPCC_MPROC_SIGNAL_SMP2P>; 926 927 qcom,local-pid = <0>; 928 qcom,remote-pid = <3>; 929 930 smp2p_slpi_out: master-kernel { 931 qcom,entry-name = "master-kernel"; 932 #qcom,smem-state-cells = <1>; 933 }; 934 935 smp2p_slpi_in: slave-kernel { 936 qcom,entry-name = "slave-kernel"; 937 interrupt-controller; 938 #interrupt-cells = <2>; 939 }; 940 }; 941 942 soc: soc@0 { 943 #address-cells = <2>; 944 #size-cells = <2>; 945 ranges = <0 0 0 0 0x10 0>; 946 dma-ranges = <0 0 0 0 0x10 0>; 947 compatible = "simple-bus"; 948 949 gcc: clock-controller@100000 { 950 compatible = "qcom,gcc-sm8250"; 951 reg = <0x0 0x00100000 0x0 0x1f0000>; 952 #clock-cells = <1>; 953 #reset-cells = <1>; 954 #power-domain-cells = <1>; 955 clock-names = "bi_tcxo", 956 "bi_tcxo_ao", 957 "sleep_clk"; 958 clocks = <&rpmhcc RPMH_CXO_CLK>, 959 <&rpmhcc RPMH_CXO_CLK_A>, 960 <&sleep_clk>; 961 }; 962 963 ipcc: mailbox@408000 { 964 compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; 965 reg = <0 0x00408000 0 0x1000>; 966 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 967 interrupt-controller; 968 #interrupt-cells = <3>; 969 #mbox-cells = <2>; 970 }; 971 972 qfprom: efuse@784000 { 973 compatible = "qcom,sm8250-qfprom", "qcom,qfprom"; 974 reg = <0 0x00784000 0 0x8ff>; 975 #address-cells = <1>; 976 #size-cells = <1>; 977 978 gpu_speed_bin: gpu-speed-bin@19b { 979 reg = <0x19b 0x1>; 980 bits = <5 3>; 981 }; 982 }; 983 984 rng: rng@793000 { 985 compatible = "qcom,prng-ee"; 986 reg = <0 0x00793000 0 0x1000>; 987 clocks = <&gcc GCC_PRNG_AHB_CLK>; 988 clock-names = "core"; 989 }; 990 991 gpi_dma2: dma-controller@800000 { 992 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 993 reg = <0 0x00800000 0 0x70000>; 994 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 997 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 998 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 999 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 1000 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1001 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1002 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1003 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; 1004 dma-channels = <10>; 1005 dma-channel-mask = <0x3f>; 1006 iommus = <&apps_smmu 0x76 0x0>; 1007 #dma-cells = <3>; 1008 status = "disabled"; 1009 }; 1010 1011 qupv3_id_2: geniqup@8c0000 { 1012 compatible = "qcom,geni-se-qup"; 1013 reg = <0x0 0x008c0000 0x0 0x6000>; 1014 clock-names = "m-ahb", "s-ahb"; 1015 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1016 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1017 #address-cells = <2>; 1018 #size-cells = <2>; 1019 iommus = <&apps_smmu 0x63 0x0>; 1020 ranges; 1021 status = "disabled"; 1022 1023 i2c14: i2c@880000 { 1024 compatible = "qcom,geni-i2c"; 1025 reg = <0 0x00880000 0 0x4000>; 1026 clock-names = "se"; 1027 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1028 pinctrl-names = "default"; 1029 pinctrl-0 = <&qup_i2c14_default>; 1030 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1031 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1032 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1033 dma-names = "tx", "rx"; 1034 power-domains = <&rpmhpd SM8250_CX>; 1035 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1036 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1037 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1038 interconnect-names = "qup-core", 1039 "qup-config", 1040 "qup-memory"; 1041 #address-cells = <1>; 1042 #size-cells = <0>; 1043 status = "disabled"; 1044 }; 1045 1046 spi14: spi@880000 { 1047 compatible = "qcom,geni-spi"; 1048 reg = <0 0x00880000 0 0x4000>; 1049 clock-names = "se"; 1050 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1051 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1052 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1053 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1054 dma-names = "tx", "rx"; 1055 power-domains = <&rpmhpd RPMHPD_CX>; 1056 operating-points-v2 = <&qup_opp_table>; 1057 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1058 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1059 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1060 interconnect-names = "qup-core", 1061 "qup-config", 1062 "qup-memory"; 1063 #address-cells = <1>; 1064 #size-cells = <0>; 1065 status = "disabled"; 1066 }; 1067 1068 i2c15: i2c@884000 { 1069 compatible = "qcom,geni-i2c"; 1070 reg = <0 0x00884000 0 0x4000>; 1071 clock-names = "se"; 1072 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1073 pinctrl-names = "default"; 1074 pinctrl-0 = <&qup_i2c15_default>; 1075 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1076 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1077 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1078 dma-names = "tx", "rx"; 1079 power-domains = <&rpmhpd SM8250_CX>; 1080 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1081 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1082 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1083 interconnect-names = "qup-core", 1084 "qup-config", 1085 "qup-memory"; 1086 #address-cells = <1>; 1087 #size-cells = <0>; 1088 status = "disabled"; 1089 }; 1090 1091 spi15: spi@884000 { 1092 compatible = "qcom,geni-spi"; 1093 reg = <0 0x00884000 0 0x4000>; 1094 clock-names = "se"; 1095 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1096 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1097 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1098 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1099 dma-names = "tx", "rx"; 1100 power-domains = <&rpmhpd RPMHPD_CX>; 1101 operating-points-v2 = <&qup_opp_table>; 1102 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1103 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1104 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1105 interconnect-names = "qup-core", 1106 "qup-config", 1107 "qup-memory"; 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 status = "disabled"; 1111 }; 1112 1113 i2c16: i2c@888000 { 1114 compatible = "qcom,geni-i2c"; 1115 reg = <0 0x00888000 0 0x4000>; 1116 clock-names = "se"; 1117 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1118 pinctrl-names = "default"; 1119 pinctrl-0 = <&qup_i2c16_default>; 1120 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1121 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1122 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1123 dma-names = "tx", "rx"; 1124 power-domains = <&rpmhpd SM8250_CX>; 1125 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1126 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1127 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1128 interconnect-names = "qup-core", 1129 "qup-config", 1130 "qup-memory"; 1131 #address-cells = <1>; 1132 #size-cells = <0>; 1133 status = "disabled"; 1134 }; 1135 1136 spi16: spi@888000 { 1137 compatible = "qcom,geni-spi"; 1138 reg = <0 0x00888000 0 0x4000>; 1139 clock-names = "se"; 1140 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1141 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1142 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1143 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1144 dma-names = "tx", "rx"; 1145 power-domains = <&rpmhpd RPMHPD_CX>; 1146 operating-points-v2 = <&qup_opp_table>; 1147 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1148 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1149 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1150 interconnect-names = "qup-core", 1151 "qup-config", 1152 "qup-memory"; 1153 #address-cells = <1>; 1154 #size-cells = <0>; 1155 status = "disabled"; 1156 }; 1157 1158 i2c17: i2c@88c000 { 1159 compatible = "qcom,geni-i2c"; 1160 reg = <0 0x0088c000 0 0x4000>; 1161 clock-names = "se"; 1162 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1163 pinctrl-names = "default"; 1164 pinctrl-0 = <&qup_i2c17_default>; 1165 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1166 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1167 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1168 dma-names = "tx", "rx"; 1169 power-domains = <&rpmhpd SM8250_CX>; 1170 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1171 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1172 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1173 interconnect-names = "qup-core", 1174 "qup-config", 1175 "qup-memory"; 1176 #address-cells = <1>; 1177 #size-cells = <0>; 1178 status = "disabled"; 1179 }; 1180 1181 spi17: spi@88c000 { 1182 compatible = "qcom,geni-spi"; 1183 reg = <0 0x0088c000 0 0x4000>; 1184 clock-names = "se"; 1185 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1186 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1187 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1188 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1189 dma-names = "tx", "rx"; 1190 power-domains = <&rpmhpd RPMHPD_CX>; 1191 operating-points-v2 = <&qup_opp_table>; 1192 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1193 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1194 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1195 interconnect-names = "qup-core", 1196 "qup-config", 1197 "qup-memory"; 1198 #address-cells = <1>; 1199 #size-cells = <0>; 1200 status = "disabled"; 1201 }; 1202 1203 uart17: serial@88c000 { 1204 compatible = "qcom,geni-uart"; 1205 reg = <0 0x0088c000 0 0x4000>; 1206 clock-names = "se"; 1207 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1208 pinctrl-names = "default"; 1209 pinctrl-0 = <&qup_uart17_default>; 1210 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1211 power-domains = <&rpmhpd RPMHPD_CX>; 1212 operating-points-v2 = <&qup_opp_table>; 1213 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1214 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1215 interconnect-names = "qup-core", 1216 "qup-config"; 1217 status = "disabled"; 1218 }; 1219 1220 i2c18: i2c@890000 { 1221 compatible = "qcom,geni-i2c"; 1222 reg = <0 0x00890000 0 0x4000>; 1223 clock-names = "se"; 1224 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1225 pinctrl-names = "default"; 1226 pinctrl-0 = <&qup_i2c18_default>; 1227 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1228 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1229 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1230 dma-names = "tx", "rx"; 1231 power-domains = <&rpmhpd SM8250_CX>; 1232 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1233 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1234 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1235 interconnect-names = "qup-core", 1236 "qup-config", 1237 "qup-memory"; 1238 #address-cells = <1>; 1239 #size-cells = <0>; 1240 status = "disabled"; 1241 }; 1242 1243 spi18: spi@890000 { 1244 compatible = "qcom,geni-spi"; 1245 reg = <0 0x00890000 0 0x4000>; 1246 clock-names = "se"; 1247 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1248 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1249 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1250 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1251 dma-names = "tx", "rx"; 1252 power-domains = <&rpmhpd RPMHPD_CX>; 1253 operating-points-v2 = <&qup_opp_table>; 1254 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1255 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1256 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1257 interconnect-names = "qup-core", 1258 "qup-config", 1259 "qup-memory"; 1260 #address-cells = <1>; 1261 #size-cells = <0>; 1262 status = "disabled"; 1263 }; 1264 1265 uart18: serial@890000 { 1266 compatible = "qcom,geni-uart"; 1267 reg = <0 0x00890000 0 0x4000>; 1268 clock-names = "se"; 1269 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1270 pinctrl-names = "default"; 1271 pinctrl-0 = <&qup_uart18_default>; 1272 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1273 power-domains = <&rpmhpd RPMHPD_CX>; 1274 operating-points-v2 = <&qup_opp_table>; 1275 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1276 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1277 interconnect-names = "qup-core", 1278 "qup-config"; 1279 status = "disabled"; 1280 }; 1281 1282 i2c19: i2c@894000 { 1283 compatible = "qcom,geni-i2c"; 1284 reg = <0 0x00894000 0 0x4000>; 1285 clock-names = "se"; 1286 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1287 pinctrl-names = "default"; 1288 pinctrl-0 = <&qup_i2c19_default>; 1289 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1290 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1291 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1292 dma-names = "tx", "rx"; 1293 power-domains = <&rpmhpd SM8250_CX>; 1294 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1295 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1296 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1297 interconnect-names = "qup-core", 1298 "qup-config", 1299 "qup-memory"; 1300 #address-cells = <1>; 1301 #size-cells = <0>; 1302 status = "disabled"; 1303 }; 1304 1305 spi19: spi@894000 { 1306 compatible = "qcom,geni-spi"; 1307 reg = <0 0x00894000 0 0x4000>; 1308 clock-names = "se"; 1309 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1310 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1311 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1312 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1313 dma-names = "tx", "rx"; 1314 power-domains = <&rpmhpd RPMHPD_CX>; 1315 operating-points-v2 = <&qup_opp_table>; 1316 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1317 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1318 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1319 interconnect-names = "qup-core", 1320 "qup-config", 1321 "qup-memory"; 1322 #address-cells = <1>; 1323 #size-cells = <0>; 1324 status = "disabled"; 1325 }; 1326 }; 1327 1328 gpi_dma0: dma-controller@900000 { 1329 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 1330 reg = <0 0x00900000 0 0x70000>; 1331 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1332 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1333 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1334 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1335 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1336 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1337 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1338 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1339 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1340 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1341 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1342 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1343 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1344 dma-channels = <15>; 1345 dma-channel-mask = <0x7ff>; 1346 iommus = <&apps_smmu 0x5b6 0x0>; 1347 #dma-cells = <3>; 1348 status = "disabled"; 1349 }; 1350 1351 qupv3_id_0: geniqup@9c0000 { 1352 compatible = "qcom,geni-se-qup"; 1353 reg = <0x0 0x009c0000 0x0 0x6000>; 1354 clock-names = "m-ahb", "s-ahb"; 1355 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1356 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1357 #address-cells = <2>; 1358 #size-cells = <2>; 1359 iommus = <&apps_smmu 0x5a3 0x0>; 1360 ranges; 1361 status = "disabled"; 1362 1363 i2c0: i2c@980000 { 1364 compatible = "qcom,geni-i2c"; 1365 reg = <0 0x00980000 0 0x4000>; 1366 clock-names = "se"; 1367 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1368 pinctrl-names = "default"; 1369 pinctrl-0 = <&qup_i2c0_default>; 1370 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1371 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1372 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1373 dma-names = "tx", "rx"; 1374 power-domains = <&rpmhpd SM8250_CX>; 1375 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1376 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1377 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1378 interconnect-names = "qup-core", 1379 "qup-config", 1380 "qup-memory"; 1381 #address-cells = <1>; 1382 #size-cells = <0>; 1383 status = "disabled"; 1384 }; 1385 1386 spi0: spi@980000 { 1387 compatible = "qcom,geni-spi"; 1388 reg = <0 0x00980000 0 0x4000>; 1389 clock-names = "se"; 1390 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1391 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1392 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1393 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1394 dma-names = "tx", "rx"; 1395 power-domains = <&rpmhpd RPMHPD_CX>; 1396 operating-points-v2 = <&qup_opp_table>; 1397 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1398 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1399 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1400 interconnect-names = "qup-core", 1401 "qup-config", 1402 "qup-memory"; 1403 #address-cells = <1>; 1404 #size-cells = <0>; 1405 status = "disabled"; 1406 }; 1407 1408 i2c1: i2c@984000 { 1409 compatible = "qcom,geni-i2c"; 1410 reg = <0 0x00984000 0 0x4000>; 1411 clock-names = "se"; 1412 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1413 pinctrl-names = "default"; 1414 pinctrl-0 = <&qup_i2c1_default>; 1415 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1416 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1417 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1418 dma-names = "tx", "rx"; 1419 power-domains = <&rpmhpd SM8250_CX>; 1420 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1421 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1422 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1423 interconnect-names = "qup-core", 1424 "qup-config", 1425 "qup-memory"; 1426 #address-cells = <1>; 1427 #size-cells = <0>; 1428 status = "disabled"; 1429 }; 1430 1431 spi1: spi@984000 { 1432 compatible = "qcom,geni-spi"; 1433 reg = <0 0x00984000 0 0x4000>; 1434 clock-names = "se"; 1435 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1436 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1437 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1438 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1439 dma-names = "tx", "rx"; 1440 power-domains = <&rpmhpd RPMHPD_CX>; 1441 operating-points-v2 = <&qup_opp_table>; 1442 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1443 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1444 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1445 interconnect-names = "qup-core", 1446 "qup-config", 1447 "qup-memory"; 1448 #address-cells = <1>; 1449 #size-cells = <0>; 1450 status = "disabled"; 1451 }; 1452 1453 i2c2: i2c@988000 { 1454 compatible = "qcom,geni-i2c"; 1455 reg = <0 0x00988000 0 0x4000>; 1456 clock-names = "se"; 1457 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1458 pinctrl-names = "default"; 1459 pinctrl-0 = <&qup_i2c2_default>; 1460 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1461 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1462 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1463 dma-names = "tx", "rx"; 1464 power-domains = <&rpmhpd SM8250_CX>; 1465 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1466 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1467 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1468 interconnect-names = "qup-core", 1469 "qup-config", 1470 "qup-memory"; 1471 #address-cells = <1>; 1472 #size-cells = <0>; 1473 status = "disabled"; 1474 }; 1475 1476 spi2: spi@988000 { 1477 compatible = "qcom,geni-spi"; 1478 reg = <0 0x00988000 0 0x4000>; 1479 clock-names = "se"; 1480 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1481 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1482 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1483 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1484 dma-names = "tx", "rx"; 1485 power-domains = <&rpmhpd RPMHPD_CX>; 1486 operating-points-v2 = <&qup_opp_table>; 1487 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1488 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1489 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1490 interconnect-names = "qup-core", 1491 "qup-config", 1492 "qup-memory"; 1493 #address-cells = <1>; 1494 #size-cells = <0>; 1495 status = "disabled"; 1496 }; 1497 1498 uart2: serial@988000 { 1499 compatible = "qcom,geni-debug-uart"; 1500 reg = <0 0x00988000 0 0x4000>; 1501 clock-names = "se"; 1502 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1503 pinctrl-names = "default"; 1504 pinctrl-0 = <&qup_uart2_default>; 1505 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1506 power-domains = <&rpmhpd RPMHPD_CX>; 1507 operating-points-v2 = <&qup_opp_table>; 1508 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1509 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1510 interconnect-names = "qup-core", 1511 "qup-config"; 1512 status = "disabled"; 1513 }; 1514 1515 i2c3: i2c@98c000 { 1516 compatible = "qcom,geni-i2c"; 1517 reg = <0 0x0098c000 0 0x4000>; 1518 clock-names = "se"; 1519 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1520 pinctrl-names = "default"; 1521 pinctrl-0 = <&qup_i2c3_default>; 1522 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1523 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1524 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1525 dma-names = "tx", "rx"; 1526 power-domains = <&rpmhpd SM8250_CX>; 1527 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1528 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1529 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1530 interconnect-names = "qup-core", 1531 "qup-config", 1532 "qup-memory"; 1533 #address-cells = <1>; 1534 #size-cells = <0>; 1535 status = "disabled"; 1536 }; 1537 1538 spi3: spi@98c000 { 1539 compatible = "qcom,geni-spi"; 1540 reg = <0 0x0098c000 0 0x4000>; 1541 clock-names = "se"; 1542 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1543 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1544 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1545 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1546 dma-names = "tx", "rx"; 1547 power-domains = <&rpmhpd RPMHPD_CX>; 1548 operating-points-v2 = <&qup_opp_table>; 1549 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1550 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1551 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1552 interconnect-names = "qup-core", 1553 "qup-config", 1554 "qup-memory"; 1555 #address-cells = <1>; 1556 #size-cells = <0>; 1557 status = "disabled"; 1558 }; 1559 1560 i2c4: i2c@990000 { 1561 compatible = "qcom,geni-i2c"; 1562 reg = <0 0x00990000 0 0x4000>; 1563 clock-names = "se"; 1564 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1565 pinctrl-names = "default"; 1566 pinctrl-0 = <&qup_i2c4_default>; 1567 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1568 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1569 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1570 dma-names = "tx", "rx"; 1571 power-domains = <&rpmhpd SM8250_CX>; 1572 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1573 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1574 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1575 interconnect-names = "qup-core", 1576 "qup-config", 1577 "qup-memory"; 1578 #address-cells = <1>; 1579 #size-cells = <0>; 1580 status = "disabled"; 1581 }; 1582 1583 spi4: spi@990000 { 1584 compatible = "qcom,geni-spi"; 1585 reg = <0 0x00990000 0 0x4000>; 1586 clock-names = "se"; 1587 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1588 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1589 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1590 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1591 dma-names = "tx", "rx"; 1592 power-domains = <&rpmhpd RPMHPD_CX>; 1593 operating-points-v2 = <&qup_opp_table>; 1594 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1595 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1596 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1597 interconnect-names = "qup-core", 1598 "qup-config", 1599 "qup-memory"; 1600 #address-cells = <1>; 1601 #size-cells = <0>; 1602 status = "disabled"; 1603 }; 1604 1605 i2c5: i2c@994000 { 1606 compatible = "qcom,geni-i2c"; 1607 reg = <0 0x00994000 0 0x4000>; 1608 clock-names = "se"; 1609 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1610 pinctrl-names = "default"; 1611 pinctrl-0 = <&qup_i2c5_default>; 1612 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1613 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1614 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1615 dma-names = "tx", "rx"; 1616 power-domains = <&rpmhpd SM8250_CX>; 1617 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1618 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1619 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1620 interconnect-names = "qup-core", 1621 "qup-config", 1622 "qup-memory"; 1623 #address-cells = <1>; 1624 #size-cells = <0>; 1625 status = "disabled"; 1626 }; 1627 1628 spi5: spi@994000 { 1629 compatible = "qcom,geni-spi"; 1630 reg = <0 0x00994000 0 0x4000>; 1631 clock-names = "se"; 1632 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1633 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1634 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1635 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1636 dma-names = "tx", "rx"; 1637 power-domains = <&rpmhpd RPMHPD_CX>; 1638 operating-points-v2 = <&qup_opp_table>; 1639 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1640 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1641 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1642 interconnect-names = "qup-core", 1643 "qup-config", 1644 "qup-memory"; 1645 #address-cells = <1>; 1646 #size-cells = <0>; 1647 status = "disabled"; 1648 }; 1649 1650 i2c6: i2c@998000 { 1651 compatible = "qcom,geni-i2c"; 1652 reg = <0 0x00998000 0 0x4000>; 1653 clock-names = "se"; 1654 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1655 pinctrl-names = "default"; 1656 pinctrl-0 = <&qup_i2c6_default>; 1657 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1658 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1659 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1660 dma-names = "tx", "rx"; 1661 power-domains = <&rpmhpd SM8250_CX>; 1662 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1663 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1664 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1665 interconnect-names = "qup-core", 1666 "qup-config", 1667 "qup-memory"; 1668 #address-cells = <1>; 1669 #size-cells = <0>; 1670 status = "disabled"; 1671 }; 1672 1673 spi6: spi@998000 { 1674 compatible = "qcom,geni-spi"; 1675 reg = <0 0x00998000 0 0x4000>; 1676 clock-names = "se"; 1677 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1678 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1679 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1680 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1681 dma-names = "tx", "rx"; 1682 power-domains = <&rpmhpd RPMHPD_CX>; 1683 operating-points-v2 = <&qup_opp_table>; 1684 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1685 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1686 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1687 interconnect-names = "qup-core", 1688 "qup-config", 1689 "qup-memory"; 1690 #address-cells = <1>; 1691 #size-cells = <0>; 1692 status = "disabled"; 1693 }; 1694 1695 uart6: serial@998000 { 1696 compatible = "qcom,geni-uart"; 1697 reg = <0 0x00998000 0 0x4000>; 1698 clock-names = "se"; 1699 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1700 pinctrl-names = "default"; 1701 pinctrl-0 = <&qup_uart6_default>; 1702 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1703 power-domains = <&rpmhpd RPMHPD_CX>; 1704 operating-points-v2 = <&qup_opp_table>; 1705 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1706 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1707 interconnect-names = "qup-core", 1708 "qup-config"; 1709 status = "disabled"; 1710 }; 1711 1712 i2c7: i2c@99c000 { 1713 compatible = "qcom,geni-i2c"; 1714 reg = <0 0x0099c000 0 0x4000>; 1715 clock-names = "se"; 1716 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1717 pinctrl-names = "default"; 1718 pinctrl-0 = <&qup_i2c7_default>; 1719 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1720 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1721 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1722 dma-names = "tx", "rx"; 1723 power-domains = <&rpmhpd SM8250_CX>; 1724 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1725 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1726 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1727 interconnect-names = "qup-core", 1728 "qup-config", 1729 "qup-memory"; 1730 #address-cells = <1>; 1731 #size-cells = <0>; 1732 status = "disabled"; 1733 }; 1734 1735 spi7: spi@99c000 { 1736 compatible = "qcom,geni-spi"; 1737 reg = <0 0x0099c000 0 0x4000>; 1738 clock-names = "se"; 1739 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1740 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1741 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1742 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1743 dma-names = "tx", "rx"; 1744 power-domains = <&rpmhpd RPMHPD_CX>; 1745 operating-points-v2 = <&qup_opp_table>; 1746 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1747 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1748 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1749 interconnect-names = "qup-core", 1750 "qup-config", 1751 "qup-memory"; 1752 #address-cells = <1>; 1753 #size-cells = <0>; 1754 status = "disabled"; 1755 }; 1756 }; 1757 1758 gpi_dma1: dma-controller@a00000 { 1759 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 1760 reg = <0 0x00a00000 0 0x70000>; 1761 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1770 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; 1771 dma-channels = <10>; 1772 dma-channel-mask = <0x3f>; 1773 iommus = <&apps_smmu 0x56 0x0>; 1774 #dma-cells = <3>; 1775 status = "disabled"; 1776 }; 1777 1778 qupv3_id_1: geniqup@ac0000 { 1779 compatible = "qcom,geni-se-qup"; 1780 reg = <0x0 0x00ac0000 0x0 0x6000>; 1781 clock-names = "m-ahb", "s-ahb"; 1782 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1783 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1784 #address-cells = <2>; 1785 #size-cells = <2>; 1786 iommus = <&apps_smmu 0x43 0x0>; 1787 ranges; 1788 status = "disabled"; 1789 1790 i2c8: i2c@a80000 { 1791 compatible = "qcom,geni-i2c"; 1792 reg = <0 0x00a80000 0 0x4000>; 1793 clock-names = "se"; 1794 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1795 pinctrl-names = "default"; 1796 pinctrl-0 = <&qup_i2c8_default>; 1797 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1798 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1799 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1800 dma-names = "tx", "rx"; 1801 power-domains = <&rpmhpd SM8250_CX>; 1802 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1803 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1804 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1805 interconnect-names = "qup-core", 1806 "qup-config", 1807 "qup-memory"; 1808 #address-cells = <1>; 1809 #size-cells = <0>; 1810 status = "disabled"; 1811 }; 1812 1813 spi8: spi@a80000 { 1814 compatible = "qcom,geni-spi"; 1815 reg = <0 0x00a80000 0 0x4000>; 1816 clock-names = "se"; 1817 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1818 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1819 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1820 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1821 dma-names = "tx", "rx"; 1822 power-domains = <&rpmhpd RPMHPD_CX>; 1823 operating-points-v2 = <&qup_opp_table>; 1824 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1825 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1826 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1827 interconnect-names = "qup-core", 1828 "qup-config", 1829 "qup-memory"; 1830 #address-cells = <1>; 1831 #size-cells = <0>; 1832 status = "disabled"; 1833 }; 1834 1835 i2c9: i2c@a84000 { 1836 compatible = "qcom,geni-i2c"; 1837 reg = <0 0x00a84000 0 0x4000>; 1838 clock-names = "se"; 1839 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1840 pinctrl-names = "default"; 1841 pinctrl-0 = <&qup_i2c9_default>; 1842 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1843 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1844 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1845 dma-names = "tx", "rx"; 1846 power-domains = <&rpmhpd SM8250_CX>; 1847 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1848 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1849 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1850 interconnect-names = "qup-core", 1851 "qup-config", 1852 "qup-memory"; 1853 #address-cells = <1>; 1854 #size-cells = <0>; 1855 status = "disabled"; 1856 }; 1857 1858 spi9: spi@a84000 { 1859 compatible = "qcom,geni-spi"; 1860 reg = <0 0x00a84000 0 0x4000>; 1861 clock-names = "se"; 1862 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1863 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1864 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1865 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1866 dma-names = "tx", "rx"; 1867 power-domains = <&rpmhpd RPMHPD_CX>; 1868 operating-points-v2 = <&qup_opp_table>; 1869 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1870 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1871 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1872 interconnect-names = "qup-core", 1873 "qup-config", 1874 "qup-memory"; 1875 #address-cells = <1>; 1876 #size-cells = <0>; 1877 status = "disabled"; 1878 }; 1879 1880 i2c10: i2c@a88000 { 1881 compatible = "qcom,geni-i2c"; 1882 reg = <0 0x00a88000 0 0x4000>; 1883 clock-names = "se"; 1884 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1885 pinctrl-names = "default"; 1886 pinctrl-0 = <&qup_i2c10_default>; 1887 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1888 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1889 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1890 dma-names = "tx", "rx"; 1891 power-domains = <&rpmhpd SM8250_CX>; 1892 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1893 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1894 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1895 interconnect-names = "qup-core", 1896 "qup-config", 1897 "qup-memory"; 1898 #address-cells = <1>; 1899 #size-cells = <0>; 1900 status = "disabled"; 1901 }; 1902 1903 spi10: spi@a88000 { 1904 compatible = "qcom,geni-spi"; 1905 reg = <0 0x00a88000 0 0x4000>; 1906 clock-names = "se"; 1907 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1908 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1909 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1910 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1911 dma-names = "tx", "rx"; 1912 power-domains = <&rpmhpd RPMHPD_CX>; 1913 operating-points-v2 = <&qup_opp_table>; 1914 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1915 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1916 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1917 interconnect-names = "qup-core", 1918 "qup-config", 1919 "qup-memory"; 1920 #address-cells = <1>; 1921 #size-cells = <0>; 1922 status = "disabled"; 1923 }; 1924 1925 i2c11: i2c@a8c000 { 1926 compatible = "qcom,geni-i2c"; 1927 reg = <0 0x00a8c000 0 0x4000>; 1928 clock-names = "se"; 1929 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1930 pinctrl-names = "default"; 1931 pinctrl-0 = <&qup_i2c11_default>; 1932 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1933 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1934 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1935 dma-names = "tx", "rx"; 1936 power-domains = <&rpmhpd SM8250_CX>; 1937 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1938 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1939 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1940 interconnect-names = "qup-core", 1941 "qup-config", 1942 "qup-memory"; 1943 #address-cells = <1>; 1944 #size-cells = <0>; 1945 status = "disabled"; 1946 }; 1947 1948 spi11: spi@a8c000 { 1949 compatible = "qcom,geni-spi"; 1950 reg = <0 0x00a8c000 0 0x4000>; 1951 clock-names = "se"; 1952 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1953 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1954 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1955 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1956 dma-names = "tx", "rx"; 1957 power-domains = <&rpmhpd RPMHPD_CX>; 1958 operating-points-v2 = <&qup_opp_table>; 1959 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1960 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1961 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1962 interconnect-names = "qup-core", 1963 "qup-config", 1964 "qup-memory"; 1965 #address-cells = <1>; 1966 #size-cells = <0>; 1967 status = "disabled"; 1968 }; 1969 1970 i2c12: i2c@a90000 { 1971 compatible = "qcom,geni-i2c"; 1972 reg = <0 0x00a90000 0 0x4000>; 1973 clock-names = "se"; 1974 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1975 pinctrl-names = "default"; 1976 pinctrl-0 = <&qup_i2c12_default>; 1977 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1978 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1979 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1980 dma-names = "tx", "rx"; 1981 power-domains = <&rpmhpd SM8250_CX>; 1982 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1983 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1984 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1985 interconnect-names = "qup-core", 1986 "qup-config", 1987 "qup-memory"; 1988 #address-cells = <1>; 1989 #size-cells = <0>; 1990 status = "disabled"; 1991 }; 1992 1993 spi12: spi@a90000 { 1994 compatible = "qcom,geni-spi"; 1995 reg = <0 0x00a90000 0 0x4000>; 1996 clock-names = "se"; 1997 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1998 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1999 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 2000 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 2001 dma-names = "tx", "rx"; 2002 power-domains = <&rpmhpd RPMHPD_CX>; 2003 operating-points-v2 = <&qup_opp_table>; 2004 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 2005 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 2006 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 2007 interconnect-names = "qup-core", 2008 "qup-config", 2009 "qup-memory"; 2010 #address-cells = <1>; 2011 #size-cells = <0>; 2012 status = "disabled"; 2013 }; 2014 2015 uart12: serial@a90000 { 2016 compatible = "qcom,geni-debug-uart"; 2017 reg = <0x0 0x00a90000 0x0 0x4000>; 2018 clock-names = "se"; 2019 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2020 pinctrl-names = "default"; 2021 pinctrl-0 = <&qup_uart12_default>; 2022 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2023 power-domains = <&rpmhpd RPMHPD_CX>; 2024 operating-points-v2 = <&qup_opp_table>; 2025 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 2026 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 2027 interconnect-names = "qup-core", 2028 "qup-config"; 2029 status = "disabled"; 2030 }; 2031 2032 i2c13: i2c@a94000 { 2033 compatible = "qcom,geni-i2c"; 2034 reg = <0 0x00a94000 0 0x4000>; 2035 clock-names = "se"; 2036 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2037 pinctrl-names = "default"; 2038 pinctrl-0 = <&qup_i2c13_default>; 2039 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2040 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 2041 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 2042 dma-names = "tx", "rx"; 2043 power-domains = <&rpmhpd SM8250_CX>; 2044 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 2045 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 2046 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 2047 interconnect-names = "qup-core", 2048 "qup-config", 2049 "qup-memory"; 2050 #address-cells = <1>; 2051 #size-cells = <0>; 2052 status = "disabled"; 2053 }; 2054 2055 spi13: spi@a94000 { 2056 compatible = "qcom,geni-spi"; 2057 reg = <0 0x00a94000 0 0x4000>; 2058 clock-names = "se"; 2059 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2060 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2061 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 2062 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 2063 dma-names = "tx", "rx"; 2064 power-domains = <&rpmhpd RPMHPD_CX>; 2065 operating-points-v2 = <&qup_opp_table>; 2066 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 2067 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 2068 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 2069 interconnect-names = "qup-core", 2070 "qup-config", 2071 "qup-memory"; 2072 #address-cells = <1>; 2073 #size-cells = <0>; 2074 status = "disabled"; 2075 }; 2076 }; 2077 2078 config_noc: interconnect@1500000 { 2079 compatible = "qcom,sm8250-config-noc"; 2080 reg = <0 0x01500000 0 0xa580>; 2081 #interconnect-cells = <2>; 2082 qcom,bcm-voters = <&apps_bcm_voter>; 2083 }; 2084 2085 system_noc: interconnect@1620000 { 2086 compatible = "qcom,sm8250-system-noc"; 2087 reg = <0 0x01620000 0 0x1c200>; 2088 #interconnect-cells = <2>; 2089 qcom,bcm-voters = <&apps_bcm_voter>; 2090 }; 2091 2092 mc_virt: interconnect@163d000 { 2093 compatible = "qcom,sm8250-mc-virt"; 2094 reg = <0 0x0163d000 0 0x1000>; 2095 #interconnect-cells = <2>; 2096 qcom,bcm-voters = <&apps_bcm_voter>; 2097 }; 2098 2099 aggre1_noc: interconnect@16e0000 { 2100 compatible = "qcom,sm8250-aggre1-noc"; 2101 reg = <0 0x016e0000 0 0x1f180>; 2102 #interconnect-cells = <2>; 2103 qcom,bcm-voters = <&apps_bcm_voter>; 2104 }; 2105 2106 aggre2_noc: interconnect@1700000 { 2107 compatible = "qcom,sm8250-aggre2-noc"; 2108 reg = <0 0x01700000 0 0x33000>; 2109 #interconnect-cells = <2>; 2110 qcom,bcm-voters = <&apps_bcm_voter>; 2111 }; 2112 2113 compute_noc: interconnect@1733000 { 2114 compatible = "qcom,sm8250-compute-noc"; 2115 reg = <0 0x01733000 0 0xa180>; 2116 #interconnect-cells = <2>; 2117 qcom,bcm-voters = <&apps_bcm_voter>; 2118 }; 2119 2120 mmss_noc: interconnect@1740000 { 2121 compatible = "qcom,sm8250-mmss-noc"; 2122 reg = <0 0x01740000 0 0x1f080>; 2123 #interconnect-cells = <2>; 2124 qcom,bcm-voters = <&apps_bcm_voter>; 2125 }; 2126 2127 pcie0: pcie@1c00000 { 2128 compatible = "qcom,pcie-sm8250"; 2129 reg = <0 0x01c00000 0 0x3000>, 2130 <0 0x60000000 0 0xf1d>, 2131 <0 0x60000f20 0 0xa8>, 2132 <0 0x60001000 0 0x1000>, 2133 <0 0x60100000 0 0x100000>, 2134 <0 0x01c03000 0 0x1000>; 2135 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2136 device_type = "pci"; 2137 linux,pci-domain = <0>; 2138 bus-range = <0x00 0xff>; 2139 num-lanes = <1>; 2140 2141 #address-cells = <3>; 2142 #size-cells = <2>; 2143 2144 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 2145 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 2146 2147 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2148 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2149 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2150 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2151 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2152 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2153 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2154 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2155 interrupt-names = "msi0", 2156 "msi1", 2157 "msi2", 2158 "msi3", 2159 "msi4", 2160 "msi5", 2161 "msi6", 2162 "msi7"; 2163 #interrupt-cells = <1>; 2164 interrupt-map-mask = <0 0 0 0x7>; 2165 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2166 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2167 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2168 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2169 2170 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 2171 <&gcc GCC_PCIE_0_AUX_CLK>, 2172 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2173 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2174 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2175 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2176 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2177 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 2178 clock-names = "pipe", 2179 "aux", 2180 "cfg", 2181 "bus_master", 2182 "bus_slave", 2183 "slave_q2a", 2184 "tbu", 2185 "ddrss_sf_tbu"; 2186 2187 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 2188 <0x100 &apps_smmu 0x1c01 0x1>; 2189 2190 resets = <&gcc GCC_PCIE_0_BCR>; 2191 reset-names = "pci"; 2192 2193 power-domains = <&gcc PCIE_0_GDSC>; 2194 2195 phys = <&pcie0_phy>; 2196 phy-names = "pciephy"; 2197 2198 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; 2199 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; 2200 2201 pinctrl-names = "default"; 2202 pinctrl-0 = <&pcie0_default_state>; 2203 dma-coherent; 2204 2205 status = "disabled"; 2206 2207 pcie@0 { 2208 device_type = "pci"; 2209 reg = <0x0 0x0 0x0 0x0 0x0>; 2210 bus-range = <0x01 0xff>; 2211 2212 #address-cells = <3>; 2213 #size-cells = <2>; 2214 ranges; 2215 }; 2216 }; 2217 2218 pcie0_phy: phy@1c06000 { 2219 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; 2220 reg = <0 0x01c06000 0 0x1000>; 2221 2222 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2223 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2224 <&gcc GCC_PCIE_WIFI_CLKREF_EN>, 2225 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, 2226 <&gcc GCC_PCIE_0_PIPE_CLK>; 2227 clock-names = "aux", 2228 "cfg_ahb", 2229 "ref", 2230 "refgen", 2231 "pipe"; 2232 2233 clock-output-names = "pcie_0_pipe_clk"; 2234 #clock-cells = <0>; 2235 2236 #phy-cells = <0>; 2237 2238 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2239 reset-names = "phy"; 2240 2241 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 2242 assigned-clock-rates = <100000000>; 2243 2244 status = "disabled"; 2245 }; 2246 2247 pcie1: pcie@1c08000 { 2248 compatible = "qcom,pcie-sm8250"; 2249 reg = <0 0x01c08000 0 0x3000>, 2250 <0 0x40000000 0 0xf1d>, 2251 <0 0x40000f20 0 0xa8>, 2252 <0 0x40001000 0 0x1000>, 2253 <0 0x40100000 0 0x100000>, 2254 <0 0x01c0b000 0 0x1000>; 2255 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2256 device_type = "pci"; 2257 linux,pci-domain = <1>; 2258 bus-range = <0x00 0xff>; 2259 num-lanes = <2>; 2260 2261 #address-cells = <3>; 2262 #size-cells = <2>; 2263 2264 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2265 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2266 2267 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2268 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2269 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2270 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2271 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2272 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2273 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2274 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 2275 interrupt-names = "msi0", 2276 "msi1", 2277 "msi2", 2278 "msi3", 2279 "msi4", 2280 "msi5", 2281 "msi6", 2282 "msi7"; 2283 #interrupt-cells = <1>; 2284 interrupt-map-mask = <0 0 0 0x7>; 2285 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2286 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2287 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2288 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2289 2290 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2291 <&gcc GCC_PCIE_1_AUX_CLK>, 2292 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2293 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2294 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2295 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2296 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 2297 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2298 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 2299 clock-names = "pipe", 2300 "aux", 2301 "cfg", 2302 "bus_master", 2303 "bus_slave", 2304 "slave_q2a", 2305 "ref", 2306 "tbu", 2307 "ddrss_sf_tbu"; 2308 2309 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2310 assigned-clock-rates = <19200000>; 2311 2312 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2313 <0x100 &apps_smmu 0x1c81 0x1>; 2314 2315 resets = <&gcc GCC_PCIE_1_BCR>; 2316 reset-names = "pci"; 2317 2318 power-domains = <&gcc PCIE_1_GDSC>; 2319 2320 phys = <&pcie1_phy>; 2321 phy-names = "pciephy"; 2322 2323 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; 2324 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>; 2325 2326 pinctrl-names = "default"; 2327 pinctrl-0 = <&pcie1_default_state>; 2328 dma-coherent; 2329 2330 status = "disabled"; 2331 2332 pcie@0 { 2333 device_type = "pci"; 2334 reg = <0x0 0x0 0x0 0x0 0x0>; 2335 bus-range = <0x01 0xff>; 2336 2337 #address-cells = <3>; 2338 #size-cells = <2>; 2339 ranges; 2340 }; 2341 }; 2342 2343 pcie1_phy: phy@1c0e000 { 2344 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2345 reg = <0 0x01c0e000 0 0x1000>; 2346 2347 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2348 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2349 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 2350 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, 2351 <&gcc GCC_PCIE_1_PIPE_CLK>; 2352 clock-names = "aux", 2353 "cfg_ahb", 2354 "ref", 2355 "refgen", 2356 "pipe"; 2357 2358 clock-output-names = "pcie_1_pipe_clk"; 2359 #clock-cells = <0>; 2360 2361 #phy-cells = <0>; 2362 2363 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2364 reset-names = "phy"; 2365 2366 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2367 assigned-clock-rates = <100000000>; 2368 2369 status = "disabled"; 2370 }; 2371 2372 pcie2: pcie@1c10000 { 2373 compatible = "qcom,pcie-sm8250"; 2374 reg = <0 0x01c10000 0 0x3000>, 2375 <0 0x64000000 0 0xf1d>, 2376 <0 0x64000f20 0 0xa8>, 2377 <0 0x64001000 0 0x1000>, 2378 <0 0x64100000 0 0x100000>, 2379 <0 0x01c13000 0 0x1000>; 2380 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2381 device_type = "pci"; 2382 linux,pci-domain = <2>; 2383 bus-range = <0x00 0xff>; 2384 num-lanes = <2>; 2385 2386 #address-cells = <3>; 2387 #size-cells = <2>; 2388 2389 ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>, 2390 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; 2391 2392 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, 2393 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2394 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2395 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2396 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 2397 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 2398 <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 2399 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>; 2400 interrupt-names = "msi0", 2401 "msi1", 2402 "msi2", 2403 "msi3", 2404 "msi4", 2405 "msi5", 2406 "msi6", 2407 "msi7"; 2408 #interrupt-cells = <1>; 2409 interrupt-map-mask = <0 0 0 0x7>; 2410 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2411 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2412 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2413 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2414 2415 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2416 <&gcc GCC_PCIE_2_AUX_CLK>, 2417 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2418 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2419 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 2420 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 2421 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2422 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2423 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 2424 clock-names = "pipe", 2425 "aux", 2426 "cfg", 2427 "bus_master", 2428 "bus_slave", 2429 "slave_q2a", 2430 "ref", 2431 "tbu", 2432 "ddrss_sf_tbu"; 2433 2434 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 2435 assigned-clock-rates = <19200000>; 2436 2437 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 2438 <0x100 &apps_smmu 0x1d01 0x1>; 2439 2440 resets = <&gcc GCC_PCIE_2_BCR>; 2441 reset-names = "pci"; 2442 2443 power-domains = <&gcc PCIE_2_GDSC>; 2444 2445 phys = <&pcie2_phy>; 2446 phy-names = "pciephy"; 2447 2448 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; 2449 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; 2450 2451 pinctrl-names = "default"; 2452 pinctrl-0 = <&pcie2_default_state>; 2453 dma-coherent; 2454 2455 status = "disabled"; 2456 2457 pcie@0 { 2458 device_type = "pci"; 2459 reg = <0x0 0x0 0x0 0x0 0x0>; 2460 bus-range = <0x01 0xff>; 2461 2462 #address-cells = <3>; 2463 #size-cells = <2>; 2464 ranges; 2465 }; 2466 }; 2467 2468 pcie2_phy: phy@1c16000 { 2469 compatible = "qcom,sm8250-qmp-modem-pcie-phy"; 2470 reg = <0 0x01c16000 0 0x1000>; 2471 2472 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2473 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2474 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2475 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>, 2476 <&gcc GCC_PCIE_2_PIPE_CLK>; 2477 clock-names = "aux", 2478 "cfg_ahb", 2479 "ref", 2480 "refgen", 2481 "pipe"; 2482 2483 clock-output-names = "pcie_2_pipe_clk"; 2484 #clock-cells = <0>; 2485 2486 #phy-cells = <0>; 2487 2488 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 2489 reset-names = "phy"; 2490 2491 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2492 assigned-clock-rates = <100000000>; 2493 2494 status = "disabled"; 2495 }; 2496 2497 ufs_mem_hc: ufshc@1d84000 { 2498 compatible = "qcom,sm8250-ufshc", "qcom,ufshc", 2499 "jedec,ufs-2.0"; 2500 reg = <0 0x01d84000 0 0x3000>; 2501 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2502 phys = <&ufs_mem_phy>; 2503 phy-names = "ufsphy"; 2504 lanes-per-direction = <2>; 2505 #reset-cells = <1>; 2506 resets = <&gcc GCC_UFS_PHY_BCR>; 2507 reset-names = "rst"; 2508 2509 power-domains = <&gcc UFS_PHY_GDSC>; 2510 2511 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; 2512 2513 clock-names = 2514 "core_clk", 2515 "bus_aggr_clk", 2516 "iface_clk", 2517 "core_clk_unipro", 2518 "ref_clk", 2519 "tx_lane0_sync_clk", 2520 "rx_lane0_sync_clk", 2521 "rx_lane1_sync_clk"; 2522 clocks = 2523 <&gcc GCC_UFS_PHY_AXI_CLK>, 2524 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2525 <&gcc GCC_UFS_PHY_AHB_CLK>, 2526 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2527 <&rpmhcc RPMH_CXO_CLK>, 2528 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2529 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2530 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2531 2532 operating-points-v2 = <&ufs_opp_table>; 2533 2534 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI_CH0 0>, 2535 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 2536 interconnect-names = "ufs-ddr", "cpu-ufs"; 2537 2538 status = "disabled"; 2539 2540 ufs_opp_table: opp-table { 2541 compatible = "operating-points-v2"; 2542 2543 opp-37500000 { 2544 opp-hz = /bits/ 64 <37500000>, 2545 /bits/ 64 <0>, 2546 /bits/ 64 <0>, 2547 /bits/ 64 <37500000>, 2548 /bits/ 64 <0>, 2549 /bits/ 64 <0>, 2550 /bits/ 64 <0>, 2551 /bits/ 64 <0>; 2552 required-opps = <&rpmhpd_opp_low_svs>; 2553 }; 2554 2555 opp-300000000 { 2556 opp-hz = /bits/ 64 <300000000>, 2557 /bits/ 64 <0>, 2558 /bits/ 64 <0>, 2559 /bits/ 64 <300000000>, 2560 /bits/ 64 <0>, 2561 /bits/ 64 <0>, 2562 /bits/ 64 <0>, 2563 /bits/ 64 <0>; 2564 required-opps = <&rpmhpd_opp_nom>; 2565 }; 2566 }; 2567 }; 2568 2569 ufs_mem_phy: phy@1d87000 { 2570 compatible = "qcom,sm8250-qmp-ufs-phy"; 2571 reg = <0 0x01d87000 0 0x1000>; 2572 2573 clocks = <&rpmhcc RPMH_CXO_CLK>, 2574 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2575 <&gcc GCC_UFS_1X_CLKREF_EN>; 2576 clock-names = "ref", 2577 "ref_aux", 2578 "qref"; 2579 2580 resets = <&ufs_mem_hc 0>; 2581 reset-names = "ufsphy"; 2582 2583 #phy-cells = <0>; 2584 2585 status = "disabled"; 2586 }; 2587 2588 cryptobam: dma-controller@1dc4000 { 2589 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2590 reg = <0 0x01dc4000 0 0x24000>; 2591 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2592 #dma-cells = <1>; 2593 qcom,ee = <0>; 2594 qcom,controlled-remotely; 2595 num-channels = <8>; 2596 qcom,num-ees = <2>; 2597 iommus = <&apps_smmu 0x592 0x0000>, 2598 <&apps_smmu 0x598 0x0000>, 2599 <&apps_smmu 0x599 0x0000>, 2600 <&apps_smmu 0x59f 0x0000>, 2601 <&apps_smmu 0x586 0x0011>, 2602 <&apps_smmu 0x596 0x0011>; 2603 }; 2604 2605 crypto: crypto@1dfa000 { 2606 compatible = "qcom,sm8250-qce", "qcom,sm8150-qce", "qcom,qce"; 2607 reg = <0 0x01dfa000 0 0x6000>; 2608 dmas = <&cryptobam 4>, <&cryptobam 5>; 2609 dma-names = "rx", "tx"; 2610 iommus = <&apps_smmu 0x592 0x0000>, 2611 <&apps_smmu 0x598 0x0000>, 2612 <&apps_smmu 0x599 0x0000>, 2613 <&apps_smmu 0x59f 0x0000>, 2614 <&apps_smmu 0x586 0x0011>, 2615 <&apps_smmu 0x596 0x0011>; 2616 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>; 2617 interconnect-names = "memory"; 2618 }; 2619 2620 tcsr_mutex: hwlock@1f40000 { 2621 compatible = "qcom,tcsr-mutex"; 2622 reg = <0x0 0x01f40000 0x0 0x40000>; 2623 #hwlock-cells = <1>; 2624 }; 2625 2626 tcsr: syscon@1fc0000 { 2627 compatible = "qcom,sm8250-tcsr", "syscon"; 2628 reg = <0x0 0x1fc0000 0x0 0x30000>; 2629 }; 2630 2631 wsamacro: codec@3240000 { 2632 compatible = "qcom,sm8250-lpass-wsa-macro"; 2633 reg = <0 0x03240000 0 0x1000>; 2634 clocks = <&audiocc LPASS_CDC_WSA_MCLK>, 2635 <&audiocc LPASS_CDC_WSA_NPL>, 2636 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2637 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2638 <&aoncc LPASS_CDC_VA_MCLK>, 2639 <&vamacro>; 2640 2641 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; 2642 2643 #clock-cells = <0>; 2644 clock-output-names = "mclk"; 2645 #sound-dai-cells = <1>; 2646 2647 pinctrl-names = "default"; 2648 pinctrl-0 = <&wsa_swr_active>; 2649 2650 status = "disabled"; 2651 }; 2652 2653 swr0: soundwire@3250000 { 2654 reg = <0 0x03250000 0 0x2000>; 2655 compatible = "qcom,soundwire-v1.5.1"; 2656 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 2657 clocks = <&wsamacro>; 2658 clock-names = "iface"; 2659 2660 qcom,din-ports = <2>; 2661 qcom,dout-ports = <6>; 2662 2663 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2664 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2665 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2666 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; 2667 2668 #sound-dai-cells = <1>; 2669 #address-cells = <2>; 2670 #size-cells = <0>; 2671 2672 status = "disabled"; 2673 }; 2674 2675 audiocc: clock-controller@3300000 { 2676 compatible = "qcom,sm8250-lpass-audiocc"; 2677 reg = <0 0x03300000 0 0x30000>; 2678 #clock-cells = <1>; 2679 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2680 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2681 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2682 clock-names = "core", "audio", "bus"; 2683 }; 2684 2685 vamacro: codec@3370000 { 2686 compatible = "qcom,sm8250-lpass-va-macro"; 2687 reg = <0 0x03370000 0 0x1000>; 2688 clocks = <&aoncc LPASS_CDC_VA_MCLK>, 2689 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2690 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2691 2692 clock-names = "mclk", "macro", "dcodec"; 2693 2694 #clock-cells = <0>; 2695 clock-output-names = "fsgen"; 2696 #sound-dai-cells = <1>; 2697 }; 2698 2699 rxmacro: rxmacro@3200000 { 2700 pinctrl-names = "default"; 2701 pinctrl-0 = <&rx_swr_active>; 2702 compatible = "qcom,sm8250-lpass-rx-macro"; 2703 reg = <0 0x03200000 0 0x1000>; 2704 status = "disabled"; 2705 2706 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2707 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2708 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2709 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2710 <&vamacro>; 2711 2712 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2713 2714 #clock-cells = <0>; 2715 clock-output-names = "mclk"; 2716 #sound-dai-cells = <1>; 2717 }; 2718 2719 swr1: soundwire@3210000 { 2720 reg = <0 0x03210000 0 0x2000>; 2721 compatible = "qcom,soundwire-v1.5.1"; 2722 status = "disabled"; 2723 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 2724 clocks = <&rxmacro>; 2725 clock-names = "iface"; 2726 label = "RX"; 2727 qcom,din-ports = <0>; 2728 qcom,dout-ports = <5>; 2729 2730 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2731 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; 2732 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2733 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2734 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2735 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2736 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2737 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2738 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2739 2740 #sound-dai-cells = <1>; 2741 #address-cells = <2>; 2742 #size-cells = <0>; 2743 }; 2744 2745 txmacro: txmacro@3220000 { 2746 pinctrl-names = "default"; 2747 pinctrl-0 = <&tx_swr_active>; 2748 compatible = "qcom,sm8250-lpass-tx-macro"; 2749 reg = <0 0x03220000 0 0x1000>; 2750 status = "disabled"; 2751 2752 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2753 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2754 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2755 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2756 <&vamacro>; 2757 2758 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2759 2760 #clock-cells = <0>; 2761 clock-output-names = "mclk"; 2762 #sound-dai-cells = <1>; 2763 }; 2764 2765 /* tx macro */ 2766 swr2: soundwire@3230000 { 2767 reg = <0 0x03230000 0 0x2000>; 2768 compatible = "qcom,soundwire-v1.5.1"; 2769 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 2770 interrupt-names = "core"; 2771 status = "disabled"; 2772 2773 clocks = <&txmacro>; 2774 clock-names = "iface"; 2775 label = "TX"; 2776 2777 qcom,din-ports = <5>; 2778 qcom,dout-ports = <0>; 2779 qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>; 2780 qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>; 2781 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>; 2782 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2783 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2784 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2785 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2786 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2787 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>; 2788 #sound-dai-cells = <1>; 2789 #address-cells = <2>; 2790 #size-cells = <0>; 2791 }; 2792 2793 aoncc: clock-controller@3380000 { 2794 compatible = "qcom,sm8250-lpass-aoncc"; 2795 reg = <0 0x03380000 0 0x40000>; 2796 #clock-cells = <1>; 2797 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2798 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2799 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2800 clock-names = "core", "audio", "bus"; 2801 }; 2802 2803 lpass_tlmm: pinctrl@33c0000 { 2804 compatible = "qcom,sm8250-lpass-lpi-pinctrl"; 2805 reg = <0 0x033c0000 0x0 0x20000>, 2806 <0 0x03550000 0x0 0x10000>; 2807 gpio-controller; 2808 #gpio-cells = <2>; 2809 gpio-ranges = <&lpass_tlmm 0 0 14>; 2810 2811 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2812 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2813 clock-names = "core", "audio"; 2814 2815 wsa_swr_active: wsa-swr-active-state { 2816 clk-pins { 2817 pins = "gpio10"; 2818 function = "wsa_swr_clk"; 2819 drive-strength = <2>; 2820 slew-rate = <1>; 2821 bias-disable; 2822 }; 2823 2824 data-pins { 2825 pins = "gpio11"; 2826 function = "wsa_swr_data"; 2827 drive-strength = <2>; 2828 slew-rate = <1>; 2829 bias-bus-hold; 2830 }; 2831 }; 2832 2833 wsa_swr_sleep: wsa-swr-sleep-state { 2834 clk-pins { 2835 pins = "gpio10"; 2836 function = "wsa_swr_clk"; 2837 drive-strength = <2>; 2838 bias-pull-down; 2839 }; 2840 2841 data-pins { 2842 pins = "gpio11"; 2843 function = "wsa_swr_data"; 2844 drive-strength = <2>; 2845 bias-pull-down; 2846 }; 2847 }; 2848 2849 dmic01_active: dmic01-active-state { 2850 clk-pins { 2851 pins = "gpio6"; 2852 function = "dmic1_clk"; 2853 drive-strength = <8>; 2854 output-high; 2855 }; 2856 data-pins { 2857 pins = "gpio7"; 2858 function = "dmic1_data"; 2859 drive-strength = <8>; 2860 }; 2861 }; 2862 2863 dmic01_sleep: dmic01-sleep-state { 2864 clk-pins { 2865 pins = "gpio6"; 2866 function = "dmic1_clk"; 2867 drive-strength = <2>; 2868 bias-disable; 2869 output-low; 2870 }; 2871 2872 data-pins { 2873 pins = "gpio7"; 2874 function = "dmic1_data"; 2875 drive-strength = <2>; 2876 bias-pull-down; 2877 }; 2878 }; 2879 2880 rx_swr_active: rx-swr-active-state { 2881 clk-pins { 2882 pins = "gpio3"; 2883 function = "swr_rx_clk"; 2884 drive-strength = <2>; 2885 slew-rate = <1>; 2886 bias-disable; 2887 }; 2888 2889 data-pins { 2890 pins = "gpio4", "gpio5"; 2891 function = "swr_rx_data"; 2892 drive-strength = <2>; 2893 slew-rate = <1>; 2894 bias-bus-hold; 2895 }; 2896 }; 2897 2898 tx_swr_active: tx-swr-active-state { 2899 clk-pins { 2900 pins = "gpio0"; 2901 function = "swr_tx_clk"; 2902 drive-strength = <2>; 2903 slew-rate = <1>; 2904 bias-disable; 2905 }; 2906 2907 data-pins { 2908 pins = "gpio1", "gpio2"; 2909 function = "swr_tx_data"; 2910 drive-strength = <2>; 2911 slew-rate = <1>; 2912 bias-bus-hold; 2913 }; 2914 }; 2915 2916 tx_swr_sleep: tx-swr-sleep-state { 2917 clk-pins { 2918 pins = "gpio0"; 2919 function = "swr_tx_clk"; 2920 drive-strength = <2>; 2921 bias-pull-down; 2922 }; 2923 2924 data1-pins { 2925 pins = "gpio1"; 2926 function = "swr_tx_data"; 2927 drive-strength = <2>; 2928 bias-bus-hold; 2929 }; 2930 2931 data2-pins { 2932 pins = "gpio2"; 2933 function = "swr_tx_data"; 2934 drive-strength = <2>; 2935 bias-pull-down; 2936 }; 2937 }; 2938 }; 2939 2940 gpu: gpu@3d00000 { 2941 compatible = "qcom,adreno-650.2", 2942 "qcom,adreno"; 2943 2944 reg = <0 0x03d00000 0 0x40000>; 2945 reg-names = "kgsl_3d0_reg_memory"; 2946 2947 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2948 2949 iommus = <&adreno_smmu 0 0x401>; 2950 2951 operating-points-v2 = <&gpu_opp_table>; 2952 2953 qcom,gmu = <&gmu>; 2954 2955 nvmem-cells = <&gpu_speed_bin>; 2956 nvmem-cell-names = "speed_bin"; 2957 #cooling-cells = <2>; 2958 2959 status = "disabled"; 2960 2961 zap-shader { 2962 memory-region = <&gpu_mem>; 2963 }; 2964 2965 gpu_opp_table: opp-table { 2966 compatible = "operating-points-v2"; 2967 2968 opp-670000000 { 2969 opp-hz = /bits/ 64 <670000000>; 2970 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2971 opp-supported-hw = <0xa>; 2972 }; 2973 2974 opp-587000000 { 2975 opp-hz = /bits/ 64 <587000000>; 2976 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2977 opp-supported-hw = <0xb>; 2978 }; 2979 2980 opp-525000000 { 2981 opp-hz = /bits/ 64 <525000000>; 2982 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2983 opp-supported-hw = <0xf>; 2984 }; 2985 2986 opp-490000000 { 2987 opp-hz = /bits/ 64 <490000000>; 2988 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2989 opp-supported-hw = <0xf>; 2990 }; 2991 2992 opp-441600000 { 2993 opp-hz = /bits/ 64 <441600000>; 2994 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2995 opp-supported-hw = <0xf>; 2996 }; 2997 2998 opp-400000000 { 2999 opp-hz = /bits/ 64 <400000000>; 3000 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3001 opp-supported-hw = <0xf>; 3002 }; 3003 3004 opp-305000000 { 3005 opp-hz = /bits/ 64 <305000000>; 3006 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3007 opp-supported-hw = <0xf>; 3008 }; 3009 }; 3010 }; 3011 3012 gmu: gmu@3d6a000 { 3013 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; 3014 3015 reg = <0 0x03d6a000 0 0x30000>, 3016 <0 0x3de0000 0 0x10000>, 3017 <0 0xb290000 0 0x10000>, 3018 <0 0xb490000 0 0x10000>; 3019 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; 3020 3021 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 3022 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 3023 interrupt-names = "hfi", "gmu"; 3024 3025 clocks = <&gpucc GPU_CC_AHB_CLK>, 3026 <&gpucc GPU_CC_CX_GMU_CLK>, 3027 <&gpucc GPU_CC_CXO_CLK>, 3028 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 3029 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 3030 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 3031 3032 power-domains = <&gpucc GPU_CX_GDSC>, 3033 <&gpucc GPU_GX_GDSC>; 3034 power-domain-names = "cx", "gx"; 3035 3036 iommus = <&adreno_smmu 5 0x400>; 3037 3038 operating-points-v2 = <&gmu_opp_table>; 3039 3040 status = "disabled"; 3041 3042 gmu_opp_table: opp-table { 3043 compatible = "operating-points-v2"; 3044 3045 opp-200000000 { 3046 opp-hz = /bits/ 64 <200000000>; 3047 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3048 }; 3049 }; 3050 }; 3051 3052 gpucc: clock-controller@3d90000 { 3053 compatible = "qcom,sm8250-gpucc"; 3054 reg = <0 0x03d90000 0 0x9000>; 3055 clocks = <&rpmhcc RPMH_CXO_CLK>, 3056 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3057 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3058 clock-names = "bi_tcxo", 3059 "gcc_gpu_gpll0_clk_src", 3060 "gcc_gpu_gpll0_div_clk_src"; 3061 #clock-cells = <1>; 3062 #reset-cells = <1>; 3063 #power-domain-cells = <1>; 3064 }; 3065 3066 adreno_smmu: iommu@3da0000 { 3067 compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu", 3068 "qcom,smmu-500", "arm,mmu-500"; 3069 reg = <0 0x03da0000 0 0x10000>; 3070 #iommu-cells = <2>; 3071 #global-interrupts = <2>; 3072 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 3073 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 3074 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 3075 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 3076 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 3077 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 3078 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 3079 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 3080 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 3081 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; 3082 clocks = <&gpucc GPU_CC_AHB_CLK>, 3083 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3084 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 3085 clock-names = "ahb", "bus", "iface"; 3086 3087 power-domains = <&gpucc GPU_CX_GDSC>; 3088 dma-coherent; 3089 }; 3090 3091 slpi: remoteproc@5c00000 { 3092 compatible = "qcom,sm8250-slpi-pas"; 3093 reg = <0 0x05c00000 0 0x4000>; 3094 3095 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 3096 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 3097 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 3098 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 3099 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 3100 interrupt-names = "wdog", "fatal", "ready", 3101 "handover", "stop-ack"; 3102 3103 clocks = <&rpmhcc RPMH_CXO_CLK>; 3104 clock-names = "xo"; 3105 3106 power-domains = <&rpmhpd RPMHPD_LCX>, 3107 <&rpmhpd RPMHPD_LMX>; 3108 power-domain-names = "lcx", "lmx"; 3109 3110 memory-region = <&slpi_mem>; 3111 3112 qcom,qmp = <&aoss_qmp>; 3113 3114 qcom,smem-states = <&smp2p_slpi_out 0>; 3115 qcom,smem-state-names = "stop"; 3116 3117 status = "disabled"; 3118 3119 glink-edge { 3120 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 3121 IPCC_MPROC_SIGNAL_GLINK_QMP 3122 IRQ_TYPE_EDGE_RISING>; 3123 mboxes = <&ipcc IPCC_CLIENT_SLPI 3124 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3125 3126 label = "slpi"; 3127 qcom,remote-pid = <3>; 3128 3129 fastrpc { 3130 compatible = "qcom,fastrpc"; 3131 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3132 label = "sdsp"; 3133 qcom,non-secure-domain; 3134 #address-cells = <1>; 3135 #size-cells = <0>; 3136 3137 compute-cb@1 { 3138 compatible = "qcom,fastrpc-compute-cb"; 3139 reg = <1>; 3140 iommus = <&apps_smmu 0x0541 0x0>; 3141 }; 3142 3143 compute-cb@2 { 3144 compatible = "qcom,fastrpc-compute-cb"; 3145 reg = <2>; 3146 iommus = <&apps_smmu 0x0542 0x0>; 3147 }; 3148 3149 compute-cb@3 { 3150 compatible = "qcom,fastrpc-compute-cb"; 3151 reg = <3>; 3152 iommus = <&apps_smmu 0x0543 0x0>; 3153 /* note: shared-cb = <4> in downstream */ 3154 }; 3155 }; 3156 }; 3157 }; 3158 3159 stm@6002000 { 3160 compatible = "arm,coresight-stm", "arm,primecell"; 3161 reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>; 3162 reg-names = "stm-base", "stm-stimulus-base"; 3163 3164 clocks = <&aoss_qmp>; 3165 clock-names = "apb_pclk"; 3166 3167 out-ports { 3168 port { 3169 stm_out: endpoint { 3170 remote-endpoint = <&funnel0_in7>; 3171 }; 3172 }; 3173 }; 3174 }; 3175 3176 tpda@6004000 { 3177 compatible = "qcom,coresight-tpda", "arm,primecell"; 3178 reg = <0 0x06004000 0 0x1000>; 3179 3180 clocks = <&aoss_qmp>; 3181 clock-names = "apb_pclk"; 3182 3183 out-ports { 3184 3185 port { 3186 tpda_out_funnel_qatb: endpoint { 3187 remote-endpoint = <&funnel_qatb_in_tpda>; 3188 }; 3189 }; 3190 }; 3191 3192 in-ports { 3193 #address-cells = <1>; 3194 #size-cells = <0>; 3195 3196 port@9 { 3197 reg = <9>; 3198 tpda_9_in_tpdm_mm: endpoint { 3199 remote-endpoint = <&tpdm_mm_out_tpda9>; 3200 }; 3201 }; 3202 3203 port@17 { 3204 reg = <23>; 3205 tpda_23_in_tpdm_prng: endpoint { 3206 remote-endpoint = <&tpdm_prng_out_tpda_23>; 3207 }; 3208 }; 3209 }; 3210 }; 3211 3212 funnel@6005000 { 3213 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3214 reg = <0 0x06005000 0 0x1000>; 3215 3216 clocks = <&aoss_qmp>; 3217 clock-names = "apb_pclk"; 3218 3219 out-ports { 3220 port { 3221 funnel_qatb_out_funnel_in0: endpoint { 3222 remote-endpoint = <&funnel_in0_in_funnel_qatb>; 3223 }; 3224 }; 3225 }; 3226 3227 in-ports { 3228 port { 3229 funnel_qatb_in_tpda: endpoint { 3230 remote-endpoint = <&tpda_out_funnel_qatb>; 3231 }; 3232 }; 3233 }; 3234 }; 3235 3236 funnel@6041000 { 3237 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3238 reg = <0 0x06041000 0 0x1000>; 3239 3240 clocks = <&aoss_qmp>; 3241 clock-names = "apb_pclk"; 3242 3243 out-ports { 3244 port { 3245 funnel_in0_out_funnel_merg: endpoint { 3246 remote-endpoint = <&funnel_merg_in_funnel_in0>; 3247 }; 3248 }; 3249 }; 3250 3251 in-ports { 3252 #address-cells = <1>; 3253 #size-cells = <0>; 3254 3255 port@6 { 3256 reg = <6>; 3257 funnel_in0_in_funnel_qatb: endpoint { 3258 remote-endpoint = <&funnel_qatb_out_funnel_in0>; 3259 }; 3260 }; 3261 3262 port@7 { 3263 reg = <7>; 3264 funnel0_in7: endpoint { 3265 remote-endpoint = <&stm_out>; 3266 }; 3267 }; 3268 }; 3269 }; 3270 3271 funnel@6042000 { 3272 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3273 reg = <0 0x06042000 0 0x1000>; 3274 3275 clocks = <&aoss_qmp>; 3276 clock-names = "apb_pclk"; 3277 3278 out-ports { 3279 port { 3280 funnel_in1_out_funnel_merg: endpoint { 3281 remote-endpoint = <&funnel_merg_in_funnel_in1>; 3282 }; 3283 }; 3284 }; 3285 3286 in-ports { 3287 #address-cells = <1>; 3288 #size-cells = <0>; 3289 3290 port@4 { 3291 reg = <4>; 3292 funnel_in1_in_funnel_apss_merg: endpoint { 3293 remote-endpoint = <&funnel_apss_merg_out_funnel_in1>; 3294 }; 3295 }; 3296 }; 3297 }; 3298 3299 funnel@6045000 { 3300 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3301 reg = <0 0x06045000 0 0x1000>; 3302 3303 clocks = <&aoss_qmp>; 3304 clock-names = "apb_pclk"; 3305 3306 out-ports { 3307 port { 3308 funnel_merg_out_funnel_swao: endpoint { 3309 remote-endpoint = <&funnel_swao_in_funnel_merg>; 3310 }; 3311 }; 3312 }; 3313 3314 in-ports { 3315 #address-cells = <1>; 3316 #size-cells = <0>; 3317 3318 port@0 { 3319 reg = <0>; 3320 funnel_merg_in_funnel_in0: endpoint { 3321 remote-endpoint = <&funnel_in0_out_funnel_merg>; 3322 }; 3323 }; 3324 3325 port@1 { 3326 reg = <1>; 3327 funnel_merg_in_funnel_in1: endpoint { 3328 remote-endpoint = <&funnel_in1_out_funnel_merg>; 3329 }; 3330 }; 3331 }; 3332 }; 3333 3334 replicator@6046000 { 3335 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3336 reg = <0 0x06046000 0 0x1000>; 3337 3338 clocks = <&aoss_qmp>; 3339 clock-names = "apb_pclk"; 3340 3341 out-ports { 3342 port { 3343 replicator_out: endpoint { 3344 remote-endpoint = <&etr_in>; 3345 }; 3346 }; 3347 }; 3348 3349 in-ports { 3350 port { 3351 replicator_cx_in_swao_out: endpoint { 3352 remote-endpoint = <&replicator_swao_out_cx_in>; 3353 }; 3354 }; 3355 }; 3356 }; 3357 3358 etr@6048000 { 3359 compatible = "arm,coresight-tmc", "arm,primecell"; 3360 reg = <0 0x06048000 0 0x1000>; 3361 3362 clocks = <&aoss_qmp>; 3363 clock-names = "apb_pclk"; 3364 arm,scatter-gather; 3365 3366 in-ports { 3367 port { 3368 etr_in: endpoint { 3369 remote-endpoint = <&replicator_out>; 3370 }; 3371 }; 3372 }; 3373 }; 3374 3375 tpdm@684c000 { 3376 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3377 reg = <0 0x0684c000 0 0x1000>; 3378 3379 clocks = <&aoss_qmp>; 3380 clock-names = "apb_pclk"; 3381 3382 out-ports { 3383 port { 3384 tpdm_prng_out_tpda_23: endpoint { 3385 remote-endpoint = <&tpda_23_in_tpdm_prng>; 3386 }; 3387 }; 3388 }; 3389 }; 3390 3391 funnel@6b04000 { 3392 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3393 arm,primecell-periphid = <0x000bb908>; 3394 3395 reg = <0 0x06b04000 0 0x1000>; 3396 3397 clocks = <&aoss_qmp>; 3398 clock-names = "apb_pclk"; 3399 3400 out-ports { 3401 port { 3402 funnel_swao_out_etf: endpoint { 3403 remote-endpoint = <&etf_in_funnel_swao_out>; 3404 }; 3405 }; 3406 }; 3407 3408 in-ports { 3409 #address-cells = <1>; 3410 #size-cells = <0>; 3411 3412 port@7 { 3413 reg = <7>; 3414 funnel_swao_in_funnel_merg: endpoint { 3415 remote-endpoint = <&funnel_merg_out_funnel_swao>; 3416 }; 3417 }; 3418 }; 3419 }; 3420 3421 etf@6b05000 { 3422 compatible = "arm,coresight-tmc", "arm,primecell"; 3423 reg = <0 0x06b05000 0 0x1000>; 3424 3425 clocks = <&aoss_qmp>; 3426 clock-names = "apb_pclk"; 3427 3428 out-ports { 3429 port { 3430 etf_out: endpoint { 3431 remote-endpoint = <&replicator_in>; 3432 }; 3433 }; 3434 }; 3435 3436 in-ports { 3437 3438 port { 3439 etf_in_funnel_swao_out: endpoint { 3440 remote-endpoint = <&funnel_swao_out_etf>; 3441 }; 3442 }; 3443 }; 3444 }; 3445 3446 replicator@6b06000 { 3447 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3448 reg = <0 0x06b06000 0 0x1000>; 3449 3450 clocks = <&aoss_qmp>; 3451 clock-names = "apb_pclk"; 3452 3453 out-ports { 3454 port { 3455 replicator_swao_out_cx_in: endpoint { 3456 remote-endpoint = <&replicator_cx_in_swao_out>; 3457 }; 3458 }; 3459 }; 3460 3461 in-ports { 3462 port { 3463 replicator_in: endpoint { 3464 remote-endpoint = <&etf_out>; 3465 }; 3466 }; 3467 }; 3468 }; 3469 3470 tpdm@6c08000 { 3471 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3472 reg = <0 0x06c08000 0 0x1000>; 3473 3474 clocks = <&aoss_qmp>; 3475 clock-names = "apb_pclk"; 3476 3477 out-ports { 3478 port { 3479 tpdm_mm_out_funnel_dl_mm: endpoint { 3480 remote-endpoint = <&funnel_dl_mm_in_tpdm_mm>; 3481 }; 3482 }; 3483 }; 3484 }; 3485 3486 funnel@6c0b000 { 3487 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3488 reg = <0 0x06c0b000 0 0x1000>; 3489 3490 clocks = <&aoss_qmp>; 3491 clock-names = "apb_pclk"; 3492 3493 out-ports { 3494 port { 3495 funnel_dl_mm_out_funnel_dl_center: endpoint { 3496 remote-endpoint = <&funnel_dl_center_in_funnel_dl_mm>; 3497 }; 3498 }; 3499 }; 3500 3501 in-ports { 3502 #address-cells = <1>; 3503 #size-cells = <0>; 3504 3505 port@3 { 3506 reg = <3>; 3507 funnel_dl_mm_in_tpdm_mm: endpoint { 3508 remote-endpoint = <&tpdm_mm_out_funnel_dl_mm>; 3509 }; 3510 }; 3511 }; 3512 }; 3513 3514 funnel@6c2d000 { 3515 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3516 reg = <0 0x06c2d000 0 0x1000>; 3517 3518 clocks = <&aoss_qmp>; 3519 clock-names = "apb_pclk"; 3520 3521 out-ports { 3522 port { 3523 tpdm_mm_out_tpda9: endpoint { 3524 remote-endpoint = <&tpda_9_in_tpdm_mm>; 3525 }; 3526 }; 3527 }; 3528 3529 in-ports { 3530 #address-cells = <1>; 3531 #size-cells = <0>; 3532 3533 port@2 { 3534 reg = <2>; 3535 funnel_dl_center_in_funnel_dl_mm: endpoint { 3536 remote-endpoint = <&funnel_dl_mm_out_funnel_dl_center>; 3537 }; 3538 }; 3539 }; 3540 }; 3541 3542 etm@7040000 { 3543 compatible = "arm,coresight-etm4x", "arm,primecell"; 3544 reg = <0 0x07040000 0 0x1000>; 3545 3546 cpu = <&CPU0>; 3547 3548 clocks = <&aoss_qmp>; 3549 clock-names = "apb_pclk"; 3550 arm,coresight-loses-context-with-cpu; 3551 3552 out-ports { 3553 port { 3554 etm0_out: endpoint { 3555 remote-endpoint = <&apss_funnel_in0>; 3556 }; 3557 }; 3558 }; 3559 }; 3560 3561 etm@7140000 { 3562 compatible = "arm,coresight-etm4x", "arm,primecell"; 3563 reg = <0 0x07140000 0 0x1000>; 3564 3565 cpu = <&CPU1>; 3566 3567 clocks = <&aoss_qmp>; 3568 clock-names = "apb_pclk"; 3569 arm,coresight-loses-context-with-cpu; 3570 3571 out-ports { 3572 port { 3573 etm1_out: endpoint { 3574 remote-endpoint = <&apss_funnel_in1>; 3575 }; 3576 }; 3577 }; 3578 }; 3579 3580 etm@7240000 { 3581 compatible = "arm,coresight-etm4x", "arm,primecell"; 3582 reg = <0 0x07240000 0 0x1000>; 3583 3584 cpu = <&CPU2>; 3585 3586 clocks = <&aoss_qmp>; 3587 clock-names = "apb_pclk"; 3588 arm,coresight-loses-context-with-cpu; 3589 3590 out-ports { 3591 port { 3592 etm2_out: endpoint { 3593 remote-endpoint = <&apss_funnel_in2>; 3594 }; 3595 }; 3596 }; 3597 }; 3598 3599 etm@7340000 { 3600 compatible = "arm,coresight-etm4x", "arm,primecell"; 3601 reg = <0 0x07340000 0 0x1000>; 3602 3603 cpu = <&CPU3>; 3604 3605 clocks = <&aoss_qmp>; 3606 clock-names = "apb_pclk"; 3607 arm,coresight-loses-context-with-cpu; 3608 3609 out-ports { 3610 port { 3611 etm3_out: endpoint { 3612 remote-endpoint = <&apss_funnel_in3>; 3613 }; 3614 }; 3615 }; 3616 }; 3617 3618 etm@7440000 { 3619 compatible = "arm,coresight-etm4x", "arm,primecell"; 3620 reg = <0 0x07440000 0 0x1000>; 3621 3622 cpu = <&CPU4>; 3623 3624 clocks = <&aoss_qmp>; 3625 clock-names = "apb_pclk"; 3626 arm,coresight-loses-context-with-cpu; 3627 3628 out-ports { 3629 port { 3630 etm4_out: endpoint { 3631 remote-endpoint = <&apss_funnel_in4>; 3632 }; 3633 }; 3634 }; 3635 }; 3636 3637 etm@7540000 { 3638 compatible = "arm,coresight-etm4x", "arm,primecell"; 3639 reg = <0 0x07540000 0 0x1000>; 3640 3641 cpu = <&CPU5>; 3642 3643 clocks = <&aoss_qmp>; 3644 clock-names = "apb_pclk"; 3645 arm,coresight-loses-context-with-cpu; 3646 3647 out-ports { 3648 port { 3649 etm5_out: endpoint { 3650 remote-endpoint = <&apss_funnel_in5>; 3651 }; 3652 }; 3653 }; 3654 }; 3655 3656 etm@7640000 { 3657 compatible = "arm,coresight-etm4x", "arm,primecell"; 3658 reg = <0 0x07640000 0 0x1000>; 3659 3660 cpu = <&CPU6>; 3661 3662 clocks = <&aoss_qmp>; 3663 clock-names = "apb_pclk"; 3664 arm,coresight-loses-context-with-cpu; 3665 3666 out-ports { 3667 port { 3668 etm6_out: endpoint { 3669 remote-endpoint = <&apss_funnel_in6>; 3670 }; 3671 }; 3672 }; 3673 }; 3674 3675 etm@7740000 { 3676 compatible = "arm,coresight-etm4x", "arm,primecell"; 3677 reg = <0 0x07740000 0 0x1000>; 3678 3679 cpu = <&CPU7>; 3680 3681 clocks = <&aoss_qmp>; 3682 clock-names = "apb_pclk"; 3683 arm,coresight-loses-context-with-cpu; 3684 3685 out-ports { 3686 port { 3687 etm7_out: endpoint { 3688 remote-endpoint = <&apss_funnel_in7>; 3689 }; 3690 }; 3691 }; 3692 }; 3693 3694 funnel@7800000 { 3695 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3696 reg = <0 0x07800000 0 0x1000>; 3697 3698 clocks = <&aoss_qmp>; 3699 clock-names = "apb_pclk"; 3700 3701 out-ports { 3702 port { 3703 funnel_apss_out_funnel_apss_merg: endpoint { 3704 remote-endpoint = <&funnel_apss_merg_in_funnel_apss>; 3705 }; 3706 }; 3707 }; 3708 3709 in-ports { 3710 #address-cells = <1>; 3711 #size-cells = <0>; 3712 3713 port@0 { 3714 reg = <0>; 3715 apss_funnel_in0: endpoint { 3716 remote-endpoint = <&etm0_out>; 3717 }; 3718 }; 3719 3720 port@1 { 3721 reg = <1>; 3722 apss_funnel_in1: endpoint { 3723 remote-endpoint = <&etm1_out>; 3724 }; 3725 }; 3726 3727 port@2 { 3728 reg = <2>; 3729 apss_funnel_in2: endpoint { 3730 remote-endpoint = <&etm2_out>; 3731 }; 3732 }; 3733 3734 port@3 { 3735 reg = <3>; 3736 apss_funnel_in3: endpoint { 3737 remote-endpoint = <&etm3_out>; 3738 }; 3739 }; 3740 3741 port@4 { 3742 reg = <4>; 3743 apss_funnel_in4: endpoint { 3744 remote-endpoint = <&etm4_out>; 3745 }; 3746 }; 3747 3748 port@5 { 3749 reg = <5>; 3750 apss_funnel_in5: endpoint { 3751 remote-endpoint = <&etm5_out>; 3752 }; 3753 }; 3754 3755 port@6 { 3756 reg = <6>; 3757 apss_funnel_in6: endpoint { 3758 remote-endpoint = <&etm6_out>; 3759 }; 3760 }; 3761 3762 port@7 { 3763 reg = <7>; 3764 apss_funnel_in7: endpoint { 3765 remote-endpoint = <&etm7_out>; 3766 }; 3767 }; 3768 }; 3769 }; 3770 3771 funnel@7810000 { 3772 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3773 reg = <0 0x07810000 0 0x1000>; 3774 3775 clocks = <&aoss_qmp>; 3776 clock-names = "apb_pclk"; 3777 3778 out-ports { 3779 port { 3780 funnel_apss_merg_out_funnel_in1: endpoint { 3781 remote-endpoint = <&funnel_in1_in_funnel_apss_merg>; 3782 }; 3783 }; 3784 }; 3785 3786 in-ports { 3787 port { 3788 funnel_apss_merg_in_funnel_apss: endpoint { 3789 remote-endpoint = <&funnel_apss_out_funnel_apss_merg>; 3790 }; 3791 }; 3792 }; 3793 }; 3794 3795 cdsp: remoteproc@8300000 { 3796 compatible = "qcom,sm8250-cdsp-pas"; 3797 reg = <0 0x08300000 0 0x10000>; 3798 3799 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3800 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3801 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3802 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3803 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3804 interrupt-names = "wdog", "fatal", "ready", 3805 "handover", "stop-ack"; 3806 3807 clocks = <&rpmhcc RPMH_CXO_CLK>; 3808 clock-names = "xo"; 3809 3810 power-domains = <&rpmhpd RPMHPD_CX>; 3811 3812 memory-region = <&cdsp_mem>; 3813 3814 qcom,qmp = <&aoss_qmp>; 3815 3816 qcom,smem-states = <&smp2p_cdsp_out 0>; 3817 qcom,smem-state-names = "stop"; 3818 3819 status = "disabled"; 3820 3821 glink-edge { 3822 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3823 IPCC_MPROC_SIGNAL_GLINK_QMP 3824 IRQ_TYPE_EDGE_RISING>; 3825 mboxes = <&ipcc IPCC_CLIENT_CDSP 3826 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3827 3828 label = "cdsp"; 3829 qcom,remote-pid = <5>; 3830 3831 fastrpc { 3832 compatible = "qcom,fastrpc"; 3833 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3834 label = "cdsp"; 3835 qcom,non-secure-domain; 3836 #address-cells = <1>; 3837 #size-cells = <0>; 3838 3839 compute-cb@1 { 3840 compatible = "qcom,fastrpc-compute-cb"; 3841 reg = <1>; 3842 iommus = <&apps_smmu 0x1001 0x0460>; 3843 }; 3844 3845 compute-cb@2 { 3846 compatible = "qcom,fastrpc-compute-cb"; 3847 reg = <2>; 3848 iommus = <&apps_smmu 0x1002 0x0460>; 3849 }; 3850 3851 compute-cb@3 { 3852 compatible = "qcom,fastrpc-compute-cb"; 3853 reg = <3>; 3854 iommus = <&apps_smmu 0x1003 0x0460>; 3855 }; 3856 3857 compute-cb@4 { 3858 compatible = "qcom,fastrpc-compute-cb"; 3859 reg = <4>; 3860 iommus = <&apps_smmu 0x1004 0x0460>; 3861 }; 3862 3863 compute-cb@5 { 3864 compatible = "qcom,fastrpc-compute-cb"; 3865 reg = <5>; 3866 iommus = <&apps_smmu 0x1005 0x0460>; 3867 }; 3868 3869 compute-cb@6 { 3870 compatible = "qcom,fastrpc-compute-cb"; 3871 reg = <6>; 3872 iommus = <&apps_smmu 0x1006 0x0460>; 3873 }; 3874 3875 compute-cb@7 { 3876 compatible = "qcom,fastrpc-compute-cb"; 3877 reg = <7>; 3878 iommus = <&apps_smmu 0x1007 0x0460>; 3879 }; 3880 3881 compute-cb@8 { 3882 compatible = "qcom,fastrpc-compute-cb"; 3883 reg = <8>; 3884 iommus = <&apps_smmu 0x1008 0x0460>; 3885 }; 3886 3887 /* note: secure cb9 in downstream */ 3888 }; 3889 }; 3890 }; 3891 3892 usb_1_hsphy: phy@88e3000 { 3893 compatible = "qcom,sm8250-usb-hs-phy", 3894 "qcom,usb-snps-hs-7nm-phy"; 3895 reg = <0 0x088e3000 0 0x400>; 3896 status = "disabled"; 3897 #phy-cells = <0>; 3898 3899 clocks = <&rpmhcc RPMH_CXO_CLK>; 3900 clock-names = "ref"; 3901 3902 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3903 }; 3904 3905 usb_2_hsphy: phy@88e4000 { 3906 compatible = "qcom,sm8250-usb-hs-phy", 3907 "qcom,usb-snps-hs-7nm-phy"; 3908 reg = <0 0x088e4000 0 0x400>; 3909 status = "disabled"; 3910 #phy-cells = <0>; 3911 3912 clocks = <&rpmhcc RPMH_CXO_CLK>; 3913 clock-names = "ref"; 3914 3915 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3916 }; 3917 3918 usb_1_qmpphy: phy@88e8000 { 3919 compatible = "qcom,sm8250-qmp-usb3-dp-phy"; 3920 reg = <0 0x088e8000 0 0x3000>; 3921 status = "disabled"; 3922 3923 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3924 <&rpmhcc RPMH_CXO_CLK>, 3925 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3926 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3927 clock-names = "aux", 3928 "ref", 3929 "com_aux", 3930 "usb3_pipe"; 3931 3932 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3933 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3934 reset-names = "phy", "common"; 3935 3936 #clock-cells = <1>; 3937 #phy-cells = <1>; 3938 3939 ports { 3940 #address-cells = <1>; 3941 #size-cells = <0>; 3942 3943 port@0 { 3944 reg = <0>; 3945 usb_1_qmpphy_out: endpoint {}; 3946 }; 3947 3948 port@1 { 3949 reg = <1>; 3950 }; 3951 3952 port@2 { 3953 reg = <2>; 3954 3955 usb_1_qmpphy_dp_in: endpoint {}; 3956 }; 3957 }; 3958 }; 3959 3960 usb_2_qmpphy: phy@88eb000 { 3961 compatible = "qcom,sm8250-qmp-usb3-uni-phy"; 3962 reg = <0 0x088eb000 0 0x1000>; 3963 3964 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3965 <&gcc GCC_USB3_SEC_CLKREF_EN>, 3966 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 3967 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3968 clock-names = "aux", 3969 "ref", 3970 "com_aux", 3971 "pipe"; 3972 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3973 #clock-cells = <0>; 3974 #phy-cells = <0>; 3975 3976 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 3977 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 3978 reset-names = "phy", 3979 "phy_phy"; 3980 3981 status = "disabled"; 3982 }; 3983 3984 sdhc_2: mmc@8804000 { 3985 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; 3986 reg = <0 0x08804000 0 0x1000>; 3987 3988 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3989 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3990 interrupt-names = "hc_irq", "pwr_irq"; 3991 3992 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3993 <&gcc GCC_SDCC2_APPS_CLK>, 3994 <&rpmhcc RPMH_CXO_CLK>; 3995 clock-names = "iface", "core", "xo"; 3996 iommus = <&apps_smmu 0x4a0 0x0>; 3997 qcom,dll-config = <0x0007642c>; 3998 qcom,ddr-config = <0x80040868>; 3999 power-domains = <&rpmhpd RPMHPD_CX>; 4000 operating-points-v2 = <&sdhc2_opp_table>; 4001 4002 status = "disabled"; 4003 4004 sdhc2_opp_table: opp-table { 4005 compatible = "operating-points-v2"; 4006 4007 opp-19200000 { 4008 opp-hz = /bits/ 64 <19200000>; 4009 required-opps = <&rpmhpd_opp_min_svs>; 4010 }; 4011 4012 opp-50000000 { 4013 opp-hz = /bits/ 64 <50000000>; 4014 required-opps = <&rpmhpd_opp_low_svs>; 4015 }; 4016 4017 opp-100000000 { 4018 opp-hz = /bits/ 64 <100000000>; 4019 required-opps = <&rpmhpd_opp_svs>; 4020 }; 4021 4022 opp-202000000 { 4023 opp-hz = /bits/ 64 <202000000>; 4024 required-opps = <&rpmhpd_opp_svs_l1>; 4025 }; 4026 }; 4027 }; 4028 4029 pmu@9091000 { 4030 compatible = "qcom,sm8250-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 4031 reg = <0 0x09091000 0 0x1000>; 4032 4033 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 4034 4035 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI_CH0 3>; 4036 4037 operating-points-v2 = <&llcc_bwmon_opp_table>; 4038 4039 llcc_bwmon_opp_table: opp-table { 4040 compatible = "operating-points-v2"; 4041 4042 opp-800000 { 4043 opp-peak-kBps = <(200 * 4 * 1000)>; 4044 }; 4045 4046 opp-1200000 { 4047 opp-peak-kBps = <(300 * 4 * 1000)>; 4048 }; 4049 4050 opp-1804000 { 4051 opp-peak-kBps = <(451 * 4 * 1000)>; 4052 }; 4053 4054 opp-2188000 { 4055 opp-peak-kBps = <(547 * 4 * 1000)>; 4056 }; 4057 4058 opp-2724000 { 4059 opp-peak-kBps = <(681 * 4 * 1000)>; 4060 }; 4061 4062 opp-3072000 { 4063 opp-peak-kBps = <(768 * 4 * 1000)>; 4064 }; 4065 4066 opp-4068000 { 4067 opp-peak-kBps = <(1017 * 4 * 1000)>; 4068 }; 4069 4070 /* 1353 MHz, LPDDR4X */ 4071 4072 opp-6220000 { 4073 opp-peak-kBps = <(1555 * 4 * 1000)>; 4074 }; 4075 4076 opp-7216000 { 4077 opp-peak-kBps = <(1804 * 4 * 1000)>; 4078 }; 4079 4080 opp-8368000 { 4081 opp-peak-kBps = <(2092 * 4 * 1000)>; 4082 }; 4083 4084 /* LPDDR5 */ 4085 opp-10944000 { 4086 opp-peak-kBps = <(2736 * 4 * 1000)>; 4087 }; 4088 }; 4089 }; 4090 4091 pmu@90b6400 { 4092 compatible = "qcom,sm8250-cpu-bwmon", "qcom,sdm845-bwmon"; 4093 reg = <0 0x090b6400 0 0x600>; 4094 4095 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4096 4097 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &gem_noc SLAVE_LLCC 3>; 4098 operating-points-v2 = <&cpu_bwmon_opp_table>; 4099 4100 cpu_bwmon_opp_table: opp-table { 4101 compatible = "operating-points-v2"; 4102 4103 opp-800000 { 4104 opp-peak-kBps = <(200 * 4 * 1000)>; 4105 }; 4106 4107 opp-1804000 { 4108 opp-peak-kBps = <(451 * 4 * 1000)>; 4109 }; 4110 4111 opp-2188000 { 4112 opp-peak-kBps = <(547 * 4 * 1000)>; 4113 }; 4114 4115 opp-2724000 { 4116 opp-peak-kBps = <(681 * 4 * 1000)>; 4117 }; 4118 4119 opp-3072000 { 4120 opp-peak-kBps = <(768 * 4 * 1000)>; 4121 }; 4122 4123 /* 1017MHz, 1353 MHz, LPDDR4X */ 4124 4125 opp-6220000 { 4126 opp-peak-kBps = <(1555 * 4 * 1000)>; 4127 }; 4128 4129 opp-6832000 { 4130 opp-peak-kBps = <(1708 * 4 * 1000)>; 4131 }; 4132 4133 opp-8368000 { 4134 opp-peak-kBps = <(2092 * 4 * 1000)>; 4135 }; 4136 4137 /* 2133MHz, LPDDR4X */ 4138 4139 /* LPDDR5 */ 4140 opp-10944000 { 4141 opp-peak-kBps = <(2736 * 4 * 1000)>; 4142 }; 4143 4144 /* LPDDR5 */ 4145 opp-12784000 { 4146 opp-peak-kBps = <(3196 * 4 * 1000)>; 4147 }; 4148 }; 4149 }; 4150 4151 dc_noc: interconnect@90c0000 { 4152 compatible = "qcom,sm8250-dc-noc"; 4153 reg = <0 0x090c0000 0 0x4200>; 4154 #interconnect-cells = <2>; 4155 qcom,bcm-voters = <&apps_bcm_voter>; 4156 }; 4157 4158 gem_noc: interconnect@9100000 { 4159 compatible = "qcom,sm8250-gem-noc"; 4160 reg = <0 0x09100000 0 0xb4000>; 4161 #interconnect-cells = <2>; 4162 qcom,bcm-voters = <&apps_bcm_voter>; 4163 }; 4164 4165 npu_noc: interconnect@9990000 { 4166 compatible = "qcom,sm8250-npu-noc"; 4167 reg = <0 0x09990000 0 0x1600>; 4168 #interconnect-cells = <2>; 4169 qcom,bcm-voters = <&apps_bcm_voter>; 4170 }; 4171 4172 usb_1: usb@a6f8800 { 4173 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 4174 reg = <0 0x0a6f8800 0 0x400>; 4175 status = "disabled"; 4176 #address-cells = <2>; 4177 #size-cells = <2>; 4178 ranges; 4179 dma-ranges; 4180 4181 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4182 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4183 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4184 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4185 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4186 <&gcc GCC_USB3_SEC_CLKREF_EN>; 4187 clock-names = "cfg_noc", 4188 "core", 4189 "iface", 4190 "sleep", 4191 "mock_utmi", 4192 "xo"; 4193 4194 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4195 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4196 assigned-clock-rates = <19200000>, <200000000>; 4197 4198 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4199 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4200 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4201 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4202 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 4203 interrupt-names = "pwr_event", 4204 "hs_phy_irq", 4205 "dp_hs_phy_irq", 4206 "dm_hs_phy_irq", 4207 "ss_phy_irq"; 4208 4209 power-domains = <&gcc USB30_PRIM_GDSC>; 4210 wakeup-source; 4211 4212 resets = <&gcc GCC_USB30_PRIM_BCR>; 4213 4214 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, 4215 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 4216 interconnect-names = "usb-ddr", "apps-usb"; 4217 4218 usb_1_dwc3: usb@a600000 { 4219 compatible = "snps,dwc3"; 4220 reg = <0 0x0a600000 0 0xcd00>; 4221 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4222 iommus = <&apps_smmu 0x0 0x0>; 4223 snps,dis_u2_susphy_quirk; 4224 snps,dis_enblslpm_quirk; 4225 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4226 phy-names = "usb2-phy", "usb3-phy"; 4227 4228 port { 4229 usb_1_role_switch_out: endpoint {}; 4230 }; 4231 }; 4232 }; 4233 4234 system-cache-controller@9200000 { 4235 compatible = "qcom,sm8250-llcc"; 4236 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, 4237 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, 4238 <0 0x09600000 0 0x50000>; 4239 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 4240 "llcc3_base", "llcc_broadcast_base"; 4241 }; 4242 4243 usb_2: usb@a8f8800 { 4244 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 4245 reg = <0 0x0a8f8800 0 0x400>; 4246 status = "disabled"; 4247 #address-cells = <2>; 4248 #size-cells = <2>; 4249 ranges; 4250 dma-ranges; 4251 4252 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4253 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4254 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4255 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4256 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4257 <&gcc GCC_USB3_SEC_CLKREF_EN>; 4258 clock-names = "cfg_noc", 4259 "core", 4260 "iface", 4261 "sleep", 4262 "mock_utmi", 4263 "xo"; 4264 4265 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4266 <&gcc GCC_USB30_SEC_MASTER_CLK>; 4267 assigned-clock-rates = <19200000>, <200000000>; 4268 4269 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 4270 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 4271 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 4272 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 4273 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 4274 interrupt-names = "pwr_event", 4275 "hs_phy_irq", 4276 "dp_hs_phy_irq", 4277 "dm_hs_phy_irq", 4278 "ss_phy_irq"; 4279 4280 power-domains = <&gcc USB30_SEC_GDSC>; 4281 wakeup-source; 4282 4283 resets = <&gcc GCC_USB30_SEC_BCR>; 4284 4285 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, 4286 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; 4287 interconnect-names = "usb-ddr", "apps-usb"; 4288 4289 usb_2_dwc3: usb@a800000 { 4290 compatible = "snps,dwc3"; 4291 reg = <0 0x0a800000 0 0xcd00>; 4292 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 4293 iommus = <&apps_smmu 0x20 0>; 4294 snps,dis_u2_susphy_quirk; 4295 snps,dis_enblslpm_quirk; 4296 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>; 4297 phy-names = "usb2-phy", "usb3-phy"; 4298 }; 4299 }; 4300 4301 venus: video-codec@aa00000 { 4302 compatible = "qcom,sm8250-venus"; 4303 reg = <0 0x0aa00000 0 0x100000>; 4304 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4305 power-domains = <&videocc MVS0C_GDSC>, 4306 <&videocc MVS0_GDSC>, 4307 <&rpmhpd RPMHPD_MX>; 4308 power-domain-names = "venus", "vcodec0", "mx"; 4309 operating-points-v2 = <&venus_opp_table>; 4310 4311 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 4312 <&videocc VIDEO_CC_MVS0C_CLK>, 4313 <&videocc VIDEO_CC_MVS0_CLK>; 4314 clock-names = "iface", "core", "vcodec0_core"; 4315 4316 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_VENUS_CFG 0>, 4317 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI_CH0 0>; 4318 interconnect-names = "cpu-cfg", "video-mem"; 4319 4320 iommus = <&apps_smmu 0x2100 0x0400>; 4321 memory-region = <&video_mem>; 4322 4323 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 4324 <&videocc VIDEO_CC_MVS0C_CLK_ARES>; 4325 reset-names = "bus", "core"; 4326 4327 status = "disabled"; 4328 4329 video-decoder { 4330 compatible = "venus-decoder"; 4331 }; 4332 4333 video-encoder { 4334 compatible = "venus-encoder"; 4335 }; 4336 4337 venus_opp_table: opp-table { 4338 compatible = "operating-points-v2"; 4339 4340 opp-720000000 { 4341 opp-hz = /bits/ 64 <720000000>; 4342 required-opps = <&rpmhpd_opp_low_svs>; 4343 }; 4344 4345 opp-1014000000 { 4346 opp-hz = /bits/ 64 <1014000000>; 4347 required-opps = <&rpmhpd_opp_svs>; 4348 }; 4349 4350 opp-1098000000 { 4351 opp-hz = /bits/ 64 <1098000000>; 4352 required-opps = <&rpmhpd_opp_svs_l1>; 4353 }; 4354 4355 opp-1332000000 { 4356 opp-hz = /bits/ 64 <1332000000>; 4357 required-opps = <&rpmhpd_opp_nom>; 4358 }; 4359 }; 4360 }; 4361 4362 videocc: clock-controller@abf0000 { 4363 compatible = "qcom,sm8250-videocc"; 4364 reg = <0 0x0abf0000 0 0x10000>; 4365 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 4366 <&rpmhcc RPMH_CXO_CLK>, 4367 <&rpmhcc RPMH_CXO_CLK_A>; 4368 power-domains = <&rpmhpd RPMHPD_MMCX>; 4369 required-opps = <&rpmhpd_opp_low_svs>; 4370 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; 4371 #clock-cells = <1>; 4372 #reset-cells = <1>; 4373 #power-domain-cells = <1>; 4374 }; 4375 4376 cci0: cci@ac4f000 { 4377 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci"; 4378 #address-cells = <1>; 4379 #size-cells = <0>; 4380 4381 reg = <0 0x0ac4f000 0 0x1000>; 4382 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4383 power-domains = <&camcc TITAN_TOP_GDSC>; 4384 4385 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4386 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4387 <&camcc CAM_CC_CPAS_AHB_CLK>, 4388 <&camcc CAM_CC_CCI_0_CLK>, 4389 <&camcc CAM_CC_CCI_0_CLK_SRC>; 4390 clock-names = "camnoc_axi", 4391 "slow_ahb_src", 4392 "cpas_ahb", 4393 "cci", 4394 "cci_src"; 4395 4396 pinctrl-0 = <&cci0_default>; 4397 pinctrl-1 = <&cci0_sleep>; 4398 pinctrl-names = "default", "sleep"; 4399 4400 status = "disabled"; 4401 4402 cci0_i2c0: i2c-bus@0 { 4403 reg = <0>; 4404 clock-frequency = <1000000>; 4405 #address-cells = <1>; 4406 #size-cells = <0>; 4407 }; 4408 4409 cci0_i2c1: i2c-bus@1 { 4410 reg = <1>; 4411 clock-frequency = <1000000>; 4412 #address-cells = <1>; 4413 #size-cells = <0>; 4414 }; 4415 }; 4416 4417 cci1: cci@ac50000 { 4418 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci"; 4419 #address-cells = <1>; 4420 #size-cells = <0>; 4421 4422 reg = <0 0x0ac50000 0 0x1000>; 4423 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 4424 power-domains = <&camcc TITAN_TOP_GDSC>; 4425 4426 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4427 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4428 <&camcc CAM_CC_CPAS_AHB_CLK>, 4429 <&camcc CAM_CC_CCI_1_CLK>, 4430 <&camcc CAM_CC_CCI_1_CLK_SRC>; 4431 clock-names = "camnoc_axi", 4432 "slow_ahb_src", 4433 "cpas_ahb", 4434 "cci", 4435 "cci_src"; 4436 4437 pinctrl-0 = <&cci1_default>; 4438 pinctrl-1 = <&cci1_sleep>; 4439 pinctrl-names = "default", "sleep"; 4440 4441 status = "disabled"; 4442 4443 cci1_i2c0: i2c-bus@0 { 4444 reg = <0>; 4445 clock-frequency = <1000000>; 4446 #address-cells = <1>; 4447 #size-cells = <0>; 4448 }; 4449 4450 cci1_i2c1: i2c-bus@1 { 4451 reg = <1>; 4452 clock-frequency = <1000000>; 4453 #address-cells = <1>; 4454 #size-cells = <0>; 4455 }; 4456 }; 4457 4458 camss: camss@ac6a000 { 4459 compatible = "qcom,sm8250-camss"; 4460 status = "disabled"; 4461 4462 reg = <0 0x0ac6a000 0 0x2000>, 4463 <0 0x0ac6c000 0 0x2000>, 4464 <0 0x0ac6e000 0 0x1000>, 4465 <0 0x0ac70000 0 0x1000>, 4466 <0 0x0ac72000 0 0x1000>, 4467 <0 0x0ac74000 0 0x1000>, 4468 <0 0x0acb4000 0 0xd000>, 4469 <0 0x0acc3000 0 0xd000>, 4470 <0 0x0acd9000 0 0x2200>, 4471 <0 0x0acdb200 0 0x2200>; 4472 reg-names = "csiphy0", 4473 "csiphy1", 4474 "csiphy2", 4475 "csiphy3", 4476 "csiphy4", 4477 "csiphy5", 4478 "vfe0", 4479 "vfe1", 4480 "vfe_lite0", 4481 "vfe_lite1"; 4482 4483 interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, 4484 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, 4485 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, 4486 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 4487 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 4488 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 4489 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 4490 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 4491 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 4492 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 4493 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 4494 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 4495 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 4496 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 4497 interrupt-names = "csiphy0", 4498 "csiphy1", 4499 "csiphy2", 4500 "csiphy3", 4501 "csiphy4", 4502 "csiphy5", 4503 "csid0", 4504 "csid1", 4505 "csid2", 4506 "csid3", 4507 "vfe0", 4508 "vfe1", 4509 "vfe_lite0", 4510 "vfe_lite1"; 4511 4512 power-domains = <&camcc IFE_0_GDSC>, 4513 <&camcc IFE_1_GDSC>, 4514 <&camcc TITAN_TOP_GDSC>; 4515 4516 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4517 <&gcc GCC_CAMERA_HF_AXI_CLK>, 4518 <&gcc GCC_CAMERA_SF_AXI_CLK>, 4519 <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4520 <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, 4521 <&camcc CAM_CC_CORE_AHB_CLK>, 4522 <&camcc CAM_CC_CPAS_AHB_CLK>, 4523 <&camcc CAM_CC_CSIPHY0_CLK>, 4524 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 4525 <&camcc CAM_CC_CSIPHY1_CLK>, 4526 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 4527 <&camcc CAM_CC_CSIPHY2_CLK>, 4528 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 4529 <&camcc CAM_CC_CSIPHY3_CLK>, 4530 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 4531 <&camcc CAM_CC_CSIPHY4_CLK>, 4532 <&camcc CAM_CC_CSI4PHYTIMER_CLK>, 4533 <&camcc CAM_CC_CSIPHY5_CLK>, 4534 <&camcc CAM_CC_CSI5PHYTIMER_CLK>, 4535 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4536 <&camcc CAM_CC_IFE_0_AHB_CLK>, 4537 <&camcc CAM_CC_IFE_0_AXI_CLK>, 4538 <&camcc CAM_CC_IFE_0_CLK>, 4539 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 4540 <&camcc CAM_CC_IFE_0_CSID_CLK>, 4541 <&camcc CAM_CC_IFE_0_AREG_CLK>, 4542 <&camcc CAM_CC_IFE_1_AHB_CLK>, 4543 <&camcc CAM_CC_IFE_1_AXI_CLK>, 4544 <&camcc CAM_CC_IFE_1_CLK>, 4545 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 4546 <&camcc CAM_CC_IFE_1_CSID_CLK>, 4547 <&camcc CAM_CC_IFE_1_AREG_CLK>, 4548 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 4549 <&camcc CAM_CC_IFE_LITE_AXI_CLK>, 4550 <&camcc CAM_CC_IFE_LITE_CLK>, 4551 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 4552 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 4553 4554 clock-names = "cam_ahb_clk", 4555 "cam_hf_axi", 4556 "cam_sf_axi", 4557 "camnoc_axi", 4558 "camnoc_axi_src", 4559 "core_ahb", 4560 "cpas_ahb", 4561 "csiphy0", 4562 "csiphy0_timer", 4563 "csiphy1", 4564 "csiphy1_timer", 4565 "csiphy2", 4566 "csiphy2_timer", 4567 "csiphy3", 4568 "csiphy3_timer", 4569 "csiphy4", 4570 "csiphy4_timer", 4571 "csiphy5", 4572 "csiphy5_timer", 4573 "slow_ahb_src", 4574 "vfe0_ahb", 4575 "vfe0_axi", 4576 "vfe0", 4577 "vfe0_cphy_rx", 4578 "vfe0_csid", 4579 "vfe0_areg", 4580 "vfe1_ahb", 4581 "vfe1_axi", 4582 "vfe1", 4583 "vfe1_cphy_rx", 4584 "vfe1_csid", 4585 "vfe1_areg", 4586 "vfe_lite_ahb", 4587 "vfe_lite_axi", 4588 "vfe_lite", 4589 "vfe_lite_cphy_rx", 4590 "vfe_lite_csid"; 4591 4592 iommus = <&apps_smmu 0x800 0x400>, 4593 <&apps_smmu 0x801 0x400>, 4594 <&apps_smmu 0x840 0x400>, 4595 <&apps_smmu 0x841 0x400>, 4596 <&apps_smmu 0xc00 0x400>, 4597 <&apps_smmu 0xc01 0x400>, 4598 <&apps_smmu 0xc40 0x400>, 4599 <&apps_smmu 0xc41 0x400>; 4600 4601 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_CAMERA_CFG 0>, 4602 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI_CH0 0>, 4603 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI_CH0 0>, 4604 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI_CH0 0>; 4605 interconnect-names = "cam_ahb", 4606 "cam_hf_0_mnoc", 4607 "cam_sf_0_mnoc", 4608 "cam_sf_icp_mnoc"; 4609 4610 ports { 4611 #address-cells = <1>; 4612 #size-cells = <0>; 4613 4614 port@0 { 4615 reg = <0>; 4616 }; 4617 4618 port@1 { 4619 reg = <1>; 4620 }; 4621 4622 port@2 { 4623 reg = <2>; 4624 }; 4625 4626 port@3 { 4627 reg = <3>; 4628 }; 4629 4630 port@4 { 4631 reg = <4>; 4632 }; 4633 4634 port@5 { 4635 reg = <5>; 4636 }; 4637 }; 4638 }; 4639 4640 camcc: clock-controller@ad00000 { 4641 compatible = "qcom,sm8250-camcc"; 4642 reg = <0 0x0ad00000 0 0x10000>; 4643 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4644 <&rpmhcc RPMH_CXO_CLK>, 4645 <&rpmhcc RPMH_CXO_CLK_A>, 4646 <&sleep_clk>; 4647 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 4648 power-domains = <&rpmhpd RPMHPD_MMCX>; 4649 required-opps = <&rpmhpd_opp_low_svs>; 4650 status = "disabled"; 4651 #clock-cells = <1>; 4652 #reset-cells = <1>; 4653 #power-domain-cells = <1>; 4654 }; 4655 4656 mdss: display-subsystem@ae00000 { 4657 compatible = "qcom,sm8250-mdss"; 4658 reg = <0 0x0ae00000 0 0x1000>; 4659 reg-names = "mdss"; 4660 4661 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>, 4662 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>; 4663 interconnect-names = "mdp0-mem", "mdp1-mem"; 4664 4665 power-domains = <&dispcc MDSS_GDSC>; 4666 4667 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4668 <&gcc GCC_DISP_HF_AXI_CLK>, 4669 <&gcc GCC_DISP_SF_AXI_CLK>, 4670 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4671 clock-names = "iface", "bus", "nrt_bus", "core"; 4672 4673 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4674 interrupt-controller; 4675 #interrupt-cells = <1>; 4676 4677 iommus = <&apps_smmu 0x820 0x402>; 4678 4679 status = "disabled"; 4680 4681 #address-cells = <2>; 4682 #size-cells = <2>; 4683 ranges; 4684 4685 mdss_mdp: display-controller@ae01000 { 4686 compatible = "qcom,sm8250-dpu"; 4687 reg = <0 0x0ae01000 0 0x8f000>, 4688 <0 0x0aeb0000 0 0x2008>; 4689 reg-names = "mdp", "vbif"; 4690 4691 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4692 <&gcc GCC_DISP_HF_AXI_CLK>, 4693 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4694 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4695 clock-names = "iface", "bus", "core", "vsync"; 4696 4697 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4698 assigned-clock-rates = <19200000>; 4699 4700 operating-points-v2 = <&mdp_opp_table>; 4701 power-domains = <&rpmhpd RPMHPD_MMCX>; 4702 4703 interrupt-parent = <&mdss>; 4704 interrupts = <0>; 4705 4706 ports { 4707 #address-cells = <1>; 4708 #size-cells = <0>; 4709 4710 port@0 { 4711 reg = <0>; 4712 dpu_intf1_out: endpoint { 4713 remote-endpoint = <&mdss_dsi0_in>; 4714 }; 4715 }; 4716 4717 port@1 { 4718 reg = <1>; 4719 dpu_intf2_out: endpoint { 4720 remote-endpoint = <&mdss_dsi1_in>; 4721 }; 4722 }; 4723 4724 port@2 { 4725 reg = <2>; 4726 4727 dpu_intf0_out: endpoint { 4728 remote-endpoint = <&mdss_dp_in>; 4729 }; 4730 }; 4731 }; 4732 4733 mdp_opp_table: opp-table { 4734 compatible = "operating-points-v2"; 4735 4736 opp-200000000 { 4737 opp-hz = /bits/ 64 <200000000>; 4738 required-opps = <&rpmhpd_opp_low_svs>; 4739 }; 4740 4741 opp-300000000 { 4742 opp-hz = /bits/ 64 <300000000>; 4743 required-opps = <&rpmhpd_opp_svs>; 4744 }; 4745 4746 opp-345000000 { 4747 opp-hz = /bits/ 64 <345000000>; 4748 required-opps = <&rpmhpd_opp_svs_l1>; 4749 }; 4750 4751 opp-460000000 { 4752 opp-hz = /bits/ 64 <460000000>; 4753 required-opps = <&rpmhpd_opp_nom>; 4754 }; 4755 }; 4756 }; 4757 4758 mdss_dp: displayport-controller@ae90000 { 4759 compatible = "qcom,sm8250-dp", "qcom,sm8350-dp"; 4760 reg = <0 0xae90000 0 0x200>, 4761 <0 0xae90200 0 0x200>, 4762 <0 0xae90400 0 0x600>, 4763 <0 0xae91000 0 0x400>, 4764 <0 0xae91400 0 0x400>; 4765 interrupt-parent = <&mdss>; 4766 interrupts = <12>; 4767 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4768 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4769 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4770 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4771 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4772 clock-names = "core_iface", 4773 "core_aux", 4774 "ctrl_link", 4775 "ctrl_link_iface", 4776 "stream_pixel"; 4777 4778 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4779 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4780 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4781 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4782 4783 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 4784 phy-names = "dp"; 4785 4786 #sound-dai-cells = <0>; 4787 4788 operating-points-v2 = <&dp_opp_table>; 4789 power-domains = <&rpmhpd SM8250_MMCX>; 4790 4791 status = "disabled"; 4792 4793 ports { 4794 #address-cells = <1>; 4795 #size-cells = <0>; 4796 4797 port@0 { 4798 reg = <0>; 4799 mdss_dp_in: endpoint { 4800 remote-endpoint = <&dpu_intf0_out>; 4801 }; 4802 }; 4803 4804 port@1 { 4805 reg = <1>; 4806 4807 mdss_dp_out: endpoint { 4808 }; 4809 }; 4810 }; 4811 4812 dp_opp_table: opp-table { 4813 compatible = "operating-points-v2"; 4814 4815 opp-160000000 { 4816 opp-hz = /bits/ 64 <160000000>; 4817 required-opps = <&rpmhpd_opp_low_svs>; 4818 }; 4819 4820 opp-270000000 { 4821 opp-hz = /bits/ 64 <270000000>; 4822 required-opps = <&rpmhpd_opp_svs>; 4823 }; 4824 4825 opp-540000000 { 4826 opp-hz = /bits/ 64 <540000000>; 4827 required-opps = <&rpmhpd_opp_svs_l1>; 4828 }; 4829 4830 opp-810000000 { 4831 opp-hz = /bits/ 64 <810000000>; 4832 required-opps = <&rpmhpd_opp_nom>; 4833 }; 4834 }; 4835 }; 4836 4837 mdss_dsi0: dsi@ae94000 { 4838 compatible = "qcom,sm8250-dsi-ctrl", 4839 "qcom,mdss-dsi-ctrl"; 4840 reg = <0 0x0ae94000 0 0x400>; 4841 reg-names = "dsi_ctrl"; 4842 4843 interrupt-parent = <&mdss>; 4844 interrupts = <4>; 4845 4846 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4847 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4848 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4849 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4850 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4851 <&gcc GCC_DISP_HF_AXI_CLK>; 4852 clock-names = "byte", 4853 "byte_intf", 4854 "pixel", 4855 "core", 4856 "iface", 4857 "bus"; 4858 4859 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4860 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 4861 4862 operating-points-v2 = <&dsi_opp_table>; 4863 power-domains = <&rpmhpd RPMHPD_MMCX>; 4864 4865 phys = <&mdss_dsi0_phy>; 4866 4867 status = "disabled"; 4868 4869 #address-cells = <1>; 4870 #size-cells = <0>; 4871 4872 ports { 4873 #address-cells = <1>; 4874 #size-cells = <0>; 4875 4876 port@0 { 4877 reg = <0>; 4878 mdss_dsi0_in: endpoint { 4879 remote-endpoint = <&dpu_intf1_out>; 4880 }; 4881 }; 4882 4883 port@1 { 4884 reg = <1>; 4885 mdss_dsi0_out: endpoint { 4886 }; 4887 }; 4888 }; 4889 4890 dsi_opp_table: opp-table { 4891 compatible = "operating-points-v2"; 4892 4893 opp-187500000 { 4894 opp-hz = /bits/ 64 <187500000>; 4895 required-opps = <&rpmhpd_opp_low_svs>; 4896 }; 4897 4898 opp-300000000 { 4899 opp-hz = /bits/ 64 <300000000>; 4900 required-opps = <&rpmhpd_opp_svs>; 4901 }; 4902 4903 opp-358000000 { 4904 opp-hz = /bits/ 64 <358000000>; 4905 required-opps = <&rpmhpd_opp_svs_l1>; 4906 }; 4907 }; 4908 }; 4909 4910 mdss_dsi0_phy: phy@ae94400 { 4911 compatible = "qcom,dsi-phy-7nm"; 4912 reg = <0 0x0ae94400 0 0x200>, 4913 <0 0x0ae94600 0 0x280>, 4914 <0 0x0ae94900 0 0x260>; 4915 reg-names = "dsi_phy", 4916 "dsi_phy_lane", 4917 "dsi_pll"; 4918 4919 #clock-cells = <1>; 4920 #phy-cells = <0>; 4921 4922 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4923 <&rpmhcc RPMH_CXO_CLK>; 4924 clock-names = "iface", "ref"; 4925 4926 status = "disabled"; 4927 }; 4928 4929 mdss_dsi1: dsi@ae96000 { 4930 compatible = "qcom,sm8250-dsi-ctrl", 4931 "qcom,mdss-dsi-ctrl"; 4932 reg = <0 0x0ae96000 0 0x400>; 4933 reg-names = "dsi_ctrl"; 4934 4935 interrupt-parent = <&mdss>; 4936 interrupts = <5>; 4937 4938 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 4939 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 4940 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 4941 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 4942 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4943 <&gcc GCC_DISP_HF_AXI_CLK>; 4944 clock-names = "byte", 4945 "byte_intf", 4946 "pixel", 4947 "core", 4948 "iface", 4949 "bus"; 4950 4951 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 4952 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 4953 4954 operating-points-v2 = <&dsi_opp_table>; 4955 power-domains = <&rpmhpd RPMHPD_MMCX>; 4956 4957 phys = <&mdss_dsi1_phy>; 4958 4959 status = "disabled"; 4960 4961 #address-cells = <1>; 4962 #size-cells = <0>; 4963 4964 ports { 4965 #address-cells = <1>; 4966 #size-cells = <0>; 4967 4968 port@0 { 4969 reg = <0>; 4970 mdss_dsi1_in: endpoint { 4971 remote-endpoint = <&dpu_intf2_out>; 4972 }; 4973 }; 4974 4975 port@1 { 4976 reg = <1>; 4977 mdss_dsi1_out: endpoint { 4978 }; 4979 }; 4980 }; 4981 }; 4982 4983 mdss_dsi1_phy: phy@ae96400 { 4984 compatible = "qcom,dsi-phy-7nm"; 4985 reg = <0 0x0ae96400 0 0x200>, 4986 <0 0x0ae96600 0 0x280>, 4987 <0 0x0ae96900 0 0x260>; 4988 reg-names = "dsi_phy", 4989 "dsi_phy_lane", 4990 "dsi_pll"; 4991 4992 #clock-cells = <1>; 4993 #phy-cells = <0>; 4994 4995 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4996 <&rpmhcc RPMH_CXO_CLK>; 4997 clock-names = "iface", "ref"; 4998 4999 status = "disabled"; 5000 }; 5001 }; 5002 5003 dispcc: clock-controller@af00000 { 5004 compatible = "qcom,sm8250-dispcc"; 5005 reg = <0 0x0af00000 0 0x10000>; 5006 power-domains = <&rpmhpd RPMHPD_MMCX>; 5007 required-opps = <&rpmhpd_opp_low_svs>; 5008 clocks = <&rpmhcc RPMH_CXO_CLK>, 5009 <&mdss_dsi0_phy 0>, 5010 <&mdss_dsi0_phy 1>, 5011 <&mdss_dsi1_phy 0>, 5012 <&mdss_dsi1_phy 1>, 5013 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5014 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5015 clock-names = "bi_tcxo", 5016 "dsi0_phy_pll_out_byteclk", 5017 "dsi0_phy_pll_out_dsiclk", 5018 "dsi1_phy_pll_out_byteclk", 5019 "dsi1_phy_pll_out_dsiclk", 5020 "dp_phy_pll_link_clk", 5021 "dp_phy_pll_vco_div_clk"; 5022 #clock-cells = <1>; 5023 #reset-cells = <1>; 5024 #power-domain-cells = <1>; 5025 }; 5026 5027 pdc: interrupt-controller@b220000 { 5028 compatible = "qcom,sm8250-pdc", "qcom,pdc"; 5029 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 5030 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 5031 <125 63 1>, <126 716 12>; 5032 #interrupt-cells = <2>; 5033 interrupt-parent = <&intc>; 5034 interrupt-controller; 5035 }; 5036 5037 tsens0: thermal-sensor@c263000 { 5038 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 5039 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 5040 <0 0x0c222000 0 0x1ff>; /* SROT */ 5041 #qcom,sensors = <16>; 5042 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 5043 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 5044 interrupt-names = "uplow", "critical"; 5045 #thermal-sensor-cells = <1>; 5046 }; 5047 5048 tsens1: thermal-sensor@c265000 { 5049 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 5050 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 5051 <0 0x0c223000 0 0x1ff>; /* SROT */ 5052 #qcom,sensors = <9>; 5053 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 5054 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 5055 interrupt-names = "uplow", "critical"; 5056 #thermal-sensor-cells = <1>; 5057 }; 5058 5059 aoss_qmp: power-management@c300000 { 5060 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp"; 5061 reg = <0 0x0c300000 0 0x400>; 5062 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 5063 IPCC_MPROC_SIGNAL_GLINK_QMP 5064 IRQ_TYPE_EDGE_RISING>; 5065 mboxes = <&ipcc IPCC_CLIENT_AOP 5066 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5067 5068 #clock-cells = <0>; 5069 }; 5070 5071 sram@c3f0000 { 5072 compatible = "qcom,rpmh-stats"; 5073 reg = <0 0x0c3f0000 0 0x400>; 5074 }; 5075 5076 spmi_bus: spmi@c440000 { 5077 compatible = "qcom,spmi-pmic-arb"; 5078 reg = <0x0 0x0c440000 0x0 0x0001100>, 5079 <0x0 0x0c600000 0x0 0x2000000>, 5080 <0x0 0x0e600000 0x0 0x0100000>, 5081 <0x0 0x0e700000 0x0 0x00a0000>, 5082 <0x0 0x0c40a000 0x0 0x0026000>; 5083 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 5084 interrupt-names = "periph_irq"; 5085 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5086 qcom,ee = <0>; 5087 qcom,channel = <0>; 5088 #address-cells = <2>; 5089 #size-cells = <0>; 5090 interrupt-controller; 5091 #interrupt-cells = <4>; 5092 }; 5093 5094 tlmm: pinctrl@f100000 { 5095 compatible = "qcom,sm8250-pinctrl"; 5096 reg = <0 0x0f100000 0 0x300000>, 5097 <0 0x0f500000 0 0x300000>, 5098 <0 0x0f900000 0 0x300000>; 5099 reg-names = "west", "south", "north"; 5100 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 5101 gpio-controller; 5102 #gpio-cells = <2>; 5103 interrupt-controller; 5104 #interrupt-cells = <2>; 5105 gpio-ranges = <&tlmm 0 0 181>; 5106 wakeup-parent = <&pdc>; 5107 5108 cam2_default: cam2-default-state { 5109 rst-pins { 5110 pins = "gpio78"; 5111 function = "gpio"; 5112 drive-strength = <2>; 5113 bias-disable; 5114 }; 5115 5116 mclk-pins { 5117 pins = "gpio96"; 5118 function = "cam_mclk"; 5119 drive-strength = <16>; 5120 bias-disable; 5121 }; 5122 }; 5123 5124 cam2_suspend: cam2-suspend-state { 5125 rst-pins { 5126 pins = "gpio78"; 5127 function = "gpio"; 5128 drive-strength = <2>; 5129 bias-pull-down; 5130 output-low; 5131 }; 5132 5133 mclk-pins { 5134 pins = "gpio96"; 5135 function = "cam_mclk"; 5136 drive-strength = <2>; 5137 bias-disable; 5138 }; 5139 }; 5140 5141 cci0_default: cci0-default-state { 5142 cci0_i2c0_default: cci0-i2c0-default-pins { 5143 /* SDA, SCL */ 5144 pins = "gpio101", "gpio102"; 5145 function = "cci_i2c"; 5146 5147 bias-pull-up; 5148 drive-strength = <2>; /* 2 mA */ 5149 }; 5150 5151 cci0_i2c1_default: cci0-i2c1-default-pins { 5152 /* SDA, SCL */ 5153 pins = "gpio103", "gpio104"; 5154 function = "cci_i2c"; 5155 5156 bias-pull-up; 5157 drive-strength = <2>; /* 2 mA */ 5158 }; 5159 }; 5160 5161 cci0_sleep: cci0-sleep-state { 5162 cci0_i2c0_sleep: cci0-i2c0-sleep-pins { 5163 /* SDA, SCL */ 5164 pins = "gpio101", "gpio102"; 5165 function = "cci_i2c"; 5166 5167 drive-strength = <2>; /* 2 mA */ 5168 bias-pull-down; 5169 }; 5170 5171 cci0_i2c1_sleep: cci0-i2c1-sleep-pins { 5172 /* SDA, SCL */ 5173 pins = "gpio103", "gpio104"; 5174 function = "cci_i2c"; 5175 5176 drive-strength = <2>; /* 2 mA */ 5177 bias-pull-down; 5178 }; 5179 }; 5180 5181 cci1_default: cci1-default-state { 5182 cci1_i2c0_default: cci1-i2c0-default-pins { 5183 /* SDA, SCL */ 5184 pins = "gpio105","gpio106"; 5185 function = "cci_i2c"; 5186 5187 bias-pull-up; 5188 drive-strength = <2>; /* 2 mA */ 5189 }; 5190 5191 cci1_i2c1_default: cci1-i2c1-default-pins { 5192 /* SDA, SCL */ 5193 pins = "gpio107","gpio108"; 5194 function = "cci_i2c"; 5195 5196 bias-pull-up; 5197 drive-strength = <2>; /* 2 mA */ 5198 }; 5199 }; 5200 5201 cci1_sleep: cci1-sleep-state { 5202 cci1_i2c0_sleep: cci1-i2c0-sleep-pins { 5203 /* SDA, SCL */ 5204 pins = "gpio105","gpio106"; 5205 function = "cci_i2c"; 5206 5207 bias-pull-down; 5208 drive-strength = <2>; /* 2 mA */ 5209 }; 5210 5211 cci1_i2c1_sleep: cci1-i2c1-sleep-pins { 5212 /* SDA, SCL */ 5213 pins = "gpio107","gpio108"; 5214 function = "cci_i2c"; 5215 5216 bias-pull-down; 5217 drive-strength = <2>; /* 2 mA */ 5218 }; 5219 }; 5220 5221 pri_mi2s_active: pri-mi2s-active-state { 5222 sclk-pins { 5223 pins = "gpio138"; 5224 function = "mi2s0_sck"; 5225 drive-strength = <8>; 5226 bias-disable; 5227 }; 5228 5229 ws-pins { 5230 pins = "gpio141"; 5231 function = "mi2s0_ws"; 5232 drive-strength = <8>; 5233 output-high; 5234 }; 5235 5236 data0-pins { 5237 pins = "gpio139"; 5238 function = "mi2s0_data0"; 5239 drive-strength = <8>; 5240 bias-disable; 5241 output-high; 5242 }; 5243 5244 data1-pins { 5245 pins = "gpio140"; 5246 function = "mi2s0_data1"; 5247 drive-strength = <8>; 5248 output-high; 5249 }; 5250 }; 5251 5252 qup_i2c0_default: qup-i2c0-default-state { 5253 pins = "gpio28", "gpio29"; 5254 function = "qup0"; 5255 drive-strength = <2>; 5256 bias-disable; 5257 }; 5258 5259 qup_i2c1_default: qup-i2c1-default-state { 5260 pins = "gpio4", "gpio5"; 5261 function = "qup1"; 5262 drive-strength = <2>; 5263 bias-disable; 5264 }; 5265 5266 qup_i2c2_default: qup-i2c2-default-state { 5267 pins = "gpio115", "gpio116"; 5268 function = "qup2"; 5269 drive-strength = <2>; 5270 bias-disable; 5271 }; 5272 5273 qup_i2c3_default: qup-i2c3-default-state { 5274 pins = "gpio119", "gpio120"; 5275 function = "qup3"; 5276 drive-strength = <2>; 5277 bias-disable; 5278 }; 5279 5280 qup_i2c4_default: qup-i2c4-default-state { 5281 pins = "gpio8", "gpio9"; 5282 function = "qup4"; 5283 drive-strength = <2>; 5284 bias-disable; 5285 }; 5286 5287 qup_i2c5_default: qup-i2c5-default-state { 5288 pins = "gpio12", "gpio13"; 5289 function = "qup5"; 5290 drive-strength = <2>; 5291 bias-disable; 5292 }; 5293 5294 qup_i2c6_default: qup-i2c6-default-state { 5295 pins = "gpio16", "gpio17"; 5296 function = "qup6"; 5297 drive-strength = <2>; 5298 bias-disable; 5299 }; 5300 5301 qup_i2c7_default: qup-i2c7-default-state { 5302 pins = "gpio20", "gpio21"; 5303 function = "qup7"; 5304 drive-strength = <2>; 5305 bias-disable; 5306 }; 5307 5308 qup_i2c8_default: qup-i2c8-default-state { 5309 pins = "gpio24", "gpio25"; 5310 function = "qup8"; 5311 drive-strength = <2>; 5312 bias-disable; 5313 }; 5314 5315 qup_i2c9_default: qup-i2c9-default-state { 5316 pins = "gpio125", "gpio126"; 5317 function = "qup9"; 5318 drive-strength = <2>; 5319 bias-disable; 5320 }; 5321 5322 qup_i2c10_default: qup-i2c10-default-state { 5323 pins = "gpio129", "gpio130"; 5324 function = "qup10"; 5325 drive-strength = <2>; 5326 bias-disable; 5327 }; 5328 5329 qup_i2c11_default: qup-i2c11-default-state { 5330 pins = "gpio60", "gpio61"; 5331 function = "qup11"; 5332 drive-strength = <2>; 5333 bias-disable; 5334 }; 5335 5336 qup_i2c12_default: qup-i2c12-default-state { 5337 pins = "gpio32", "gpio33"; 5338 function = "qup12"; 5339 drive-strength = <2>; 5340 bias-disable; 5341 }; 5342 5343 qup_i2c13_default: qup-i2c13-default-state { 5344 pins = "gpio36", "gpio37"; 5345 function = "qup13"; 5346 drive-strength = <2>; 5347 bias-disable; 5348 }; 5349 5350 qup_i2c14_default: qup-i2c14-default-state { 5351 pins = "gpio40", "gpio41"; 5352 function = "qup14"; 5353 drive-strength = <2>; 5354 bias-disable; 5355 }; 5356 5357 qup_i2c15_default: qup-i2c15-default-state { 5358 pins = "gpio44", "gpio45"; 5359 function = "qup15"; 5360 drive-strength = <2>; 5361 bias-disable; 5362 }; 5363 5364 qup_i2c16_default: qup-i2c16-default-state { 5365 pins = "gpio48", "gpio49"; 5366 function = "qup16"; 5367 drive-strength = <2>; 5368 bias-disable; 5369 }; 5370 5371 qup_i2c17_default: qup-i2c17-default-state { 5372 pins = "gpio52", "gpio53"; 5373 function = "qup17"; 5374 drive-strength = <2>; 5375 bias-disable; 5376 }; 5377 5378 qup_i2c18_default: qup-i2c18-default-state { 5379 pins = "gpio56", "gpio57"; 5380 function = "qup18"; 5381 drive-strength = <2>; 5382 bias-disable; 5383 }; 5384 5385 qup_i2c19_default: qup-i2c19-default-state { 5386 pins = "gpio0", "gpio1"; 5387 function = "qup19"; 5388 drive-strength = <2>; 5389 bias-disable; 5390 }; 5391 5392 qup_spi0_cs: qup-spi0-cs-state { 5393 pins = "gpio31"; 5394 function = "qup0"; 5395 }; 5396 5397 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 5398 pins = "gpio31"; 5399 function = "gpio"; 5400 }; 5401 5402 qup_spi0_data_clk: qup-spi0-data-clk-state { 5403 pins = "gpio28", "gpio29", 5404 "gpio30"; 5405 function = "qup0"; 5406 }; 5407 5408 qup_spi1_cs: qup-spi1-cs-state { 5409 pins = "gpio7"; 5410 function = "qup1"; 5411 }; 5412 5413 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 5414 pins = "gpio7"; 5415 function = "gpio"; 5416 }; 5417 5418 qup_spi1_data_clk: qup-spi1-data-clk-state { 5419 pins = "gpio4", "gpio5", 5420 "gpio6"; 5421 function = "qup1"; 5422 }; 5423 5424 qup_spi2_cs: qup-spi2-cs-state { 5425 pins = "gpio118"; 5426 function = "qup2"; 5427 }; 5428 5429 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 5430 pins = "gpio118"; 5431 function = "gpio"; 5432 }; 5433 5434 qup_spi2_data_clk: qup-spi2-data-clk-state { 5435 pins = "gpio115", "gpio116", 5436 "gpio117"; 5437 function = "qup2"; 5438 }; 5439 5440 qup_spi3_cs: qup-spi3-cs-state { 5441 pins = "gpio122"; 5442 function = "qup3"; 5443 }; 5444 5445 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 5446 pins = "gpio122"; 5447 function = "gpio"; 5448 }; 5449 5450 qup_spi3_data_clk: qup-spi3-data-clk-state { 5451 pins = "gpio119", "gpio120", 5452 "gpio121"; 5453 function = "qup3"; 5454 }; 5455 5456 qup_spi4_cs: qup-spi4-cs-state { 5457 pins = "gpio11"; 5458 function = "qup4"; 5459 }; 5460 5461 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 5462 pins = "gpio11"; 5463 function = "gpio"; 5464 }; 5465 5466 qup_spi4_data_clk: qup-spi4-data-clk-state { 5467 pins = "gpio8", "gpio9", 5468 "gpio10"; 5469 function = "qup4"; 5470 }; 5471 5472 qup_spi5_cs: qup-spi5-cs-state { 5473 pins = "gpio15"; 5474 function = "qup5"; 5475 }; 5476 5477 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 5478 pins = "gpio15"; 5479 function = "gpio"; 5480 }; 5481 5482 qup_spi5_data_clk: qup-spi5-data-clk-state { 5483 pins = "gpio12", "gpio13", 5484 "gpio14"; 5485 function = "qup5"; 5486 }; 5487 5488 qup_spi6_cs: qup-spi6-cs-state { 5489 pins = "gpio19"; 5490 function = "qup6"; 5491 }; 5492 5493 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 5494 pins = "gpio19"; 5495 function = "gpio"; 5496 }; 5497 5498 qup_spi6_data_clk: qup-spi6-data-clk-state { 5499 pins = "gpio16", "gpio17", 5500 "gpio18"; 5501 function = "qup6"; 5502 }; 5503 5504 qup_spi7_cs: qup-spi7-cs-state { 5505 pins = "gpio23"; 5506 function = "qup7"; 5507 }; 5508 5509 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 5510 pins = "gpio23"; 5511 function = "gpio"; 5512 }; 5513 5514 qup_spi7_data_clk: qup-spi7-data-clk-state { 5515 pins = "gpio20", "gpio21", 5516 "gpio22"; 5517 function = "qup7"; 5518 }; 5519 5520 qup_spi8_cs: qup-spi8-cs-state { 5521 pins = "gpio27"; 5522 function = "qup8"; 5523 }; 5524 5525 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 5526 pins = "gpio27"; 5527 function = "gpio"; 5528 }; 5529 5530 qup_spi8_data_clk: qup-spi8-data-clk-state { 5531 pins = "gpio24", "gpio25", 5532 "gpio26"; 5533 function = "qup8"; 5534 }; 5535 5536 qup_spi9_cs: qup-spi9-cs-state { 5537 pins = "gpio128"; 5538 function = "qup9"; 5539 }; 5540 5541 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 5542 pins = "gpio128"; 5543 function = "gpio"; 5544 }; 5545 5546 qup_spi9_data_clk: qup-spi9-data-clk-state { 5547 pins = "gpio125", "gpio126", 5548 "gpio127"; 5549 function = "qup9"; 5550 }; 5551 5552 qup_spi10_cs: qup-spi10-cs-state { 5553 pins = "gpio132"; 5554 function = "qup10"; 5555 }; 5556 5557 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 5558 pins = "gpio132"; 5559 function = "gpio"; 5560 }; 5561 5562 qup_spi10_data_clk: qup-spi10-data-clk-state { 5563 pins = "gpio129", "gpio130", 5564 "gpio131"; 5565 function = "qup10"; 5566 }; 5567 5568 qup_spi11_cs: qup-spi11-cs-state { 5569 pins = "gpio63"; 5570 function = "qup11"; 5571 }; 5572 5573 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 5574 pins = "gpio63"; 5575 function = "gpio"; 5576 }; 5577 5578 qup_spi11_data_clk: qup-spi11-data-clk-state { 5579 pins = "gpio60", "gpio61", 5580 "gpio62"; 5581 function = "qup11"; 5582 }; 5583 5584 qup_spi12_cs: qup-spi12-cs-state { 5585 pins = "gpio35"; 5586 function = "qup12"; 5587 }; 5588 5589 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 5590 pins = "gpio35"; 5591 function = "gpio"; 5592 }; 5593 5594 qup_spi12_data_clk: qup-spi12-data-clk-state { 5595 pins = "gpio32", "gpio33", 5596 "gpio34"; 5597 function = "qup12"; 5598 }; 5599 5600 qup_spi13_cs: qup-spi13-cs-state { 5601 pins = "gpio39"; 5602 function = "qup13"; 5603 }; 5604 5605 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 5606 pins = "gpio39"; 5607 function = "gpio"; 5608 }; 5609 5610 qup_spi13_data_clk: qup-spi13-data-clk-state { 5611 pins = "gpio36", "gpio37", 5612 "gpio38"; 5613 function = "qup13"; 5614 }; 5615 5616 qup_spi14_cs: qup-spi14-cs-state { 5617 pins = "gpio43"; 5618 function = "qup14"; 5619 }; 5620 5621 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 5622 pins = "gpio43"; 5623 function = "gpio"; 5624 }; 5625 5626 qup_spi14_data_clk: qup-spi14-data-clk-state { 5627 pins = "gpio40", "gpio41", 5628 "gpio42"; 5629 function = "qup14"; 5630 }; 5631 5632 qup_spi15_cs: qup-spi15-cs-state { 5633 pins = "gpio47"; 5634 function = "qup15"; 5635 }; 5636 5637 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 5638 pins = "gpio47"; 5639 function = "gpio"; 5640 }; 5641 5642 qup_spi15_data_clk: qup-spi15-data-clk-state { 5643 pins = "gpio44", "gpio45", 5644 "gpio46"; 5645 function = "qup15"; 5646 }; 5647 5648 qup_spi16_cs: qup-spi16-cs-state { 5649 pins = "gpio51"; 5650 function = "qup16"; 5651 }; 5652 5653 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state { 5654 pins = "gpio51"; 5655 function = "gpio"; 5656 }; 5657 5658 qup_spi16_data_clk: qup-spi16-data-clk-state { 5659 pins = "gpio48", "gpio49", 5660 "gpio50"; 5661 function = "qup16"; 5662 }; 5663 5664 qup_spi17_cs: qup-spi17-cs-state { 5665 pins = "gpio55"; 5666 function = "qup17"; 5667 }; 5668 5669 qup_spi17_cs_gpio: qup-spi17-cs-gpio-state { 5670 pins = "gpio55"; 5671 function = "gpio"; 5672 }; 5673 5674 qup_spi17_data_clk: qup-spi17-data-clk-state { 5675 pins = "gpio52", "gpio53", 5676 "gpio54"; 5677 function = "qup17"; 5678 }; 5679 5680 qup_spi18_cs: qup-spi18-cs-state { 5681 pins = "gpio59"; 5682 function = "qup18"; 5683 }; 5684 5685 qup_spi18_cs_gpio: qup-spi18-cs-gpio-state { 5686 pins = "gpio59"; 5687 function = "gpio"; 5688 }; 5689 5690 qup_spi18_data_clk: qup-spi18-data-clk-state { 5691 pins = "gpio56", "gpio57", 5692 "gpio58"; 5693 function = "qup18"; 5694 }; 5695 5696 qup_spi19_cs: qup-spi19-cs-state { 5697 pins = "gpio3"; 5698 function = "qup19"; 5699 }; 5700 5701 qup_spi19_cs_gpio: qup-spi19-cs-gpio-state { 5702 pins = "gpio3"; 5703 function = "gpio"; 5704 }; 5705 5706 qup_spi19_data_clk: qup-spi19-data-clk-state { 5707 pins = "gpio0", "gpio1", 5708 "gpio2"; 5709 function = "qup19"; 5710 }; 5711 5712 qup_uart2_default: qup-uart2-default-state { 5713 pins = "gpio117", "gpio118"; 5714 function = "qup2"; 5715 }; 5716 5717 qup_uart6_default: qup-uart6-default-state { 5718 pins = "gpio16", "gpio17", "gpio18", "gpio19"; 5719 function = "qup6"; 5720 }; 5721 5722 qup_uart12_default: qup-uart12-default-state { 5723 pins = "gpio34", "gpio35"; 5724 function = "qup12"; 5725 }; 5726 5727 qup_uart17_default: qup-uart17-default-state { 5728 pins = "gpio52", "gpio53", "gpio54", "gpio55"; 5729 function = "qup17"; 5730 }; 5731 5732 qup_uart18_default: qup-uart18-default-state { 5733 pins = "gpio58", "gpio59"; 5734 function = "qup18"; 5735 }; 5736 5737 tert_mi2s_active: tert-mi2s-active-state { 5738 sck-pins { 5739 pins = "gpio133"; 5740 function = "mi2s2_sck"; 5741 drive-strength = <8>; 5742 bias-disable; 5743 }; 5744 5745 data0-pins { 5746 pins = "gpio134"; 5747 function = "mi2s2_data0"; 5748 drive-strength = <8>; 5749 bias-disable; 5750 output-high; 5751 }; 5752 5753 ws-pins { 5754 pins = "gpio135"; 5755 function = "mi2s2_ws"; 5756 drive-strength = <8>; 5757 output-high; 5758 }; 5759 }; 5760 5761 sdc2_sleep_state: sdc2-sleep-state { 5762 clk-pins { 5763 pins = "sdc2_clk"; 5764 drive-strength = <2>; 5765 bias-disable; 5766 }; 5767 5768 cmd-pins { 5769 pins = "sdc2_cmd"; 5770 drive-strength = <2>; 5771 bias-pull-up; 5772 }; 5773 5774 data-pins { 5775 pins = "sdc2_data"; 5776 drive-strength = <2>; 5777 bias-pull-up; 5778 }; 5779 }; 5780 5781 pcie0_default_state: pcie0-default-state { 5782 perst-pins { 5783 pins = "gpio79"; 5784 function = "gpio"; 5785 drive-strength = <2>; 5786 bias-pull-down; 5787 }; 5788 5789 clkreq-pins { 5790 pins = "gpio80"; 5791 function = "pci_e0"; 5792 drive-strength = <2>; 5793 bias-pull-up; 5794 }; 5795 5796 wake-pins { 5797 pins = "gpio81"; 5798 function = "gpio"; 5799 drive-strength = <2>; 5800 bias-pull-up; 5801 }; 5802 }; 5803 5804 pcie1_default_state: pcie1-default-state { 5805 perst-pins { 5806 pins = "gpio82"; 5807 function = "gpio"; 5808 drive-strength = <2>; 5809 bias-pull-down; 5810 }; 5811 5812 clkreq-pins { 5813 pins = "gpio83"; 5814 function = "pci_e1"; 5815 drive-strength = <2>; 5816 bias-pull-up; 5817 }; 5818 5819 wake-pins { 5820 pins = "gpio84"; 5821 function = "gpio"; 5822 drive-strength = <2>; 5823 bias-pull-up; 5824 }; 5825 }; 5826 5827 pcie2_default_state: pcie2-default-state { 5828 perst-pins { 5829 pins = "gpio85"; 5830 function = "gpio"; 5831 drive-strength = <2>; 5832 bias-pull-down; 5833 }; 5834 5835 clkreq-pins { 5836 pins = "gpio86"; 5837 function = "pci_e2"; 5838 drive-strength = <2>; 5839 bias-pull-up; 5840 }; 5841 5842 wake-pins { 5843 pins = "gpio87"; 5844 function = "gpio"; 5845 drive-strength = <2>; 5846 bias-pull-up; 5847 }; 5848 }; 5849 }; 5850 5851 apps_smmu: iommu@15000000 { 5852 compatible = "qcom,sm8250-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 5853 reg = <0 0x15000000 0 0x100000>; 5854 #iommu-cells = <2>; 5855 #global-interrupts = <2>; 5856 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 5857 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5858 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5859 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5860 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5861 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5862 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5863 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5864 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5865 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5866 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5867 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5868 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5869 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5870 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5871 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5872 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5873 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5874 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5875 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5876 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5877 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5878 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5879 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5880 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5881 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5882 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5883 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5884 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5885 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5886 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5887 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5888 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5889 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5890 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5891 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5892 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5893 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5894 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5895 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5896 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5897 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5898 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5899 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5900 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5901 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5902 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5903 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5904 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5905 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5906 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5907 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5908 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5909 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5910 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5911 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5912 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5913 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5914 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5915 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5916 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5917 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5918 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5919 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5920 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5921 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5922 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5923 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5924 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5925 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5926 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5927 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5928 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5929 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5930 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5931 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5932 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5933 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5934 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5935 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5936 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5937 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5938 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5939 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5940 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5941 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5942 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5943 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5944 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5945 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5946 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5947 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5948 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5949 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5950 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5951 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5952 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 5953 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 5954 dma-coherent; 5955 }; 5956 5957 adsp: remoteproc@17300000 { 5958 compatible = "qcom,sm8250-adsp-pas"; 5959 reg = <0 0x17300000 0 0x100>; 5960 5961 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 5962 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 5963 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 5964 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 5965 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 5966 interrupt-names = "wdog", "fatal", "ready", 5967 "handover", "stop-ack"; 5968 5969 clocks = <&rpmhcc RPMH_CXO_CLK>; 5970 clock-names = "xo"; 5971 5972 power-domains = <&rpmhpd RPMHPD_LCX>, 5973 <&rpmhpd RPMHPD_LMX>; 5974 power-domain-names = "lcx", "lmx"; 5975 5976 memory-region = <&adsp_mem>; 5977 5978 qcom,qmp = <&aoss_qmp>; 5979 5980 qcom,smem-states = <&smp2p_adsp_out 0>; 5981 qcom,smem-state-names = "stop"; 5982 5983 status = "disabled"; 5984 5985 glink-edge { 5986 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 5987 IPCC_MPROC_SIGNAL_GLINK_QMP 5988 IRQ_TYPE_EDGE_RISING>; 5989 mboxes = <&ipcc IPCC_CLIENT_LPASS 5990 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5991 5992 label = "lpass"; 5993 qcom,remote-pid = <2>; 5994 5995 apr { 5996 compatible = "qcom,apr-v2"; 5997 qcom,glink-channels = "apr_audio_svc"; 5998 qcom,domain = <APR_DOMAIN_ADSP>; 5999 #address-cells = <1>; 6000 #size-cells = <0>; 6001 6002 service@3 { 6003 reg = <APR_SVC_ADSP_CORE>; 6004 compatible = "qcom,q6core"; 6005 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 6006 }; 6007 6008 q6afe: service@4 { 6009 compatible = "qcom,q6afe"; 6010 reg = <APR_SVC_AFE>; 6011 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 6012 q6afedai: dais { 6013 compatible = "qcom,q6afe-dais"; 6014 #address-cells = <1>; 6015 #size-cells = <0>; 6016 #sound-dai-cells = <1>; 6017 }; 6018 6019 q6afecc: clock-controller { 6020 compatible = "qcom,q6afe-clocks"; 6021 #clock-cells = <2>; 6022 }; 6023 }; 6024 6025 q6asm: service@7 { 6026 compatible = "qcom,q6asm"; 6027 reg = <APR_SVC_ASM>; 6028 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 6029 q6asmdai: dais { 6030 compatible = "qcom,q6asm-dais"; 6031 #address-cells = <1>; 6032 #size-cells = <0>; 6033 #sound-dai-cells = <1>; 6034 iommus = <&apps_smmu 0x1801 0x0>; 6035 }; 6036 }; 6037 6038 q6adm: service@8 { 6039 compatible = "qcom,q6adm"; 6040 reg = <APR_SVC_ADM>; 6041 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 6042 q6routing: routing { 6043 compatible = "qcom,q6adm-routing"; 6044 #sound-dai-cells = <0>; 6045 }; 6046 }; 6047 }; 6048 6049 fastrpc { 6050 compatible = "qcom,fastrpc"; 6051 qcom,glink-channels = "fastrpcglink-apps-dsp"; 6052 label = "adsp"; 6053 qcom,non-secure-domain; 6054 #address-cells = <1>; 6055 #size-cells = <0>; 6056 6057 compute-cb@3 { 6058 compatible = "qcom,fastrpc-compute-cb"; 6059 reg = <3>; 6060 iommus = <&apps_smmu 0x1803 0x0>; 6061 }; 6062 6063 compute-cb@4 { 6064 compatible = "qcom,fastrpc-compute-cb"; 6065 reg = <4>; 6066 iommus = <&apps_smmu 0x1804 0x0>; 6067 }; 6068 6069 compute-cb@5 { 6070 compatible = "qcom,fastrpc-compute-cb"; 6071 reg = <5>; 6072 iommus = <&apps_smmu 0x1805 0x0>; 6073 }; 6074 }; 6075 }; 6076 }; 6077 6078 intc: interrupt-controller@17a00000 { 6079 compatible = "arm,gic-v3"; 6080 #interrupt-cells = <3>; 6081 interrupt-controller; 6082 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 6083 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 6084 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 6085 }; 6086 6087 watchdog@17c10000 { 6088 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; 6089 reg = <0 0x17c10000 0 0x1000>; 6090 clocks = <&sleep_clk>; 6091 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 6092 }; 6093 6094 timer@17c20000 { 6095 #address-cells = <1>; 6096 #size-cells = <1>; 6097 ranges = <0 0 0 0x20000000>; 6098 compatible = "arm,armv7-timer-mem"; 6099 reg = <0x0 0x17c20000 0x0 0x1000>; 6100 clock-frequency = <19200000>; 6101 6102 frame@17c21000 { 6103 frame-number = <0>; 6104 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 6105 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 6106 reg = <0x17c21000 0x1000>, 6107 <0x17c22000 0x1000>; 6108 }; 6109 6110 frame@17c23000 { 6111 frame-number = <1>; 6112 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 6113 reg = <0x17c23000 0x1000>; 6114 status = "disabled"; 6115 }; 6116 6117 frame@17c25000 { 6118 frame-number = <2>; 6119 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 6120 reg = <0x17c25000 0x1000>; 6121 status = "disabled"; 6122 }; 6123 6124 frame@17c27000 { 6125 frame-number = <3>; 6126 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 6127 reg = <0x17c27000 0x1000>; 6128 status = "disabled"; 6129 }; 6130 6131 frame@17c29000 { 6132 frame-number = <4>; 6133 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 6134 reg = <0x17c29000 0x1000>; 6135 status = "disabled"; 6136 }; 6137 6138 frame@17c2b000 { 6139 frame-number = <5>; 6140 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 6141 reg = <0x17c2b000 0x1000>; 6142 status = "disabled"; 6143 }; 6144 6145 frame@17c2d000 { 6146 frame-number = <6>; 6147 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 6148 reg = <0x17c2d000 0x1000>; 6149 status = "disabled"; 6150 }; 6151 }; 6152 6153 apps_rsc: rsc@18200000 { 6154 label = "apps_rsc"; 6155 compatible = "qcom,rpmh-rsc"; 6156 reg = <0x0 0x18200000 0x0 0x10000>, 6157 <0x0 0x18210000 0x0 0x10000>, 6158 <0x0 0x18220000 0x0 0x10000>; 6159 reg-names = "drv-0", "drv-1", "drv-2"; 6160 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 6161 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 6162 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 6163 qcom,tcs-offset = <0xd00>; 6164 qcom,drv-id = <2>; 6165 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 6166 <WAKE_TCS 3>, <CONTROL_TCS 1>; 6167 power-domains = <&CLUSTER_PD>; 6168 6169 rpmhcc: clock-controller { 6170 compatible = "qcom,sm8250-rpmh-clk"; 6171 #clock-cells = <1>; 6172 clock-names = "xo"; 6173 clocks = <&xo_board>; 6174 }; 6175 6176 rpmhpd: power-controller { 6177 compatible = "qcom,sm8250-rpmhpd"; 6178 #power-domain-cells = <1>; 6179 operating-points-v2 = <&rpmhpd_opp_table>; 6180 6181 rpmhpd_opp_table: opp-table { 6182 compatible = "operating-points-v2"; 6183 6184 rpmhpd_opp_ret: opp1 { 6185 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 6186 }; 6187 6188 rpmhpd_opp_min_svs: opp2 { 6189 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 6190 }; 6191 6192 rpmhpd_opp_low_svs: opp3 { 6193 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 6194 }; 6195 6196 rpmhpd_opp_svs: opp4 { 6197 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 6198 }; 6199 6200 rpmhpd_opp_svs_l1: opp5 { 6201 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 6202 }; 6203 6204 rpmhpd_opp_nom: opp6 { 6205 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 6206 }; 6207 6208 rpmhpd_opp_nom_l1: opp7 { 6209 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 6210 }; 6211 6212 rpmhpd_opp_nom_l2: opp8 { 6213 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 6214 }; 6215 6216 rpmhpd_opp_turbo: opp9 { 6217 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 6218 }; 6219 6220 rpmhpd_opp_turbo_l1: opp10 { 6221 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 6222 }; 6223 }; 6224 }; 6225 6226 apps_bcm_voter: bcm-voter { 6227 compatible = "qcom,bcm-voter"; 6228 }; 6229 }; 6230 6231 epss_l3: interconnect@18590000 { 6232 compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3"; 6233 reg = <0 0x18590000 0 0x1000>; 6234 6235 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 6236 clock-names = "xo", "alternate"; 6237 6238 #interconnect-cells = <1>; 6239 }; 6240 6241 cpufreq_hw: cpufreq@18591000 { 6242 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; 6243 reg = <0 0x18591000 0 0x1000>, 6244 <0 0x18592000 0 0x1000>, 6245 <0 0x18593000 0 0x1000>; 6246 reg-names = "freq-domain0", "freq-domain1", 6247 "freq-domain2"; 6248 6249 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 6250 clock-names = "xo", "alternate"; 6251 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 6252 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 6253 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 6254 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 6255 #freq-domain-cells = <1>; 6256 #clock-cells = <1>; 6257 }; 6258 }; 6259 6260 sound: sound { 6261 }; 6262 6263 timer { 6264 compatible = "arm,armv8-timer"; 6265 interrupts = <GIC_PPI 13 6266 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6267 <GIC_PPI 14 6268 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6269 <GIC_PPI 11 6270 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6271 <GIC_PPI 10 6272 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 6273 }; 6274 6275 thermal-zones { 6276 cpu0-thermal { 6277 polling-delay-passive = <250>; 6278 polling-delay = <1000>; 6279 6280 thermal-sensors = <&tsens0 1>; 6281 6282 trips { 6283 cpu0_alert0: trip-point0 { 6284 temperature = <90000>; 6285 hysteresis = <2000>; 6286 type = "passive"; 6287 }; 6288 6289 cpu0_alert1: trip-point1 { 6290 temperature = <95000>; 6291 hysteresis = <2000>; 6292 type = "passive"; 6293 }; 6294 6295 cpu0_crit: cpu-crit { 6296 temperature = <110000>; 6297 hysteresis = <1000>; 6298 type = "critical"; 6299 }; 6300 }; 6301 6302 cooling-maps { 6303 map0 { 6304 trip = <&cpu0_alert0>; 6305 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6306 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6307 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6308 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6309 }; 6310 map1 { 6311 trip = <&cpu0_alert1>; 6312 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6313 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6314 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6315 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6316 }; 6317 }; 6318 }; 6319 6320 cpu1-thermal { 6321 polling-delay-passive = <250>; 6322 polling-delay = <1000>; 6323 6324 thermal-sensors = <&tsens0 2>; 6325 6326 trips { 6327 cpu1_alert0: trip-point0 { 6328 temperature = <90000>; 6329 hysteresis = <2000>; 6330 type = "passive"; 6331 }; 6332 6333 cpu1_alert1: trip-point1 { 6334 temperature = <95000>; 6335 hysteresis = <2000>; 6336 type = "passive"; 6337 }; 6338 6339 cpu1_crit: cpu-crit { 6340 temperature = <110000>; 6341 hysteresis = <1000>; 6342 type = "critical"; 6343 }; 6344 }; 6345 6346 cooling-maps { 6347 map0 { 6348 trip = <&cpu1_alert0>; 6349 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6350 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6351 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6352 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6353 }; 6354 map1 { 6355 trip = <&cpu1_alert1>; 6356 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6357 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6358 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6359 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6360 }; 6361 }; 6362 }; 6363 6364 cpu2-thermal { 6365 polling-delay-passive = <250>; 6366 polling-delay = <1000>; 6367 6368 thermal-sensors = <&tsens0 3>; 6369 6370 trips { 6371 cpu2_alert0: trip-point0 { 6372 temperature = <90000>; 6373 hysteresis = <2000>; 6374 type = "passive"; 6375 }; 6376 6377 cpu2_alert1: trip-point1 { 6378 temperature = <95000>; 6379 hysteresis = <2000>; 6380 type = "passive"; 6381 }; 6382 6383 cpu2_crit: cpu-crit { 6384 temperature = <110000>; 6385 hysteresis = <1000>; 6386 type = "critical"; 6387 }; 6388 }; 6389 6390 cooling-maps { 6391 map0 { 6392 trip = <&cpu2_alert0>; 6393 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6394 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6395 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6396 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6397 }; 6398 map1 { 6399 trip = <&cpu2_alert1>; 6400 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6401 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6402 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6403 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6404 }; 6405 }; 6406 }; 6407 6408 cpu3-thermal { 6409 polling-delay-passive = <250>; 6410 polling-delay = <1000>; 6411 6412 thermal-sensors = <&tsens0 4>; 6413 6414 trips { 6415 cpu3_alert0: trip-point0 { 6416 temperature = <90000>; 6417 hysteresis = <2000>; 6418 type = "passive"; 6419 }; 6420 6421 cpu3_alert1: trip-point1 { 6422 temperature = <95000>; 6423 hysteresis = <2000>; 6424 type = "passive"; 6425 }; 6426 6427 cpu3_crit: cpu-crit { 6428 temperature = <110000>; 6429 hysteresis = <1000>; 6430 type = "critical"; 6431 }; 6432 }; 6433 6434 cooling-maps { 6435 map0 { 6436 trip = <&cpu3_alert0>; 6437 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6438 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6439 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6440 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6441 }; 6442 map1 { 6443 trip = <&cpu3_alert1>; 6444 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6445 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6446 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6447 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6448 }; 6449 }; 6450 }; 6451 6452 cpu4-top-thermal { 6453 polling-delay-passive = <250>; 6454 polling-delay = <1000>; 6455 6456 thermal-sensors = <&tsens0 7>; 6457 6458 trips { 6459 cpu4_top_alert0: trip-point0 { 6460 temperature = <90000>; 6461 hysteresis = <2000>; 6462 type = "passive"; 6463 }; 6464 6465 cpu4_top_alert1: trip-point1 { 6466 temperature = <95000>; 6467 hysteresis = <2000>; 6468 type = "passive"; 6469 }; 6470 6471 cpu4_top_crit: cpu-crit { 6472 temperature = <110000>; 6473 hysteresis = <1000>; 6474 type = "critical"; 6475 }; 6476 }; 6477 6478 cooling-maps { 6479 map0 { 6480 trip = <&cpu4_top_alert0>; 6481 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6482 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6483 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6484 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6485 }; 6486 map1 { 6487 trip = <&cpu4_top_alert1>; 6488 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6489 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6490 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6491 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6492 }; 6493 }; 6494 }; 6495 6496 cpu5-top-thermal { 6497 polling-delay-passive = <250>; 6498 polling-delay = <1000>; 6499 6500 thermal-sensors = <&tsens0 8>; 6501 6502 trips { 6503 cpu5_top_alert0: trip-point0 { 6504 temperature = <90000>; 6505 hysteresis = <2000>; 6506 type = "passive"; 6507 }; 6508 6509 cpu5_top_alert1: trip-point1 { 6510 temperature = <95000>; 6511 hysteresis = <2000>; 6512 type = "passive"; 6513 }; 6514 6515 cpu5_top_crit: cpu-crit { 6516 temperature = <110000>; 6517 hysteresis = <1000>; 6518 type = "critical"; 6519 }; 6520 }; 6521 6522 cooling-maps { 6523 map0 { 6524 trip = <&cpu5_top_alert0>; 6525 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6526 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6527 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6528 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6529 }; 6530 map1 { 6531 trip = <&cpu5_top_alert1>; 6532 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6533 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6534 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6535 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6536 }; 6537 }; 6538 }; 6539 6540 cpu6-top-thermal { 6541 polling-delay-passive = <250>; 6542 polling-delay = <1000>; 6543 6544 thermal-sensors = <&tsens0 9>; 6545 6546 trips { 6547 cpu6_top_alert0: trip-point0 { 6548 temperature = <90000>; 6549 hysteresis = <2000>; 6550 type = "passive"; 6551 }; 6552 6553 cpu6_top_alert1: trip-point1 { 6554 temperature = <95000>; 6555 hysteresis = <2000>; 6556 type = "passive"; 6557 }; 6558 6559 cpu6_top_crit: cpu-crit { 6560 temperature = <110000>; 6561 hysteresis = <1000>; 6562 type = "critical"; 6563 }; 6564 }; 6565 6566 cooling-maps { 6567 map0 { 6568 trip = <&cpu6_top_alert0>; 6569 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6570 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6571 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6572 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6573 }; 6574 map1 { 6575 trip = <&cpu6_top_alert1>; 6576 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6577 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6578 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6579 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6580 }; 6581 }; 6582 }; 6583 6584 cpu7-top-thermal { 6585 polling-delay-passive = <250>; 6586 polling-delay = <1000>; 6587 6588 thermal-sensors = <&tsens0 10>; 6589 6590 trips { 6591 cpu7_top_alert0: trip-point0 { 6592 temperature = <90000>; 6593 hysteresis = <2000>; 6594 type = "passive"; 6595 }; 6596 6597 cpu7_top_alert1: trip-point1 { 6598 temperature = <95000>; 6599 hysteresis = <2000>; 6600 type = "passive"; 6601 }; 6602 6603 cpu7_top_crit: cpu-crit { 6604 temperature = <110000>; 6605 hysteresis = <1000>; 6606 type = "critical"; 6607 }; 6608 }; 6609 6610 cooling-maps { 6611 map0 { 6612 trip = <&cpu7_top_alert0>; 6613 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6614 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6615 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6616 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6617 }; 6618 map1 { 6619 trip = <&cpu7_top_alert1>; 6620 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6621 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6622 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6623 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6624 }; 6625 }; 6626 }; 6627 6628 cpu4-bottom-thermal { 6629 polling-delay-passive = <250>; 6630 polling-delay = <1000>; 6631 6632 thermal-sensors = <&tsens0 11>; 6633 6634 trips { 6635 cpu4_bottom_alert0: trip-point0 { 6636 temperature = <90000>; 6637 hysteresis = <2000>; 6638 type = "passive"; 6639 }; 6640 6641 cpu4_bottom_alert1: trip-point1 { 6642 temperature = <95000>; 6643 hysteresis = <2000>; 6644 type = "passive"; 6645 }; 6646 6647 cpu4_bottom_crit: cpu-crit { 6648 temperature = <110000>; 6649 hysteresis = <1000>; 6650 type = "critical"; 6651 }; 6652 }; 6653 6654 cooling-maps { 6655 map0 { 6656 trip = <&cpu4_bottom_alert0>; 6657 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6658 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6659 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6660 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6661 }; 6662 map1 { 6663 trip = <&cpu4_bottom_alert1>; 6664 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6665 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6666 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6667 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6668 }; 6669 }; 6670 }; 6671 6672 cpu5-bottom-thermal { 6673 polling-delay-passive = <250>; 6674 polling-delay = <1000>; 6675 6676 thermal-sensors = <&tsens0 12>; 6677 6678 trips { 6679 cpu5_bottom_alert0: trip-point0 { 6680 temperature = <90000>; 6681 hysteresis = <2000>; 6682 type = "passive"; 6683 }; 6684 6685 cpu5_bottom_alert1: trip-point1 { 6686 temperature = <95000>; 6687 hysteresis = <2000>; 6688 type = "passive"; 6689 }; 6690 6691 cpu5_bottom_crit: cpu-crit { 6692 temperature = <110000>; 6693 hysteresis = <1000>; 6694 type = "critical"; 6695 }; 6696 }; 6697 6698 cooling-maps { 6699 map0 { 6700 trip = <&cpu5_bottom_alert0>; 6701 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6702 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6703 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6704 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6705 }; 6706 map1 { 6707 trip = <&cpu5_bottom_alert1>; 6708 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6709 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6710 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6711 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6712 }; 6713 }; 6714 }; 6715 6716 cpu6-bottom-thermal { 6717 polling-delay-passive = <250>; 6718 polling-delay = <1000>; 6719 6720 thermal-sensors = <&tsens0 13>; 6721 6722 trips { 6723 cpu6_bottom_alert0: trip-point0 { 6724 temperature = <90000>; 6725 hysteresis = <2000>; 6726 type = "passive"; 6727 }; 6728 6729 cpu6_bottom_alert1: trip-point1 { 6730 temperature = <95000>; 6731 hysteresis = <2000>; 6732 type = "passive"; 6733 }; 6734 6735 cpu6_bottom_crit: cpu-crit { 6736 temperature = <110000>; 6737 hysteresis = <1000>; 6738 type = "critical"; 6739 }; 6740 }; 6741 6742 cooling-maps { 6743 map0 { 6744 trip = <&cpu6_bottom_alert0>; 6745 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6746 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6747 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6748 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6749 }; 6750 map1 { 6751 trip = <&cpu6_bottom_alert1>; 6752 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6753 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6754 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6755 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6756 }; 6757 }; 6758 }; 6759 6760 cpu7-bottom-thermal { 6761 polling-delay-passive = <250>; 6762 polling-delay = <1000>; 6763 6764 thermal-sensors = <&tsens0 14>; 6765 6766 trips { 6767 cpu7_bottom_alert0: trip-point0 { 6768 temperature = <90000>; 6769 hysteresis = <2000>; 6770 type = "passive"; 6771 }; 6772 6773 cpu7_bottom_alert1: trip-point1 { 6774 temperature = <95000>; 6775 hysteresis = <2000>; 6776 type = "passive"; 6777 }; 6778 6779 cpu7_bottom_crit: cpu-crit { 6780 temperature = <110000>; 6781 hysteresis = <1000>; 6782 type = "critical"; 6783 }; 6784 }; 6785 6786 cooling-maps { 6787 map0 { 6788 trip = <&cpu7_bottom_alert0>; 6789 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6790 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6791 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6792 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6793 }; 6794 map1 { 6795 trip = <&cpu7_bottom_alert1>; 6796 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6797 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6798 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6799 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6800 }; 6801 }; 6802 }; 6803 6804 aoss0-thermal { 6805 polling-delay-passive = <250>; 6806 polling-delay = <1000>; 6807 6808 thermal-sensors = <&tsens0 0>; 6809 6810 trips { 6811 aoss0_alert0: trip-point0 { 6812 temperature = <90000>; 6813 hysteresis = <2000>; 6814 type = "hot"; 6815 }; 6816 }; 6817 }; 6818 6819 cluster0-thermal { 6820 polling-delay-passive = <250>; 6821 polling-delay = <1000>; 6822 6823 thermal-sensors = <&tsens0 5>; 6824 6825 trips { 6826 cluster0_alert0: trip-point0 { 6827 temperature = <90000>; 6828 hysteresis = <2000>; 6829 type = "hot"; 6830 }; 6831 cluster0_crit: cluster0-crit { 6832 temperature = <110000>; 6833 hysteresis = <2000>; 6834 type = "critical"; 6835 }; 6836 }; 6837 }; 6838 6839 cluster1-thermal { 6840 polling-delay-passive = <250>; 6841 polling-delay = <1000>; 6842 6843 thermal-sensors = <&tsens0 6>; 6844 6845 trips { 6846 cluster1_alert0: trip-point0 { 6847 temperature = <90000>; 6848 hysteresis = <2000>; 6849 type = "hot"; 6850 }; 6851 cluster1_crit: cluster1-crit { 6852 temperature = <110000>; 6853 hysteresis = <2000>; 6854 type = "critical"; 6855 }; 6856 }; 6857 }; 6858 6859 gpu-top-thermal { 6860 polling-delay-passive = <250>; 6861 polling-delay = <1000>; 6862 6863 thermal-sensors = <&tsens0 15>; 6864 6865 cooling-maps { 6866 map0 { 6867 trip = <&gpu_top_alert0>; 6868 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6869 }; 6870 }; 6871 6872 trips { 6873 gpu_top_alert0: trip-point0 { 6874 temperature = <90000>; 6875 hysteresis = <2000>; 6876 type = "hot"; 6877 }; 6878 }; 6879 }; 6880 6881 aoss1-thermal { 6882 polling-delay-passive = <250>; 6883 polling-delay = <1000>; 6884 6885 thermal-sensors = <&tsens1 0>; 6886 6887 trips { 6888 aoss1_alert0: trip-point0 { 6889 temperature = <90000>; 6890 hysteresis = <2000>; 6891 type = "hot"; 6892 }; 6893 }; 6894 }; 6895 6896 wlan-thermal { 6897 polling-delay-passive = <250>; 6898 polling-delay = <1000>; 6899 6900 thermal-sensors = <&tsens1 1>; 6901 6902 trips { 6903 wlan_alert0: trip-point0 { 6904 temperature = <90000>; 6905 hysteresis = <2000>; 6906 type = "hot"; 6907 }; 6908 }; 6909 }; 6910 6911 video-thermal { 6912 polling-delay-passive = <250>; 6913 polling-delay = <1000>; 6914 6915 thermal-sensors = <&tsens1 2>; 6916 6917 trips { 6918 video_alert0: trip-point0 { 6919 temperature = <90000>; 6920 hysteresis = <2000>; 6921 type = "hot"; 6922 }; 6923 }; 6924 }; 6925 6926 mem-thermal { 6927 polling-delay-passive = <250>; 6928 polling-delay = <1000>; 6929 6930 thermal-sensors = <&tsens1 3>; 6931 6932 trips { 6933 mem_alert0: trip-point0 { 6934 temperature = <90000>; 6935 hysteresis = <2000>; 6936 type = "hot"; 6937 }; 6938 }; 6939 }; 6940 6941 q6-hvx-thermal { 6942 polling-delay-passive = <250>; 6943 polling-delay = <1000>; 6944 6945 thermal-sensors = <&tsens1 4>; 6946 6947 trips { 6948 q6_hvx_alert0: trip-point0 { 6949 temperature = <90000>; 6950 hysteresis = <2000>; 6951 type = "hot"; 6952 }; 6953 }; 6954 }; 6955 6956 camera-thermal { 6957 polling-delay-passive = <250>; 6958 polling-delay = <1000>; 6959 6960 thermal-sensors = <&tsens1 5>; 6961 6962 trips { 6963 camera_alert0: trip-point0 { 6964 temperature = <90000>; 6965 hysteresis = <2000>; 6966 type = "hot"; 6967 }; 6968 }; 6969 }; 6970 6971 compute-thermal { 6972 polling-delay-passive = <250>; 6973 polling-delay = <1000>; 6974 6975 thermal-sensors = <&tsens1 6>; 6976 6977 trips { 6978 compute_alert0: trip-point0 { 6979 temperature = <90000>; 6980 hysteresis = <2000>; 6981 type = "hot"; 6982 }; 6983 }; 6984 }; 6985 6986 npu-thermal { 6987 polling-delay-passive = <250>; 6988 polling-delay = <1000>; 6989 6990 thermal-sensors = <&tsens1 7>; 6991 6992 trips { 6993 npu_alert0: trip-point0 { 6994 temperature = <90000>; 6995 hysteresis = <2000>; 6996 type = "hot"; 6997 }; 6998 }; 6999 }; 7000 7001 gpu-bottom-thermal { 7002 polling-delay-passive = <250>; 7003 polling-delay = <1000>; 7004 7005 thermal-sensors = <&tsens1 8>; 7006 7007 cooling-maps { 7008 map0 { 7009 trip = <&gpu_bottom_alert0>; 7010 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7011 }; 7012 }; 7013 7014 trips { 7015 gpu_bottom_alert0: trip-point0 { 7016 temperature = <90000>; 7017 hysteresis = <2000>; 7018 type = "hot"; 7019 }; 7020 }; 7021 }; 7022 }; 7023}; 7024