1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,gcc-sm8250.h> 9#include <dt-bindings/clock/qcom,gpucc-sm8250.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sm8250-lpass-aoncc.h> 12#include <dt-bindings/clock/qcom,sm8250-lpass-audiocc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,sm8250.h> 17#include <dt-bindings/mailbox/qcom-ipcc.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/soc/qcom,apr.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/sound/qcom,q6afe.h> 22#include <dt-bindings/thermal/thermal.h> 23#include <dt-bindings/clock/qcom,camcc-sm8250.h> 24#include <dt-bindings/clock/qcom,videocc-sm8250.h> 25 26/ { 27 interrupt-parent = <&intc>; 28 29 #address-cells = <2>; 30 #size-cells = <2>; 31 32 aliases { 33 i2c0 = &i2c0; 34 i2c1 = &i2c1; 35 i2c2 = &i2c2; 36 i2c3 = &i2c3; 37 i2c4 = &i2c4; 38 i2c5 = &i2c5; 39 i2c6 = &i2c6; 40 i2c7 = &i2c7; 41 i2c8 = &i2c8; 42 i2c9 = &i2c9; 43 i2c10 = &i2c10; 44 i2c11 = &i2c11; 45 i2c12 = &i2c12; 46 i2c13 = &i2c13; 47 i2c14 = &i2c14; 48 i2c15 = &i2c15; 49 i2c16 = &i2c16; 50 i2c17 = &i2c17; 51 i2c18 = &i2c18; 52 i2c19 = &i2c19; 53 spi0 = &spi0; 54 spi1 = &spi1; 55 spi2 = &spi2; 56 spi3 = &spi3; 57 spi4 = &spi4; 58 spi5 = &spi5; 59 spi6 = &spi6; 60 spi7 = &spi7; 61 spi8 = &spi8; 62 spi9 = &spi9; 63 spi10 = &spi10; 64 spi11 = &spi11; 65 spi12 = &spi12; 66 spi13 = &spi13; 67 spi14 = &spi14; 68 spi15 = &spi15; 69 spi16 = &spi16; 70 spi17 = &spi17; 71 spi18 = &spi18; 72 spi19 = &spi19; 73 }; 74 75 chosen { }; 76 77 clocks { 78 xo_board: xo-board { 79 compatible = "fixed-clock"; 80 #clock-cells = <0>; 81 clock-frequency = <38400000>; 82 clock-output-names = "xo_board"; 83 }; 84 85 sleep_clk: sleep-clk { 86 compatible = "fixed-clock"; 87 clock-frequency = <32768>; 88 #clock-cells = <0>; 89 }; 90 }; 91 92 cpus { 93 #address-cells = <2>; 94 #size-cells = <0>; 95 96 CPU0: cpu@0 { 97 device_type = "cpu"; 98 compatible = "qcom,kryo485"; 99 reg = <0x0 0x0>; 100 enable-method = "psci"; 101 capacity-dmips-mhz = <448>; 102 dynamic-power-coefficient = <205>; 103 next-level-cache = <&L2_0>; 104 power-domains = <&CPU_PD0>; 105 power-domain-names = "psci"; 106 qcom,freq-domain = <&cpufreq_hw 0>; 107 operating-points-v2 = <&cpu0_opp_table>; 108 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 109 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 110 #cooling-cells = <2>; 111 L2_0: l2-cache { 112 compatible = "cache"; 113 cache-level = <2>; 114 cache-size = <0x20000>; 115 cache-unified; 116 next-level-cache = <&L3_0>; 117 L3_0: l3-cache { 118 compatible = "cache"; 119 cache-level = <3>; 120 cache-size = <0x400000>; 121 cache-unified; 122 }; 123 }; 124 }; 125 126 CPU1: cpu@100 { 127 device_type = "cpu"; 128 compatible = "qcom,kryo485"; 129 reg = <0x0 0x100>; 130 enable-method = "psci"; 131 capacity-dmips-mhz = <448>; 132 dynamic-power-coefficient = <205>; 133 next-level-cache = <&L2_100>; 134 power-domains = <&CPU_PD1>; 135 power-domain-names = "psci"; 136 qcom,freq-domain = <&cpufreq_hw 0>; 137 operating-points-v2 = <&cpu0_opp_table>; 138 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 139 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 140 #cooling-cells = <2>; 141 L2_100: l2-cache { 142 compatible = "cache"; 143 cache-level = <2>; 144 cache-size = <0x20000>; 145 cache-unified; 146 next-level-cache = <&L3_0>; 147 }; 148 }; 149 150 CPU2: cpu@200 { 151 device_type = "cpu"; 152 compatible = "qcom,kryo485"; 153 reg = <0x0 0x200>; 154 enable-method = "psci"; 155 capacity-dmips-mhz = <448>; 156 dynamic-power-coefficient = <205>; 157 next-level-cache = <&L2_200>; 158 power-domains = <&CPU_PD2>; 159 power-domain-names = "psci"; 160 qcom,freq-domain = <&cpufreq_hw 0>; 161 operating-points-v2 = <&cpu0_opp_table>; 162 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 163 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 164 #cooling-cells = <2>; 165 L2_200: l2-cache { 166 compatible = "cache"; 167 cache-level = <2>; 168 cache-size = <0x20000>; 169 cache-unified; 170 next-level-cache = <&L3_0>; 171 }; 172 }; 173 174 CPU3: cpu@300 { 175 device_type = "cpu"; 176 compatible = "qcom,kryo485"; 177 reg = <0x0 0x300>; 178 enable-method = "psci"; 179 capacity-dmips-mhz = <448>; 180 dynamic-power-coefficient = <205>; 181 next-level-cache = <&L2_300>; 182 power-domains = <&CPU_PD3>; 183 power-domain-names = "psci"; 184 qcom,freq-domain = <&cpufreq_hw 0>; 185 operating-points-v2 = <&cpu0_opp_table>; 186 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 187 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 188 #cooling-cells = <2>; 189 L2_300: l2-cache { 190 compatible = "cache"; 191 cache-level = <2>; 192 cache-size = <0x20000>; 193 cache-unified; 194 next-level-cache = <&L3_0>; 195 }; 196 }; 197 198 CPU4: cpu@400 { 199 device_type = "cpu"; 200 compatible = "qcom,kryo485"; 201 reg = <0x0 0x400>; 202 enable-method = "psci"; 203 capacity-dmips-mhz = <1024>; 204 dynamic-power-coefficient = <379>; 205 next-level-cache = <&L2_400>; 206 power-domains = <&CPU_PD4>; 207 power-domain-names = "psci"; 208 qcom,freq-domain = <&cpufreq_hw 1>; 209 operating-points-v2 = <&cpu4_opp_table>; 210 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 211 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 212 #cooling-cells = <2>; 213 L2_400: l2-cache { 214 compatible = "cache"; 215 cache-level = <2>; 216 cache-size = <0x40000>; 217 cache-unified; 218 next-level-cache = <&L3_0>; 219 }; 220 }; 221 222 CPU5: cpu@500 { 223 device_type = "cpu"; 224 compatible = "qcom,kryo485"; 225 reg = <0x0 0x500>; 226 enable-method = "psci"; 227 capacity-dmips-mhz = <1024>; 228 dynamic-power-coefficient = <379>; 229 next-level-cache = <&L2_500>; 230 power-domains = <&CPU_PD5>; 231 power-domain-names = "psci"; 232 qcom,freq-domain = <&cpufreq_hw 1>; 233 operating-points-v2 = <&cpu4_opp_table>; 234 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 235 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 236 #cooling-cells = <2>; 237 L2_500: l2-cache { 238 compatible = "cache"; 239 cache-level = <2>; 240 cache-size = <0x40000>; 241 cache-unified; 242 next-level-cache = <&L3_0>; 243 }; 244 245 }; 246 247 CPU6: cpu@600 { 248 device_type = "cpu"; 249 compatible = "qcom,kryo485"; 250 reg = <0x0 0x600>; 251 enable-method = "psci"; 252 capacity-dmips-mhz = <1024>; 253 dynamic-power-coefficient = <379>; 254 next-level-cache = <&L2_600>; 255 power-domains = <&CPU_PD6>; 256 power-domain-names = "psci"; 257 qcom,freq-domain = <&cpufreq_hw 1>; 258 operating-points-v2 = <&cpu4_opp_table>; 259 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 260 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 261 #cooling-cells = <2>; 262 L2_600: l2-cache { 263 compatible = "cache"; 264 cache-level = <2>; 265 cache-size = <0x40000>; 266 cache-unified; 267 next-level-cache = <&L3_0>; 268 }; 269 }; 270 271 CPU7: cpu@700 { 272 device_type = "cpu"; 273 compatible = "qcom,kryo485"; 274 reg = <0x0 0x700>; 275 enable-method = "psci"; 276 capacity-dmips-mhz = <1024>; 277 dynamic-power-coefficient = <444>; 278 next-level-cache = <&L2_700>; 279 power-domains = <&CPU_PD7>; 280 power-domain-names = "psci"; 281 qcom,freq-domain = <&cpufreq_hw 2>; 282 operating-points-v2 = <&cpu7_opp_table>; 283 interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>, 284 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 285 #cooling-cells = <2>; 286 L2_700: l2-cache { 287 compatible = "cache"; 288 cache-level = <2>; 289 cache-size = <0x80000>; 290 cache-unified; 291 next-level-cache = <&L3_0>; 292 }; 293 }; 294 295 cpu-map { 296 cluster0 { 297 core0 { 298 cpu = <&CPU0>; 299 }; 300 301 core1 { 302 cpu = <&CPU1>; 303 }; 304 305 core2 { 306 cpu = <&CPU2>; 307 }; 308 309 core3 { 310 cpu = <&CPU3>; 311 }; 312 313 core4 { 314 cpu = <&CPU4>; 315 }; 316 317 core5 { 318 cpu = <&CPU5>; 319 }; 320 321 core6 { 322 cpu = <&CPU6>; 323 }; 324 325 core7 { 326 cpu = <&CPU7>; 327 }; 328 }; 329 }; 330 331 idle-states { 332 entry-method = "psci"; 333 334 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 335 compatible = "arm,idle-state"; 336 idle-state-name = "silver-rail-power-collapse"; 337 arm,psci-suspend-param = <0x40000004>; 338 entry-latency-us = <360>; 339 exit-latency-us = <531>; 340 min-residency-us = <3934>; 341 local-timer-stop; 342 }; 343 344 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 345 compatible = "arm,idle-state"; 346 idle-state-name = "gold-rail-power-collapse"; 347 arm,psci-suspend-param = <0x40000004>; 348 entry-latency-us = <702>; 349 exit-latency-us = <1061>; 350 min-residency-us = <4488>; 351 local-timer-stop; 352 }; 353 }; 354 355 domain-idle-states { 356 CLUSTER_SLEEP_0: cluster-sleep-0 { 357 compatible = "domain-idle-state"; 358 idle-state-name = "cluster-llcc-off"; 359 arm,psci-suspend-param = <0x4100c244>; 360 entry-latency-us = <3264>; 361 exit-latency-us = <6562>; 362 min-residency-us = <9987>; 363 local-timer-stop; 364 }; 365 }; 366 }; 367 368 cpu0_opp_table: opp-table-cpu0 { 369 compatible = "operating-points-v2"; 370 opp-shared; 371 372 cpu0_opp1: opp-300000000 { 373 opp-hz = /bits/ 64 <300000000>; 374 opp-peak-kBps = <800000 9600000>; 375 }; 376 377 cpu0_opp2: opp-403200000 { 378 opp-hz = /bits/ 64 <403200000>; 379 opp-peak-kBps = <800000 9600000>; 380 }; 381 382 cpu0_opp3: opp-518400000 { 383 opp-hz = /bits/ 64 <518400000>; 384 opp-peak-kBps = <800000 16588800>; 385 }; 386 387 cpu0_opp4: opp-614400000 { 388 opp-hz = /bits/ 64 <614400000>; 389 opp-peak-kBps = <800000 16588800>; 390 }; 391 392 cpu0_opp5: opp-691200000 { 393 opp-hz = /bits/ 64 <691200000>; 394 opp-peak-kBps = <800000 19660800>; 395 }; 396 397 cpu0_opp6: opp-787200000 { 398 opp-hz = /bits/ 64 <787200000>; 399 opp-peak-kBps = <1804000 19660800>; 400 }; 401 402 cpu0_opp7: opp-883200000 { 403 opp-hz = /bits/ 64 <883200000>; 404 opp-peak-kBps = <1804000 23347200>; 405 }; 406 407 cpu0_opp8: opp-979200000 { 408 opp-hz = /bits/ 64 <979200000>; 409 opp-peak-kBps = <1804000 26419200>; 410 }; 411 412 cpu0_opp9: opp-1075200000 { 413 opp-hz = /bits/ 64 <1075200000>; 414 opp-peak-kBps = <1804000 29491200>; 415 }; 416 417 cpu0_opp10: opp-1171200000 { 418 opp-hz = /bits/ 64 <1171200000>; 419 opp-peak-kBps = <1804000 32563200>; 420 }; 421 422 cpu0_opp11: opp-1248000000 { 423 opp-hz = /bits/ 64 <1248000000>; 424 opp-peak-kBps = <1804000 36249600>; 425 }; 426 427 cpu0_opp12: opp-1344000000 { 428 opp-hz = /bits/ 64 <1344000000>; 429 opp-peak-kBps = <2188000 36249600>; 430 }; 431 432 cpu0_opp13: opp-1420800000 { 433 opp-hz = /bits/ 64 <1420800000>; 434 opp-peak-kBps = <2188000 39321600>; 435 }; 436 437 cpu0_opp14: opp-1516800000 { 438 opp-hz = /bits/ 64 <1516800000>; 439 opp-peak-kBps = <3072000 42393600>; 440 }; 441 442 cpu0_opp15: opp-1612800000 { 443 opp-hz = /bits/ 64 <1612800000>; 444 opp-peak-kBps = <3072000 42393600>; 445 }; 446 447 cpu0_opp16: opp-1708800000 { 448 opp-hz = /bits/ 64 <1708800000>; 449 opp-peak-kBps = <4068000 42393600>; 450 }; 451 452 cpu0_opp17: opp-1804800000 { 453 opp-hz = /bits/ 64 <1804800000>; 454 opp-peak-kBps = <4068000 42393600>; 455 }; 456 }; 457 458 cpu4_opp_table: opp-table-cpu4 { 459 compatible = "operating-points-v2"; 460 opp-shared; 461 462 cpu4_opp1: opp-710400000 { 463 opp-hz = /bits/ 64 <710400000>; 464 opp-peak-kBps = <1804000 19660800>; 465 }; 466 467 cpu4_opp2: opp-825600000 { 468 opp-hz = /bits/ 64 <825600000>; 469 opp-peak-kBps = <2188000 23347200>; 470 }; 471 472 cpu4_opp3: opp-940800000 { 473 opp-hz = /bits/ 64 <940800000>; 474 opp-peak-kBps = <2188000 26419200>; 475 }; 476 477 cpu4_opp4: opp-1056000000 { 478 opp-hz = /bits/ 64 <1056000000>; 479 opp-peak-kBps = <3072000 26419200>; 480 }; 481 482 cpu4_opp5: opp-1171200000 { 483 opp-hz = /bits/ 64 <1171200000>; 484 opp-peak-kBps = <3072000 29491200>; 485 }; 486 487 cpu4_opp6: opp-1286400000 { 488 opp-hz = /bits/ 64 <1286400000>; 489 opp-peak-kBps = <4068000 29491200>; 490 }; 491 492 cpu4_opp7: opp-1382400000 { 493 opp-hz = /bits/ 64 <1382400000>; 494 opp-peak-kBps = <4068000 32563200>; 495 }; 496 497 cpu4_opp8: opp-1478400000 { 498 opp-hz = /bits/ 64 <1478400000>; 499 opp-peak-kBps = <4068000 32563200>; 500 }; 501 502 cpu4_opp9: opp-1574400000 { 503 opp-hz = /bits/ 64 <1574400000>; 504 opp-peak-kBps = <5412000 39321600>; 505 }; 506 507 cpu4_opp10: opp-1670400000 { 508 opp-hz = /bits/ 64 <1670400000>; 509 opp-peak-kBps = <5412000 42393600>; 510 }; 511 512 cpu4_opp11: opp-1766400000 { 513 opp-hz = /bits/ 64 <1766400000>; 514 opp-peak-kBps = <5412000 45465600>; 515 }; 516 517 cpu4_opp12: opp-1862400000 { 518 opp-hz = /bits/ 64 <1862400000>; 519 opp-peak-kBps = <6220000 45465600>; 520 }; 521 522 cpu4_opp13: opp-1958400000 { 523 opp-hz = /bits/ 64 <1958400000>; 524 opp-peak-kBps = <6220000 48537600>; 525 }; 526 527 cpu4_opp14: opp-2054400000 { 528 opp-hz = /bits/ 64 <2054400000>; 529 opp-peak-kBps = <7216000 48537600>; 530 }; 531 532 cpu4_opp15: opp-2150400000 { 533 opp-hz = /bits/ 64 <2150400000>; 534 opp-peak-kBps = <7216000 51609600>; 535 }; 536 537 cpu4_opp16: opp-2246400000 { 538 opp-hz = /bits/ 64 <2246400000>; 539 opp-peak-kBps = <7216000 51609600>; 540 }; 541 542 cpu4_opp17: opp-2342400000 { 543 opp-hz = /bits/ 64 <2342400000>; 544 opp-peak-kBps = <8368000 51609600>; 545 }; 546 547 cpu4_opp18: opp-2419200000 { 548 opp-hz = /bits/ 64 <2419200000>; 549 opp-peak-kBps = <8368000 51609600>; 550 }; 551 }; 552 553 cpu7_opp_table: opp-table-cpu7 { 554 compatible = "operating-points-v2"; 555 opp-shared; 556 557 cpu7_opp1: opp-844800000 { 558 opp-hz = /bits/ 64 <844800000>; 559 opp-peak-kBps = <2188000 19660800>; 560 }; 561 562 cpu7_opp2: opp-960000000 { 563 opp-hz = /bits/ 64 <960000000>; 564 opp-peak-kBps = <2188000 26419200>; 565 }; 566 567 cpu7_opp3: opp-1075200000 { 568 opp-hz = /bits/ 64 <1075200000>; 569 opp-peak-kBps = <3072000 26419200>; 570 }; 571 572 cpu7_opp4: opp-1190400000 { 573 opp-hz = /bits/ 64 <1190400000>; 574 opp-peak-kBps = <3072000 29491200>; 575 }; 576 577 cpu7_opp5: opp-1305600000 { 578 opp-hz = /bits/ 64 <1305600000>; 579 opp-peak-kBps = <4068000 32563200>; 580 }; 581 582 cpu7_opp6: opp-1401600000 { 583 opp-hz = /bits/ 64 <1401600000>; 584 opp-peak-kBps = <4068000 32563200>; 585 }; 586 587 cpu7_opp7: opp-1516800000 { 588 opp-hz = /bits/ 64 <1516800000>; 589 opp-peak-kBps = <4068000 36249600>; 590 }; 591 592 cpu7_opp8: opp-1632000000 { 593 opp-hz = /bits/ 64 <1632000000>; 594 opp-peak-kBps = <5412000 39321600>; 595 }; 596 597 cpu7_opp9: opp-1747200000 { 598 opp-hz = /bits/ 64 <1708800000>; 599 opp-peak-kBps = <5412000 42393600>; 600 }; 601 602 cpu7_opp10: opp-1862400000 { 603 opp-hz = /bits/ 64 <1862400000>; 604 opp-peak-kBps = <6220000 45465600>; 605 }; 606 607 cpu7_opp11: opp-1977600000 { 608 opp-hz = /bits/ 64 <1977600000>; 609 opp-peak-kBps = <6220000 48537600>; 610 }; 611 612 cpu7_opp12: opp-2073600000 { 613 opp-hz = /bits/ 64 <2073600000>; 614 opp-peak-kBps = <7216000 48537600>; 615 }; 616 617 cpu7_opp13: opp-2169600000 { 618 opp-hz = /bits/ 64 <2169600000>; 619 opp-peak-kBps = <7216000 51609600>; 620 }; 621 622 cpu7_opp14: opp-2265600000 { 623 opp-hz = /bits/ 64 <2265600000>; 624 opp-peak-kBps = <7216000 51609600>; 625 }; 626 627 cpu7_opp15: opp-2361600000 { 628 opp-hz = /bits/ 64 <2361600000>; 629 opp-peak-kBps = <8368000 51609600>; 630 }; 631 632 cpu7_opp16: opp-2457600000 { 633 opp-hz = /bits/ 64 <2457600000>; 634 opp-peak-kBps = <8368000 51609600>; 635 }; 636 637 cpu7_opp17: opp-2553600000 { 638 opp-hz = /bits/ 64 <2553600000>; 639 opp-peak-kBps = <8368000 51609600>; 640 }; 641 642 cpu7_opp18: opp-2649600000 { 643 opp-hz = /bits/ 64 <2649600000>; 644 opp-peak-kBps = <8368000 51609600>; 645 }; 646 647 cpu7_opp19: opp-2745600000 { 648 opp-hz = /bits/ 64 <2745600000>; 649 opp-peak-kBps = <8368000 51609600>; 650 }; 651 652 cpu7_opp20: opp-2841600000 { 653 opp-hz = /bits/ 64 <2841600000>; 654 opp-peak-kBps = <8368000 51609600>; 655 }; 656 }; 657 658 firmware { 659 scm: scm { 660 compatible = "qcom,scm-sm8250", "qcom,scm"; 661 #reset-cells = <1>; 662 }; 663 }; 664 665 memory@80000000 { 666 device_type = "memory"; 667 /* We expect the bootloader to fill in the size */ 668 reg = <0x0 0x80000000 0x0 0x0>; 669 }; 670 671 pmu { 672 compatible = "arm,armv8-pmuv3"; 673 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 674 }; 675 676 psci { 677 compatible = "arm,psci-1.0"; 678 method = "smc"; 679 680 CPU_PD0: power-domain-cpu0 { 681 #power-domain-cells = <0>; 682 power-domains = <&CLUSTER_PD>; 683 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 684 }; 685 686 CPU_PD1: power-domain-cpu1 { 687 #power-domain-cells = <0>; 688 power-domains = <&CLUSTER_PD>; 689 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 690 }; 691 692 CPU_PD2: power-domain-cpu2 { 693 #power-domain-cells = <0>; 694 power-domains = <&CLUSTER_PD>; 695 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 696 }; 697 698 CPU_PD3: power-domain-cpu3 { 699 #power-domain-cells = <0>; 700 power-domains = <&CLUSTER_PD>; 701 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 702 }; 703 704 CPU_PD4: power-domain-cpu4 { 705 #power-domain-cells = <0>; 706 power-domains = <&CLUSTER_PD>; 707 domain-idle-states = <&BIG_CPU_SLEEP_0>; 708 }; 709 710 CPU_PD5: power-domain-cpu5 { 711 #power-domain-cells = <0>; 712 power-domains = <&CLUSTER_PD>; 713 domain-idle-states = <&BIG_CPU_SLEEP_0>; 714 }; 715 716 CPU_PD6: power-domain-cpu6 { 717 #power-domain-cells = <0>; 718 power-domains = <&CLUSTER_PD>; 719 domain-idle-states = <&BIG_CPU_SLEEP_0>; 720 }; 721 722 CPU_PD7: power-domain-cpu7 { 723 #power-domain-cells = <0>; 724 power-domains = <&CLUSTER_PD>; 725 domain-idle-states = <&BIG_CPU_SLEEP_0>; 726 }; 727 728 CLUSTER_PD: power-domain-cpu-cluster0 { 729 #power-domain-cells = <0>; 730 domain-idle-states = <&CLUSTER_SLEEP_0>; 731 }; 732 }; 733 734 qup_opp_table: opp-table-qup { 735 compatible = "operating-points-v2"; 736 737 opp-50000000 { 738 opp-hz = /bits/ 64 <50000000>; 739 required-opps = <&rpmhpd_opp_min_svs>; 740 }; 741 742 opp-75000000 { 743 opp-hz = /bits/ 64 <75000000>; 744 required-opps = <&rpmhpd_opp_low_svs>; 745 }; 746 747 opp-120000000 { 748 opp-hz = /bits/ 64 <120000000>; 749 required-opps = <&rpmhpd_opp_svs>; 750 }; 751 }; 752 753 reserved-memory { 754 #address-cells = <2>; 755 #size-cells = <2>; 756 ranges; 757 758 hyp_mem: memory@80000000 { 759 reg = <0x0 0x80000000 0x0 0x600000>; 760 no-map; 761 }; 762 763 xbl_aop_mem: memory@80700000 { 764 reg = <0x0 0x80700000 0x0 0x160000>; 765 no-map; 766 }; 767 768 cmd_db: memory@80860000 { 769 compatible = "qcom,cmd-db"; 770 reg = <0x0 0x80860000 0x0 0x20000>; 771 no-map; 772 }; 773 774 smem_mem: memory@80900000 { 775 reg = <0x0 0x80900000 0x0 0x200000>; 776 no-map; 777 }; 778 779 removed_mem: memory@80b00000 { 780 reg = <0x0 0x80b00000 0x0 0x5300000>; 781 no-map; 782 }; 783 784 camera_mem: memory@86200000 { 785 reg = <0x0 0x86200000 0x0 0x500000>; 786 no-map; 787 }; 788 789 wlan_mem: memory@86700000 { 790 reg = <0x0 0x86700000 0x0 0x100000>; 791 no-map; 792 }; 793 794 ipa_fw_mem: memory@86800000 { 795 reg = <0x0 0x86800000 0x0 0x10000>; 796 no-map; 797 }; 798 799 ipa_gsi_mem: memory@86810000 { 800 reg = <0x0 0x86810000 0x0 0xa000>; 801 no-map; 802 }; 803 804 gpu_mem: memory@8681a000 { 805 reg = <0x0 0x8681a000 0x0 0x2000>; 806 no-map; 807 }; 808 809 npu_mem: memory@86900000 { 810 reg = <0x0 0x86900000 0x0 0x500000>; 811 no-map; 812 }; 813 814 video_mem: memory@86e00000 { 815 reg = <0x0 0x86e00000 0x0 0x500000>; 816 no-map; 817 }; 818 819 cvp_mem: memory@87300000 { 820 reg = <0x0 0x87300000 0x0 0x500000>; 821 no-map; 822 }; 823 824 cdsp_mem: memory@87800000 { 825 reg = <0x0 0x87800000 0x0 0x1400000>; 826 no-map; 827 }; 828 829 slpi_mem: memory@88c00000 { 830 reg = <0x0 0x88c00000 0x0 0x1500000>; 831 no-map; 832 }; 833 834 adsp_mem: memory@8a100000 { 835 reg = <0x0 0x8a100000 0x0 0x1d00000>; 836 no-map; 837 }; 838 839 spss_mem: memory@8be00000 { 840 reg = <0x0 0x8be00000 0x0 0x100000>; 841 no-map; 842 }; 843 844 cdsp_secure_heap: memory@8bf00000 { 845 reg = <0x0 0x8bf00000 0x0 0x4600000>; 846 no-map; 847 }; 848 }; 849 850 smem { 851 compatible = "qcom,smem"; 852 memory-region = <&smem_mem>; 853 hwlocks = <&tcsr_mutex 3>; 854 }; 855 856 smp2p-adsp { 857 compatible = "qcom,smp2p"; 858 qcom,smem = <443>, <429>; 859 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 860 IPCC_MPROC_SIGNAL_SMP2P 861 IRQ_TYPE_EDGE_RISING>; 862 mboxes = <&ipcc IPCC_CLIENT_LPASS 863 IPCC_MPROC_SIGNAL_SMP2P>; 864 865 qcom,local-pid = <0>; 866 qcom,remote-pid = <2>; 867 868 smp2p_adsp_out: master-kernel { 869 qcom,entry-name = "master-kernel"; 870 #qcom,smem-state-cells = <1>; 871 }; 872 873 smp2p_adsp_in: slave-kernel { 874 qcom,entry-name = "slave-kernel"; 875 interrupt-controller; 876 #interrupt-cells = <2>; 877 }; 878 }; 879 880 smp2p-cdsp { 881 compatible = "qcom,smp2p"; 882 qcom,smem = <94>, <432>; 883 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 884 IPCC_MPROC_SIGNAL_SMP2P 885 IRQ_TYPE_EDGE_RISING>; 886 mboxes = <&ipcc IPCC_CLIENT_CDSP 887 IPCC_MPROC_SIGNAL_SMP2P>; 888 889 qcom,local-pid = <0>; 890 qcom,remote-pid = <5>; 891 892 smp2p_cdsp_out: master-kernel { 893 qcom,entry-name = "master-kernel"; 894 #qcom,smem-state-cells = <1>; 895 }; 896 897 smp2p_cdsp_in: slave-kernel { 898 qcom,entry-name = "slave-kernel"; 899 interrupt-controller; 900 #interrupt-cells = <2>; 901 }; 902 }; 903 904 smp2p-slpi { 905 compatible = "qcom,smp2p"; 906 qcom,smem = <481>, <430>; 907 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 908 IPCC_MPROC_SIGNAL_SMP2P 909 IRQ_TYPE_EDGE_RISING>; 910 mboxes = <&ipcc IPCC_CLIENT_SLPI 911 IPCC_MPROC_SIGNAL_SMP2P>; 912 913 qcom,local-pid = <0>; 914 qcom,remote-pid = <3>; 915 916 smp2p_slpi_out: master-kernel { 917 qcom,entry-name = "master-kernel"; 918 #qcom,smem-state-cells = <1>; 919 }; 920 921 smp2p_slpi_in: slave-kernel { 922 qcom,entry-name = "slave-kernel"; 923 interrupt-controller; 924 #interrupt-cells = <2>; 925 }; 926 }; 927 928 soc: soc@0 { 929 #address-cells = <2>; 930 #size-cells = <2>; 931 ranges = <0 0 0 0 0x10 0>; 932 dma-ranges = <0 0 0 0 0x10 0>; 933 compatible = "simple-bus"; 934 935 gcc: clock-controller@100000 { 936 compatible = "qcom,gcc-sm8250"; 937 reg = <0x0 0x00100000 0x0 0x1f0000>; 938 #clock-cells = <1>; 939 #reset-cells = <1>; 940 #power-domain-cells = <1>; 941 clock-names = "bi_tcxo", 942 "bi_tcxo_ao", 943 "sleep_clk"; 944 clocks = <&rpmhcc RPMH_CXO_CLK>, 945 <&rpmhcc RPMH_CXO_CLK_A>, 946 <&sleep_clk>; 947 }; 948 949 ipcc: mailbox@408000 { 950 compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; 951 reg = <0 0x00408000 0 0x1000>; 952 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 953 interrupt-controller; 954 #interrupt-cells = <3>; 955 #mbox-cells = <2>; 956 }; 957 958 rng: rng@793000 { 959 compatible = "qcom,prng-ee"; 960 reg = <0 0x00793000 0 0x1000>; 961 clocks = <&gcc GCC_PRNG_AHB_CLK>; 962 clock-names = "core"; 963 }; 964 965 gpi_dma2: dma-controller@800000 { 966 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 967 reg = <0 0x00800000 0 0x70000>; 968 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 975 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 976 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 977 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; 978 dma-channels = <10>; 979 dma-channel-mask = <0x3f>; 980 iommus = <&apps_smmu 0x76 0x0>; 981 #dma-cells = <3>; 982 status = "disabled"; 983 }; 984 985 qupv3_id_2: geniqup@8c0000 { 986 compatible = "qcom,geni-se-qup"; 987 reg = <0x0 0x008c0000 0x0 0x6000>; 988 clock-names = "m-ahb", "s-ahb"; 989 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 990 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 991 #address-cells = <2>; 992 #size-cells = <2>; 993 iommus = <&apps_smmu 0x63 0x0>; 994 ranges; 995 status = "disabled"; 996 997 i2c14: i2c@880000 { 998 compatible = "qcom,geni-i2c"; 999 reg = <0 0x00880000 0 0x4000>; 1000 clock-names = "se"; 1001 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1002 pinctrl-names = "default"; 1003 pinctrl-0 = <&qup_i2c14_default>; 1004 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1005 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1006 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1007 dma-names = "tx", "rx"; 1008 #address-cells = <1>; 1009 #size-cells = <0>; 1010 status = "disabled"; 1011 }; 1012 1013 spi14: spi@880000 { 1014 compatible = "qcom,geni-spi"; 1015 reg = <0 0x00880000 0 0x4000>; 1016 clock-names = "se"; 1017 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1018 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1019 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1020 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1021 dma-names = "tx", "rx"; 1022 power-domains = <&rpmhpd SM8250_CX>; 1023 operating-points-v2 = <&qup_opp_table>; 1024 #address-cells = <1>; 1025 #size-cells = <0>; 1026 status = "disabled"; 1027 }; 1028 1029 i2c15: i2c@884000 { 1030 compatible = "qcom,geni-i2c"; 1031 reg = <0 0x00884000 0 0x4000>; 1032 clock-names = "se"; 1033 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1034 pinctrl-names = "default"; 1035 pinctrl-0 = <&qup_i2c15_default>; 1036 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1037 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1038 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1039 dma-names = "tx", "rx"; 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 status = "disabled"; 1043 }; 1044 1045 spi15: spi@884000 { 1046 compatible = "qcom,geni-spi"; 1047 reg = <0 0x00884000 0 0x4000>; 1048 clock-names = "se"; 1049 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1050 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1051 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1052 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1053 dma-names = "tx", "rx"; 1054 power-domains = <&rpmhpd SM8250_CX>; 1055 operating-points-v2 = <&qup_opp_table>; 1056 #address-cells = <1>; 1057 #size-cells = <0>; 1058 status = "disabled"; 1059 }; 1060 1061 i2c16: i2c@888000 { 1062 compatible = "qcom,geni-i2c"; 1063 reg = <0 0x00888000 0 0x4000>; 1064 clock-names = "se"; 1065 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1066 pinctrl-names = "default"; 1067 pinctrl-0 = <&qup_i2c16_default>; 1068 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1069 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1070 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1071 dma-names = "tx", "rx"; 1072 #address-cells = <1>; 1073 #size-cells = <0>; 1074 status = "disabled"; 1075 }; 1076 1077 spi16: spi@888000 { 1078 compatible = "qcom,geni-spi"; 1079 reg = <0 0x00888000 0 0x4000>; 1080 clock-names = "se"; 1081 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1082 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1083 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1084 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1085 dma-names = "tx", "rx"; 1086 power-domains = <&rpmhpd SM8250_CX>; 1087 operating-points-v2 = <&qup_opp_table>; 1088 #address-cells = <1>; 1089 #size-cells = <0>; 1090 status = "disabled"; 1091 }; 1092 1093 i2c17: i2c@88c000 { 1094 compatible = "qcom,geni-i2c"; 1095 reg = <0 0x0088c000 0 0x4000>; 1096 clock-names = "se"; 1097 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1098 pinctrl-names = "default"; 1099 pinctrl-0 = <&qup_i2c17_default>; 1100 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1101 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1102 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1103 dma-names = "tx", "rx"; 1104 #address-cells = <1>; 1105 #size-cells = <0>; 1106 status = "disabled"; 1107 }; 1108 1109 spi17: spi@88c000 { 1110 compatible = "qcom,geni-spi"; 1111 reg = <0 0x0088c000 0 0x4000>; 1112 clock-names = "se"; 1113 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1114 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1115 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1116 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1117 dma-names = "tx", "rx"; 1118 power-domains = <&rpmhpd SM8250_CX>; 1119 operating-points-v2 = <&qup_opp_table>; 1120 #address-cells = <1>; 1121 #size-cells = <0>; 1122 status = "disabled"; 1123 }; 1124 1125 uart17: serial@88c000 { 1126 compatible = "qcom,geni-uart"; 1127 reg = <0 0x0088c000 0 0x4000>; 1128 clock-names = "se"; 1129 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1130 pinctrl-names = "default"; 1131 pinctrl-0 = <&qup_uart17_default>; 1132 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1133 power-domains = <&rpmhpd SM8250_CX>; 1134 operating-points-v2 = <&qup_opp_table>; 1135 status = "disabled"; 1136 }; 1137 1138 i2c18: i2c@890000 { 1139 compatible = "qcom,geni-i2c"; 1140 reg = <0 0x00890000 0 0x4000>; 1141 clock-names = "se"; 1142 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1143 pinctrl-names = "default"; 1144 pinctrl-0 = <&qup_i2c18_default>; 1145 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1146 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1147 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1148 dma-names = "tx", "rx"; 1149 #address-cells = <1>; 1150 #size-cells = <0>; 1151 status = "disabled"; 1152 }; 1153 1154 spi18: spi@890000 { 1155 compatible = "qcom,geni-spi"; 1156 reg = <0 0x00890000 0 0x4000>; 1157 clock-names = "se"; 1158 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1159 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1160 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1161 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1162 dma-names = "tx", "rx"; 1163 power-domains = <&rpmhpd SM8250_CX>; 1164 operating-points-v2 = <&qup_opp_table>; 1165 #address-cells = <1>; 1166 #size-cells = <0>; 1167 status = "disabled"; 1168 }; 1169 1170 uart18: serial@890000 { 1171 compatible = "qcom,geni-uart"; 1172 reg = <0 0x00890000 0 0x4000>; 1173 clock-names = "se"; 1174 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1175 pinctrl-names = "default"; 1176 pinctrl-0 = <&qup_uart18_default>; 1177 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1178 power-domains = <&rpmhpd SM8250_CX>; 1179 operating-points-v2 = <&qup_opp_table>; 1180 status = "disabled"; 1181 }; 1182 1183 i2c19: i2c@894000 { 1184 compatible = "qcom,geni-i2c"; 1185 reg = <0 0x00894000 0 0x4000>; 1186 clock-names = "se"; 1187 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1188 pinctrl-names = "default"; 1189 pinctrl-0 = <&qup_i2c19_default>; 1190 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1191 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1192 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1193 dma-names = "tx", "rx"; 1194 #address-cells = <1>; 1195 #size-cells = <0>; 1196 status = "disabled"; 1197 }; 1198 1199 spi19: spi@894000 { 1200 compatible = "qcom,geni-spi"; 1201 reg = <0 0x00894000 0 0x4000>; 1202 clock-names = "se"; 1203 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1204 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1205 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1206 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1207 dma-names = "tx", "rx"; 1208 power-domains = <&rpmhpd SM8250_CX>; 1209 operating-points-v2 = <&qup_opp_table>; 1210 #address-cells = <1>; 1211 #size-cells = <0>; 1212 status = "disabled"; 1213 }; 1214 }; 1215 1216 gpi_dma0: dma-controller@900000 { 1217 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 1218 reg = <0 0x00900000 0 0x70000>; 1219 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1232 dma-channels = <15>; 1233 dma-channel-mask = <0x7ff>; 1234 iommus = <&apps_smmu 0x5b6 0x0>; 1235 #dma-cells = <3>; 1236 status = "disabled"; 1237 }; 1238 1239 qupv3_id_0: geniqup@9c0000 { 1240 compatible = "qcom,geni-se-qup"; 1241 reg = <0x0 0x009c0000 0x0 0x6000>; 1242 clock-names = "m-ahb", "s-ahb"; 1243 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1244 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1245 #address-cells = <2>; 1246 #size-cells = <2>; 1247 iommus = <&apps_smmu 0x5a3 0x0>; 1248 ranges; 1249 status = "disabled"; 1250 1251 i2c0: i2c@980000 { 1252 compatible = "qcom,geni-i2c"; 1253 reg = <0 0x00980000 0 0x4000>; 1254 clock-names = "se"; 1255 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1256 pinctrl-names = "default"; 1257 pinctrl-0 = <&qup_i2c0_default>; 1258 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1259 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1260 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1261 dma-names = "tx", "rx"; 1262 #address-cells = <1>; 1263 #size-cells = <0>; 1264 status = "disabled"; 1265 }; 1266 1267 spi0: spi@980000 { 1268 compatible = "qcom,geni-spi"; 1269 reg = <0 0x00980000 0 0x4000>; 1270 clock-names = "se"; 1271 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1272 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1273 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1274 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1275 dma-names = "tx", "rx"; 1276 power-domains = <&rpmhpd SM8250_CX>; 1277 operating-points-v2 = <&qup_opp_table>; 1278 #address-cells = <1>; 1279 #size-cells = <0>; 1280 status = "disabled"; 1281 }; 1282 1283 i2c1: i2c@984000 { 1284 compatible = "qcom,geni-i2c"; 1285 reg = <0 0x00984000 0 0x4000>; 1286 clock-names = "se"; 1287 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1288 pinctrl-names = "default"; 1289 pinctrl-0 = <&qup_i2c1_default>; 1290 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1291 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1292 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1293 dma-names = "tx", "rx"; 1294 #address-cells = <1>; 1295 #size-cells = <0>; 1296 status = "disabled"; 1297 }; 1298 1299 spi1: spi@984000 { 1300 compatible = "qcom,geni-spi"; 1301 reg = <0 0x00984000 0 0x4000>; 1302 clock-names = "se"; 1303 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1304 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1305 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1306 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1307 dma-names = "tx", "rx"; 1308 power-domains = <&rpmhpd SM8250_CX>; 1309 operating-points-v2 = <&qup_opp_table>; 1310 #address-cells = <1>; 1311 #size-cells = <0>; 1312 status = "disabled"; 1313 }; 1314 1315 i2c2: i2c@988000 { 1316 compatible = "qcom,geni-i2c"; 1317 reg = <0 0x00988000 0 0x4000>; 1318 clock-names = "se"; 1319 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1320 pinctrl-names = "default"; 1321 pinctrl-0 = <&qup_i2c2_default>; 1322 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1323 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1324 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1325 dma-names = "tx", "rx"; 1326 #address-cells = <1>; 1327 #size-cells = <0>; 1328 status = "disabled"; 1329 }; 1330 1331 spi2: spi@988000 { 1332 compatible = "qcom,geni-spi"; 1333 reg = <0 0x00988000 0 0x4000>; 1334 clock-names = "se"; 1335 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1336 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1337 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1338 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1339 dma-names = "tx", "rx"; 1340 power-domains = <&rpmhpd SM8250_CX>; 1341 operating-points-v2 = <&qup_opp_table>; 1342 #address-cells = <1>; 1343 #size-cells = <0>; 1344 status = "disabled"; 1345 }; 1346 1347 uart2: serial@988000 { 1348 compatible = "qcom,geni-debug-uart"; 1349 reg = <0 0x00988000 0 0x4000>; 1350 clock-names = "se"; 1351 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1352 pinctrl-names = "default"; 1353 pinctrl-0 = <&qup_uart2_default>; 1354 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1355 power-domains = <&rpmhpd SM8250_CX>; 1356 operating-points-v2 = <&qup_opp_table>; 1357 status = "disabled"; 1358 }; 1359 1360 i2c3: i2c@98c000 { 1361 compatible = "qcom,geni-i2c"; 1362 reg = <0 0x0098c000 0 0x4000>; 1363 clock-names = "se"; 1364 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1365 pinctrl-names = "default"; 1366 pinctrl-0 = <&qup_i2c3_default>; 1367 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1368 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1369 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1370 dma-names = "tx", "rx"; 1371 #address-cells = <1>; 1372 #size-cells = <0>; 1373 status = "disabled"; 1374 }; 1375 1376 spi3: spi@98c000 { 1377 compatible = "qcom,geni-spi"; 1378 reg = <0 0x0098c000 0 0x4000>; 1379 clock-names = "se"; 1380 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1381 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1382 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1383 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1384 dma-names = "tx", "rx"; 1385 power-domains = <&rpmhpd SM8250_CX>; 1386 operating-points-v2 = <&qup_opp_table>; 1387 #address-cells = <1>; 1388 #size-cells = <0>; 1389 status = "disabled"; 1390 }; 1391 1392 i2c4: i2c@990000 { 1393 compatible = "qcom,geni-i2c"; 1394 reg = <0 0x00990000 0 0x4000>; 1395 clock-names = "se"; 1396 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1397 pinctrl-names = "default"; 1398 pinctrl-0 = <&qup_i2c4_default>; 1399 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1400 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1401 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1402 dma-names = "tx", "rx"; 1403 #address-cells = <1>; 1404 #size-cells = <0>; 1405 status = "disabled"; 1406 }; 1407 1408 spi4: spi@990000 { 1409 compatible = "qcom,geni-spi"; 1410 reg = <0 0x00990000 0 0x4000>; 1411 clock-names = "se"; 1412 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1413 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1414 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1415 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1416 dma-names = "tx", "rx"; 1417 power-domains = <&rpmhpd SM8250_CX>; 1418 operating-points-v2 = <&qup_opp_table>; 1419 #address-cells = <1>; 1420 #size-cells = <0>; 1421 status = "disabled"; 1422 }; 1423 1424 i2c5: i2c@994000 { 1425 compatible = "qcom,geni-i2c"; 1426 reg = <0 0x00994000 0 0x4000>; 1427 clock-names = "se"; 1428 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1429 pinctrl-names = "default"; 1430 pinctrl-0 = <&qup_i2c5_default>; 1431 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1432 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1433 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1434 dma-names = "tx", "rx"; 1435 #address-cells = <1>; 1436 #size-cells = <0>; 1437 status = "disabled"; 1438 }; 1439 1440 spi5: spi@994000 { 1441 compatible = "qcom,geni-spi"; 1442 reg = <0 0x00994000 0 0x4000>; 1443 clock-names = "se"; 1444 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1445 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1446 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1447 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1448 dma-names = "tx", "rx"; 1449 power-domains = <&rpmhpd SM8250_CX>; 1450 operating-points-v2 = <&qup_opp_table>; 1451 #address-cells = <1>; 1452 #size-cells = <0>; 1453 status = "disabled"; 1454 }; 1455 1456 i2c6: i2c@998000 { 1457 compatible = "qcom,geni-i2c"; 1458 reg = <0 0x00998000 0 0x4000>; 1459 clock-names = "se"; 1460 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1461 pinctrl-names = "default"; 1462 pinctrl-0 = <&qup_i2c6_default>; 1463 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1464 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1465 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1466 dma-names = "tx", "rx"; 1467 #address-cells = <1>; 1468 #size-cells = <0>; 1469 status = "disabled"; 1470 }; 1471 1472 spi6: spi@998000 { 1473 compatible = "qcom,geni-spi"; 1474 reg = <0 0x00998000 0 0x4000>; 1475 clock-names = "se"; 1476 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1477 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1478 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1479 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1480 dma-names = "tx", "rx"; 1481 power-domains = <&rpmhpd SM8250_CX>; 1482 operating-points-v2 = <&qup_opp_table>; 1483 #address-cells = <1>; 1484 #size-cells = <0>; 1485 status = "disabled"; 1486 }; 1487 1488 uart6: serial@998000 { 1489 compatible = "qcom,geni-uart"; 1490 reg = <0 0x00998000 0 0x4000>; 1491 clock-names = "se"; 1492 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1493 pinctrl-names = "default"; 1494 pinctrl-0 = <&qup_uart6_default>; 1495 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1496 power-domains = <&rpmhpd SM8250_CX>; 1497 operating-points-v2 = <&qup_opp_table>; 1498 status = "disabled"; 1499 }; 1500 1501 i2c7: i2c@99c000 { 1502 compatible = "qcom,geni-i2c"; 1503 reg = <0 0x0099c000 0 0x4000>; 1504 clock-names = "se"; 1505 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1506 pinctrl-names = "default"; 1507 pinctrl-0 = <&qup_i2c7_default>; 1508 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1509 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1510 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1511 dma-names = "tx", "rx"; 1512 #address-cells = <1>; 1513 #size-cells = <0>; 1514 status = "disabled"; 1515 }; 1516 1517 spi7: spi@99c000 { 1518 compatible = "qcom,geni-spi"; 1519 reg = <0 0x0099c000 0 0x4000>; 1520 clock-names = "se"; 1521 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1522 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1523 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1524 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1525 dma-names = "tx", "rx"; 1526 power-domains = <&rpmhpd SM8250_CX>; 1527 operating-points-v2 = <&qup_opp_table>; 1528 #address-cells = <1>; 1529 #size-cells = <0>; 1530 status = "disabled"; 1531 }; 1532 }; 1533 1534 gpi_dma1: dma-controller@a00000 { 1535 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 1536 reg = <0 0x00a00000 0 0x70000>; 1537 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1540 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1541 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1542 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1543 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1544 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1545 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1546 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; 1547 dma-channels = <10>; 1548 dma-channel-mask = <0x3f>; 1549 iommus = <&apps_smmu 0x56 0x0>; 1550 #dma-cells = <3>; 1551 status = "disabled"; 1552 }; 1553 1554 qupv3_id_1: geniqup@ac0000 { 1555 compatible = "qcom,geni-se-qup"; 1556 reg = <0x0 0x00ac0000 0x0 0x6000>; 1557 clock-names = "m-ahb", "s-ahb"; 1558 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1559 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1560 #address-cells = <2>; 1561 #size-cells = <2>; 1562 iommus = <&apps_smmu 0x43 0x0>; 1563 ranges; 1564 status = "disabled"; 1565 1566 i2c8: i2c@a80000 { 1567 compatible = "qcom,geni-i2c"; 1568 reg = <0 0x00a80000 0 0x4000>; 1569 clock-names = "se"; 1570 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1571 pinctrl-names = "default"; 1572 pinctrl-0 = <&qup_i2c8_default>; 1573 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1574 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1575 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1576 dma-names = "tx", "rx"; 1577 #address-cells = <1>; 1578 #size-cells = <0>; 1579 status = "disabled"; 1580 }; 1581 1582 spi8: spi@a80000 { 1583 compatible = "qcom,geni-spi"; 1584 reg = <0 0x00a80000 0 0x4000>; 1585 clock-names = "se"; 1586 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1587 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1588 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1589 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1590 dma-names = "tx", "rx"; 1591 power-domains = <&rpmhpd SM8250_CX>; 1592 operating-points-v2 = <&qup_opp_table>; 1593 #address-cells = <1>; 1594 #size-cells = <0>; 1595 status = "disabled"; 1596 }; 1597 1598 i2c9: i2c@a84000 { 1599 compatible = "qcom,geni-i2c"; 1600 reg = <0 0x00a84000 0 0x4000>; 1601 clock-names = "se"; 1602 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1603 pinctrl-names = "default"; 1604 pinctrl-0 = <&qup_i2c9_default>; 1605 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1606 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1607 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1608 dma-names = "tx", "rx"; 1609 #address-cells = <1>; 1610 #size-cells = <0>; 1611 status = "disabled"; 1612 }; 1613 1614 spi9: spi@a84000 { 1615 compatible = "qcom,geni-spi"; 1616 reg = <0 0x00a84000 0 0x4000>; 1617 clock-names = "se"; 1618 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1619 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1620 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1621 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1622 dma-names = "tx", "rx"; 1623 power-domains = <&rpmhpd SM8250_CX>; 1624 operating-points-v2 = <&qup_opp_table>; 1625 #address-cells = <1>; 1626 #size-cells = <0>; 1627 status = "disabled"; 1628 }; 1629 1630 i2c10: i2c@a88000 { 1631 compatible = "qcom,geni-i2c"; 1632 reg = <0 0x00a88000 0 0x4000>; 1633 clock-names = "se"; 1634 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1635 pinctrl-names = "default"; 1636 pinctrl-0 = <&qup_i2c10_default>; 1637 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1638 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1639 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1640 dma-names = "tx", "rx"; 1641 #address-cells = <1>; 1642 #size-cells = <0>; 1643 status = "disabled"; 1644 }; 1645 1646 spi10: spi@a88000 { 1647 compatible = "qcom,geni-spi"; 1648 reg = <0 0x00a88000 0 0x4000>; 1649 clock-names = "se"; 1650 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1651 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1652 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1653 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1654 dma-names = "tx", "rx"; 1655 power-domains = <&rpmhpd SM8250_CX>; 1656 operating-points-v2 = <&qup_opp_table>; 1657 #address-cells = <1>; 1658 #size-cells = <0>; 1659 status = "disabled"; 1660 }; 1661 1662 i2c11: i2c@a8c000 { 1663 compatible = "qcom,geni-i2c"; 1664 reg = <0 0x00a8c000 0 0x4000>; 1665 clock-names = "se"; 1666 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1667 pinctrl-names = "default"; 1668 pinctrl-0 = <&qup_i2c11_default>; 1669 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1670 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1671 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1672 dma-names = "tx", "rx"; 1673 #address-cells = <1>; 1674 #size-cells = <0>; 1675 status = "disabled"; 1676 }; 1677 1678 spi11: spi@a8c000 { 1679 compatible = "qcom,geni-spi"; 1680 reg = <0 0x00a8c000 0 0x4000>; 1681 clock-names = "se"; 1682 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1683 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1684 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1685 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1686 dma-names = "tx", "rx"; 1687 power-domains = <&rpmhpd SM8250_CX>; 1688 operating-points-v2 = <&qup_opp_table>; 1689 #address-cells = <1>; 1690 #size-cells = <0>; 1691 status = "disabled"; 1692 }; 1693 1694 i2c12: i2c@a90000 { 1695 compatible = "qcom,geni-i2c"; 1696 reg = <0 0x00a90000 0 0x4000>; 1697 clock-names = "se"; 1698 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1699 pinctrl-names = "default"; 1700 pinctrl-0 = <&qup_i2c12_default>; 1701 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1702 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1703 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1704 dma-names = "tx", "rx"; 1705 #address-cells = <1>; 1706 #size-cells = <0>; 1707 status = "disabled"; 1708 }; 1709 1710 spi12: spi@a90000 { 1711 compatible = "qcom,geni-spi"; 1712 reg = <0 0x00a90000 0 0x4000>; 1713 clock-names = "se"; 1714 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1715 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1716 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1717 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1718 dma-names = "tx", "rx"; 1719 power-domains = <&rpmhpd SM8250_CX>; 1720 operating-points-v2 = <&qup_opp_table>; 1721 #address-cells = <1>; 1722 #size-cells = <0>; 1723 status = "disabled"; 1724 }; 1725 1726 uart12: serial@a90000 { 1727 compatible = "qcom,geni-debug-uart"; 1728 reg = <0x0 0x00a90000 0x0 0x4000>; 1729 clock-names = "se"; 1730 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1731 pinctrl-names = "default"; 1732 pinctrl-0 = <&qup_uart12_default>; 1733 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1734 power-domains = <&rpmhpd SM8250_CX>; 1735 operating-points-v2 = <&qup_opp_table>; 1736 status = "disabled"; 1737 }; 1738 1739 i2c13: i2c@a94000 { 1740 compatible = "qcom,geni-i2c"; 1741 reg = <0 0x00a94000 0 0x4000>; 1742 clock-names = "se"; 1743 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1744 pinctrl-names = "default"; 1745 pinctrl-0 = <&qup_i2c13_default>; 1746 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1747 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1748 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1749 dma-names = "tx", "rx"; 1750 #address-cells = <1>; 1751 #size-cells = <0>; 1752 status = "disabled"; 1753 }; 1754 1755 spi13: spi@a94000 { 1756 compatible = "qcom,geni-spi"; 1757 reg = <0 0x00a94000 0 0x4000>; 1758 clock-names = "se"; 1759 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1760 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1761 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1762 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1763 dma-names = "tx", "rx"; 1764 power-domains = <&rpmhpd SM8250_CX>; 1765 operating-points-v2 = <&qup_opp_table>; 1766 #address-cells = <1>; 1767 #size-cells = <0>; 1768 status = "disabled"; 1769 }; 1770 }; 1771 1772 config_noc: interconnect@1500000 { 1773 compatible = "qcom,sm8250-config-noc"; 1774 reg = <0 0x01500000 0 0xa580>; 1775 #interconnect-cells = <1>; 1776 qcom,bcm-voters = <&apps_bcm_voter>; 1777 }; 1778 1779 system_noc: interconnect@1620000 { 1780 compatible = "qcom,sm8250-system-noc"; 1781 reg = <0 0x01620000 0 0x1c200>; 1782 #interconnect-cells = <1>; 1783 qcom,bcm-voters = <&apps_bcm_voter>; 1784 }; 1785 1786 mc_virt: interconnect@163d000 { 1787 compatible = "qcom,sm8250-mc-virt"; 1788 reg = <0 0x0163d000 0 0x1000>; 1789 #interconnect-cells = <1>; 1790 qcom,bcm-voters = <&apps_bcm_voter>; 1791 }; 1792 1793 aggre1_noc: interconnect@16e0000 { 1794 compatible = "qcom,sm8250-aggre1-noc"; 1795 reg = <0 0x016e0000 0 0x1f180>; 1796 #interconnect-cells = <1>; 1797 qcom,bcm-voters = <&apps_bcm_voter>; 1798 }; 1799 1800 aggre2_noc: interconnect@1700000 { 1801 compatible = "qcom,sm8250-aggre2-noc"; 1802 reg = <0 0x01700000 0 0x33000>; 1803 #interconnect-cells = <1>; 1804 qcom,bcm-voters = <&apps_bcm_voter>; 1805 }; 1806 1807 compute_noc: interconnect@1733000 { 1808 compatible = "qcom,sm8250-compute-noc"; 1809 reg = <0 0x01733000 0 0xa180>; 1810 #interconnect-cells = <1>; 1811 qcom,bcm-voters = <&apps_bcm_voter>; 1812 }; 1813 1814 mmss_noc: interconnect@1740000 { 1815 compatible = "qcom,sm8250-mmss-noc"; 1816 reg = <0 0x01740000 0 0x1f080>; 1817 #interconnect-cells = <1>; 1818 qcom,bcm-voters = <&apps_bcm_voter>; 1819 }; 1820 1821 pcie0: pci@1c00000 { 1822 compatible = "qcom,pcie-sm8250"; 1823 reg = <0 0x01c00000 0 0x3000>, 1824 <0 0x60000000 0 0xf1d>, 1825 <0 0x60000f20 0 0xa8>, 1826 <0 0x60001000 0 0x1000>, 1827 <0 0x60100000 0 0x100000>; 1828 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1829 device_type = "pci"; 1830 linux,pci-domain = <0>; 1831 bus-range = <0x00 0xff>; 1832 num-lanes = <1>; 1833 1834 #address-cells = <3>; 1835 #size-cells = <2>; 1836 1837 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1838 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; 1839 1840 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1848 interrupt-names = "msi0", "msi1", "msi2", "msi3", 1849 "msi4", "msi5", "msi6", "msi7"; 1850 #interrupt-cells = <1>; 1851 interrupt-map-mask = <0 0 0 0x7>; 1852 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1853 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1854 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1855 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1856 1857 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1858 <&gcc GCC_PCIE_0_AUX_CLK>, 1859 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1860 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1861 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1862 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1863 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1864 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1865 clock-names = "pipe", 1866 "aux", 1867 "cfg", 1868 "bus_master", 1869 "bus_slave", 1870 "slave_q2a", 1871 "tbu", 1872 "ddrss_sf_tbu"; 1873 1874 iommus = <&apps_smmu 0x1c00 0x7f>; 1875 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1876 <0x100 &apps_smmu 0x1c01 0x1>; 1877 1878 resets = <&gcc GCC_PCIE_0_BCR>; 1879 reset-names = "pci"; 1880 1881 power-domains = <&gcc PCIE_0_GDSC>; 1882 1883 phys = <&pcie0_lane>; 1884 phy-names = "pciephy"; 1885 1886 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; 1887 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; 1888 1889 pinctrl-names = "default"; 1890 pinctrl-0 = <&pcie0_default_state>; 1891 1892 status = "disabled"; 1893 }; 1894 1895 pcie0_phy: phy@1c06000 { 1896 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; 1897 reg = <0 0x01c06000 0 0x1c0>; 1898 #address-cells = <2>; 1899 #size-cells = <2>; 1900 ranges; 1901 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1902 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1903 <&gcc GCC_PCIE_WIFI_CLKREF_EN>, 1904 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1905 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1906 1907 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1908 reset-names = "phy"; 1909 1910 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1911 assigned-clock-rates = <100000000>; 1912 1913 status = "disabled"; 1914 1915 pcie0_lane: phy@1c06200 { 1916 reg = <0 0x01c06200 0 0x170>, /* tx */ 1917 <0 0x01c06400 0 0x200>, /* rx */ 1918 <0 0x01c06800 0 0x1f0>, /* pcs */ 1919 <0 0x01c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ 1920 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1921 clock-names = "pipe0"; 1922 1923 #phy-cells = <0>; 1924 1925 #clock-cells = <0>; 1926 clock-output-names = "pcie_0_pipe_clk"; 1927 }; 1928 }; 1929 1930 pcie1: pci@1c08000 { 1931 compatible = "qcom,pcie-sm8250"; 1932 reg = <0 0x01c08000 0 0x3000>, 1933 <0 0x40000000 0 0xf1d>, 1934 <0 0x40000f20 0 0xa8>, 1935 <0 0x40001000 0 0x1000>, 1936 <0 0x40100000 0 0x100000>; 1937 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1938 device_type = "pci"; 1939 linux,pci-domain = <1>; 1940 bus-range = <0x00 0xff>; 1941 num-lanes = <2>; 1942 1943 #address-cells = <3>; 1944 #size-cells = <2>; 1945 1946 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1947 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1948 1949 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1950 interrupt-names = "msi"; 1951 #interrupt-cells = <1>; 1952 interrupt-map-mask = <0 0 0 0x7>; 1953 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1954 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1955 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1956 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1957 1958 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1959 <&gcc GCC_PCIE_1_AUX_CLK>, 1960 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1961 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1962 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1963 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1964 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 1965 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1966 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 1967 clock-names = "pipe", 1968 "aux", 1969 "cfg", 1970 "bus_master", 1971 "bus_slave", 1972 "slave_q2a", 1973 "ref", 1974 "tbu", 1975 "ddrss_sf_tbu"; 1976 1977 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1978 assigned-clock-rates = <19200000>; 1979 1980 iommus = <&apps_smmu 0x1c80 0x7f>; 1981 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1982 <0x100 &apps_smmu 0x1c81 0x1>; 1983 1984 resets = <&gcc GCC_PCIE_1_BCR>; 1985 reset-names = "pci"; 1986 1987 power-domains = <&gcc PCIE_1_GDSC>; 1988 1989 phys = <&pcie1_lane>; 1990 phy-names = "pciephy"; 1991 1992 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; 1993 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>; 1994 1995 pinctrl-names = "default"; 1996 pinctrl-0 = <&pcie1_default_state>; 1997 1998 status = "disabled"; 1999 }; 2000 2001 pcie1_phy: phy@1c0e000 { 2002 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2003 reg = <0 0x01c0e000 0 0x1c0>; 2004 #address-cells = <2>; 2005 #size-cells = <2>; 2006 ranges; 2007 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2008 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2009 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 2010 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2011 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2012 2013 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2014 reset-names = "phy"; 2015 2016 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2017 assigned-clock-rates = <100000000>; 2018 2019 status = "disabled"; 2020 2021 pcie1_lane: phy@1c0e200 { 2022 reg = <0 0x01c0e200 0 0x170>, /* tx0 */ 2023 <0 0x01c0e400 0 0x200>, /* rx0 */ 2024 <0 0x01c0ea00 0 0x1f0>, /* pcs */ 2025 <0 0x01c0e600 0 0x170>, /* tx1 */ 2026 <0 0x01c0e800 0 0x200>, /* rx1 */ 2027 <0 0x01c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 2028 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 2029 clock-names = "pipe0"; 2030 2031 #phy-cells = <0>; 2032 2033 #clock-cells = <0>; 2034 clock-output-names = "pcie_1_pipe_clk"; 2035 }; 2036 }; 2037 2038 pcie2: pci@1c10000 { 2039 compatible = "qcom,pcie-sm8250"; 2040 reg = <0 0x01c10000 0 0x3000>, 2041 <0 0x64000000 0 0xf1d>, 2042 <0 0x64000f20 0 0xa8>, 2043 <0 0x64001000 0 0x1000>, 2044 <0 0x64100000 0 0x100000>; 2045 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2046 device_type = "pci"; 2047 linux,pci-domain = <2>; 2048 bus-range = <0x00 0xff>; 2049 num-lanes = <2>; 2050 2051 #address-cells = <3>; 2052 #size-cells = <2>; 2053 2054 ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>, 2055 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; 2056 2057 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2058 interrupt-names = "msi"; 2059 #interrupt-cells = <1>; 2060 interrupt-map-mask = <0 0 0 0x7>; 2061 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2062 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2063 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2064 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2065 2066 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2067 <&gcc GCC_PCIE_2_AUX_CLK>, 2068 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2069 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2070 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 2071 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 2072 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2073 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2074 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 2075 clock-names = "pipe", 2076 "aux", 2077 "cfg", 2078 "bus_master", 2079 "bus_slave", 2080 "slave_q2a", 2081 "ref", 2082 "tbu", 2083 "ddrss_sf_tbu"; 2084 2085 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 2086 assigned-clock-rates = <19200000>; 2087 2088 iommus = <&apps_smmu 0x1d00 0x7f>; 2089 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 2090 <0x100 &apps_smmu 0x1d01 0x1>; 2091 2092 resets = <&gcc GCC_PCIE_2_BCR>; 2093 reset-names = "pci"; 2094 2095 power-domains = <&gcc PCIE_2_GDSC>; 2096 2097 phys = <&pcie2_lane>; 2098 phy-names = "pciephy"; 2099 2100 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; 2101 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; 2102 2103 pinctrl-names = "default"; 2104 pinctrl-0 = <&pcie2_default_state>; 2105 2106 status = "disabled"; 2107 }; 2108 2109 pcie2_phy: phy@1c16000 { 2110 compatible = "qcom,sm8250-qmp-modem-pcie-phy"; 2111 reg = <0 0x01c16000 0 0x1c0>; 2112 #address-cells = <2>; 2113 #size-cells = <2>; 2114 ranges; 2115 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2116 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2117 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2118 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2119 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 2120 2121 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 2122 reset-names = "phy"; 2123 2124 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2125 assigned-clock-rates = <100000000>; 2126 2127 status = "disabled"; 2128 2129 pcie2_lane: phy@1c16200 { 2130 reg = <0 0x01c16200 0 0x170>, /* tx0 */ 2131 <0 0x01c16400 0 0x200>, /* rx0 */ 2132 <0 0x01c16a00 0 0x1f0>, /* pcs */ 2133 <0 0x01c16600 0 0x170>, /* tx1 */ 2134 <0 0x01c16800 0 0x200>, /* rx1 */ 2135 <0 0x01c16e00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ 2136 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; 2137 clock-names = "pipe0"; 2138 2139 #phy-cells = <0>; 2140 2141 #clock-cells = <0>; 2142 clock-output-names = "pcie_2_pipe_clk"; 2143 }; 2144 }; 2145 2146 ufs_mem_hc: ufshc@1d84000 { 2147 compatible = "qcom,sm8250-ufshc", "qcom,ufshc", 2148 "jedec,ufs-2.0"; 2149 reg = <0 0x01d84000 0 0x3000>; 2150 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2151 phys = <&ufs_mem_phy_lanes>; 2152 phy-names = "ufsphy"; 2153 lanes-per-direction = <2>; 2154 #reset-cells = <1>; 2155 resets = <&gcc GCC_UFS_PHY_BCR>; 2156 reset-names = "rst"; 2157 2158 power-domains = <&gcc UFS_PHY_GDSC>; 2159 2160 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; 2161 2162 clock-names = 2163 "core_clk", 2164 "bus_aggr_clk", 2165 "iface_clk", 2166 "core_clk_unipro", 2167 "ref_clk", 2168 "tx_lane0_sync_clk", 2169 "rx_lane0_sync_clk", 2170 "rx_lane1_sync_clk"; 2171 clocks = 2172 <&gcc GCC_UFS_PHY_AXI_CLK>, 2173 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2174 <&gcc GCC_UFS_PHY_AHB_CLK>, 2175 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2176 <&rpmhcc RPMH_CXO_CLK>, 2177 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2178 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2179 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2180 freq-table-hz = 2181 <37500000 300000000>, 2182 <0 0>, 2183 <0 0>, 2184 <37500000 300000000>, 2185 <0 0>, 2186 <0 0>, 2187 <0 0>, 2188 <0 0>; 2189 2190 status = "disabled"; 2191 }; 2192 2193 ufs_mem_phy: phy@1d87000 { 2194 compatible = "qcom,sm8250-qmp-ufs-phy"; 2195 reg = <0 0x01d87000 0 0x1c0>; 2196 #address-cells = <2>; 2197 #size-cells = <2>; 2198 ranges; 2199 clock-names = "ref", 2200 "ref_aux"; 2201 clocks = <&rpmhcc RPMH_CXO_CLK>, 2202 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2203 2204 resets = <&ufs_mem_hc 0>; 2205 reset-names = "ufsphy"; 2206 status = "disabled"; 2207 2208 ufs_mem_phy_lanes: phy@1d87400 { 2209 reg = <0 0x01d87400 0 0x16c>, 2210 <0 0x01d87600 0 0x200>, 2211 <0 0x01d87c00 0 0x200>, 2212 <0 0x01d87800 0 0x16c>, 2213 <0 0x01d87a00 0 0x200>; 2214 #phy-cells = <0>; 2215 }; 2216 }; 2217 2218 tcsr_mutex: hwlock@1f40000 { 2219 compatible = "qcom,tcsr-mutex"; 2220 reg = <0x0 0x01f40000 0x0 0x40000>; 2221 #hwlock-cells = <1>; 2222 }; 2223 2224 wsamacro: codec@3240000 { 2225 compatible = "qcom,sm8250-lpass-wsa-macro"; 2226 reg = <0 0x03240000 0 0x1000>; 2227 clocks = <&audiocc LPASS_CDC_WSA_MCLK>, 2228 <&audiocc LPASS_CDC_WSA_NPL>, 2229 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2230 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2231 <&aoncc LPASS_CDC_VA_MCLK>, 2232 <&vamacro>; 2233 2234 clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; 2235 2236 #clock-cells = <0>; 2237 clock-output-names = "mclk"; 2238 #sound-dai-cells = <1>; 2239 2240 pinctrl-names = "default"; 2241 pinctrl-0 = <&wsa_swr_active>; 2242 2243 status = "disabled"; 2244 }; 2245 2246 swr0: soundwire-controller@3250000 { 2247 reg = <0 0x03250000 0 0x2000>; 2248 compatible = "qcom,soundwire-v1.5.1"; 2249 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 2250 clocks = <&wsamacro>; 2251 clock-names = "iface"; 2252 2253 qcom,din-ports = <2>; 2254 qcom,dout-ports = <6>; 2255 2256 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2257 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2258 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2259 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; 2260 2261 #sound-dai-cells = <1>; 2262 #address-cells = <2>; 2263 #size-cells = <0>; 2264 2265 status = "disabled"; 2266 }; 2267 2268 audiocc: clock-controller@3300000 { 2269 compatible = "qcom,sm8250-lpass-audiocc"; 2270 reg = <0 0x03300000 0 0x30000>; 2271 #clock-cells = <1>; 2272 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2273 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2274 <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2275 clock-names = "core", "audio", "bus"; 2276 }; 2277 2278 vamacro: codec@3370000 { 2279 compatible = "qcom,sm8250-lpass-va-macro"; 2280 reg = <0 0x03370000 0 0x1000>; 2281 clocks = <&aoncc LPASS_CDC_VA_MCLK>, 2282 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2283 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2284 2285 clock-names = "mclk", "macro", "dcodec"; 2286 2287 #clock-cells = <0>; 2288 clock-output-names = "fsgen"; 2289 #sound-dai-cells = <1>; 2290 }; 2291 2292 rxmacro: rxmacro@3200000 { 2293 pinctrl-names = "default"; 2294 pinctrl-0 = <&rx_swr_active>; 2295 compatible = "qcom,sm8250-lpass-rx-macro"; 2296 reg = <0 0x03200000 0 0x1000>; 2297 status = "disabled"; 2298 2299 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2300 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2301 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2302 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2303 <&vamacro>; 2304 2305 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2306 2307 #clock-cells = <0>; 2308 clock-output-names = "mclk"; 2309 #sound-dai-cells = <1>; 2310 }; 2311 2312 swr1: soundwire-controller@3210000 { 2313 reg = <0 0x03210000 0 0x2000>; 2314 compatible = "qcom,soundwire-v1.5.1"; 2315 status = "disabled"; 2316 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 2317 clocks = <&rxmacro>; 2318 clock-names = "iface"; 2319 label = "RX"; 2320 qcom,din-ports = <0>; 2321 qcom,dout-ports = <5>; 2322 2323 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2324 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; 2325 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2326 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2327 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2328 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2329 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2330 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2331 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2332 2333 #sound-dai-cells = <1>; 2334 #address-cells = <2>; 2335 #size-cells = <0>; 2336 }; 2337 2338 txmacro: txmacro@3220000 { 2339 pinctrl-names = "default"; 2340 pinctrl-0 = <&tx_swr_active>; 2341 compatible = "qcom,sm8250-lpass-tx-macro"; 2342 reg = <0 0x03220000 0 0x1000>; 2343 status = "disabled"; 2344 2345 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2346 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2347 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2348 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2349 <&vamacro>; 2350 2351 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2352 2353 #clock-cells = <0>; 2354 clock-output-names = "mclk"; 2355 #sound-dai-cells = <1>; 2356 }; 2357 2358 /* tx macro */ 2359 swr2: soundwire-controller@3230000 { 2360 reg = <0 0x03230000 0 0x2000>; 2361 compatible = "qcom,soundwire-v1.5.1"; 2362 interrupts-extended = <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 2363 interrupt-names = "core"; 2364 status = "disabled"; 2365 2366 clocks = <&txmacro>; 2367 clock-names = "iface"; 2368 label = "TX"; 2369 2370 qcom,din-ports = <5>; 2371 qcom,dout-ports = <0>; 2372 qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>; 2373 qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>; 2374 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>; 2375 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2376 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2377 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2378 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2379 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2380 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>; 2381 #sound-dai-cells = <1>; 2382 #address-cells = <2>; 2383 #size-cells = <0>; 2384 }; 2385 2386 aoncc: clock-controller@3380000 { 2387 compatible = "qcom,sm8250-lpass-aoncc"; 2388 reg = <0 0x03380000 0 0x40000>; 2389 #clock-cells = <1>; 2390 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2391 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2392 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2393 clock-names = "core", "audio", "bus"; 2394 }; 2395 2396 lpass_tlmm: pinctrl@33c0000 { 2397 compatible = "qcom,sm8250-lpass-lpi-pinctrl"; 2398 reg = <0 0x033c0000 0x0 0x20000>, 2399 <0 0x03550000 0x0 0x10000>; 2400 gpio-controller; 2401 #gpio-cells = <2>; 2402 gpio-ranges = <&lpass_tlmm 0 0 14>; 2403 2404 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2405 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2406 clock-names = "core", "audio"; 2407 2408 wsa_swr_active: wsa-swr-active-state { 2409 clk-pins { 2410 pins = "gpio10"; 2411 function = "wsa_swr_clk"; 2412 drive-strength = <2>; 2413 slew-rate = <1>; 2414 bias-disable; 2415 }; 2416 2417 data-pins { 2418 pins = "gpio11"; 2419 function = "wsa_swr_data"; 2420 drive-strength = <2>; 2421 slew-rate = <1>; 2422 bias-bus-hold; 2423 2424 }; 2425 }; 2426 2427 wsa_swr_sleep: wsa-swr-sleep-state { 2428 clk-pins { 2429 pins = "gpio10"; 2430 function = "wsa_swr_clk"; 2431 drive-strength = <2>; 2432 input-enable; 2433 bias-pull-down; 2434 }; 2435 2436 data-pins { 2437 pins = "gpio11"; 2438 function = "wsa_swr_data"; 2439 drive-strength = <2>; 2440 input-enable; 2441 bias-pull-down; 2442 2443 }; 2444 }; 2445 2446 dmic01_active: dmic01-active-state { 2447 clk-pins { 2448 pins = "gpio6"; 2449 function = "dmic1_clk"; 2450 drive-strength = <8>; 2451 output-high; 2452 }; 2453 data-pins { 2454 pins = "gpio7"; 2455 function = "dmic1_data"; 2456 drive-strength = <8>; 2457 input-enable; 2458 }; 2459 }; 2460 2461 dmic01_sleep: dmic01-sleep-state { 2462 clk-pins { 2463 pins = "gpio6"; 2464 function = "dmic1_clk"; 2465 drive-strength = <2>; 2466 bias-disable; 2467 output-low; 2468 }; 2469 2470 data-pins { 2471 pins = "gpio7"; 2472 function = "dmic1_data"; 2473 drive-strength = <2>; 2474 bias-pull-down; 2475 input-enable; 2476 }; 2477 }; 2478 2479 rx_swr_active: rx-swr-active-state { 2480 clk-pins { 2481 pins = "gpio3"; 2482 function = "swr_rx_clk"; 2483 drive-strength = <2>; 2484 slew-rate = <1>; 2485 bias-disable; 2486 }; 2487 2488 data-pins { 2489 pins = "gpio4", "gpio5"; 2490 function = "swr_rx_data"; 2491 drive-strength = <2>; 2492 slew-rate = <1>; 2493 bias-bus-hold; 2494 }; 2495 }; 2496 2497 tx_swr_active: tx-swr-active-state { 2498 clk-pins { 2499 pins = "gpio0"; 2500 function = "swr_tx_clk"; 2501 drive-strength = <2>; 2502 slew-rate = <1>; 2503 bias-disable; 2504 }; 2505 2506 data-pins { 2507 pins = "gpio1", "gpio2"; 2508 function = "swr_tx_data"; 2509 drive-strength = <2>; 2510 slew-rate = <1>; 2511 bias-bus-hold; 2512 }; 2513 }; 2514 2515 tx_swr_sleep: tx-swr-sleep-state { 2516 clk-pins { 2517 pins = "gpio0"; 2518 function = "swr_tx_clk"; 2519 drive-strength = <2>; 2520 input-enable; 2521 bias-pull-down; 2522 }; 2523 2524 data1-pins { 2525 pins = "gpio1"; 2526 function = "swr_tx_data"; 2527 drive-strength = <2>; 2528 input-enable; 2529 bias-bus-hold; 2530 }; 2531 2532 data2-pins { 2533 pins = "gpio2"; 2534 function = "swr_tx_data"; 2535 drive-strength = <2>; 2536 input-enable; 2537 bias-pull-down; 2538 }; 2539 }; 2540 }; 2541 2542 gpu: gpu@3d00000 { 2543 compatible = "qcom,adreno-650.2", 2544 "qcom,adreno"; 2545 2546 reg = <0 0x03d00000 0 0x40000>; 2547 reg-names = "kgsl_3d0_reg_memory"; 2548 2549 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2550 2551 iommus = <&adreno_smmu 0 0x401>; 2552 2553 operating-points-v2 = <&gpu_opp_table>; 2554 2555 qcom,gmu = <&gmu>; 2556 2557 status = "disabled"; 2558 2559 zap-shader { 2560 memory-region = <&gpu_mem>; 2561 }; 2562 2563 /* note: downstream checks gpu binning for 670 Mhz */ 2564 gpu_opp_table: opp-table { 2565 compatible = "operating-points-v2"; 2566 2567 opp-670000000 { 2568 opp-hz = /bits/ 64 <670000000>; 2569 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2570 }; 2571 2572 opp-587000000 { 2573 opp-hz = /bits/ 64 <587000000>; 2574 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2575 }; 2576 2577 opp-525000000 { 2578 opp-hz = /bits/ 64 <525000000>; 2579 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2580 }; 2581 2582 opp-490000000 { 2583 opp-hz = /bits/ 64 <490000000>; 2584 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2585 }; 2586 2587 opp-441600000 { 2588 opp-hz = /bits/ 64 <441600000>; 2589 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2590 }; 2591 2592 opp-400000000 { 2593 opp-hz = /bits/ 64 <400000000>; 2594 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2595 }; 2596 2597 opp-305000000 { 2598 opp-hz = /bits/ 64 <305000000>; 2599 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2600 }; 2601 }; 2602 }; 2603 2604 gmu: gmu@3d6a000 { 2605 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; 2606 2607 reg = <0 0x03d6a000 0 0x30000>, 2608 <0 0x3de0000 0 0x10000>, 2609 <0 0xb290000 0 0x10000>, 2610 <0 0xb490000 0 0x10000>; 2611 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; 2612 2613 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2614 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2615 interrupt-names = "hfi", "gmu"; 2616 2617 clocks = <&gpucc GPU_CC_AHB_CLK>, 2618 <&gpucc GPU_CC_CX_GMU_CLK>, 2619 <&gpucc GPU_CC_CXO_CLK>, 2620 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2621 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2622 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2623 2624 power-domains = <&gpucc GPU_CX_GDSC>, 2625 <&gpucc GPU_GX_GDSC>; 2626 power-domain-names = "cx", "gx"; 2627 2628 iommus = <&adreno_smmu 5 0x400>; 2629 2630 operating-points-v2 = <&gmu_opp_table>; 2631 2632 status = "disabled"; 2633 2634 gmu_opp_table: opp-table { 2635 compatible = "operating-points-v2"; 2636 2637 opp-200000000 { 2638 opp-hz = /bits/ 64 <200000000>; 2639 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2640 }; 2641 }; 2642 }; 2643 2644 gpucc: clock-controller@3d90000 { 2645 compatible = "qcom,sm8250-gpucc"; 2646 reg = <0 0x03d90000 0 0x9000>; 2647 clocks = <&rpmhcc RPMH_CXO_CLK>, 2648 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2649 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2650 clock-names = "bi_tcxo", 2651 "gcc_gpu_gpll0_clk_src", 2652 "gcc_gpu_gpll0_div_clk_src"; 2653 #clock-cells = <1>; 2654 #reset-cells = <1>; 2655 #power-domain-cells = <1>; 2656 }; 2657 2658 adreno_smmu: iommu@3da0000 { 2659 compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; 2660 reg = <0 0x03da0000 0 0x10000>; 2661 #iommu-cells = <2>; 2662 #global-interrupts = <2>; 2663 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2664 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2665 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2666 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2667 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2668 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2669 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2670 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2671 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2672 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; 2673 clocks = <&gpucc GPU_CC_AHB_CLK>, 2674 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2675 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2676 clock-names = "ahb", "bus", "iface"; 2677 2678 power-domains = <&gpucc GPU_CX_GDSC>; 2679 }; 2680 2681 slpi: remoteproc@5c00000 { 2682 compatible = "qcom,sm8250-slpi-pas"; 2683 reg = <0 0x05c00000 0 0x4000>; 2684 2685 interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>, 2686 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2687 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2688 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2689 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2690 interrupt-names = "wdog", "fatal", "ready", 2691 "handover", "stop-ack"; 2692 2693 clocks = <&rpmhcc RPMH_CXO_CLK>; 2694 clock-names = "xo"; 2695 2696 power-domains = <&rpmhpd SM8250_LCX>, 2697 <&rpmhpd SM8250_LMX>; 2698 power-domain-names = "lcx", "lmx"; 2699 2700 memory-region = <&slpi_mem>; 2701 2702 qcom,qmp = <&aoss_qmp>; 2703 2704 qcom,smem-states = <&smp2p_slpi_out 0>; 2705 qcom,smem-state-names = "stop"; 2706 2707 status = "disabled"; 2708 2709 glink-edge { 2710 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2711 IPCC_MPROC_SIGNAL_GLINK_QMP 2712 IRQ_TYPE_EDGE_RISING>; 2713 mboxes = <&ipcc IPCC_CLIENT_SLPI 2714 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2715 2716 label = "slpi"; 2717 qcom,remote-pid = <3>; 2718 2719 fastrpc { 2720 compatible = "qcom,fastrpc"; 2721 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2722 label = "sdsp"; 2723 qcom,non-secure-domain; 2724 #address-cells = <1>; 2725 #size-cells = <0>; 2726 2727 compute-cb@1 { 2728 compatible = "qcom,fastrpc-compute-cb"; 2729 reg = <1>; 2730 iommus = <&apps_smmu 0x0541 0x0>; 2731 }; 2732 2733 compute-cb@2 { 2734 compatible = "qcom,fastrpc-compute-cb"; 2735 reg = <2>; 2736 iommus = <&apps_smmu 0x0542 0x0>; 2737 }; 2738 2739 compute-cb@3 { 2740 compatible = "qcom,fastrpc-compute-cb"; 2741 reg = <3>; 2742 iommus = <&apps_smmu 0x0543 0x0>; 2743 /* note: shared-cb = <4> in downstream */ 2744 }; 2745 }; 2746 }; 2747 }; 2748 2749 stm@6002000 { 2750 compatible = "arm,coresight-stm", "arm,primecell"; 2751 reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>; 2752 reg-names = "stm-base", "stm-stimulus-base"; 2753 2754 clocks = <&aoss_qmp>; 2755 clock-names = "apb_pclk"; 2756 2757 out-ports { 2758 port { 2759 stm_out: endpoint { 2760 remote-endpoint = <&funnel0_in7>; 2761 }; 2762 }; 2763 }; 2764 }; 2765 2766 funnel@6041000 { 2767 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2768 reg = <0 0x06041000 0 0x1000>; 2769 2770 clocks = <&aoss_qmp>; 2771 clock-names = "apb_pclk"; 2772 2773 out-ports { 2774 port { 2775 funnel_in0_out_funnel_merg: endpoint { 2776 remote-endpoint = <&funnel_merg_in_funnel_in0>; 2777 }; 2778 }; 2779 }; 2780 2781 in-ports { 2782 #address-cells = <1>; 2783 #size-cells = <0>; 2784 2785 port@7 { 2786 reg = <7>; 2787 funnel0_in7: endpoint { 2788 remote-endpoint = <&stm_out>; 2789 }; 2790 }; 2791 }; 2792 }; 2793 2794 funnel@6042000 { 2795 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2796 reg = <0 0x06042000 0 0x1000>; 2797 2798 clocks = <&aoss_qmp>; 2799 clock-names = "apb_pclk"; 2800 2801 out-ports { 2802 #address-cells = <1>; 2803 #size-cells = <0>; 2804 2805 port@0 { 2806 reg = <0>; 2807 funnel_in1_out_funnel_merg: endpoint { 2808 remote-endpoint = <&funnel_merg_in_funnel_in1>; 2809 }; 2810 }; 2811 }; 2812 2813 in-ports { 2814 #address-cells = <1>; 2815 #size-cells = <0>; 2816 2817 port@4 { 2818 reg = <4>; 2819 funnel_in1_in_funnel_apss_merg: endpoint { 2820 remote-endpoint = <&funnel_apss_merg_out_funnel_in1>; 2821 }; 2822 }; 2823 }; 2824 }; 2825 2826 funnel@6045000 { 2827 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2828 reg = <0 0x06045000 0 0x1000>; 2829 2830 clocks = <&aoss_qmp>; 2831 clock-names = "apb_pclk"; 2832 2833 out-ports { 2834 port { 2835 funnel_merg_out_funnel_swao: endpoint { 2836 remote-endpoint = <&funnel_swao_in_funnel_merg>; 2837 }; 2838 }; 2839 }; 2840 2841 in-ports { 2842 #address-cells = <1>; 2843 #size-cells = <0>; 2844 2845 port@0 { 2846 reg = <0>; 2847 funnel_merg_in_funnel_in0: endpoint { 2848 remote-endpoint = <&funnel_in0_out_funnel_merg>; 2849 }; 2850 }; 2851 2852 port@1 { 2853 reg = <1>; 2854 funnel_merg_in_funnel_in1: endpoint { 2855 remote-endpoint = <&funnel_in1_out_funnel_merg>; 2856 }; 2857 }; 2858 }; 2859 }; 2860 2861 replicator@6046000 { 2862 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2863 reg = <0 0x06046000 0 0x1000>; 2864 2865 clocks = <&aoss_qmp>; 2866 clock-names = "apb_pclk"; 2867 2868 out-ports { 2869 port { 2870 replicator_out: endpoint { 2871 remote-endpoint = <&etr_in>; 2872 }; 2873 }; 2874 }; 2875 2876 in-ports { 2877 port { 2878 replicator_cx_in_swao_out: endpoint { 2879 remote-endpoint = <&replicator_swao_out_cx_in>; 2880 }; 2881 }; 2882 }; 2883 }; 2884 2885 etr@6048000 { 2886 compatible = "arm,coresight-tmc", "arm,primecell"; 2887 reg = <0 0x06048000 0 0x1000>; 2888 2889 clocks = <&aoss_qmp>; 2890 clock-names = "apb_pclk"; 2891 arm,scatter-gather; 2892 2893 in-ports { 2894 port { 2895 etr_in: endpoint { 2896 remote-endpoint = <&replicator_out>; 2897 }; 2898 }; 2899 }; 2900 }; 2901 2902 funnel@6b04000 { 2903 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2904 arm,primecell-periphid = <0x000bb908>; 2905 2906 reg = <0 0x06b04000 0 0x1000>; 2907 reg-names = "funnel-base"; 2908 2909 clocks = <&aoss_qmp>; 2910 clock-names = "apb_pclk"; 2911 2912 out-ports { 2913 port { 2914 funnel_swao_out_etf: endpoint { 2915 remote-endpoint = <&etf_in_funnel_swao_out>; 2916 }; 2917 }; 2918 }; 2919 2920 in-ports { 2921 #address-cells = <1>; 2922 #size-cells = <0>; 2923 2924 port@7 { 2925 reg = <7>; 2926 funnel_swao_in_funnel_merg: endpoint { 2927 remote-endpoint= <&funnel_merg_out_funnel_swao>; 2928 }; 2929 }; 2930 }; 2931 2932 }; 2933 2934 etf@6b05000 { 2935 compatible = "arm,coresight-tmc", "arm,primecell"; 2936 reg = <0 0x06b05000 0 0x1000>; 2937 2938 clocks = <&aoss_qmp>; 2939 clock-names = "apb_pclk"; 2940 2941 out-ports { 2942 port { 2943 etf_out: endpoint { 2944 remote-endpoint = <&replicator_in>; 2945 }; 2946 }; 2947 }; 2948 2949 in-ports { 2950 #address-cells = <1>; 2951 #size-cells = <0>; 2952 2953 port@0 { 2954 reg = <0>; 2955 etf_in_funnel_swao_out: endpoint { 2956 remote-endpoint = <&funnel_swao_out_etf>; 2957 }; 2958 }; 2959 }; 2960 }; 2961 2962 replicator@6b06000 { 2963 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2964 reg = <0 0x06b06000 0 0x1000>; 2965 2966 clocks = <&aoss_qmp>; 2967 clock-names = "apb_pclk"; 2968 2969 out-ports { 2970 port { 2971 replicator_swao_out_cx_in: endpoint { 2972 remote-endpoint = <&replicator_cx_in_swao_out>; 2973 }; 2974 }; 2975 }; 2976 2977 in-ports { 2978 port { 2979 replicator_in: endpoint { 2980 remote-endpoint = <&etf_out>; 2981 }; 2982 }; 2983 }; 2984 }; 2985 2986 etm@7040000 { 2987 compatible = "arm,coresight-etm4x", "arm,primecell"; 2988 reg = <0 0x07040000 0 0x1000>; 2989 2990 cpu = <&CPU0>; 2991 2992 clocks = <&aoss_qmp>; 2993 clock-names = "apb_pclk"; 2994 arm,coresight-loses-context-with-cpu; 2995 2996 out-ports { 2997 port { 2998 etm0_out: endpoint { 2999 remote-endpoint = <&apss_funnel_in0>; 3000 }; 3001 }; 3002 }; 3003 }; 3004 3005 etm@7140000 { 3006 compatible = "arm,coresight-etm4x", "arm,primecell"; 3007 reg = <0 0x07140000 0 0x1000>; 3008 3009 cpu = <&CPU1>; 3010 3011 clocks = <&aoss_qmp>; 3012 clock-names = "apb_pclk"; 3013 arm,coresight-loses-context-with-cpu; 3014 3015 out-ports { 3016 port { 3017 etm1_out: endpoint { 3018 remote-endpoint = <&apss_funnel_in1>; 3019 }; 3020 }; 3021 }; 3022 }; 3023 3024 etm@7240000 { 3025 compatible = "arm,coresight-etm4x", "arm,primecell"; 3026 reg = <0 0x07240000 0 0x1000>; 3027 3028 cpu = <&CPU2>; 3029 3030 clocks = <&aoss_qmp>; 3031 clock-names = "apb_pclk"; 3032 arm,coresight-loses-context-with-cpu; 3033 3034 out-ports { 3035 port { 3036 etm2_out: endpoint { 3037 remote-endpoint = <&apss_funnel_in2>; 3038 }; 3039 }; 3040 }; 3041 }; 3042 3043 etm@7340000 { 3044 compatible = "arm,coresight-etm4x", "arm,primecell"; 3045 reg = <0 0x07340000 0 0x1000>; 3046 3047 cpu = <&CPU3>; 3048 3049 clocks = <&aoss_qmp>; 3050 clock-names = "apb_pclk"; 3051 arm,coresight-loses-context-with-cpu; 3052 3053 out-ports { 3054 port { 3055 etm3_out: endpoint { 3056 remote-endpoint = <&apss_funnel_in3>; 3057 }; 3058 }; 3059 }; 3060 }; 3061 3062 etm@7440000 { 3063 compatible = "arm,coresight-etm4x", "arm,primecell"; 3064 reg = <0 0x07440000 0 0x1000>; 3065 3066 cpu = <&CPU4>; 3067 3068 clocks = <&aoss_qmp>; 3069 clock-names = "apb_pclk"; 3070 arm,coresight-loses-context-with-cpu; 3071 3072 out-ports { 3073 port { 3074 etm4_out: endpoint { 3075 remote-endpoint = <&apss_funnel_in4>; 3076 }; 3077 }; 3078 }; 3079 }; 3080 3081 etm@7540000 { 3082 compatible = "arm,coresight-etm4x", "arm,primecell"; 3083 reg = <0 0x07540000 0 0x1000>; 3084 3085 cpu = <&CPU5>; 3086 3087 clocks = <&aoss_qmp>; 3088 clock-names = "apb_pclk"; 3089 arm,coresight-loses-context-with-cpu; 3090 3091 out-ports { 3092 port { 3093 etm5_out: endpoint { 3094 remote-endpoint = <&apss_funnel_in5>; 3095 }; 3096 }; 3097 }; 3098 }; 3099 3100 etm@7640000 { 3101 compatible = "arm,coresight-etm4x", "arm,primecell"; 3102 reg = <0 0x07640000 0 0x1000>; 3103 3104 cpu = <&CPU6>; 3105 3106 clocks = <&aoss_qmp>; 3107 clock-names = "apb_pclk"; 3108 arm,coresight-loses-context-with-cpu; 3109 3110 out-ports { 3111 port { 3112 etm6_out: endpoint { 3113 remote-endpoint = <&apss_funnel_in6>; 3114 }; 3115 }; 3116 }; 3117 }; 3118 3119 etm@7740000 { 3120 compatible = "arm,coresight-etm4x", "arm,primecell"; 3121 reg = <0 0x07740000 0 0x1000>; 3122 3123 cpu = <&CPU7>; 3124 3125 clocks = <&aoss_qmp>; 3126 clock-names = "apb_pclk"; 3127 arm,coresight-loses-context-with-cpu; 3128 3129 out-ports { 3130 port { 3131 etm7_out: endpoint { 3132 remote-endpoint = <&apss_funnel_in7>; 3133 }; 3134 }; 3135 }; 3136 }; 3137 3138 funnel@7800000 { 3139 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3140 reg = <0 0x07800000 0 0x1000>; 3141 3142 clocks = <&aoss_qmp>; 3143 clock-names = "apb_pclk"; 3144 3145 out-ports { 3146 port { 3147 funnel_apss_out_funnel_apss_merg: endpoint { 3148 remote-endpoint = <&funnel_apss_merg_in_funnel_apss>; 3149 }; 3150 }; 3151 }; 3152 3153 in-ports { 3154 #address-cells = <1>; 3155 #size-cells = <0>; 3156 3157 port@0 { 3158 reg = <0>; 3159 apss_funnel_in0: endpoint { 3160 remote-endpoint = <&etm0_out>; 3161 }; 3162 }; 3163 3164 port@1 { 3165 reg = <1>; 3166 apss_funnel_in1: endpoint { 3167 remote-endpoint = <&etm1_out>; 3168 }; 3169 }; 3170 3171 port@2 { 3172 reg = <2>; 3173 apss_funnel_in2: endpoint { 3174 remote-endpoint = <&etm2_out>; 3175 }; 3176 }; 3177 3178 port@3 { 3179 reg = <3>; 3180 apss_funnel_in3: endpoint { 3181 remote-endpoint = <&etm3_out>; 3182 }; 3183 }; 3184 3185 port@4 { 3186 reg = <4>; 3187 apss_funnel_in4: endpoint { 3188 remote-endpoint = <&etm4_out>; 3189 }; 3190 }; 3191 3192 port@5 { 3193 reg = <5>; 3194 apss_funnel_in5: endpoint { 3195 remote-endpoint = <&etm5_out>; 3196 }; 3197 }; 3198 3199 port@6 { 3200 reg = <6>; 3201 apss_funnel_in6: endpoint { 3202 remote-endpoint = <&etm6_out>; 3203 }; 3204 }; 3205 3206 port@7 { 3207 reg = <7>; 3208 apss_funnel_in7: endpoint { 3209 remote-endpoint = <&etm7_out>; 3210 }; 3211 }; 3212 }; 3213 }; 3214 3215 funnel@7810000 { 3216 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3217 reg = <0 0x07810000 0 0x1000>; 3218 3219 clocks = <&aoss_qmp>; 3220 clock-names = "apb_pclk"; 3221 3222 out-ports { 3223 #address-cells = <1>; 3224 #size-cells = <0>; 3225 3226 port { 3227 funnel_apss_merg_out_funnel_in1: endpoint { 3228 remote-endpoint = <&funnel_in1_in_funnel_apss_merg>; 3229 }; 3230 }; 3231 }; 3232 3233 in-ports { 3234 #address-cells = <1>; 3235 #size-cells = <0>; 3236 3237 port@0 { 3238 reg = <0>; 3239 funnel_apss_merg_in_funnel_apss: endpoint { 3240 remote-endpoint = <&funnel_apss_out_funnel_apss_merg>; 3241 }; 3242 }; 3243 }; 3244 }; 3245 3246 cdsp: remoteproc@8300000 { 3247 compatible = "qcom,sm8250-cdsp-pas"; 3248 reg = <0 0x08300000 0 0x10000>; 3249 3250 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 3251 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3252 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3253 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3254 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3255 interrupt-names = "wdog", "fatal", "ready", 3256 "handover", "stop-ack"; 3257 3258 clocks = <&rpmhcc RPMH_CXO_CLK>; 3259 clock-names = "xo"; 3260 3261 power-domains = <&rpmhpd SM8250_CX>; 3262 3263 memory-region = <&cdsp_mem>; 3264 3265 qcom,qmp = <&aoss_qmp>; 3266 3267 qcom,smem-states = <&smp2p_cdsp_out 0>; 3268 qcom,smem-state-names = "stop"; 3269 3270 status = "disabled"; 3271 3272 glink-edge { 3273 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3274 IPCC_MPROC_SIGNAL_GLINK_QMP 3275 IRQ_TYPE_EDGE_RISING>; 3276 mboxes = <&ipcc IPCC_CLIENT_CDSP 3277 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3278 3279 label = "cdsp"; 3280 qcom,remote-pid = <5>; 3281 3282 fastrpc { 3283 compatible = "qcom,fastrpc"; 3284 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3285 label = "cdsp"; 3286 qcom,non-secure-domain; 3287 #address-cells = <1>; 3288 #size-cells = <0>; 3289 3290 compute-cb@1 { 3291 compatible = "qcom,fastrpc-compute-cb"; 3292 reg = <1>; 3293 iommus = <&apps_smmu 0x1001 0x0460>; 3294 }; 3295 3296 compute-cb@2 { 3297 compatible = "qcom,fastrpc-compute-cb"; 3298 reg = <2>; 3299 iommus = <&apps_smmu 0x1002 0x0460>; 3300 }; 3301 3302 compute-cb@3 { 3303 compatible = "qcom,fastrpc-compute-cb"; 3304 reg = <3>; 3305 iommus = <&apps_smmu 0x1003 0x0460>; 3306 }; 3307 3308 compute-cb@4 { 3309 compatible = "qcom,fastrpc-compute-cb"; 3310 reg = <4>; 3311 iommus = <&apps_smmu 0x1004 0x0460>; 3312 }; 3313 3314 compute-cb@5 { 3315 compatible = "qcom,fastrpc-compute-cb"; 3316 reg = <5>; 3317 iommus = <&apps_smmu 0x1005 0x0460>; 3318 }; 3319 3320 compute-cb@6 { 3321 compatible = "qcom,fastrpc-compute-cb"; 3322 reg = <6>; 3323 iommus = <&apps_smmu 0x1006 0x0460>; 3324 }; 3325 3326 compute-cb@7 { 3327 compatible = "qcom,fastrpc-compute-cb"; 3328 reg = <7>; 3329 iommus = <&apps_smmu 0x1007 0x0460>; 3330 }; 3331 3332 compute-cb@8 { 3333 compatible = "qcom,fastrpc-compute-cb"; 3334 reg = <8>; 3335 iommus = <&apps_smmu 0x1008 0x0460>; 3336 }; 3337 3338 /* note: secure cb9 in downstream */ 3339 }; 3340 }; 3341 }; 3342 3343 usb_1_hsphy: phy@88e3000 { 3344 compatible = "qcom,sm8250-usb-hs-phy", 3345 "qcom,usb-snps-hs-7nm-phy"; 3346 reg = <0 0x088e3000 0 0x400>; 3347 status = "disabled"; 3348 #phy-cells = <0>; 3349 3350 clocks = <&rpmhcc RPMH_CXO_CLK>; 3351 clock-names = "ref"; 3352 3353 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3354 }; 3355 3356 usb_2_hsphy: phy@88e4000 { 3357 compatible = "qcom,sm8250-usb-hs-phy", 3358 "qcom,usb-snps-hs-7nm-phy"; 3359 reg = <0 0x088e4000 0 0x400>; 3360 status = "disabled"; 3361 #phy-cells = <0>; 3362 3363 clocks = <&rpmhcc RPMH_CXO_CLK>; 3364 clock-names = "ref"; 3365 3366 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3367 }; 3368 3369 usb_1_qmpphy: phy@88e9000 { 3370 compatible = "qcom,sm8250-qmp-usb3-dp-phy"; 3371 reg = <0 0x088e9000 0 0x200>, 3372 <0 0x088e8000 0 0x40>, 3373 <0 0x088ea000 0 0x200>; 3374 status = "disabled"; 3375 #address-cells = <2>; 3376 #size-cells = <2>; 3377 ranges; 3378 3379 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3380 <&rpmhcc RPMH_CXO_CLK>, 3381 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 3382 clock-names = "aux", "ref_clk_src", "com_aux"; 3383 3384 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3385 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3386 reset-names = "phy", "common"; 3387 3388 usb_1_ssphy: usb3-phy@88e9200 { 3389 reg = <0 0x088e9200 0 0x200>, 3390 <0 0x088e9400 0 0x200>, 3391 <0 0x088e9c00 0 0x400>, 3392 <0 0x088e9600 0 0x200>, 3393 <0 0x088e9800 0 0x200>, 3394 <0 0x088e9a00 0 0x100>; 3395 #clock-cells = <0>; 3396 #phy-cells = <0>; 3397 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3398 clock-names = "pipe0"; 3399 clock-output-names = "usb3_phy_pipe_clk_src"; 3400 }; 3401 3402 dp_phy: dp-phy@88ea200 { 3403 reg = <0 0x088ea200 0 0x200>, 3404 <0 0x088ea400 0 0x200>, 3405 <0 0x088eaa00 0 0x200>, 3406 <0 0x088ea600 0 0x200>, 3407 <0 0x088ea800 0 0x200>; 3408 #phy-cells = <0>; 3409 #clock-cells = <1>; 3410 }; 3411 }; 3412 3413 usb_2_qmpphy: phy@88eb000 { 3414 compatible = "qcom,sm8250-qmp-usb3-uni-phy"; 3415 reg = <0 0x088eb000 0 0x200>; 3416 status = "disabled"; 3417 #address-cells = <2>; 3418 #size-cells = <2>; 3419 ranges; 3420 3421 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3422 <&rpmhcc RPMH_CXO_CLK>, 3423 <&gcc GCC_USB3_SEC_CLKREF_EN>, 3424 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 3425 clock-names = "aux", "ref_clk_src", "ref", "com_aux"; 3426 3427 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 3428 <&gcc GCC_USB3_PHY_SEC_BCR>; 3429 reset-names = "phy", "common"; 3430 3431 usb_2_ssphy: phy@88eb200 { 3432 reg = <0 0x088eb200 0 0x200>, 3433 <0 0x088eb400 0 0x200>, 3434 <0 0x088eb800 0 0x800>; 3435 #clock-cells = <0>; 3436 #phy-cells = <0>; 3437 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3438 clock-names = "pipe0"; 3439 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3440 }; 3441 }; 3442 3443 sdhc_2: mmc@8804000 { 3444 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; 3445 reg = <0 0x08804000 0 0x1000>; 3446 3447 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3448 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3449 interrupt-names = "hc_irq", "pwr_irq"; 3450 3451 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3452 <&gcc GCC_SDCC2_APPS_CLK>, 3453 <&rpmhcc RPMH_CXO_CLK>; 3454 clock-names = "iface", "core", "xo"; 3455 iommus = <&apps_smmu 0x4a0 0x0>; 3456 qcom,dll-config = <0x0007642c>; 3457 qcom,ddr-config = <0x80040868>; 3458 power-domains = <&rpmhpd SM8250_CX>; 3459 operating-points-v2 = <&sdhc2_opp_table>; 3460 3461 status = "disabled"; 3462 3463 sdhc2_opp_table: opp-table { 3464 compatible = "operating-points-v2"; 3465 3466 opp-19200000 { 3467 opp-hz = /bits/ 64 <19200000>; 3468 required-opps = <&rpmhpd_opp_min_svs>; 3469 }; 3470 3471 opp-50000000 { 3472 opp-hz = /bits/ 64 <50000000>; 3473 required-opps = <&rpmhpd_opp_low_svs>; 3474 }; 3475 3476 opp-100000000 { 3477 opp-hz = /bits/ 64 <100000000>; 3478 required-opps = <&rpmhpd_opp_svs>; 3479 }; 3480 3481 opp-202000000 { 3482 opp-hz = /bits/ 64 <202000000>; 3483 required-opps = <&rpmhpd_opp_svs_l1>; 3484 }; 3485 }; 3486 }; 3487 3488 dc_noc: interconnect@90c0000 { 3489 compatible = "qcom,sm8250-dc-noc"; 3490 reg = <0 0x090c0000 0 0x4200>; 3491 #interconnect-cells = <1>; 3492 qcom,bcm-voters = <&apps_bcm_voter>; 3493 }; 3494 3495 gem_noc: interconnect@9100000 { 3496 compatible = "qcom,sm8250-gem-noc"; 3497 reg = <0 0x09100000 0 0xb4000>; 3498 #interconnect-cells = <1>; 3499 qcom,bcm-voters = <&apps_bcm_voter>; 3500 }; 3501 3502 npu_noc: interconnect@9990000 { 3503 compatible = "qcom,sm8250-npu-noc"; 3504 reg = <0 0x09990000 0 0x1600>; 3505 #interconnect-cells = <1>; 3506 qcom,bcm-voters = <&apps_bcm_voter>; 3507 }; 3508 3509 usb_1: usb@a6f8800 { 3510 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 3511 reg = <0 0x0a6f8800 0 0x400>; 3512 status = "disabled"; 3513 #address-cells = <2>; 3514 #size-cells = <2>; 3515 ranges; 3516 dma-ranges; 3517 3518 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3519 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3520 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3521 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3522 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3523 <&gcc GCC_USB3_SEC_CLKREF_EN>; 3524 clock-names = "cfg_noc", 3525 "core", 3526 "iface", 3527 "sleep", 3528 "mock_utmi", 3529 "xo"; 3530 3531 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3532 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3533 assigned-clock-rates = <19200000>, <200000000>; 3534 3535 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3536 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 3537 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3538 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 3539 interrupt-names = "hs_phy_irq", 3540 "ss_phy_irq", 3541 "dm_hs_phy_irq", 3542 "dp_hs_phy_irq"; 3543 3544 power-domains = <&gcc USB30_PRIM_GDSC>; 3545 3546 resets = <&gcc GCC_USB30_PRIM_BCR>; 3547 3548 usb_1_dwc3: usb@a600000 { 3549 compatible = "snps,dwc3"; 3550 reg = <0 0x0a600000 0 0xcd00>; 3551 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3552 iommus = <&apps_smmu 0x0 0x0>; 3553 snps,dis_u2_susphy_quirk; 3554 snps,dis_enblslpm_quirk; 3555 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 3556 phy-names = "usb2-phy", "usb3-phy"; 3557 }; 3558 }; 3559 3560 system-cache-controller@9200000 { 3561 compatible = "qcom,sm8250-llcc"; 3562 reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; 3563 reg-names = "llcc_base", "llcc_broadcast_base"; 3564 }; 3565 3566 usb_2: usb@a8f8800 { 3567 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 3568 reg = <0 0x0a8f8800 0 0x400>; 3569 status = "disabled"; 3570 #address-cells = <2>; 3571 #size-cells = <2>; 3572 ranges; 3573 dma-ranges; 3574 3575 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3576 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3577 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3578 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3579 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3580 <&gcc GCC_USB3_SEC_CLKREF_EN>; 3581 clock-names = "cfg_noc", 3582 "core", 3583 "iface", 3584 "sleep", 3585 "mock_utmi", 3586 "xo"; 3587 3588 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3589 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3590 assigned-clock-rates = <19200000>, <200000000>; 3591 3592 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3593 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, 3594 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 3595 <&pdc 12 IRQ_TYPE_EDGE_BOTH>; 3596 interrupt-names = "hs_phy_irq", 3597 "ss_phy_irq", 3598 "dm_hs_phy_irq", 3599 "dp_hs_phy_irq"; 3600 3601 power-domains = <&gcc USB30_SEC_GDSC>; 3602 3603 resets = <&gcc GCC_USB30_SEC_BCR>; 3604 3605 usb_2_dwc3: usb@a800000 { 3606 compatible = "snps,dwc3"; 3607 reg = <0 0x0a800000 0 0xcd00>; 3608 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3609 iommus = <&apps_smmu 0x20 0>; 3610 snps,dis_u2_susphy_quirk; 3611 snps,dis_enblslpm_quirk; 3612 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 3613 phy-names = "usb2-phy", "usb3-phy"; 3614 }; 3615 }; 3616 3617 venus: video-codec@aa00000 { 3618 compatible = "qcom,sm8250-venus"; 3619 reg = <0 0x0aa00000 0 0x100000>; 3620 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3621 power-domains = <&videocc MVS0C_GDSC>, 3622 <&videocc MVS0_GDSC>, 3623 <&rpmhpd SM8250_MX>; 3624 power-domain-names = "venus", "vcodec0", "mx"; 3625 operating-points-v2 = <&venus_opp_table>; 3626 3627 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 3628 <&videocc VIDEO_CC_MVS0C_CLK>, 3629 <&videocc VIDEO_CC_MVS0_CLK>; 3630 clock-names = "iface", "core", "vcodec0_core"; 3631 3632 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_VENUS_CFG>, 3633 <&mmss_noc MASTER_VIDEO_P0 &mc_virt SLAVE_EBI_CH0>; 3634 interconnect-names = "cpu-cfg", "video-mem"; 3635 3636 iommus = <&apps_smmu 0x2100 0x0400>; 3637 memory-region = <&video_mem>; 3638 3639 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 3640 <&videocc VIDEO_CC_MVS0C_CLK_ARES>; 3641 reset-names = "bus", "core"; 3642 3643 status = "disabled"; 3644 3645 video-decoder { 3646 compatible = "venus-decoder"; 3647 }; 3648 3649 video-encoder { 3650 compatible = "venus-encoder"; 3651 }; 3652 3653 venus_opp_table: opp-table { 3654 compatible = "operating-points-v2"; 3655 3656 opp-720000000 { 3657 opp-hz = /bits/ 64 <720000000>; 3658 required-opps = <&rpmhpd_opp_low_svs>; 3659 }; 3660 3661 opp-1014000000 { 3662 opp-hz = /bits/ 64 <1014000000>; 3663 required-opps = <&rpmhpd_opp_svs>; 3664 }; 3665 3666 opp-1098000000 { 3667 opp-hz = /bits/ 64 <1098000000>; 3668 required-opps = <&rpmhpd_opp_svs_l1>; 3669 }; 3670 3671 opp-1332000000 { 3672 opp-hz = /bits/ 64 <1332000000>; 3673 required-opps = <&rpmhpd_opp_nom>; 3674 }; 3675 }; 3676 }; 3677 3678 videocc: clock-controller@abf0000 { 3679 compatible = "qcom,sm8250-videocc"; 3680 reg = <0 0x0abf0000 0 0x10000>; 3681 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 3682 <&rpmhcc RPMH_CXO_CLK>, 3683 <&rpmhcc RPMH_CXO_CLK_A>; 3684 power-domains = <&rpmhpd SM8250_MMCX>; 3685 required-opps = <&rpmhpd_opp_low_svs>; 3686 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; 3687 #clock-cells = <1>; 3688 #reset-cells = <1>; 3689 #power-domain-cells = <1>; 3690 }; 3691 3692 cci0: cci@ac4f000 { 3693 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci"; 3694 #address-cells = <1>; 3695 #size-cells = <0>; 3696 3697 reg = <0 0x0ac4f000 0 0x1000>; 3698 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 3699 power-domains = <&camcc TITAN_TOP_GDSC>; 3700 3701 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3702 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3703 <&camcc CAM_CC_CPAS_AHB_CLK>, 3704 <&camcc CAM_CC_CCI_0_CLK>, 3705 <&camcc CAM_CC_CCI_0_CLK_SRC>; 3706 clock-names = "camnoc_axi", 3707 "slow_ahb_src", 3708 "cpas_ahb", 3709 "cci", 3710 "cci_src"; 3711 3712 pinctrl-0 = <&cci0_default>; 3713 pinctrl-1 = <&cci0_sleep>; 3714 pinctrl-names = "default", "sleep"; 3715 3716 status = "disabled"; 3717 3718 cci0_i2c0: i2c-bus@0 { 3719 reg = <0>; 3720 clock-frequency = <1000000>; 3721 #address-cells = <1>; 3722 #size-cells = <0>; 3723 }; 3724 3725 cci0_i2c1: i2c-bus@1 { 3726 reg = <1>; 3727 clock-frequency = <1000000>; 3728 #address-cells = <1>; 3729 #size-cells = <0>; 3730 }; 3731 }; 3732 3733 cci1: cci@ac50000 { 3734 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci"; 3735 #address-cells = <1>; 3736 #size-cells = <0>; 3737 3738 reg = <0 0x0ac50000 0 0x1000>; 3739 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 3740 power-domains = <&camcc TITAN_TOP_GDSC>; 3741 3742 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3743 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3744 <&camcc CAM_CC_CPAS_AHB_CLK>, 3745 <&camcc CAM_CC_CCI_1_CLK>, 3746 <&camcc CAM_CC_CCI_1_CLK_SRC>; 3747 clock-names = "camnoc_axi", 3748 "slow_ahb_src", 3749 "cpas_ahb", 3750 "cci", 3751 "cci_src"; 3752 3753 pinctrl-0 = <&cci1_default>; 3754 pinctrl-1 = <&cci1_sleep>; 3755 pinctrl-names = "default", "sleep"; 3756 3757 status = "disabled"; 3758 3759 cci1_i2c0: i2c-bus@0 { 3760 reg = <0>; 3761 clock-frequency = <1000000>; 3762 #address-cells = <1>; 3763 #size-cells = <0>; 3764 }; 3765 3766 cci1_i2c1: i2c-bus@1 { 3767 reg = <1>; 3768 clock-frequency = <1000000>; 3769 #address-cells = <1>; 3770 #size-cells = <0>; 3771 }; 3772 }; 3773 3774 camss: camss@ac6a000 { 3775 compatible = "qcom,sm8250-camss"; 3776 status = "disabled"; 3777 3778 reg = <0 0x0ac6a000 0 0x2000>, 3779 <0 0x0ac6c000 0 0x2000>, 3780 <0 0x0ac6e000 0 0x1000>, 3781 <0 0x0ac70000 0 0x1000>, 3782 <0 0x0ac72000 0 0x1000>, 3783 <0 0x0ac74000 0 0x1000>, 3784 <0 0x0acb4000 0 0xd000>, 3785 <0 0x0acc3000 0 0xd000>, 3786 <0 0x0acd9000 0 0x2200>, 3787 <0 0x0acdb200 0 0x2200>; 3788 reg-names = "csiphy0", 3789 "csiphy1", 3790 "csiphy2", 3791 "csiphy3", 3792 "csiphy4", 3793 "csiphy5", 3794 "vfe0", 3795 "vfe1", 3796 "vfe_lite0", 3797 "vfe_lite1"; 3798 3799 interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, 3800 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, 3801 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, 3802 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 3803 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 3804 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 3805 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 3806 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 3807 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 3808 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 3809 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 3810 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 3811 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 3812 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 3813 interrupt-names = "csiphy0", 3814 "csiphy1", 3815 "csiphy2", 3816 "csiphy3", 3817 "csiphy4", 3818 "csiphy5", 3819 "csid0", 3820 "csid1", 3821 "csid2", 3822 "csid3", 3823 "vfe0", 3824 "vfe1", 3825 "vfe_lite0", 3826 "vfe_lite1"; 3827 3828 power-domains = <&camcc IFE_0_GDSC>, 3829 <&camcc IFE_1_GDSC>, 3830 <&camcc TITAN_TOP_GDSC>; 3831 3832 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 3833 <&gcc GCC_CAMERA_HF_AXI_CLK>, 3834 <&gcc GCC_CAMERA_SF_AXI_CLK>, 3835 <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3836 <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, 3837 <&camcc CAM_CC_CORE_AHB_CLK>, 3838 <&camcc CAM_CC_CPAS_AHB_CLK>, 3839 <&camcc CAM_CC_CSIPHY0_CLK>, 3840 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 3841 <&camcc CAM_CC_CSIPHY1_CLK>, 3842 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 3843 <&camcc CAM_CC_CSIPHY2_CLK>, 3844 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 3845 <&camcc CAM_CC_CSIPHY3_CLK>, 3846 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 3847 <&camcc CAM_CC_CSIPHY4_CLK>, 3848 <&camcc CAM_CC_CSI4PHYTIMER_CLK>, 3849 <&camcc CAM_CC_CSIPHY5_CLK>, 3850 <&camcc CAM_CC_CSI5PHYTIMER_CLK>, 3851 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3852 <&camcc CAM_CC_IFE_0_AHB_CLK>, 3853 <&camcc CAM_CC_IFE_0_AXI_CLK>, 3854 <&camcc CAM_CC_IFE_0_CLK>, 3855 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 3856 <&camcc CAM_CC_IFE_0_CSID_CLK>, 3857 <&camcc CAM_CC_IFE_0_AREG_CLK>, 3858 <&camcc CAM_CC_IFE_1_AHB_CLK>, 3859 <&camcc CAM_CC_IFE_1_AXI_CLK>, 3860 <&camcc CAM_CC_IFE_1_CLK>, 3861 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 3862 <&camcc CAM_CC_IFE_1_CSID_CLK>, 3863 <&camcc CAM_CC_IFE_1_AREG_CLK>, 3864 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 3865 <&camcc CAM_CC_IFE_LITE_AXI_CLK>, 3866 <&camcc CAM_CC_IFE_LITE_CLK>, 3867 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 3868 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 3869 3870 clock-names = "cam_ahb_clk", 3871 "cam_hf_axi", 3872 "cam_sf_axi", 3873 "camnoc_axi", 3874 "camnoc_axi_src", 3875 "core_ahb", 3876 "cpas_ahb", 3877 "csiphy0", 3878 "csiphy0_timer", 3879 "csiphy1", 3880 "csiphy1_timer", 3881 "csiphy2", 3882 "csiphy2_timer", 3883 "csiphy3", 3884 "csiphy3_timer", 3885 "csiphy4", 3886 "csiphy4_timer", 3887 "csiphy5", 3888 "csiphy5_timer", 3889 "slow_ahb_src", 3890 "vfe0_ahb", 3891 "vfe0_axi", 3892 "vfe0", 3893 "vfe0_cphy_rx", 3894 "vfe0_csid", 3895 "vfe0_areg", 3896 "vfe1_ahb", 3897 "vfe1_axi", 3898 "vfe1", 3899 "vfe1_cphy_rx", 3900 "vfe1_csid", 3901 "vfe1_areg", 3902 "vfe_lite_ahb", 3903 "vfe_lite_axi", 3904 "vfe_lite", 3905 "vfe_lite_cphy_rx", 3906 "vfe_lite_csid"; 3907 3908 iommus = <&apps_smmu 0x800 0x400>, 3909 <&apps_smmu 0x801 0x400>, 3910 <&apps_smmu 0x840 0x400>, 3911 <&apps_smmu 0x841 0x400>, 3912 <&apps_smmu 0xc00 0x400>, 3913 <&apps_smmu 0xc01 0x400>, 3914 <&apps_smmu 0xc40 0x400>, 3915 <&apps_smmu 0xc41 0x400>; 3916 3917 interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>, 3918 <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>, 3919 <&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>, 3920 <&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>; 3921 interconnect-names = "cam_ahb", 3922 "cam_hf_0_mnoc", 3923 "cam_sf_0_mnoc", 3924 "cam_sf_icp_mnoc"; 3925 3926 ports { 3927 #address-cells = <1>; 3928 #size-cells = <0>; 3929 3930 port@0 { 3931 reg = <0>; 3932 }; 3933 3934 port@1 { 3935 reg = <1>; 3936 }; 3937 3938 port@2 { 3939 reg = <2>; 3940 }; 3941 3942 port@3 { 3943 reg = <3>; 3944 }; 3945 3946 port@4 { 3947 reg = <4>; 3948 }; 3949 3950 port@5 { 3951 reg = <5>; 3952 }; 3953 }; 3954 }; 3955 3956 camcc: clock-controller@ad00000 { 3957 compatible = "qcom,sm8250-camcc"; 3958 reg = <0 0x0ad00000 0 0x10000>; 3959 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 3960 <&rpmhcc RPMH_CXO_CLK>, 3961 <&rpmhcc RPMH_CXO_CLK_A>, 3962 <&sleep_clk>; 3963 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3964 power-domains = <&rpmhpd SM8250_MMCX>; 3965 required-opps = <&rpmhpd_opp_low_svs>; 3966 status = "disabled"; 3967 #clock-cells = <1>; 3968 #reset-cells = <1>; 3969 #power-domain-cells = <1>; 3970 }; 3971 3972 mdss: display-subsystem@ae00000 { 3973 compatible = "qcom,sm8250-mdss"; 3974 reg = <0 0x0ae00000 0 0x1000>; 3975 reg-names = "mdss"; 3976 3977 interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, 3978 <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>; 3979 interconnect-names = "mdp0-mem", "mdp1-mem"; 3980 3981 power-domains = <&dispcc MDSS_GDSC>; 3982 3983 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3984 <&gcc GCC_DISP_HF_AXI_CLK>, 3985 <&gcc GCC_DISP_SF_AXI_CLK>, 3986 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3987 clock-names = "iface", "bus", "nrt_bus", "core"; 3988 3989 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3990 interrupt-controller; 3991 #interrupt-cells = <1>; 3992 3993 iommus = <&apps_smmu 0x820 0x402>; 3994 3995 status = "disabled"; 3996 3997 #address-cells = <2>; 3998 #size-cells = <2>; 3999 ranges; 4000 4001 mdss_mdp: display-controller@ae01000 { 4002 compatible = "qcom,sm8250-dpu"; 4003 reg = <0 0x0ae01000 0 0x8f000>, 4004 <0 0x0aeb0000 0 0x2008>; 4005 reg-names = "mdp", "vbif"; 4006 4007 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4008 <&gcc GCC_DISP_HF_AXI_CLK>, 4009 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4010 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4011 clock-names = "iface", "bus", "core", "vsync"; 4012 4013 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4014 assigned-clock-rates = <19200000>; 4015 4016 operating-points-v2 = <&mdp_opp_table>; 4017 power-domains = <&rpmhpd SM8250_MMCX>; 4018 4019 interrupt-parent = <&mdss>; 4020 interrupts = <0>; 4021 4022 ports { 4023 #address-cells = <1>; 4024 #size-cells = <0>; 4025 4026 port@0 { 4027 reg = <0>; 4028 dpu_intf1_out: endpoint { 4029 remote-endpoint = <&dsi0_in>; 4030 }; 4031 }; 4032 4033 port@1 { 4034 reg = <1>; 4035 dpu_intf2_out: endpoint { 4036 remote-endpoint = <&dsi1_in>; 4037 }; 4038 }; 4039 }; 4040 4041 mdp_opp_table: opp-table { 4042 compatible = "operating-points-v2"; 4043 4044 opp-200000000 { 4045 opp-hz = /bits/ 64 <200000000>; 4046 required-opps = <&rpmhpd_opp_low_svs>; 4047 }; 4048 4049 opp-300000000 { 4050 opp-hz = /bits/ 64 <300000000>; 4051 required-opps = <&rpmhpd_opp_svs>; 4052 }; 4053 4054 opp-345000000 { 4055 opp-hz = /bits/ 64 <345000000>; 4056 required-opps = <&rpmhpd_opp_svs_l1>; 4057 }; 4058 4059 opp-460000000 { 4060 opp-hz = /bits/ 64 <460000000>; 4061 required-opps = <&rpmhpd_opp_nom>; 4062 }; 4063 }; 4064 }; 4065 4066 dsi0: dsi@ae94000 { 4067 compatible = "qcom,sm8250-dsi-ctrl", 4068 "qcom,mdss-dsi-ctrl"; 4069 reg = <0 0x0ae94000 0 0x400>; 4070 reg-names = "dsi_ctrl"; 4071 4072 interrupt-parent = <&mdss>; 4073 interrupts = <4>; 4074 4075 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4076 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4077 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4078 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4079 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4080 <&gcc GCC_DISP_HF_AXI_CLK>; 4081 clock-names = "byte", 4082 "byte_intf", 4083 "pixel", 4084 "core", 4085 "iface", 4086 "bus"; 4087 4088 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4089 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; 4090 4091 operating-points-v2 = <&dsi_opp_table>; 4092 power-domains = <&rpmhpd SM8250_MMCX>; 4093 4094 phys = <&dsi0_phy>; 4095 4096 status = "disabled"; 4097 4098 #address-cells = <1>; 4099 #size-cells = <0>; 4100 4101 ports { 4102 #address-cells = <1>; 4103 #size-cells = <0>; 4104 4105 port@0 { 4106 reg = <0>; 4107 dsi0_in: endpoint { 4108 remote-endpoint = <&dpu_intf1_out>; 4109 }; 4110 }; 4111 4112 port@1 { 4113 reg = <1>; 4114 dsi0_out: endpoint { 4115 }; 4116 }; 4117 }; 4118 4119 dsi_opp_table: opp-table { 4120 compatible = "operating-points-v2"; 4121 4122 opp-187500000 { 4123 opp-hz = /bits/ 64 <187500000>; 4124 required-opps = <&rpmhpd_opp_low_svs>; 4125 }; 4126 4127 opp-300000000 { 4128 opp-hz = /bits/ 64 <300000000>; 4129 required-opps = <&rpmhpd_opp_svs>; 4130 }; 4131 4132 opp-358000000 { 4133 opp-hz = /bits/ 64 <358000000>; 4134 required-opps = <&rpmhpd_opp_svs_l1>; 4135 }; 4136 }; 4137 }; 4138 4139 dsi0_phy: phy@ae94400 { 4140 compatible = "qcom,dsi-phy-7nm"; 4141 reg = <0 0x0ae94400 0 0x200>, 4142 <0 0x0ae94600 0 0x280>, 4143 <0 0x0ae94900 0 0x260>; 4144 reg-names = "dsi_phy", 4145 "dsi_phy_lane", 4146 "dsi_pll"; 4147 4148 #clock-cells = <1>; 4149 #phy-cells = <0>; 4150 4151 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4152 <&rpmhcc RPMH_CXO_CLK>; 4153 clock-names = "iface", "ref"; 4154 4155 status = "disabled"; 4156 }; 4157 4158 dsi1: dsi@ae96000 { 4159 compatible = "qcom,sm8250-dsi-ctrl", 4160 "qcom,mdss-dsi-ctrl"; 4161 reg = <0 0x0ae96000 0 0x400>; 4162 reg-names = "dsi_ctrl"; 4163 4164 interrupt-parent = <&mdss>; 4165 interrupts = <5>; 4166 4167 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 4168 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 4169 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 4170 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 4171 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4172 <&gcc GCC_DISP_HF_AXI_CLK>; 4173 clock-names = "byte", 4174 "byte_intf", 4175 "pixel", 4176 "core", 4177 "iface", 4178 "bus"; 4179 4180 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 4181 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; 4182 4183 operating-points-v2 = <&dsi_opp_table>; 4184 power-domains = <&rpmhpd SM8250_MMCX>; 4185 4186 phys = <&dsi1_phy>; 4187 4188 status = "disabled"; 4189 4190 #address-cells = <1>; 4191 #size-cells = <0>; 4192 4193 ports { 4194 #address-cells = <1>; 4195 #size-cells = <0>; 4196 4197 port@0 { 4198 reg = <0>; 4199 dsi1_in: endpoint { 4200 remote-endpoint = <&dpu_intf2_out>; 4201 }; 4202 }; 4203 4204 port@1 { 4205 reg = <1>; 4206 dsi1_out: endpoint { 4207 }; 4208 }; 4209 }; 4210 }; 4211 4212 dsi1_phy: phy@ae96400 { 4213 compatible = "qcom,dsi-phy-7nm"; 4214 reg = <0 0x0ae96400 0 0x200>, 4215 <0 0x0ae96600 0 0x280>, 4216 <0 0x0ae96900 0 0x260>; 4217 reg-names = "dsi_phy", 4218 "dsi_phy_lane", 4219 "dsi_pll"; 4220 4221 #clock-cells = <1>; 4222 #phy-cells = <0>; 4223 4224 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4225 <&rpmhcc RPMH_CXO_CLK>; 4226 clock-names = "iface", "ref"; 4227 4228 status = "disabled"; 4229 }; 4230 }; 4231 4232 dispcc: clock-controller@af00000 { 4233 compatible = "qcom,sm8250-dispcc"; 4234 reg = <0 0x0af00000 0 0x10000>; 4235 power-domains = <&rpmhpd SM8250_MMCX>; 4236 required-opps = <&rpmhpd_opp_low_svs>; 4237 clocks = <&rpmhcc RPMH_CXO_CLK>, 4238 <&dsi0_phy 0>, 4239 <&dsi0_phy 1>, 4240 <&dsi1_phy 0>, 4241 <&dsi1_phy 1>, 4242 <&dp_phy 0>, 4243 <&dp_phy 1>; 4244 clock-names = "bi_tcxo", 4245 "dsi0_phy_pll_out_byteclk", 4246 "dsi0_phy_pll_out_dsiclk", 4247 "dsi1_phy_pll_out_byteclk", 4248 "dsi1_phy_pll_out_dsiclk", 4249 "dp_phy_pll_link_clk", 4250 "dp_phy_pll_vco_div_clk"; 4251 #clock-cells = <1>; 4252 #reset-cells = <1>; 4253 #power-domain-cells = <1>; 4254 }; 4255 4256 pdc: interrupt-controller@b220000 { 4257 compatible = "qcom,sm8250-pdc", "qcom,pdc"; 4258 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 4259 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 4260 <125 63 1>, <126 716 12>; 4261 #interrupt-cells = <2>; 4262 interrupt-parent = <&intc>; 4263 interrupt-controller; 4264 }; 4265 4266 tsens0: thermal-sensor@c263000 { 4267 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 4268 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4269 <0 0x0c222000 0 0x1ff>; /* SROT */ 4270 #qcom,sensors = <16>; 4271 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4272 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4273 interrupt-names = "uplow", "critical"; 4274 #thermal-sensor-cells = <1>; 4275 }; 4276 4277 tsens1: thermal-sensor@c265000 { 4278 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 4279 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4280 <0 0x0c223000 0 0x1ff>; /* SROT */ 4281 #qcom,sensors = <9>; 4282 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4283 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4284 interrupt-names = "uplow", "critical"; 4285 #thermal-sensor-cells = <1>; 4286 }; 4287 4288 aoss_qmp: power-management@c300000 { 4289 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp"; 4290 reg = <0 0x0c300000 0 0x400>; 4291 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4292 IPCC_MPROC_SIGNAL_GLINK_QMP 4293 IRQ_TYPE_EDGE_RISING>; 4294 mboxes = <&ipcc IPCC_CLIENT_AOP 4295 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4296 4297 #clock-cells = <0>; 4298 }; 4299 4300 sram@c3f0000 { 4301 compatible = "qcom,rpmh-stats"; 4302 reg = <0 0x0c3f0000 0 0x400>; 4303 }; 4304 4305 spmi_bus: spmi@c440000 { 4306 compatible = "qcom,spmi-pmic-arb"; 4307 reg = <0x0 0x0c440000 0x0 0x0001100>, 4308 <0x0 0x0c600000 0x0 0x2000000>, 4309 <0x0 0x0e600000 0x0 0x0100000>, 4310 <0x0 0x0e700000 0x0 0x00a0000>, 4311 <0x0 0x0c40a000 0x0 0x0026000>; 4312 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4313 interrupt-names = "periph_irq"; 4314 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4315 qcom,ee = <0>; 4316 qcom,channel = <0>; 4317 #address-cells = <2>; 4318 #size-cells = <0>; 4319 interrupt-controller; 4320 #interrupt-cells = <4>; 4321 }; 4322 4323 tlmm: pinctrl@f100000 { 4324 compatible = "qcom,sm8250-pinctrl"; 4325 reg = <0 0x0f100000 0 0x300000>, 4326 <0 0x0f500000 0 0x300000>, 4327 <0 0x0f900000 0 0x300000>; 4328 reg-names = "west", "south", "north"; 4329 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4330 gpio-controller; 4331 #gpio-cells = <2>; 4332 interrupt-controller; 4333 #interrupt-cells = <2>; 4334 gpio-ranges = <&tlmm 0 0 181>; 4335 wakeup-parent = <&pdc>; 4336 4337 cam2_default: cam2-default-state { 4338 rst-pins { 4339 pins = "gpio78"; 4340 function = "gpio"; 4341 drive-strength = <2>; 4342 bias-disable; 4343 }; 4344 4345 mclk-pins { 4346 pins = "gpio96"; 4347 function = "cam_mclk"; 4348 drive-strength = <16>; 4349 bias-disable; 4350 }; 4351 }; 4352 4353 cam2_suspend: cam2-suspend-state { 4354 rst-pins { 4355 pins = "gpio78"; 4356 function = "gpio"; 4357 drive-strength = <2>; 4358 bias-pull-down; 4359 output-low; 4360 }; 4361 4362 mclk-pins { 4363 pins = "gpio96"; 4364 function = "cam_mclk"; 4365 drive-strength = <2>; 4366 bias-disable; 4367 }; 4368 }; 4369 4370 cci0_default: cci0-default-state { 4371 cci0_i2c0_default: cci0-i2c0-default-pins { 4372 /* SDA, SCL */ 4373 pins = "gpio101", "gpio102"; 4374 function = "cci_i2c"; 4375 4376 bias-pull-up; 4377 drive-strength = <2>; /* 2 mA */ 4378 }; 4379 4380 cci0_i2c1_default: cci0-i2c1-default-pins { 4381 /* SDA, SCL */ 4382 pins = "gpio103", "gpio104"; 4383 function = "cci_i2c"; 4384 4385 bias-pull-up; 4386 drive-strength = <2>; /* 2 mA */ 4387 }; 4388 }; 4389 4390 cci0_sleep: cci0-sleep-state { 4391 cci0_i2c0_sleep: cci0-i2c0-sleep-pins { 4392 /* SDA, SCL */ 4393 pins = "gpio101", "gpio102"; 4394 function = "cci_i2c"; 4395 4396 drive-strength = <2>; /* 2 mA */ 4397 bias-pull-down; 4398 }; 4399 4400 cci0_i2c1_sleep: cci0-i2c1-sleep-pins { 4401 /* SDA, SCL */ 4402 pins = "gpio103", "gpio104"; 4403 function = "cci_i2c"; 4404 4405 drive-strength = <2>; /* 2 mA */ 4406 bias-pull-down; 4407 }; 4408 }; 4409 4410 cci1_default: cci1-default-state { 4411 cci1_i2c0_default: cci1-i2c0-default-pins { 4412 /* SDA, SCL */ 4413 pins = "gpio105","gpio106"; 4414 function = "cci_i2c"; 4415 4416 bias-pull-up; 4417 drive-strength = <2>; /* 2 mA */ 4418 }; 4419 4420 cci1_i2c1_default: cci1-i2c1-default-pins { 4421 /* SDA, SCL */ 4422 pins = "gpio107","gpio108"; 4423 function = "cci_i2c"; 4424 4425 bias-pull-up; 4426 drive-strength = <2>; /* 2 mA */ 4427 }; 4428 }; 4429 4430 cci1_sleep: cci1-sleep-state { 4431 cci1_i2c0_sleep: cci1-i2c0-sleep-pins { 4432 /* SDA, SCL */ 4433 pins = "gpio105","gpio106"; 4434 function = "cci_i2c"; 4435 4436 bias-pull-down; 4437 drive-strength = <2>; /* 2 mA */ 4438 }; 4439 4440 cci1_i2c1_sleep: cci1-i2c1-sleep-pins { 4441 /* SDA, SCL */ 4442 pins = "gpio107","gpio108"; 4443 function = "cci_i2c"; 4444 4445 bias-pull-down; 4446 drive-strength = <2>; /* 2 mA */ 4447 }; 4448 }; 4449 4450 pri_mi2s_active: pri-mi2s-active-state { 4451 sclk-pins { 4452 pins = "gpio138"; 4453 function = "mi2s0_sck"; 4454 drive-strength = <8>; 4455 bias-disable; 4456 }; 4457 4458 ws-pins { 4459 pins = "gpio141"; 4460 function = "mi2s0_ws"; 4461 drive-strength = <8>; 4462 output-high; 4463 }; 4464 4465 data0-pins { 4466 pins = "gpio139"; 4467 function = "mi2s0_data0"; 4468 drive-strength = <8>; 4469 bias-disable; 4470 output-high; 4471 }; 4472 4473 data1-pins { 4474 pins = "gpio140"; 4475 function = "mi2s0_data1"; 4476 drive-strength = <8>; 4477 output-high; 4478 }; 4479 }; 4480 4481 qup_i2c0_default: qup-i2c0-default-state { 4482 pins = "gpio28", "gpio29"; 4483 function = "qup0"; 4484 drive-strength = <2>; 4485 bias-disable; 4486 }; 4487 4488 qup_i2c1_default: qup-i2c1-default-state { 4489 pins = "gpio4", "gpio5"; 4490 function = "qup1"; 4491 drive-strength = <2>; 4492 bias-disable; 4493 }; 4494 4495 qup_i2c2_default: qup-i2c2-default-state { 4496 pins = "gpio115", "gpio116"; 4497 function = "qup2"; 4498 drive-strength = <2>; 4499 bias-disable; 4500 }; 4501 4502 qup_i2c3_default: qup-i2c3-default-state { 4503 pins = "gpio119", "gpio120"; 4504 function = "qup3"; 4505 drive-strength = <2>; 4506 bias-disable; 4507 }; 4508 4509 qup_i2c4_default: qup-i2c4-default-state { 4510 pins = "gpio8", "gpio9"; 4511 function = "qup4"; 4512 drive-strength = <2>; 4513 bias-disable; 4514 }; 4515 4516 qup_i2c5_default: qup-i2c5-default-state { 4517 pins = "gpio12", "gpio13"; 4518 function = "qup5"; 4519 drive-strength = <2>; 4520 bias-disable; 4521 }; 4522 4523 qup_i2c6_default: qup-i2c6-default-state { 4524 pins = "gpio16", "gpio17"; 4525 function = "qup6"; 4526 drive-strength = <2>; 4527 bias-disable; 4528 }; 4529 4530 qup_i2c7_default: qup-i2c7-default-state { 4531 pins = "gpio20", "gpio21"; 4532 function = "qup7"; 4533 drive-strength = <2>; 4534 bias-disable; 4535 }; 4536 4537 qup_i2c8_default: qup-i2c8-default-state { 4538 pins = "gpio24", "gpio25"; 4539 function = "qup8"; 4540 drive-strength = <2>; 4541 bias-disable; 4542 }; 4543 4544 qup_i2c9_default: qup-i2c9-default-state { 4545 pins = "gpio125", "gpio126"; 4546 function = "qup9"; 4547 drive-strength = <2>; 4548 bias-disable; 4549 }; 4550 4551 qup_i2c10_default: qup-i2c10-default-state { 4552 pins = "gpio129", "gpio130"; 4553 function = "qup10"; 4554 drive-strength = <2>; 4555 bias-disable; 4556 }; 4557 4558 qup_i2c11_default: qup-i2c11-default-state { 4559 pins = "gpio60", "gpio61"; 4560 function = "qup11"; 4561 drive-strength = <2>; 4562 bias-disable; 4563 }; 4564 4565 qup_i2c12_default: qup-i2c12-default-state { 4566 pins = "gpio32", "gpio33"; 4567 function = "qup12"; 4568 drive-strength = <2>; 4569 bias-disable; 4570 }; 4571 4572 qup_i2c13_default: qup-i2c13-default-state { 4573 pins = "gpio36", "gpio37"; 4574 function = "qup13"; 4575 drive-strength = <2>; 4576 bias-disable; 4577 }; 4578 4579 qup_i2c14_default: qup-i2c14-default-state { 4580 pins = "gpio40", "gpio41"; 4581 function = "qup14"; 4582 drive-strength = <2>; 4583 bias-disable; 4584 }; 4585 4586 qup_i2c15_default: qup-i2c15-default-state { 4587 pins = "gpio44", "gpio45"; 4588 function = "qup15"; 4589 drive-strength = <2>; 4590 bias-disable; 4591 }; 4592 4593 qup_i2c16_default: qup-i2c16-default-state { 4594 pins = "gpio48", "gpio49"; 4595 function = "qup16"; 4596 drive-strength = <2>; 4597 bias-disable; 4598 }; 4599 4600 qup_i2c17_default: qup-i2c17-default-state { 4601 pins = "gpio52", "gpio53"; 4602 function = "qup17"; 4603 drive-strength = <2>; 4604 bias-disable; 4605 }; 4606 4607 qup_i2c18_default: qup-i2c18-default-state { 4608 pins = "gpio56", "gpio57"; 4609 function = "qup18"; 4610 drive-strength = <2>; 4611 bias-disable; 4612 }; 4613 4614 qup_i2c19_default: qup-i2c19-default-state { 4615 pins = "gpio0", "gpio1"; 4616 function = "qup19"; 4617 drive-strength = <2>; 4618 bias-disable; 4619 }; 4620 4621 qup_spi0_cs: qup-spi0-cs-state { 4622 pins = "gpio31"; 4623 function = "qup0"; 4624 }; 4625 4626 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 4627 pins = "gpio31"; 4628 function = "gpio"; 4629 }; 4630 4631 qup_spi0_data_clk: qup-spi0-data-clk-state { 4632 pins = "gpio28", "gpio29", 4633 "gpio30"; 4634 function = "qup0"; 4635 }; 4636 4637 qup_spi1_cs: qup-spi1-cs-state { 4638 pins = "gpio7"; 4639 function = "qup1"; 4640 }; 4641 4642 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 4643 pins = "gpio7"; 4644 function = "gpio"; 4645 }; 4646 4647 qup_spi1_data_clk: qup-spi1-data-clk-state { 4648 pins = "gpio4", "gpio5", 4649 "gpio6"; 4650 function = "qup1"; 4651 }; 4652 4653 qup_spi2_cs: qup-spi2-cs-state { 4654 pins = "gpio118"; 4655 function = "qup2"; 4656 }; 4657 4658 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 4659 pins = "gpio118"; 4660 function = "gpio"; 4661 }; 4662 4663 qup_spi2_data_clk: qup-spi2-data-clk-state { 4664 pins = "gpio115", "gpio116", 4665 "gpio117"; 4666 function = "qup2"; 4667 }; 4668 4669 qup_spi3_cs: qup-spi3-cs-state { 4670 pins = "gpio122"; 4671 function = "qup3"; 4672 }; 4673 4674 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 4675 pins = "gpio122"; 4676 function = "gpio"; 4677 }; 4678 4679 qup_spi3_data_clk: qup-spi3-data-clk-state { 4680 pins = "gpio119", "gpio120", 4681 "gpio121"; 4682 function = "qup3"; 4683 }; 4684 4685 qup_spi4_cs: qup-spi4-cs-state { 4686 pins = "gpio11"; 4687 function = "qup4"; 4688 }; 4689 4690 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 4691 pins = "gpio11"; 4692 function = "gpio"; 4693 }; 4694 4695 qup_spi4_data_clk: qup-spi4-data-clk-state { 4696 pins = "gpio8", "gpio9", 4697 "gpio10"; 4698 function = "qup4"; 4699 }; 4700 4701 qup_spi5_cs: qup-spi5-cs-state { 4702 pins = "gpio15"; 4703 function = "qup5"; 4704 }; 4705 4706 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 4707 pins = "gpio15"; 4708 function = "gpio"; 4709 }; 4710 4711 qup_spi5_data_clk: qup-spi5-data-clk-state { 4712 pins = "gpio12", "gpio13", 4713 "gpio14"; 4714 function = "qup5"; 4715 }; 4716 4717 qup_spi6_cs: qup-spi6-cs-state { 4718 pins = "gpio19"; 4719 function = "qup6"; 4720 }; 4721 4722 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 4723 pins = "gpio19"; 4724 function = "gpio"; 4725 }; 4726 4727 qup_spi6_data_clk: qup-spi6-data-clk-state { 4728 pins = "gpio16", "gpio17", 4729 "gpio18"; 4730 function = "qup6"; 4731 }; 4732 4733 qup_spi7_cs: qup-spi7-cs-state { 4734 pins = "gpio23"; 4735 function = "qup7"; 4736 }; 4737 4738 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 4739 pins = "gpio23"; 4740 function = "gpio"; 4741 }; 4742 4743 qup_spi7_data_clk: qup-spi7-data-clk-state { 4744 pins = "gpio20", "gpio21", 4745 "gpio22"; 4746 function = "qup7"; 4747 }; 4748 4749 qup_spi8_cs: qup-spi8-cs-state { 4750 pins = "gpio27"; 4751 function = "qup8"; 4752 }; 4753 4754 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 4755 pins = "gpio27"; 4756 function = "gpio"; 4757 }; 4758 4759 qup_spi8_data_clk: qup-spi8-data-clk-state { 4760 pins = "gpio24", "gpio25", 4761 "gpio26"; 4762 function = "qup8"; 4763 }; 4764 4765 qup_spi9_cs: qup-spi9-cs-state { 4766 pins = "gpio128"; 4767 function = "qup9"; 4768 }; 4769 4770 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 4771 pins = "gpio128"; 4772 function = "gpio"; 4773 }; 4774 4775 qup_spi9_data_clk: qup-spi9-data-clk-state { 4776 pins = "gpio125", "gpio126", 4777 "gpio127"; 4778 function = "qup9"; 4779 }; 4780 4781 qup_spi10_cs: qup-spi10-cs-state { 4782 pins = "gpio132"; 4783 function = "qup10"; 4784 }; 4785 4786 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 4787 pins = "gpio132"; 4788 function = "gpio"; 4789 }; 4790 4791 qup_spi10_data_clk: qup-spi10-data-clk-state { 4792 pins = "gpio129", "gpio130", 4793 "gpio131"; 4794 function = "qup10"; 4795 }; 4796 4797 qup_spi11_cs: qup-spi11-cs-state { 4798 pins = "gpio63"; 4799 function = "qup11"; 4800 }; 4801 4802 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 4803 pins = "gpio63"; 4804 function = "gpio"; 4805 }; 4806 4807 qup_spi11_data_clk: qup-spi11-data-clk-state { 4808 pins = "gpio60", "gpio61", 4809 "gpio62"; 4810 function = "qup11"; 4811 }; 4812 4813 qup_spi12_cs: qup-spi12-cs-state { 4814 pins = "gpio35"; 4815 function = "qup12"; 4816 }; 4817 4818 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 4819 pins = "gpio35"; 4820 function = "gpio"; 4821 }; 4822 4823 qup_spi12_data_clk: qup-spi12-data-clk-state { 4824 pins = "gpio32", "gpio33", 4825 "gpio34"; 4826 function = "qup12"; 4827 }; 4828 4829 qup_spi13_cs: qup-spi13-cs-state { 4830 pins = "gpio39"; 4831 function = "qup13"; 4832 }; 4833 4834 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 4835 pins = "gpio39"; 4836 function = "gpio"; 4837 }; 4838 4839 qup_spi13_data_clk: qup-spi13-data-clk-state { 4840 pins = "gpio36", "gpio37", 4841 "gpio38"; 4842 function = "qup13"; 4843 }; 4844 4845 qup_spi14_cs: qup-spi14-cs-state { 4846 pins = "gpio43"; 4847 function = "qup14"; 4848 }; 4849 4850 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 4851 pins = "gpio43"; 4852 function = "gpio"; 4853 }; 4854 4855 qup_spi14_data_clk: qup-spi14-data-clk-state { 4856 pins = "gpio40", "gpio41", 4857 "gpio42"; 4858 function = "qup14"; 4859 }; 4860 4861 qup_spi15_cs: qup-spi15-cs-state { 4862 pins = "gpio47"; 4863 function = "qup15"; 4864 }; 4865 4866 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 4867 pins = "gpio47"; 4868 function = "gpio"; 4869 }; 4870 4871 qup_spi15_data_clk: qup-spi15-data-clk-state { 4872 pins = "gpio44", "gpio45", 4873 "gpio46"; 4874 function = "qup15"; 4875 }; 4876 4877 qup_spi16_cs: qup-spi16-cs-state { 4878 pins = "gpio51"; 4879 function = "qup16"; 4880 }; 4881 4882 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state { 4883 pins = "gpio51"; 4884 function = "gpio"; 4885 }; 4886 4887 qup_spi16_data_clk: qup-spi16-data-clk-state { 4888 pins = "gpio48", "gpio49", 4889 "gpio50"; 4890 function = "qup16"; 4891 }; 4892 4893 qup_spi17_cs: qup-spi17-cs-state { 4894 pins = "gpio55"; 4895 function = "qup17"; 4896 }; 4897 4898 qup_spi17_cs_gpio: qup-spi17-cs-gpio-state { 4899 pins = "gpio55"; 4900 function = "gpio"; 4901 }; 4902 4903 qup_spi17_data_clk: qup-spi17-data-clk-state { 4904 pins = "gpio52", "gpio53", 4905 "gpio54"; 4906 function = "qup17"; 4907 }; 4908 4909 qup_spi18_cs: qup-spi18-cs-state { 4910 pins = "gpio59"; 4911 function = "qup18"; 4912 }; 4913 4914 qup_spi18_cs_gpio: qup-spi18-cs-gpio-state { 4915 pins = "gpio59"; 4916 function = "gpio"; 4917 }; 4918 4919 qup_spi18_data_clk: qup-spi18-data-clk-state { 4920 pins = "gpio56", "gpio57", 4921 "gpio58"; 4922 function = "qup18"; 4923 }; 4924 4925 qup_spi19_cs: qup-spi19-cs-state { 4926 pins = "gpio3"; 4927 function = "qup19"; 4928 }; 4929 4930 qup_spi19_cs_gpio: qup-spi19-cs-gpio-state { 4931 pins = "gpio3"; 4932 function = "gpio"; 4933 }; 4934 4935 qup_spi19_data_clk: qup-spi19-data-clk-state { 4936 pins = "gpio0", "gpio1", 4937 "gpio2"; 4938 function = "qup19"; 4939 }; 4940 4941 qup_uart2_default: qup-uart2-default-state { 4942 pins = "gpio117", "gpio118"; 4943 function = "qup2"; 4944 }; 4945 4946 qup_uart6_default: qup-uart6-default-state { 4947 pins = "gpio16", "gpio17", "gpio18", "gpio19"; 4948 function = "qup6"; 4949 }; 4950 4951 qup_uart12_default: qup-uart12-default-state { 4952 pins = "gpio34", "gpio35"; 4953 function = "qup12"; 4954 }; 4955 4956 qup_uart17_default: qup-uart17-default-state { 4957 pins = "gpio52", "gpio53", "gpio54", "gpio55"; 4958 function = "qup17"; 4959 }; 4960 4961 qup_uart18_default: qup-uart18-default-state { 4962 pins = "gpio58", "gpio59"; 4963 function = "qup18"; 4964 }; 4965 4966 tert_mi2s_active: tert-mi2s-active-state { 4967 sck-pins { 4968 pins = "gpio133"; 4969 function = "mi2s2_sck"; 4970 drive-strength = <8>; 4971 bias-disable; 4972 }; 4973 4974 data0-pins { 4975 pins = "gpio134"; 4976 function = "mi2s2_data0"; 4977 drive-strength = <8>; 4978 bias-disable; 4979 output-high; 4980 }; 4981 4982 ws-pins { 4983 pins = "gpio135"; 4984 function = "mi2s2_ws"; 4985 drive-strength = <8>; 4986 output-high; 4987 }; 4988 }; 4989 4990 sdc2_sleep_state: sdc2-sleep-state { 4991 clk-pins { 4992 pins = "sdc2_clk"; 4993 drive-strength = <2>; 4994 bias-disable; 4995 }; 4996 4997 cmd-pins { 4998 pins = "sdc2_cmd"; 4999 drive-strength = <2>; 5000 bias-pull-up; 5001 }; 5002 5003 data-pins { 5004 pins = "sdc2_data"; 5005 drive-strength = <2>; 5006 bias-pull-up; 5007 }; 5008 }; 5009 5010 pcie0_default_state: pcie0-default-state { 5011 perst-pins { 5012 pins = "gpio79"; 5013 function = "gpio"; 5014 drive-strength = <2>; 5015 bias-pull-down; 5016 }; 5017 5018 clkreq-pins { 5019 pins = "gpio80"; 5020 function = "pci_e0"; 5021 drive-strength = <2>; 5022 bias-pull-up; 5023 }; 5024 5025 wake-pins { 5026 pins = "gpio81"; 5027 function = "gpio"; 5028 drive-strength = <2>; 5029 bias-pull-up; 5030 }; 5031 }; 5032 5033 pcie1_default_state: pcie1-default-state { 5034 perst-pins { 5035 pins = "gpio82"; 5036 function = "gpio"; 5037 drive-strength = <2>; 5038 bias-pull-down; 5039 }; 5040 5041 clkreq-pins { 5042 pins = "gpio83"; 5043 function = "pci_e1"; 5044 drive-strength = <2>; 5045 bias-pull-up; 5046 }; 5047 5048 wake-pins { 5049 pins = "gpio84"; 5050 function = "gpio"; 5051 drive-strength = <2>; 5052 bias-pull-up; 5053 }; 5054 }; 5055 5056 pcie2_default_state: pcie2-default-state { 5057 perst-pins { 5058 pins = "gpio85"; 5059 function = "gpio"; 5060 drive-strength = <2>; 5061 bias-pull-down; 5062 }; 5063 5064 clkreq-pins { 5065 pins = "gpio86"; 5066 function = "pci_e2"; 5067 drive-strength = <2>; 5068 bias-pull-up; 5069 }; 5070 5071 wake-pins { 5072 pins = "gpio87"; 5073 function = "gpio"; 5074 drive-strength = <2>; 5075 bias-pull-up; 5076 }; 5077 }; 5078 }; 5079 5080 apps_smmu: iommu@15000000 { 5081 compatible = "qcom,sm8250-smmu-500", "arm,mmu-500"; 5082 reg = <0 0x15000000 0 0x100000>; 5083 #iommu-cells = <2>; 5084 #global-interrupts = <2>; 5085 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 5086 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5087 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5088 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5089 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5090 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5091 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5092 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5093 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5094 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5095 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5096 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5097 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5098 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5099 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5100 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5101 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5102 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5103 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5104 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5105 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5106 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5107 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5108 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5109 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5110 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5111 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5112 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5113 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5114 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5115 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5116 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5117 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5118 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5119 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5120 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5121 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5122 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5123 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5126 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5127 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5128 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5129 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5130 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5131 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5132 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5133 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5134 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5135 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5136 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5137 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5138 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5139 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5140 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5141 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5142 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5143 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5144 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5145 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5146 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5147 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5148 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5149 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5150 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5151 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5152 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5153 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5154 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5155 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5156 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5157 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5158 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5159 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5160 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5161 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5162 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5163 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5164 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5165 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5166 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5167 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5168 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5169 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5170 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5171 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5172 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5173 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5174 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5175 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5176 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5177 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5178 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5179 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5180 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5181 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 5182 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 5183 }; 5184 5185 adsp: remoteproc@17300000 { 5186 compatible = "qcom,sm8250-adsp-pas"; 5187 reg = <0 0x17300000 0 0x100>; 5188 5189 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 5190 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 5191 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 5192 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 5193 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 5194 interrupt-names = "wdog", "fatal", "ready", 5195 "handover", "stop-ack"; 5196 5197 clocks = <&rpmhcc RPMH_CXO_CLK>; 5198 clock-names = "xo"; 5199 5200 power-domains = <&rpmhpd SM8250_LCX>, 5201 <&rpmhpd SM8250_LMX>; 5202 power-domain-names = "lcx", "lmx"; 5203 5204 memory-region = <&adsp_mem>; 5205 5206 qcom,qmp = <&aoss_qmp>; 5207 5208 qcom,smem-states = <&smp2p_adsp_out 0>; 5209 qcom,smem-state-names = "stop"; 5210 5211 status = "disabled"; 5212 5213 glink-edge { 5214 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 5215 IPCC_MPROC_SIGNAL_GLINK_QMP 5216 IRQ_TYPE_EDGE_RISING>; 5217 mboxes = <&ipcc IPCC_CLIENT_LPASS 5218 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5219 5220 label = "lpass"; 5221 qcom,remote-pid = <2>; 5222 5223 apr { 5224 compatible = "qcom,apr-v2"; 5225 qcom,glink-channels = "apr_audio_svc"; 5226 qcom,domain = <APR_DOMAIN_ADSP>; 5227 #address-cells = <1>; 5228 #size-cells = <0>; 5229 5230 service@3 { 5231 reg = <APR_SVC_ADSP_CORE>; 5232 compatible = "qcom,q6core"; 5233 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 5234 }; 5235 5236 q6afe: service@4 { 5237 compatible = "qcom,q6afe"; 5238 reg = <APR_SVC_AFE>; 5239 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 5240 q6afedai: dais { 5241 compatible = "qcom,q6afe-dais"; 5242 #address-cells = <1>; 5243 #size-cells = <0>; 5244 #sound-dai-cells = <1>; 5245 }; 5246 5247 q6afecc: clock-controller { 5248 compatible = "qcom,q6afe-clocks"; 5249 #clock-cells = <2>; 5250 }; 5251 }; 5252 5253 q6asm: service@7 { 5254 compatible = "qcom,q6asm"; 5255 reg = <APR_SVC_ASM>; 5256 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 5257 q6asmdai: dais { 5258 compatible = "qcom,q6asm-dais"; 5259 #address-cells = <1>; 5260 #size-cells = <0>; 5261 #sound-dai-cells = <1>; 5262 iommus = <&apps_smmu 0x1801 0x0>; 5263 }; 5264 }; 5265 5266 q6adm: service@8 { 5267 compatible = "qcom,q6adm"; 5268 reg = <APR_SVC_ADM>; 5269 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 5270 q6routing: routing { 5271 compatible = "qcom,q6adm-routing"; 5272 #sound-dai-cells = <0>; 5273 }; 5274 }; 5275 }; 5276 5277 fastrpc { 5278 compatible = "qcom,fastrpc"; 5279 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5280 label = "adsp"; 5281 qcom,non-secure-domain; 5282 #address-cells = <1>; 5283 #size-cells = <0>; 5284 5285 compute-cb@3 { 5286 compatible = "qcom,fastrpc-compute-cb"; 5287 reg = <3>; 5288 iommus = <&apps_smmu 0x1803 0x0>; 5289 }; 5290 5291 compute-cb@4 { 5292 compatible = "qcom,fastrpc-compute-cb"; 5293 reg = <4>; 5294 iommus = <&apps_smmu 0x1804 0x0>; 5295 }; 5296 5297 compute-cb@5 { 5298 compatible = "qcom,fastrpc-compute-cb"; 5299 reg = <5>; 5300 iommus = <&apps_smmu 0x1805 0x0>; 5301 }; 5302 }; 5303 }; 5304 }; 5305 5306 intc: interrupt-controller@17a00000 { 5307 compatible = "arm,gic-v3"; 5308 #interrupt-cells = <3>; 5309 interrupt-controller; 5310 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 5311 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 5312 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5313 }; 5314 5315 watchdog@17c10000 { 5316 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; 5317 reg = <0 0x17c10000 0 0x1000>; 5318 clocks = <&sleep_clk>; 5319 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 5320 }; 5321 5322 timer@17c20000 { 5323 #address-cells = <1>; 5324 #size-cells = <1>; 5325 ranges = <0 0 0 0x20000000>; 5326 compatible = "arm,armv7-timer-mem"; 5327 reg = <0x0 0x17c20000 0x0 0x1000>; 5328 clock-frequency = <19200000>; 5329 5330 frame@17c21000 { 5331 frame-number = <0>; 5332 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5333 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5334 reg = <0x17c21000 0x1000>, 5335 <0x17c22000 0x1000>; 5336 }; 5337 5338 frame@17c23000 { 5339 frame-number = <1>; 5340 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5341 reg = <0x17c23000 0x1000>; 5342 status = "disabled"; 5343 }; 5344 5345 frame@17c25000 { 5346 frame-number = <2>; 5347 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5348 reg = <0x17c25000 0x1000>; 5349 status = "disabled"; 5350 }; 5351 5352 frame@17c27000 { 5353 frame-number = <3>; 5354 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5355 reg = <0x17c27000 0x1000>; 5356 status = "disabled"; 5357 }; 5358 5359 frame@17c29000 { 5360 frame-number = <4>; 5361 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5362 reg = <0x17c29000 0x1000>; 5363 status = "disabled"; 5364 }; 5365 5366 frame@17c2b000 { 5367 frame-number = <5>; 5368 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5369 reg = <0x17c2b000 0x1000>; 5370 status = "disabled"; 5371 }; 5372 5373 frame@17c2d000 { 5374 frame-number = <6>; 5375 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5376 reg = <0x17c2d000 0x1000>; 5377 status = "disabled"; 5378 }; 5379 }; 5380 5381 apps_rsc: rsc@18200000 { 5382 label = "apps_rsc"; 5383 compatible = "qcom,rpmh-rsc"; 5384 reg = <0x0 0x18200000 0x0 0x10000>, 5385 <0x0 0x18210000 0x0 0x10000>, 5386 <0x0 0x18220000 0x0 0x10000>; 5387 reg-names = "drv-0", "drv-1", "drv-2"; 5388 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5389 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5390 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5391 qcom,tcs-offset = <0xd00>; 5392 qcom,drv-id = <2>; 5393 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 5394 <WAKE_TCS 3>, <CONTROL_TCS 1>; 5395 power-domains = <&CLUSTER_PD>; 5396 5397 rpmhcc: clock-controller { 5398 compatible = "qcom,sm8250-rpmh-clk"; 5399 #clock-cells = <1>; 5400 clock-names = "xo"; 5401 clocks = <&xo_board>; 5402 }; 5403 5404 rpmhpd: power-controller { 5405 compatible = "qcom,sm8250-rpmhpd"; 5406 #power-domain-cells = <1>; 5407 operating-points-v2 = <&rpmhpd_opp_table>; 5408 5409 rpmhpd_opp_table: opp-table { 5410 compatible = "operating-points-v2"; 5411 5412 rpmhpd_opp_ret: opp1 { 5413 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5414 }; 5415 5416 rpmhpd_opp_min_svs: opp2 { 5417 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5418 }; 5419 5420 rpmhpd_opp_low_svs: opp3 { 5421 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5422 }; 5423 5424 rpmhpd_opp_svs: opp4 { 5425 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5426 }; 5427 5428 rpmhpd_opp_svs_l1: opp5 { 5429 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5430 }; 5431 5432 rpmhpd_opp_nom: opp6 { 5433 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5434 }; 5435 5436 rpmhpd_opp_nom_l1: opp7 { 5437 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5438 }; 5439 5440 rpmhpd_opp_nom_l2: opp8 { 5441 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5442 }; 5443 5444 rpmhpd_opp_turbo: opp9 { 5445 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5446 }; 5447 5448 rpmhpd_opp_turbo_l1: opp10 { 5449 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5450 }; 5451 }; 5452 }; 5453 5454 apps_bcm_voter: bcm-voter { 5455 compatible = "qcom,bcm-voter"; 5456 }; 5457 }; 5458 5459 epss_l3: interconnect@18590000 { 5460 compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3"; 5461 reg = <0 0x18590000 0 0x1000>; 5462 5463 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5464 clock-names = "xo", "alternate"; 5465 5466 #interconnect-cells = <1>; 5467 }; 5468 5469 cpufreq_hw: cpufreq@18591000 { 5470 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; 5471 reg = <0 0x18591000 0 0x1000>, 5472 <0 0x18592000 0 0x1000>, 5473 <0 0x18593000 0 0x1000>; 5474 reg-names = "freq-domain0", "freq-domain1", 5475 "freq-domain2"; 5476 5477 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 5478 clock-names = "xo", "alternate"; 5479 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 5480 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5481 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 5482 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 5483 #freq-domain-cells = <1>; 5484 }; 5485 }; 5486 5487 sound: sound { 5488 }; 5489 5490 timer { 5491 compatible = "arm,armv8-timer"; 5492 interrupts = <GIC_PPI 13 5493 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5494 <GIC_PPI 14 5495 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5496 <GIC_PPI 11 5497 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5498 <GIC_PPI 10 5499 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5500 }; 5501 5502 thermal-zones { 5503 cpu0-thermal { 5504 polling-delay-passive = <250>; 5505 polling-delay = <1000>; 5506 5507 thermal-sensors = <&tsens0 1>; 5508 5509 trips { 5510 cpu0_alert0: trip-point0 { 5511 temperature = <90000>; 5512 hysteresis = <2000>; 5513 type = "passive"; 5514 }; 5515 5516 cpu0_alert1: trip-point1 { 5517 temperature = <95000>; 5518 hysteresis = <2000>; 5519 type = "passive"; 5520 }; 5521 5522 cpu0_crit: cpu-crit { 5523 temperature = <110000>; 5524 hysteresis = <1000>; 5525 type = "critical"; 5526 }; 5527 }; 5528 5529 cooling-maps { 5530 map0 { 5531 trip = <&cpu0_alert0>; 5532 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5533 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5534 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5535 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5536 }; 5537 map1 { 5538 trip = <&cpu0_alert1>; 5539 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5540 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5541 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5542 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5543 }; 5544 }; 5545 }; 5546 5547 cpu1-thermal { 5548 polling-delay-passive = <250>; 5549 polling-delay = <1000>; 5550 5551 thermal-sensors = <&tsens0 2>; 5552 5553 trips { 5554 cpu1_alert0: trip-point0 { 5555 temperature = <90000>; 5556 hysteresis = <2000>; 5557 type = "passive"; 5558 }; 5559 5560 cpu1_alert1: trip-point1 { 5561 temperature = <95000>; 5562 hysteresis = <2000>; 5563 type = "passive"; 5564 }; 5565 5566 cpu1_crit: cpu-crit { 5567 temperature = <110000>; 5568 hysteresis = <1000>; 5569 type = "critical"; 5570 }; 5571 }; 5572 5573 cooling-maps { 5574 map0 { 5575 trip = <&cpu1_alert0>; 5576 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5577 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5578 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5579 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5580 }; 5581 map1 { 5582 trip = <&cpu1_alert1>; 5583 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5584 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5585 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5586 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5587 }; 5588 }; 5589 }; 5590 5591 cpu2-thermal { 5592 polling-delay-passive = <250>; 5593 polling-delay = <1000>; 5594 5595 thermal-sensors = <&tsens0 3>; 5596 5597 trips { 5598 cpu2_alert0: trip-point0 { 5599 temperature = <90000>; 5600 hysteresis = <2000>; 5601 type = "passive"; 5602 }; 5603 5604 cpu2_alert1: trip-point1 { 5605 temperature = <95000>; 5606 hysteresis = <2000>; 5607 type = "passive"; 5608 }; 5609 5610 cpu2_crit: cpu-crit { 5611 temperature = <110000>; 5612 hysteresis = <1000>; 5613 type = "critical"; 5614 }; 5615 }; 5616 5617 cooling-maps { 5618 map0 { 5619 trip = <&cpu2_alert0>; 5620 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5621 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5622 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5623 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5624 }; 5625 map1 { 5626 trip = <&cpu2_alert1>; 5627 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5628 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5629 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5630 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5631 }; 5632 }; 5633 }; 5634 5635 cpu3-thermal { 5636 polling-delay-passive = <250>; 5637 polling-delay = <1000>; 5638 5639 thermal-sensors = <&tsens0 4>; 5640 5641 trips { 5642 cpu3_alert0: trip-point0 { 5643 temperature = <90000>; 5644 hysteresis = <2000>; 5645 type = "passive"; 5646 }; 5647 5648 cpu3_alert1: trip-point1 { 5649 temperature = <95000>; 5650 hysteresis = <2000>; 5651 type = "passive"; 5652 }; 5653 5654 cpu3_crit: cpu-crit { 5655 temperature = <110000>; 5656 hysteresis = <1000>; 5657 type = "critical"; 5658 }; 5659 }; 5660 5661 cooling-maps { 5662 map0 { 5663 trip = <&cpu3_alert0>; 5664 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5665 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5666 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5667 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5668 }; 5669 map1 { 5670 trip = <&cpu3_alert1>; 5671 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5672 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5673 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5674 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5675 }; 5676 }; 5677 }; 5678 5679 cpu4-top-thermal { 5680 polling-delay-passive = <250>; 5681 polling-delay = <1000>; 5682 5683 thermal-sensors = <&tsens0 7>; 5684 5685 trips { 5686 cpu4_top_alert0: trip-point0 { 5687 temperature = <90000>; 5688 hysteresis = <2000>; 5689 type = "passive"; 5690 }; 5691 5692 cpu4_top_alert1: trip-point1 { 5693 temperature = <95000>; 5694 hysteresis = <2000>; 5695 type = "passive"; 5696 }; 5697 5698 cpu4_top_crit: cpu-crit { 5699 temperature = <110000>; 5700 hysteresis = <1000>; 5701 type = "critical"; 5702 }; 5703 }; 5704 5705 cooling-maps { 5706 map0 { 5707 trip = <&cpu4_top_alert0>; 5708 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5709 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5710 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5711 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5712 }; 5713 map1 { 5714 trip = <&cpu4_top_alert1>; 5715 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5716 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5717 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5718 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5719 }; 5720 }; 5721 }; 5722 5723 cpu5-top-thermal { 5724 polling-delay-passive = <250>; 5725 polling-delay = <1000>; 5726 5727 thermal-sensors = <&tsens0 8>; 5728 5729 trips { 5730 cpu5_top_alert0: trip-point0 { 5731 temperature = <90000>; 5732 hysteresis = <2000>; 5733 type = "passive"; 5734 }; 5735 5736 cpu5_top_alert1: trip-point1 { 5737 temperature = <95000>; 5738 hysteresis = <2000>; 5739 type = "passive"; 5740 }; 5741 5742 cpu5_top_crit: cpu-crit { 5743 temperature = <110000>; 5744 hysteresis = <1000>; 5745 type = "critical"; 5746 }; 5747 }; 5748 5749 cooling-maps { 5750 map0 { 5751 trip = <&cpu5_top_alert0>; 5752 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5753 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5754 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5755 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5756 }; 5757 map1 { 5758 trip = <&cpu5_top_alert1>; 5759 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5760 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5761 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5762 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5763 }; 5764 }; 5765 }; 5766 5767 cpu6-top-thermal { 5768 polling-delay-passive = <250>; 5769 polling-delay = <1000>; 5770 5771 thermal-sensors = <&tsens0 9>; 5772 5773 trips { 5774 cpu6_top_alert0: trip-point0 { 5775 temperature = <90000>; 5776 hysteresis = <2000>; 5777 type = "passive"; 5778 }; 5779 5780 cpu6_top_alert1: trip-point1 { 5781 temperature = <95000>; 5782 hysteresis = <2000>; 5783 type = "passive"; 5784 }; 5785 5786 cpu6_top_crit: cpu-crit { 5787 temperature = <110000>; 5788 hysteresis = <1000>; 5789 type = "critical"; 5790 }; 5791 }; 5792 5793 cooling-maps { 5794 map0 { 5795 trip = <&cpu6_top_alert0>; 5796 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5797 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5798 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5799 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5800 }; 5801 map1 { 5802 trip = <&cpu6_top_alert1>; 5803 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5804 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5805 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5806 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5807 }; 5808 }; 5809 }; 5810 5811 cpu7-top-thermal { 5812 polling-delay-passive = <250>; 5813 polling-delay = <1000>; 5814 5815 thermal-sensors = <&tsens0 10>; 5816 5817 trips { 5818 cpu7_top_alert0: trip-point0 { 5819 temperature = <90000>; 5820 hysteresis = <2000>; 5821 type = "passive"; 5822 }; 5823 5824 cpu7_top_alert1: trip-point1 { 5825 temperature = <95000>; 5826 hysteresis = <2000>; 5827 type = "passive"; 5828 }; 5829 5830 cpu7_top_crit: cpu-crit { 5831 temperature = <110000>; 5832 hysteresis = <1000>; 5833 type = "critical"; 5834 }; 5835 }; 5836 5837 cooling-maps { 5838 map0 { 5839 trip = <&cpu7_top_alert0>; 5840 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5841 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5842 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5843 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5844 }; 5845 map1 { 5846 trip = <&cpu7_top_alert1>; 5847 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5848 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5849 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5850 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5851 }; 5852 }; 5853 }; 5854 5855 cpu4-bottom-thermal { 5856 polling-delay-passive = <250>; 5857 polling-delay = <1000>; 5858 5859 thermal-sensors = <&tsens0 11>; 5860 5861 trips { 5862 cpu4_bottom_alert0: trip-point0 { 5863 temperature = <90000>; 5864 hysteresis = <2000>; 5865 type = "passive"; 5866 }; 5867 5868 cpu4_bottom_alert1: trip-point1 { 5869 temperature = <95000>; 5870 hysteresis = <2000>; 5871 type = "passive"; 5872 }; 5873 5874 cpu4_bottom_crit: cpu-crit { 5875 temperature = <110000>; 5876 hysteresis = <1000>; 5877 type = "critical"; 5878 }; 5879 }; 5880 5881 cooling-maps { 5882 map0 { 5883 trip = <&cpu4_bottom_alert0>; 5884 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5885 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5886 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5887 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5888 }; 5889 map1 { 5890 trip = <&cpu4_bottom_alert1>; 5891 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5892 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5893 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5894 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5895 }; 5896 }; 5897 }; 5898 5899 cpu5-bottom-thermal { 5900 polling-delay-passive = <250>; 5901 polling-delay = <1000>; 5902 5903 thermal-sensors = <&tsens0 12>; 5904 5905 trips { 5906 cpu5_bottom_alert0: trip-point0 { 5907 temperature = <90000>; 5908 hysteresis = <2000>; 5909 type = "passive"; 5910 }; 5911 5912 cpu5_bottom_alert1: trip-point1 { 5913 temperature = <95000>; 5914 hysteresis = <2000>; 5915 type = "passive"; 5916 }; 5917 5918 cpu5_bottom_crit: cpu-crit { 5919 temperature = <110000>; 5920 hysteresis = <1000>; 5921 type = "critical"; 5922 }; 5923 }; 5924 5925 cooling-maps { 5926 map0 { 5927 trip = <&cpu5_bottom_alert0>; 5928 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5929 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5930 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5931 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5932 }; 5933 map1 { 5934 trip = <&cpu5_bottom_alert1>; 5935 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5936 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5937 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5938 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5939 }; 5940 }; 5941 }; 5942 5943 cpu6-bottom-thermal { 5944 polling-delay-passive = <250>; 5945 polling-delay = <1000>; 5946 5947 thermal-sensors = <&tsens0 13>; 5948 5949 trips { 5950 cpu6_bottom_alert0: trip-point0 { 5951 temperature = <90000>; 5952 hysteresis = <2000>; 5953 type = "passive"; 5954 }; 5955 5956 cpu6_bottom_alert1: trip-point1 { 5957 temperature = <95000>; 5958 hysteresis = <2000>; 5959 type = "passive"; 5960 }; 5961 5962 cpu6_bottom_crit: cpu-crit { 5963 temperature = <110000>; 5964 hysteresis = <1000>; 5965 type = "critical"; 5966 }; 5967 }; 5968 5969 cooling-maps { 5970 map0 { 5971 trip = <&cpu6_bottom_alert0>; 5972 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5973 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5974 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5975 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5976 }; 5977 map1 { 5978 trip = <&cpu6_bottom_alert1>; 5979 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5980 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5981 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5982 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5983 }; 5984 }; 5985 }; 5986 5987 cpu7-bottom-thermal { 5988 polling-delay-passive = <250>; 5989 polling-delay = <1000>; 5990 5991 thermal-sensors = <&tsens0 14>; 5992 5993 trips { 5994 cpu7_bottom_alert0: trip-point0 { 5995 temperature = <90000>; 5996 hysteresis = <2000>; 5997 type = "passive"; 5998 }; 5999 6000 cpu7_bottom_alert1: trip-point1 { 6001 temperature = <95000>; 6002 hysteresis = <2000>; 6003 type = "passive"; 6004 }; 6005 6006 cpu7_bottom_crit: cpu-crit { 6007 temperature = <110000>; 6008 hysteresis = <1000>; 6009 type = "critical"; 6010 }; 6011 }; 6012 6013 cooling-maps { 6014 map0 { 6015 trip = <&cpu7_bottom_alert0>; 6016 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6017 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6018 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6019 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6020 }; 6021 map1 { 6022 trip = <&cpu7_bottom_alert1>; 6023 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6024 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6025 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6026 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6027 }; 6028 }; 6029 }; 6030 6031 aoss0-thermal { 6032 polling-delay-passive = <250>; 6033 polling-delay = <1000>; 6034 6035 thermal-sensors = <&tsens0 0>; 6036 6037 trips { 6038 aoss0_alert0: trip-point0 { 6039 temperature = <90000>; 6040 hysteresis = <2000>; 6041 type = "hot"; 6042 }; 6043 }; 6044 }; 6045 6046 cluster0-thermal { 6047 polling-delay-passive = <250>; 6048 polling-delay = <1000>; 6049 6050 thermal-sensors = <&tsens0 5>; 6051 6052 trips { 6053 cluster0_alert0: trip-point0 { 6054 temperature = <90000>; 6055 hysteresis = <2000>; 6056 type = "hot"; 6057 }; 6058 cluster0_crit: cluster0_crit { 6059 temperature = <110000>; 6060 hysteresis = <2000>; 6061 type = "critical"; 6062 }; 6063 }; 6064 }; 6065 6066 cluster1-thermal { 6067 polling-delay-passive = <250>; 6068 polling-delay = <1000>; 6069 6070 thermal-sensors = <&tsens0 6>; 6071 6072 trips { 6073 cluster1_alert0: trip-point0 { 6074 temperature = <90000>; 6075 hysteresis = <2000>; 6076 type = "hot"; 6077 }; 6078 cluster1_crit: cluster1_crit { 6079 temperature = <110000>; 6080 hysteresis = <2000>; 6081 type = "critical"; 6082 }; 6083 }; 6084 }; 6085 6086 gpu-top-thermal { 6087 polling-delay-passive = <250>; 6088 polling-delay = <1000>; 6089 6090 thermal-sensors = <&tsens0 15>; 6091 6092 trips { 6093 gpu1_alert0: trip-point0 { 6094 temperature = <90000>; 6095 hysteresis = <2000>; 6096 type = "hot"; 6097 }; 6098 }; 6099 }; 6100 6101 aoss1-thermal { 6102 polling-delay-passive = <250>; 6103 polling-delay = <1000>; 6104 6105 thermal-sensors = <&tsens1 0>; 6106 6107 trips { 6108 aoss1_alert0: trip-point0 { 6109 temperature = <90000>; 6110 hysteresis = <2000>; 6111 type = "hot"; 6112 }; 6113 }; 6114 }; 6115 6116 wlan-thermal { 6117 polling-delay-passive = <250>; 6118 polling-delay = <1000>; 6119 6120 thermal-sensors = <&tsens1 1>; 6121 6122 trips { 6123 wlan_alert0: trip-point0 { 6124 temperature = <90000>; 6125 hysteresis = <2000>; 6126 type = "hot"; 6127 }; 6128 }; 6129 }; 6130 6131 video-thermal { 6132 polling-delay-passive = <250>; 6133 polling-delay = <1000>; 6134 6135 thermal-sensors = <&tsens1 2>; 6136 6137 trips { 6138 video_alert0: trip-point0 { 6139 temperature = <90000>; 6140 hysteresis = <2000>; 6141 type = "hot"; 6142 }; 6143 }; 6144 }; 6145 6146 mem-thermal { 6147 polling-delay-passive = <250>; 6148 polling-delay = <1000>; 6149 6150 thermal-sensors = <&tsens1 3>; 6151 6152 trips { 6153 mem_alert0: trip-point0 { 6154 temperature = <90000>; 6155 hysteresis = <2000>; 6156 type = "hot"; 6157 }; 6158 }; 6159 }; 6160 6161 q6-hvx-thermal { 6162 polling-delay-passive = <250>; 6163 polling-delay = <1000>; 6164 6165 thermal-sensors = <&tsens1 4>; 6166 6167 trips { 6168 q6_hvx_alert0: trip-point0 { 6169 temperature = <90000>; 6170 hysteresis = <2000>; 6171 type = "hot"; 6172 }; 6173 }; 6174 }; 6175 6176 camera-thermal { 6177 polling-delay-passive = <250>; 6178 polling-delay = <1000>; 6179 6180 thermal-sensors = <&tsens1 5>; 6181 6182 trips { 6183 camera_alert0: trip-point0 { 6184 temperature = <90000>; 6185 hysteresis = <2000>; 6186 type = "hot"; 6187 }; 6188 }; 6189 }; 6190 6191 compute-thermal { 6192 polling-delay-passive = <250>; 6193 polling-delay = <1000>; 6194 6195 thermal-sensors = <&tsens1 6>; 6196 6197 trips { 6198 compute_alert0: trip-point0 { 6199 temperature = <90000>; 6200 hysteresis = <2000>; 6201 type = "hot"; 6202 }; 6203 }; 6204 }; 6205 6206 npu-thermal { 6207 polling-delay-passive = <250>; 6208 polling-delay = <1000>; 6209 6210 thermal-sensors = <&tsens1 7>; 6211 6212 trips { 6213 npu_alert0: trip-point0 { 6214 temperature = <90000>; 6215 hysteresis = <2000>; 6216 type = "hot"; 6217 }; 6218 }; 6219 }; 6220 6221 gpu-bottom-thermal { 6222 polling-delay-passive = <250>; 6223 polling-delay = <1000>; 6224 6225 thermal-sensors = <&tsens1 8>; 6226 6227 trips { 6228 gpu2_alert0: trip-point0 { 6229 temperature = <90000>; 6230 hysteresis = <2000>; 6231 type = "hot"; 6232 }; 6233 }; 6234 }; 6235 }; 6236}; 6237