1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2019, Linaro Limited 5 */ 6 7#include <dt-bindings/dma/qcom-gpi.h> 8#include <dt-bindings/firmware/qcom,scm.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/phy/phy-qcom-qmp.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/soc/qcom,rpmh-rsc.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,dispcc-sm8150.h> 15#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 16#include <dt-bindings/clock/qcom,gcc-sm8150.h> 17#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 18#include <dt-bindings/clock/qcom,videocc-sm8150.h> 19#include <dt-bindings/interconnect/qcom,osm-l3.h> 20#include <dt-bindings/interconnect/qcom,sm8150.h> 21#include <dt-bindings/clock/qcom,sm8150-camcc.h> 22#include <dt-bindings/thermal/thermal.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 chosen { }; 31 32 clocks { 33 xo_board: xo-board { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <38400000>; 37 clock-output-names = "xo_board"; 38 }; 39 40 sleep_clk: sleep-clk { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <32764>; 44 clock-output-names = "sleep_clk"; 45 }; 46 }; 47 48 cpus { 49 #address-cells = <2>; 50 #size-cells = <0>; 51 52 cpu0: cpu@0 { 53 device_type = "cpu"; 54 compatible = "qcom,kryo485"; 55 reg = <0x0 0x0>; 56 clocks = <&cpufreq_hw 0>; 57 enable-method = "psci"; 58 capacity-dmips-mhz = <488>; 59 dynamic-power-coefficient = <232>; 60 next-level-cache = <&l2_0>; 61 qcom,freq-domain = <&cpufreq_hw 0>; 62 operating-points-v2 = <&cpu0_opp_table>; 63 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 64 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 65 power-domains = <&cpu_pd0>; 66 power-domain-names = "psci"; 67 #cooling-cells = <2>; 68 l2_0: l2-cache { 69 compatible = "cache"; 70 cache-level = <2>; 71 cache-unified; 72 next-level-cache = <&l3_0>; 73 l3_0: l3-cache { 74 compatible = "cache"; 75 cache-level = <3>; 76 cache-unified; 77 }; 78 }; 79 }; 80 81 cpu1: cpu@100 { 82 device_type = "cpu"; 83 compatible = "qcom,kryo485"; 84 reg = <0x0 0x100>; 85 clocks = <&cpufreq_hw 0>; 86 enable-method = "psci"; 87 capacity-dmips-mhz = <488>; 88 dynamic-power-coefficient = <232>; 89 next-level-cache = <&l2_100>; 90 qcom,freq-domain = <&cpufreq_hw 0>; 91 operating-points-v2 = <&cpu0_opp_table>; 92 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 93 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 94 power-domains = <&cpu_pd1>; 95 power-domain-names = "psci"; 96 #cooling-cells = <2>; 97 l2_100: l2-cache { 98 compatible = "cache"; 99 cache-level = <2>; 100 cache-unified; 101 next-level-cache = <&l3_0>; 102 }; 103 }; 104 105 cpu2: cpu@200 { 106 device_type = "cpu"; 107 compatible = "qcom,kryo485"; 108 reg = <0x0 0x200>; 109 clocks = <&cpufreq_hw 0>; 110 enable-method = "psci"; 111 capacity-dmips-mhz = <488>; 112 dynamic-power-coefficient = <232>; 113 next-level-cache = <&l2_200>; 114 qcom,freq-domain = <&cpufreq_hw 0>; 115 operating-points-v2 = <&cpu0_opp_table>; 116 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 117 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 118 power-domains = <&cpu_pd2>; 119 power-domain-names = "psci"; 120 #cooling-cells = <2>; 121 l2_200: l2-cache { 122 compatible = "cache"; 123 cache-level = <2>; 124 cache-unified; 125 next-level-cache = <&l3_0>; 126 }; 127 }; 128 129 cpu3: cpu@300 { 130 device_type = "cpu"; 131 compatible = "qcom,kryo485"; 132 reg = <0x0 0x300>; 133 clocks = <&cpufreq_hw 0>; 134 enable-method = "psci"; 135 capacity-dmips-mhz = <488>; 136 dynamic-power-coefficient = <232>; 137 next-level-cache = <&l2_300>; 138 qcom,freq-domain = <&cpufreq_hw 0>; 139 operating-points-v2 = <&cpu0_opp_table>; 140 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 141 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 142 power-domains = <&cpu_pd3>; 143 power-domain-names = "psci"; 144 #cooling-cells = <2>; 145 l2_300: l2-cache { 146 compatible = "cache"; 147 cache-level = <2>; 148 cache-unified; 149 next-level-cache = <&l3_0>; 150 }; 151 }; 152 153 cpu4: cpu@400 { 154 device_type = "cpu"; 155 compatible = "qcom,kryo485"; 156 reg = <0x0 0x400>; 157 clocks = <&cpufreq_hw 1>; 158 enable-method = "psci"; 159 capacity-dmips-mhz = <1024>; 160 dynamic-power-coefficient = <369>; 161 next-level-cache = <&l2_400>; 162 qcom,freq-domain = <&cpufreq_hw 1>; 163 operating-points-v2 = <&cpu4_opp_table>; 164 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 165 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 166 power-domains = <&cpu_pd4>; 167 power-domain-names = "psci"; 168 #cooling-cells = <2>; 169 l2_400: l2-cache { 170 compatible = "cache"; 171 cache-level = <2>; 172 cache-unified; 173 next-level-cache = <&l3_0>; 174 }; 175 }; 176 177 cpu5: cpu@500 { 178 device_type = "cpu"; 179 compatible = "qcom,kryo485"; 180 reg = <0x0 0x500>; 181 clocks = <&cpufreq_hw 1>; 182 enable-method = "psci"; 183 capacity-dmips-mhz = <1024>; 184 dynamic-power-coefficient = <369>; 185 next-level-cache = <&l2_500>; 186 qcom,freq-domain = <&cpufreq_hw 1>; 187 operating-points-v2 = <&cpu4_opp_table>; 188 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 189 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 190 power-domains = <&cpu_pd5>; 191 power-domain-names = "psci"; 192 #cooling-cells = <2>; 193 l2_500: l2-cache { 194 compatible = "cache"; 195 cache-level = <2>; 196 cache-unified; 197 next-level-cache = <&l3_0>; 198 }; 199 }; 200 201 cpu6: cpu@600 { 202 device_type = "cpu"; 203 compatible = "qcom,kryo485"; 204 reg = <0x0 0x600>; 205 clocks = <&cpufreq_hw 1>; 206 enable-method = "psci"; 207 capacity-dmips-mhz = <1024>; 208 dynamic-power-coefficient = <369>; 209 next-level-cache = <&l2_600>; 210 qcom,freq-domain = <&cpufreq_hw 1>; 211 operating-points-v2 = <&cpu4_opp_table>; 212 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 213 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 214 power-domains = <&cpu_pd6>; 215 power-domain-names = "psci"; 216 #cooling-cells = <2>; 217 l2_600: l2-cache { 218 compatible = "cache"; 219 cache-level = <2>; 220 cache-unified; 221 next-level-cache = <&l3_0>; 222 }; 223 }; 224 225 cpu7: cpu@700 { 226 device_type = "cpu"; 227 compatible = "qcom,kryo485"; 228 reg = <0x0 0x700>; 229 clocks = <&cpufreq_hw 2>; 230 enable-method = "psci"; 231 capacity-dmips-mhz = <1024>; 232 dynamic-power-coefficient = <421>; 233 next-level-cache = <&l2_700>; 234 qcom,freq-domain = <&cpufreq_hw 2>; 235 operating-points-v2 = <&cpu7_opp_table>; 236 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 237 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 238 power-domains = <&cpu_pd7>; 239 power-domain-names = "psci"; 240 #cooling-cells = <2>; 241 l2_700: l2-cache { 242 compatible = "cache"; 243 cache-level = <2>; 244 cache-unified; 245 next-level-cache = <&l3_0>; 246 }; 247 }; 248 249 cpu-map { 250 cluster0 { 251 core0 { 252 cpu = <&cpu0>; 253 }; 254 255 core1 { 256 cpu = <&cpu1>; 257 }; 258 259 core2 { 260 cpu = <&cpu2>; 261 }; 262 263 core3 { 264 cpu = <&cpu3>; 265 }; 266 267 core4 { 268 cpu = <&cpu4>; 269 }; 270 271 core5 { 272 cpu = <&cpu5>; 273 }; 274 275 core6 { 276 cpu = <&cpu6>; 277 }; 278 279 core7 { 280 cpu = <&cpu7>; 281 }; 282 }; 283 }; 284 285 idle-states { 286 entry-method = "psci"; 287 288 little_cpu_sleep_0: cpu-sleep-0-0 { 289 compatible = "arm,idle-state"; 290 idle-state-name = "little-rail-power-collapse"; 291 arm,psci-suspend-param = <0x40000004>; 292 entry-latency-us = <355>; 293 exit-latency-us = <909>; 294 min-residency-us = <3934>; 295 local-timer-stop; 296 }; 297 298 big_cpu_sleep_0: cpu-sleep-1-0 { 299 compatible = "arm,idle-state"; 300 idle-state-name = "big-rail-power-collapse"; 301 arm,psci-suspend-param = <0x40000004>; 302 entry-latency-us = <241>; 303 exit-latency-us = <1461>; 304 min-residency-us = <4488>; 305 local-timer-stop; 306 }; 307 }; 308 309 domain-idle-states { 310 cluster_sleep_0: cluster-sleep-0 { 311 compatible = "domain-idle-state"; 312 arm,psci-suspend-param = <0x4100c244>; 313 entry-latency-us = <3263>; 314 exit-latency-us = <6562>; 315 min-residency-us = <9987>; 316 }; 317 }; 318 }; 319 320 cpu0_opp_table: opp-table-cpu0 { 321 compatible = "operating-points-v2"; 322 opp-shared; 323 324 cpu0_opp1: opp-300000000 { 325 opp-hz = /bits/ 64 <300000000>; 326 opp-peak-kBps = <800000 9600000>; 327 }; 328 329 cpu0_opp2: opp-403200000 { 330 opp-hz = /bits/ 64 <403200000>; 331 opp-peak-kBps = <800000 9600000>; 332 }; 333 334 cpu0_opp3: opp-499200000 { 335 opp-hz = /bits/ 64 <499200000>; 336 opp-peak-kBps = <800000 12902400>; 337 }; 338 339 cpu0_opp4: opp-576000000 { 340 opp-hz = /bits/ 64 <576000000>; 341 opp-peak-kBps = <800000 12902400>; 342 }; 343 344 cpu0_opp5: opp-672000000 { 345 opp-hz = /bits/ 64 <672000000>; 346 opp-peak-kBps = <800000 15974400>; 347 }; 348 349 cpu0_opp6: opp-768000000 { 350 opp-hz = /bits/ 64 <768000000>; 351 opp-peak-kBps = <1804000 19660800>; 352 }; 353 354 cpu0_opp7: opp-844800000 { 355 opp-hz = /bits/ 64 <844800000>; 356 opp-peak-kBps = <1804000 19660800>; 357 }; 358 359 cpu0_opp8: opp-940800000 { 360 opp-hz = /bits/ 64 <940800000>; 361 opp-peak-kBps = <1804000 22732800>; 362 }; 363 364 cpu0_opp9: opp-1036800000 { 365 opp-hz = /bits/ 64 <1036800000>; 366 opp-peak-kBps = <1804000 22732800>; 367 }; 368 369 cpu0_opp10: opp-1113600000 { 370 opp-hz = /bits/ 64 <1113600000>; 371 opp-peak-kBps = <2188000 25804800>; 372 }; 373 374 cpu0_opp11: opp-1209600000 { 375 opp-hz = /bits/ 64 <1209600000>; 376 opp-peak-kBps = <2188000 31948800>; 377 }; 378 379 cpu0_opp12: opp-1305600000 { 380 opp-hz = /bits/ 64 <1305600000>; 381 opp-peak-kBps = <3072000 31948800>; 382 }; 383 384 cpu0_opp13: opp-1382400000 { 385 opp-hz = /bits/ 64 <1382400000>; 386 opp-peak-kBps = <3072000 31948800>; 387 }; 388 389 cpu0_opp14: opp-1478400000 { 390 opp-hz = /bits/ 64 <1478400000>; 391 opp-peak-kBps = <3072000 31948800>; 392 }; 393 394 cpu0_opp15: opp-1555200000 { 395 opp-hz = /bits/ 64 <1555200000>; 396 opp-peak-kBps = <3072000 40550400>; 397 }; 398 399 cpu0_opp16: opp-1632000000 { 400 opp-hz = /bits/ 64 <1632000000>; 401 opp-peak-kBps = <3072000 40550400>; 402 }; 403 404 cpu0_opp17: opp-1708800000 { 405 opp-hz = /bits/ 64 <1708800000>; 406 opp-peak-kBps = <3072000 43008000>; 407 }; 408 409 cpu0_opp18: opp-1785600000 { 410 opp-hz = /bits/ 64 <1785600000>; 411 opp-peak-kBps = <3072000 43008000>; 412 }; 413 }; 414 415 cpu4_opp_table: opp-table-cpu4 { 416 compatible = "operating-points-v2"; 417 opp-shared; 418 419 cpu4_opp1: opp-710400000 { 420 opp-hz = /bits/ 64 <710400000>; 421 opp-peak-kBps = <1804000 15974400>; 422 }; 423 424 cpu4_opp2: opp-825600000 { 425 opp-hz = /bits/ 64 <825600000>; 426 opp-peak-kBps = <2188000 19660800>; 427 }; 428 429 cpu4_opp3: opp-940800000 { 430 opp-hz = /bits/ 64 <940800000>; 431 opp-peak-kBps = <2188000 22732800>; 432 }; 433 434 cpu4_opp4: opp-1056000000 { 435 opp-hz = /bits/ 64 <1056000000>; 436 opp-peak-kBps = <3072000 25804800>; 437 }; 438 439 cpu4_opp5: opp-1171200000 { 440 opp-hz = /bits/ 64 <1171200000>; 441 opp-peak-kBps = <3072000 31948800>; 442 }; 443 444 cpu4_opp6: opp-1286400000 { 445 opp-hz = /bits/ 64 <1286400000>; 446 opp-peak-kBps = <4068000 31948800>; 447 }; 448 449 cpu4_opp7: opp-1401600000 { 450 opp-hz = /bits/ 64 <1401600000>; 451 opp-peak-kBps = <4068000 31948800>; 452 }; 453 454 cpu4_opp8: opp-1497600000 { 455 opp-hz = /bits/ 64 <1497600000>; 456 opp-peak-kBps = <4068000 40550400>; 457 }; 458 459 cpu4_opp9: opp-1612800000 { 460 opp-hz = /bits/ 64 <1612800000>; 461 opp-peak-kBps = <4068000 40550400>; 462 }; 463 464 cpu4_opp10: opp-1708800000 { 465 opp-hz = /bits/ 64 <1708800000>; 466 opp-peak-kBps = <4068000 43008000>; 467 }; 468 469 cpu4_opp11: opp-1804800000 { 470 opp-hz = /bits/ 64 <1804800000>; 471 opp-peak-kBps = <6220000 43008000>; 472 }; 473 474 cpu4_opp12: opp-1920000000 { 475 opp-hz = /bits/ 64 <1920000000>; 476 opp-peak-kBps = <6220000 49152000>; 477 }; 478 479 cpu4_opp13: opp-2016000000 { 480 opp-hz = /bits/ 64 <2016000000>; 481 opp-peak-kBps = <7216000 49152000>; 482 }; 483 484 cpu4_opp14: opp-2131200000 { 485 opp-hz = /bits/ 64 <2131200000>; 486 opp-peak-kBps = <8368000 49152000>; 487 }; 488 489 cpu4_opp15: opp-2227200000 { 490 opp-hz = /bits/ 64 <2227200000>; 491 opp-peak-kBps = <8368000 51609600>; 492 }; 493 494 cpu4_opp16: opp-2323200000 { 495 opp-hz = /bits/ 64 <2323200000>; 496 opp-peak-kBps = <8368000 51609600>; 497 }; 498 499 cpu4_opp17: opp-2419200000 { 500 opp-hz = /bits/ 64 <2419200000>; 501 opp-peak-kBps = <8368000 51609600>; 502 }; 503 }; 504 505 cpu7_opp_table: opp-table-cpu7 { 506 compatible = "operating-points-v2"; 507 opp-shared; 508 509 cpu7_opp1: opp-825600000 { 510 opp-hz = /bits/ 64 <825600000>; 511 opp-peak-kBps = <2188000 19660800>; 512 }; 513 514 cpu7_opp2: opp-940800000 { 515 opp-hz = /bits/ 64 <940800000>; 516 opp-peak-kBps = <2188000 22732800>; 517 }; 518 519 cpu7_opp3: opp-1056000000 { 520 opp-hz = /bits/ 64 <1056000000>; 521 opp-peak-kBps = <3072000 25804800>; 522 }; 523 524 cpu7_opp4: opp-1171200000 { 525 opp-hz = /bits/ 64 <1171200000>; 526 opp-peak-kBps = <3072000 31948800>; 527 }; 528 529 cpu7_opp5: opp-1286400000 { 530 opp-hz = /bits/ 64 <1286400000>; 531 opp-peak-kBps = <4068000 31948800>; 532 }; 533 534 cpu7_opp6: opp-1401600000 { 535 opp-hz = /bits/ 64 <1401600000>; 536 opp-peak-kBps = <4068000 31948800>; 537 }; 538 539 cpu7_opp7: opp-1497600000 { 540 opp-hz = /bits/ 64 <1497600000>; 541 opp-peak-kBps = <4068000 40550400>; 542 }; 543 544 cpu7_opp8: opp-1612800000 { 545 opp-hz = /bits/ 64 <1612800000>; 546 opp-peak-kBps = <4068000 40550400>; 547 }; 548 549 cpu7_opp9: opp-1708800000 { 550 opp-hz = /bits/ 64 <1708800000>; 551 opp-peak-kBps = <4068000 43008000>; 552 }; 553 554 cpu7_opp10: opp-1804800000 { 555 opp-hz = /bits/ 64 <1804800000>; 556 opp-peak-kBps = <6220000 43008000>; 557 }; 558 559 cpu7_opp11: opp-1920000000 { 560 opp-hz = /bits/ 64 <1920000000>; 561 opp-peak-kBps = <6220000 49152000>; 562 }; 563 564 cpu7_opp12: opp-2016000000 { 565 opp-hz = /bits/ 64 <2016000000>; 566 opp-peak-kBps = <7216000 49152000>; 567 }; 568 569 cpu7_opp13: opp-2131200000 { 570 opp-hz = /bits/ 64 <2131200000>; 571 opp-peak-kBps = <8368000 49152000>; 572 }; 573 574 cpu7_opp14: opp-2227200000 { 575 opp-hz = /bits/ 64 <2227200000>; 576 opp-peak-kBps = <8368000 51609600>; 577 }; 578 579 cpu7_opp15: opp-2323200000 { 580 opp-hz = /bits/ 64 <2323200000>; 581 opp-peak-kBps = <8368000 51609600>; 582 }; 583 584 cpu7_opp16: opp-2419200000 { 585 opp-hz = /bits/ 64 <2419200000>; 586 opp-peak-kBps = <8368000 51609600>; 587 }; 588 589 cpu7_opp17: opp-2534400000 { 590 opp-hz = /bits/ 64 <2534400000>; 591 opp-peak-kBps = <8368000 51609600>; 592 }; 593 594 cpu7_opp18: opp-2649600000 { 595 opp-hz = /bits/ 64 <2649600000>; 596 opp-peak-kBps = <8368000 51609600>; 597 }; 598 599 cpu7_opp19: opp-2745600000 { 600 opp-hz = /bits/ 64 <2745600000>; 601 opp-peak-kBps = <8368000 51609600>; 602 }; 603 604 cpu7_opp20: opp-2841600000 { 605 opp-hz = /bits/ 64 <2841600000>; 606 opp-peak-kBps = <8368000 51609600>; 607 }; 608 }; 609 610 firmware { 611 scm: scm { 612 compatible = "qcom,scm-sm8150", "qcom,scm"; 613 #reset-cells = <1>; 614 }; 615 }; 616 617 memory@80000000 { 618 device_type = "memory"; 619 /* We expect the bootloader to fill in the size */ 620 reg = <0x0 0x80000000 0x0 0x0>; 621 }; 622 623 pmu { 624 compatible = "arm,armv8-pmuv3"; 625 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 626 }; 627 628 psci { 629 compatible = "arm,psci-1.0"; 630 method = "smc"; 631 632 cpu_pd0: power-domain-cpu0 { 633 #power-domain-cells = <0>; 634 power-domains = <&cluster_pd>; 635 domain-idle-states = <&little_cpu_sleep_0>; 636 }; 637 638 cpu_pd1: power-domain-cpu1 { 639 #power-domain-cells = <0>; 640 power-domains = <&cluster_pd>; 641 domain-idle-states = <&little_cpu_sleep_0>; 642 }; 643 644 cpu_pd2: power-domain-cpu2 { 645 #power-domain-cells = <0>; 646 power-domains = <&cluster_pd>; 647 domain-idle-states = <&little_cpu_sleep_0>; 648 }; 649 650 cpu_pd3: power-domain-cpu3 { 651 #power-domain-cells = <0>; 652 power-domains = <&cluster_pd>; 653 domain-idle-states = <&little_cpu_sleep_0>; 654 }; 655 656 cpu_pd4: power-domain-cpu4 { 657 #power-domain-cells = <0>; 658 power-domains = <&cluster_pd>; 659 domain-idle-states = <&big_cpu_sleep_0>; 660 }; 661 662 cpu_pd5: power-domain-cpu5 { 663 #power-domain-cells = <0>; 664 power-domains = <&cluster_pd>; 665 domain-idle-states = <&big_cpu_sleep_0>; 666 }; 667 668 cpu_pd6: power-domain-cpu6 { 669 #power-domain-cells = <0>; 670 power-domains = <&cluster_pd>; 671 domain-idle-states = <&big_cpu_sleep_0>; 672 }; 673 674 cpu_pd7: power-domain-cpu7 { 675 #power-domain-cells = <0>; 676 power-domains = <&cluster_pd>; 677 domain-idle-states = <&big_cpu_sleep_0>; 678 }; 679 680 cluster_pd: power-domain-cpu-cluster0 { 681 #power-domain-cells = <0>; 682 domain-idle-states = <&cluster_sleep_0>; 683 }; 684 }; 685 686 reserved-memory { 687 #address-cells = <2>; 688 #size-cells = <2>; 689 ranges; 690 691 hyp_mem: memory@85700000 { 692 reg = <0x0 0x85700000 0x0 0x600000>; 693 no-map; 694 }; 695 696 xbl_mem: memory@85d00000 { 697 reg = <0x0 0x85d00000 0x0 0x140000>; 698 no-map; 699 }; 700 701 aop_mem: memory@85f00000 { 702 reg = <0x0 0x85f00000 0x0 0x20000>; 703 no-map; 704 }; 705 706 aop_cmd_db: memory@85f20000 { 707 compatible = "qcom,cmd-db"; 708 reg = <0x0 0x85f20000 0x0 0x20000>; 709 no-map; 710 }; 711 712 smem_mem: memory@86000000 { 713 reg = <0x0 0x86000000 0x0 0x200000>; 714 no-map; 715 }; 716 717 tz_mem: memory@86200000 { 718 reg = <0x0 0x86200000 0x0 0x3900000>; 719 no-map; 720 }; 721 722 rmtfs_mem: memory@89b00000 { 723 compatible = "qcom,rmtfs-mem"; 724 reg = <0x0 0x89b00000 0x0 0x200000>; 725 no-map; 726 727 qcom,client-id = <1>; 728 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 729 }; 730 731 camera_mem: memory@8b700000 { 732 reg = <0x0 0x8b700000 0x0 0x500000>; 733 no-map; 734 }; 735 736 wlan_mem: memory@8bc00000 { 737 reg = <0x0 0x8bc00000 0x0 0x180000>; 738 no-map; 739 }; 740 741 npu_mem: memory@8bd80000 { 742 reg = <0x0 0x8bd80000 0x0 0x80000>; 743 no-map; 744 }; 745 746 adsp_mem: memory@8be00000 { 747 reg = <0x0 0x8be00000 0x0 0x1a00000>; 748 no-map; 749 }; 750 751 mpss_mem: memory@8d800000 { 752 reg = <0x0 0x8d800000 0x0 0x9600000>; 753 no-map; 754 }; 755 756 venus_mem: memory@96e00000 { 757 reg = <0x0 0x96e00000 0x0 0x500000>; 758 no-map; 759 }; 760 761 slpi_mem: memory@97300000 { 762 reg = <0x0 0x97300000 0x0 0x1400000>; 763 no-map; 764 }; 765 766 ipa_fw_mem: memory@98700000 { 767 reg = <0x0 0x98700000 0x0 0x10000>; 768 no-map; 769 }; 770 771 ipa_gsi_mem: memory@98710000 { 772 reg = <0x0 0x98710000 0x0 0x5000>; 773 no-map; 774 }; 775 776 gpu_mem: memory@98715000 { 777 reg = <0x0 0x98715000 0x0 0x2000>; 778 no-map; 779 }; 780 781 spss_mem: memory@98800000 { 782 reg = <0x0 0x98800000 0x0 0x100000>; 783 no-map; 784 }; 785 786 cdsp_mem: memory@98900000 { 787 reg = <0x0 0x98900000 0x0 0x1400000>; 788 no-map; 789 }; 790 791 qseecom_mem: memory@9e400000 { 792 reg = <0x0 0x9e400000 0x0 0x1400000>; 793 no-map; 794 }; 795 }; 796 797 smem { 798 compatible = "qcom,smem"; 799 memory-region = <&smem_mem>; 800 hwlocks = <&tcsr_mutex 3>; 801 }; 802 803 smp2p-cdsp { 804 compatible = "qcom,smp2p"; 805 qcom,smem = <94>, <432>; 806 807 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 808 809 mboxes = <&apss_shared 6>; 810 811 qcom,local-pid = <0>; 812 qcom,remote-pid = <5>; 813 814 cdsp_smp2p_out: master-kernel { 815 qcom,entry-name = "master-kernel"; 816 #qcom,smem-state-cells = <1>; 817 }; 818 819 cdsp_smp2p_in: slave-kernel { 820 qcom,entry-name = "slave-kernel"; 821 822 interrupt-controller; 823 #interrupt-cells = <2>; 824 }; 825 }; 826 827 smp2p-lpass { 828 compatible = "qcom,smp2p"; 829 qcom,smem = <443>, <429>; 830 831 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 832 833 mboxes = <&apss_shared 10>; 834 835 qcom,local-pid = <0>; 836 qcom,remote-pid = <2>; 837 838 adsp_smp2p_out: master-kernel { 839 qcom,entry-name = "master-kernel"; 840 #qcom,smem-state-cells = <1>; 841 }; 842 843 adsp_smp2p_in: slave-kernel { 844 qcom,entry-name = "slave-kernel"; 845 846 interrupt-controller; 847 #interrupt-cells = <2>; 848 }; 849 }; 850 851 smp2p-mpss { 852 compatible = "qcom,smp2p"; 853 qcom,smem = <435>, <428>; 854 855 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 856 857 mboxes = <&apss_shared 14>; 858 859 qcom,local-pid = <0>; 860 qcom,remote-pid = <1>; 861 862 modem_smp2p_out: master-kernel { 863 qcom,entry-name = "master-kernel"; 864 #qcom,smem-state-cells = <1>; 865 }; 866 867 modem_smp2p_in: slave-kernel { 868 qcom,entry-name = "slave-kernel"; 869 870 interrupt-controller; 871 #interrupt-cells = <2>; 872 }; 873 }; 874 875 smp2p-slpi { 876 compatible = "qcom,smp2p"; 877 qcom,smem = <481>, <430>; 878 879 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 880 881 mboxes = <&apss_shared 26>; 882 883 qcom,local-pid = <0>; 884 qcom,remote-pid = <3>; 885 886 slpi_smp2p_out: master-kernel { 887 qcom,entry-name = "master-kernel"; 888 #qcom,smem-state-cells = <1>; 889 }; 890 891 slpi_smp2p_in: slave-kernel { 892 qcom,entry-name = "slave-kernel"; 893 894 interrupt-controller; 895 #interrupt-cells = <2>; 896 }; 897 }; 898 899 soc: soc@0 { 900 #address-cells = <2>; 901 #size-cells = <2>; 902 ranges = <0 0 0 0 0x10 0>; 903 dma-ranges = <0 0 0 0 0x10 0>; 904 compatible = "simple-bus"; 905 906 gcc: clock-controller@100000 { 907 compatible = "qcom,gcc-sm8150"; 908 reg = <0x0 0x00100000 0x0 0x1f0000>; 909 #clock-cells = <1>; 910 #reset-cells = <1>; 911 #power-domain-cells = <1>; 912 clock-names = "bi_tcxo", 913 "sleep_clk"; 914 clocks = <&rpmhcc RPMH_CXO_CLK>, 915 <&sleep_clk>; 916 }; 917 918 gpi_dma0: dma-controller@800000 { 919 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 920 reg = <0 0x00800000 0 0x60000>; 921 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 922 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 923 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 934 dma-channels = <13>; 935 dma-channel-mask = <0xfa>; 936 iommus = <&apps_smmu 0x00d6 0x0>; 937 #dma-cells = <3>; 938 status = "disabled"; 939 }; 940 941 ethernet: ethernet@20000 { 942 compatible = "qcom,sm8150-ethqos"; 943 reg = <0x0 0x00020000 0x0 0x10000>, 944 <0x0 0x00036000 0x0 0x100>; 945 reg-names = "stmmaceth", "rgmii"; 946 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; 947 clocks = <&gcc GCC_EMAC_AXI_CLK>, 948 <&gcc GCC_EMAC_SLV_AHB_CLK>, 949 <&gcc GCC_EMAC_PTP_CLK>, 950 <&gcc GCC_EMAC_RGMII_CLK>; 951 interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; 953 interrupt-names = "macirq", "eth_lpi"; 954 955 power-domains = <&gcc EMAC_GDSC>; 956 resets = <&gcc GCC_EMAC_BCR>; 957 958 iommus = <&apps_smmu 0x3c0 0x0>; 959 960 snps,tso; 961 rx-fifo-depth = <4096>; 962 tx-fifo-depth = <4096>; 963 964 status = "disabled"; 965 }; 966 967 qfprom: efuse@784000 { 968 compatible = "qcom,sm8150-qfprom", "qcom,qfprom"; 969 reg = <0 0x00784000 0 0x8ff>; 970 #address-cells = <1>; 971 #size-cells = <1>; 972 973 gpu_speed_bin: gpu-speed-bin@133 { 974 reg = <0x133 0x1>; 975 bits = <5 3>; 976 }; 977 }; 978 979 qupv3_id_0: geniqup@8c0000 { 980 compatible = "qcom,geni-se-qup"; 981 reg = <0x0 0x008c0000 0x0 0x6000>; 982 clock-names = "m-ahb", "s-ahb"; 983 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 984 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 985 iommus = <&apps_smmu 0xc3 0x0>; 986 #address-cells = <2>; 987 #size-cells = <2>; 988 ranges; 989 status = "disabled"; 990 991 i2c0: i2c@880000 { 992 compatible = "qcom,geni-i2c"; 993 reg = <0 0x00880000 0 0x4000>; 994 clock-names = "se"; 995 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 996 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 997 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 998 dma-names = "tx", "rx"; 999 pinctrl-names = "default"; 1000 pinctrl-0 = <&qup_i2c0_default>; 1001 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1002 #address-cells = <1>; 1003 #size-cells = <0>; 1004 status = "disabled"; 1005 }; 1006 1007 spi0: spi@880000 { 1008 compatible = "qcom,geni-spi"; 1009 reg = <0 0x00880000 0 0x4000>; 1010 reg-names = "se"; 1011 clock-names = "se"; 1012 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1013 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1014 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1015 dma-names = "tx", "rx"; 1016 pinctrl-names = "default"; 1017 pinctrl-0 = <&qup_spi0_default>; 1018 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1019 spi-max-frequency = <50000000>; 1020 #address-cells = <1>; 1021 #size-cells = <0>; 1022 status = "disabled"; 1023 }; 1024 1025 i2c1: i2c@884000 { 1026 compatible = "qcom,geni-i2c"; 1027 reg = <0 0x00884000 0 0x4000>; 1028 clock-names = "se"; 1029 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1030 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1031 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1032 dma-names = "tx", "rx"; 1033 pinctrl-names = "default"; 1034 pinctrl-0 = <&qup_i2c1_default>; 1035 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1036 #address-cells = <1>; 1037 #size-cells = <0>; 1038 status = "disabled"; 1039 }; 1040 1041 spi1: spi@884000 { 1042 compatible = "qcom,geni-spi"; 1043 reg = <0 0x00884000 0 0x4000>; 1044 reg-names = "se"; 1045 clock-names = "se"; 1046 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1047 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1048 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1049 dma-names = "tx", "rx"; 1050 pinctrl-names = "default"; 1051 pinctrl-0 = <&qup_spi1_default>; 1052 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1053 spi-max-frequency = <50000000>; 1054 #address-cells = <1>; 1055 #size-cells = <0>; 1056 status = "disabled"; 1057 }; 1058 1059 i2c2: i2c@888000 { 1060 compatible = "qcom,geni-i2c"; 1061 reg = <0 0x00888000 0 0x4000>; 1062 clock-names = "se"; 1063 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1064 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1065 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1066 dma-names = "tx", "rx"; 1067 pinctrl-names = "default"; 1068 pinctrl-0 = <&qup_i2c2_default>; 1069 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1070 #address-cells = <1>; 1071 #size-cells = <0>; 1072 status = "disabled"; 1073 }; 1074 1075 spi2: spi@888000 { 1076 compatible = "qcom,geni-spi"; 1077 reg = <0 0x00888000 0 0x4000>; 1078 reg-names = "se"; 1079 clock-names = "se"; 1080 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1081 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1082 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1083 dma-names = "tx", "rx"; 1084 pinctrl-names = "default"; 1085 pinctrl-0 = <&qup_spi2_default>; 1086 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1087 spi-max-frequency = <50000000>; 1088 #address-cells = <1>; 1089 #size-cells = <0>; 1090 status = "disabled"; 1091 }; 1092 1093 i2c3: i2c@88c000 { 1094 compatible = "qcom,geni-i2c"; 1095 reg = <0 0x0088c000 0 0x4000>; 1096 clock-names = "se"; 1097 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1098 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1099 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1100 dma-names = "tx", "rx"; 1101 pinctrl-names = "default"; 1102 pinctrl-0 = <&qup_i2c3_default>; 1103 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1104 #address-cells = <1>; 1105 #size-cells = <0>; 1106 status = "disabled"; 1107 }; 1108 1109 spi3: spi@88c000 { 1110 compatible = "qcom,geni-spi"; 1111 reg = <0 0x0088c000 0 0x4000>; 1112 reg-names = "se"; 1113 clock-names = "se"; 1114 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1115 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1116 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1117 dma-names = "tx", "rx"; 1118 pinctrl-names = "default"; 1119 pinctrl-0 = <&qup_spi3_default>; 1120 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1121 spi-max-frequency = <50000000>; 1122 #address-cells = <1>; 1123 #size-cells = <0>; 1124 status = "disabled"; 1125 }; 1126 1127 i2c4: i2c@890000 { 1128 compatible = "qcom,geni-i2c"; 1129 reg = <0 0x00890000 0 0x4000>; 1130 clock-names = "se"; 1131 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1132 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1133 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1134 dma-names = "tx", "rx"; 1135 pinctrl-names = "default"; 1136 pinctrl-0 = <&qup_i2c4_default>; 1137 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1138 #address-cells = <1>; 1139 #size-cells = <0>; 1140 status = "disabled"; 1141 }; 1142 1143 spi4: spi@890000 { 1144 compatible = "qcom,geni-spi"; 1145 reg = <0 0x00890000 0 0x4000>; 1146 reg-names = "se"; 1147 clock-names = "se"; 1148 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1149 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1150 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1151 dma-names = "tx", "rx"; 1152 pinctrl-names = "default"; 1153 pinctrl-0 = <&qup_spi4_default>; 1154 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1155 spi-max-frequency = <50000000>; 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 status = "disabled"; 1159 }; 1160 1161 i2c5: i2c@894000 { 1162 compatible = "qcom,geni-i2c"; 1163 reg = <0 0x00894000 0 0x4000>; 1164 clock-names = "se"; 1165 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1166 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1167 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1168 dma-names = "tx", "rx"; 1169 pinctrl-names = "default"; 1170 pinctrl-0 = <&qup_i2c5_default>; 1171 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 status = "disabled"; 1175 }; 1176 1177 spi5: spi@894000 { 1178 compatible = "qcom,geni-spi"; 1179 reg = <0 0x00894000 0 0x4000>; 1180 reg-names = "se"; 1181 clock-names = "se"; 1182 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1183 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1184 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1185 dma-names = "tx", "rx"; 1186 pinctrl-names = "default"; 1187 pinctrl-0 = <&qup_spi5_default>; 1188 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1189 spi-max-frequency = <50000000>; 1190 #address-cells = <1>; 1191 #size-cells = <0>; 1192 status = "disabled"; 1193 }; 1194 1195 i2c6: i2c@898000 { 1196 compatible = "qcom,geni-i2c"; 1197 reg = <0 0x00898000 0 0x4000>; 1198 clock-names = "se"; 1199 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1200 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1201 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1202 dma-names = "tx", "rx"; 1203 pinctrl-names = "default"; 1204 pinctrl-0 = <&qup_i2c6_default>; 1205 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1206 #address-cells = <1>; 1207 #size-cells = <0>; 1208 status = "disabled"; 1209 }; 1210 1211 spi6: spi@898000 { 1212 compatible = "qcom,geni-spi"; 1213 reg = <0 0x00898000 0 0x4000>; 1214 reg-names = "se"; 1215 clock-names = "se"; 1216 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1217 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1218 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1219 dma-names = "tx", "rx"; 1220 pinctrl-names = "default"; 1221 pinctrl-0 = <&qup_spi6_default>; 1222 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1223 spi-max-frequency = <50000000>; 1224 #address-cells = <1>; 1225 #size-cells = <0>; 1226 status = "disabled"; 1227 }; 1228 1229 i2c7: i2c@89c000 { 1230 compatible = "qcom,geni-i2c"; 1231 reg = <0 0x0089c000 0 0x4000>; 1232 clock-names = "se"; 1233 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1234 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1235 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1236 dma-names = "tx", "rx"; 1237 pinctrl-names = "default"; 1238 pinctrl-0 = <&qup_i2c7_default>; 1239 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1240 #address-cells = <1>; 1241 #size-cells = <0>; 1242 status = "disabled"; 1243 }; 1244 1245 spi7: spi@89c000 { 1246 compatible = "qcom,geni-spi"; 1247 reg = <0 0x0089c000 0 0x4000>; 1248 reg-names = "se"; 1249 clock-names = "se"; 1250 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1251 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1252 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1253 dma-names = "tx", "rx"; 1254 pinctrl-names = "default"; 1255 pinctrl-0 = <&qup_spi7_default>; 1256 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1257 spi-max-frequency = <50000000>; 1258 #address-cells = <1>; 1259 #size-cells = <0>; 1260 status = "disabled"; 1261 }; 1262 }; 1263 1264 gpi_dma1: dma-controller@a00000 { 1265 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 1266 reg = <0 0x00a00000 0 0x60000>; 1267 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1275 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1276 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1277 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1278 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1279 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1280 dma-channels = <13>; 1281 dma-channel-mask = <0xfa>; 1282 iommus = <&apps_smmu 0x0616 0x0>; 1283 #dma-cells = <3>; 1284 status = "disabled"; 1285 }; 1286 1287 qupv3_id_1: geniqup@ac0000 { 1288 compatible = "qcom,geni-se-qup"; 1289 reg = <0x0 0x00ac0000 0x0 0x6000>; 1290 clock-names = "m-ahb", "s-ahb"; 1291 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1292 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1293 iommus = <&apps_smmu 0x603 0x0>; 1294 #address-cells = <2>; 1295 #size-cells = <2>; 1296 ranges; 1297 status = "disabled"; 1298 1299 i2c8: i2c@a80000 { 1300 compatible = "qcom,geni-i2c"; 1301 reg = <0 0x00a80000 0 0x4000>; 1302 clock-names = "se"; 1303 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1304 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1305 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1306 dma-names = "tx", "rx"; 1307 pinctrl-names = "default"; 1308 pinctrl-0 = <&qup_i2c8_default>; 1309 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1310 #address-cells = <1>; 1311 #size-cells = <0>; 1312 status = "disabled"; 1313 }; 1314 1315 spi8: spi@a80000 { 1316 compatible = "qcom,geni-spi"; 1317 reg = <0 0x00a80000 0 0x4000>; 1318 reg-names = "se"; 1319 clock-names = "se"; 1320 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1321 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1322 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1323 dma-names = "tx", "rx"; 1324 pinctrl-names = "default"; 1325 pinctrl-0 = <&qup_spi8_default>; 1326 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1327 spi-max-frequency = <50000000>; 1328 #address-cells = <1>; 1329 #size-cells = <0>; 1330 status = "disabled"; 1331 }; 1332 1333 i2c9: i2c@a84000 { 1334 compatible = "qcom,geni-i2c"; 1335 reg = <0 0x00a84000 0 0x4000>; 1336 clock-names = "se"; 1337 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1338 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1339 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1340 dma-names = "tx", "rx"; 1341 pinctrl-names = "default"; 1342 pinctrl-0 = <&qup_i2c9_default>; 1343 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1344 #address-cells = <1>; 1345 #size-cells = <0>; 1346 status = "disabled"; 1347 }; 1348 1349 spi9: spi@a84000 { 1350 compatible = "qcom,geni-spi"; 1351 reg = <0 0x00a84000 0 0x4000>; 1352 reg-names = "se"; 1353 clock-names = "se"; 1354 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1355 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1356 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1357 dma-names = "tx", "rx"; 1358 pinctrl-names = "default"; 1359 pinctrl-0 = <&qup_spi9_default>; 1360 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1361 spi-max-frequency = <50000000>; 1362 #address-cells = <1>; 1363 #size-cells = <0>; 1364 status = "disabled"; 1365 }; 1366 1367 uart9: serial@a84000 { 1368 compatible = "qcom,geni-uart"; 1369 reg = <0x0 0x00a84000 0x0 0x4000>; 1370 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1371 clock-names = "se"; 1372 pinctrl-0 = <&qup_uart9_default>; 1373 pinctrl-names = "default"; 1374 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1375 status = "disabled"; 1376 }; 1377 1378 i2c10: i2c@a88000 { 1379 compatible = "qcom,geni-i2c"; 1380 reg = <0 0x00a88000 0 0x4000>; 1381 clock-names = "se"; 1382 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1383 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1384 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1385 dma-names = "tx", "rx"; 1386 pinctrl-names = "default"; 1387 pinctrl-0 = <&qup_i2c10_default>; 1388 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1389 #address-cells = <1>; 1390 #size-cells = <0>; 1391 status = "disabled"; 1392 }; 1393 1394 spi10: spi@a88000 { 1395 compatible = "qcom,geni-spi"; 1396 reg = <0 0x00a88000 0 0x4000>; 1397 reg-names = "se"; 1398 clock-names = "se"; 1399 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1400 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1401 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1402 dma-names = "tx", "rx"; 1403 pinctrl-names = "default"; 1404 pinctrl-0 = <&qup_spi10_default>; 1405 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1406 spi-max-frequency = <50000000>; 1407 #address-cells = <1>; 1408 #size-cells = <0>; 1409 status = "disabled"; 1410 }; 1411 1412 i2c11: i2c@a8c000 { 1413 compatible = "qcom,geni-i2c"; 1414 reg = <0 0x00a8c000 0 0x4000>; 1415 clock-names = "se"; 1416 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1417 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1418 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1419 dma-names = "tx", "rx"; 1420 pinctrl-names = "default"; 1421 pinctrl-0 = <&qup_i2c11_default>; 1422 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1423 #address-cells = <1>; 1424 #size-cells = <0>; 1425 status = "disabled"; 1426 }; 1427 1428 spi11: spi@a8c000 { 1429 compatible = "qcom,geni-spi"; 1430 reg = <0 0x00a8c000 0 0x4000>; 1431 reg-names = "se"; 1432 clock-names = "se"; 1433 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1434 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1435 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1436 dma-names = "tx", "rx"; 1437 pinctrl-names = "default"; 1438 pinctrl-0 = <&qup_spi11_default>; 1439 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1440 spi-max-frequency = <50000000>; 1441 #address-cells = <1>; 1442 #size-cells = <0>; 1443 status = "disabled"; 1444 }; 1445 1446 uart2: serial@a90000 { 1447 compatible = "qcom,geni-debug-uart"; 1448 reg = <0x0 0x00a90000 0x0 0x4000>; 1449 clock-names = "se"; 1450 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1451 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1452 status = "disabled"; 1453 }; 1454 1455 i2c12: i2c@a90000 { 1456 compatible = "qcom,geni-i2c"; 1457 reg = <0 0x00a90000 0 0x4000>; 1458 clock-names = "se"; 1459 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1460 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1461 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1462 dma-names = "tx", "rx"; 1463 pinctrl-names = "default"; 1464 pinctrl-0 = <&qup_i2c12_default>; 1465 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1466 #address-cells = <1>; 1467 #size-cells = <0>; 1468 status = "disabled"; 1469 }; 1470 1471 spi12: spi@a90000 { 1472 compatible = "qcom,geni-spi"; 1473 reg = <0 0x00a90000 0 0x4000>; 1474 reg-names = "se"; 1475 clock-names = "se"; 1476 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1477 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1478 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1479 dma-names = "tx", "rx"; 1480 pinctrl-names = "default"; 1481 pinctrl-0 = <&qup_spi12_default>; 1482 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1483 spi-max-frequency = <50000000>; 1484 #address-cells = <1>; 1485 #size-cells = <0>; 1486 status = "disabled"; 1487 }; 1488 1489 i2c16: i2c@94000 { 1490 compatible = "qcom,geni-i2c"; 1491 reg = <0 0x00094000 0 0x4000>; 1492 clock-names = "se"; 1493 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1494 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1495 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1496 dma-names = "tx", "rx"; 1497 pinctrl-names = "default"; 1498 pinctrl-0 = <&qup_i2c16_default>; 1499 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1500 #address-cells = <1>; 1501 #size-cells = <0>; 1502 status = "disabled"; 1503 }; 1504 1505 spi16: spi@a94000 { 1506 compatible = "qcom,geni-spi"; 1507 reg = <0 0x00a94000 0 0x4000>; 1508 reg-names = "se"; 1509 clock-names = "se"; 1510 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1511 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1512 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1513 dma-names = "tx", "rx"; 1514 pinctrl-names = "default"; 1515 pinctrl-0 = <&qup_spi16_default>; 1516 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1517 spi-max-frequency = <50000000>; 1518 #address-cells = <1>; 1519 #size-cells = <0>; 1520 status = "disabled"; 1521 }; 1522 }; 1523 1524 gpi_dma2: dma-controller@c00000 { 1525 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 1526 reg = <0 0x00c00000 0 0x60000>; 1527 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; 1540 dma-channels = <13>; 1541 dma-channel-mask = <0xfa>; 1542 iommus = <&apps_smmu 0x07b6 0x0>; 1543 #dma-cells = <3>; 1544 status = "disabled"; 1545 }; 1546 1547 qupv3_id_2: geniqup@cc0000 { 1548 compatible = "qcom,geni-se-qup"; 1549 reg = <0x0 0x00cc0000 0x0 0x6000>; 1550 1551 clock-names = "m-ahb", "s-ahb"; 1552 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1553 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1554 iommus = <&apps_smmu 0x7a3 0x0>; 1555 #address-cells = <2>; 1556 #size-cells = <2>; 1557 ranges; 1558 status = "disabled"; 1559 1560 i2c17: i2c@c80000 { 1561 compatible = "qcom,geni-i2c"; 1562 reg = <0 0x00c80000 0 0x4000>; 1563 clock-names = "se"; 1564 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1565 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1566 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1567 dma-names = "tx", "rx"; 1568 pinctrl-names = "default"; 1569 pinctrl-0 = <&qup_i2c17_default>; 1570 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1571 #address-cells = <1>; 1572 #size-cells = <0>; 1573 status = "disabled"; 1574 }; 1575 1576 spi17: spi@c80000 { 1577 compatible = "qcom,geni-spi"; 1578 reg = <0 0x00c80000 0 0x4000>; 1579 reg-names = "se"; 1580 clock-names = "se"; 1581 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1582 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1583 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1584 dma-names = "tx", "rx"; 1585 pinctrl-names = "default"; 1586 pinctrl-0 = <&qup_spi17_default>; 1587 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1588 spi-max-frequency = <50000000>; 1589 #address-cells = <1>; 1590 #size-cells = <0>; 1591 status = "disabled"; 1592 }; 1593 1594 i2c18: i2c@c84000 { 1595 compatible = "qcom,geni-i2c"; 1596 reg = <0 0x00c84000 0 0x4000>; 1597 clock-names = "se"; 1598 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1599 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1600 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1601 dma-names = "tx", "rx"; 1602 pinctrl-names = "default"; 1603 pinctrl-0 = <&qup_i2c18_default>; 1604 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1605 #address-cells = <1>; 1606 #size-cells = <0>; 1607 status = "disabled"; 1608 }; 1609 1610 spi18: spi@c84000 { 1611 compatible = "qcom,geni-spi"; 1612 reg = <0 0x00c84000 0 0x4000>; 1613 reg-names = "se"; 1614 clock-names = "se"; 1615 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1616 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1617 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1618 dma-names = "tx", "rx"; 1619 pinctrl-names = "default"; 1620 pinctrl-0 = <&qup_spi18_default>; 1621 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1622 spi-max-frequency = <50000000>; 1623 #address-cells = <1>; 1624 #size-cells = <0>; 1625 status = "disabled"; 1626 }; 1627 1628 i2c19: i2c@c88000 { 1629 compatible = "qcom,geni-i2c"; 1630 reg = <0 0x00c88000 0 0x4000>; 1631 clock-names = "se"; 1632 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1633 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1634 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1635 dma-names = "tx", "rx"; 1636 pinctrl-names = "default"; 1637 pinctrl-0 = <&qup_i2c19_default>; 1638 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1639 #address-cells = <1>; 1640 #size-cells = <0>; 1641 status = "disabled"; 1642 }; 1643 1644 spi19: spi@c88000 { 1645 compatible = "qcom,geni-spi"; 1646 reg = <0 0x00c88000 0 0x4000>; 1647 reg-names = "se"; 1648 clock-names = "se"; 1649 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1650 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1651 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1652 dma-names = "tx", "rx"; 1653 pinctrl-names = "default"; 1654 pinctrl-0 = <&qup_spi19_default>; 1655 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1656 spi-max-frequency = <50000000>; 1657 #address-cells = <1>; 1658 #size-cells = <0>; 1659 status = "disabled"; 1660 }; 1661 1662 i2c13: i2c@c8c000 { 1663 compatible = "qcom,geni-i2c"; 1664 reg = <0 0x00c8c000 0 0x4000>; 1665 clock-names = "se"; 1666 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1667 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1668 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1669 dma-names = "tx", "rx"; 1670 pinctrl-names = "default"; 1671 pinctrl-0 = <&qup_i2c13_default>; 1672 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1673 #address-cells = <1>; 1674 #size-cells = <0>; 1675 status = "disabled"; 1676 }; 1677 1678 spi13: spi@c8c000 { 1679 compatible = "qcom,geni-spi"; 1680 reg = <0 0x00c8c000 0 0x4000>; 1681 reg-names = "se"; 1682 clock-names = "se"; 1683 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1684 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1685 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1686 dma-names = "tx", "rx"; 1687 pinctrl-names = "default"; 1688 pinctrl-0 = <&qup_spi13_default>; 1689 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1690 spi-max-frequency = <50000000>; 1691 #address-cells = <1>; 1692 #size-cells = <0>; 1693 status = "disabled"; 1694 }; 1695 1696 uart13: serial@c8c000 { 1697 compatible = "qcom,geni-uart"; 1698 reg = <0 0x00c8c000 0 0x4000>; 1699 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1700 clock-names = "se"; 1701 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1702 status = "disabled"; 1703 }; 1704 1705 i2c14: i2c@c90000 { 1706 compatible = "qcom,geni-i2c"; 1707 reg = <0 0x00c90000 0 0x4000>; 1708 clock-names = "se"; 1709 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1710 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1711 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1712 dma-names = "tx", "rx"; 1713 pinctrl-names = "default"; 1714 pinctrl-0 = <&qup_i2c14_default>; 1715 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1716 #address-cells = <1>; 1717 #size-cells = <0>; 1718 status = "disabled"; 1719 }; 1720 1721 spi14: spi@c90000 { 1722 compatible = "qcom,geni-spi"; 1723 reg = <0 0x00c90000 0 0x4000>; 1724 reg-names = "se"; 1725 clock-names = "se"; 1726 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1727 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1728 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1729 dma-names = "tx", "rx"; 1730 pinctrl-names = "default"; 1731 pinctrl-0 = <&qup_spi14_default>; 1732 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1733 spi-max-frequency = <50000000>; 1734 #address-cells = <1>; 1735 #size-cells = <0>; 1736 status = "disabled"; 1737 }; 1738 1739 i2c15: i2c@c94000 { 1740 compatible = "qcom,geni-i2c"; 1741 reg = <0 0x00c94000 0 0x4000>; 1742 clock-names = "se"; 1743 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1744 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1745 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1746 dma-names = "tx", "rx"; 1747 pinctrl-names = "default"; 1748 pinctrl-0 = <&qup_i2c15_default>; 1749 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1750 #address-cells = <1>; 1751 #size-cells = <0>; 1752 status = "disabled"; 1753 }; 1754 1755 spi15: spi@c94000 { 1756 compatible = "qcom,geni-spi"; 1757 reg = <0 0x00c94000 0 0x4000>; 1758 reg-names = "se"; 1759 clock-names = "se"; 1760 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1761 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1762 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1763 dma-names = "tx", "rx"; 1764 pinctrl-names = "default"; 1765 pinctrl-0 = <&qup_spi15_default>; 1766 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1767 spi-max-frequency = <50000000>; 1768 #address-cells = <1>; 1769 #size-cells = <0>; 1770 status = "disabled"; 1771 }; 1772 }; 1773 1774 config_noc: interconnect@1500000 { 1775 compatible = "qcom,sm8150-config-noc"; 1776 reg = <0 0x01500000 0 0x7400>; 1777 #interconnect-cells = <2>; 1778 qcom,bcm-voters = <&apps_bcm_voter>; 1779 }; 1780 1781 system_noc: interconnect@1620000 { 1782 compatible = "qcom,sm8150-system-noc"; 1783 reg = <0 0x01620000 0 0x19400>; 1784 #interconnect-cells = <2>; 1785 qcom,bcm-voters = <&apps_bcm_voter>; 1786 }; 1787 1788 mc_virt: interconnect@163a000 { 1789 compatible = "qcom,sm8150-mc-virt"; 1790 reg = <0 0x0163a000 0 0x1000>; 1791 #interconnect-cells = <2>; 1792 qcom,bcm-voters = <&apps_bcm_voter>; 1793 }; 1794 1795 aggre1_noc: interconnect@16e0000 { 1796 compatible = "qcom,sm8150-aggre1-noc"; 1797 reg = <0 0x016e0000 0 0xd080>; 1798 #interconnect-cells = <2>; 1799 qcom,bcm-voters = <&apps_bcm_voter>; 1800 }; 1801 1802 aggre2_noc: interconnect@1700000 { 1803 compatible = "qcom,sm8150-aggre2-noc"; 1804 reg = <0 0x01700000 0 0x20000>; 1805 #interconnect-cells = <2>; 1806 qcom,bcm-voters = <&apps_bcm_voter>; 1807 }; 1808 1809 compute_noc: interconnect@1720000 { 1810 compatible = "qcom,sm8150-compute-noc"; 1811 reg = <0 0x01720000 0 0x7000>; 1812 #interconnect-cells = <2>; 1813 qcom,bcm-voters = <&apps_bcm_voter>; 1814 }; 1815 1816 mmss_noc: interconnect@1740000 { 1817 compatible = "qcom,sm8150-mmss-noc"; 1818 reg = <0 0x01740000 0 0x1c100>; 1819 #interconnect-cells = <2>; 1820 qcom,bcm-voters = <&apps_bcm_voter>; 1821 }; 1822 1823 system-cache-controller@9200000 { 1824 compatible = "qcom,sm8150-llcc"; 1825 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, 1826 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, 1827 <0 0x09600000 0 0x50000>; 1828 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 1829 "llcc3_base", "llcc_broadcast_base"; 1830 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1831 }; 1832 1833 dma@10a2000 { 1834 compatible = "qcom,sm8150-dcc", "qcom,dcc"; 1835 reg = <0x0 0x010a2000 0x0 0x1000>, 1836 <0x0 0x010ad000 0x0 0x3000>; 1837 }; 1838 1839 pcie0: pcie@1c00000 { 1840 compatible = "qcom,pcie-sm8150"; 1841 reg = <0 0x01c00000 0 0x3000>, 1842 <0 0x60000000 0 0xf1d>, 1843 <0 0x60000f20 0 0xa8>, 1844 <0 0x60001000 0 0x1000>, 1845 <0 0x60100000 0 0x100000>; 1846 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1847 device_type = "pci"; 1848 linux,pci-domain = <0>; 1849 bus-range = <0x00 0xff>; 1850 num-lanes = <1>; 1851 1852 #address-cells = <3>; 1853 #size-cells = <2>; 1854 1855 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1856 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1857 1858 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1864 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1865 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1866 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1867 interrupt-names = "msi0", 1868 "msi1", 1869 "msi2", 1870 "msi3", 1871 "msi4", 1872 "msi5", 1873 "msi6", 1874 "msi7", 1875 "global"; 1876 #interrupt-cells = <1>; 1877 interrupt-map-mask = <0 0 0 0x7>; 1878 interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1879 <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1880 <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1881 <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1882 1883 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1884 <&gcc GCC_PCIE_0_AUX_CLK>, 1885 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1886 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1887 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1888 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 1889 clock-names = "pipe", 1890 "aux", 1891 "cfg", 1892 "bus_master", 1893 "bus_slave", 1894 "slave_q2a"; 1895 1896 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, 1897 <0x100 &apps_smmu 0x1d81 0x1>; 1898 1899 resets = <&gcc GCC_PCIE_0_BCR>; 1900 reset-names = "pci"; 1901 1902 power-domains = <&gcc PCIE_0_GDSC>; 1903 1904 phys = <&pcie0_phy>; 1905 phy-names = "pciephy"; 1906 1907 perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>; 1908 wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; 1909 1910 pinctrl-names = "default"; 1911 pinctrl-0 = <&pcie0_default_state>; 1912 1913 status = "disabled"; 1914 1915 pcie@0 { 1916 device_type = "pci"; 1917 reg = <0x0 0x0 0x0 0x0 0x0>; 1918 bus-range = <0x01 0xff>; 1919 1920 #address-cells = <3>; 1921 #size-cells = <2>; 1922 ranges; 1923 }; 1924 }; 1925 1926 pcie0_phy: phy@1c06000 { 1927 compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy"; 1928 reg = <0 0x01c06000 0 0x1000>; 1929 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1930 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1931 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1932 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, 1933 <&gcc GCC_PCIE_0_PIPE_CLK>; 1934 clock-names = "aux", 1935 "cfg_ahb", 1936 "ref", 1937 "refgen", 1938 "pipe"; 1939 1940 clock-output-names = "pcie_0_pipe_clk"; 1941 #clock-cells = <0>; 1942 1943 #phy-cells = <0>; 1944 1945 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1946 reset-names = "phy"; 1947 1948 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1949 assigned-clock-rates = <100000000>; 1950 1951 status = "disabled"; 1952 }; 1953 1954 pcie1: pcie@1c08000 { 1955 compatible = "qcom,pcie-sm8150"; 1956 reg = <0 0x01c08000 0 0x3000>, 1957 <0 0x40000000 0 0xf1d>, 1958 <0 0x40000f20 0 0xa8>, 1959 <0 0x40001000 0 0x1000>, 1960 <0 0x40100000 0 0x100000>; 1961 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1962 device_type = "pci"; 1963 linux,pci-domain = <1>; 1964 bus-range = <0x00 0xff>; 1965 num-lanes = <2>; 1966 1967 #address-cells = <3>; 1968 #size-cells = <2>; 1969 1970 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1971 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1972 1973 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1974 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1975 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1976 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1977 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1978 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1979 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 1980 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 1981 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 1982 interrupt-names = "msi0", 1983 "msi1", 1984 "msi2", 1985 "msi3", 1986 "msi4", 1987 "msi5", 1988 "msi6", 1989 "msi7", 1990 "global"; 1991 #interrupt-cells = <1>; 1992 interrupt-map-mask = <0 0 0 0x7>; 1993 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1994 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1995 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1996 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1997 1998 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1999 <&gcc GCC_PCIE_1_AUX_CLK>, 2000 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2001 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2002 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2003 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 2004 clock-names = "pipe", 2005 "aux", 2006 "cfg", 2007 "bus_master", 2008 "bus_slave", 2009 "slave_q2a"; 2010 2011 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2012 assigned-clock-rates = <19200000>; 2013 2014 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 2015 <0x100 &apps_smmu 0x1e01 0x1>; 2016 2017 resets = <&gcc GCC_PCIE_1_BCR>; 2018 reset-names = "pci"; 2019 2020 power-domains = <&gcc PCIE_1_GDSC>; 2021 2022 phys = <&pcie1_phy>; 2023 phy-names = "pciephy"; 2024 2025 perst-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; 2026 enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>; 2027 2028 pinctrl-names = "default"; 2029 pinctrl-0 = <&pcie1_default_state>; 2030 2031 status = "disabled"; 2032 2033 pcie@0 { 2034 device_type = "pci"; 2035 reg = <0x0 0x0 0x0 0x0 0x0>; 2036 bus-range = <0x01 0xff>; 2037 2038 #address-cells = <3>; 2039 #size-cells = <2>; 2040 ranges; 2041 }; 2042 }; 2043 2044 pcie1_phy: phy@1c0e000 { 2045 compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy"; 2046 reg = <0 0x01c0e000 0 0x1000>; 2047 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2048 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2049 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2050 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, 2051 <&gcc GCC_PCIE_1_PIPE_CLK>; 2052 clock-names = "aux", 2053 "cfg_ahb", 2054 "ref", 2055 "refgen", 2056 "pipe"; 2057 2058 clock-output-names = "pcie_1_pipe_clk"; 2059 #clock-cells = <0>; 2060 2061 #phy-cells = <0>; 2062 2063 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2064 reset-names = "phy"; 2065 2066 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2067 assigned-clock-rates = <100000000>; 2068 2069 status = "disabled"; 2070 }; 2071 2072 ufs_mem_hc: ufshc@1d84000 { 2073 compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 2074 "jedec,ufs-2.0"; 2075 reg = <0 0x01d84000 0 0x2500>, 2076 <0 0x01d90000 0 0x8000>; 2077 reg-names = "std", "ice"; 2078 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2079 phys = <&ufs_mem_phy>; 2080 phy-names = "ufsphy"; 2081 lanes-per-direction = <2>; 2082 #reset-cells = <1>; 2083 resets = <&gcc GCC_UFS_PHY_BCR>; 2084 reset-names = "rst"; 2085 2086 iommus = <&apps_smmu 0x300 0>; 2087 2088 clock-names = 2089 "core_clk", 2090 "bus_aggr_clk", 2091 "iface_clk", 2092 "core_clk_unipro", 2093 "ref_clk", 2094 "tx_lane0_sync_clk", 2095 "rx_lane0_sync_clk", 2096 "rx_lane1_sync_clk", 2097 "ice_core_clk"; 2098 clocks = 2099 <&gcc GCC_UFS_PHY_AXI_CLK>, 2100 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2101 <&gcc GCC_UFS_PHY_AHB_CLK>, 2102 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2103 <&rpmhcc RPMH_CXO_CLK>, 2104 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2105 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2106 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 2107 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2108 freq-table-hz = 2109 <37500000 300000000>, 2110 <0 0>, 2111 <0 0>, 2112 <37500000 300000000>, 2113 <0 0>, 2114 <0 0>, 2115 <0 0>, 2116 <0 0>, 2117 <0 300000000>; 2118 2119 status = "disabled"; 2120 }; 2121 2122 ufs_mem_phy: phy@1d87000 { 2123 compatible = "qcom,sm8150-qmp-ufs-phy"; 2124 reg = <0 0x01d87000 0 0x1000>; 2125 2126 clocks = <&rpmhcc RPMH_CXO_CLK>, 2127 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2128 <&gcc GCC_UFS_MEM_CLKREF_CLK>; 2129 clock-names = "ref", 2130 "ref_aux", 2131 "qref"; 2132 2133 power-domains = <&gcc UFS_PHY_GDSC>; 2134 2135 resets = <&ufs_mem_hc 0>; 2136 reset-names = "ufsphy"; 2137 2138 #phy-cells = <0>; 2139 2140 status = "disabled"; 2141 }; 2142 2143 cryptobam: dma-controller@1dc4000 { 2144 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2145 reg = <0 0x01dc4000 0 0x24000>; 2146 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2147 #dma-cells = <1>; 2148 qcom,ee = <0>; 2149 qcom,controlled-remotely; 2150 num-channels = <8>; 2151 qcom,num-ees = <2>; 2152 iommus = <&apps_smmu 0x502 0x0641>, 2153 <&apps_smmu 0x504 0x0011>, 2154 <&apps_smmu 0x506 0x0011>, 2155 <&apps_smmu 0x508 0x0011>, 2156 <&apps_smmu 0x512 0x0000>; 2157 }; 2158 2159 crypto: crypto@1dfa000 { 2160 compatible = "qcom,sm8150-qce", "qcom,qce"; 2161 reg = <0 0x01dfa000 0 0x6000>; 2162 dmas = <&cryptobam 4>, <&cryptobam 5>; 2163 dma-names = "rx", "tx"; 2164 iommus = <&apps_smmu 0x502 0x0641>, 2165 <&apps_smmu 0x504 0x0011>, 2166 <&apps_smmu 0x506 0x0011>, 2167 <&apps_smmu 0x508 0x0011>, 2168 <&apps_smmu 0x512 0x0000>; 2169 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>; 2170 interconnect-names = "memory"; 2171 }; 2172 2173 tcsr_mutex: hwlock@1f40000 { 2174 compatible = "qcom,tcsr-mutex"; 2175 reg = <0x0 0x01f40000 0x0 0x20000>; 2176 #hwlock-cells = <1>; 2177 }; 2178 2179 tcsr_regs_1: syscon@1f60000 { 2180 compatible = "qcom,sm8150-tcsr", "syscon"; 2181 reg = <0x0 0x01f60000 0x0 0x20000>; 2182 }; 2183 2184 remoteproc_slpi: remoteproc@2400000 { 2185 compatible = "qcom,sm8150-slpi-pas"; 2186 reg = <0x0 0x02400000 0x0 0x4040>; 2187 2188 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 2189 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2190 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2191 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2192 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2193 interrupt-names = "wdog", "fatal", "ready", 2194 "handover", "stop-ack"; 2195 2196 clocks = <&rpmhcc RPMH_CXO_CLK>; 2197 clock-names = "xo"; 2198 2199 power-domains = <&rpmhpd SM8150_LCX>, 2200 <&rpmhpd SM8150_LMX>; 2201 power-domain-names = "lcx", "lmx"; 2202 2203 memory-region = <&slpi_mem>; 2204 2205 qcom,qmp = <&aoss_qmp>; 2206 2207 qcom,smem-states = <&slpi_smp2p_out 0>; 2208 qcom,smem-state-names = "stop"; 2209 2210 status = "disabled"; 2211 2212 glink-edge { 2213 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 2214 label = "dsps"; 2215 qcom,remote-pid = <3>; 2216 mboxes = <&apss_shared 24>; 2217 2218 fastrpc { 2219 compatible = "qcom,fastrpc"; 2220 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2221 label = "sdsp"; 2222 qcom,non-secure-domain; 2223 #address-cells = <1>; 2224 #size-cells = <0>; 2225 2226 compute-cb@1 { 2227 compatible = "qcom,fastrpc-compute-cb"; 2228 reg = <1>; 2229 iommus = <&apps_smmu 0x05a1 0x0>; 2230 }; 2231 2232 compute-cb@2 { 2233 compatible = "qcom,fastrpc-compute-cb"; 2234 reg = <2>; 2235 iommus = <&apps_smmu 0x05a2 0x0>; 2236 }; 2237 2238 compute-cb@3 { 2239 compatible = "qcom,fastrpc-compute-cb"; 2240 reg = <3>; 2241 iommus = <&apps_smmu 0x05a3 0x0>; 2242 /* note: shared-cb = <4> in downstream */ 2243 }; 2244 }; 2245 }; 2246 }; 2247 2248 gpu: gpu@2c00000 { 2249 compatible = "qcom,adreno-640.1", "qcom,adreno"; 2250 reg = <0 0x02c00000 0 0x40000>; 2251 reg-names = "kgsl_3d0_reg_memory"; 2252 2253 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2254 2255 iommus = <&adreno_smmu 0 0x401>; 2256 2257 operating-points-v2 = <&gpu_opp_table>; 2258 2259 qcom,gmu = <&gmu>; 2260 2261 nvmem-cells = <&gpu_speed_bin>; 2262 nvmem-cell-names = "speed_bin"; 2263 #cooling-cells = <2>; 2264 2265 status = "disabled"; 2266 2267 gpu_zap_shader: zap-shader { 2268 memory-region = <&gpu_mem>; 2269 }; 2270 2271 gpu_opp_table: opp-table { 2272 compatible = "operating-points-v2"; 2273 2274 opp-675000000 { 2275 opp-hz = /bits/ 64 <675000000>; 2276 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2277 opp-supported-hw = <0x2>; 2278 }; 2279 2280 opp-585000000 { 2281 opp-hz = /bits/ 64 <585000000>; 2282 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2283 opp-supported-hw = <0x3>; 2284 }; 2285 2286 opp-499200000 { 2287 opp-hz = /bits/ 64 <499200000>; 2288 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2289 opp-supported-hw = <0x3>; 2290 }; 2291 2292 opp-427000000 { 2293 opp-hz = /bits/ 64 <427000000>; 2294 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2295 opp-supported-hw = <0x3>; 2296 }; 2297 2298 opp-345000000 { 2299 opp-hz = /bits/ 64 <345000000>; 2300 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2301 opp-supported-hw = <0x3>; 2302 }; 2303 2304 opp-257000000 { 2305 opp-hz = /bits/ 64 <257000000>; 2306 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2307 opp-supported-hw = <0x3>; 2308 }; 2309 }; 2310 }; 2311 2312 gmu: gmu@2c6a000 { 2313 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 2314 2315 reg = <0 0x02c6a000 0 0x30000>, 2316 <0 0x0b290000 0 0x10000>, 2317 <0 0x0b490000 0 0x10000>; 2318 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2319 2320 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2321 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2322 interrupt-names = "hfi", "gmu"; 2323 2324 clocks = <&gpucc GPU_CC_AHB_CLK>, 2325 <&gpucc GPU_CC_CX_GMU_CLK>, 2326 <&gpucc GPU_CC_CXO_CLK>, 2327 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2328 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2329 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2330 2331 power-domains = <&gpucc GPU_CX_GDSC>, 2332 <&gpucc GPU_GX_GDSC>; 2333 power-domain-names = "cx", "gx"; 2334 2335 iommus = <&adreno_smmu 5 0x400>; 2336 2337 operating-points-v2 = <&gmu_opp_table>; 2338 2339 status = "disabled"; 2340 2341 gmu_opp_table: opp-table { 2342 compatible = "operating-points-v2"; 2343 2344 opp-200000000 { 2345 opp-hz = /bits/ 64 <200000000>; 2346 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2347 }; 2348 }; 2349 }; 2350 2351 gpucc: clock-controller@2c90000 { 2352 compatible = "qcom,sm8150-gpucc"; 2353 reg = <0 0x02c90000 0 0x9000>; 2354 clocks = <&rpmhcc RPMH_CXO_CLK>, 2355 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2356 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2357 clock-names = "bi_tcxo", 2358 "gcc_gpu_gpll0_clk_src", 2359 "gcc_gpu_gpll0_div_clk_src"; 2360 #clock-cells = <1>; 2361 #reset-cells = <1>; 2362 #power-domain-cells = <1>; 2363 }; 2364 2365 adreno_smmu: iommu@2ca0000 { 2366 compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu", 2367 "qcom,smmu-500", "arm,mmu-500"; 2368 reg = <0 0x02ca0000 0 0x10000>; 2369 #iommu-cells = <2>; 2370 #global-interrupts = <1>; 2371 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 2372 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2373 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2374 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2375 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2376 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2377 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2378 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2379 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 2380 clocks = <&gpucc GPU_CC_AHB_CLK>, 2381 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2382 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2383 clock-names = "ahb", "bus", "iface"; 2384 2385 power-domains = <&gpucc GPU_CX_GDSC>; 2386 }; 2387 2388 tlmm: pinctrl@3100000 { 2389 compatible = "qcom,sm8150-pinctrl"; 2390 reg = <0x0 0x03100000 0x0 0x300000>, 2391 <0x0 0x03500000 0x0 0x300000>, 2392 <0x0 0x03900000 0x0 0x300000>, 2393 <0x0 0x03d00000 0x0 0x300000>; 2394 reg-names = "west", "east", "north", "south"; 2395 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2396 gpio-ranges = <&tlmm 0 0 176>; 2397 gpio-controller; 2398 #gpio-cells = <2>; 2399 interrupt-controller; 2400 #interrupt-cells = <2>; 2401 wakeup-parent = <&pdc>; 2402 2403 qup_i2c0_default: qup-i2c0-default-state { 2404 pins = "gpio0", "gpio1"; 2405 function = "qup0"; 2406 drive-strength = <0x02>; 2407 bias-disable; 2408 }; 2409 2410 qup_spi0_default: qup-spi0-default-state { 2411 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 2412 function = "qup0"; 2413 drive-strength = <6>; 2414 bias-disable; 2415 }; 2416 2417 qup_i2c1_default: qup-i2c1-default-state { 2418 pins = "gpio114", "gpio115"; 2419 function = "qup1"; 2420 drive-strength = <2>; 2421 bias-disable; 2422 }; 2423 2424 qup_spi1_default: qup-spi1-default-state { 2425 pins = "gpio114", "gpio115", "gpio116", "gpio117"; 2426 function = "qup1"; 2427 drive-strength = <6>; 2428 bias-disable; 2429 }; 2430 2431 qup_i2c2_default: qup-i2c2-default-state { 2432 pins = "gpio126", "gpio127"; 2433 function = "qup2"; 2434 drive-strength = <2>; 2435 bias-disable; 2436 }; 2437 2438 qup_spi2_default: qup-spi2-default-state { 2439 pins = "gpio126", "gpio127", "gpio128", "gpio129"; 2440 function = "qup2"; 2441 drive-strength = <6>; 2442 bias-disable; 2443 }; 2444 2445 qup_i2c3_default: qup-i2c3-default-state { 2446 pins = "gpio144", "gpio145"; 2447 function = "qup3"; 2448 drive-strength = <2>; 2449 bias-disable; 2450 }; 2451 2452 qup_spi3_default: qup-spi3-default-state { 2453 pins = "gpio144", "gpio145", "gpio146", "gpio147"; 2454 function = "qup3"; 2455 drive-strength = <6>; 2456 bias-disable; 2457 }; 2458 2459 qup_i2c4_default: qup-i2c4-default-state { 2460 pins = "gpio51", "gpio52"; 2461 function = "qup4"; 2462 drive-strength = <2>; 2463 bias-disable; 2464 }; 2465 2466 qup_spi4_default: qup-spi4-default-state { 2467 pins = "gpio51", "gpio52", "gpio53", "gpio54"; 2468 function = "qup4"; 2469 drive-strength = <6>; 2470 bias-disable; 2471 }; 2472 2473 qup_i2c5_default: qup-i2c5-default-state { 2474 pins = "gpio121", "gpio122"; 2475 function = "qup5"; 2476 drive-strength = <2>; 2477 bias-disable; 2478 }; 2479 2480 qup_spi5_default: qup-spi5-default-state { 2481 pins = "gpio119", "gpio120", "gpio121", "gpio122"; 2482 function = "qup5"; 2483 drive-strength = <6>; 2484 bias-disable; 2485 }; 2486 2487 qup_i2c6_default: qup-i2c6-default-state { 2488 pins = "gpio6", "gpio7"; 2489 function = "qup6"; 2490 drive-strength = <2>; 2491 bias-disable; 2492 }; 2493 2494 qup_spi6_default: qup-spi6-default-state { 2495 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 2496 function = "qup6"; 2497 drive-strength = <6>; 2498 bias-disable; 2499 }; 2500 2501 qup_i2c7_default: qup-i2c7-default-state { 2502 pins = "gpio98", "gpio99"; 2503 function = "qup7"; 2504 drive-strength = <2>; 2505 bias-disable; 2506 }; 2507 2508 qup_spi7_default: qup-spi7-default-state { 2509 pins = "gpio98", "gpio99", "gpio100", "gpio101"; 2510 function = "qup7"; 2511 drive-strength = <6>; 2512 bias-disable; 2513 }; 2514 2515 qup_i2c8_default: qup-i2c8-default-state { 2516 pins = "gpio88", "gpio89"; 2517 function = "qup8"; 2518 drive-strength = <2>; 2519 bias-disable; 2520 }; 2521 2522 qup_spi8_default: qup-spi8-default-state { 2523 pins = "gpio88", "gpio89", "gpio90", "gpio91"; 2524 function = "qup8"; 2525 drive-strength = <6>; 2526 bias-disable; 2527 }; 2528 2529 qup_i2c9_default: qup-i2c9-default-state { 2530 pins = "gpio39", "gpio40"; 2531 function = "qup9"; 2532 drive-strength = <2>; 2533 bias-disable; 2534 }; 2535 2536 qup_spi9_default: qup-spi9-default-state { 2537 pins = "gpio39", "gpio40", "gpio41", "gpio42"; 2538 function = "qup9"; 2539 drive-strength = <6>; 2540 bias-disable; 2541 }; 2542 2543 qup_uart9_default: qup-uart9-default-state { 2544 pins = "gpio41", "gpio42"; 2545 function = "qup9"; 2546 drive-strength = <2>; 2547 bias-disable; 2548 }; 2549 2550 qup_i2c10_default: qup-i2c10-default-state { 2551 pins = "gpio9", "gpio10"; 2552 function = "qup10"; 2553 drive-strength = <2>; 2554 bias-disable; 2555 }; 2556 2557 qup_spi10_default: qup-spi10-default-state { 2558 pins = "gpio9", "gpio10", "gpio11", "gpio12"; 2559 function = "qup10"; 2560 drive-strength = <6>; 2561 bias-disable; 2562 }; 2563 2564 qup_i2c11_default: qup-i2c11-default-state { 2565 pins = "gpio94", "gpio95"; 2566 function = "qup11"; 2567 drive-strength = <2>; 2568 bias-disable; 2569 }; 2570 2571 qup_spi11_default: qup-spi11-default-state { 2572 pins = "gpio92", "gpio93", "gpio94", "gpio95"; 2573 function = "qup11"; 2574 drive-strength = <6>; 2575 bias-disable; 2576 }; 2577 2578 qup_i2c12_default: qup-i2c12-default-state { 2579 pins = "gpio83", "gpio84"; 2580 function = "qup12"; 2581 drive-strength = <2>; 2582 bias-disable; 2583 }; 2584 2585 qup_spi12_default: qup-spi12-default-state { 2586 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2587 function = "qup12"; 2588 drive-strength = <6>; 2589 bias-disable; 2590 }; 2591 2592 qup_i2c13_default: qup-i2c13-default-state { 2593 pins = "gpio43", "gpio44"; 2594 function = "qup13"; 2595 drive-strength = <2>; 2596 bias-disable; 2597 }; 2598 2599 qup_spi13_default: qup-spi13-default-state { 2600 pins = "gpio43", "gpio44", "gpio45", "gpio46"; 2601 function = "qup13"; 2602 drive-strength = <6>; 2603 bias-disable; 2604 }; 2605 2606 qup_i2c14_default: qup-i2c14-default-state { 2607 pins = "gpio47", "gpio48"; 2608 function = "qup14"; 2609 drive-strength = <2>; 2610 bias-disable; 2611 }; 2612 2613 qup_spi14_default: qup-spi14-default-state { 2614 pins = "gpio47", "gpio48", "gpio49", "gpio50"; 2615 function = "qup14"; 2616 drive-strength = <6>; 2617 bias-disable; 2618 }; 2619 2620 qup_i2c15_default: qup-i2c15-default-state { 2621 pins = "gpio27", "gpio28"; 2622 function = "qup15"; 2623 drive-strength = <2>; 2624 bias-disable; 2625 }; 2626 2627 qup_spi15_default: qup-spi15-default-state { 2628 pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2629 function = "qup15"; 2630 drive-strength = <6>; 2631 bias-disable; 2632 }; 2633 2634 qup_i2c16_default: qup-i2c16-default-state { 2635 pins = "gpio86", "gpio85"; 2636 function = "qup16"; 2637 drive-strength = <2>; 2638 bias-disable; 2639 }; 2640 2641 qup_spi16_default: qup-spi16-default-state { 2642 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2643 function = "qup16"; 2644 drive-strength = <6>; 2645 bias-disable; 2646 }; 2647 2648 qup_i2c17_default: qup-i2c17-default-state { 2649 pins = "gpio55", "gpio56"; 2650 function = "qup17"; 2651 drive-strength = <2>; 2652 bias-disable; 2653 }; 2654 2655 qup_spi17_default: qup-spi17-default-state { 2656 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2657 function = "qup17"; 2658 drive-strength = <6>; 2659 bias-disable; 2660 }; 2661 2662 qup_i2c18_default: qup-i2c18-default-state { 2663 pins = "gpio23", "gpio24"; 2664 function = "qup18"; 2665 drive-strength = <2>; 2666 bias-disable; 2667 }; 2668 2669 qup_spi18_default: qup-spi18-default-state { 2670 pins = "gpio23", "gpio24", "gpio25", "gpio26"; 2671 function = "qup18"; 2672 drive-strength = <6>; 2673 bias-disable; 2674 }; 2675 2676 qup_i2c19_default: qup-i2c19-default-state { 2677 pins = "gpio57", "gpio58"; 2678 function = "qup19"; 2679 drive-strength = <2>; 2680 bias-disable; 2681 }; 2682 2683 qup_spi19_default: qup-spi19-default-state { 2684 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2685 function = "qup19"; 2686 drive-strength = <6>; 2687 bias-disable; 2688 }; 2689 2690 pcie0_default_state: pcie0-default-state { 2691 perst-pins { 2692 pins = "gpio35"; 2693 function = "gpio"; 2694 drive-strength = <2>; 2695 bias-pull-down; 2696 }; 2697 2698 clkreq-pins { 2699 pins = "gpio36"; 2700 function = "pci_e0"; 2701 drive-strength = <2>; 2702 bias-pull-up; 2703 }; 2704 2705 wake-pins { 2706 pins = "gpio37"; 2707 function = "gpio"; 2708 drive-strength = <2>; 2709 bias-pull-up; 2710 }; 2711 }; 2712 2713 pcie1_default_state: pcie1-default-state { 2714 perst-pins { 2715 pins = "gpio102"; 2716 function = "gpio"; 2717 drive-strength = <2>; 2718 bias-pull-down; 2719 }; 2720 2721 clkreq-pins { 2722 pins = "gpio103"; 2723 function = "pci_e1"; 2724 drive-strength = <2>; 2725 bias-pull-up; 2726 }; 2727 2728 wake-pins { 2729 pins = "gpio104"; 2730 function = "gpio"; 2731 drive-strength = <2>; 2732 bias-pull-up; 2733 }; 2734 }; 2735 }; 2736 2737 remoteproc_mpss: remoteproc@4080000 { 2738 compatible = "qcom,sm8150-mpss-pas"; 2739 reg = <0x0 0x04080000 0x0 0x4040>; 2740 2741 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2742 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2743 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2744 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2745 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2746 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2747 interrupt-names = "wdog", "fatal", "ready", "handover", 2748 "stop-ack", "shutdown-ack"; 2749 2750 clocks = <&rpmhcc RPMH_CXO_CLK>; 2751 clock-names = "xo"; 2752 2753 power-domains = <&rpmhpd SM8150_CX>, 2754 <&rpmhpd SM8150_MSS>; 2755 power-domain-names = "cx", "mss"; 2756 2757 memory-region = <&mpss_mem>; 2758 2759 qcom,qmp = <&aoss_qmp>; 2760 2761 qcom,smem-states = <&modem_smp2p_out 0>; 2762 qcom,smem-state-names = "stop"; 2763 2764 status = "disabled"; 2765 2766 glink-edge { 2767 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2768 label = "modem"; 2769 qcom,remote-pid = <1>; 2770 mboxes = <&apss_shared 12>; 2771 }; 2772 }; 2773 2774 stm@6002000 { 2775 compatible = "arm,coresight-stm", "arm,primecell"; 2776 reg = <0 0x06002000 0 0x1000>, 2777 <0 0x16280000 0 0x180000>; 2778 reg-names = "stm-base", "stm-stimulus-base"; 2779 2780 clocks = <&aoss_qmp>; 2781 clock-names = "apb_pclk"; 2782 2783 out-ports { 2784 port { 2785 stm_out: endpoint { 2786 remote-endpoint = <&funnel0_in7>; 2787 }; 2788 }; 2789 }; 2790 }; 2791 2792 funnel@6041000 { 2793 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2794 reg = <0 0x06041000 0 0x1000>; 2795 2796 clocks = <&aoss_qmp>; 2797 clock-names = "apb_pclk"; 2798 2799 out-ports { 2800 port { 2801 funnel0_out: endpoint { 2802 remote-endpoint = <&merge_funnel_in0>; 2803 }; 2804 }; 2805 }; 2806 2807 in-ports { 2808 #address-cells = <1>; 2809 #size-cells = <0>; 2810 2811 port@7 { 2812 reg = <7>; 2813 funnel0_in7: endpoint { 2814 remote-endpoint = <&stm_out>; 2815 }; 2816 }; 2817 }; 2818 }; 2819 2820 funnel@6042000 { 2821 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2822 reg = <0 0x06042000 0 0x1000>; 2823 2824 clocks = <&aoss_qmp>; 2825 clock-names = "apb_pclk"; 2826 2827 out-ports { 2828 port { 2829 funnel1_out: endpoint { 2830 remote-endpoint = <&merge_funnel_in1>; 2831 }; 2832 }; 2833 }; 2834 2835 in-ports { 2836 #address-cells = <1>; 2837 #size-cells = <0>; 2838 2839 port@4 { 2840 reg = <4>; 2841 funnel1_in4: endpoint { 2842 remote-endpoint = <&swao_replicator_out>; 2843 }; 2844 }; 2845 }; 2846 }; 2847 2848 funnel@6043000 { 2849 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2850 reg = <0 0x06043000 0 0x1000>; 2851 2852 clocks = <&aoss_qmp>; 2853 clock-names = "apb_pclk"; 2854 2855 out-ports { 2856 port { 2857 funnel2_out: endpoint { 2858 remote-endpoint = <&merge_funnel_in2>; 2859 }; 2860 }; 2861 }; 2862 2863 in-ports { 2864 #address-cells = <1>; 2865 #size-cells = <0>; 2866 2867 port@2 { 2868 reg = <2>; 2869 funnel2_in2: endpoint { 2870 remote-endpoint = <&apss_merge_funnel_out>; 2871 }; 2872 }; 2873 }; 2874 }; 2875 2876 funnel@6045000 { 2877 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2878 reg = <0 0x06045000 0 0x1000>; 2879 2880 clocks = <&aoss_qmp>; 2881 clock-names = "apb_pclk"; 2882 2883 out-ports { 2884 port { 2885 merge_funnel_out: endpoint { 2886 remote-endpoint = <&etf_in>; 2887 }; 2888 }; 2889 }; 2890 2891 in-ports { 2892 #address-cells = <1>; 2893 #size-cells = <0>; 2894 2895 port@0 { 2896 reg = <0>; 2897 merge_funnel_in0: endpoint { 2898 remote-endpoint = <&funnel0_out>; 2899 }; 2900 }; 2901 2902 port@1 { 2903 reg = <1>; 2904 merge_funnel_in1: endpoint { 2905 remote-endpoint = <&funnel1_out>; 2906 }; 2907 }; 2908 2909 port@2 { 2910 reg = <2>; 2911 merge_funnel_in2: endpoint { 2912 remote-endpoint = <&funnel2_out>; 2913 }; 2914 }; 2915 }; 2916 }; 2917 2918 replicator@6046000 { 2919 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2920 reg = <0 0x06046000 0 0x1000>; 2921 2922 clocks = <&aoss_qmp>; 2923 clock-names = "apb_pclk"; 2924 2925 out-ports { 2926 #address-cells = <1>; 2927 #size-cells = <0>; 2928 2929 port@0 { 2930 reg = <0>; 2931 replicator_out0: endpoint { 2932 remote-endpoint = <&etr_in>; 2933 }; 2934 }; 2935 2936 port@1 { 2937 reg = <1>; 2938 replicator_out1: endpoint { 2939 remote-endpoint = <&replicator1_in>; 2940 }; 2941 }; 2942 }; 2943 2944 in-ports { 2945 port { 2946 replicator_in0: endpoint { 2947 remote-endpoint = <&etf_out>; 2948 }; 2949 }; 2950 }; 2951 }; 2952 2953 etf@6047000 { 2954 compatible = "arm,coresight-tmc", "arm,primecell"; 2955 reg = <0 0x06047000 0 0x1000>; 2956 2957 clocks = <&aoss_qmp>; 2958 clock-names = "apb_pclk"; 2959 2960 out-ports { 2961 port { 2962 etf_out: endpoint { 2963 remote-endpoint = <&replicator_in0>; 2964 }; 2965 }; 2966 }; 2967 2968 in-ports { 2969 port { 2970 etf_in: endpoint { 2971 remote-endpoint = <&merge_funnel_out>; 2972 }; 2973 }; 2974 }; 2975 }; 2976 2977 etr@6048000 { 2978 compatible = "arm,coresight-tmc", "arm,primecell"; 2979 reg = <0 0x06048000 0 0x1000>; 2980 iommus = <&apps_smmu 0x05e0 0x0>; 2981 2982 clocks = <&aoss_qmp>; 2983 clock-names = "apb_pclk"; 2984 arm,scatter-gather; 2985 2986 in-ports { 2987 port { 2988 etr_in: endpoint { 2989 remote-endpoint = <&replicator_out0>; 2990 }; 2991 }; 2992 }; 2993 }; 2994 2995 replicator@604a000 { 2996 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2997 reg = <0 0x0604a000 0 0x1000>; 2998 2999 clocks = <&aoss_qmp>; 3000 clock-names = "apb_pclk"; 3001 3002 out-ports { 3003 #address-cells = <1>; 3004 #size-cells = <0>; 3005 3006 port@1 { 3007 reg = <1>; 3008 replicator1_out: endpoint { 3009 remote-endpoint = <&swao_funnel_in>; 3010 }; 3011 }; 3012 }; 3013 3014 in-ports { 3015 3016 port { 3017 replicator1_in: endpoint { 3018 remote-endpoint = <&replicator_out1>; 3019 }; 3020 }; 3021 }; 3022 }; 3023 3024 funnel@6b08000 { 3025 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3026 reg = <0 0x06b08000 0 0x1000>; 3027 3028 clocks = <&aoss_qmp>; 3029 clock-names = "apb_pclk"; 3030 3031 out-ports { 3032 port { 3033 swao_funnel_out: endpoint { 3034 remote-endpoint = <&swao_etf_in>; 3035 }; 3036 }; 3037 }; 3038 3039 in-ports { 3040 #address-cells = <1>; 3041 #size-cells = <0>; 3042 3043 port@6 { 3044 reg = <6>; 3045 swao_funnel_in: endpoint { 3046 remote-endpoint = <&replicator1_out>; 3047 }; 3048 }; 3049 }; 3050 }; 3051 3052 etf@6b09000 { 3053 compatible = "arm,coresight-tmc", "arm,primecell"; 3054 reg = <0 0x06b09000 0 0x1000>; 3055 3056 clocks = <&aoss_qmp>; 3057 clock-names = "apb_pclk"; 3058 3059 out-ports { 3060 port { 3061 swao_etf_out: endpoint { 3062 remote-endpoint = <&swao_replicator_in>; 3063 }; 3064 }; 3065 }; 3066 3067 in-ports { 3068 port { 3069 swao_etf_in: endpoint { 3070 remote-endpoint = <&swao_funnel_out>; 3071 }; 3072 }; 3073 }; 3074 }; 3075 3076 replicator@6b0a000 { 3077 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3078 reg = <0 0x06b0a000 0 0x1000>; 3079 3080 clocks = <&aoss_qmp>; 3081 clock-names = "apb_pclk"; 3082 qcom,replicator-loses-context; 3083 3084 out-ports { 3085 port { 3086 swao_replicator_out: endpoint { 3087 remote-endpoint = <&funnel1_in4>; 3088 }; 3089 }; 3090 }; 3091 3092 in-ports { 3093 port { 3094 swao_replicator_in: endpoint { 3095 remote-endpoint = <&swao_etf_out>; 3096 }; 3097 }; 3098 }; 3099 }; 3100 3101 etm@7040000 { 3102 compatible = "arm,coresight-etm4x", "arm,primecell"; 3103 reg = <0 0x07040000 0 0x1000>; 3104 3105 cpu = <&cpu0>; 3106 3107 clocks = <&aoss_qmp>; 3108 clock-names = "apb_pclk"; 3109 arm,coresight-loses-context-with-cpu; 3110 qcom,skip-power-up; 3111 3112 out-ports { 3113 port { 3114 etm0_out: endpoint { 3115 remote-endpoint = <&apss_funnel_in0>; 3116 }; 3117 }; 3118 }; 3119 }; 3120 3121 etm@7140000 { 3122 compatible = "arm,coresight-etm4x", "arm,primecell"; 3123 reg = <0 0x07140000 0 0x1000>; 3124 3125 cpu = <&cpu1>; 3126 3127 clocks = <&aoss_qmp>; 3128 clock-names = "apb_pclk"; 3129 arm,coresight-loses-context-with-cpu; 3130 qcom,skip-power-up; 3131 3132 out-ports { 3133 port { 3134 etm1_out: endpoint { 3135 remote-endpoint = <&apss_funnel_in1>; 3136 }; 3137 }; 3138 }; 3139 }; 3140 3141 etm@7240000 { 3142 compatible = "arm,coresight-etm4x", "arm,primecell"; 3143 reg = <0 0x07240000 0 0x1000>; 3144 3145 cpu = <&cpu2>; 3146 3147 clocks = <&aoss_qmp>; 3148 clock-names = "apb_pclk"; 3149 arm,coresight-loses-context-with-cpu; 3150 qcom,skip-power-up; 3151 3152 out-ports { 3153 port { 3154 etm2_out: endpoint { 3155 remote-endpoint = <&apss_funnel_in2>; 3156 }; 3157 }; 3158 }; 3159 }; 3160 3161 etm@7340000 { 3162 compatible = "arm,coresight-etm4x", "arm,primecell"; 3163 reg = <0 0x07340000 0 0x1000>; 3164 3165 cpu = <&cpu3>; 3166 3167 clocks = <&aoss_qmp>; 3168 clock-names = "apb_pclk"; 3169 arm,coresight-loses-context-with-cpu; 3170 qcom,skip-power-up; 3171 3172 out-ports { 3173 port { 3174 etm3_out: endpoint { 3175 remote-endpoint = <&apss_funnel_in3>; 3176 }; 3177 }; 3178 }; 3179 }; 3180 3181 etm@7440000 { 3182 compatible = "arm,coresight-etm4x", "arm,primecell"; 3183 reg = <0 0x07440000 0 0x1000>; 3184 3185 cpu = <&cpu4>; 3186 3187 clocks = <&aoss_qmp>; 3188 clock-names = "apb_pclk"; 3189 arm,coresight-loses-context-with-cpu; 3190 qcom,skip-power-up; 3191 3192 out-ports { 3193 port { 3194 etm4_out: endpoint { 3195 remote-endpoint = <&apss_funnel_in4>; 3196 }; 3197 }; 3198 }; 3199 }; 3200 3201 etm@7540000 { 3202 compatible = "arm,coresight-etm4x", "arm,primecell"; 3203 reg = <0 0x07540000 0 0x1000>; 3204 3205 cpu = <&cpu5>; 3206 3207 clocks = <&aoss_qmp>; 3208 clock-names = "apb_pclk"; 3209 arm,coresight-loses-context-with-cpu; 3210 qcom,skip-power-up; 3211 3212 out-ports { 3213 port { 3214 etm5_out: endpoint { 3215 remote-endpoint = <&apss_funnel_in5>; 3216 }; 3217 }; 3218 }; 3219 }; 3220 3221 etm@7640000 { 3222 compatible = "arm,coresight-etm4x", "arm,primecell"; 3223 reg = <0 0x07640000 0 0x1000>; 3224 3225 cpu = <&cpu6>; 3226 3227 clocks = <&aoss_qmp>; 3228 clock-names = "apb_pclk"; 3229 arm,coresight-loses-context-with-cpu; 3230 qcom,skip-power-up; 3231 3232 out-ports { 3233 port { 3234 etm6_out: endpoint { 3235 remote-endpoint = <&apss_funnel_in6>; 3236 }; 3237 }; 3238 }; 3239 }; 3240 3241 etm@7740000 { 3242 compatible = "arm,coresight-etm4x", "arm,primecell"; 3243 reg = <0 0x07740000 0 0x1000>; 3244 3245 cpu = <&cpu7>; 3246 3247 clocks = <&aoss_qmp>; 3248 clock-names = "apb_pclk"; 3249 arm,coresight-loses-context-with-cpu; 3250 qcom,skip-power-up; 3251 3252 out-ports { 3253 port { 3254 etm7_out: endpoint { 3255 remote-endpoint = <&apss_funnel_in7>; 3256 }; 3257 }; 3258 }; 3259 }; 3260 3261 funnel@7800000 { /* APSS Funnel */ 3262 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3263 reg = <0 0x07800000 0 0x1000>; 3264 3265 clocks = <&aoss_qmp>; 3266 clock-names = "apb_pclk"; 3267 3268 out-ports { 3269 port { 3270 apss_funnel_out: endpoint { 3271 remote-endpoint = <&apss_merge_funnel_in>; 3272 }; 3273 }; 3274 }; 3275 3276 in-ports { 3277 #address-cells = <1>; 3278 #size-cells = <0>; 3279 3280 port@0 { 3281 reg = <0>; 3282 apss_funnel_in0: endpoint { 3283 remote-endpoint = <&etm0_out>; 3284 }; 3285 }; 3286 3287 port@1 { 3288 reg = <1>; 3289 apss_funnel_in1: endpoint { 3290 remote-endpoint = <&etm1_out>; 3291 }; 3292 }; 3293 3294 port@2 { 3295 reg = <2>; 3296 apss_funnel_in2: endpoint { 3297 remote-endpoint = <&etm2_out>; 3298 }; 3299 }; 3300 3301 port@3 { 3302 reg = <3>; 3303 apss_funnel_in3: endpoint { 3304 remote-endpoint = <&etm3_out>; 3305 }; 3306 }; 3307 3308 port@4 { 3309 reg = <4>; 3310 apss_funnel_in4: endpoint { 3311 remote-endpoint = <&etm4_out>; 3312 }; 3313 }; 3314 3315 port@5 { 3316 reg = <5>; 3317 apss_funnel_in5: endpoint { 3318 remote-endpoint = <&etm5_out>; 3319 }; 3320 }; 3321 3322 port@6 { 3323 reg = <6>; 3324 apss_funnel_in6: endpoint { 3325 remote-endpoint = <&etm6_out>; 3326 }; 3327 }; 3328 3329 port@7 { 3330 reg = <7>; 3331 apss_funnel_in7: endpoint { 3332 remote-endpoint = <&etm7_out>; 3333 }; 3334 }; 3335 }; 3336 }; 3337 3338 funnel@7810000 { 3339 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3340 reg = <0 0x07810000 0 0x1000>; 3341 3342 clocks = <&aoss_qmp>; 3343 clock-names = "apb_pclk"; 3344 3345 out-ports { 3346 port { 3347 apss_merge_funnel_out: endpoint { 3348 remote-endpoint = <&funnel2_in2>; 3349 }; 3350 }; 3351 }; 3352 3353 in-ports { 3354 port { 3355 apss_merge_funnel_in: endpoint { 3356 remote-endpoint = <&apss_funnel_out>; 3357 }; 3358 }; 3359 }; 3360 }; 3361 3362 remoteproc_cdsp: remoteproc@8300000 { 3363 compatible = "qcom,sm8150-cdsp-pas"; 3364 reg = <0x0 0x08300000 0x0 0x4040>; 3365 3366 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3367 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3368 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3369 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3370 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3371 interrupt-names = "wdog", "fatal", "ready", 3372 "handover", "stop-ack"; 3373 3374 clocks = <&rpmhcc RPMH_CXO_CLK>; 3375 clock-names = "xo"; 3376 3377 power-domains = <&rpmhpd SM8150_CX>; 3378 3379 memory-region = <&cdsp_mem>; 3380 3381 qcom,qmp = <&aoss_qmp>; 3382 3383 qcom,smem-states = <&cdsp_smp2p_out 0>; 3384 qcom,smem-state-names = "stop"; 3385 3386 status = "disabled"; 3387 3388 glink-edge { 3389 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 3390 label = "cdsp"; 3391 qcom,remote-pid = <5>; 3392 mboxes = <&apss_shared 4>; 3393 3394 fastrpc { 3395 compatible = "qcom,fastrpc"; 3396 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3397 label = "cdsp"; 3398 qcom,non-secure-domain; 3399 #address-cells = <1>; 3400 #size-cells = <0>; 3401 3402 compute-cb@1 { 3403 compatible = "qcom,fastrpc-compute-cb"; 3404 reg = <1>; 3405 iommus = <&apps_smmu 0x1001 0x0460>; 3406 }; 3407 3408 compute-cb@2 { 3409 compatible = "qcom,fastrpc-compute-cb"; 3410 reg = <2>; 3411 iommus = <&apps_smmu 0x1002 0x0460>; 3412 }; 3413 3414 compute-cb@3 { 3415 compatible = "qcom,fastrpc-compute-cb"; 3416 reg = <3>; 3417 iommus = <&apps_smmu 0x1003 0x0460>; 3418 }; 3419 3420 compute-cb@4 { 3421 compatible = "qcom,fastrpc-compute-cb"; 3422 reg = <4>; 3423 iommus = <&apps_smmu 0x1004 0x0460>; 3424 }; 3425 3426 compute-cb@5 { 3427 compatible = "qcom,fastrpc-compute-cb"; 3428 reg = <5>; 3429 iommus = <&apps_smmu 0x1005 0x0460>; 3430 }; 3431 3432 compute-cb@6 { 3433 compatible = "qcom,fastrpc-compute-cb"; 3434 reg = <6>; 3435 iommus = <&apps_smmu 0x1006 0x0460>; 3436 }; 3437 3438 compute-cb@7 { 3439 compatible = "qcom,fastrpc-compute-cb"; 3440 reg = <7>; 3441 iommus = <&apps_smmu 0x1007 0x0460>; 3442 }; 3443 3444 compute-cb@8 { 3445 compatible = "qcom,fastrpc-compute-cb"; 3446 reg = <8>; 3447 iommus = <&apps_smmu 0x1008 0x0460>; 3448 }; 3449 3450 /* note: secure cb9 in downstream */ 3451 }; 3452 }; 3453 }; 3454 3455 usb_1_hsphy: phy@88e2000 { 3456 compatible = "qcom,sm8150-usb-hs-phy", 3457 "qcom,usb-snps-hs-7nm-phy"; 3458 reg = <0 0x088e2000 0 0x400>; 3459 status = "disabled"; 3460 #phy-cells = <0>; 3461 3462 clocks = <&rpmhcc RPMH_CXO_CLK>; 3463 clock-names = "ref"; 3464 3465 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3466 }; 3467 3468 usb_2_hsphy: phy@88e3000 { 3469 compatible = "qcom,sm8150-usb-hs-phy", 3470 "qcom,usb-snps-hs-7nm-phy"; 3471 reg = <0 0x088e3000 0 0x400>; 3472 status = "disabled"; 3473 #phy-cells = <0>; 3474 3475 clocks = <&rpmhcc RPMH_CXO_CLK>; 3476 clock-names = "ref"; 3477 3478 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3479 }; 3480 3481 refgen: regulator@88e7000 { 3482 compatible = "qcom,sm8150-refgen-regulator", 3483 "qcom,sdm845-refgen-regulator"; 3484 reg = <0x0 0x088e7000 0x0 0x60>; 3485 }; 3486 3487 usb_1_qmpphy: phy@88e8000 { 3488 compatible = "qcom,sm8150-qmp-usb3-dp-phy"; 3489 reg = <0 0x088e8000 0 0x3000>; 3490 3491 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3492 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3493 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3494 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3495 clock-names = "aux", 3496 "ref", 3497 "com_aux", 3498 "usb3_pipe"; 3499 3500 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3501 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3502 reset-names = "phy", "common"; 3503 3504 #clock-cells = <1>; 3505 #phy-cells = <1>; 3506 3507 status = "disabled"; 3508 3509 ports { 3510 #address-cells = <1>; 3511 #size-cells = <0>; 3512 3513 port@0 { 3514 reg = <0>; 3515 3516 usb_1_qmpphy_out: endpoint { 3517 }; 3518 }; 3519 3520 port@1 { 3521 reg = <1>; 3522 3523 usb_1_qmpphy_usb_ss_in: endpoint { 3524 remote-endpoint = <&usb_1_dwc3_ss>; 3525 }; 3526 }; 3527 3528 port@2 { 3529 reg = <2>; 3530 3531 usb_1_qmpphy_dp_in: endpoint { 3532 remote-endpoint = <&mdss_dp_out>; 3533 }; 3534 }; 3535 }; 3536 }; 3537 3538 usb_2_qmpphy: phy@88eb000 { 3539 compatible = "qcom,sm8150-qmp-usb3-uni-phy"; 3540 reg = <0 0x088eb000 0 0x1000>; 3541 3542 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3543 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 3544 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 3545 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3546 clock-names = "aux", 3547 "ref", 3548 "com_aux", 3549 "pipe"; 3550 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3551 #clock-cells = <0>; 3552 #phy-cells = <0>; 3553 3554 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 3555 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 3556 reset-names = "phy", 3557 "phy_phy"; 3558 3559 status = "disabled"; 3560 }; 3561 3562 sdhc_2: mmc@8804000 { 3563 compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5"; 3564 reg = <0 0x08804000 0 0x1000>; 3565 3566 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3567 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3568 interrupt-names = "hc_irq", "pwr_irq"; 3569 3570 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3571 <&gcc GCC_SDCC2_APPS_CLK>, 3572 <&rpmhcc RPMH_CXO_CLK>; 3573 clock-names = "iface", "core", "xo"; 3574 iommus = <&apps_smmu 0x6a0 0x0>; 3575 qcom,dll-config = <0x0007642c>; 3576 qcom,ddr-config = <0x80040868>; 3577 power-domains = <&rpmhpd 0>; 3578 operating-points-v2 = <&sdhc2_opp_table>; 3579 3580 status = "disabled"; 3581 3582 sdhc2_opp_table: opp-table { 3583 compatible = "operating-points-v2"; 3584 3585 opp-19200000 { 3586 opp-hz = /bits/ 64 <19200000>; 3587 required-opps = <&rpmhpd_opp_min_svs>; 3588 }; 3589 3590 opp-50000000 { 3591 opp-hz = /bits/ 64 <50000000>; 3592 required-opps = <&rpmhpd_opp_low_svs>; 3593 }; 3594 3595 opp-100000000 { 3596 opp-hz = /bits/ 64 <100000000>; 3597 required-opps = <&rpmhpd_opp_svs>; 3598 }; 3599 3600 opp-202000000 { 3601 opp-hz = /bits/ 64 <202000000>; 3602 required-opps = <&rpmhpd_opp_svs_l1>; 3603 }; 3604 }; 3605 }; 3606 3607 dc_noc: interconnect@9160000 { 3608 compatible = "qcom,sm8150-dc-noc"; 3609 reg = <0 0x09160000 0 0x3200>; 3610 #interconnect-cells = <2>; 3611 qcom,bcm-voters = <&apps_bcm_voter>; 3612 }; 3613 3614 gem_noc: interconnect@9680000 { 3615 compatible = "qcom,sm8150-gem-noc"; 3616 reg = <0 0x09680000 0 0x3e200>; 3617 #interconnect-cells = <2>; 3618 qcom,bcm-voters = <&apps_bcm_voter>; 3619 }; 3620 3621 usb_1: usb@a6f8800 { 3622 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3623 reg = <0 0x0a6f8800 0 0x400>; 3624 status = "disabled"; 3625 #address-cells = <2>; 3626 #size-cells = <2>; 3627 ranges; 3628 dma-ranges; 3629 3630 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3631 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3632 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3633 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3634 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3635 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3636 clock-names = "cfg_noc", 3637 "core", 3638 "iface", 3639 "sleep", 3640 "mock_utmi", 3641 "xo"; 3642 3643 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3644 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3645 assigned-clock-rates = <19200000>, <200000000>; 3646 3647 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 3648 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3649 <&pdc 9 IRQ_TYPE_EDGE_BOTH>, 3650 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 3651 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; 3652 interrupt-names = "pwr_event", 3653 "hs_phy_irq", 3654 "dp_hs_phy_irq", 3655 "dm_hs_phy_irq", 3656 "ss_phy_irq"; 3657 3658 power-domains = <&gcc USB30_PRIM_GDSC>; 3659 3660 resets = <&gcc GCC_USB30_PRIM_BCR>; 3661 3662 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, 3663 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 3664 interconnect-names = "usb-ddr", "apps-usb"; 3665 3666 usb_1_dwc3: usb@a600000 { 3667 compatible = "snps,dwc3"; 3668 reg = <0 0x0a600000 0 0xcd00>; 3669 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3670 iommus = <&apps_smmu 0x140 0>; 3671 snps,dis_u2_susphy_quirk; 3672 snps,dis_u3_susphy_quirk; 3673 snps,dis_enblslpm_quirk; 3674 snps,dis-u1-entry-quirk; 3675 snps,dis-u2-entry-quirk; 3676 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 3677 phy-names = "usb2-phy", "usb3-phy"; 3678 3679 ports { 3680 #address-cells = <1>; 3681 #size-cells = <0>; 3682 3683 port@0 { 3684 reg = <0>; 3685 3686 usb_1_dwc3_hs: endpoint { 3687 }; 3688 }; 3689 3690 port@1 { 3691 reg = <1>; 3692 3693 usb_1_dwc3_ss: endpoint { 3694 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 3695 }; 3696 }; 3697 }; 3698 }; 3699 }; 3700 3701 usb_2: usb@a8f8800 { 3702 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3703 reg = <0 0x0a8f8800 0 0x400>; 3704 status = "disabled"; 3705 #address-cells = <2>; 3706 #size-cells = <2>; 3707 ranges; 3708 dma-ranges; 3709 3710 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3711 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3712 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3713 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3714 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3715 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3716 clock-names = "cfg_noc", 3717 "core", 3718 "iface", 3719 "sleep", 3720 "mock_utmi", 3721 "xo"; 3722 3723 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3724 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3725 assigned-clock-rates = <19200000>, <200000000>; 3726 3727 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 3728 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3729 <&pdc 11 IRQ_TYPE_EDGE_BOTH>, 3730 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 3731 <&pdc 7 IRQ_TYPE_LEVEL_HIGH>; 3732 interrupt-names = "pwr_event", 3733 "hs_phy_irq", 3734 "dp_hs_phy_irq", 3735 "dm_hs_phy_irq", 3736 "ss_phy_irq"; 3737 3738 power-domains = <&gcc USB30_SEC_GDSC>; 3739 3740 resets = <&gcc GCC_USB30_SEC_BCR>; 3741 3742 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, 3743 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; 3744 interconnect-names = "usb-ddr", "apps-usb"; 3745 3746 usb_2_dwc3: usb@a800000 { 3747 compatible = "snps,dwc3"; 3748 reg = <0 0x0a800000 0 0xcd00>; 3749 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3750 iommus = <&apps_smmu 0x160 0>; 3751 snps,dis_u2_susphy_quirk; 3752 snps,dis_u3_susphy_quirk; 3753 snps,dis_enblslpm_quirk; 3754 snps,dis-u1-entry-quirk; 3755 snps,dis-u2-entry-quirk; 3756 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>; 3757 phy-names = "usb2-phy", "usb3-phy"; 3758 }; 3759 }; 3760 3761 videocc: clock-controller@ab00000 { 3762 compatible = "qcom,sm8150-videocc"; 3763 reg = <0 0x0ab00000 0 0x10000>; 3764 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 3765 <&rpmhcc RPMH_CXO_CLK>; 3766 clock-names = "iface", "bi_tcxo"; 3767 power-domains = <&rpmhpd SM8150_MMCX>; 3768 required-opps = <&rpmhpd_opp_low_svs>; 3769 #clock-cells = <1>; 3770 #reset-cells = <1>; 3771 #power-domain-cells = <1>; 3772 }; 3773 3774 camnoc_virt: interconnect@ac00000 { 3775 compatible = "qcom,sm8150-camnoc-virt"; 3776 reg = <0 0x0ac00000 0 0x1000>; 3777 #interconnect-cells = <2>; 3778 qcom,bcm-voters = <&apps_bcm_voter>; 3779 }; 3780 3781 camcc: clock-controller@ad00000 { 3782 compatible = "qcom,sm8150-camcc"; 3783 reg = <0 0x0ad00000 0 0x10000>; 3784 clocks = <&rpmhcc RPMH_CXO_CLK>, 3785 <&gcc GCC_CAMERA_AHB_CLK>; 3786 power-domains = <&rpmhpd SM8150_MMCX>; 3787 required-opps = <&rpmhpd_opp_low_svs>; 3788 #clock-cells = <1>; 3789 #reset-cells = <1>; 3790 #power-domain-cells = <1>; 3791 }; 3792 3793 mdss: display-subsystem@ae00000 { 3794 compatible = "qcom,sm8150-mdss"; 3795 reg = <0 0x0ae00000 0 0x1000>; 3796 reg-names = "mdss"; 3797 3798 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>, 3799 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>; 3800 interconnect-names = "mdp0-mem", "mdp1-mem"; 3801 3802 power-domains = <&dispcc MDSS_GDSC>; 3803 3804 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3805 <&gcc GCC_DISP_HF_AXI_CLK>, 3806 <&gcc GCC_DISP_SF_AXI_CLK>, 3807 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3808 clock-names = "iface", "bus", "nrt_bus", "core"; 3809 3810 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3811 interrupt-controller; 3812 #interrupt-cells = <1>; 3813 3814 iommus = <&apps_smmu 0x800 0x420>; 3815 3816 status = "disabled"; 3817 3818 #address-cells = <2>; 3819 #size-cells = <2>; 3820 ranges; 3821 3822 mdss_mdp: display-controller@ae01000 { 3823 compatible = "qcom,sm8150-dpu"; 3824 reg = <0 0x0ae01000 0 0x8f000>, 3825 <0 0x0aeb0000 0 0x3000>; 3826 reg-names = "mdp", "vbif"; 3827 3828 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3829 <&gcc GCC_DISP_HF_AXI_CLK>, 3830 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3831 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3832 clock-names = "iface", "bus", "core", "vsync"; 3833 3834 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3835 assigned-clock-rates = <19200000>; 3836 3837 operating-points-v2 = <&mdp_opp_table>; 3838 power-domains = <&rpmhpd SM8150_MMCX>; 3839 3840 interrupt-parent = <&mdss>; 3841 interrupts = <0>; 3842 3843 ports { 3844 #address-cells = <1>; 3845 #size-cells = <0>; 3846 3847 port@0 { 3848 reg = <0>; 3849 dpu_intf1_out: endpoint { 3850 remote-endpoint = <&mdss_dsi0_in>; 3851 }; 3852 }; 3853 3854 port@1 { 3855 reg = <1>; 3856 dpu_intf2_out: endpoint { 3857 remote-endpoint = <&mdss_dsi1_in>; 3858 }; 3859 }; 3860 3861 port@2 { 3862 reg = <2>; 3863 dpu_intf0_out: endpoint { 3864 remote-endpoint = <&mdss_dp_in>; 3865 }; 3866 }; 3867 }; 3868 3869 mdp_opp_table: opp-table { 3870 compatible = "operating-points-v2"; 3871 3872 opp-171428571 { 3873 opp-hz = /bits/ 64 <171428571>; 3874 required-opps = <&rpmhpd_opp_low_svs>; 3875 }; 3876 3877 opp-300000000 { 3878 opp-hz = /bits/ 64 <300000000>; 3879 required-opps = <&rpmhpd_opp_svs>; 3880 }; 3881 3882 opp-345000000 { 3883 opp-hz = /bits/ 64 <345000000>; 3884 required-opps = <&rpmhpd_opp_svs_l1>; 3885 }; 3886 3887 opp-460000000 { 3888 opp-hz = /bits/ 64 <460000000>; 3889 required-opps = <&rpmhpd_opp_nom>; 3890 }; 3891 }; 3892 }; 3893 3894 mdss_dp: displayport-controller@ae90000 { 3895 compatible = "qcom,sm8150-dp", "qcom,sm8350-dp"; 3896 reg = <0 0xae90000 0 0x200>, 3897 <0 0xae90200 0 0x200>, 3898 <0 0xae90400 0 0x600>, 3899 <0 0x0ae90a00 0 0x600>, 3900 <0 0x0ae91000 0 0x600>; 3901 3902 interrupt-parent = <&mdss>; 3903 interrupts = <12>; 3904 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3905 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3906 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3907 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3908 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, 3909 <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; 3910 clock-names = "core_iface", 3911 "core_aux", 3912 "ctrl_link", 3913 "ctrl_link_iface", 3914 "stream_pixel", 3915 "stream_1_pixel"; 3916 3917 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3918 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, 3919 <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; 3920 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3921 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3922 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3923 3924 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 3925 phy-names = "dp"; 3926 3927 #sound-dai-cells = <0>; 3928 3929 operating-points-v2 = <&dp_opp_table>; 3930 power-domains = <&rpmhpd SM8150_MMCX>; 3931 3932 status = "disabled"; 3933 3934 ports { 3935 #address-cells = <1>; 3936 #size-cells = <0>; 3937 3938 port@0 { 3939 reg = <0>; 3940 mdss_dp_in: endpoint { 3941 remote-endpoint = <&dpu_intf0_out>; 3942 }; 3943 }; 3944 3945 port@1 { 3946 reg = <1>; 3947 3948 mdss_dp_out: endpoint { 3949 remote-endpoint = <&usb_1_qmpphy_dp_in>; 3950 }; 3951 }; 3952 }; 3953 3954 dp_opp_table: opp-table { 3955 compatible = "operating-points-v2"; 3956 3957 opp-162000000 { 3958 opp-hz = /bits/ 64 <162000000>; 3959 required-opps = <&rpmhpd_opp_low_svs>; 3960 }; 3961 3962 opp-270000000 { 3963 opp-hz = /bits/ 64 <270000000>; 3964 required-opps = <&rpmhpd_opp_svs>; 3965 }; 3966 3967 opp-540000000 { 3968 opp-hz = /bits/ 64 <540000000>; 3969 required-opps = <&rpmhpd_opp_svs_l1>; 3970 }; 3971 3972 opp-810000000 { 3973 opp-hz = /bits/ 64 <810000000>; 3974 required-opps = <&rpmhpd_opp_nom>; 3975 }; 3976 }; 3977 }; 3978 3979 mdss_dsi0: dsi@ae94000 { 3980 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3981 reg = <0 0x0ae94000 0 0x400>; 3982 reg-names = "dsi_ctrl"; 3983 3984 interrupt-parent = <&mdss>; 3985 interrupts = <4>; 3986 3987 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3988 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3989 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3990 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3991 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3992 <&gcc GCC_DISP_HF_AXI_CLK>; 3993 clock-names = "byte", 3994 "byte_intf", 3995 "pixel", 3996 "core", 3997 "iface", 3998 "bus"; 3999 4000 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 4001 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4002 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 4003 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 4004 4005 operating-points-v2 = <&dsi_opp_table>; 4006 power-domains = <&rpmhpd SM8150_MMCX>; 4007 4008 phys = <&mdss_dsi0_phy>; 4009 4010 refgen-supply = <&refgen>; 4011 4012 status = "disabled"; 4013 4014 #address-cells = <1>; 4015 #size-cells = <0>; 4016 4017 ports { 4018 #address-cells = <1>; 4019 #size-cells = <0>; 4020 4021 port@0 { 4022 reg = <0>; 4023 mdss_dsi0_in: endpoint { 4024 remote-endpoint = <&dpu_intf1_out>; 4025 }; 4026 }; 4027 4028 port@1 { 4029 reg = <1>; 4030 mdss_dsi0_out: endpoint { 4031 }; 4032 }; 4033 }; 4034 4035 dsi_opp_table: opp-table { 4036 compatible = "operating-points-v2"; 4037 4038 opp-187500000 { 4039 opp-hz = /bits/ 64 <187500000>; 4040 required-opps = <&rpmhpd_opp_low_svs>; 4041 }; 4042 4043 opp-300000000 { 4044 opp-hz = /bits/ 64 <300000000>; 4045 required-opps = <&rpmhpd_opp_svs>; 4046 }; 4047 4048 opp-358000000 { 4049 opp-hz = /bits/ 64 <358000000>; 4050 required-opps = <&rpmhpd_opp_svs_l1>; 4051 }; 4052 }; 4053 }; 4054 4055 mdss_dsi0_phy: phy@ae94400 { 4056 compatible = "qcom,dsi-phy-7nm-8150"; 4057 reg = <0 0x0ae94400 0 0x200>, 4058 <0 0x0ae94600 0 0x280>, 4059 <0 0x0ae94900 0 0x260>; 4060 reg-names = "dsi_phy", 4061 "dsi_phy_lane", 4062 "dsi_pll"; 4063 4064 #clock-cells = <1>; 4065 #phy-cells = <0>; 4066 4067 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4068 <&rpmhcc RPMH_CXO_CLK>; 4069 clock-names = "iface", "ref"; 4070 4071 status = "disabled"; 4072 }; 4073 4074 mdss_dsi1: dsi@ae96000 { 4075 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 4076 reg = <0 0x0ae96000 0 0x400>; 4077 reg-names = "dsi_ctrl"; 4078 4079 interrupt-parent = <&mdss>; 4080 interrupts = <5>; 4081 4082 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 4083 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 4084 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 4085 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 4086 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4087 <&gcc GCC_DISP_HF_AXI_CLK>; 4088 clock-names = "byte", 4089 "byte_intf", 4090 "pixel", 4091 "core", 4092 "iface", 4093 "bus"; 4094 4095 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 4096 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 4097 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 4098 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 4099 4100 operating-points-v2 = <&dsi_opp_table>; 4101 power-domains = <&rpmhpd SM8150_MMCX>; 4102 4103 phys = <&mdss_dsi1_phy>; 4104 4105 refgen-supply = <&refgen>; 4106 4107 status = "disabled"; 4108 4109 #address-cells = <1>; 4110 #size-cells = <0>; 4111 4112 ports { 4113 #address-cells = <1>; 4114 #size-cells = <0>; 4115 4116 port@0 { 4117 reg = <0>; 4118 mdss_dsi1_in: endpoint { 4119 remote-endpoint = <&dpu_intf2_out>; 4120 }; 4121 }; 4122 4123 port@1 { 4124 reg = <1>; 4125 mdss_dsi1_out: endpoint { 4126 }; 4127 }; 4128 }; 4129 }; 4130 4131 mdss_dsi1_phy: phy@ae96400 { 4132 compatible = "qcom,dsi-phy-7nm-8150"; 4133 reg = <0 0x0ae96400 0 0x200>, 4134 <0 0x0ae96600 0 0x280>, 4135 <0 0x0ae96900 0 0x260>; 4136 reg-names = "dsi_phy", 4137 "dsi_phy_lane", 4138 "dsi_pll"; 4139 4140 #clock-cells = <1>; 4141 #phy-cells = <0>; 4142 4143 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4144 <&rpmhcc RPMH_CXO_CLK>; 4145 clock-names = "iface", "ref"; 4146 4147 status = "disabled"; 4148 }; 4149 }; 4150 4151 dispcc: clock-controller@af00000 { 4152 compatible = "qcom,sm8150-dispcc"; 4153 reg = <0 0x0af00000 0 0x10000>; 4154 clocks = <&rpmhcc RPMH_CXO_CLK>, 4155 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 4156 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 4157 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 4158 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 4159 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4160 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4161 clock-names = "bi_tcxo", 4162 "dsi0_phy_pll_out_byteclk", 4163 "dsi0_phy_pll_out_dsiclk", 4164 "dsi1_phy_pll_out_byteclk", 4165 "dsi1_phy_pll_out_dsiclk", 4166 "dp_phy_pll_link_clk", 4167 "dp_phy_pll_vco_div_clk"; 4168 power-domains = <&rpmhpd SM8150_MMCX>; 4169 required-opps = <&rpmhpd_opp_low_svs>; 4170 #clock-cells = <1>; 4171 #reset-cells = <1>; 4172 #power-domain-cells = <1>; 4173 }; 4174 4175 pdc: interrupt-controller@b220000 { 4176 compatible = "qcom,sm8150-pdc", "qcom,pdc"; 4177 reg = <0 0x0b220000 0 0x30000>; 4178 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 4179 <125 63 1>; 4180 #interrupt-cells = <2>; 4181 interrupt-parent = <&intc>; 4182 interrupt-controller; 4183 }; 4184 4185 aoss_qmp: power-management@c300000 { 4186 compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp"; 4187 reg = <0x0 0x0c300000 0x0 0x400>; 4188 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 4189 mboxes = <&apss_shared 0>; 4190 4191 #clock-cells = <0>; 4192 }; 4193 4194 sram@c3f0000 { 4195 compatible = "qcom,rpmh-stats"; 4196 reg = <0 0x0c3f0000 0 0x400>; 4197 }; 4198 4199 tsens0: thermal-sensor@c263000 { 4200 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 4201 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4202 <0 0x0c222000 0 0x1ff>; /* SROT */ 4203 #qcom,sensors = <16>; 4204 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4205 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4206 interrupt-names = "uplow", "critical"; 4207 #thermal-sensor-cells = <1>; 4208 }; 4209 4210 tsens1: thermal-sensor@c265000 { 4211 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 4212 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4213 <0 0x0c223000 0 0x1ff>; /* SROT */ 4214 #qcom,sensors = <8>; 4215 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4216 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4217 interrupt-names = "uplow", "critical"; 4218 #thermal-sensor-cells = <1>; 4219 }; 4220 4221 spmi_bus: spmi@c440000 { 4222 compatible = "qcom,spmi-pmic-arb"; 4223 reg = <0x0 0x0c440000 0x0 0x0001100>, 4224 <0x0 0x0c600000 0x0 0x2000000>, 4225 <0x0 0x0e600000 0x0 0x0100000>, 4226 <0x0 0x0e700000 0x0 0x00a0000>, 4227 <0x0 0x0c40a000 0x0 0x0026000>; 4228 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4229 interrupt-names = "periph_irq"; 4230 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 4231 qcom,ee = <0>; 4232 qcom,channel = <0>; 4233 #address-cells = <2>; 4234 #size-cells = <0>; 4235 interrupt-controller; 4236 #interrupt-cells = <4>; 4237 }; 4238 4239 apps_smmu: iommu@15000000 { 4240 compatible = "qcom,sm8150-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 4241 reg = <0 0x15000000 0 0x100000>; 4242 #iommu-cells = <2>; 4243 #global-interrupts = <1>; 4244 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4245 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4246 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4247 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4248 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4249 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4250 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4251 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4252 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4253 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4254 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4255 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4256 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4257 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4258 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4259 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4260 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4261 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4262 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4263 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4264 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4265 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4266 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4267 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4268 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4269 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4270 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4271 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4272 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4273 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4274 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4275 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4276 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4277 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4278 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4279 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4280 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4281 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4282 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4283 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4284 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4285 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4286 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4287 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4288 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4289 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4290 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4291 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4292 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4293 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4294 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4295 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4296 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4297 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4298 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4299 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4300 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4301 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4302 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4303 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4304 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4305 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4306 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4307 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4308 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4309 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4310 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4311 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4312 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4313 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4314 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4315 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4316 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4317 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4318 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4319 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4320 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4321 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4322 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4323 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4324 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 4325 dma-coherent; 4326 }; 4327 4328 remoteproc_adsp: remoteproc@17300000 { 4329 compatible = "qcom,sm8150-adsp-pas"; 4330 reg = <0x0 0x17300000 0x0 0x4040>; 4331 4332 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 4333 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4334 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 4335 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 4336 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 4337 interrupt-names = "wdog", "fatal", "ready", 4338 "handover", "stop-ack"; 4339 4340 clocks = <&rpmhcc RPMH_CXO_CLK>; 4341 clock-names = "xo"; 4342 4343 power-domains = <&rpmhpd SM8150_CX>; 4344 4345 memory-region = <&adsp_mem>; 4346 4347 qcom,qmp = <&aoss_qmp>; 4348 4349 qcom,smem-states = <&adsp_smp2p_out 0>; 4350 qcom,smem-state-names = "stop"; 4351 4352 status = "disabled"; 4353 4354 glink-edge { 4355 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 4356 label = "lpass"; 4357 qcom,remote-pid = <2>; 4358 mboxes = <&apss_shared 8>; 4359 4360 fastrpc { 4361 compatible = "qcom,fastrpc"; 4362 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4363 label = "adsp"; 4364 qcom,non-secure-domain; 4365 #address-cells = <1>; 4366 #size-cells = <0>; 4367 4368 compute-cb@3 { 4369 compatible = "qcom,fastrpc-compute-cb"; 4370 reg = <3>; 4371 iommus = <&apps_smmu 0x1b23 0x0>; 4372 }; 4373 4374 compute-cb@4 { 4375 compatible = "qcom,fastrpc-compute-cb"; 4376 reg = <4>; 4377 iommus = <&apps_smmu 0x1b24 0x0>; 4378 }; 4379 4380 compute-cb@5 { 4381 compatible = "qcom,fastrpc-compute-cb"; 4382 reg = <5>; 4383 iommus = <&apps_smmu 0x1b25 0x0>; 4384 }; 4385 }; 4386 }; 4387 }; 4388 4389 intc: interrupt-controller@17a00000 { 4390 compatible = "arm,gic-v3"; 4391 interrupt-controller; 4392 #address-cells = <0>; 4393 #interrupt-cells = <3>; 4394 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4395 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4396 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4397 }; 4398 4399 apss_shared: mailbox@17c00000 { 4400 compatible = "qcom,sm8150-apss-shared", 4401 "qcom,sdm845-apss-shared"; 4402 reg = <0x0 0x17c00000 0x0 0x1000>; 4403 #mbox-cells = <1>; 4404 }; 4405 4406 watchdog@17c10000 { 4407 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; 4408 reg = <0 0x17c10000 0 0x1000>; 4409 clocks = <&sleep_clk>; 4410 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 4411 }; 4412 4413 timer@17c20000 { 4414 #address-cells = <1>; 4415 #size-cells = <1>; 4416 ranges = <0 0 0 0x20000000>; 4417 compatible = "arm,armv7-timer-mem"; 4418 reg = <0x0 0x17c20000 0x0 0x1000>; 4419 clock-frequency = <19200000>; 4420 4421 frame@17c21000 { 4422 frame-number = <0>; 4423 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4424 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4425 reg = <0x17c21000 0x1000>, 4426 <0x17c22000 0x1000>; 4427 }; 4428 4429 frame@17c23000 { 4430 frame-number = <1>; 4431 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4432 reg = <0x17c23000 0x1000>; 4433 status = "disabled"; 4434 }; 4435 4436 frame@17c25000 { 4437 frame-number = <2>; 4438 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4439 reg = <0x17c25000 0x1000>; 4440 status = "disabled"; 4441 }; 4442 4443 frame@17c27000 { 4444 frame-number = <3>; 4445 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4446 reg = <0x17c27000 0x1000>; 4447 status = "disabled"; 4448 }; 4449 4450 frame@17c29000 { 4451 frame-number = <4>; 4452 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4453 reg = <0x17c29000 0x1000>; 4454 status = "disabled"; 4455 }; 4456 4457 frame@17c2b000 { 4458 frame-number = <5>; 4459 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4460 reg = <0x17c2b000 0x1000>; 4461 status = "disabled"; 4462 }; 4463 4464 frame@17c2d000 { 4465 frame-number = <6>; 4466 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4467 reg = <0x17c2d000 0x1000>; 4468 status = "disabled"; 4469 }; 4470 }; 4471 4472 apps_rsc: rsc@18200000 { 4473 label = "apps_rsc"; 4474 compatible = "qcom,rpmh-rsc"; 4475 reg = <0x0 0x18200000 0x0 0x10000>, 4476 <0x0 0x18210000 0x0 0x10000>, 4477 <0x0 0x18220000 0x0 0x10000>; 4478 reg-names = "drv-0", "drv-1", "drv-2"; 4479 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4480 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4481 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4482 qcom,tcs-offset = <0xd00>; 4483 qcom,drv-id = <2>; 4484 qcom,tcs-config = <ACTIVE_TCS 2>, 4485 <SLEEP_TCS 3>, 4486 <WAKE_TCS 3>, 4487 <CONTROL_TCS 1>; 4488 power-domains = <&cluster_pd>; 4489 4490 rpmhcc: clock-controller { 4491 compatible = "qcom,sm8150-rpmh-clk"; 4492 #clock-cells = <1>; 4493 clock-names = "xo"; 4494 clocks = <&xo_board>; 4495 }; 4496 4497 rpmhpd: power-controller { 4498 compatible = "qcom,sm8150-rpmhpd"; 4499 #power-domain-cells = <1>; 4500 operating-points-v2 = <&rpmhpd_opp_table>; 4501 4502 rpmhpd_opp_table: opp-table { 4503 compatible = "operating-points-v2"; 4504 4505 rpmhpd_opp_ret: opp1 { 4506 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4507 }; 4508 4509 rpmhpd_opp_min_svs: opp2 { 4510 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4511 }; 4512 4513 rpmhpd_opp_low_svs: opp3 { 4514 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4515 }; 4516 4517 rpmhpd_opp_svs: opp4 { 4518 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4519 }; 4520 4521 rpmhpd_opp_svs_l1: opp5 { 4522 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4523 }; 4524 4525 rpmhpd_opp_svs_l2: opp6 { 4526 opp-level = <224>; 4527 }; 4528 4529 rpmhpd_opp_nom: opp7 { 4530 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4531 }; 4532 4533 rpmhpd_opp_nom_l1: opp8 { 4534 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4535 }; 4536 4537 rpmhpd_opp_nom_l2: opp9 { 4538 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4539 }; 4540 4541 rpmhpd_opp_turbo: opp10 { 4542 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4543 }; 4544 4545 rpmhpd_opp_turbo_l1: opp11 { 4546 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4547 }; 4548 }; 4549 }; 4550 4551 apps_bcm_voter: bcm-voter { 4552 compatible = "qcom,bcm-voter"; 4553 }; 4554 }; 4555 4556 osm_l3: interconnect@18321000 { 4557 compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3"; 4558 reg = <0 0x18321000 0 0x1400>; 4559 4560 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4561 clock-names = "xo", "alternate"; 4562 4563 #interconnect-cells = <1>; 4564 }; 4565 4566 cpufreq_hw: cpufreq@18323000 { 4567 compatible = "qcom,sm8150-cpufreq-hw", "qcom,cpufreq-hw"; 4568 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, 4569 <0 0x18327800 0 0x1400>; 4570 reg-names = "freq-domain0", "freq-domain1", 4571 "freq-domain2"; 4572 4573 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4574 clock-names = "xo", "alternate"; 4575 4576 #freq-domain-cells = <1>; 4577 #clock-cells = <1>; 4578 }; 4579 4580 lmh_cluster1: lmh@18350800 { 4581 compatible = "qcom,sm8150-lmh"; 4582 reg = <0 0x18350800 0 0x400>; 4583 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 4584 cpus = <&cpu4>; 4585 qcom,lmh-temp-arm-millicelsius = <60000>; 4586 qcom,lmh-temp-low-millicelsius = <84500>; 4587 qcom,lmh-temp-high-millicelsius = <85000>; 4588 interrupt-controller; 4589 #interrupt-cells = <1>; 4590 }; 4591 4592 lmh_cluster0: lmh@18358800 { 4593 compatible = "qcom,sm8150-lmh"; 4594 reg = <0 0x18358800 0 0x400>; 4595 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 4596 cpus = <&cpu0>; 4597 qcom,lmh-temp-arm-millicelsius = <60000>; 4598 qcom,lmh-temp-low-millicelsius = <84500>; 4599 qcom,lmh-temp-high-millicelsius = <85000>; 4600 interrupt-controller; 4601 #interrupt-cells = <1>; 4602 }; 4603 4604 wifi: wifi@18800000 { 4605 compatible = "qcom,wcn3990-wifi"; 4606 reg = <0 0x18800000 0 0x800000>; 4607 reg-names = "membase"; 4608 memory-region = <&wlan_mem>; 4609 clock-names = "cxo_ref_clk_pin", "qdss"; 4610 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; 4611 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 4612 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 4613 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 4614 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 4615 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4616 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4617 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 4618 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4619 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4620 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4621 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4622 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 4623 iommus = <&apps_smmu 0x0640 0x1>; 4624 status = "disabled"; 4625 }; 4626 }; 4627 4628 timer { 4629 compatible = "arm,armv8-timer"; 4630 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4631 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4632 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4633 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4634 }; 4635 4636 thermal-zones { 4637 cpu0-thermal { 4638 polling-delay-passive = <250>; 4639 4640 thermal-sensors = <&tsens0 1>; 4641 4642 trips { 4643 cpu0_alert0: trip-point0 { 4644 temperature = <90000>; 4645 hysteresis = <2000>; 4646 type = "passive"; 4647 }; 4648 4649 cpu0_alert1: trip-point1 { 4650 temperature = <95000>; 4651 hysteresis = <2000>; 4652 type = "passive"; 4653 }; 4654 4655 cpu0_crit: cpu-crit { 4656 temperature = <110000>; 4657 hysteresis = <1000>; 4658 type = "critical"; 4659 }; 4660 }; 4661 4662 cooling-maps { 4663 map0 { 4664 trip = <&cpu0_alert0>; 4665 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4666 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4667 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4668 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4669 }; 4670 map1 { 4671 trip = <&cpu0_alert1>; 4672 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4673 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4674 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4675 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4676 }; 4677 }; 4678 }; 4679 4680 cpu1-thermal { 4681 polling-delay-passive = <250>; 4682 4683 thermal-sensors = <&tsens0 2>; 4684 4685 trips { 4686 cpu1_alert0: trip-point0 { 4687 temperature = <90000>; 4688 hysteresis = <2000>; 4689 type = "passive"; 4690 }; 4691 4692 cpu1_alert1: trip-point1 { 4693 temperature = <95000>; 4694 hysteresis = <2000>; 4695 type = "passive"; 4696 }; 4697 4698 cpu1_crit: cpu-crit { 4699 temperature = <110000>; 4700 hysteresis = <1000>; 4701 type = "critical"; 4702 }; 4703 }; 4704 4705 cooling-maps { 4706 map0 { 4707 trip = <&cpu1_alert0>; 4708 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4709 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4710 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4711 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4712 }; 4713 map1 { 4714 trip = <&cpu1_alert1>; 4715 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4716 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4717 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4718 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4719 }; 4720 }; 4721 }; 4722 4723 cpu2-thermal { 4724 polling-delay-passive = <250>; 4725 4726 thermal-sensors = <&tsens0 3>; 4727 4728 trips { 4729 cpu2_alert0: trip-point0 { 4730 temperature = <90000>; 4731 hysteresis = <2000>; 4732 type = "passive"; 4733 }; 4734 4735 cpu2_alert1: trip-point1 { 4736 temperature = <95000>; 4737 hysteresis = <2000>; 4738 type = "passive"; 4739 }; 4740 4741 cpu2_crit: cpu-crit { 4742 temperature = <110000>; 4743 hysteresis = <1000>; 4744 type = "critical"; 4745 }; 4746 }; 4747 4748 cooling-maps { 4749 map0 { 4750 trip = <&cpu2_alert0>; 4751 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4752 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4753 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4754 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4755 }; 4756 map1 { 4757 trip = <&cpu2_alert1>; 4758 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4759 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4760 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4761 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4762 }; 4763 }; 4764 }; 4765 4766 cpu3-thermal { 4767 polling-delay-passive = <250>; 4768 4769 thermal-sensors = <&tsens0 4>; 4770 4771 trips { 4772 cpu3_alert0: trip-point0 { 4773 temperature = <90000>; 4774 hysteresis = <2000>; 4775 type = "passive"; 4776 }; 4777 4778 cpu3_alert1: trip-point1 { 4779 temperature = <95000>; 4780 hysteresis = <2000>; 4781 type = "passive"; 4782 }; 4783 4784 cpu3_crit: cpu-crit { 4785 temperature = <110000>; 4786 hysteresis = <1000>; 4787 type = "critical"; 4788 }; 4789 }; 4790 4791 cooling-maps { 4792 map0 { 4793 trip = <&cpu3_alert0>; 4794 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4795 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4796 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4797 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4798 }; 4799 map1 { 4800 trip = <&cpu3_alert1>; 4801 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4802 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4803 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4804 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4805 }; 4806 }; 4807 }; 4808 4809 cpu4-top-thermal { 4810 polling-delay-passive = <250>; 4811 4812 thermal-sensors = <&tsens0 7>; 4813 4814 trips { 4815 cpu4_top_alert0: trip-point0 { 4816 temperature = <90000>; 4817 hysteresis = <2000>; 4818 type = "passive"; 4819 }; 4820 4821 cpu4_top_alert1: trip-point1 { 4822 temperature = <95000>; 4823 hysteresis = <2000>; 4824 type = "passive"; 4825 }; 4826 4827 cpu4_top_crit: cpu-crit { 4828 temperature = <110000>; 4829 hysteresis = <1000>; 4830 type = "critical"; 4831 }; 4832 }; 4833 4834 cooling-maps { 4835 map0 { 4836 trip = <&cpu4_top_alert0>; 4837 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4838 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4839 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4840 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4841 }; 4842 map1 { 4843 trip = <&cpu4_top_alert1>; 4844 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4845 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4846 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4847 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4848 }; 4849 }; 4850 }; 4851 4852 cpu5-top-thermal { 4853 polling-delay-passive = <250>; 4854 4855 thermal-sensors = <&tsens0 8>; 4856 4857 trips { 4858 cpu5_top_alert0: trip-point0 { 4859 temperature = <90000>; 4860 hysteresis = <2000>; 4861 type = "passive"; 4862 }; 4863 4864 cpu5_top_alert1: trip-point1 { 4865 temperature = <95000>; 4866 hysteresis = <2000>; 4867 type = "passive"; 4868 }; 4869 4870 cpu5_top_crit: cpu-crit { 4871 temperature = <110000>; 4872 hysteresis = <1000>; 4873 type = "critical"; 4874 }; 4875 }; 4876 4877 cooling-maps { 4878 map0 { 4879 trip = <&cpu5_top_alert0>; 4880 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4881 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4882 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4883 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4884 }; 4885 map1 { 4886 trip = <&cpu5_top_alert1>; 4887 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4888 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4889 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4890 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4891 }; 4892 }; 4893 }; 4894 4895 cpu6-top-thermal { 4896 polling-delay-passive = <250>; 4897 4898 thermal-sensors = <&tsens0 9>; 4899 4900 trips { 4901 cpu6_top_alert0: trip-point0 { 4902 temperature = <90000>; 4903 hysteresis = <2000>; 4904 type = "passive"; 4905 }; 4906 4907 cpu6_top_alert1: trip-point1 { 4908 temperature = <95000>; 4909 hysteresis = <2000>; 4910 type = "passive"; 4911 }; 4912 4913 cpu6_top_crit: cpu-crit { 4914 temperature = <110000>; 4915 hysteresis = <1000>; 4916 type = "critical"; 4917 }; 4918 }; 4919 4920 cooling-maps { 4921 map0 { 4922 trip = <&cpu6_top_alert0>; 4923 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4924 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4925 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4926 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4927 }; 4928 map1 { 4929 trip = <&cpu6_top_alert1>; 4930 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4931 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4932 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4933 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4934 }; 4935 }; 4936 }; 4937 4938 cpu7-top-thermal { 4939 polling-delay-passive = <250>; 4940 4941 thermal-sensors = <&tsens0 10>; 4942 4943 trips { 4944 cpu7_top_alert0: trip-point0 { 4945 temperature = <90000>; 4946 hysteresis = <2000>; 4947 type = "passive"; 4948 }; 4949 4950 cpu7_top_alert1: trip-point1 { 4951 temperature = <95000>; 4952 hysteresis = <2000>; 4953 type = "passive"; 4954 }; 4955 4956 cpu7_top_crit: cpu-crit { 4957 temperature = <110000>; 4958 hysteresis = <1000>; 4959 type = "critical"; 4960 }; 4961 }; 4962 4963 cooling-maps { 4964 map0 { 4965 trip = <&cpu7_top_alert0>; 4966 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4967 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4968 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4969 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4970 }; 4971 map1 { 4972 trip = <&cpu7_top_alert1>; 4973 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4974 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4975 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4976 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4977 }; 4978 }; 4979 }; 4980 4981 cpu4-bottom-thermal { 4982 polling-delay-passive = <250>; 4983 4984 thermal-sensors = <&tsens0 11>; 4985 4986 trips { 4987 cpu4_bottom_alert0: trip-point0 { 4988 temperature = <90000>; 4989 hysteresis = <2000>; 4990 type = "passive"; 4991 }; 4992 4993 cpu4_bottom_alert1: trip-point1 { 4994 temperature = <95000>; 4995 hysteresis = <2000>; 4996 type = "passive"; 4997 }; 4998 4999 cpu4_bottom_crit: cpu-crit { 5000 temperature = <110000>; 5001 hysteresis = <1000>; 5002 type = "critical"; 5003 }; 5004 }; 5005 5006 cooling-maps { 5007 map0 { 5008 trip = <&cpu4_bottom_alert0>; 5009 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5010 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5011 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5012 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5013 }; 5014 map1 { 5015 trip = <&cpu4_bottom_alert1>; 5016 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5017 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5018 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5019 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5020 }; 5021 }; 5022 }; 5023 5024 cpu5-bottom-thermal { 5025 polling-delay-passive = <250>; 5026 5027 thermal-sensors = <&tsens0 12>; 5028 5029 trips { 5030 cpu5_bottom_alert0: trip-point0 { 5031 temperature = <90000>; 5032 hysteresis = <2000>; 5033 type = "passive"; 5034 }; 5035 5036 cpu5_bottom_alert1: trip-point1 { 5037 temperature = <95000>; 5038 hysteresis = <2000>; 5039 type = "passive"; 5040 }; 5041 5042 cpu5_bottom_crit: cpu-crit { 5043 temperature = <110000>; 5044 hysteresis = <1000>; 5045 type = "critical"; 5046 }; 5047 }; 5048 5049 cooling-maps { 5050 map0 { 5051 trip = <&cpu5_bottom_alert0>; 5052 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5053 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5054 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5055 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5056 }; 5057 map1 { 5058 trip = <&cpu5_bottom_alert1>; 5059 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5060 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5061 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5062 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5063 }; 5064 }; 5065 }; 5066 5067 cpu6-bottom-thermal { 5068 polling-delay-passive = <250>; 5069 5070 thermal-sensors = <&tsens0 13>; 5071 5072 trips { 5073 cpu6_bottom_alert0: trip-point0 { 5074 temperature = <90000>; 5075 hysteresis = <2000>; 5076 type = "passive"; 5077 }; 5078 5079 cpu6_bottom_alert1: trip-point1 { 5080 temperature = <95000>; 5081 hysteresis = <2000>; 5082 type = "passive"; 5083 }; 5084 5085 cpu6_bottom_crit: cpu-crit { 5086 temperature = <110000>; 5087 hysteresis = <1000>; 5088 type = "critical"; 5089 }; 5090 }; 5091 5092 cooling-maps { 5093 map0 { 5094 trip = <&cpu6_bottom_alert0>; 5095 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5096 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5097 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5098 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5099 }; 5100 map1 { 5101 trip = <&cpu6_bottom_alert1>; 5102 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5103 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5104 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5105 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5106 }; 5107 }; 5108 }; 5109 5110 cpu7-bottom-thermal { 5111 polling-delay-passive = <250>; 5112 5113 thermal-sensors = <&tsens0 14>; 5114 5115 trips { 5116 cpu7_bottom_alert0: trip-point0 { 5117 temperature = <90000>; 5118 hysteresis = <2000>; 5119 type = "passive"; 5120 }; 5121 5122 cpu7_bottom_alert1: trip-point1 { 5123 temperature = <95000>; 5124 hysteresis = <2000>; 5125 type = "passive"; 5126 }; 5127 5128 cpu7_bottom_crit: cpu-crit { 5129 temperature = <110000>; 5130 hysteresis = <1000>; 5131 type = "critical"; 5132 }; 5133 }; 5134 5135 cooling-maps { 5136 map0 { 5137 trip = <&cpu7_bottom_alert0>; 5138 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5139 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5140 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5141 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5142 }; 5143 map1 { 5144 trip = <&cpu7_bottom_alert1>; 5145 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5146 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5147 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5148 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5149 }; 5150 }; 5151 }; 5152 5153 aoss0-thermal { 5154 polling-delay-passive = <250>; 5155 5156 thermal-sensors = <&tsens0 0>; 5157 5158 trips { 5159 aoss0_alert0: trip-point0 { 5160 temperature = <90000>; 5161 hysteresis = <2000>; 5162 type = "hot"; 5163 }; 5164 }; 5165 }; 5166 5167 cluster0-thermal { 5168 polling-delay-passive = <250>; 5169 5170 thermal-sensors = <&tsens0 5>; 5171 5172 trips { 5173 cluster0_alert0: trip-point0 { 5174 temperature = <90000>; 5175 hysteresis = <2000>; 5176 type = "hot"; 5177 }; 5178 cluster0_crit: cluster0-crit { 5179 temperature = <110000>; 5180 hysteresis = <2000>; 5181 type = "critical"; 5182 }; 5183 }; 5184 }; 5185 5186 cluster1-thermal { 5187 polling-delay-passive = <250>; 5188 5189 thermal-sensors = <&tsens0 6>; 5190 5191 trips { 5192 cluster1_alert0: trip-point0 { 5193 temperature = <90000>; 5194 hysteresis = <2000>; 5195 type = "hot"; 5196 }; 5197 cluster1_crit: cluster1-crit { 5198 temperature = <110000>; 5199 hysteresis = <2000>; 5200 type = "critical"; 5201 }; 5202 }; 5203 }; 5204 5205 gpu-top-thermal { 5206 polling-delay-passive = <250>; 5207 5208 thermal-sensors = <&tsens0 15>; 5209 5210 cooling-maps { 5211 map0 { 5212 trip = <&gpu_top_alert0>; 5213 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5214 }; 5215 }; 5216 5217 trips { 5218 gpu_top_alert0: trip-point0 { 5219 temperature = <85000>; 5220 hysteresis = <1000>; 5221 type = "passive"; 5222 }; 5223 5224 trip-point1 { 5225 temperature = <90000>; 5226 hysteresis = <1000>; 5227 type = "hot"; 5228 }; 5229 5230 trip-point2 { 5231 temperature = <110000>; 5232 hysteresis = <1000>; 5233 type = "critical"; 5234 }; 5235 }; 5236 }; 5237 5238 aoss1-thermal { 5239 polling-delay-passive = <250>; 5240 5241 thermal-sensors = <&tsens1 0>; 5242 5243 trips { 5244 aoss1_alert0: trip-point0 { 5245 temperature = <90000>; 5246 hysteresis = <2000>; 5247 type = "hot"; 5248 }; 5249 }; 5250 }; 5251 5252 wlan-thermal { 5253 polling-delay-passive = <250>; 5254 5255 thermal-sensors = <&tsens1 1>; 5256 5257 trips { 5258 wlan_alert0: trip-point0 { 5259 temperature = <90000>; 5260 hysteresis = <2000>; 5261 type = "hot"; 5262 }; 5263 }; 5264 }; 5265 5266 video-thermal { 5267 polling-delay-passive = <250>; 5268 5269 thermal-sensors = <&tsens1 2>; 5270 5271 trips { 5272 video_alert0: trip-point0 { 5273 temperature = <90000>; 5274 hysteresis = <2000>; 5275 type = "hot"; 5276 }; 5277 }; 5278 }; 5279 5280 mem-thermal { 5281 polling-delay-passive = <250>; 5282 5283 thermal-sensors = <&tsens1 3>; 5284 5285 trips { 5286 mem_alert0: trip-point0 { 5287 temperature = <90000>; 5288 hysteresis = <2000>; 5289 type = "hot"; 5290 }; 5291 }; 5292 }; 5293 5294 q6-hvx-thermal { 5295 polling-delay-passive = <250>; 5296 5297 thermal-sensors = <&tsens1 4>; 5298 5299 trips { 5300 q6_hvx_alert0: trip-point0 { 5301 temperature = <90000>; 5302 hysteresis = <2000>; 5303 type = "hot"; 5304 }; 5305 }; 5306 }; 5307 5308 camera-thermal { 5309 polling-delay-passive = <250>; 5310 5311 thermal-sensors = <&tsens1 5>; 5312 5313 trips { 5314 camera_alert0: trip-point0 { 5315 temperature = <90000>; 5316 hysteresis = <2000>; 5317 type = "hot"; 5318 }; 5319 }; 5320 }; 5321 5322 compute-thermal { 5323 polling-delay-passive = <250>; 5324 5325 thermal-sensors = <&tsens1 6>; 5326 5327 trips { 5328 compute_alert0: trip-point0 { 5329 temperature = <90000>; 5330 hysteresis = <2000>; 5331 type = "hot"; 5332 }; 5333 }; 5334 }; 5335 5336 modem-thermal { 5337 polling-delay-passive = <250>; 5338 5339 thermal-sensors = <&tsens1 7>; 5340 5341 trips { 5342 modem_alert0: trip-point0 { 5343 temperature = <90000>; 5344 hysteresis = <2000>; 5345 type = "hot"; 5346 }; 5347 }; 5348 }; 5349 5350 npu-thermal { 5351 polling-delay-passive = <250>; 5352 5353 thermal-sensors = <&tsens1 8>; 5354 5355 trips { 5356 npu_alert0: trip-point0 { 5357 temperature = <90000>; 5358 hysteresis = <2000>; 5359 type = "hot"; 5360 }; 5361 }; 5362 }; 5363 5364 modem-vec-thermal { 5365 polling-delay-passive = <250>; 5366 5367 thermal-sensors = <&tsens1 9>; 5368 5369 trips { 5370 modem_vec_alert0: trip-point0 { 5371 temperature = <90000>; 5372 hysteresis = <2000>; 5373 type = "hot"; 5374 }; 5375 }; 5376 }; 5377 5378 modem-scl-thermal { 5379 polling-delay-passive = <250>; 5380 5381 thermal-sensors = <&tsens1 10>; 5382 5383 trips { 5384 modem_scl_alert0: trip-point0 { 5385 temperature = <90000>; 5386 hysteresis = <2000>; 5387 type = "hot"; 5388 }; 5389 }; 5390 }; 5391 5392 gpu-bottom-thermal { 5393 polling-delay-passive = <250>; 5394 5395 thermal-sensors = <&tsens1 11>; 5396 5397 cooling-maps { 5398 map0 { 5399 trip = <&gpu_bottom_alert0>; 5400 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5401 }; 5402 }; 5403 5404 trips { 5405 gpu_bottom_alert0: trip-point0 { 5406 temperature = <85000>; 5407 hysteresis = <1000>; 5408 type = "passive"; 5409 }; 5410 5411 trip-point1 { 5412 temperature = <90000>; 5413 hysteresis = <1000>; 5414 type = "hot"; 5415 }; 5416 5417 trip-point2 { 5418 temperature = <110000>; 5419 hysteresis = <1000>; 5420 type = "critical"; 5421 }; 5422 }; 5423 }; 5424 }; 5425}; 5426