1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2019, Linaro Limited 5 */ 6 7#include <dt-bindings/dma/qcom-gpi.h> 8#include <dt-bindings/firmware/qcom,scm.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/phy/phy-qcom-qmp.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/soc/qcom,rpmh-rsc.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,dispcc-sm8150.h> 15#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 16#include <dt-bindings/clock/qcom,gcc-sm8150.h> 17#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 18#include <dt-bindings/clock/qcom,videocc-sm8150.h> 19#include <dt-bindings/interconnect/qcom,osm-l3.h> 20#include <dt-bindings/interconnect/qcom,sm8150.h> 21#include <dt-bindings/clock/qcom,sm8150-camcc.h> 22#include <dt-bindings/thermal/thermal.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 chosen { }; 31 32 clocks { 33 xo_board: xo-board { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <38400000>; 37 clock-output-names = "xo_board"; 38 }; 39 40 sleep_clk: sleep-clk { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <32764>; 44 clock-output-names = "sleep_clk"; 45 }; 46 }; 47 48 cpus { 49 #address-cells = <2>; 50 #size-cells = <0>; 51 52 cpu0: cpu@0 { 53 device_type = "cpu"; 54 compatible = "qcom,kryo485"; 55 reg = <0x0 0x0>; 56 clocks = <&cpufreq_hw 0>; 57 enable-method = "psci"; 58 capacity-dmips-mhz = <488>; 59 dynamic-power-coefficient = <232>; 60 next-level-cache = <&l2_0>; 61 qcom,freq-domain = <&cpufreq_hw 0>; 62 operating-points-v2 = <&cpu0_opp_table>; 63 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 64 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 65 power-domains = <&cpu_pd0>; 66 power-domain-names = "psci"; 67 #cooling-cells = <2>; 68 l2_0: l2-cache { 69 compatible = "cache"; 70 cache-level = <2>; 71 cache-unified; 72 next-level-cache = <&l3_0>; 73 l3_0: l3-cache { 74 compatible = "cache"; 75 cache-level = <3>; 76 cache-unified; 77 }; 78 }; 79 }; 80 81 cpu1: cpu@100 { 82 device_type = "cpu"; 83 compatible = "qcom,kryo485"; 84 reg = <0x0 0x100>; 85 clocks = <&cpufreq_hw 0>; 86 enable-method = "psci"; 87 capacity-dmips-mhz = <488>; 88 dynamic-power-coefficient = <232>; 89 next-level-cache = <&l2_100>; 90 qcom,freq-domain = <&cpufreq_hw 0>; 91 operating-points-v2 = <&cpu0_opp_table>; 92 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 93 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 94 power-domains = <&cpu_pd1>; 95 power-domain-names = "psci"; 96 #cooling-cells = <2>; 97 l2_100: l2-cache { 98 compatible = "cache"; 99 cache-level = <2>; 100 cache-unified; 101 next-level-cache = <&l3_0>; 102 }; 103 }; 104 105 cpu2: cpu@200 { 106 device_type = "cpu"; 107 compatible = "qcom,kryo485"; 108 reg = <0x0 0x200>; 109 clocks = <&cpufreq_hw 0>; 110 enable-method = "psci"; 111 capacity-dmips-mhz = <488>; 112 dynamic-power-coefficient = <232>; 113 next-level-cache = <&l2_200>; 114 qcom,freq-domain = <&cpufreq_hw 0>; 115 operating-points-v2 = <&cpu0_opp_table>; 116 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 117 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 118 power-domains = <&cpu_pd2>; 119 power-domain-names = "psci"; 120 #cooling-cells = <2>; 121 l2_200: l2-cache { 122 compatible = "cache"; 123 cache-level = <2>; 124 cache-unified; 125 next-level-cache = <&l3_0>; 126 }; 127 }; 128 129 cpu3: cpu@300 { 130 device_type = "cpu"; 131 compatible = "qcom,kryo485"; 132 reg = <0x0 0x300>; 133 clocks = <&cpufreq_hw 0>; 134 enable-method = "psci"; 135 capacity-dmips-mhz = <488>; 136 dynamic-power-coefficient = <232>; 137 next-level-cache = <&l2_300>; 138 qcom,freq-domain = <&cpufreq_hw 0>; 139 operating-points-v2 = <&cpu0_opp_table>; 140 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 141 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 142 power-domains = <&cpu_pd3>; 143 power-domain-names = "psci"; 144 #cooling-cells = <2>; 145 l2_300: l2-cache { 146 compatible = "cache"; 147 cache-level = <2>; 148 cache-unified; 149 next-level-cache = <&l3_0>; 150 }; 151 }; 152 153 cpu4: cpu@400 { 154 device_type = "cpu"; 155 compatible = "qcom,kryo485"; 156 reg = <0x0 0x400>; 157 clocks = <&cpufreq_hw 1>; 158 enable-method = "psci"; 159 capacity-dmips-mhz = <1024>; 160 dynamic-power-coefficient = <369>; 161 next-level-cache = <&l2_400>; 162 qcom,freq-domain = <&cpufreq_hw 1>; 163 operating-points-v2 = <&cpu4_opp_table>; 164 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 165 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 166 power-domains = <&cpu_pd4>; 167 power-domain-names = "psci"; 168 #cooling-cells = <2>; 169 l2_400: l2-cache { 170 compatible = "cache"; 171 cache-level = <2>; 172 cache-unified; 173 next-level-cache = <&l3_0>; 174 }; 175 }; 176 177 cpu5: cpu@500 { 178 device_type = "cpu"; 179 compatible = "qcom,kryo485"; 180 reg = <0x0 0x500>; 181 clocks = <&cpufreq_hw 1>; 182 enable-method = "psci"; 183 capacity-dmips-mhz = <1024>; 184 dynamic-power-coefficient = <369>; 185 next-level-cache = <&l2_500>; 186 qcom,freq-domain = <&cpufreq_hw 1>; 187 operating-points-v2 = <&cpu4_opp_table>; 188 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 189 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 190 power-domains = <&cpu_pd5>; 191 power-domain-names = "psci"; 192 #cooling-cells = <2>; 193 l2_500: l2-cache { 194 compatible = "cache"; 195 cache-level = <2>; 196 cache-unified; 197 next-level-cache = <&l3_0>; 198 }; 199 }; 200 201 cpu6: cpu@600 { 202 device_type = "cpu"; 203 compatible = "qcom,kryo485"; 204 reg = <0x0 0x600>; 205 clocks = <&cpufreq_hw 1>; 206 enable-method = "psci"; 207 capacity-dmips-mhz = <1024>; 208 dynamic-power-coefficient = <369>; 209 next-level-cache = <&l2_600>; 210 qcom,freq-domain = <&cpufreq_hw 1>; 211 operating-points-v2 = <&cpu4_opp_table>; 212 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 213 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 214 power-domains = <&cpu_pd6>; 215 power-domain-names = "psci"; 216 #cooling-cells = <2>; 217 l2_600: l2-cache { 218 compatible = "cache"; 219 cache-level = <2>; 220 cache-unified; 221 next-level-cache = <&l3_0>; 222 }; 223 }; 224 225 cpu7: cpu@700 { 226 device_type = "cpu"; 227 compatible = "qcom,kryo485"; 228 reg = <0x0 0x700>; 229 clocks = <&cpufreq_hw 2>; 230 enable-method = "psci"; 231 capacity-dmips-mhz = <1024>; 232 dynamic-power-coefficient = <421>; 233 next-level-cache = <&l2_700>; 234 qcom,freq-domain = <&cpufreq_hw 2>; 235 operating-points-v2 = <&cpu7_opp_table>; 236 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 237 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 238 power-domains = <&cpu_pd7>; 239 power-domain-names = "psci"; 240 #cooling-cells = <2>; 241 l2_700: l2-cache { 242 compatible = "cache"; 243 cache-level = <2>; 244 cache-unified; 245 next-level-cache = <&l3_0>; 246 }; 247 }; 248 249 cpu-map { 250 cluster0 { 251 core0 { 252 cpu = <&cpu0>; 253 }; 254 255 core1 { 256 cpu = <&cpu1>; 257 }; 258 259 core2 { 260 cpu = <&cpu2>; 261 }; 262 263 core3 { 264 cpu = <&cpu3>; 265 }; 266 267 core4 { 268 cpu = <&cpu4>; 269 }; 270 271 core5 { 272 cpu = <&cpu5>; 273 }; 274 275 core6 { 276 cpu = <&cpu6>; 277 }; 278 279 core7 { 280 cpu = <&cpu7>; 281 }; 282 }; 283 }; 284 285 idle-states { 286 entry-method = "psci"; 287 288 little_cpu_sleep_0: cpu-sleep-0-0 { 289 compatible = "arm,idle-state"; 290 idle-state-name = "little-rail-power-collapse"; 291 arm,psci-suspend-param = <0x40000004>; 292 entry-latency-us = <355>; 293 exit-latency-us = <909>; 294 min-residency-us = <3934>; 295 local-timer-stop; 296 }; 297 298 big_cpu_sleep_0: cpu-sleep-1-0 { 299 compatible = "arm,idle-state"; 300 idle-state-name = "big-rail-power-collapse"; 301 arm,psci-suspend-param = <0x40000004>; 302 entry-latency-us = <241>; 303 exit-latency-us = <1461>; 304 min-residency-us = <4488>; 305 local-timer-stop; 306 }; 307 }; 308 309 domain-idle-states { 310 cluster_sleep_0: cluster-sleep-0 { 311 compatible = "domain-idle-state"; 312 arm,psci-suspend-param = <0x4100c244>; 313 entry-latency-us = <3263>; 314 exit-latency-us = <6562>; 315 min-residency-us = <9987>; 316 }; 317 }; 318 }; 319 320 cpu0_opp_table: opp-table-cpu0 { 321 compatible = "operating-points-v2"; 322 opp-shared; 323 324 cpu0_opp1: opp-300000000 { 325 opp-hz = /bits/ 64 <300000000>; 326 opp-peak-kBps = <800000 9600000>; 327 }; 328 329 cpu0_opp2: opp-403200000 { 330 opp-hz = /bits/ 64 <403200000>; 331 opp-peak-kBps = <800000 9600000>; 332 }; 333 334 cpu0_opp3: opp-499200000 { 335 opp-hz = /bits/ 64 <499200000>; 336 opp-peak-kBps = <800000 12902400>; 337 }; 338 339 cpu0_opp4: opp-576000000 { 340 opp-hz = /bits/ 64 <576000000>; 341 opp-peak-kBps = <800000 12902400>; 342 }; 343 344 cpu0_opp5: opp-672000000 { 345 opp-hz = /bits/ 64 <672000000>; 346 opp-peak-kBps = <800000 15974400>; 347 }; 348 349 cpu0_opp6: opp-768000000 { 350 opp-hz = /bits/ 64 <768000000>; 351 opp-peak-kBps = <1804000 19660800>; 352 }; 353 354 cpu0_opp7: opp-844800000 { 355 opp-hz = /bits/ 64 <844800000>; 356 opp-peak-kBps = <1804000 19660800>; 357 }; 358 359 cpu0_opp8: opp-940800000 { 360 opp-hz = /bits/ 64 <940800000>; 361 opp-peak-kBps = <1804000 22732800>; 362 }; 363 364 cpu0_opp9: opp-1036800000 { 365 opp-hz = /bits/ 64 <1036800000>; 366 opp-peak-kBps = <1804000 22732800>; 367 }; 368 369 cpu0_opp10: opp-1113600000 { 370 opp-hz = /bits/ 64 <1113600000>; 371 opp-peak-kBps = <2188000 25804800>; 372 }; 373 374 cpu0_opp11: opp-1209600000 { 375 opp-hz = /bits/ 64 <1209600000>; 376 opp-peak-kBps = <2188000 31948800>; 377 }; 378 379 cpu0_opp12: opp-1305600000 { 380 opp-hz = /bits/ 64 <1305600000>; 381 opp-peak-kBps = <3072000 31948800>; 382 }; 383 384 cpu0_opp13: opp-1382400000 { 385 opp-hz = /bits/ 64 <1382400000>; 386 opp-peak-kBps = <3072000 31948800>; 387 }; 388 389 cpu0_opp14: opp-1478400000 { 390 opp-hz = /bits/ 64 <1478400000>; 391 opp-peak-kBps = <3072000 31948800>; 392 }; 393 394 cpu0_opp15: opp-1555200000 { 395 opp-hz = /bits/ 64 <1555200000>; 396 opp-peak-kBps = <3072000 40550400>; 397 }; 398 399 cpu0_opp16: opp-1632000000 { 400 opp-hz = /bits/ 64 <1632000000>; 401 opp-peak-kBps = <3072000 40550400>; 402 }; 403 404 cpu0_opp17: opp-1708800000 { 405 opp-hz = /bits/ 64 <1708800000>; 406 opp-peak-kBps = <3072000 43008000>; 407 }; 408 409 cpu0_opp18: opp-1785600000 { 410 opp-hz = /bits/ 64 <1785600000>; 411 opp-peak-kBps = <3072000 43008000>; 412 }; 413 }; 414 415 cpu4_opp_table: opp-table-cpu4 { 416 compatible = "operating-points-v2"; 417 opp-shared; 418 419 cpu4_opp1: opp-710400000 { 420 opp-hz = /bits/ 64 <710400000>; 421 opp-peak-kBps = <1804000 15974400>; 422 }; 423 424 cpu4_opp2: opp-825600000 { 425 opp-hz = /bits/ 64 <825600000>; 426 opp-peak-kBps = <2188000 19660800>; 427 }; 428 429 cpu4_opp3: opp-940800000 { 430 opp-hz = /bits/ 64 <940800000>; 431 opp-peak-kBps = <2188000 22732800>; 432 }; 433 434 cpu4_opp4: opp-1056000000 { 435 opp-hz = /bits/ 64 <1056000000>; 436 opp-peak-kBps = <3072000 25804800>; 437 }; 438 439 cpu4_opp5: opp-1171200000 { 440 opp-hz = /bits/ 64 <1171200000>; 441 opp-peak-kBps = <3072000 31948800>; 442 }; 443 444 cpu4_opp6: opp-1286400000 { 445 opp-hz = /bits/ 64 <1286400000>; 446 opp-peak-kBps = <4068000 31948800>; 447 }; 448 449 cpu4_opp7: opp-1401600000 { 450 opp-hz = /bits/ 64 <1401600000>; 451 opp-peak-kBps = <4068000 31948800>; 452 }; 453 454 cpu4_opp8: opp-1497600000 { 455 opp-hz = /bits/ 64 <1497600000>; 456 opp-peak-kBps = <4068000 40550400>; 457 }; 458 459 cpu4_opp9: opp-1612800000 { 460 opp-hz = /bits/ 64 <1612800000>; 461 opp-peak-kBps = <4068000 40550400>; 462 }; 463 464 cpu4_opp10: opp-1708800000 { 465 opp-hz = /bits/ 64 <1708800000>; 466 opp-peak-kBps = <4068000 43008000>; 467 }; 468 469 cpu4_opp11: opp-1804800000 { 470 opp-hz = /bits/ 64 <1804800000>; 471 opp-peak-kBps = <6220000 43008000>; 472 }; 473 474 cpu4_opp12: opp-1920000000 { 475 opp-hz = /bits/ 64 <1920000000>; 476 opp-peak-kBps = <6220000 49152000>; 477 }; 478 479 cpu4_opp13: opp-2016000000 { 480 opp-hz = /bits/ 64 <2016000000>; 481 opp-peak-kBps = <7216000 49152000>; 482 }; 483 484 cpu4_opp14: opp-2131200000 { 485 opp-hz = /bits/ 64 <2131200000>; 486 opp-peak-kBps = <8368000 49152000>; 487 }; 488 489 cpu4_opp15: opp-2227200000 { 490 opp-hz = /bits/ 64 <2227200000>; 491 opp-peak-kBps = <8368000 51609600>; 492 }; 493 494 cpu4_opp16: opp-2323200000 { 495 opp-hz = /bits/ 64 <2323200000>; 496 opp-peak-kBps = <8368000 51609600>; 497 }; 498 499 cpu4_opp17: opp-2419200000 { 500 opp-hz = /bits/ 64 <2419200000>; 501 opp-peak-kBps = <8368000 51609600>; 502 }; 503 }; 504 505 cpu7_opp_table: opp-table-cpu7 { 506 compatible = "operating-points-v2"; 507 opp-shared; 508 509 cpu7_opp1: opp-825600000 { 510 opp-hz = /bits/ 64 <825600000>; 511 opp-peak-kBps = <2188000 19660800>; 512 }; 513 514 cpu7_opp2: opp-940800000 { 515 opp-hz = /bits/ 64 <940800000>; 516 opp-peak-kBps = <2188000 22732800>; 517 }; 518 519 cpu7_opp3: opp-1056000000 { 520 opp-hz = /bits/ 64 <1056000000>; 521 opp-peak-kBps = <3072000 25804800>; 522 }; 523 524 cpu7_opp4: opp-1171200000 { 525 opp-hz = /bits/ 64 <1171200000>; 526 opp-peak-kBps = <3072000 31948800>; 527 }; 528 529 cpu7_opp5: opp-1286400000 { 530 opp-hz = /bits/ 64 <1286400000>; 531 opp-peak-kBps = <4068000 31948800>; 532 }; 533 534 cpu7_opp6: opp-1401600000 { 535 opp-hz = /bits/ 64 <1401600000>; 536 opp-peak-kBps = <4068000 31948800>; 537 }; 538 539 cpu7_opp7: opp-1497600000 { 540 opp-hz = /bits/ 64 <1497600000>; 541 opp-peak-kBps = <4068000 40550400>; 542 }; 543 544 cpu7_opp8: opp-1612800000 { 545 opp-hz = /bits/ 64 <1612800000>; 546 opp-peak-kBps = <4068000 40550400>; 547 }; 548 549 cpu7_opp9: opp-1708800000 { 550 opp-hz = /bits/ 64 <1708800000>; 551 opp-peak-kBps = <4068000 43008000>; 552 }; 553 554 cpu7_opp10: opp-1804800000 { 555 opp-hz = /bits/ 64 <1804800000>; 556 opp-peak-kBps = <6220000 43008000>; 557 }; 558 559 cpu7_opp11: opp-1920000000 { 560 opp-hz = /bits/ 64 <1920000000>; 561 opp-peak-kBps = <6220000 49152000>; 562 }; 563 564 cpu7_opp12: opp-2016000000 { 565 opp-hz = /bits/ 64 <2016000000>; 566 opp-peak-kBps = <7216000 49152000>; 567 }; 568 569 cpu7_opp13: opp-2131200000 { 570 opp-hz = /bits/ 64 <2131200000>; 571 opp-peak-kBps = <8368000 49152000>; 572 }; 573 574 cpu7_opp14: opp-2227200000 { 575 opp-hz = /bits/ 64 <2227200000>; 576 opp-peak-kBps = <8368000 51609600>; 577 }; 578 579 cpu7_opp15: opp-2323200000 { 580 opp-hz = /bits/ 64 <2323200000>; 581 opp-peak-kBps = <8368000 51609600>; 582 }; 583 584 cpu7_opp16: opp-2419200000 { 585 opp-hz = /bits/ 64 <2419200000>; 586 opp-peak-kBps = <8368000 51609600>; 587 }; 588 589 cpu7_opp17: opp-2534400000 { 590 opp-hz = /bits/ 64 <2534400000>; 591 opp-peak-kBps = <8368000 51609600>; 592 }; 593 594 cpu7_opp18: opp-2649600000 { 595 opp-hz = /bits/ 64 <2649600000>; 596 opp-peak-kBps = <8368000 51609600>; 597 }; 598 599 cpu7_opp19: opp-2745600000 { 600 opp-hz = /bits/ 64 <2745600000>; 601 opp-peak-kBps = <8368000 51609600>; 602 }; 603 604 cpu7_opp20: opp-2841600000 { 605 opp-hz = /bits/ 64 <2841600000>; 606 opp-peak-kBps = <8368000 51609600>; 607 }; 608 }; 609 610 firmware { 611 scm: scm { 612 compatible = "qcom,scm-sm8150", "qcom,scm"; 613 #reset-cells = <1>; 614 }; 615 }; 616 617 memory@80000000 { 618 device_type = "memory"; 619 /* We expect the bootloader to fill in the size */ 620 reg = <0x0 0x80000000 0x0 0x0>; 621 }; 622 623 pmu { 624 compatible = "arm,armv8-pmuv3"; 625 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 626 }; 627 628 psci { 629 compatible = "arm,psci-1.0"; 630 method = "smc"; 631 632 cpu_pd0: power-domain-cpu0 { 633 #power-domain-cells = <0>; 634 power-domains = <&cluster_pd>; 635 domain-idle-states = <&little_cpu_sleep_0>; 636 }; 637 638 cpu_pd1: power-domain-cpu1 { 639 #power-domain-cells = <0>; 640 power-domains = <&cluster_pd>; 641 domain-idle-states = <&little_cpu_sleep_0>; 642 }; 643 644 cpu_pd2: power-domain-cpu2 { 645 #power-domain-cells = <0>; 646 power-domains = <&cluster_pd>; 647 domain-idle-states = <&little_cpu_sleep_0>; 648 }; 649 650 cpu_pd3: power-domain-cpu3 { 651 #power-domain-cells = <0>; 652 power-domains = <&cluster_pd>; 653 domain-idle-states = <&little_cpu_sleep_0>; 654 }; 655 656 cpu_pd4: power-domain-cpu4 { 657 #power-domain-cells = <0>; 658 power-domains = <&cluster_pd>; 659 domain-idle-states = <&big_cpu_sleep_0>; 660 }; 661 662 cpu_pd5: power-domain-cpu5 { 663 #power-domain-cells = <0>; 664 power-domains = <&cluster_pd>; 665 domain-idle-states = <&big_cpu_sleep_0>; 666 }; 667 668 cpu_pd6: power-domain-cpu6 { 669 #power-domain-cells = <0>; 670 power-domains = <&cluster_pd>; 671 domain-idle-states = <&big_cpu_sleep_0>; 672 }; 673 674 cpu_pd7: power-domain-cpu7 { 675 #power-domain-cells = <0>; 676 power-domains = <&cluster_pd>; 677 domain-idle-states = <&big_cpu_sleep_0>; 678 }; 679 680 cluster_pd: power-domain-cpu-cluster0 { 681 #power-domain-cells = <0>; 682 domain-idle-states = <&cluster_sleep_0>; 683 }; 684 }; 685 686 reserved-memory { 687 #address-cells = <2>; 688 #size-cells = <2>; 689 ranges; 690 691 hyp_mem: memory@85700000 { 692 reg = <0x0 0x85700000 0x0 0x600000>; 693 no-map; 694 }; 695 696 xbl_mem: memory@85d00000 { 697 reg = <0x0 0x85d00000 0x0 0x140000>; 698 no-map; 699 }; 700 701 aop_mem: memory@85f00000 { 702 reg = <0x0 0x85f00000 0x0 0x20000>; 703 no-map; 704 }; 705 706 aop_cmd_db: memory@85f20000 { 707 compatible = "qcom,cmd-db"; 708 reg = <0x0 0x85f20000 0x0 0x20000>; 709 no-map; 710 }; 711 712 smem_mem: memory@86000000 { 713 reg = <0x0 0x86000000 0x0 0x200000>; 714 no-map; 715 }; 716 717 tz_mem: memory@86200000 { 718 reg = <0x0 0x86200000 0x0 0x3900000>; 719 no-map; 720 }; 721 722 rmtfs_mem: memory@89b00000 { 723 compatible = "qcom,rmtfs-mem"; 724 reg = <0x0 0x89b00000 0x0 0x200000>; 725 no-map; 726 727 qcom,client-id = <1>; 728 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 729 }; 730 731 camera_mem: memory@8b700000 { 732 reg = <0x0 0x8b700000 0x0 0x500000>; 733 no-map; 734 }; 735 736 wlan_mem: memory@8bc00000 { 737 reg = <0x0 0x8bc00000 0x0 0x180000>; 738 no-map; 739 }; 740 741 npu_mem: memory@8bd80000 { 742 reg = <0x0 0x8bd80000 0x0 0x80000>; 743 no-map; 744 }; 745 746 adsp_mem: memory@8be00000 { 747 reg = <0x0 0x8be00000 0x0 0x1a00000>; 748 no-map; 749 }; 750 751 mpss_mem: memory@8d800000 { 752 reg = <0x0 0x8d800000 0x0 0x9600000>; 753 no-map; 754 }; 755 756 venus_mem: memory@96e00000 { 757 reg = <0x0 0x96e00000 0x0 0x500000>; 758 no-map; 759 }; 760 761 slpi_mem: memory@97300000 { 762 reg = <0x0 0x97300000 0x0 0x1400000>; 763 no-map; 764 }; 765 766 ipa_fw_mem: memory@98700000 { 767 reg = <0x0 0x98700000 0x0 0x10000>; 768 no-map; 769 }; 770 771 ipa_gsi_mem: memory@98710000 { 772 reg = <0x0 0x98710000 0x0 0x5000>; 773 no-map; 774 }; 775 776 gpu_mem: memory@98715000 { 777 reg = <0x0 0x98715000 0x0 0x2000>; 778 no-map; 779 }; 780 781 spss_mem: memory@98800000 { 782 reg = <0x0 0x98800000 0x0 0x100000>; 783 no-map; 784 }; 785 786 cdsp_mem: memory@98900000 { 787 reg = <0x0 0x98900000 0x0 0x1400000>; 788 no-map; 789 }; 790 791 qseecom_mem: memory@9e400000 { 792 reg = <0x0 0x9e400000 0x0 0x1400000>; 793 no-map; 794 }; 795 }; 796 797 smem { 798 compatible = "qcom,smem"; 799 memory-region = <&smem_mem>; 800 hwlocks = <&tcsr_mutex 3>; 801 }; 802 803 smp2p-cdsp { 804 compatible = "qcom,smp2p"; 805 qcom,smem = <94>, <432>; 806 807 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 808 809 mboxes = <&apss_shared 6>; 810 811 qcom,local-pid = <0>; 812 qcom,remote-pid = <5>; 813 814 cdsp_smp2p_out: master-kernel { 815 qcom,entry-name = "master-kernel"; 816 #qcom,smem-state-cells = <1>; 817 }; 818 819 cdsp_smp2p_in: slave-kernel { 820 qcom,entry-name = "slave-kernel"; 821 822 interrupt-controller; 823 #interrupt-cells = <2>; 824 }; 825 }; 826 827 smp2p-lpass { 828 compatible = "qcom,smp2p"; 829 qcom,smem = <443>, <429>; 830 831 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 832 833 mboxes = <&apss_shared 10>; 834 835 qcom,local-pid = <0>; 836 qcom,remote-pid = <2>; 837 838 adsp_smp2p_out: master-kernel { 839 qcom,entry-name = "master-kernel"; 840 #qcom,smem-state-cells = <1>; 841 }; 842 843 adsp_smp2p_in: slave-kernel { 844 qcom,entry-name = "slave-kernel"; 845 846 interrupt-controller; 847 #interrupt-cells = <2>; 848 }; 849 }; 850 851 smp2p-mpss { 852 compatible = "qcom,smp2p"; 853 qcom,smem = <435>, <428>; 854 855 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 856 857 mboxes = <&apss_shared 14>; 858 859 qcom,local-pid = <0>; 860 qcom,remote-pid = <1>; 861 862 modem_smp2p_out: master-kernel { 863 qcom,entry-name = "master-kernel"; 864 #qcom,smem-state-cells = <1>; 865 }; 866 867 modem_smp2p_in: slave-kernel { 868 qcom,entry-name = "slave-kernel"; 869 870 interrupt-controller; 871 #interrupt-cells = <2>; 872 }; 873 }; 874 875 smp2p-slpi { 876 compatible = "qcom,smp2p"; 877 qcom,smem = <481>, <430>; 878 879 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 880 881 mboxes = <&apss_shared 26>; 882 883 qcom,local-pid = <0>; 884 qcom,remote-pid = <3>; 885 886 slpi_smp2p_out: master-kernel { 887 qcom,entry-name = "master-kernel"; 888 #qcom,smem-state-cells = <1>; 889 }; 890 891 slpi_smp2p_in: slave-kernel { 892 qcom,entry-name = "slave-kernel"; 893 894 interrupt-controller; 895 #interrupt-cells = <2>; 896 }; 897 }; 898 899 soc: soc@0 { 900 #address-cells = <2>; 901 #size-cells = <2>; 902 ranges = <0 0 0 0 0x10 0>; 903 dma-ranges = <0 0 0 0 0x10 0>; 904 compatible = "simple-bus"; 905 906 gcc: clock-controller@100000 { 907 compatible = "qcom,gcc-sm8150"; 908 reg = <0x0 0x00100000 0x0 0x1f0000>; 909 #clock-cells = <1>; 910 #reset-cells = <1>; 911 #power-domain-cells = <1>; 912 clock-names = "bi_tcxo", 913 "sleep_clk"; 914 clocks = <&rpmhcc RPMH_CXO_CLK>, 915 <&sleep_clk>; 916 }; 917 918 gpi_dma0: dma-controller@800000 { 919 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 920 reg = <0 0x00800000 0 0x60000>; 921 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 922 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 923 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 934 dma-channels = <13>; 935 dma-channel-mask = <0xfa>; 936 iommus = <&apps_smmu 0x00d6 0x0>; 937 #dma-cells = <3>; 938 status = "disabled"; 939 }; 940 941 ethernet: ethernet@20000 { 942 compatible = "qcom,sm8150-ethqos"; 943 reg = <0x0 0x00020000 0x0 0x10000>, 944 <0x0 0x00036000 0x0 0x100>; 945 reg-names = "stmmaceth", "rgmii"; 946 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; 947 clocks = <&gcc GCC_EMAC_AXI_CLK>, 948 <&gcc GCC_EMAC_SLV_AHB_CLK>, 949 <&gcc GCC_EMAC_PTP_CLK>, 950 <&gcc GCC_EMAC_RGMII_CLK>; 951 interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; 953 interrupt-names = "macirq", "eth_lpi"; 954 955 power-domains = <&gcc EMAC_GDSC>; 956 resets = <&gcc GCC_EMAC_BCR>; 957 958 iommus = <&apps_smmu 0x3c0 0x0>; 959 960 snps,tso; 961 rx-fifo-depth = <4096>; 962 tx-fifo-depth = <4096>; 963 964 status = "disabled"; 965 }; 966 967 qfprom: efuse@784000 { 968 compatible = "qcom,sm8150-qfprom", "qcom,qfprom"; 969 reg = <0 0x00784000 0 0x8ff>; 970 #address-cells = <1>; 971 #size-cells = <1>; 972 973 gpu_speed_bin: gpu-speed-bin@133 { 974 reg = <0x133 0x1>; 975 bits = <5 3>; 976 }; 977 }; 978 979 qupv3_id_0: geniqup@8c0000 { 980 compatible = "qcom,geni-se-qup"; 981 reg = <0x0 0x008c0000 0x0 0x6000>; 982 clock-names = "m-ahb", "s-ahb"; 983 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 984 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 985 iommus = <&apps_smmu 0xc3 0x0>; 986 #address-cells = <2>; 987 #size-cells = <2>; 988 ranges; 989 status = "disabled"; 990 991 i2c0: i2c@880000 { 992 compatible = "qcom,geni-i2c"; 993 reg = <0 0x00880000 0 0x4000>; 994 clock-names = "se"; 995 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 996 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 997 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 998 dma-names = "tx", "rx"; 999 pinctrl-names = "default"; 1000 pinctrl-0 = <&qup_i2c0_default>; 1001 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1002 #address-cells = <1>; 1003 #size-cells = <0>; 1004 status = "disabled"; 1005 }; 1006 1007 spi0: spi@880000 { 1008 compatible = "qcom,geni-spi"; 1009 reg = <0 0x00880000 0 0x4000>; 1010 reg-names = "se"; 1011 clock-names = "se"; 1012 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1013 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1014 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1015 dma-names = "tx", "rx"; 1016 pinctrl-names = "default"; 1017 pinctrl-0 = <&qup_spi0_default>; 1018 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1019 spi-max-frequency = <50000000>; 1020 #address-cells = <1>; 1021 #size-cells = <0>; 1022 status = "disabled"; 1023 }; 1024 1025 i2c1: i2c@884000 { 1026 compatible = "qcom,geni-i2c"; 1027 reg = <0 0x00884000 0 0x4000>; 1028 clock-names = "se"; 1029 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1030 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1031 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1032 dma-names = "tx", "rx"; 1033 pinctrl-names = "default"; 1034 pinctrl-0 = <&qup_i2c1_default>; 1035 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1036 #address-cells = <1>; 1037 #size-cells = <0>; 1038 status = "disabled"; 1039 }; 1040 1041 spi1: spi@884000 { 1042 compatible = "qcom,geni-spi"; 1043 reg = <0 0x00884000 0 0x4000>; 1044 reg-names = "se"; 1045 clock-names = "se"; 1046 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1047 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1048 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1049 dma-names = "tx", "rx"; 1050 pinctrl-names = "default"; 1051 pinctrl-0 = <&qup_spi1_default>; 1052 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1053 spi-max-frequency = <50000000>; 1054 #address-cells = <1>; 1055 #size-cells = <0>; 1056 status = "disabled"; 1057 }; 1058 1059 i2c2: i2c@888000 { 1060 compatible = "qcom,geni-i2c"; 1061 reg = <0 0x00888000 0 0x4000>; 1062 clock-names = "se"; 1063 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1064 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1065 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1066 dma-names = "tx", "rx"; 1067 pinctrl-names = "default"; 1068 pinctrl-0 = <&qup_i2c2_default>; 1069 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1070 #address-cells = <1>; 1071 #size-cells = <0>; 1072 status = "disabled"; 1073 }; 1074 1075 spi2: spi@888000 { 1076 compatible = "qcom,geni-spi"; 1077 reg = <0 0x00888000 0 0x4000>; 1078 reg-names = "se"; 1079 clock-names = "se"; 1080 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1081 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1082 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1083 dma-names = "tx", "rx"; 1084 pinctrl-names = "default"; 1085 pinctrl-0 = <&qup_spi2_default>; 1086 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1087 spi-max-frequency = <50000000>; 1088 #address-cells = <1>; 1089 #size-cells = <0>; 1090 status = "disabled"; 1091 }; 1092 1093 i2c3: i2c@88c000 { 1094 compatible = "qcom,geni-i2c"; 1095 reg = <0 0x0088c000 0 0x4000>; 1096 clock-names = "se"; 1097 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1098 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1099 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1100 dma-names = "tx", "rx"; 1101 pinctrl-names = "default"; 1102 pinctrl-0 = <&qup_i2c3_default>; 1103 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1104 #address-cells = <1>; 1105 #size-cells = <0>; 1106 status = "disabled"; 1107 }; 1108 1109 spi3: spi@88c000 { 1110 compatible = "qcom,geni-spi"; 1111 reg = <0 0x0088c000 0 0x4000>; 1112 reg-names = "se"; 1113 clock-names = "se"; 1114 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1115 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1116 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1117 dma-names = "tx", "rx"; 1118 pinctrl-names = "default"; 1119 pinctrl-0 = <&qup_spi3_default>; 1120 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1121 spi-max-frequency = <50000000>; 1122 #address-cells = <1>; 1123 #size-cells = <0>; 1124 status = "disabled"; 1125 }; 1126 1127 i2c4: i2c@890000 { 1128 compatible = "qcom,geni-i2c"; 1129 reg = <0 0x00890000 0 0x4000>; 1130 clock-names = "se"; 1131 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1132 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1133 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1134 dma-names = "tx", "rx"; 1135 pinctrl-names = "default"; 1136 pinctrl-0 = <&qup_i2c4_default>; 1137 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1138 #address-cells = <1>; 1139 #size-cells = <0>; 1140 status = "disabled"; 1141 }; 1142 1143 spi4: spi@890000 { 1144 compatible = "qcom,geni-spi"; 1145 reg = <0 0x00890000 0 0x4000>; 1146 reg-names = "se"; 1147 clock-names = "se"; 1148 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1149 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1150 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1151 dma-names = "tx", "rx"; 1152 pinctrl-names = "default"; 1153 pinctrl-0 = <&qup_spi4_default>; 1154 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1155 spi-max-frequency = <50000000>; 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 status = "disabled"; 1159 }; 1160 1161 i2c5: i2c@894000 { 1162 compatible = "qcom,geni-i2c"; 1163 reg = <0 0x00894000 0 0x4000>; 1164 clock-names = "se"; 1165 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1166 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1167 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1168 dma-names = "tx", "rx"; 1169 pinctrl-names = "default"; 1170 pinctrl-0 = <&qup_i2c5_default>; 1171 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 status = "disabled"; 1175 }; 1176 1177 spi5: spi@894000 { 1178 compatible = "qcom,geni-spi"; 1179 reg = <0 0x00894000 0 0x4000>; 1180 reg-names = "se"; 1181 clock-names = "se"; 1182 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1183 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1184 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1185 dma-names = "tx", "rx"; 1186 pinctrl-names = "default"; 1187 pinctrl-0 = <&qup_spi5_default>; 1188 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1189 spi-max-frequency = <50000000>; 1190 #address-cells = <1>; 1191 #size-cells = <0>; 1192 status = "disabled"; 1193 }; 1194 1195 i2c6: i2c@898000 { 1196 compatible = "qcom,geni-i2c"; 1197 reg = <0 0x00898000 0 0x4000>; 1198 clock-names = "se"; 1199 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1200 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1201 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1202 dma-names = "tx", "rx"; 1203 pinctrl-names = "default"; 1204 pinctrl-0 = <&qup_i2c6_default>; 1205 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1206 #address-cells = <1>; 1207 #size-cells = <0>; 1208 status = "disabled"; 1209 }; 1210 1211 spi6: spi@898000 { 1212 compatible = "qcom,geni-spi"; 1213 reg = <0 0x00898000 0 0x4000>; 1214 reg-names = "se"; 1215 clock-names = "se"; 1216 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1217 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1218 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1219 dma-names = "tx", "rx"; 1220 pinctrl-names = "default"; 1221 pinctrl-0 = <&qup_spi6_default>; 1222 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1223 spi-max-frequency = <50000000>; 1224 #address-cells = <1>; 1225 #size-cells = <0>; 1226 status = "disabled"; 1227 }; 1228 1229 i2c7: i2c@89c000 { 1230 compatible = "qcom,geni-i2c"; 1231 reg = <0 0x0089c000 0 0x4000>; 1232 clock-names = "se"; 1233 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1234 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1235 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1236 dma-names = "tx", "rx"; 1237 pinctrl-names = "default"; 1238 pinctrl-0 = <&qup_i2c7_default>; 1239 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1240 #address-cells = <1>; 1241 #size-cells = <0>; 1242 status = "disabled"; 1243 }; 1244 1245 spi7: spi@89c000 { 1246 compatible = "qcom,geni-spi"; 1247 reg = <0 0x0089c000 0 0x4000>; 1248 reg-names = "se"; 1249 clock-names = "se"; 1250 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1251 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1252 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1253 dma-names = "tx", "rx"; 1254 pinctrl-names = "default"; 1255 pinctrl-0 = <&qup_spi7_default>; 1256 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1257 spi-max-frequency = <50000000>; 1258 #address-cells = <1>; 1259 #size-cells = <0>; 1260 status = "disabled"; 1261 }; 1262 }; 1263 1264 gpi_dma1: dma-controller@a00000 { 1265 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 1266 reg = <0 0x00a00000 0 0x60000>; 1267 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1275 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1276 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1277 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1278 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1279 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1280 dma-channels = <13>; 1281 dma-channel-mask = <0xfa>; 1282 iommus = <&apps_smmu 0x0616 0x0>; 1283 #dma-cells = <3>; 1284 status = "disabled"; 1285 }; 1286 1287 qupv3_id_1: geniqup@ac0000 { 1288 compatible = "qcom,geni-se-qup"; 1289 reg = <0x0 0x00ac0000 0x0 0x6000>; 1290 clock-names = "m-ahb", "s-ahb"; 1291 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1292 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1293 iommus = <&apps_smmu 0x603 0x0>; 1294 #address-cells = <2>; 1295 #size-cells = <2>; 1296 ranges; 1297 status = "disabled"; 1298 1299 i2c8: i2c@a80000 { 1300 compatible = "qcom,geni-i2c"; 1301 reg = <0 0x00a80000 0 0x4000>; 1302 clock-names = "se"; 1303 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1304 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1305 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1306 dma-names = "tx", "rx"; 1307 pinctrl-names = "default"; 1308 pinctrl-0 = <&qup_i2c8_default>; 1309 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1310 #address-cells = <1>; 1311 #size-cells = <0>; 1312 status = "disabled"; 1313 }; 1314 1315 spi8: spi@a80000 { 1316 compatible = "qcom,geni-spi"; 1317 reg = <0 0x00a80000 0 0x4000>; 1318 reg-names = "se"; 1319 clock-names = "se"; 1320 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1321 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1322 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1323 dma-names = "tx", "rx"; 1324 pinctrl-names = "default"; 1325 pinctrl-0 = <&qup_spi8_default>; 1326 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1327 spi-max-frequency = <50000000>; 1328 #address-cells = <1>; 1329 #size-cells = <0>; 1330 status = "disabled"; 1331 }; 1332 1333 i2c9: i2c@a84000 { 1334 compatible = "qcom,geni-i2c"; 1335 reg = <0 0x00a84000 0 0x4000>; 1336 clock-names = "se"; 1337 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1338 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1339 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1340 dma-names = "tx", "rx"; 1341 pinctrl-names = "default"; 1342 pinctrl-0 = <&qup_i2c9_default>; 1343 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1344 #address-cells = <1>; 1345 #size-cells = <0>; 1346 status = "disabled"; 1347 }; 1348 1349 spi9: spi@a84000 { 1350 compatible = "qcom,geni-spi"; 1351 reg = <0 0x00a84000 0 0x4000>; 1352 reg-names = "se"; 1353 clock-names = "se"; 1354 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1355 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1356 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1357 dma-names = "tx", "rx"; 1358 pinctrl-names = "default"; 1359 pinctrl-0 = <&qup_spi9_default>; 1360 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1361 spi-max-frequency = <50000000>; 1362 #address-cells = <1>; 1363 #size-cells = <0>; 1364 status = "disabled"; 1365 }; 1366 1367 uart9: serial@a84000 { 1368 compatible = "qcom,geni-uart"; 1369 reg = <0x0 0x00a84000 0x0 0x4000>; 1370 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1371 clock-names = "se"; 1372 pinctrl-0 = <&qup_uart9_default>; 1373 pinctrl-names = "default"; 1374 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1375 status = "disabled"; 1376 }; 1377 1378 i2c10: i2c@a88000 { 1379 compatible = "qcom,geni-i2c"; 1380 reg = <0 0x00a88000 0 0x4000>; 1381 clock-names = "se"; 1382 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1383 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1384 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1385 dma-names = "tx", "rx"; 1386 pinctrl-names = "default"; 1387 pinctrl-0 = <&qup_i2c10_default>; 1388 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1389 #address-cells = <1>; 1390 #size-cells = <0>; 1391 status = "disabled"; 1392 }; 1393 1394 spi10: spi@a88000 { 1395 compatible = "qcom,geni-spi"; 1396 reg = <0 0x00a88000 0 0x4000>; 1397 reg-names = "se"; 1398 clock-names = "se"; 1399 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1400 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1401 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1402 dma-names = "tx", "rx"; 1403 pinctrl-names = "default"; 1404 pinctrl-0 = <&qup_spi10_default>; 1405 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1406 spi-max-frequency = <50000000>; 1407 #address-cells = <1>; 1408 #size-cells = <0>; 1409 status = "disabled"; 1410 }; 1411 1412 i2c11: i2c@a8c000 { 1413 compatible = "qcom,geni-i2c"; 1414 reg = <0 0x00a8c000 0 0x4000>; 1415 clock-names = "se"; 1416 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1417 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1418 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1419 dma-names = "tx", "rx"; 1420 pinctrl-names = "default"; 1421 pinctrl-0 = <&qup_i2c11_default>; 1422 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1423 #address-cells = <1>; 1424 #size-cells = <0>; 1425 status = "disabled"; 1426 }; 1427 1428 spi11: spi@a8c000 { 1429 compatible = "qcom,geni-spi"; 1430 reg = <0 0x00a8c000 0 0x4000>; 1431 reg-names = "se"; 1432 clock-names = "se"; 1433 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1434 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1435 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1436 dma-names = "tx", "rx"; 1437 pinctrl-names = "default"; 1438 pinctrl-0 = <&qup_spi11_default>; 1439 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1440 spi-max-frequency = <50000000>; 1441 #address-cells = <1>; 1442 #size-cells = <0>; 1443 status = "disabled"; 1444 }; 1445 1446 uart2: serial@a90000 { 1447 compatible = "qcom,geni-debug-uart"; 1448 reg = <0x0 0x00a90000 0x0 0x4000>; 1449 clock-names = "se"; 1450 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1451 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1452 status = "disabled"; 1453 }; 1454 1455 i2c12: i2c@a90000 { 1456 compatible = "qcom,geni-i2c"; 1457 reg = <0 0x00a90000 0 0x4000>; 1458 clock-names = "se"; 1459 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1460 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1461 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1462 dma-names = "tx", "rx"; 1463 pinctrl-names = "default"; 1464 pinctrl-0 = <&qup_i2c12_default>; 1465 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1466 #address-cells = <1>; 1467 #size-cells = <0>; 1468 status = "disabled"; 1469 }; 1470 1471 spi12: spi@a90000 { 1472 compatible = "qcom,geni-spi"; 1473 reg = <0 0x00a90000 0 0x4000>; 1474 reg-names = "se"; 1475 clock-names = "se"; 1476 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1477 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1478 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1479 dma-names = "tx", "rx"; 1480 pinctrl-names = "default"; 1481 pinctrl-0 = <&qup_spi12_default>; 1482 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1483 spi-max-frequency = <50000000>; 1484 #address-cells = <1>; 1485 #size-cells = <0>; 1486 status = "disabled"; 1487 }; 1488 1489 i2c16: i2c@94000 { 1490 compatible = "qcom,geni-i2c"; 1491 reg = <0 0x00094000 0 0x4000>; 1492 clock-names = "se"; 1493 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1494 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1495 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1496 dma-names = "tx", "rx"; 1497 pinctrl-names = "default"; 1498 pinctrl-0 = <&qup_i2c16_default>; 1499 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1500 #address-cells = <1>; 1501 #size-cells = <0>; 1502 status = "disabled"; 1503 }; 1504 1505 spi16: spi@a94000 { 1506 compatible = "qcom,geni-spi"; 1507 reg = <0 0x00a94000 0 0x4000>; 1508 reg-names = "se"; 1509 clock-names = "se"; 1510 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1511 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1512 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1513 dma-names = "tx", "rx"; 1514 pinctrl-names = "default"; 1515 pinctrl-0 = <&qup_spi16_default>; 1516 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1517 spi-max-frequency = <50000000>; 1518 #address-cells = <1>; 1519 #size-cells = <0>; 1520 status = "disabled"; 1521 }; 1522 }; 1523 1524 gpi_dma2: dma-controller@c00000 { 1525 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 1526 reg = <0 0x00c00000 0 0x60000>; 1527 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; 1540 dma-channels = <13>; 1541 dma-channel-mask = <0xfa>; 1542 iommus = <&apps_smmu 0x07b6 0x0>; 1543 #dma-cells = <3>; 1544 status = "disabled"; 1545 }; 1546 1547 qupv3_id_2: geniqup@cc0000 { 1548 compatible = "qcom,geni-se-qup"; 1549 reg = <0x0 0x00cc0000 0x0 0x6000>; 1550 1551 clock-names = "m-ahb", "s-ahb"; 1552 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1553 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1554 iommus = <&apps_smmu 0x7a3 0x0>; 1555 #address-cells = <2>; 1556 #size-cells = <2>; 1557 ranges; 1558 status = "disabled"; 1559 1560 i2c17: i2c@c80000 { 1561 compatible = "qcom,geni-i2c"; 1562 reg = <0 0x00c80000 0 0x4000>; 1563 clock-names = "se"; 1564 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1565 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1566 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1567 dma-names = "tx", "rx"; 1568 pinctrl-names = "default"; 1569 pinctrl-0 = <&qup_i2c17_default>; 1570 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1571 #address-cells = <1>; 1572 #size-cells = <0>; 1573 status = "disabled"; 1574 }; 1575 1576 spi17: spi@c80000 { 1577 compatible = "qcom,geni-spi"; 1578 reg = <0 0x00c80000 0 0x4000>; 1579 reg-names = "se"; 1580 clock-names = "se"; 1581 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1582 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1583 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1584 dma-names = "tx", "rx"; 1585 pinctrl-names = "default"; 1586 pinctrl-0 = <&qup_spi17_default>; 1587 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1588 spi-max-frequency = <50000000>; 1589 #address-cells = <1>; 1590 #size-cells = <0>; 1591 status = "disabled"; 1592 }; 1593 1594 i2c18: i2c@c84000 { 1595 compatible = "qcom,geni-i2c"; 1596 reg = <0 0x00c84000 0 0x4000>; 1597 clock-names = "se"; 1598 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1599 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1600 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1601 dma-names = "tx", "rx"; 1602 pinctrl-names = "default"; 1603 pinctrl-0 = <&qup_i2c18_default>; 1604 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1605 #address-cells = <1>; 1606 #size-cells = <0>; 1607 status = "disabled"; 1608 }; 1609 1610 spi18: spi@c84000 { 1611 compatible = "qcom,geni-spi"; 1612 reg = <0 0x00c84000 0 0x4000>; 1613 reg-names = "se"; 1614 clock-names = "se"; 1615 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1616 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1617 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1618 dma-names = "tx", "rx"; 1619 pinctrl-names = "default"; 1620 pinctrl-0 = <&qup_spi18_default>; 1621 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1622 spi-max-frequency = <50000000>; 1623 #address-cells = <1>; 1624 #size-cells = <0>; 1625 status = "disabled"; 1626 }; 1627 1628 i2c19: i2c@c88000 { 1629 compatible = "qcom,geni-i2c"; 1630 reg = <0 0x00c88000 0 0x4000>; 1631 clock-names = "se"; 1632 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1633 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1634 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1635 dma-names = "tx", "rx"; 1636 pinctrl-names = "default"; 1637 pinctrl-0 = <&qup_i2c19_default>; 1638 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1639 #address-cells = <1>; 1640 #size-cells = <0>; 1641 status = "disabled"; 1642 }; 1643 1644 spi19: spi@c88000 { 1645 compatible = "qcom,geni-spi"; 1646 reg = <0 0x00c88000 0 0x4000>; 1647 reg-names = "se"; 1648 clock-names = "se"; 1649 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1650 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1651 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1652 dma-names = "tx", "rx"; 1653 pinctrl-names = "default"; 1654 pinctrl-0 = <&qup_spi19_default>; 1655 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1656 spi-max-frequency = <50000000>; 1657 #address-cells = <1>; 1658 #size-cells = <0>; 1659 status = "disabled"; 1660 }; 1661 1662 i2c13: i2c@c8c000 { 1663 compatible = "qcom,geni-i2c"; 1664 reg = <0 0x00c8c000 0 0x4000>; 1665 clock-names = "se"; 1666 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1667 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1668 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1669 dma-names = "tx", "rx"; 1670 pinctrl-names = "default"; 1671 pinctrl-0 = <&qup_i2c13_default>; 1672 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1673 #address-cells = <1>; 1674 #size-cells = <0>; 1675 status = "disabled"; 1676 }; 1677 1678 spi13: spi@c8c000 { 1679 compatible = "qcom,geni-spi"; 1680 reg = <0 0x00c8c000 0 0x4000>; 1681 reg-names = "se"; 1682 clock-names = "se"; 1683 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1684 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1685 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1686 dma-names = "tx", "rx"; 1687 pinctrl-names = "default"; 1688 pinctrl-0 = <&qup_spi13_default>; 1689 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1690 spi-max-frequency = <50000000>; 1691 #address-cells = <1>; 1692 #size-cells = <0>; 1693 status = "disabled"; 1694 }; 1695 1696 i2c14: i2c@c90000 { 1697 compatible = "qcom,geni-i2c"; 1698 reg = <0 0x00c90000 0 0x4000>; 1699 clock-names = "se"; 1700 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1701 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1702 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1703 dma-names = "tx", "rx"; 1704 pinctrl-names = "default"; 1705 pinctrl-0 = <&qup_i2c14_default>; 1706 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1707 #address-cells = <1>; 1708 #size-cells = <0>; 1709 status = "disabled"; 1710 }; 1711 1712 spi14: spi@c90000 { 1713 compatible = "qcom,geni-spi"; 1714 reg = <0 0x00c90000 0 0x4000>; 1715 reg-names = "se"; 1716 clock-names = "se"; 1717 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1718 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1719 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1720 dma-names = "tx", "rx"; 1721 pinctrl-names = "default"; 1722 pinctrl-0 = <&qup_spi14_default>; 1723 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1724 spi-max-frequency = <50000000>; 1725 #address-cells = <1>; 1726 #size-cells = <0>; 1727 status = "disabled"; 1728 }; 1729 1730 i2c15: i2c@c94000 { 1731 compatible = "qcom,geni-i2c"; 1732 reg = <0 0x00c94000 0 0x4000>; 1733 clock-names = "se"; 1734 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1735 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1736 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1737 dma-names = "tx", "rx"; 1738 pinctrl-names = "default"; 1739 pinctrl-0 = <&qup_i2c15_default>; 1740 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1741 #address-cells = <1>; 1742 #size-cells = <0>; 1743 status = "disabled"; 1744 }; 1745 1746 spi15: spi@c94000 { 1747 compatible = "qcom,geni-spi"; 1748 reg = <0 0x00c94000 0 0x4000>; 1749 reg-names = "se"; 1750 clock-names = "se"; 1751 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1752 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1753 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1754 dma-names = "tx", "rx"; 1755 pinctrl-names = "default"; 1756 pinctrl-0 = <&qup_spi15_default>; 1757 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1758 spi-max-frequency = <50000000>; 1759 #address-cells = <1>; 1760 #size-cells = <0>; 1761 status = "disabled"; 1762 }; 1763 }; 1764 1765 config_noc: interconnect@1500000 { 1766 compatible = "qcom,sm8150-config-noc"; 1767 reg = <0 0x01500000 0 0x7400>; 1768 #interconnect-cells = <2>; 1769 qcom,bcm-voters = <&apps_bcm_voter>; 1770 }; 1771 1772 system_noc: interconnect@1620000 { 1773 compatible = "qcom,sm8150-system-noc"; 1774 reg = <0 0x01620000 0 0x19400>; 1775 #interconnect-cells = <2>; 1776 qcom,bcm-voters = <&apps_bcm_voter>; 1777 }; 1778 1779 mc_virt: interconnect@163a000 { 1780 compatible = "qcom,sm8150-mc-virt"; 1781 reg = <0 0x0163a000 0 0x1000>; 1782 #interconnect-cells = <2>; 1783 qcom,bcm-voters = <&apps_bcm_voter>; 1784 }; 1785 1786 aggre1_noc: interconnect@16e0000 { 1787 compatible = "qcom,sm8150-aggre1-noc"; 1788 reg = <0 0x016e0000 0 0xd080>; 1789 #interconnect-cells = <2>; 1790 qcom,bcm-voters = <&apps_bcm_voter>; 1791 }; 1792 1793 aggre2_noc: interconnect@1700000 { 1794 compatible = "qcom,sm8150-aggre2-noc"; 1795 reg = <0 0x01700000 0 0x20000>; 1796 #interconnect-cells = <2>; 1797 qcom,bcm-voters = <&apps_bcm_voter>; 1798 }; 1799 1800 compute_noc: interconnect@1720000 { 1801 compatible = "qcom,sm8150-compute-noc"; 1802 reg = <0 0x01720000 0 0x7000>; 1803 #interconnect-cells = <2>; 1804 qcom,bcm-voters = <&apps_bcm_voter>; 1805 }; 1806 1807 mmss_noc: interconnect@1740000 { 1808 compatible = "qcom,sm8150-mmss-noc"; 1809 reg = <0 0x01740000 0 0x1c100>; 1810 #interconnect-cells = <2>; 1811 qcom,bcm-voters = <&apps_bcm_voter>; 1812 }; 1813 1814 system-cache-controller@9200000 { 1815 compatible = "qcom,sm8150-llcc"; 1816 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, 1817 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, 1818 <0 0x09600000 0 0x50000>; 1819 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 1820 "llcc3_base", "llcc_broadcast_base"; 1821 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1822 }; 1823 1824 dma@10a2000 { 1825 compatible = "qcom,sm8150-dcc", "qcom,dcc"; 1826 reg = <0x0 0x010a2000 0x0 0x1000>, 1827 <0x0 0x010ad000 0x0 0x3000>; 1828 }; 1829 1830 pcie0: pcie@1c00000 { 1831 compatible = "qcom,pcie-sm8150"; 1832 reg = <0 0x01c00000 0 0x3000>, 1833 <0 0x60000000 0 0xf1d>, 1834 <0 0x60000f20 0 0xa8>, 1835 <0 0x60001000 0 0x1000>, 1836 <0 0x60100000 0 0x100000>; 1837 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1838 device_type = "pci"; 1839 linux,pci-domain = <0>; 1840 bus-range = <0x00 0xff>; 1841 num-lanes = <1>; 1842 1843 #address-cells = <3>; 1844 #size-cells = <2>; 1845 1846 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1847 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1848 1849 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1857 interrupt-names = "msi0", 1858 "msi1", 1859 "msi2", 1860 "msi3", 1861 "msi4", 1862 "msi5", 1863 "msi6", 1864 "msi7"; 1865 #interrupt-cells = <1>; 1866 interrupt-map-mask = <0 0 0 0x7>; 1867 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1868 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1869 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1870 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1871 1872 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1873 <&gcc GCC_PCIE_0_AUX_CLK>, 1874 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1875 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1876 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1877 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1878 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1879 <&rpmhcc RPMH_CXO_CLK>; 1880 clock-names = "pipe", 1881 "aux", 1882 "cfg", 1883 "bus_master", 1884 "bus_slave", 1885 "slave_q2a", 1886 "tbu", 1887 "ref"; 1888 1889 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, 1890 <0x100 &apps_smmu 0x1d81 0x1>; 1891 1892 resets = <&gcc GCC_PCIE_0_BCR>; 1893 reset-names = "pci"; 1894 1895 power-domains = <&gcc PCIE_0_GDSC>; 1896 1897 phys = <&pcie0_phy>; 1898 phy-names = "pciephy"; 1899 1900 perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>; 1901 wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; 1902 1903 pinctrl-names = "default"; 1904 pinctrl-0 = <&pcie0_default_state>; 1905 1906 status = "disabled"; 1907 1908 pcie@0 { 1909 device_type = "pci"; 1910 reg = <0x0 0x0 0x0 0x0 0x0>; 1911 bus-range = <0x01 0xff>; 1912 1913 #address-cells = <3>; 1914 #size-cells = <2>; 1915 ranges; 1916 }; 1917 }; 1918 1919 pcie0_phy: phy@1c06000 { 1920 compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy"; 1921 reg = <0 0x01c06000 0 0x1000>; 1922 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1923 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1924 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1925 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, 1926 <&gcc GCC_PCIE_0_PIPE_CLK>; 1927 clock-names = "aux", 1928 "cfg_ahb", 1929 "ref", 1930 "refgen", 1931 "pipe"; 1932 1933 clock-output-names = "pcie_0_pipe_clk"; 1934 #clock-cells = <0>; 1935 1936 #phy-cells = <0>; 1937 1938 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1939 reset-names = "phy"; 1940 1941 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1942 assigned-clock-rates = <100000000>; 1943 1944 status = "disabled"; 1945 }; 1946 1947 pcie1: pcie@1c08000 { 1948 compatible = "qcom,pcie-sm8150"; 1949 reg = <0 0x01c08000 0 0x3000>, 1950 <0 0x40000000 0 0xf1d>, 1951 <0 0x40000f20 0 0xa8>, 1952 <0 0x40001000 0 0x1000>, 1953 <0 0x40100000 0 0x100000>; 1954 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1955 device_type = "pci"; 1956 linux,pci-domain = <1>; 1957 bus-range = <0x00 0xff>; 1958 num-lanes = <2>; 1959 1960 #address-cells = <3>; 1961 #size-cells = <2>; 1962 1963 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1964 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1965 1966 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1967 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1968 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1969 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1970 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1971 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1972 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 1973 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1974 interrupt-names = "msi0", 1975 "msi1", 1976 "msi2", 1977 "msi3", 1978 "msi4", 1979 "msi5", 1980 "msi6", 1981 "msi7"; 1982 #interrupt-cells = <1>; 1983 interrupt-map-mask = <0 0 0 0x7>; 1984 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1985 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1986 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1987 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1988 1989 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1990 <&gcc GCC_PCIE_1_AUX_CLK>, 1991 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1992 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1993 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1994 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1995 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1996 <&rpmhcc RPMH_CXO_CLK>; 1997 clock-names = "pipe", 1998 "aux", 1999 "cfg", 2000 "bus_master", 2001 "bus_slave", 2002 "slave_q2a", 2003 "tbu", 2004 "ref"; 2005 2006 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2007 assigned-clock-rates = <19200000>; 2008 2009 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 2010 <0x100 &apps_smmu 0x1e01 0x1>; 2011 2012 resets = <&gcc GCC_PCIE_1_BCR>; 2013 reset-names = "pci"; 2014 2015 power-domains = <&gcc PCIE_1_GDSC>; 2016 2017 phys = <&pcie1_phy>; 2018 phy-names = "pciephy"; 2019 2020 perst-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; 2021 enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>; 2022 2023 pinctrl-names = "default"; 2024 pinctrl-0 = <&pcie1_default_state>; 2025 2026 status = "disabled"; 2027 2028 pcie@0 { 2029 device_type = "pci"; 2030 reg = <0x0 0x0 0x0 0x0 0x0>; 2031 bus-range = <0x01 0xff>; 2032 2033 #address-cells = <3>; 2034 #size-cells = <2>; 2035 ranges; 2036 }; 2037 }; 2038 2039 pcie1_phy: phy@1c0e000 { 2040 compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy"; 2041 reg = <0 0x01c0e000 0 0x1000>; 2042 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2043 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2044 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2045 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, 2046 <&gcc GCC_PCIE_1_PIPE_CLK>; 2047 clock-names = "aux", 2048 "cfg_ahb", 2049 "ref", 2050 "refgen", 2051 "pipe"; 2052 2053 clock-output-names = "pcie_1_pipe_clk"; 2054 #clock-cells = <0>; 2055 2056 #phy-cells = <0>; 2057 2058 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2059 reset-names = "phy"; 2060 2061 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2062 assigned-clock-rates = <100000000>; 2063 2064 status = "disabled"; 2065 }; 2066 2067 ufs_mem_hc: ufshc@1d84000 { 2068 compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 2069 "jedec,ufs-2.0"; 2070 reg = <0 0x01d84000 0 0x2500>, 2071 <0 0x01d90000 0 0x8000>; 2072 reg-names = "std", "ice"; 2073 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2074 phys = <&ufs_mem_phy>; 2075 phy-names = "ufsphy"; 2076 lanes-per-direction = <2>; 2077 #reset-cells = <1>; 2078 resets = <&gcc GCC_UFS_PHY_BCR>; 2079 reset-names = "rst"; 2080 2081 iommus = <&apps_smmu 0x300 0>; 2082 2083 clock-names = 2084 "core_clk", 2085 "bus_aggr_clk", 2086 "iface_clk", 2087 "core_clk_unipro", 2088 "ref_clk", 2089 "tx_lane0_sync_clk", 2090 "rx_lane0_sync_clk", 2091 "rx_lane1_sync_clk", 2092 "ice_core_clk"; 2093 clocks = 2094 <&gcc GCC_UFS_PHY_AXI_CLK>, 2095 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2096 <&gcc GCC_UFS_PHY_AHB_CLK>, 2097 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2098 <&rpmhcc RPMH_CXO_CLK>, 2099 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2100 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2101 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 2102 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2103 freq-table-hz = 2104 <37500000 300000000>, 2105 <0 0>, 2106 <0 0>, 2107 <37500000 300000000>, 2108 <0 0>, 2109 <0 0>, 2110 <0 0>, 2111 <0 0>, 2112 <0 300000000>; 2113 2114 status = "disabled"; 2115 }; 2116 2117 ufs_mem_phy: phy@1d87000 { 2118 compatible = "qcom,sm8150-qmp-ufs-phy"; 2119 reg = <0 0x01d87000 0 0x1000>; 2120 2121 clocks = <&rpmhcc RPMH_CXO_CLK>, 2122 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2123 <&gcc GCC_UFS_MEM_CLKREF_CLK>; 2124 clock-names = "ref", 2125 "ref_aux", 2126 "qref"; 2127 2128 power-domains = <&gcc UFS_PHY_GDSC>; 2129 2130 resets = <&ufs_mem_hc 0>; 2131 reset-names = "ufsphy"; 2132 2133 #phy-cells = <0>; 2134 2135 status = "disabled"; 2136 }; 2137 2138 cryptobam: dma-controller@1dc4000 { 2139 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2140 reg = <0 0x01dc4000 0 0x24000>; 2141 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2142 #dma-cells = <1>; 2143 qcom,ee = <0>; 2144 qcom,controlled-remotely; 2145 num-channels = <8>; 2146 qcom,num-ees = <2>; 2147 iommus = <&apps_smmu 0x502 0x0641>, 2148 <&apps_smmu 0x504 0x0011>, 2149 <&apps_smmu 0x506 0x0011>, 2150 <&apps_smmu 0x508 0x0011>, 2151 <&apps_smmu 0x512 0x0000>; 2152 }; 2153 2154 crypto: crypto@1dfa000 { 2155 compatible = "qcom,sm8150-qce", "qcom,qce"; 2156 reg = <0 0x01dfa000 0 0x6000>; 2157 dmas = <&cryptobam 4>, <&cryptobam 5>; 2158 dma-names = "rx", "tx"; 2159 iommus = <&apps_smmu 0x502 0x0641>, 2160 <&apps_smmu 0x504 0x0011>, 2161 <&apps_smmu 0x506 0x0011>, 2162 <&apps_smmu 0x508 0x0011>, 2163 <&apps_smmu 0x512 0x0000>; 2164 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>; 2165 interconnect-names = "memory"; 2166 }; 2167 2168 tcsr_mutex: hwlock@1f40000 { 2169 compatible = "qcom,tcsr-mutex"; 2170 reg = <0x0 0x01f40000 0x0 0x20000>; 2171 #hwlock-cells = <1>; 2172 }; 2173 2174 tcsr_regs_1: syscon@1f60000 { 2175 compatible = "qcom,sm8150-tcsr", "syscon"; 2176 reg = <0x0 0x01f60000 0x0 0x20000>; 2177 }; 2178 2179 remoteproc_slpi: remoteproc@2400000 { 2180 compatible = "qcom,sm8150-slpi-pas"; 2181 reg = <0x0 0x02400000 0x0 0x4040>; 2182 2183 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 2184 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2185 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2186 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2187 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2188 interrupt-names = "wdog", "fatal", "ready", 2189 "handover", "stop-ack"; 2190 2191 clocks = <&rpmhcc RPMH_CXO_CLK>; 2192 clock-names = "xo"; 2193 2194 power-domains = <&rpmhpd SM8150_LCX>, 2195 <&rpmhpd SM8150_LMX>; 2196 power-domain-names = "lcx", "lmx"; 2197 2198 memory-region = <&slpi_mem>; 2199 2200 qcom,qmp = <&aoss_qmp>; 2201 2202 qcom,smem-states = <&slpi_smp2p_out 0>; 2203 qcom,smem-state-names = "stop"; 2204 2205 status = "disabled"; 2206 2207 glink-edge { 2208 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 2209 label = "dsps"; 2210 qcom,remote-pid = <3>; 2211 mboxes = <&apss_shared 24>; 2212 2213 fastrpc { 2214 compatible = "qcom,fastrpc"; 2215 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2216 label = "sdsp"; 2217 qcom,non-secure-domain; 2218 #address-cells = <1>; 2219 #size-cells = <0>; 2220 2221 compute-cb@1 { 2222 compatible = "qcom,fastrpc-compute-cb"; 2223 reg = <1>; 2224 iommus = <&apps_smmu 0x05a1 0x0>; 2225 }; 2226 2227 compute-cb@2 { 2228 compatible = "qcom,fastrpc-compute-cb"; 2229 reg = <2>; 2230 iommus = <&apps_smmu 0x05a2 0x0>; 2231 }; 2232 2233 compute-cb@3 { 2234 compatible = "qcom,fastrpc-compute-cb"; 2235 reg = <3>; 2236 iommus = <&apps_smmu 0x05a3 0x0>; 2237 /* note: shared-cb = <4> in downstream */ 2238 }; 2239 }; 2240 }; 2241 }; 2242 2243 gpu: gpu@2c00000 { 2244 compatible = "qcom,adreno-640.1", "qcom,adreno"; 2245 reg = <0 0x02c00000 0 0x40000>; 2246 reg-names = "kgsl_3d0_reg_memory"; 2247 2248 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2249 2250 iommus = <&adreno_smmu 0 0x401>; 2251 2252 operating-points-v2 = <&gpu_opp_table>; 2253 2254 qcom,gmu = <&gmu>; 2255 2256 nvmem-cells = <&gpu_speed_bin>; 2257 nvmem-cell-names = "speed_bin"; 2258 #cooling-cells = <2>; 2259 2260 status = "disabled"; 2261 2262 zap-shader { 2263 memory-region = <&gpu_mem>; 2264 }; 2265 2266 gpu_opp_table: opp-table { 2267 compatible = "operating-points-v2"; 2268 2269 opp-675000000 { 2270 opp-hz = /bits/ 64 <675000000>; 2271 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2272 opp-supported-hw = <0x2>; 2273 }; 2274 2275 opp-585000000 { 2276 opp-hz = /bits/ 64 <585000000>; 2277 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2278 opp-supported-hw = <0x3>; 2279 }; 2280 2281 opp-499200000 { 2282 opp-hz = /bits/ 64 <499200000>; 2283 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2284 opp-supported-hw = <0x3>; 2285 }; 2286 2287 opp-427000000 { 2288 opp-hz = /bits/ 64 <427000000>; 2289 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2290 opp-supported-hw = <0x3>; 2291 }; 2292 2293 opp-345000000 { 2294 opp-hz = /bits/ 64 <345000000>; 2295 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2296 opp-supported-hw = <0x3>; 2297 }; 2298 2299 opp-257000000 { 2300 opp-hz = /bits/ 64 <257000000>; 2301 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2302 opp-supported-hw = <0x3>; 2303 }; 2304 }; 2305 }; 2306 2307 gmu: gmu@2c6a000 { 2308 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 2309 2310 reg = <0 0x02c6a000 0 0x30000>, 2311 <0 0x0b290000 0 0x10000>, 2312 <0 0x0b490000 0 0x10000>; 2313 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2314 2315 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2316 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2317 interrupt-names = "hfi", "gmu"; 2318 2319 clocks = <&gpucc GPU_CC_AHB_CLK>, 2320 <&gpucc GPU_CC_CX_GMU_CLK>, 2321 <&gpucc GPU_CC_CXO_CLK>, 2322 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2323 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2324 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2325 2326 power-domains = <&gpucc GPU_CX_GDSC>, 2327 <&gpucc GPU_GX_GDSC>; 2328 power-domain-names = "cx", "gx"; 2329 2330 iommus = <&adreno_smmu 5 0x400>; 2331 2332 operating-points-v2 = <&gmu_opp_table>; 2333 2334 status = "disabled"; 2335 2336 gmu_opp_table: opp-table { 2337 compatible = "operating-points-v2"; 2338 2339 opp-200000000 { 2340 opp-hz = /bits/ 64 <200000000>; 2341 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2342 }; 2343 }; 2344 }; 2345 2346 gpucc: clock-controller@2c90000 { 2347 compatible = "qcom,sm8150-gpucc"; 2348 reg = <0 0x02c90000 0 0x9000>; 2349 clocks = <&rpmhcc RPMH_CXO_CLK>, 2350 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2351 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2352 clock-names = "bi_tcxo", 2353 "gcc_gpu_gpll0_clk_src", 2354 "gcc_gpu_gpll0_div_clk_src"; 2355 #clock-cells = <1>; 2356 #reset-cells = <1>; 2357 #power-domain-cells = <1>; 2358 }; 2359 2360 adreno_smmu: iommu@2ca0000 { 2361 compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu", 2362 "qcom,smmu-500", "arm,mmu-500"; 2363 reg = <0 0x02ca0000 0 0x10000>; 2364 #iommu-cells = <2>; 2365 #global-interrupts = <1>; 2366 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 2367 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2368 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2369 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2370 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2371 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2372 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2373 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2374 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 2375 clocks = <&gpucc GPU_CC_AHB_CLK>, 2376 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2377 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2378 clock-names = "ahb", "bus", "iface"; 2379 2380 power-domains = <&gpucc GPU_CX_GDSC>; 2381 }; 2382 2383 tlmm: pinctrl@3100000 { 2384 compatible = "qcom,sm8150-pinctrl"; 2385 reg = <0x0 0x03100000 0x0 0x300000>, 2386 <0x0 0x03500000 0x0 0x300000>, 2387 <0x0 0x03900000 0x0 0x300000>, 2388 <0x0 0x03D00000 0x0 0x300000>; 2389 reg-names = "west", "east", "north", "south"; 2390 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2391 gpio-ranges = <&tlmm 0 0 176>; 2392 gpio-controller; 2393 #gpio-cells = <2>; 2394 interrupt-controller; 2395 #interrupt-cells = <2>; 2396 wakeup-parent = <&pdc>; 2397 2398 qup_i2c0_default: qup-i2c0-default-state { 2399 pins = "gpio0", "gpio1"; 2400 function = "qup0"; 2401 drive-strength = <0x02>; 2402 bias-disable; 2403 }; 2404 2405 qup_spi0_default: qup-spi0-default-state { 2406 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 2407 function = "qup0"; 2408 drive-strength = <6>; 2409 bias-disable; 2410 }; 2411 2412 qup_i2c1_default: qup-i2c1-default-state { 2413 pins = "gpio114", "gpio115"; 2414 function = "qup1"; 2415 drive-strength = <2>; 2416 bias-disable; 2417 }; 2418 2419 qup_spi1_default: qup-spi1-default-state { 2420 pins = "gpio114", "gpio115", "gpio116", "gpio117"; 2421 function = "qup1"; 2422 drive-strength = <6>; 2423 bias-disable; 2424 }; 2425 2426 qup_i2c2_default: qup-i2c2-default-state { 2427 pins = "gpio126", "gpio127"; 2428 function = "qup2"; 2429 drive-strength = <2>; 2430 bias-disable; 2431 }; 2432 2433 qup_spi2_default: qup-spi2-default-state { 2434 pins = "gpio126", "gpio127", "gpio128", "gpio129"; 2435 function = "qup2"; 2436 drive-strength = <6>; 2437 bias-disable; 2438 }; 2439 2440 qup_i2c3_default: qup-i2c3-default-state { 2441 pins = "gpio144", "gpio145"; 2442 function = "qup3"; 2443 drive-strength = <2>; 2444 bias-disable; 2445 }; 2446 2447 qup_spi3_default: qup-spi3-default-state { 2448 pins = "gpio144", "gpio145", "gpio146", "gpio147"; 2449 function = "qup3"; 2450 drive-strength = <6>; 2451 bias-disable; 2452 }; 2453 2454 qup_i2c4_default: qup-i2c4-default-state { 2455 pins = "gpio51", "gpio52"; 2456 function = "qup4"; 2457 drive-strength = <2>; 2458 bias-disable; 2459 }; 2460 2461 qup_spi4_default: qup-spi4-default-state { 2462 pins = "gpio51", "gpio52", "gpio53", "gpio54"; 2463 function = "qup4"; 2464 drive-strength = <6>; 2465 bias-disable; 2466 }; 2467 2468 qup_i2c5_default: qup-i2c5-default-state { 2469 pins = "gpio121", "gpio122"; 2470 function = "qup5"; 2471 drive-strength = <2>; 2472 bias-disable; 2473 }; 2474 2475 qup_spi5_default: qup-spi5-default-state { 2476 pins = "gpio119", "gpio120", "gpio121", "gpio122"; 2477 function = "qup5"; 2478 drive-strength = <6>; 2479 bias-disable; 2480 }; 2481 2482 qup_i2c6_default: qup-i2c6-default-state { 2483 pins = "gpio6", "gpio7"; 2484 function = "qup6"; 2485 drive-strength = <2>; 2486 bias-disable; 2487 }; 2488 2489 qup_spi6_default: qup-spi6-default-state { 2490 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 2491 function = "qup6"; 2492 drive-strength = <6>; 2493 bias-disable; 2494 }; 2495 2496 qup_i2c7_default: qup-i2c7-default-state { 2497 pins = "gpio98", "gpio99"; 2498 function = "qup7"; 2499 drive-strength = <2>; 2500 bias-disable; 2501 }; 2502 2503 qup_spi7_default: qup-spi7-default-state { 2504 pins = "gpio98", "gpio99", "gpio100", "gpio101"; 2505 function = "qup7"; 2506 drive-strength = <6>; 2507 bias-disable; 2508 }; 2509 2510 qup_i2c8_default: qup-i2c8-default-state { 2511 pins = "gpio88", "gpio89"; 2512 function = "qup8"; 2513 drive-strength = <2>; 2514 bias-disable; 2515 }; 2516 2517 qup_spi8_default: qup-spi8-default-state { 2518 pins = "gpio88", "gpio89", "gpio90", "gpio91"; 2519 function = "qup8"; 2520 drive-strength = <6>; 2521 bias-disable; 2522 }; 2523 2524 qup_i2c9_default: qup-i2c9-default-state { 2525 pins = "gpio39", "gpio40"; 2526 function = "qup9"; 2527 drive-strength = <2>; 2528 bias-disable; 2529 }; 2530 2531 qup_spi9_default: qup-spi9-default-state { 2532 pins = "gpio39", "gpio40", "gpio41", "gpio42"; 2533 function = "qup9"; 2534 drive-strength = <6>; 2535 bias-disable; 2536 }; 2537 2538 qup_uart9_default: qup-uart9-default-state { 2539 pins = "gpio41", "gpio42"; 2540 function = "qup9"; 2541 drive-strength = <2>; 2542 bias-disable; 2543 }; 2544 2545 qup_i2c10_default: qup-i2c10-default-state { 2546 pins = "gpio9", "gpio10"; 2547 function = "qup10"; 2548 drive-strength = <2>; 2549 bias-disable; 2550 }; 2551 2552 qup_spi10_default: qup-spi10-default-state { 2553 pins = "gpio9", "gpio10", "gpio11", "gpio12"; 2554 function = "qup10"; 2555 drive-strength = <6>; 2556 bias-disable; 2557 }; 2558 2559 qup_i2c11_default: qup-i2c11-default-state { 2560 pins = "gpio94", "gpio95"; 2561 function = "qup11"; 2562 drive-strength = <2>; 2563 bias-disable; 2564 }; 2565 2566 qup_spi11_default: qup-spi11-default-state { 2567 pins = "gpio92", "gpio93", "gpio94", "gpio95"; 2568 function = "qup11"; 2569 drive-strength = <6>; 2570 bias-disable; 2571 }; 2572 2573 qup_i2c12_default: qup-i2c12-default-state { 2574 pins = "gpio83", "gpio84"; 2575 function = "qup12"; 2576 drive-strength = <2>; 2577 bias-disable; 2578 }; 2579 2580 qup_spi12_default: qup-spi12-default-state { 2581 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2582 function = "qup12"; 2583 drive-strength = <6>; 2584 bias-disable; 2585 }; 2586 2587 qup_i2c13_default: qup-i2c13-default-state { 2588 pins = "gpio43", "gpio44"; 2589 function = "qup13"; 2590 drive-strength = <2>; 2591 bias-disable; 2592 }; 2593 2594 qup_spi13_default: qup-spi13-default-state { 2595 pins = "gpio43", "gpio44", "gpio45", "gpio46"; 2596 function = "qup13"; 2597 drive-strength = <6>; 2598 bias-disable; 2599 }; 2600 2601 qup_i2c14_default: qup-i2c14-default-state { 2602 pins = "gpio47", "gpio48"; 2603 function = "qup14"; 2604 drive-strength = <2>; 2605 bias-disable; 2606 }; 2607 2608 qup_spi14_default: qup-spi14-default-state { 2609 pins = "gpio47", "gpio48", "gpio49", "gpio50"; 2610 function = "qup14"; 2611 drive-strength = <6>; 2612 bias-disable; 2613 }; 2614 2615 qup_i2c15_default: qup-i2c15-default-state { 2616 pins = "gpio27", "gpio28"; 2617 function = "qup15"; 2618 drive-strength = <2>; 2619 bias-disable; 2620 }; 2621 2622 qup_spi15_default: qup-spi15-default-state { 2623 pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2624 function = "qup15"; 2625 drive-strength = <6>; 2626 bias-disable; 2627 }; 2628 2629 qup_i2c16_default: qup-i2c16-default-state { 2630 pins = "gpio86", "gpio85"; 2631 function = "qup16"; 2632 drive-strength = <2>; 2633 bias-disable; 2634 }; 2635 2636 qup_spi16_default: qup-spi16-default-state { 2637 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2638 function = "qup16"; 2639 drive-strength = <6>; 2640 bias-disable; 2641 }; 2642 2643 qup_i2c17_default: qup-i2c17-default-state { 2644 pins = "gpio55", "gpio56"; 2645 function = "qup17"; 2646 drive-strength = <2>; 2647 bias-disable; 2648 }; 2649 2650 qup_spi17_default: qup-spi17-default-state { 2651 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2652 function = "qup17"; 2653 drive-strength = <6>; 2654 bias-disable; 2655 }; 2656 2657 qup_i2c18_default: qup-i2c18-default-state { 2658 pins = "gpio23", "gpio24"; 2659 function = "qup18"; 2660 drive-strength = <2>; 2661 bias-disable; 2662 }; 2663 2664 qup_spi18_default: qup-spi18-default-state { 2665 pins = "gpio23", "gpio24", "gpio25", "gpio26"; 2666 function = "qup18"; 2667 drive-strength = <6>; 2668 bias-disable; 2669 }; 2670 2671 qup_i2c19_default: qup-i2c19-default-state { 2672 pins = "gpio57", "gpio58"; 2673 function = "qup19"; 2674 drive-strength = <2>; 2675 bias-disable; 2676 }; 2677 2678 qup_spi19_default: qup-spi19-default-state { 2679 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2680 function = "qup19"; 2681 drive-strength = <6>; 2682 bias-disable; 2683 }; 2684 2685 pcie0_default_state: pcie0-default-state { 2686 perst-pins { 2687 pins = "gpio35"; 2688 function = "gpio"; 2689 drive-strength = <2>; 2690 bias-pull-down; 2691 }; 2692 2693 clkreq-pins { 2694 pins = "gpio36"; 2695 function = "pci_e0"; 2696 drive-strength = <2>; 2697 bias-pull-up; 2698 }; 2699 2700 wake-pins { 2701 pins = "gpio37"; 2702 function = "gpio"; 2703 drive-strength = <2>; 2704 bias-pull-up; 2705 }; 2706 }; 2707 2708 pcie1_default_state: pcie1-default-state { 2709 perst-pins { 2710 pins = "gpio102"; 2711 function = "gpio"; 2712 drive-strength = <2>; 2713 bias-pull-down; 2714 }; 2715 2716 clkreq-pins { 2717 pins = "gpio103"; 2718 function = "pci_e1"; 2719 drive-strength = <2>; 2720 bias-pull-up; 2721 }; 2722 2723 wake-pins { 2724 pins = "gpio104"; 2725 function = "gpio"; 2726 drive-strength = <2>; 2727 bias-pull-up; 2728 }; 2729 }; 2730 }; 2731 2732 remoteproc_mpss: remoteproc@4080000 { 2733 compatible = "qcom,sm8150-mpss-pas"; 2734 reg = <0x0 0x04080000 0x0 0x4040>; 2735 2736 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2737 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2738 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2739 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2740 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2741 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2742 interrupt-names = "wdog", "fatal", "ready", "handover", 2743 "stop-ack", "shutdown-ack"; 2744 2745 clocks = <&rpmhcc RPMH_CXO_CLK>; 2746 clock-names = "xo"; 2747 2748 power-domains = <&rpmhpd SM8150_CX>, 2749 <&rpmhpd SM8150_MSS>; 2750 power-domain-names = "cx", "mss"; 2751 2752 memory-region = <&mpss_mem>; 2753 2754 qcom,qmp = <&aoss_qmp>; 2755 2756 qcom,smem-states = <&modem_smp2p_out 0>; 2757 qcom,smem-state-names = "stop"; 2758 2759 status = "disabled"; 2760 2761 glink-edge { 2762 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2763 label = "modem"; 2764 qcom,remote-pid = <1>; 2765 mboxes = <&apss_shared 12>; 2766 }; 2767 }; 2768 2769 stm@6002000 { 2770 compatible = "arm,coresight-stm", "arm,primecell"; 2771 reg = <0 0x06002000 0 0x1000>, 2772 <0 0x16280000 0 0x180000>; 2773 reg-names = "stm-base", "stm-stimulus-base"; 2774 2775 clocks = <&aoss_qmp>; 2776 clock-names = "apb_pclk"; 2777 2778 out-ports { 2779 port { 2780 stm_out: endpoint { 2781 remote-endpoint = <&funnel0_in7>; 2782 }; 2783 }; 2784 }; 2785 }; 2786 2787 funnel@6041000 { 2788 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2789 reg = <0 0x06041000 0 0x1000>; 2790 2791 clocks = <&aoss_qmp>; 2792 clock-names = "apb_pclk"; 2793 2794 out-ports { 2795 port { 2796 funnel0_out: endpoint { 2797 remote-endpoint = <&merge_funnel_in0>; 2798 }; 2799 }; 2800 }; 2801 2802 in-ports { 2803 #address-cells = <1>; 2804 #size-cells = <0>; 2805 2806 port@7 { 2807 reg = <7>; 2808 funnel0_in7: endpoint { 2809 remote-endpoint = <&stm_out>; 2810 }; 2811 }; 2812 }; 2813 }; 2814 2815 funnel@6042000 { 2816 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2817 reg = <0 0x06042000 0 0x1000>; 2818 2819 clocks = <&aoss_qmp>; 2820 clock-names = "apb_pclk"; 2821 2822 out-ports { 2823 port { 2824 funnel1_out: endpoint { 2825 remote-endpoint = <&merge_funnel_in1>; 2826 }; 2827 }; 2828 }; 2829 2830 in-ports { 2831 #address-cells = <1>; 2832 #size-cells = <0>; 2833 2834 port@4 { 2835 reg = <4>; 2836 funnel1_in4: endpoint { 2837 remote-endpoint = <&swao_replicator_out>; 2838 }; 2839 }; 2840 }; 2841 }; 2842 2843 funnel@6043000 { 2844 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2845 reg = <0 0x06043000 0 0x1000>; 2846 2847 clocks = <&aoss_qmp>; 2848 clock-names = "apb_pclk"; 2849 2850 out-ports { 2851 port { 2852 funnel2_out: endpoint { 2853 remote-endpoint = <&merge_funnel_in2>; 2854 }; 2855 }; 2856 }; 2857 2858 in-ports { 2859 #address-cells = <1>; 2860 #size-cells = <0>; 2861 2862 port@2 { 2863 reg = <2>; 2864 funnel2_in2: endpoint { 2865 remote-endpoint = <&apss_merge_funnel_out>; 2866 }; 2867 }; 2868 }; 2869 }; 2870 2871 funnel@6045000 { 2872 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2873 reg = <0 0x06045000 0 0x1000>; 2874 2875 clocks = <&aoss_qmp>; 2876 clock-names = "apb_pclk"; 2877 2878 out-ports { 2879 port { 2880 merge_funnel_out: endpoint { 2881 remote-endpoint = <&etf_in>; 2882 }; 2883 }; 2884 }; 2885 2886 in-ports { 2887 #address-cells = <1>; 2888 #size-cells = <0>; 2889 2890 port@0 { 2891 reg = <0>; 2892 merge_funnel_in0: endpoint { 2893 remote-endpoint = <&funnel0_out>; 2894 }; 2895 }; 2896 2897 port@1 { 2898 reg = <1>; 2899 merge_funnel_in1: endpoint { 2900 remote-endpoint = <&funnel1_out>; 2901 }; 2902 }; 2903 2904 port@2 { 2905 reg = <2>; 2906 merge_funnel_in2: endpoint { 2907 remote-endpoint = <&funnel2_out>; 2908 }; 2909 }; 2910 }; 2911 }; 2912 2913 replicator@6046000 { 2914 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2915 reg = <0 0x06046000 0 0x1000>; 2916 2917 clocks = <&aoss_qmp>; 2918 clock-names = "apb_pclk"; 2919 2920 out-ports { 2921 #address-cells = <1>; 2922 #size-cells = <0>; 2923 2924 port@0 { 2925 reg = <0>; 2926 replicator_out0: endpoint { 2927 remote-endpoint = <&etr_in>; 2928 }; 2929 }; 2930 2931 port@1 { 2932 reg = <1>; 2933 replicator_out1: endpoint { 2934 remote-endpoint = <&replicator1_in>; 2935 }; 2936 }; 2937 }; 2938 2939 in-ports { 2940 port { 2941 replicator_in0: endpoint { 2942 remote-endpoint = <&etf_out>; 2943 }; 2944 }; 2945 }; 2946 }; 2947 2948 etf@6047000 { 2949 compatible = "arm,coresight-tmc", "arm,primecell"; 2950 reg = <0 0x06047000 0 0x1000>; 2951 2952 clocks = <&aoss_qmp>; 2953 clock-names = "apb_pclk"; 2954 2955 out-ports { 2956 port { 2957 etf_out: endpoint { 2958 remote-endpoint = <&replicator_in0>; 2959 }; 2960 }; 2961 }; 2962 2963 in-ports { 2964 port { 2965 etf_in: endpoint { 2966 remote-endpoint = <&merge_funnel_out>; 2967 }; 2968 }; 2969 }; 2970 }; 2971 2972 etr@6048000 { 2973 compatible = "arm,coresight-tmc", "arm,primecell"; 2974 reg = <0 0x06048000 0 0x1000>; 2975 iommus = <&apps_smmu 0x05e0 0x0>; 2976 2977 clocks = <&aoss_qmp>; 2978 clock-names = "apb_pclk"; 2979 arm,scatter-gather; 2980 2981 in-ports { 2982 port { 2983 etr_in: endpoint { 2984 remote-endpoint = <&replicator_out0>; 2985 }; 2986 }; 2987 }; 2988 }; 2989 2990 replicator@604a000 { 2991 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2992 reg = <0 0x0604a000 0 0x1000>; 2993 2994 clocks = <&aoss_qmp>; 2995 clock-names = "apb_pclk"; 2996 2997 out-ports { 2998 #address-cells = <1>; 2999 #size-cells = <0>; 3000 3001 port@1 { 3002 reg = <1>; 3003 replicator1_out: endpoint { 3004 remote-endpoint = <&swao_funnel_in>; 3005 }; 3006 }; 3007 }; 3008 3009 in-ports { 3010 3011 port { 3012 replicator1_in: endpoint { 3013 remote-endpoint = <&replicator_out1>; 3014 }; 3015 }; 3016 }; 3017 }; 3018 3019 funnel@6b08000 { 3020 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3021 reg = <0 0x06b08000 0 0x1000>; 3022 3023 clocks = <&aoss_qmp>; 3024 clock-names = "apb_pclk"; 3025 3026 out-ports { 3027 port { 3028 swao_funnel_out: endpoint { 3029 remote-endpoint = <&swao_etf_in>; 3030 }; 3031 }; 3032 }; 3033 3034 in-ports { 3035 #address-cells = <1>; 3036 #size-cells = <0>; 3037 3038 port@6 { 3039 reg = <6>; 3040 swao_funnel_in: endpoint { 3041 remote-endpoint = <&replicator1_out>; 3042 }; 3043 }; 3044 }; 3045 }; 3046 3047 etf@6b09000 { 3048 compatible = "arm,coresight-tmc", "arm,primecell"; 3049 reg = <0 0x06b09000 0 0x1000>; 3050 3051 clocks = <&aoss_qmp>; 3052 clock-names = "apb_pclk"; 3053 3054 out-ports { 3055 port { 3056 swao_etf_out: endpoint { 3057 remote-endpoint = <&swao_replicator_in>; 3058 }; 3059 }; 3060 }; 3061 3062 in-ports { 3063 port { 3064 swao_etf_in: endpoint { 3065 remote-endpoint = <&swao_funnel_out>; 3066 }; 3067 }; 3068 }; 3069 }; 3070 3071 replicator@6b0a000 { 3072 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3073 reg = <0 0x06b0a000 0 0x1000>; 3074 3075 clocks = <&aoss_qmp>; 3076 clock-names = "apb_pclk"; 3077 qcom,replicator-loses-context; 3078 3079 out-ports { 3080 port { 3081 swao_replicator_out: endpoint { 3082 remote-endpoint = <&funnel1_in4>; 3083 }; 3084 }; 3085 }; 3086 3087 in-ports { 3088 port { 3089 swao_replicator_in: endpoint { 3090 remote-endpoint = <&swao_etf_out>; 3091 }; 3092 }; 3093 }; 3094 }; 3095 3096 etm@7040000 { 3097 compatible = "arm,coresight-etm4x", "arm,primecell"; 3098 reg = <0 0x07040000 0 0x1000>; 3099 3100 cpu = <&cpu0>; 3101 3102 clocks = <&aoss_qmp>; 3103 clock-names = "apb_pclk"; 3104 arm,coresight-loses-context-with-cpu; 3105 qcom,skip-power-up; 3106 3107 out-ports { 3108 port { 3109 etm0_out: endpoint { 3110 remote-endpoint = <&apss_funnel_in0>; 3111 }; 3112 }; 3113 }; 3114 }; 3115 3116 etm@7140000 { 3117 compatible = "arm,coresight-etm4x", "arm,primecell"; 3118 reg = <0 0x07140000 0 0x1000>; 3119 3120 cpu = <&cpu1>; 3121 3122 clocks = <&aoss_qmp>; 3123 clock-names = "apb_pclk"; 3124 arm,coresight-loses-context-with-cpu; 3125 qcom,skip-power-up; 3126 3127 out-ports { 3128 port { 3129 etm1_out: endpoint { 3130 remote-endpoint = <&apss_funnel_in1>; 3131 }; 3132 }; 3133 }; 3134 }; 3135 3136 etm@7240000 { 3137 compatible = "arm,coresight-etm4x", "arm,primecell"; 3138 reg = <0 0x07240000 0 0x1000>; 3139 3140 cpu = <&cpu2>; 3141 3142 clocks = <&aoss_qmp>; 3143 clock-names = "apb_pclk"; 3144 arm,coresight-loses-context-with-cpu; 3145 qcom,skip-power-up; 3146 3147 out-ports { 3148 port { 3149 etm2_out: endpoint { 3150 remote-endpoint = <&apss_funnel_in2>; 3151 }; 3152 }; 3153 }; 3154 }; 3155 3156 etm@7340000 { 3157 compatible = "arm,coresight-etm4x", "arm,primecell"; 3158 reg = <0 0x07340000 0 0x1000>; 3159 3160 cpu = <&cpu3>; 3161 3162 clocks = <&aoss_qmp>; 3163 clock-names = "apb_pclk"; 3164 arm,coresight-loses-context-with-cpu; 3165 qcom,skip-power-up; 3166 3167 out-ports { 3168 port { 3169 etm3_out: endpoint { 3170 remote-endpoint = <&apss_funnel_in3>; 3171 }; 3172 }; 3173 }; 3174 }; 3175 3176 etm@7440000 { 3177 compatible = "arm,coresight-etm4x", "arm,primecell"; 3178 reg = <0 0x07440000 0 0x1000>; 3179 3180 cpu = <&cpu4>; 3181 3182 clocks = <&aoss_qmp>; 3183 clock-names = "apb_pclk"; 3184 arm,coresight-loses-context-with-cpu; 3185 qcom,skip-power-up; 3186 3187 out-ports { 3188 port { 3189 etm4_out: endpoint { 3190 remote-endpoint = <&apss_funnel_in4>; 3191 }; 3192 }; 3193 }; 3194 }; 3195 3196 etm@7540000 { 3197 compatible = "arm,coresight-etm4x", "arm,primecell"; 3198 reg = <0 0x07540000 0 0x1000>; 3199 3200 cpu = <&cpu5>; 3201 3202 clocks = <&aoss_qmp>; 3203 clock-names = "apb_pclk"; 3204 arm,coresight-loses-context-with-cpu; 3205 qcom,skip-power-up; 3206 3207 out-ports { 3208 port { 3209 etm5_out: endpoint { 3210 remote-endpoint = <&apss_funnel_in5>; 3211 }; 3212 }; 3213 }; 3214 }; 3215 3216 etm@7640000 { 3217 compatible = "arm,coresight-etm4x", "arm,primecell"; 3218 reg = <0 0x07640000 0 0x1000>; 3219 3220 cpu = <&cpu6>; 3221 3222 clocks = <&aoss_qmp>; 3223 clock-names = "apb_pclk"; 3224 arm,coresight-loses-context-with-cpu; 3225 qcom,skip-power-up; 3226 3227 out-ports { 3228 port { 3229 etm6_out: endpoint { 3230 remote-endpoint = <&apss_funnel_in6>; 3231 }; 3232 }; 3233 }; 3234 }; 3235 3236 etm@7740000 { 3237 compatible = "arm,coresight-etm4x", "arm,primecell"; 3238 reg = <0 0x07740000 0 0x1000>; 3239 3240 cpu = <&cpu7>; 3241 3242 clocks = <&aoss_qmp>; 3243 clock-names = "apb_pclk"; 3244 arm,coresight-loses-context-with-cpu; 3245 qcom,skip-power-up; 3246 3247 out-ports { 3248 port { 3249 etm7_out: endpoint { 3250 remote-endpoint = <&apss_funnel_in7>; 3251 }; 3252 }; 3253 }; 3254 }; 3255 3256 funnel@7800000 { /* APSS Funnel */ 3257 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3258 reg = <0 0x07800000 0 0x1000>; 3259 3260 clocks = <&aoss_qmp>; 3261 clock-names = "apb_pclk"; 3262 3263 out-ports { 3264 port { 3265 apss_funnel_out: endpoint { 3266 remote-endpoint = <&apss_merge_funnel_in>; 3267 }; 3268 }; 3269 }; 3270 3271 in-ports { 3272 #address-cells = <1>; 3273 #size-cells = <0>; 3274 3275 port@0 { 3276 reg = <0>; 3277 apss_funnel_in0: endpoint { 3278 remote-endpoint = <&etm0_out>; 3279 }; 3280 }; 3281 3282 port@1 { 3283 reg = <1>; 3284 apss_funnel_in1: endpoint { 3285 remote-endpoint = <&etm1_out>; 3286 }; 3287 }; 3288 3289 port@2 { 3290 reg = <2>; 3291 apss_funnel_in2: endpoint { 3292 remote-endpoint = <&etm2_out>; 3293 }; 3294 }; 3295 3296 port@3 { 3297 reg = <3>; 3298 apss_funnel_in3: endpoint { 3299 remote-endpoint = <&etm3_out>; 3300 }; 3301 }; 3302 3303 port@4 { 3304 reg = <4>; 3305 apss_funnel_in4: endpoint { 3306 remote-endpoint = <&etm4_out>; 3307 }; 3308 }; 3309 3310 port@5 { 3311 reg = <5>; 3312 apss_funnel_in5: endpoint { 3313 remote-endpoint = <&etm5_out>; 3314 }; 3315 }; 3316 3317 port@6 { 3318 reg = <6>; 3319 apss_funnel_in6: endpoint { 3320 remote-endpoint = <&etm6_out>; 3321 }; 3322 }; 3323 3324 port@7 { 3325 reg = <7>; 3326 apss_funnel_in7: endpoint { 3327 remote-endpoint = <&etm7_out>; 3328 }; 3329 }; 3330 }; 3331 }; 3332 3333 funnel@7810000 { 3334 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3335 reg = <0 0x07810000 0 0x1000>; 3336 3337 clocks = <&aoss_qmp>; 3338 clock-names = "apb_pclk"; 3339 3340 out-ports { 3341 port { 3342 apss_merge_funnel_out: endpoint { 3343 remote-endpoint = <&funnel2_in2>; 3344 }; 3345 }; 3346 }; 3347 3348 in-ports { 3349 port { 3350 apss_merge_funnel_in: endpoint { 3351 remote-endpoint = <&apss_funnel_out>; 3352 }; 3353 }; 3354 }; 3355 }; 3356 3357 remoteproc_cdsp: remoteproc@8300000 { 3358 compatible = "qcom,sm8150-cdsp-pas"; 3359 reg = <0x0 0x08300000 0x0 0x4040>; 3360 3361 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3362 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3363 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3364 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3365 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3366 interrupt-names = "wdog", "fatal", "ready", 3367 "handover", "stop-ack"; 3368 3369 clocks = <&rpmhcc RPMH_CXO_CLK>; 3370 clock-names = "xo"; 3371 3372 power-domains = <&rpmhpd SM8150_CX>; 3373 3374 memory-region = <&cdsp_mem>; 3375 3376 qcom,qmp = <&aoss_qmp>; 3377 3378 qcom,smem-states = <&cdsp_smp2p_out 0>; 3379 qcom,smem-state-names = "stop"; 3380 3381 status = "disabled"; 3382 3383 glink-edge { 3384 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 3385 label = "cdsp"; 3386 qcom,remote-pid = <5>; 3387 mboxes = <&apss_shared 4>; 3388 3389 fastrpc { 3390 compatible = "qcom,fastrpc"; 3391 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3392 label = "cdsp"; 3393 qcom,non-secure-domain; 3394 #address-cells = <1>; 3395 #size-cells = <0>; 3396 3397 compute-cb@1 { 3398 compatible = "qcom,fastrpc-compute-cb"; 3399 reg = <1>; 3400 iommus = <&apps_smmu 0x1001 0x0460>; 3401 }; 3402 3403 compute-cb@2 { 3404 compatible = "qcom,fastrpc-compute-cb"; 3405 reg = <2>; 3406 iommus = <&apps_smmu 0x1002 0x0460>; 3407 }; 3408 3409 compute-cb@3 { 3410 compatible = "qcom,fastrpc-compute-cb"; 3411 reg = <3>; 3412 iommus = <&apps_smmu 0x1003 0x0460>; 3413 }; 3414 3415 compute-cb@4 { 3416 compatible = "qcom,fastrpc-compute-cb"; 3417 reg = <4>; 3418 iommus = <&apps_smmu 0x1004 0x0460>; 3419 }; 3420 3421 compute-cb@5 { 3422 compatible = "qcom,fastrpc-compute-cb"; 3423 reg = <5>; 3424 iommus = <&apps_smmu 0x1005 0x0460>; 3425 }; 3426 3427 compute-cb@6 { 3428 compatible = "qcom,fastrpc-compute-cb"; 3429 reg = <6>; 3430 iommus = <&apps_smmu 0x1006 0x0460>; 3431 }; 3432 3433 compute-cb@7 { 3434 compatible = "qcom,fastrpc-compute-cb"; 3435 reg = <7>; 3436 iommus = <&apps_smmu 0x1007 0x0460>; 3437 }; 3438 3439 compute-cb@8 { 3440 compatible = "qcom,fastrpc-compute-cb"; 3441 reg = <8>; 3442 iommus = <&apps_smmu 0x1008 0x0460>; 3443 }; 3444 3445 /* note: secure cb9 in downstream */ 3446 }; 3447 }; 3448 }; 3449 3450 usb_1_hsphy: phy@88e2000 { 3451 compatible = "qcom,sm8150-usb-hs-phy", 3452 "qcom,usb-snps-hs-7nm-phy"; 3453 reg = <0 0x088e2000 0 0x400>; 3454 status = "disabled"; 3455 #phy-cells = <0>; 3456 3457 clocks = <&rpmhcc RPMH_CXO_CLK>; 3458 clock-names = "ref"; 3459 3460 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3461 }; 3462 3463 usb_2_hsphy: phy@88e3000 { 3464 compatible = "qcom,sm8150-usb-hs-phy", 3465 "qcom,usb-snps-hs-7nm-phy"; 3466 reg = <0 0x088e3000 0 0x400>; 3467 status = "disabled"; 3468 #phy-cells = <0>; 3469 3470 clocks = <&rpmhcc RPMH_CXO_CLK>; 3471 clock-names = "ref"; 3472 3473 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3474 }; 3475 3476 usb_1_qmpphy: phy@88e8000 { 3477 compatible = "qcom,sm8150-qmp-usb3-dp-phy"; 3478 reg = <0 0x088e8000 0 0x3000>; 3479 3480 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3481 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3482 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3483 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3484 clock-names = "aux", 3485 "ref", 3486 "com_aux", 3487 "usb3_pipe"; 3488 3489 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3490 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3491 reset-names = "phy", "common"; 3492 3493 #clock-cells = <1>; 3494 #phy-cells = <1>; 3495 3496 status = "disabled"; 3497 3498 ports { 3499 #address-cells = <1>; 3500 #size-cells = <0>; 3501 3502 port@0 { 3503 reg = <0>; 3504 3505 usb_1_qmpphy_out: endpoint { 3506 }; 3507 }; 3508 3509 port@1 { 3510 reg = <1>; 3511 3512 usb_1_qmpphy_usb_ss_in: endpoint { 3513 remote-endpoint = <&usb_1_dwc3_ss>; 3514 }; 3515 }; 3516 3517 port@2 { 3518 reg = <2>; 3519 3520 usb_1_qmpphy_dp_in: endpoint { 3521 remote-endpoint = <&mdss_dp_out>; 3522 }; 3523 }; 3524 }; 3525 }; 3526 3527 usb_2_qmpphy: phy@88eb000 { 3528 compatible = "qcom,sm8150-qmp-usb3-uni-phy"; 3529 reg = <0 0x088eb000 0 0x1000>; 3530 3531 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3532 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 3533 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 3534 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3535 clock-names = "aux", 3536 "ref", 3537 "com_aux", 3538 "pipe"; 3539 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3540 #clock-cells = <0>; 3541 #phy-cells = <0>; 3542 3543 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 3544 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 3545 reset-names = "phy", 3546 "phy_phy"; 3547 3548 status = "disabled"; 3549 }; 3550 3551 sdhc_2: mmc@8804000 { 3552 compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5"; 3553 reg = <0 0x08804000 0 0x1000>; 3554 3555 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3556 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3557 interrupt-names = "hc_irq", "pwr_irq"; 3558 3559 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3560 <&gcc GCC_SDCC2_APPS_CLK>, 3561 <&rpmhcc RPMH_CXO_CLK>; 3562 clock-names = "iface", "core", "xo"; 3563 iommus = <&apps_smmu 0x6a0 0x0>; 3564 qcom,dll-config = <0x0007642c>; 3565 qcom,ddr-config = <0x80040868>; 3566 power-domains = <&rpmhpd 0>; 3567 operating-points-v2 = <&sdhc2_opp_table>; 3568 3569 status = "disabled"; 3570 3571 sdhc2_opp_table: opp-table { 3572 compatible = "operating-points-v2"; 3573 3574 opp-19200000 { 3575 opp-hz = /bits/ 64 <19200000>; 3576 required-opps = <&rpmhpd_opp_min_svs>; 3577 }; 3578 3579 opp-50000000 { 3580 opp-hz = /bits/ 64 <50000000>; 3581 required-opps = <&rpmhpd_opp_low_svs>; 3582 }; 3583 3584 opp-100000000 { 3585 opp-hz = /bits/ 64 <100000000>; 3586 required-opps = <&rpmhpd_opp_svs>; 3587 }; 3588 3589 opp-202000000 { 3590 opp-hz = /bits/ 64 <202000000>; 3591 required-opps = <&rpmhpd_opp_svs_l1>; 3592 }; 3593 }; 3594 }; 3595 3596 dc_noc: interconnect@9160000 { 3597 compatible = "qcom,sm8150-dc-noc"; 3598 reg = <0 0x09160000 0 0x3200>; 3599 #interconnect-cells = <2>; 3600 qcom,bcm-voters = <&apps_bcm_voter>; 3601 }; 3602 3603 gem_noc: interconnect@9680000 { 3604 compatible = "qcom,sm8150-gem-noc"; 3605 reg = <0 0x09680000 0 0x3e200>; 3606 #interconnect-cells = <2>; 3607 qcom,bcm-voters = <&apps_bcm_voter>; 3608 }; 3609 3610 usb_1: usb@a6f8800 { 3611 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3612 reg = <0 0x0a6f8800 0 0x400>; 3613 status = "disabled"; 3614 #address-cells = <2>; 3615 #size-cells = <2>; 3616 ranges; 3617 dma-ranges; 3618 3619 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3620 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3621 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3622 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3623 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3624 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3625 clock-names = "cfg_noc", 3626 "core", 3627 "iface", 3628 "sleep", 3629 "mock_utmi", 3630 "xo"; 3631 3632 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3633 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3634 assigned-clock-rates = <19200000>, <200000000>; 3635 3636 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 3637 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3638 <&pdc 9 IRQ_TYPE_EDGE_BOTH>, 3639 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 3640 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; 3641 interrupt-names = "pwr_event", 3642 "hs_phy_irq", 3643 "dp_hs_phy_irq", 3644 "dm_hs_phy_irq", 3645 "ss_phy_irq"; 3646 3647 power-domains = <&gcc USB30_PRIM_GDSC>; 3648 3649 resets = <&gcc GCC_USB30_PRIM_BCR>; 3650 3651 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, 3652 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 3653 interconnect-names = "usb-ddr", "apps-usb"; 3654 3655 usb_1_dwc3: usb@a600000 { 3656 compatible = "snps,dwc3"; 3657 reg = <0 0x0a600000 0 0xcd00>; 3658 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3659 iommus = <&apps_smmu 0x140 0>; 3660 snps,dis_u2_susphy_quirk; 3661 snps,dis_u3_susphy_quirk; 3662 snps,dis_enblslpm_quirk; 3663 snps,dis-u1-entry-quirk; 3664 snps,dis-u2-entry-quirk; 3665 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 3666 phy-names = "usb2-phy", "usb3-phy"; 3667 3668 ports { 3669 #address-cells = <1>; 3670 #size-cells = <0>; 3671 3672 port@0 { 3673 reg = <0>; 3674 3675 usb_1_dwc3_hs: endpoint { 3676 }; 3677 }; 3678 3679 port@1 { 3680 reg = <1>; 3681 3682 usb_1_dwc3_ss: endpoint { 3683 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 3684 }; 3685 }; 3686 }; 3687 }; 3688 }; 3689 3690 usb_2: usb@a8f8800 { 3691 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3692 reg = <0 0x0a8f8800 0 0x400>; 3693 status = "disabled"; 3694 #address-cells = <2>; 3695 #size-cells = <2>; 3696 ranges; 3697 dma-ranges; 3698 3699 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3700 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3701 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3702 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3703 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3704 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3705 clock-names = "cfg_noc", 3706 "core", 3707 "iface", 3708 "sleep", 3709 "mock_utmi", 3710 "xo"; 3711 3712 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3713 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3714 assigned-clock-rates = <19200000>, <200000000>; 3715 3716 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 3717 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3718 <&pdc 11 IRQ_TYPE_EDGE_BOTH>, 3719 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 3720 <&pdc 7 IRQ_TYPE_LEVEL_HIGH>; 3721 interrupt-names = "pwr_event", 3722 "hs_phy_irq", 3723 "dp_hs_phy_irq", 3724 "dm_hs_phy_irq", 3725 "ss_phy_irq"; 3726 3727 power-domains = <&gcc USB30_SEC_GDSC>; 3728 3729 resets = <&gcc GCC_USB30_SEC_BCR>; 3730 3731 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, 3732 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; 3733 interconnect-names = "usb-ddr", "apps-usb"; 3734 3735 usb_2_dwc3: usb@a800000 { 3736 compatible = "snps,dwc3"; 3737 reg = <0 0x0a800000 0 0xcd00>; 3738 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3739 iommus = <&apps_smmu 0x160 0>; 3740 snps,dis_u2_susphy_quirk; 3741 snps,dis_u3_susphy_quirk; 3742 snps,dis_enblslpm_quirk; 3743 snps,dis-u1-entry-quirk; 3744 snps,dis-u2-entry-quirk; 3745 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>; 3746 phy-names = "usb2-phy", "usb3-phy"; 3747 }; 3748 }; 3749 3750 videocc: clock-controller@ab00000 { 3751 compatible = "qcom,sm8150-videocc"; 3752 reg = <0 0x0ab00000 0 0x10000>; 3753 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 3754 <&rpmhcc RPMH_CXO_CLK>; 3755 clock-names = "iface", "bi_tcxo"; 3756 power-domains = <&rpmhpd SM8150_MMCX>; 3757 required-opps = <&rpmhpd_opp_low_svs>; 3758 #clock-cells = <1>; 3759 #reset-cells = <1>; 3760 #power-domain-cells = <1>; 3761 }; 3762 3763 camnoc_virt: interconnect@ac00000 { 3764 compatible = "qcom,sm8150-camnoc-virt"; 3765 reg = <0 0x0ac00000 0 0x1000>; 3766 #interconnect-cells = <2>; 3767 qcom,bcm-voters = <&apps_bcm_voter>; 3768 }; 3769 3770 camcc: clock-controller@ad00000 { 3771 compatible = "qcom,sm8150-camcc"; 3772 reg = <0 0x0ad00000 0 0x10000>; 3773 clocks = <&rpmhcc RPMH_CXO_CLK>, 3774 <&gcc GCC_CAMERA_AHB_CLK>; 3775 power-domains = <&rpmhpd SM8150_MMCX>; 3776 required-opps = <&rpmhpd_opp_low_svs>; 3777 #clock-cells = <1>; 3778 #reset-cells = <1>; 3779 #power-domain-cells = <1>; 3780 }; 3781 3782 mdss: display-subsystem@ae00000 { 3783 compatible = "qcom,sm8150-mdss"; 3784 reg = <0 0x0ae00000 0 0x1000>; 3785 reg-names = "mdss"; 3786 3787 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>, 3788 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>; 3789 interconnect-names = "mdp0-mem", "mdp1-mem"; 3790 3791 power-domains = <&dispcc MDSS_GDSC>; 3792 3793 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3794 <&gcc GCC_DISP_HF_AXI_CLK>, 3795 <&gcc GCC_DISP_SF_AXI_CLK>, 3796 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3797 clock-names = "iface", "bus", "nrt_bus", "core"; 3798 3799 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3800 interrupt-controller; 3801 #interrupt-cells = <1>; 3802 3803 iommus = <&apps_smmu 0x800 0x420>; 3804 3805 status = "disabled"; 3806 3807 #address-cells = <2>; 3808 #size-cells = <2>; 3809 ranges; 3810 3811 mdss_mdp: display-controller@ae01000 { 3812 compatible = "qcom,sm8150-dpu"; 3813 reg = <0 0x0ae01000 0 0x8f000>, 3814 <0 0x0aeb0000 0 0x3000>; 3815 reg-names = "mdp", "vbif"; 3816 3817 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3818 <&gcc GCC_DISP_HF_AXI_CLK>, 3819 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3820 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3821 clock-names = "iface", "bus", "core", "vsync"; 3822 3823 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3824 assigned-clock-rates = <19200000>; 3825 3826 operating-points-v2 = <&mdp_opp_table>; 3827 power-domains = <&rpmhpd SM8150_MMCX>; 3828 3829 interrupt-parent = <&mdss>; 3830 interrupts = <0>; 3831 3832 ports { 3833 #address-cells = <1>; 3834 #size-cells = <0>; 3835 3836 port@0 { 3837 reg = <0>; 3838 dpu_intf1_out: endpoint { 3839 remote-endpoint = <&mdss_dsi0_in>; 3840 }; 3841 }; 3842 3843 port@1 { 3844 reg = <1>; 3845 dpu_intf2_out: endpoint { 3846 remote-endpoint = <&mdss_dsi1_in>; 3847 }; 3848 }; 3849 3850 port@2 { 3851 reg = <2>; 3852 dpu_intf0_out: endpoint { 3853 remote-endpoint = <&mdss_dp_in>; 3854 }; 3855 }; 3856 }; 3857 3858 mdp_opp_table: opp-table { 3859 compatible = "operating-points-v2"; 3860 3861 opp-171428571 { 3862 opp-hz = /bits/ 64 <171428571>; 3863 required-opps = <&rpmhpd_opp_low_svs>; 3864 }; 3865 3866 opp-300000000 { 3867 opp-hz = /bits/ 64 <300000000>; 3868 required-opps = <&rpmhpd_opp_svs>; 3869 }; 3870 3871 opp-345000000 { 3872 opp-hz = /bits/ 64 <345000000>; 3873 required-opps = <&rpmhpd_opp_svs_l1>; 3874 }; 3875 3876 opp-460000000 { 3877 opp-hz = /bits/ 64 <460000000>; 3878 required-opps = <&rpmhpd_opp_nom>; 3879 }; 3880 }; 3881 }; 3882 3883 mdss_dp: displayport-controller@ae90000 { 3884 compatible = "qcom,sm8150-dp", "qcom,sm8350-dp"; 3885 reg = <0 0xae90000 0 0x200>, 3886 <0 0xae90200 0 0x200>, 3887 <0 0xae90400 0 0x600>, 3888 <0 0x0ae90a00 0 0x600>, 3889 <0 0x0ae91000 0 0x600>; 3890 3891 interrupt-parent = <&mdss>; 3892 interrupts = <12>; 3893 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3894 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3895 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3896 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3897 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3898 clock-names = "core_iface", 3899 "core_aux", 3900 "ctrl_link", 3901 "ctrl_link_iface", 3902 "stream_pixel"; 3903 3904 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3905 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3906 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3907 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3908 3909 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 3910 phy-names = "dp"; 3911 3912 #sound-dai-cells = <0>; 3913 3914 operating-points-v2 = <&dp_opp_table>; 3915 power-domains = <&rpmhpd SM8250_MMCX>; 3916 3917 status = "disabled"; 3918 3919 ports { 3920 #address-cells = <1>; 3921 #size-cells = <0>; 3922 3923 port@0 { 3924 reg = <0>; 3925 mdss_dp_in: endpoint { 3926 remote-endpoint = <&dpu_intf0_out>; 3927 }; 3928 }; 3929 3930 port@1 { 3931 reg = <1>; 3932 3933 mdss_dp_out: endpoint { 3934 remote-endpoint = <&usb_1_qmpphy_dp_in>; 3935 }; 3936 }; 3937 }; 3938 3939 dp_opp_table: opp-table { 3940 compatible = "operating-points-v2"; 3941 3942 opp-160000000 { 3943 opp-hz = /bits/ 64 <160000000>; 3944 required-opps = <&rpmhpd_opp_low_svs>; 3945 }; 3946 3947 opp-270000000 { 3948 opp-hz = /bits/ 64 <270000000>; 3949 required-opps = <&rpmhpd_opp_svs>; 3950 }; 3951 3952 opp-540000000 { 3953 opp-hz = /bits/ 64 <540000000>; 3954 required-opps = <&rpmhpd_opp_svs_l1>; 3955 }; 3956 3957 opp-810000000 { 3958 opp-hz = /bits/ 64 <810000000>; 3959 required-opps = <&rpmhpd_opp_nom>; 3960 }; 3961 }; 3962 }; 3963 3964 mdss_dsi0: dsi@ae94000 { 3965 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3966 reg = <0 0x0ae94000 0 0x400>; 3967 reg-names = "dsi_ctrl"; 3968 3969 interrupt-parent = <&mdss>; 3970 interrupts = <4>; 3971 3972 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3973 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3974 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3975 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3976 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3977 <&gcc GCC_DISP_HF_AXI_CLK>; 3978 clock-names = "byte", 3979 "byte_intf", 3980 "pixel", 3981 "core", 3982 "iface", 3983 "bus"; 3984 3985 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 3986 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3987 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 3988 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 3989 3990 operating-points-v2 = <&dsi_opp_table>; 3991 power-domains = <&rpmhpd SM8150_MMCX>; 3992 3993 phys = <&mdss_dsi0_phy>; 3994 3995 status = "disabled"; 3996 3997 #address-cells = <1>; 3998 #size-cells = <0>; 3999 4000 ports { 4001 #address-cells = <1>; 4002 #size-cells = <0>; 4003 4004 port@0 { 4005 reg = <0>; 4006 mdss_dsi0_in: endpoint { 4007 remote-endpoint = <&dpu_intf1_out>; 4008 }; 4009 }; 4010 4011 port@1 { 4012 reg = <1>; 4013 mdss_dsi0_out: endpoint { 4014 }; 4015 }; 4016 }; 4017 4018 dsi_opp_table: opp-table { 4019 compatible = "operating-points-v2"; 4020 4021 opp-187500000 { 4022 opp-hz = /bits/ 64 <187500000>; 4023 required-opps = <&rpmhpd_opp_low_svs>; 4024 }; 4025 4026 opp-300000000 { 4027 opp-hz = /bits/ 64 <300000000>; 4028 required-opps = <&rpmhpd_opp_svs>; 4029 }; 4030 4031 opp-358000000 { 4032 opp-hz = /bits/ 64 <358000000>; 4033 required-opps = <&rpmhpd_opp_svs_l1>; 4034 }; 4035 }; 4036 }; 4037 4038 mdss_dsi0_phy: phy@ae94400 { 4039 compatible = "qcom,dsi-phy-7nm-8150"; 4040 reg = <0 0x0ae94400 0 0x200>, 4041 <0 0x0ae94600 0 0x280>, 4042 <0 0x0ae94900 0 0x260>; 4043 reg-names = "dsi_phy", 4044 "dsi_phy_lane", 4045 "dsi_pll"; 4046 4047 #clock-cells = <1>; 4048 #phy-cells = <0>; 4049 4050 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4051 <&rpmhcc RPMH_CXO_CLK>; 4052 clock-names = "iface", "ref"; 4053 4054 status = "disabled"; 4055 }; 4056 4057 mdss_dsi1: dsi@ae96000 { 4058 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 4059 reg = <0 0x0ae96000 0 0x400>; 4060 reg-names = "dsi_ctrl"; 4061 4062 interrupt-parent = <&mdss>; 4063 interrupts = <5>; 4064 4065 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 4066 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 4067 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 4068 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 4069 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4070 <&gcc GCC_DISP_HF_AXI_CLK>; 4071 clock-names = "byte", 4072 "byte_intf", 4073 "pixel", 4074 "core", 4075 "iface", 4076 "bus"; 4077 4078 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 4079 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 4080 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 4081 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 4082 4083 operating-points-v2 = <&dsi_opp_table>; 4084 power-domains = <&rpmhpd SM8150_MMCX>; 4085 4086 phys = <&mdss_dsi1_phy>; 4087 4088 status = "disabled"; 4089 4090 #address-cells = <1>; 4091 #size-cells = <0>; 4092 4093 ports { 4094 #address-cells = <1>; 4095 #size-cells = <0>; 4096 4097 port@0 { 4098 reg = <0>; 4099 mdss_dsi1_in: endpoint { 4100 remote-endpoint = <&dpu_intf2_out>; 4101 }; 4102 }; 4103 4104 port@1 { 4105 reg = <1>; 4106 mdss_dsi1_out: endpoint { 4107 }; 4108 }; 4109 }; 4110 }; 4111 4112 mdss_dsi1_phy: phy@ae96400 { 4113 compatible = "qcom,dsi-phy-7nm-8150"; 4114 reg = <0 0x0ae96400 0 0x200>, 4115 <0 0x0ae96600 0 0x280>, 4116 <0 0x0ae96900 0 0x260>; 4117 reg-names = "dsi_phy", 4118 "dsi_phy_lane", 4119 "dsi_pll"; 4120 4121 #clock-cells = <1>; 4122 #phy-cells = <0>; 4123 4124 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4125 <&rpmhcc RPMH_CXO_CLK>; 4126 clock-names = "iface", "ref"; 4127 4128 status = "disabled"; 4129 }; 4130 }; 4131 4132 dispcc: clock-controller@af00000 { 4133 compatible = "qcom,sm8150-dispcc"; 4134 reg = <0 0x0af00000 0 0x10000>; 4135 clocks = <&rpmhcc RPMH_CXO_CLK>, 4136 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 4137 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 4138 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 4139 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 4140 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4141 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4142 clock-names = "bi_tcxo", 4143 "dsi0_phy_pll_out_byteclk", 4144 "dsi0_phy_pll_out_dsiclk", 4145 "dsi1_phy_pll_out_byteclk", 4146 "dsi1_phy_pll_out_dsiclk", 4147 "dp_phy_pll_link_clk", 4148 "dp_phy_pll_vco_div_clk"; 4149 power-domains = <&rpmhpd SM8150_MMCX>; 4150 required-opps = <&rpmhpd_opp_low_svs>; 4151 #clock-cells = <1>; 4152 #reset-cells = <1>; 4153 #power-domain-cells = <1>; 4154 }; 4155 4156 pdc: interrupt-controller@b220000 { 4157 compatible = "qcom,sm8150-pdc", "qcom,pdc"; 4158 reg = <0 0x0b220000 0 0x30000>; 4159 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 4160 <125 63 1>; 4161 #interrupt-cells = <2>; 4162 interrupt-parent = <&intc>; 4163 interrupt-controller; 4164 }; 4165 4166 aoss_qmp: power-management@c300000 { 4167 compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp"; 4168 reg = <0x0 0x0c300000 0x0 0x400>; 4169 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 4170 mboxes = <&apss_shared 0>; 4171 4172 #clock-cells = <0>; 4173 }; 4174 4175 sram@c3f0000 { 4176 compatible = "qcom,rpmh-stats"; 4177 reg = <0 0x0c3f0000 0 0x400>; 4178 }; 4179 4180 tsens0: thermal-sensor@c263000 { 4181 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 4182 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4183 <0 0x0c222000 0 0x1ff>; /* SROT */ 4184 #qcom,sensors = <16>; 4185 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4186 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4187 interrupt-names = "uplow", "critical"; 4188 #thermal-sensor-cells = <1>; 4189 }; 4190 4191 tsens1: thermal-sensor@c265000 { 4192 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 4193 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4194 <0 0x0c223000 0 0x1ff>; /* SROT */ 4195 #qcom,sensors = <8>; 4196 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4197 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4198 interrupt-names = "uplow", "critical"; 4199 #thermal-sensor-cells = <1>; 4200 }; 4201 4202 spmi_bus: spmi@c440000 { 4203 compatible = "qcom,spmi-pmic-arb"; 4204 reg = <0x0 0x0c440000 0x0 0x0001100>, 4205 <0x0 0x0c600000 0x0 0x2000000>, 4206 <0x0 0x0e600000 0x0 0x0100000>, 4207 <0x0 0x0e700000 0x0 0x00a0000>, 4208 <0x0 0x0c40a000 0x0 0x0026000>; 4209 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4210 interrupt-names = "periph_irq"; 4211 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 4212 qcom,ee = <0>; 4213 qcom,channel = <0>; 4214 #address-cells = <2>; 4215 #size-cells = <0>; 4216 interrupt-controller; 4217 #interrupt-cells = <4>; 4218 }; 4219 4220 apps_smmu: iommu@15000000 { 4221 compatible = "qcom,sm8150-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 4222 reg = <0 0x15000000 0 0x100000>; 4223 #iommu-cells = <2>; 4224 #global-interrupts = <1>; 4225 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4226 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4227 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4228 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4229 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4230 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4231 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4232 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4233 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4234 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4235 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4236 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4237 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4238 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4239 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4240 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4241 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4242 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4243 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4244 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4245 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4246 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4247 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4248 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4249 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4250 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4251 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4252 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4253 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4254 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4255 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4256 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4257 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4258 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4259 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4260 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4261 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4262 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4263 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4264 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4265 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4266 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4267 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4268 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4269 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4270 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4271 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4272 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4273 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4274 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4275 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4276 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4277 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4278 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4279 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4280 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4281 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4282 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4283 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4284 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4285 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4286 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4287 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4288 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4289 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4290 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4291 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4292 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4293 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4294 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4295 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4296 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4297 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4298 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4299 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4300 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4301 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4302 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4303 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4304 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4305 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 4306 dma-coherent; 4307 }; 4308 4309 remoteproc_adsp: remoteproc@17300000 { 4310 compatible = "qcom,sm8150-adsp-pas"; 4311 reg = <0x0 0x17300000 0x0 0x4040>; 4312 4313 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 4314 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4315 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 4316 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 4317 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 4318 interrupt-names = "wdog", "fatal", "ready", 4319 "handover", "stop-ack"; 4320 4321 clocks = <&rpmhcc RPMH_CXO_CLK>; 4322 clock-names = "xo"; 4323 4324 power-domains = <&rpmhpd SM8150_CX>; 4325 4326 memory-region = <&adsp_mem>; 4327 4328 qcom,qmp = <&aoss_qmp>; 4329 4330 qcom,smem-states = <&adsp_smp2p_out 0>; 4331 qcom,smem-state-names = "stop"; 4332 4333 status = "disabled"; 4334 4335 glink-edge { 4336 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 4337 label = "lpass"; 4338 qcom,remote-pid = <2>; 4339 mboxes = <&apss_shared 8>; 4340 4341 fastrpc { 4342 compatible = "qcom,fastrpc"; 4343 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4344 label = "adsp"; 4345 qcom,non-secure-domain; 4346 #address-cells = <1>; 4347 #size-cells = <0>; 4348 4349 compute-cb@3 { 4350 compatible = "qcom,fastrpc-compute-cb"; 4351 reg = <3>; 4352 iommus = <&apps_smmu 0x1b23 0x0>; 4353 }; 4354 4355 compute-cb@4 { 4356 compatible = "qcom,fastrpc-compute-cb"; 4357 reg = <4>; 4358 iommus = <&apps_smmu 0x1b24 0x0>; 4359 }; 4360 4361 compute-cb@5 { 4362 compatible = "qcom,fastrpc-compute-cb"; 4363 reg = <5>; 4364 iommus = <&apps_smmu 0x1b25 0x0>; 4365 }; 4366 }; 4367 }; 4368 }; 4369 4370 intc: interrupt-controller@17a00000 { 4371 compatible = "arm,gic-v3"; 4372 interrupt-controller; 4373 #interrupt-cells = <3>; 4374 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4375 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4376 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4377 }; 4378 4379 apss_shared: mailbox@17c00000 { 4380 compatible = "qcom,sm8150-apss-shared", 4381 "qcom,sdm845-apss-shared"; 4382 reg = <0x0 0x17c00000 0x0 0x1000>; 4383 #mbox-cells = <1>; 4384 }; 4385 4386 watchdog@17c10000 { 4387 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; 4388 reg = <0 0x17c10000 0 0x1000>; 4389 clocks = <&sleep_clk>; 4390 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 4391 }; 4392 4393 timer@17c20000 { 4394 #address-cells = <1>; 4395 #size-cells = <1>; 4396 ranges = <0 0 0 0x20000000>; 4397 compatible = "arm,armv7-timer-mem"; 4398 reg = <0x0 0x17c20000 0x0 0x1000>; 4399 clock-frequency = <19200000>; 4400 4401 frame@17c21000 { 4402 frame-number = <0>; 4403 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4404 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4405 reg = <0x17c21000 0x1000>, 4406 <0x17c22000 0x1000>; 4407 }; 4408 4409 frame@17c23000 { 4410 frame-number = <1>; 4411 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4412 reg = <0x17c23000 0x1000>; 4413 status = "disabled"; 4414 }; 4415 4416 frame@17c25000 { 4417 frame-number = <2>; 4418 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4419 reg = <0x17c25000 0x1000>; 4420 status = "disabled"; 4421 }; 4422 4423 frame@17c27000 { 4424 frame-number = <3>; 4425 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4426 reg = <0x17c26000 0x1000>; 4427 status = "disabled"; 4428 }; 4429 4430 frame@17c29000 { 4431 frame-number = <4>; 4432 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4433 reg = <0x17c29000 0x1000>; 4434 status = "disabled"; 4435 }; 4436 4437 frame@17c2b000 { 4438 frame-number = <5>; 4439 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4440 reg = <0x17c2b000 0x1000>; 4441 status = "disabled"; 4442 }; 4443 4444 frame@17c2d000 { 4445 frame-number = <6>; 4446 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4447 reg = <0x17c2d000 0x1000>; 4448 status = "disabled"; 4449 }; 4450 }; 4451 4452 apps_rsc: rsc@18200000 { 4453 label = "apps_rsc"; 4454 compatible = "qcom,rpmh-rsc"; 4455 reg = <0x0 0x18200000 0x0 0x10000>, 4456 <0x0 0x18210000 0x0 0x10000>, 4457 <0x0 0x18220000 0x0 0x10000>; 4458 reg-names = "drv-0", "drv-1", "drv-2"; 4459 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4460 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4461 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4462 qcom,tcs-offset = <0xd00>; 4463 qcom,drv-id = <2>; 4464 qcom,tcs-config = <ACTIVE_TCS 2>, 4465 <SLEEP_TCS 3>, 4466 <WAKE_TCS 3>, 4467 <CONTROL_TCS 1>; 4468 power-domains = <&cluster_pd>; 4469 4470 rpmhcc: clock-controller { 4471 compatible = "qcom,sm8150-rpmh-clk"; 4472 #clock-cells = <1>; 4473 clock-names = "xo"; 4474 clocks = <&xo_board>; 4475 }; 4476 4477 rpmhpd: power-controller { 4478 compatible = "qcom,sm8150-rpmhpd"; 4479 #power-domain-cells = <1>; 4480 operating-points-v2 = <&rpmhpd_opp_table>; 4481 4482 rpmhpd_opp_table: opp-table { 4483 compatible = "operating-points-v2"; 4484 4485 rpmhpd_opp_ret: opp1 { 4486 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4487 }; 4488 4489 rpmhpd_opp_min_svs: opp2 { 4490 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4491 }; 4492 4493 rpmhpd_opp_low_svs: opp3 { 4494 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4495 }; 4496 4497 rpmhpd_opp_svs: opp4 { 4498 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4499 }; 4500 4501 rpmhpd_opp_svs_l1: opp5 { 4502 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4503 }; 4504 4505 rpmhpd_opp_svs_l2: opp6 { 4506 opp-level = <224>; 4507 }; 4508 4509 rpmhpd_opp_nom: opp7 { 4510 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4511 }; 4512 4513 rpmhpd_opp_nom_l1: opp8 { 4514 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4515 }; 4516 4517 rpmhpd_opp_nom_l2: opp9 { 4518 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4519 }; 4520 4521 rpmhpd_opp_turbo: opp10 { 4522 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4523 }; 4524 4525 rpmhpd_opp_turbo_l1: opp11 { 4526 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4527 }; 4528 }; 4529 }; 4530 4531 apps_bcm_voter: bcm-voter { 4532 compatible = "qcom,bcm-voter"; 4533 }; 4534 }; 4535 4536 osm_l3: interconnect@18321000 { 4537 compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3"; 4538 reg = <0 0x18321000 0 0x1400>; 4539 4540 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4541 clock-names = "xo", "alternate"; 4542 4543 #interconnect-cells = <1>; 4544 }; 4545 4546 cpufreq_hw: cpufreq@18323000 { 4547 compatible = "qcom,sm8150-cpufreq-hw", "qcom,cpufreq-hw"; 4548 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, 4549 <0 0x18327800 0 0x1400>; 4550 reg-names = "freq-domain0", "freq-domain1", 4551 "freq-domain2"; 4552 4553 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4554 clock-names = "xo", "alternate"; 4555 4556 #freq-domain-cells = <1>; 4557 #clock-cells = <1>; 4558 }; 4559 4560 lmh_cluster1: lmh@18350800 { 4561 compatible = "qcom,sm8150-lmh"; 4562 reg = <0 0x18350800 0 0x400>; 4563 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 4564 cpus = <&cpu4>; 4565 qcom,lmh-temp-arm-millicelsius = <60000>; 4566 qcom,lmh-temp-low-millicelsius = <84500>; 4567 qcom,lmh-temp-high-millicelsius = <85000>; 4568 interrupt-controller; 4569 #interrupt-cells = <1>; 4570 }; 4571 4572 lmh_cluster0: lmh@18358800 { 4573 compatible = "qcom,sm8150-lmh"; 4574 reg = <0 0x18358800 0 0x400>; 4575 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 4576 cpus = <&cpu0>; 4577 qcom,lmh-temp-arm-millicelsius = <60000>; 4578 qcom,lmh-temp-low-millicelsius = <84500>; 4579 qcom,lmh-temp-high-millicelsius = <85000>; 4580 interrupt-controller; 4581 #interrupt-cells = <1>; 4582 }; 4583 4584 wifi: wifi@18800000 { 4585 compatible = "qcom,wcn3990-wifi"; 4586 reg = <0 0x18800000 0 0x800000>; 4587 reg-names = "membase"; 4588 memory-region = <&wlan_mem>; 4589 clock-names = "cxo_ref_clk_pin", "qdss"; 4590 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; 4591 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 4592 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 4593 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 4594 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 4595 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4596 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4597 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 4598 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4599 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4600 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4601 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4602 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 4603 iommus = <&apps_smmu 0x0640 0x1>; 4604 status = "disabled"; 4605 }; 4606 }; 4607 4608 timer { 4609 compatible = "arm,armv8-timer"; 4610 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4611 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4612 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4613 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4614 }; 4615 4616 thermal-zones { 4617 cpu0-thermal { 4618 polling-delay-passive = <250>; 4619 4620 thermal-sensors = <&tsens0 1>; 4621 4622 trips { 4623 cpu0_alert0: trip-point0 { 4624 temperature = <90000>; 4625 hysteresis = <2000>; 4626 type = "passive"; 4627 }; 4628 4629 cpu0_alert1: trip-point1 { 4630 temperature = <95000>; 4631 hysteresis = <2000>; 4632 type = "passive"; 4633 }; 4634 4635 cpu0_crit: cpu-crit { 4636 temperature = <110000>; 4637 hysteresis = <1000>; 4638 type = "critical"; 4639 }; 4640 }; 4641 4642 cooling-maps { 4643 map0 { 4644 trip = <&cpu0_alert0>; 4645 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4646 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4647 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4648 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4649 }; 4650 map1 { 4651 trip = <&cpu0_alert1>; 4652 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4653 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4654 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4655 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4656 }; 4657 }; 4658 }; 4659 4660 cpu1-thermal { 4661 polling-delay-passive = <250>; 4662 4663 thermal-sensors = <&tsens0 2>; 4664 4665 trips { 4666 cpu1_alert0: trip-point0 { 4667 temperature = <90000>; 4668 hysteresis = <2000>; 4669 type = "passive"; 4670 }; 4671 4672 cpu1_alert1: trip-point1 { 4673 temperature = <95000>; 4674 hysteresis = <2000>; 4675 type = "passive"; 4676 }; 4677 4678 cpu1_crit: cpu-crit { 4679 temperature = <110000>; 4680 hysteresis = <1000>; 4681 type = "critical"; 4682 }; 4683 }; 4684 4685 cooling-maps { 4686 map0 { 4687 trip = <&cpu1_alert0>; 4688 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4689 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4690 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4691 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4692 }; 4693 map1 { 4694 trip = <&cpu1_alert1>; 4695 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4696 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4697 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4698 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4699 }; 4700 }; 4701 }; 4702 4703 cpu2-thermal { 4704 polling-delay-passive = <250>; 4705 4706 thermal-sensors = <&tsens0 3>; 4707 4708 trips { 4709 cpu2_alert0: trip-point0 { 4710 temperature = <90000>; 4711 hysteresis = <2000>; 4712 type = "passive"; 4713 }; 4714 4715 cpu2_alert1: trip-point1 { 4716 temperature = <95000>; 4717 hysteresis = <2000>; 4718 type = "passive"; 4719 }; 4720 4721 cpu2_crit: cpu-crit { 4722 temperature = <110000>; 4723 hysteresis = <1000>; 4724 type = "critical"; 4725 }; 4726 }; 4727 4728 cooling-maps { 4729 map0 { 4730 trip = <&cpu2_alert0>; 4731 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4732 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4733 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4734 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4735 }; 4736 map1 { 4737 trip = <&cpu2_alert1>; 4738 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4739 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4740 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4741 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4742 }; 4743 }; 4744 }; 4745 4746 cpu3-thermal { 4747 polling-delay-passive = <250>; 4748 4749 thermal-sensors = <&tsens0 4>; 4750 4751 trips { 4752 cpu3_alert0: trip-point0 { 4753 temperature = <90000>; 4754 hysteresis = <2000>; 4755 type = "passive"; 4756 }; 4757 4758 cpu3_alert1: trip-point1 { 4759 temperature = <95000>; 4760 hysteresis = <2000>; 4761 type = "passive"; 4762 }; 4763 4764 cpu3_crit: cpu-crit { 4765 temperature = <110000>; 4766 hysteresis = <1000>; 4767 type = "critical"; 4768 }; 4769 }; 4770 4771 cooling-maps { 4772 map0 { 4773 trip = <&cpu3_alert0>; 4774 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4775 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4776 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4777 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4778 }; 4779 map1 { 4780 trip = <&cpu3_alert1>; 4781 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4782 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4783 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4784 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4785 }; 4786 }; 4787 }; 4788 4789 cpu4-top-thermal { 4790 polling-delay-passive = <250>; 4791 4792 thermal-sensors = <&tsens0 7>; 4793 4794 trips { 4795 cpu4_top_alert0: trip-point0 { 4796 temperature = <90000>; 4797 hysteresis = <2000>; 4798 type = "passive"; 4799 }; 4800 4801 cpu4_top_alert1: trip-point1 { 4802 temperature = <95000>; 4803 hysteresis = <2000>; 4804 type = "passive"; 4805 }; 4806 4807 cpu4_top_crit: cpu-crit { 4808 temperature = <110000>; 4809 hysteresis = <1000>; 4810 type = "critical"; 4811 }; 4812 }; 4813 4814 cooling-maps { 4815 map0 { 4816 trip = <&cpu4_top_alert0>; 4817 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4818 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4819 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4820 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4821 }; 4822 map1 { 4823 trip = <&cpu4_top_alert1>; 4824 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4825 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4826 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4827 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4828 }; 4829 }; 4830 }; 4831 4832 cpu5-top-thermal { 4833 polling-delay-passive = <250>; 4834 4835 thermal-sensors = <&tsens0 8>; 4836 4837 trips { 4838 cpu5_top_alert0: trip-point0 { 4839 temperature = <90000>; 4840 hysteresis = <2000>; 4841 type = "passive"; 4842 }; 4843 4844 cpu5_top_alert1: trip-point1 { 4845 temperature = <95000>; 4846 hysteresis = <2000>; 4847 type = "passive"; 4848 }; 4849 4850 cpu5_top_crit: cpu-crit { 4851 temperature = <110000>; 4852 hysteresis = <1000>; 4853 type = "critical"; 4854 }; 4855 }; 4856 4857 cooling-maps { 4858 map0 { 4859 trip = <&cpu5_top_alert0>; 4860 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4861 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4862 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4863 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4864 }; 4865 map1 { 4866 trip = <&cpu5_top_alert1>; 4867 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4868 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4869 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4870 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4871 }; 4872 }; 4873 }; 4874 4875 cpu6-top-thermal { 4876 polling-delay-passive = <250>; 4877 4878 thermal-sensors = <&tsens0 9>; 4879 4880 trips { 4881 cpu6_top_alert0: trip-point0 { 4882 temperature = <90000>; 4883 hysteresis = <2000>; 4884 type = "passive"; 4885 }; 4886 4887 cpu6_top_alert1: trip-point1 { 4888 temperature = <95000>; 4889 hysteresis = <2000>; 4890 type = "passive"; 4891 }; 4892 4893 cpu6_top_crit: cpu-crit { 4894 temperature = <110000>; 4895 hysteresis = <1000>; 4896 type = "critical"; 4897 }; 4898 }; 4899 4900 cooling-maps { 4901 map0 { 4902 trip = <&cpu6_top_alert0>; 4903 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4904 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4905 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4906 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4907 }; 4908 map1 { 4909 trip = <&cpu6_top_alert1>; 4910 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4911 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4912 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4913 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4914 }; 4915 }; 4916 }; 4917 4918 cpu7-top-thermal { 4919 polling-delay-passive = <250>; 4920 4921 thermal-sensors = <&tsens0 10>; 4922 4923 trips { 4924 cpu7_top_alert0: trip-point0 { 4925 temperature = <90000>; 4926 hysteresis = <2000>; 4927 type = "passive"; 4928 }; 4929 4930 cpu7_top_alert1: trip-point1 { 4931 temperature = <95000>; 4932 hysteresis = <2000>; 4933 type = "passive"; 4934 }; 4935 4936 cpu7_top_crit: cpu-crit { 4937 temperature = <110000>; 4938 hysteresis = <1000>; 4939 type = "critical"; 4940 }; 4941 }; 4942 4943 cooling-maps { 4944 map0 { 4945 trip = <&cpu7_top_alert0>; 4946 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4947 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4948 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4949 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4950 }; 4951 map1 { 4952 trip = <&cpu7_top_alert1>; 4953 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4954 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4955 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4956 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4957 }; 4958 }; 4959 }; 4960 4961 cpu4-bottom-thermal { 4962 polling-delay-passive = <250>; 4963 4964 thermal-sensors = <&tsens0 11>; 4965 4966 trips { 4967 cpu4_bottom_alert0: trip-point0 { 4968 temperature = <90000>; 4969 hysteresis = <2000>; 4970 type = "passive"; 4971 }; 4972 4973 cpu4_bottom_alert1: trip-point1 { 4974 temperature = <95000>; 4975 hysteresis = <2000>; 4976 type = "passive"; 4977 }; 4978 4979 cpu4_bottom_crit: cpu-crit { 4980 temperature = <110000>; 4981 hysteresis = <1000>; 4982 type = "critical"; 4983 }; 4984 }; 4985 4986 cooling-maps { 4987 map0 { 4988 trip = <&cpu4_bottom_alert0>; 4989 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4990 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4991 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4992 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4993 }; 4994 map1 { 4995 trip = <&cpu4_bottom_alert1>; 4996 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4997 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4998 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4999 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5000 }; 5001 }; 5002 }; 5003 5004 cpu5-bottom-thermal { 5005 polling-delay-passive = <250>; 5006 5007 thermal-sensors = <&tsens0 12>; 5008 5009 trips { 5010 cpu5_bottom_alert0: trip-point0 { 5011 temperature = <90000>; 5012 hysteresis = <2000>; 5013 type = "passive"; 5014 }; 5015 5016 cpu5_bottom_alert1: trip-point1 { 5017 temperature = <95000>; 5018 hysteresis = <2000>; 5019 type = "passive"; 5020 }; 5021 5022 cpu5_bottom_crit: cpu-crit { 5023 temperature = <110000>; 5024 hysteresis = <1000>; 5025 type = "critical"; 5026 }; 5027 }; 5028 5029 cooling-maps { 5030 map0 { 5031 trip = <&cpu5_bottom_alert0>; 5032 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5033 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5034 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5035 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5036 }; 5037 map1 { 5038 trip = <&cpu5_bottom_alert1>; 5039 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5040 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5041 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5042 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5043 }; 5044 }; 5045 }; 5046 5047 cpu6-bottom-thermal { 5048 polling-delay-passive = <250>; 5049 5050 thermal-sensors = <&tsens0 13>; 5051 5052 trips { 5053 cpu6_bottom_alert0: trip-point0 { 5054 temperature = <90000>; 5055 hysteresis = <2000>; 5056 type = "passive"; 5057 }; 5058 5059 cpu6_bottom_alert1: trip-point1 { 5060 temperature = <95000>; 5061 hysteresis = <2000>; 5062 type = "passive"; 5063 }; 5064 5065 cpu6_bottom_crit: cpu-crit { 5066 temperature = <110000>; 5067 hysteresis = <1000>; 5068 type = "critical"; 5069 }; 5070 }; 5071 5072 cooling-maps { 5073 map0 { 5074 trip = <&cpu6_bottom_alert0>; 5075 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5076 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5077 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5078 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5079 }; 5080 map1 { 5081 trip = <&cpu6_bottom_alert1>; 5082 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5083 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5084 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5085 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5086 }; 5087 }; 5088 }; 5089 5090 cpu7-bottom-thermal { 5091 polling-delay-passive = <250>; 5092 5093 thermal-sensors = <&tsens0 14>; 5094 5095 trips { 5096 cpu7_bottom_alert0: trip-point0 { 5097 temperature = <90000>; 5098 hysteresis = <2000>; 5099 type = "passive"; 5100 }; 5101 5102 cpu7_bottom_alert1: trip-point1 { 5103 temperature = <95000>; 5104 hysteresis = <2000>; 5105 type = "passive"; 5106 }; 5107 5108 cpu7_bottom_crit: cpu-crit { 5109 temperature = <110000>; 5110 hysteresis = <1000>; 5111 type = "critical"; 5112 }; 5113 }; 5114 5115 cooling-maps { 5116 map0 { 5117 trip = <&cpu7_bottom_alert0>; 5118 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5119 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5120 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5121 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5122 }; 5123 map1 { 5124 trip = <&cpu7_bottom_alert1>; 5125 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5126 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5127 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5128 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5129 }; 5130 }; 5131 }; 5132 5133 aoss0-thermal { 5134 polling-delay-passive = <250>; 5135 5136 thermal-sensors = <&tsens0 0>; 5137 5138 trips { 5139 aoss0_alert0: trip-point0 { 5140 temperature = <90000>; 5141 hysteresis = <2000>; 5142 type = "hot"; 5143 }; 5144 }; 5145 }; 5146 5147 cluster0-thermal { 5148 polling-delay-passive = <250>; 5149 5150 thermal-sensors = <&tsens0 5>; 5151 5152 trips { 5153 cluster0_alert0: trip-point0 { 5154 temperature = <90000>; 5155 hysteresis = <2000>; 5156 type = "hot"; 5157 }; 5158 cluster0_crit: cluster0-crit { 5159 temperature = <110000>; 5160 hysteresis = <2000>; 5161 type = "critical"; 5162 }; 5163 }; 5164 }; 5165 5166 cluster1-thermal { 5167 polling-delay-passive = <250>; 5168 5169 thermal-sensors = <&tsens0 6>; 5170 5171 trips { 5172 cluster1_alert0: trip-point0 { 5173 temperature = <90000>; 5174 hysteresis = <2000>; 5175 type = "hot"; 5176 }; 5177 cluster1_crit: cluster1-crit { 5178 temperature = <110000>; 5179 hysteresis = <2000>; 5180 type = "critical"; 5181 }; 5182 }; 5183 }; 5184 5185 gpu-top-thermal { 5186 polling-delay-passive = <250>; 5187 5188 thermal-sensors = <&tsens0 15>; 5189 5190 cooling-maps { 5191 map0 { 5192 trip = <&gpu_top_alert0>; 5193 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5194 }; 5195 }; 5196 5197 trips { 5198 gpu_top_alert0: trip-point0 { 5199 temperature = <85000>; 5200 hysteresis = <1000>; 5201 type = "passive"; 5202 }; 5203 5204 trip-point1 { 5205 temperature = <90000>; 5206 hysteresis = <1000>; 5207 type = "hot"; 5208 }; 5209 5210 trip-point2 { 5211 temperature = <110000>; 5212 hysteresis = <1000>; 5213 type = "critical"; 5214 }; 5215 }; 5216 }; 5217 5218 aoss1-thermal { 5219 polling-delay-passive = <250>; 5220 5221 thermal-sensors = <&tsens1 0>; 5222 5223 trips { 5224 aoss1_alert0: trip-point0 { 5225 temperature = <90000>; 5226 hysteresis = <2000>; 5227 type = "hot"; 5228 }; 5229 }; 5230 }; 5231 5232 wlan-thermal { 5233 polling-delay-passive = <250>; 5234 5235 thermal-sensors = <&tsens1 1>; 5236 5237 trips { 5238 wlan_alert0: trip-point0 { 5239 temperature = <90000>; 5240 hysteresis = <2000>; 5241 type = "hot"; 5242 }; 5243 }; 5244 }; 5245 5246 video-thermal { 5247 polling-delay-passive = <250>; 5248 5249 thermal-sensors = <&tsens1 2>; 5250 5251 trips { 5252 video_alert0: trip-point0 { 5253 temperature = <90000>; 5254 hysteresis = <2000>; 5255 type = "hot"; 5256 }; 5257 }; 5258 }; 5259 5260 mem-thermal { 5261 polling-delay-passive = <250>; 5262 5263 thermal-sensors = <&tsens1 3>; 5264 5265 trips { 5266 mem_alert0: trip-point0 { 5267 temperature = <90000>; 5268 hysteresis = <2000>; 5269 type = "hot"; 5270 }; 5271 }; 5272 }; 5273 5274 q6-hvx-thermal { 5275 polling-delay-passive = <250>; 5276 5277 thermal-sensors = <&tsens1 4>; 5278 5279 trips { 5280 q6_hvx_alert0: trip-point0 { 5281 temperature = <90000>; 5282 hysteresis = <2000>; 5283 type = "hot"; 5284 }; 5285 }; 5286 }; 5287 5288 camera-thermal { 5289 polling-delay-passive = <250>; 5290 5291 thermal-sensors = <&tsens1 5>; 5292 5293 trips { 5294 camera_alert0: trip-point0 { 5295 temperature = <90000>; 5296 hysteresis = <2000>; 5297 type = "hot"; 5298 }; 5299 }; 5300 }; 5301 5302 compute-thermal { 5303 polling-delay-passive = <250>; 5304 5305 thermal-sensors = <&tsens1 6>; 5306 5307 trips { 5308 compute_alert0: trip-point0 { 5309 temperature = <90000>; 5310 hysteresis = <2000>; 5311 type = "hot"; 5312 }; 5313 }; 5314 }; 5315 5316 modem-thermal { 5317 polling-delay-passive = <250>; 5318 5319 thermal-sensors = <&tsens1 7>; 5320 5321 trips { 5322 modem_alert0: trip-point0 { 5323 temperature = <90000>; 5324 hysteresis = <2000>; 5325 type = "hot"; 5326 }; 5327 }; 5328 }; 5329 5330 npu-thermal { 5331 polling-delay-passive = <250>; 5332 5333 thermal-sensors = <&tsens1 8>; 5334 5335 trips { 5336 npu_alert0: trip-point0 { 5337 temperature = <90000>; 5338 hysteresis = <2000>; 5339 type = "hot"; 5340 }; 5341 }; 5342 }; 5343 5344 modem-vec-thermal { 5345 polling-delay-passive = <250>; 5346 5347 thermal-sensors = <&tsens1 9>; 5348 5349 trips { 5350 modem_vec_alert0: trip-point0 { 5351 temperature = <90000>; 5352 hysteresis = <2000>; 5353 type = "hot"; 5354 }; 5355 }; 5356 }; 5357 5358 modem-scl-thermal { 5359 polling-delay-passive = <250>; 5360 5361 thermal-sensors = <&tsens1 10>; 5362 5363 trips { 5364 modem_scl_alert0: trip-point0 { 5365 temperature = <90000>; 5366 hysteresis = <2000>; 5367 type = "hot"; 5368 }; 5369 }; 5370 }; 5371 5372 gpu-bottom-thermal { 5373 polling-delay-passive = <250>; 5374 5375 thermal-sensors = <&tsens1 11>; 5376 5377 cooling-maps { 5378 map0 { 5379 trip = <&gpu_bottom_alert0>; 5380 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5381 }; 5382 }; 5383 5384 trips { 5385 gpu_bottom_alert0: trip-point0 { 5386 temperature = <85000>; 5387 hysteresis = <1000>; 5388 type = "passive"; 5389 }; 5390 5391 trip-point1 { 5392 temperature = <90000>; 5393 hysteresis = <1000>; 5394 type = "hot"; 5395 }; 5396 5397 trip-point2 { 5398 temperature = <110000>; 5399 hysteresis = <1000>; 5400 type = "critical"; 5401 }; 5402 }; 5403 }; 5404 }; 5405}; 5406