1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2019, Linaro Limited 5 */ 6 7#include <dt-bindings/dma/qcom-gpi.h> 8#include <dt-bindings/firmware/qcom,scm.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/phy/phy-qcom-qmp.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/soc/qcom,rpmh-rsc.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,dispcc-sm8150.h> 15#include <dt-bindings/clock/qcom,gcc-sm8150.h> 16#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sm8150.h> 19#include <dt-bindings/thermal/thermal.h> 20 21/ { 22 interrupt-parent = <&intc>; 23 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 chosen { }; 28 29 clocks { 30 xo_board: xo-board { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <38400000>; 34 clock-output-names = "xo_board"; 35 }; 36 37 sleep_clk: sleep-clk { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <32764>; 41 clock-output-names = "sleep_clk"; 42 }; 43 }; 44 45 cpus { 46 #address-cells = <2>; 47 #size-cells = <0>; 48 49 CPU0: cpu@0 { 50 device_type = "cpu"; 51 compatible = "qcom,kryo485"; 52 reg = <0x0 0x0>; 53 clocks = <&cpufreq_hw 0>; 54 enable-method = "psci"; 55 capacity-dmips-mhz = <488>; 56 dynamic-power-coefficient = <232>; 57 next-level-cache = <&L2_0>; 58 qcom,freq-domain = <&cpufreq_hw 0>; 59 operating-points-v2 = <&cpu0_opp_table>; 60 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 61 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 62 power-domains = <&CPU_PD0>; 63 power-domain-names = "psci"; 64 #cooling-cells = <2>; 65 L2_0: l2-cache { 66 compatible = "cache"; 67 cache-level = <2>; 68 cache-unified; 69 next-level-cache = <&L3_0>; 70 L3_0: l3-cache { 71 compatible = "cache"; 72 cache-level = <3>; 73 cache-unified; 74 }; 75 }; 76 }; 77 78 CPU1: cpu@100 { 79 device_type = "cpu"; 80 compatible = "qcom,kryo485"; 81 reg = <0x0 0x100>; 82 clocks = <&cpufreq_hw 0>; 83 enable-method = "psci"; 84 capacity-dmips-mhz = <488>; 85 dynamic-power-coefficient = <232>; 86 next-level-cache = <&L2_100>; 87 qcom,freq-domain = <&cpufreq_hw 0>; 88 operating-points-v2 = <&cpu0_opp_table>; 89 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 90 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 91 power-domains = <&CPU_PD1>; 92 power-domain-names = "psci"; 93 #cooling-cells = <2>; 94 L2_100: l2-cache { 95 compatible = "cache"; 96 cache-level = <2>; 97 cache-unified; 98 next-level-cache = <&L3_0>; 99 }; 100 }; 101 102 CPU2: cpu@200 { 103 device_type = "cpu"; 104 compatible = "qcom,kryo485"; 105 reg = <0x0 0x200>; 106 clocks = <&cpufreq_hw 0>; 107 enable-method = "psci"; 108 capacity-dmips-mhz = <488>; 109 dynamic-power-coefficient = <232>; 110 next-level-cache = <&L2_200>; 111 qcom,freq-domain = <&cpufreq_hw 0>; 112 operating-points-v2 = <&cpu0_opp_table>; 113 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 114 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 115 power-domains = <&CPU_PD2>; 116 power-domain-names = "psci"; 117 #cooling-cells = <2>; 118 L2_200: l2-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 cache-unified; 122 next-level-cache = <&L3_0>; 123 }; 124 }; 125 126 CPU3: cpu@300 { 127 device_type = "cpu"; 128 compatible = "qcom,kryo485"; 129 reg = <0x0 0x300>; 130 clocks = <&cpufreq_hw 0>; 131 enable-method = "psci"; 132 capacity-dmips-mhz = <488>; 133 dynamic-power-coefficient = <232>; 134 next-level-cache = <&L2_300>; 135 qcom,freq-domain = <&cpufreq_hw 0>; 136 operating-points-v2 = <&cpu0_opp_table>; 137 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 138 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 139 power-domains = <&CPU_PD3>; 140 power-domain-names = "psci"; 141 #cooling-cells = <2>; 142 L2_300: l2-cache { 143 compatible = "cache"; 144 cache-level = <2>; 145 cache-unified; 146 next-level-cache = <&L3_0>; 147 }; 148 }; 149 150 CPU4: cpu@400 { 151 device_type = "cpu"; 152 compatible = "qcom,kryo485"; 153 reg = <0x0 0x400>; 154 clocks = <&cpufreq_hw 1>; 155 enable-method = "psci"; 156 capacity-dmips-mhz = <1024>; 157 dynamic-power-coefficient = <369>; 158 next-level-cache = <&L2_400>; 159 qcom,freq-domain = <&cpufreq_hw 1>; 160 operating-points-v2 = <&cpu4_opp_table>; 161 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 162 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 163 power-domains = <&CPU_PD4>; 164 power-domain-names = "psci"; 165 #cooling-cells = <2>; 166 L2_400: l2-cache { 167 compatible = "cache"; 168 cache-level = <2>; 169 cache-unified; 170 next-level-cache = <&L3_0>; 171 }; 172 }; 173 174 CPU5: cpu@500 { 175 device_type = "cpu"; 176 compatible = "qcom,kryo485"; 177 reg = <0x0 0x500>; 178 clocks = <&cpufreq_hw 1>; 179 enable-method = "psci"; 180 capacity-dmips-mhz = <1024>; 181 dynamic-power-coefficient = <369>; 182 next-level-cache = <&L2_500>; 183 qcom,freq-domain = <&cpufreq_hw 1>; 184 operating-points-v2 = <&cpu4_opp_table>; 185 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 186 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 187 power-domains = <&CPU_PD5>; 188 power-domain-names = "psci"; 189 #cooling-cells = <2>; 190 L2_500: l2-cache { 191 compatible = "cache"; 192 cache-level = <2>; 193 cache-unified; 194 next-level-cache = <&L3_0>; 195 }; 196 }; 197 198 CPU6: cpu@600 { 199 device_type = "cpu"; 200 compatible = "qcom,kryo485"; 201 reg = <0x0 0x600>; 202 clocks = <&cpufreq_hw 1>; 203 enable-method = "psci"; 204 capacity-dmips-mhz = <1024>; 205 dynamic-power-coefficient = <369>; 206 next-level-cache = <&L2_600>; 207 qcom,freq-domain = <&cpufreq_hw 1>; 208 operating-points-v2 = <&cpu4_opp_table>; 209 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 210 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 211 power-domains = <&CPU_PD6>; 212 power-domain-names = "psci"; 213 #cooling-cells = <2>; 214 L2_600: l2-cache { 215 compatible = "cache"; 216 cache-level = <2>; 217 cache-unified; 218 next-level-cache = <&L3_0>; 219 }; 220 }; 221 222 CPU7: cpu@700 { 223 device_type = "cpu"; 224 compatible = "qcom,kryo485"; 225 reg = <0x0 0x700>; 226 clocks = <&cpufreq_hw 2>; 227 enable-method = "psci"; 228 capacity-dmips-mhz = <1024>; 229 dynamic-power-coefficient = <421>; 230 next-level-cache = <&L2_700>; 231 qcom,freq-domain = <&cpufreq_hw 2>; 232 operating-points-v2 = <&cpu7_opp_table>; 233 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 234 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 235 power-domains = <&CPU_PD7>; 236 power-domain-names = "psci"; 237 #cooling-cells = <2>; 238 L2_700: l2-cache { 239 compatible = "cache"; 240 cache-level = <2>; 241 cache-unified; 242 next-level-cache = <&L3_0>; 243 }; 244 }; 245 246 cpu-map { 247 cluster0 { 248 core0 { 249 cpu = <&CPU0>; 250 }; 251 252 core1 { 253 cpu = <&CPU1>; 254 }; 255 256 core2 { 257 cpu = <&CPU2>; 258 }; 259 260 core3 { 261 cpu = <&CPU3>; 262 }; 263 264 core4 { 265 cpu = <&CPU4>; 266 }; 267 268 core5 { 269 cpu = <&CPU5>; 270 }; 271 272 core6 { 273 cpu = <&CPU6>; 274 }; 275 276 core7 { 277 cpu = <&CPU7>; 278 }; 279 }; 280 }; 281 282 idle-states { 283 entry-method = "psci"; 284 285 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 286 compatible = "arm,idle-state"; 287 idle-state-name = "little-rail-power-collapse"; 288 arm,psci-suspend-param = <0x40000004>; 289 entry-latency-us = <355>; 290 exit-latency-us = <909>; 291 min-residency-us = <3934>; 292 local-timer-stop; 293 }; 294 295 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 296 compatible = "arm,idle-state"; 297 idle-state-name = "big-rail-power-collapse"; 298 arm,psci-suspend-param = <0x40000004>; 299 entry-latency-us = <241>; 300 exit-latency-us = <1461>; 301 min-residency-us = <4488>; 302 local-timer-stop; 303 }; 304 }; 305 306 domain-idle-states { 307 CLUSTER_SLEEP_0: cluster-sleep-0 { 308 compatible = "domain-idle-state"; 309 arm,psci-suspend-param = <0x4100c244>; 310 entry-latency-us = <3263>; 311 exit-latency-us = <6562>; 312 min-residency-us = <9987>; 313 }; 314 }; 315 }; 316 317 cpu0_opp_table: opp-table-cpu0 { 318 compatible = "operating-points-v2"; 319 opp-shared; 320 321 cpu0_opp1: opp-300000000 { 322 opp-hz = /bits/ 64 <300000000>; 323 opp-peak-kBps = <800000 9600000>; 324 }; 325 326 cpu0_opp2: opp-403200000 { 327 opp-hz = /bits/ 64 <403200000>; 328 opp-peak-kBps = <800000 9600000>; 329 }; 330 331 cpu0_opp3: opp-499200000 { 332 opp-hz = /bits/ 64 <499200000>; 333 opp-peak-kBps = <800000 12902400>; 334 }; 335 336 cpu0_opp4: opp-576000000 { 337 opp-hz = /bits/ 64 <576000000>; 338 opp-peak-kBps = <800000 12902400>; 339 }; 340 341 cpu0_opp5: opp-672000000 { 342 opp-hz = /bits/ 64 <672000000>; 343 opp-peak-kBps = <800000 15974400>; 344 }; 345 346 cpu0_opp6: opp-768000000 { 347 opp-hz = /bits/ 64 <768000000>; 348 opp-peak-kBps = <1804000 19660800>; 349 }; 350 351 cpu0_opp7: opp-844800000 { 352 opp-hz = /bits/ 64 <844800000>; 353 opp-peak-kBps = <1804000 19660800>; 354 }; 355 356 cpu0_opp8: opp-940800000 { 357 opp-hz = /bits/ 64 <940800000>; 358 opp-peak-kBps = <1804000 22732800>; 359 }; 360 361 cpu0_opp9: opp-1036800000 { 362 opp-hz = /bits/ 64 <1036800000>; 363 opp-peak-kBps = <1804000 22732800>; 364 }; 365 366 cpu0_opp10: opp-1113600000 { 367 opp-hz = /bits/ 64 <1113600000>; 368 opp-peak-kBps = <2188000 25804800>; 369 }; 370 371 cpu0_opp11: opp-1209600000 { 372 opp-hz = /bits/ 64 <1209600000>; 373 opp-peak-kBps = <2188000 31948800>; 374 }; 375 376 cpu0_opp12: opp-1305600000 { 377 opp-hz = /bits/ 64 <1305600000>; 378 opp-peak-kBps = <3072000 31948800>; 379 }; 380 381 cpu0_opp13: opp-1382400000 { 382 opp-hz = /bits/ 64 <1382400000>; 383 opp-peak-kBps = <3072000 31948800>; 384 }; 385 386 cpu0_opp14: opp-1478400000 { 387 opp-hz = /bits/ 64 <1478400000>; 388 opp-peak-kBps = <3072000 31948800>; 389 }; 390 391 cpu0_opp15: opp-1555200000 { 392 opp-hz = /bits/ 64 <1555200000>; 393 opp-peak-kBps = <3072000 40550400>; 394 }; 395 396 cpu0_opp16: opp-1632000000 { 397 opp-hz = /bits/ 64 <1632000000>; 398 opp-peak-kBps = <3072000 40550400>; 399 }; 400 401 cpu0_opp17: opp-1708800000 { 402 opp-hz = /bits/ 64 <1708800000>; 403 opp-peak-kBps = <3072000 43008000>; 404 }; 405 406 cpu0_opp18: opp-1785600000 { 407 opp-hz = /bits/ 64 <1785600000>; 408 opp-peak-kBps = <3072000 43008000>; 409 }; 410 }; 411 412 cpu4_opp_table: opp-table-cpu4 { 413 compatible = "operating-points-v2"; 414 opp-shared; 415 416 cpu4_opp1: opp-710400000 { 417 opp-hz = /bits/ 64 <710400000>; 418 opp-peak-kBps = <1804000 15974400>; 419 }; 420 421 cpu4_opp2: opp-825600000 { 422 opp-hz = /bits/ 64 <825600000>; 423 opp-peak-kBps = <2188000 19660800>; 424 }; 425 426 cpu4_opp3: opp-940800000 { 427 opp-hz = /bits/ 64 <940800000>; 428 opp-peak-kBps = <2188000 22732800>; 429 }; 430 431 cpu4_opp4: opp-1056000000 { 432 opp-hz = /bits/ 64 <1056000000>; 433 opp-peak-kBps = <3072000 25804800>; 434 }; 435 436 cpu4_opp5: opp-1171200000 { 437 opp-hz = /bits/ 64 <1171200000>; 438 opp-peak-kBps = <3072000 31948800>; 439 }; 440 441 cpu4_opp6: opp-1286400000 { 442 opp-hz = /bits/ 64 <1286400000>; 443 opp-peak-kBps = <4068000 31948800>; 444 }; 445 446 cpu4_opp7: opp-1401600000 { 447 opp-hz = /bits/ 64 <1401600000>; 448 opp-peak-kBps = <4068000 31948800>; 449 }; 450 451 cpu4_opp8: opp-1497600000 { 452 opp-hz = /bits/ 64 <1497600000>; 453 opp-peak-kBps = <4068000 40550400>; 454 }; 455 456 cpu4_opp9: opp-1612800000 { 457 opp-hz = /bits/ 64 <1612800000>; 458 opp-peak-kBps = <4068000 40550400>; 459 }; 460 461 cpu4_opp10: opp-1708800000 { 462 opp-hz = /bits/ 64 <1708800000>; 463 opp-peak-kBps = <4068000 43008000>; 464 }; 465 466 cpu4_opp11: opp-1804800000 { 467 opp-hz = /bits/ 64 <1804800000>; 468 opp-peak-kBps = <6220000 43008000>; 469 }; 470 471 cpu4_opp12: opp-1920000000 { 472 opp-hz = /bits/ 64 <1920000000>; 473 opp-peak-kBps = <6220000 49152000>; 474 }; 475 476 cpu4_opp13: opp-2016000000 { 477 opp-hz = /bits/ 64 <2016000000>; 478 opp-peak-kBps = <7216000 49152000>; 479 }; 480 481 cpu4_opp14: opp-2131200000 { 482 opp-hz = /bits/ 64 <2131200000>; 483 opp-peak-kBps = <8368000 49152000>; 484 }; 485 486 cpu4_opp15: opp-2227200000 { 487 opp-hz = /bits/ 64 <2227200000>; 488 opp-peak-kBps = <8368000 51609600>; 489 }; 490 491 cpu4_opp16: opp-2323200000 { 492 opp-hz = /bits/ 64 <2323200000>; 493 opp-peak-kBps = <8368000 51609600>; 494 }; 495 496 cpu4_opp17: opp-2419200000 { 497 opp-hz = /bits/ 64 <2419200000>; 498 opp-peak-kBps = <8368000 51609600>; 499 }; 500 }; 501 502 cpu7_opp_table: opp-table-cpu7 { 503 compatible = "operating-points-v2"; 504 opp-shared; 505 506 cpu7_opp1: opp-825600000 { 507 opp-hz = /bits/ 64 <825600000>; 508 opp-peak-kBps = <2188000 19660800>; 509 }; 510 511 cpu7_opp2: opp-940800000 { 512 opp-hz = /bits/ 64 <940800000>; 513 opp-peak-kBps = <2188000 22732800>; 514 }; 515 516 cpu7_opp3: opp-1056000000 { 517 opp-hz = /bits/ 64 <1056000000>; 518 opp-peak-kBps = <3072000 25804800>; 519 }; 520 521 cpu7_opp4: opp-1171200000 { 522 opp-hz = /bits/ 64 <1171200000>; 523 opp-peak-kBps = <3072000 31948800>; 524 }; 525 526 cpu7_opp5: opp-1286400000 { 527 opp-hz = /bits/ 64 <1286400000>; 528 opp-peak-kBps = <4068000 31948800>; 529 }; 530 531 cpu7_opp6: opp-1401600000 { 532 opp-hz = /bits/ 64 <1401600000>; 533 opp-peak-kBps = <4068000 31948800>; 534 }; 535 536 cpu7_opp7: opp-1497600000 { 537 opp-hz = /bits/ 64 <1497600000>; 538 opp-peak-kBps = <4068000 40550400>; 539 }; 540 541 cpu7_opp8: opp-1612800000 { 542 opp-hz = /bits/ 64 <1612800000>; 543 opp-peak-kBps = <4068000 40550400>; 544 }; 545 546 cpu7_opp9: opp-1708800000 { 547 opp-hz = /bits/ 64 <1708800000>; 548 opp-peak-kBps = <4068000 43008000>; 549 }; 550 551 cpu7_opp10: opp-1804800000 { 552 opp-hz = /bits/ 64 <1804800000>; 553 opp-peak-kBps = <6220000 43008000>; 554 }; 555 556 cpu7_opp11: opp-1920000000 { 557 opp-hz = /bits/ 64 <1920000000>; 558 opp-peak-kBps = <6220000 49152000>; 559 }; 560 561 cpu7_opp12: opp-2016000000 { 562 opp-hz = /bits/ 64 <2016000000>; 563 opp-peak-kBps = <7216000 49152000>; 564 }; 565 566 cpu7_opp13: opp-2131200000 { 567 opp-hz = /bits/ 64 <2131200000>; 568 opp-peak-kBps = <8368000 49152000>; 569 }; 570 571 cpu7_opp14: opp-2227200000 { 572 opp-hz = /bits/ 64 <2227200000>; 573 opp-peak-kBps = <8368000 51609600>; 574 }; 575 576 cpu7_opp15: opp-2323200000 { 577 opp-hz = /bits/ 64 <2323200000>; 578 opp-peak-kBps = <8368000 51609600>; 579 }; 580 581 cpu7_opp16: opp-2419200000 { 582 opp-hz = /bits/ 64 <2419200000>; 583 opp-peak-kBps = <8368000 51609600>; 584 }; 585 586 cpu7_opp17: opp-2534400000 { 587 opp-hz = /bits/ 64 <2534400000>; 588 opp-peak-kBps = <8368000 51609600>; 589 }; 590 591 cpu7_opp18: opp-2649600000 { 592 opp-hz = /bits/ 64 <2649600000>; 593 opp-peak-kBps = <8368000 51609600>; 594 }; 595 596 cpu7_opp19: opp-2745600000 { 597 opp-hz = /bits/ 64 <2745600000>; 598 opp-peak-kBps = <8368000 51609600>; 599 }; 600 601 cpu7_opp20: opp-2841600000 { 602 opp-hz = /bits/ 64 <2841600000>; 603 opp-peak-kBps = <8368000 51609600>; 604 }; 605 }; 606 607 firmware { 608 scm: scm { 609 compatible = "qcom,scm-sm8150", "qcom,scm"; 610 #reset-cells = <1>; 611 }; 612 }; 613 614 memory@80000000 { 615 device_type = "memory"; 616 /* We expect the bootloader to fill in the size */ 617 reg = <0x0 0x80000000 0x0 0x0>; 618 }; 619 620 pmu { 621 compatible = "arm,armv8-pmuv3"; 622 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 623 }; 624 625 psci { 626 compatible = "arm,psci-1.0"; 627 method = "smc"; 628 629 CPU_PD0: power-domain-cpu0 { 630 #power-domain-cells = <0>; 631 power-domains = <&CLUSTER_PD>; 632 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 633 }; 634 635 CPU_PD1: power-domain-cpu1 { 636 #power-domain-cells = <0>; 637 power-domains = <&CLUSTER_PD>; 638 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 639 }; 640 641 CPU_PD2: power-domain-cpu2 { 642 #power-domain-cells = <0>; 643 power-domains = <&CLUSTER_PD>; 644 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 645 }; 646 647 CPU_PD3: power-domain-cpu3 { 648 #power-domain-cells = <0>; 649 power-domains = <&CLUSTER_PD>; 650 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 651 }; 652 653 CPU_PD4: power-domain-cpu4 { 654 #power-domain-cells = <0>; 655 power-domains = <&CLUSTER_PD>; 656 domain-idle-states = <&BIG_CPU_SLEEP_0>; 657 }; 658 659 CPU_PD5: power-domain-cpu5 { 660 #power-domain-cells = <0>; 661 power-domains = <&CLUSTER_PD>; 662 domain-idle-states = <&BIG_CPU_SLEEP_0>; 663 }; 664 665 CPU_PD6: power-domain-cpu6 { 666 #power-domain-cells = <0>; 667 power-domains = <&CLUSTER_PD>; 668 domain-idle-states = <&BIG_CPU_SLEEP_0>; 669 }; 670 671 CPU_PD7: power-domain-cpu7 { 672 #power-domain-cells = <0>; 673 power-domains = <&CLUSTER_PD>; 674 domain-idle-states = <&BIG_CPU_SLEEP_0>; 675 }; 676 677 CLUSTER_PD: power-domain-cpu-cluster0 { 678 #power-domain-cells = <0>; 679 domain-idle-states = <&CLUSTER_SLEEP_0>; 680 }; 681 }; 682 683 reserved-memory { 684 #address-cells = <2>; 685 #size-cells = <2>; 686 ranges; 687 688 hyp_mem: memory@85700000 { 689 reg = <0x0 0x85700000 0x0 0x600000>; 690 no-map; 691 }; 692 693 xbl_mem: memory@85d00000 { 694 reg = <0x0 0x85d00000 0x0 0x140000>; 695 no-map; 696 }; 697 698 aop_mem: memory@85f00000 { 699 reg = <0x0 0x85f00000 0x0 0x20000>; 700 no-map; 701 }; 702 703 aop_cmd_db: memory@85f20000 { 704 compatible = "qcom,cmd-db"; 705 reg = <0x0 0x85f20000 0x0 0x20000>; 706 no-map; 707 }; 708 709 smem_mem: memory@86000000 { 710 reg = <0x0 0x86000000 0x0 0x200000>; 711 no-map; 712 }; 713 714 tz_mem: memory@86200000 { 715 reg = <0x0 0x86200000 0x0 0x3900000>; 716 no-map; 717 }; 718 719 rmtfs_mem: memory@89b00000 { 720 compatible = "qcom,rmtfs-mem"; 721 reg = <0x0 0x89b00000 0x0 0x200000>; 722 no-map; 723 724 qcom,client-id = <1>; 725 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 726 }; 727 728 camera_mem: memory@8b700000 { 729 reg = <0x0 0x8b700000 0x0 0x500000>; 730 no-map; 731 }; 732 733 wlan_mem: memory@8bc00000 { 734 reg = <0x0 0x8bc00000 0x0 0x180000>; 735 no-map; 736 }; 737 738 npu_mem: memory@8bd80000 { 739 reg = <0x0 0x8bd80000 0x0 0x80000>; 740 no-map; 741 }; 742 743 adsp_mem: memory@8be00000 { 744 reg = <0x0 0x8be00000 0x0 0x1a00000>; 745 no-map; 746 }; 747 748 mpss_mem: memory@8d800000 { 749 reg = <0x0 0x8d800000 0x0 0x9600000>; 750 no-map; 751 }; 752 753 venus_mem: memory@96e00000 { 754 reg = <0x0 0x96e00000 0x0 0x500000>; 755 no-map; 756 }; 757 758 slpi_mem: memory@97300000 { 759 reg = <0x0 0x97300000 0x0 0x1400000>; 760 no-map; 761 }; 762 763 ipa_fw_mem: memory@98700000 { 764 reg = <0x0 0x98700000 0x0 0x10000>; 765 no-map; 766 }; 767 768 ipa_gsi_mem: memory@98710000 { 769 reg = <0x0 0x98710000 0x0 0x5000>; 770 no-map; 771 }; 772 773 gpu_mem: memory@98715000 { 774 reg = <0x0 0x98715000 0x0 0x2000>; 775 no-map; 776 }; 777 778 spss_mem: memory@98800000 { 779 reg = <0x0 0x98800000 0x0 0x100000>; 780 no-map; 781 }; 782 783 cdsp_mem: memory@98900000 { 784 reg = <0x0 0x98900000 0x0 0x1400000>; 785 no-map; 786 }; 787 788 qseecom_mem: memory@9e400000 { 789 reg = <0x0 0x9e400000 0x0 0x1400000>; 790 no-map; 791 }; 792 }; 793 794 smem { 795 compatible = "qcom,smem"; 796 memory-region = <&smem_mem>; 797 hwlocks = <&tcsr_mutex 3>; 798 }; 799 800 smp2p-cdsp { 801 compatible = "qcom,smp2p"; 802 qcom,smem = <94>, <432>; 803 804 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 805 806 mboxes = <&apss_shared 6>; 807 808 qcom,local-pid = <0>; 809 qcom,remote-pid = <5>; 810 811 cdsp_smp2p_out: master-kernel { 812 qcom,entry-name = "master-kernel"; 813 #qcom,smem-state-cells = <1>; 814 }; 815 816 cdsp_smp2p_in: slave-kernel { 817 qcom,entry-name = "slave-kernel"; 818 819 interrupt-controller; 820 #interrupt-cells = <2>; 821 }; 822 }; 823 824 smp2p-lpass { 825 compatible = "qcom,smp2p"; 826 qcom,smem = <443>, <429>; 827 828 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 829 830 mboxes = <&apss_shared 10>; 831 832 qcom,local-pid = <0>; 833 qcom,remote-pid = <2>; 834 835 adsp_smp2p_out: master-kernel { 836 qcom,entry-name = "master-kernel"; 837 #qcom,smem-state-cells = <1>; 838 }; 839 840 adsp_smp2p_in: slave-kernel { 841 qcom,entry-name = "slave-kernel"; 842 843 interrupt-controller; 844 #interrupt-cells = <2>; 845 }; 846 }; 847 848 smp2p-mpss { 849 compatible = "qcom,smp2p"; 850 qcom,smem = <435>, <428>; 851 852 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 853 854 mboxes = <&apss_shared 14>; 855 856 qcom,local-pid = <0>; 857 qcom,remote-pid = <1>; 858 859 modem_smp2p_out: master-kernel { 860 qcom,entry-name = "master-kernel"; 861 #qcom,smem-state-cells = <1>; 862 }; 863 864 modem_smp2p_in: slave-kernel { 865 qcom,entry-name = "slave-kernel"; 866 867 interrupt-controller; 868 #interrupt-cells = <2>; 869 }; 870 }; 871 872 smp2p-slpi { 873 compatible = "qcom,smp2p"; 874 qcom,smem = <481>, <430>; 875 876 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 877 878 mboxes = <&apss_shared 26>; 879 880 qcom,local-pid = <0>; 881 qcom,remote-pid = <3>; 882 883 slpi_smp2p_out: master-kernel { 884 qcom,entry-name = "master-kernel"; 885 #qcom,smem-state-cells = <1>; 886 }; 887 888 slpi_smp2p_in: slave-kernel { 889 qcom,entry-name = "slave-kernel"; 890 891 interrupt-controller; 892 #interrupt-cells = <2>; 893 }; 894 }; 895 896 soc: soc@0 { 897 #address-cells = <2>; 898 #size-cells = <2>; 899 ranges = <0 0 0 0 0x10 0>; 900 dma-ranges = <0 0 0 0 0x10 0>; 901 compatible = "simple-bus"; 902 903 gcc: clock-controller@100000 { 904 compatible = "qcom,gcc-sm8150"; 905 reg = <0x0 0x00100000 0x0 0x1f0000>; 906 #clock-cells = <1>; 907 #reset-cells = <1>; 908 #power-domain-cells = <1>; 909 clock-names = "bi_tcxo", 910 "sleep_clk"; 911 clocks = <&rpmhcc RPMH_CXO_CLK>, 912 <&sleep_clk>; 913 }; 914 915 gpi_dma0: dma-controller@800000 { 916 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 917 reg = <0 0x00800000 0 0x60000>; 918 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 919 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 920 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 921 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 922 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 923 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 931 dma-channels = <13>; 932 dma-channel-mask = <0xfa>; 933 iommus = <&apps_smmu 0x00d6 0x0>; 934 #dma-cells = <3>; 935 status = "disabled"; 936 }; 937 938 ethernet: ethernet@20000 { 939 compatible = "qcom,sm8150-ethqos"; 940 reg = <0x0 0x00020000 0x0 0x10000>, 941 <0x0 0x00036000 0x0 0x100>; 942 reg-names = "stmmaceth", "rgmii"; 943 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; 944 clocks = <&gcc GCC_EMAC_AXI_CLK>, 945 <&gcc GCC_EMAC_SLV_AHB_CLK>, 946 <&gcc GCC_EMAC_PTP_CLK>, 947 <&gcc GCC_EMAC_RGMII_CLK>; 948 interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; 950 interrupt-names = "macirq", "eth_lpi"; 951 952 power-domains = <&gcc EMAC_GDSC>; 953 resets = <&gcc GCC_EMAC_BCR>; 954 955 iommus = <&apps_smmu 0x3c0 0x0>; 956 957 snps,tso; 958 rx-fifo-depth = <4096>; 959 tx-fifo-depth = <4096>; 960 961 status = "disabled"; 962 }; 963 964 qfprom: efuse@784000 { 965 compatible = "qcom,sm8150-qfprom", "qcom,qfprom"; 966 reg = <0 0x00784000 0 0x8ff>; 967 #address-cells = <1>; 968 #size-cells = <1>; 969 970 gpu_speed_bin: gpu_speed_bin@133 { 971 reg = <0x133 0x1>; 972 bits = <5 3>; 973 }; 974 }; 975 976 qupv3_id_0: geniqup@8c0000 { 977 compatible = "qcom,geni-se-qup"; 978 reg = <0x0 0x008c0000 0x0 0x6000>; 979 clock-names = "m-ahb", "s-ahb"; 980 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 981 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 982 iommus = <&apps_smmu 0xc3 0x0>; 983 #address-cells = <2>; 984 #size-cells = <2>; 985 ranges; 986 status = "disabled"; 987 988 i2c0: i2c@880000 { 989 compatible = "qcom,geni-i2c"; 990 reg = <0 0x00880000 0 0x4000>; 991 clock-names = "se"; 992 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 993 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 994 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 995 dma-names = "tx", "rx"; 996 pinctrl-names = "default"; 997 pinctrl-0 = <&qup_i2c0_default>; 998 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 999 #address-cells = <1>; 1000 #size-cells = <0>; 1001 status = "disabled"; 1002 }; 1003 1004 spi0: spi@880000 { 1005 compatible = "qcom,geni-spi"; 1006 reg = <0 0x00880000 0 0x4000>; 1007 reg-names = "se"; 1008 clock-names = "se"; 1009 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1010 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1011 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1012 dma-names = "tx", "rx"; 1013 pinctrl-names = "default"; 1014 pinctrl-0 = <&qup_spi0_default>; 1015 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1016 spi-max-frequency = <50000000>; 1017 #address-cells = <1>; 1018 #size-cells = <0>; 1019 status = "disabled"; 1020 }; 1021 1022 i2c1: i2c@884000 { 1023 compatible = "qcom,geni-i2c"; 1024 reg = <0 0x00884000 0 0x4000>; 1025 clock-names = "se"; 1026 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1027 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1028 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1029 dma-names = "tx", "rx"; 1030 pinctrl-names = "default"; 1031 pinctrl-0 = <&qup_i2c1_default>; 1032 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1033 #address-cells = <1>; 1034 #size-cells = <0>; 1035 status = "disabled"; 1036 }; 1037 1038 spi1: spi@884000 { 1039 compatible = "qcom,geni-spi"; 1040 reg = <0 0x00884000 0 0x4000>; 1041 reg-names = "se"; 1042 clock-names = "se"; 1043 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1044 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1045 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1046 dma-names = "tx", "rx"; 1047 pinctrl-names = "default"; 1048 pinctrl-0 = <&qup_spi1_default>; 1049 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1050 spi-max-frequency = <50000000>; 1051 #address-cells = <1>; 1052 #size-cells = <0>; 1053 status = "disabled"; 1054 }; 1055 1056 i2c2: i2c@888000 { 1057 compatible = "qcom,geni-i2c"; 1058 reg = <0 0x00888000 0 0x4000>; 1059 clock-names = "se"; 1060 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1061 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1062 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1063 dma-names = "tx", "rx"; 1064 pinctrl-names = "default"; 1065 pinctrl-0 = <&qup_i2c2_default>; 1066 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1067 #address-cells = <1>; 1068 #size-cells = <0>; 1069 status = "disabled"; 1070 }; 1071 1072 spi2: spi@888000 { 1073 compatible = "qcom,geni-spi"; 1074 reg = <0 0x00888000 0 0x4000>; 1075 reg-names = "se"; 1076 clock-names = "se"; 1077 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1078 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1079 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1080 dma-names = "tx", "rx"; 1081 pinctrl-names = "default"; 1082 pinctrl-0 = <&qup_spi2_default>; 1083 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1084 spi-max-frequency = <50000000>; 1085 #address-cells = <1>; 1086 #size-cells = <0>; 1087 status = "disabled"; 1088 }; 1089 1090 i2c3: i2c@88c000 { 1091 compatible = "qcom,geni-i2c"; 1092 reg = <0 0x0088c000 0 0x4000>; 1093 clock-names = "se"; 1094 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1095 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1096 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1097 dma-names = "tx", "rx"; 1098 pinctrl-names = "default"; 1099 pinctrl-0 = <&qup_i2c3_default>; 1100 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1101 #address-cells = <1>; 1102 #size-cells = <0>; 1103 status = "disabled"; 1104 }; 1105 1106 spi3: spi@88c000 { 1107 compatible = "qcom,geni-spi"; 1108 reg = <0 0x0088c000 0 0x4000>; 1109 reg-names = "se"; 1110 clock-names = "se"; 1111 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1112 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1113 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1114 dma-names = "tx", "rx"; 1115 pinctrl-names = "default"; 1116 pinctrl-0 = <&qup_spi3_default>; 1117 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1118 spi-max-frequency = <50000000>; 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 status = "disabled"; 1122 }; 1123 1124 i2c4: i2c@890000 { 1125 compatible = "qcom,geni-i2c"; 1126 reg = <0 0x00890000 0 0x4000>; 1127 clock-names = "se"; 1128 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1129 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1130 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1131 dma-names = "tx", "rx"; 1132 pinctrl-names = "default"; 1133 pinctrl-0 = <&qup_i2c4_default>; 1134 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1135 #address-cells = <1>; 1136 #size-cells = <0>; 1137 status = "disabled"; 1138 }; 1139 1140 spi4: spi@890000 { 1141 compatible = "qcom,geni-spi"; 1142 reg = <0 0x00890000 0 0x4000>; 1143 reg-names = "se"; 1144 clock-names = "se"; 1145 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1146 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1147 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1148 dma-names = "tx", "rx"; 1149 pinctrl-names = "default"; 1150 pinctrl-0 = <&qup_spi4_default>; 1151 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1152 spi-max-frequency = <50000000>; 1153 #address-cells = <1>; 1154 #size-cells = <0>; 1155 status = "disabled"; 1156 }; 1157 1158 i2c5: i2c@894000 { 1159 compatible = "qcom,geni-i2c"; 1160 reg = <0 0x00894000 0 0x4000>; 1161 clock-names = "se"; 1162 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1163 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1164 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1165 dma-names = "tx", "rx"; 1166 pinctrl-names = "default"; 1167 pinctrl-0 = <&qup_i2c5_default>; 1168 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1169 #address-cells = <1>; 1170 #size-cells = <0>; 1171 status = "disabled"; 1172 }; 1173 1174 spi5: spi@894000 { 1175 compatible = "qcom,geni-spi"; 1176 reg = <0 0x00894000 0 0x4000>; 1177 reg-names = "se"; 1178 clock-names = "se"; 1179 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1180 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1181 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1182 dma-names = "tx", "rx"; 1183 pinctrl-names = "default"; 1184 pinctrl-0 = <&qup_spi5_default>; 1185 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1186 spi-max-frequency = <50000000>; 1187 #address-cells = <1>; 1188 #size-cells = <0>; 1189 status = "disabled"; 1190 }; 1191 1192 i2c6: i2c@898000 { 1193 compatible = "qcom,geni-i2c"; 1194 reg = <0 0x00898000 0 0x4000>; 1195 clock-names = "se"; 1196 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1197 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1198 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1199 dma-names = "tx", "rx"; 1200 pinctrl-names = "default"; 1201 pinctrl-0 = <&qup_i2c6_default>; 1202 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1203 #address-cells = <1>; 1204 #size-cells = <0>; 1205 status = "disabled"; 1206 }; 1207 1208 spi6: spi@898000 { 1209 compatible = "qcom,geni-spi"; 1210 reg = <0 0x00898000 0 0x4000>; 1211 reg-names = "se"; 1212 clock-names = "se"; 1213 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1214 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1215 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1216 dma-names = "tx", "rx"; 1217 pinctrl-names = "default"; 1218 pinctrl-0 = <&qup_spi6_default>; 1219 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1220 spi-max-frequency = <50000000>; 1221 #address-cells = <1>; 1222 #size-cells = <0>; 1223 status = "disabled"; 1224 }; 1225 1226 i2c7: i2c@89c000 { 1227 compatible = "qcom,geni-i2c"; 1228 reg = <0 0x0089c000 0 0x4000>; 1229 clock-names = "se"; 1230 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1231 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1232 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1233 dma-names = "tx", "rx"; 1234 pinctrl-names = "default"; 1235 pinctrl-0 = <&qup_i2c7_default>; 1236 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1237 #address-cells = <1>; 1238 #size-cells = <0>; 1239 status = "disabled"; 1240 }; 1241 1242 spi7: spi@89c000 { 1243 compatible = "qcom,geni-spi"; 1244 reg = <0 0x0089c000 0 0x4000>; 1245 reg-names = "se"; 1246 clock-names = "se"; 1247 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1248 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1249 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1250 dma-names = "tx", "rx"; 1251 pinctrl-names = "default"; 1252 pinctrl-0 = <&qup_spi7_default>; 1253 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1254 spi-max-frequency = <50000000>; 1255 #address-cells = <1>; 1256 #size-cells = <0>; 1257 status = "disabled"; 1258 }; 1259 }; 1260 1261 gpi_dma1: dma-controller@a00000 { 1262 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 1263 reg = <0 0x00a00000 0 0x60000>; 1264 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1265 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1266 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1267 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1275 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1276 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1277 dma-channels = <13>; 1278 dma-channel-mask = <0xfa>; 1279 iommus = <&apps_smmu 0x0616 0x0>; 1280 #dma-cells = <3>; 1281 status = "disabled"; 1282 }; 1283 1284 qupv3_id_1: geniqup@ac0000 { 1285 compatible = "qcom,geni-se-qup"; 1286 reg = <0x0 0x00ac0000 0x0 0x6000>; 1287 clock-names = "m-ahb", "s-ahb"; 1288 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1289 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1290 iommus = <&apps_smmu 0x603 0x0>; 1291 #address-cells = <2>; 1292 #size-cells = <2>; 1293 ranges; 1294 status = "disabled"; 1295 1296 i2c8: i2c@a80000 { 1297 compatible = "qcom,geni-i2c"; 1298 reg = <0 0x00a80000 0 0x4000>; 1299 clock-names = "se"; 1300 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1301 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1302 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1303 dma-names = "tx", "rx"; 1304 pinctrl-names = "default"; 1305 pinctrl-0 = <&qup_i2c8_default>; 1306 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1307 #address-cells = <1>; 1308 #size-cells = <0>; 1309 status = "disabled"; 1310 }; 1311 1312 spi8: spi@a80000 { 1313 compatible = "qcom,geni-spi"; 1314 reg = <0 0x00a80000 0 0x4000>; 1315 reg-names = "se"; 1316 clock-names = "se"; 1317 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1318 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1319 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1320 dma-names = "tx", "rx"; 1321 pinctrl-names = "default"; 1322 pinctrl-0 = <&qup_spi8_default>; 1323 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1324 spi-max-frequency = <50000000>; 1325 #address-cells = <1>; 1326 #size-cells = <0>; 1327 status = "disabled"; 1328 }; 1329 1330 i2c9: i2c@a84000 { 1331 compatible = "qcom,geni-i2c"; 1332 reg = <0 0x00a84000 0 0x4000>; 1333 clock-names = "se"; 1334 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1335 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1336 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1337 dma-names = "tx", "rx"; 1338 pinctrl-names = "default"; 1339 pinctrl-0 = <&qup_i2c9_default>; 1340 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1341 #address-cells = <1>; 1342 #size-cells = <0>; 1343 status = "disabled"; 1344 }; 1345 1346 spi9: spi@a84000 { 1347 compatible = "qcom,geni-spi"; 1348 reg = <0 0x00a84000 0 0x4000>; 1349 reg-names = "se"; 1350 clock-names = "se"; 1351 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1352 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1353 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1354 dma-names = "tx", "rx"; 1355 pinctrl-names = "default"; 1356 pinctrl-0 = <&qup_spi9_default>; 1357 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1358 spi-max-frequency = <50000000>; 1359 #address-cells = <1>; 1360 #size-cells = <0>; 1361 status = "disabled"; 1362 }; 1363 1364 uart9: serial@a84000 { 1365 compatible = "qcom,geni-uart"; 1366 reg = <0x0 0x00a84000 0x0 0x4000>; 1367 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1368 clock-names = "se"; 1369 pinctrl-0 = <&qup_uart9_default>; 1370 pinctrl-names = "default"; 1371 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1372 status = "disabled"; 1373 }; 1374 1375 i2c10: i2c@a88000 { 1376 compatible = "qcom,geni-i2c"; 1377 reg = <0 0x00a88000 0 0x4000>; 1378 clock-names = "se"; 1379 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1380 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1381 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1382 dma-names = "tx", "rx"; 1383 pinctrl-names = "default"; 1384 pinctrl-0 = <&qup_i2c10_default>; 1385 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1386 #address-cells = <1>; 1387 #size-cells = <0>; 1388 status = "disabled"; 1389 }; 1390 1391 spi10: spi@a88000 { 1392 compatible = "qcom,geni-spi"; 1393 reg = <0 0x00a88000 0 0x4000>; 1394 reg-names = "se"; 1395 clock-names = "se"; 1396 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1397 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1398 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1399 dma-names = "tx", "rx"; 1400 pinctrl-names = "default"; 1401 pinctrl-0 = <&qup_spi10_default>; 1402 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1403 spi-max-frequency = <50000000>; 1404 #address-cells = <1>; 1405 #size-cells = <0>; 1406 status = "disabled"; 1407 }; 1408 1409 i2c11: i2c@a8c000 { 1410 compatible = "qcom,geni-i2c"; 1411 reg = <0 0x00a8c000 0 0x4000>; 1412 clock-names = "se"; 1413 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1414 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1415 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1416 dma-names = "tx", "rx"; 1417 pinctrl-names = "default"; 1418 pinctrl-0 = <&qup_i2c11_default>; 1419 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1420 #address-cells = <1>; 1421 #size-cells = <0>; 1422 status = "disabled"; 1423 }; 1424 1425 spi11: spi@a8c000 { 1426 compatible = "qcom,geni-spi"; 1427 reg = <0 0x00a8c000 0 0x4000>; 1428 reg-names = "se"; 1429 clock-names = "se"; 1430 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1431 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1432 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1433 dma-names = "tx", "rx"; 1434 pinctrl-names = "default"; 1435 pinctrl-0 = <&qup_spi11_default>; 1436 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1437 spi-max-frequency = <50000000>; 1438 #address-cells = <1>; 1439 #size-cells = <0>; 1440 status = "disabled"; 1441 }; 1442 1443 uart2: serial@a90000 { 1444 compatible = "qcom,geni-debug-uart"; 1445 reg = <0x0 0x00a90000 0x0 0x4000>; 1446 clock-names = "se"; 1447 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1448 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1449 status = "disabled"; 1450 }; 1451 1452 i2c12: i2c@a90000 { 1453 compatible = "qcom,geni-i2c"; 1454 reg = <0 0x00a90000 0 0x4000>; 1455 clock-names = "se"; 1456 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1457 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1458 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1459 dma-names = "tx", "rx"; 1460 pinctrl-names = "default"; 1461 pinctrl-0 = <&qup_i2c12_default>; 1462 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1463 #address-cells = <1>; 1464 #size-cells = <0>; 1465 status = "disabled"; 1466 }; 1467 1468 spi12: spi@a90000 { 1469 compatible = "qcom,geni-spi"; 1470 reg = <0 0x00a90000 0 0x4000>; 1471 reg-names = "se"; 1472 clock-names = "se"; 1473 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1474 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1475 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1476 dma-names = "tx", "rx"; 1477 pinctrl-names = "default"; 1478 pinctrl-0 = <&qup_spi12_default>; 1479 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1480 spi-max-frequency = <50000000>; 1481 #address-cells = <1>; 1482 #size-cells = <0>; 1483 status = "disabled"; 1484 }; 1485 1486 i2c16: i2c@94000 { 1487 compatible = "qcom,geni-i2c"; 1488 reg = <0 0x00094000 0 0x4000>; 1489 clock-names = "se"; 1490 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1491 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1492 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1493 dma-names = "tx", "rx"; 1494 pinctrl-names = "default"; 1495 pinctrl-0 = <&qup_i2c16_default>; 1496 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1497 #address-cells = <1>; 1498 #size-cells = <0>; 1499 status = "disabled"; 1500 }; 1501 1502 spi16: spi@a94000 { 1503 compatible = "qcom,geni-spi"; 1504 reg = <0 0x00a94000 0 0x4000>; 1505 reg-names = "se"; 1506 clock-names = "se"; 1507 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1508 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1509 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1510 dma-names = "tx", "rx"; 1511 pinctrl-names = "default"; 1512 pinctrl-0 = <&qup_spi16_default>; 1513 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1514 spi-max-frequency = <50000000>; 1515 #address-cells = <1>; 1516 #size-cells = <0>; 1517 status = "disabled"; 1518 }; 1519 }; 1520 1521 gpi_dma2: dma-controller@c00000 { 1522 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 1523 reg = <0 0x00c00000 0 0x60000>; 1524 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; 1537 dma-channels = <13>; 1538 dma-channel-mask = <0xfa>; 1539 iommus = <&apps_smmu 0x07b6 0x0>; 1540 #dma-cells = <3>; 1541 status = "disabled"; 1542 }; 1543 1544 qupv3_id_2: geniqup@cc0000 { 1545 compatible = "qcom,geni-se-qup"; 1546 reg = <0x0 0x00cc0000 0x0 0x6000>; 1547 1548 clock-names = "m-ahb", "s-ahb"; 1549 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1550 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1551 iommus = <&apps_smmu 0x7a3 0x0>; 1552 #address-cells = <2>; 1553 #size-cells = <2>; 1554 ranges; 1555 status = "disabled"; 1556 1557 i2c17: i2c@c80000 { 1558 compatible = "qcom,geni-i2c"; 1559 reg = <0 0x00c80000 0 0x4000>; 1560 clock-names = "se"; 1561 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1562 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1563 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1564 dma-names = "tx", "rx"; 1565 pinctrl-names = "default"; 1566 pinctrl-0 = <&qup_i2c17_default>; 1567 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1568 #address-cells = <1>; 1569 #size-cells = <0>; 1570 status = "disabled"; 1571 }; 1572 1573 spi17: spi@c80000 { 1574 compatible = "qcom,geni-spi"; 1575 reg = <0 0x00c80000 0 0x4000>; 1576 reg-names = "se"; 1577 clock-names = "se"; 1578 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1579 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1580 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1581 dma-names = "tx", "rx"; 1582 pinctrl-names = "default"; 1583 pinctrl-0 = <&qup_spi17_default>; 1584 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1585 spi-max-frequency = <50000000>; 1586 #address-cells = <1>; 1587 #size-cells = <0>; 1588 status = "disabled"; 1589 }; 1590 1591 i2c18: i2c@c84000 { 1592 compatible = "qcom,geni-i2c"; 1593 reg = <0 0x00c84000 0 0x4000>; 1594 clock-names = "se"; 1595 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1596 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1597 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1598 dma-names = "tx", "rx"; 1599 pinctrl-names = "default"; 1600 pinctrl-0 = <&qup_i2c18_default>; 1601 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1602 #address-cells = <1>; 1603 #size-cells = <0>; 1604 status = "disabled"; 1605 }; 1606 1607 spi18: spi@c84000 { 1608 compatible = "qcom,geni-spi"; 1609 reg = <0 0x00c84000 0 0x4000>; 1610 reg-names = "se"; 1611 clock-names = "se"; 1612 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1613 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1614 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1615 dma-names = "tx", "rx"; 1616 pinctrl-names = "default"; 1617 pinctrl-0 = <&qup_spi18_default>; 1618 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1619 spi-max-frequency = <50000000>; 1620 #address-cells = <1>; 1621 #size-cells = <0>; 1622 status = "disabled"; 1623 }; 1624 1625 i2c19: i2c@c88000 { 1626 compatible = "qcom,geni-i2c"; 1627 reg = <0 0x00c88000 0 0x4000>; 1628 clock-names = "se"; 1629 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1630 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1631 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1632 dma-names = "tx", "rx"; 1633 pinctrl-names = "default"; 1634 pinctrl-0 = <&qup_i2c19_default>; 1635 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1636 #address-cells = <1>; 1637 #size-cells = <0>; 1638 status = "disabled"; 1639 }; 1640 1641 spi19: spi@c88000 { 1642 compatible = "qcom,geni-spi"; 1643 reg = <0 0x00c88000 0 0x4000>; 1644 reg-names = "se"; 1645 clock-names = "se"; 1646 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1647 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1648 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1649 dma-names = "tx", "rx"; 1650 pinctrl-names = "default"; 1651 pinctrl-0 = <&qup_spi19_default>; 1652 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1653 spi-max-frequency = <50000000>; 1654 #address-cells = <1>; 1655 #size-cells = <0>; 1656 status = "disabled"; 1657 }; 1658 1659 i2c13: i2c@c8c000 { 1660 compatible = "qcom,geni-i2c"; 1661 reg = <0 0x00c8c000 0 0x4000>; 1662 clock-names = "se"; 1663 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1664 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1665 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1666 dma-names = "tx", "rx"; 1667 pinctrl-names = "default"; 1668 pinctrl-0 = <&qup_i2c13_default>; 1669 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1670 #address-cells = <1>; 1671 #size-cells = <0>; 1672 status = "disabled"; 1673 }; 1674 1675 spi13: spi@c8c000 { 1676 compatible = "qcom,geni-spi"; 1677 reg = <0 0x00c8c000 0 0x4000>; 1678 reg-names = "se"; 1679 clock-names = "se"; 1680 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1681 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1682 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1683 dma-names = "tx", "rx"; 1684 pinctrl-names = "default"; 1685 pinctrl-0 = <&qup_spi13_default>; 1686 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1687 spi-max-frequency = <50000000>; 1688 #address-cells = <1>; 1689 #size-cells = <0>; 1690 status = "disabled"; 1691 }; 1692 1693 i2c14: i2c@c90000 { 1694 compatible = "qcom,geni-i2c"; 1695 reg = <0 0x00c90000 0 0x4000>; 1696 clock-names = "se"; 1697 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1698 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1699 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1700 dma-names = "tx", "rx"; 1701 pinctrl-names = "default"; 1702 pinctrl-0 = <&qup_i2c14_default>; 1703 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1704 #address-cells = <1>; 1705 #size-cells = <0>; 1706 status = "disabled"; 1707 }; 1708 1709 spi14: spi@c90000 { 1710 compatible = "qcom,geni-spi"; 1711 reg = <0 0x00c90000 0 0x4000>; 1712 reg-names = "se"; 1713 clock-names = "se"; 1714 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1715 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1716 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1717 dma-names = "tx", "rx"; 1718 pinctrl-names = "default"; 1719 pinctrl-0 = <&qup_spi14_default>; 1720 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1721 spi-max-frequency = <50000000>; 1722 #address-cells = <1>; 1723 #size-cells = <0>; 1724 status = "disabled"; 1725 }; 1726 1727 i2c15: i2c@c94000 { 1728 compatible = "qcom,geni-i2c"; 1729 reg = <0 0x00c94000 0 0x4000>; 1730 clock-names = "se"; 1731 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1732 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1733 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1734 dma-names = "tx", "rx"; 1735 pinctrl-names = "default"; 1736 pinctrl-0 = <&qup_i2c15_default>; 1737 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1738 #address-cells = <1>; 1739 #size-cells = <0>; 1740 status = "disabled"; 1741 }; 1742 1743 spi15: spi@c94000 { 1744 compatible = "qcom,geni-spi"; 1745 reg = <0 0x00c94000 0 0x4000>; 1746 reg-names = "se"; 1747 clock-names = "se"; 1748 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1749 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1750 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1751 dma-names = "tx", "rx"; 1752 pinctrl-names = "default"; 1753 pinctrl-0 = <&qup_spi15_default>; 1754 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1755 spi-max-frequency = <50000000>; 1756 #address-cells = <1>; 1757 #size-cells = <0>; 1758 status = "disabled"; 1759 }; 1760 }; 1761 1762 config_noc: interconnect@1500000 { 1763 compatible = "qcom,sm8150-config-noc"; 1764 reg = <0 0x01500000 0 0x7400>; 1765 #interconnect-cells = <2>; 1766 qcom,bcm-voters = <&apps_bcm_voter>; 1767 }; 1768 1769 system_noc: interconnect@1620000 { 1770 compatible = "qcom,sm8150-system-noc"; 1771 reg = <0 0x01620000 0 0x19400>; 1772 #interconnect-cells = <2>; 1773 qcom,bcm-voters = <&apps_bcm_voter>; 1774 }; 1775 1776 mc_virt: interconnect@163a000 { 1777 compatible = "qcom,sm8150-mc-virt"; 1778 reg = <0 0x0163a000 0 0x1000>; 1779 #interconnect-cells = <2>; 1780 qcom,bcm-voters = <&apps_bcm_voter>; 1781 }; 1782 1783 aggre1_noc: interconnect@16e0000 { 1784 compatible = "qcom,sm8150-aggre1-noc"; 1785 reg = <0 0x016e0000 0 0xd080>; 1786 #interconnect-cells = <2>; 1787 qcom,bcm-voters = <&apps_bcm_voter>; 1788 }; 1789 1790 aggre2_noc: interconnect@1700000 { 1791 compatible = "qcom,sm8150-aggre2-noc"; 1792 reg = <0 0x01700000 0 0x20000>; 1793 #interconnect-cells = <2>; 1794 qcom,bcm-voters = <&apps_bcm_voter>; 1795 }; 1796 1797 compute_noc: interconnect@1720000 { 1798 compatible = "qcom,sm8150-compute-noc"; 1799 reg = <0 0x01720000 0 0x7000>; 1800 #interconnect-cells = <2>; 1801 qcom,bcm-voters = <&apps_bcm_voter>; 1802 }; 1803 1804 mmss_noc: interconnect@1740000 { 1805 compatible = "qcom,sm8150-mmss-noc"; 1806 reg = <0 0x01740000 0 0x1c100>; 1807 #interconnect-cells = <2>; 1808 qcom,bcm-voters = <&apps_bcm_voter>; 1809 }; 1810 1811 system-cache-controller@9200000 { 1812 compatible = "qcom,sm8150-llcc"; 1813 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, 1814 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, 1815 <0 0x09600000 0 0x50000>; 1816 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 1817 "llcc3_base", "llcc_broadcast_base"; 1818 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1819 }; 1820 1821 dma@10a2000 { 1822 compatible = "qcom,sm8150-dcc", "qcom,dcc"; 1823 reg = <0x0 0x010a2000 0x0 0x1000>, 1824 <0x0 0x010ad000 0x0 0x3000>; 1825 }; 1826 1827 pcie0: pcie@1c00000 { 1828 compatible = "qcom,pcie-sm8150"; 1829 reg = <0 0x01c00000 0 0x3000>, 1830 <0 0x60000000 0 0xf1d>, 1831 <0 0x60000f20 0 0xa8>, 1832 <0 0x60001000 0 0x1000>, 1833 <0 0x60100000 0 0x100000>; 1834 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1835 device_type = "pci"; 1836 linux,pci-domain = <0>; 1837 bus-range = <0x00 0xff>; 1838 num-lanes = <1>; 1839 1840 #address-cells = <3>; 1841 #size-cells = <2>; 1842 1843 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1844 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1845 1846 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1847 interrupt-names = "msi"; 1848 #interrupt-cells = <1>; 1849 interrupt-map-mask = <0 0 0 0x7>; 1850 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1851 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1852 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1853 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1854 1855 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1856 <&gcc GCC_PCIE_0_AUX_CLK>, 1857 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1858 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1859 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1860 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1861 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1862 clock-names = "pipe", 1863 "aux", 1864 "cfg", 1865 "bus_master", 1866 "bus_slave", 1867 "slave_q2a", 1868 "tbu"; 1869 1870 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, 1871 <0x100 &apps_smmu 0x1d81 0x1>; 1872 1873 resets = <&gcc GCC_PCIE_0_BCR>; 1874 reset-names = "pci"; 1875 1876 power-domains = <&gcc PCIE_0_GDSC>; 1877 1878 phys = <&pcie0_phy>; 1879 phy-names = "pciephy"; 1880 1881 perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>; 1882 enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>; 1883 1884 pinctrl-names = "default"; 1885 pinctrl-0 = <&pcie0_default_state>; 1886 1887 status = "disabled"; 1888 }; 1889 1890 pcie0_phy: phy@1c06000 { 1891 compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy"; 1892 reg = <0 0x01c06000 0 0x1000>; 1893 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1894 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1895 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1896 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, 1897 <&gcc GCC_PCIE_0_PIPE_CLK>; 1898 clock-names = "aux", 1899 "cfg_ahb", 1900 "ref", 1901 "refgen", 1902 "pipe"; 1903 1904 clock-output-names = "pcie_0_pipe_clk"; 1905 #clock-cells = <0>; 1906 1907 #phy-cells = <0>; 1908 1909 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1910 reset-names = "phy"; 1911 1912 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1913 assigned-clock-rates = <100000000>; 1914 1915 status = "disabled"; 1916 }; 1917 1918 pcie1: pcie@1c08000 { 1919 compatible = "qcom,pcie-sm8150"; 1920 reg = <0 0x01c08000 0 0x3000>, 1921 <0 0x40000000 0 0xf1d>, 1922 <0 0x40000f20 0 0xa8>, 1923 <0 0x40001000 0 0x1000>, 1924 <0 0x40100000 0 0x100000>; 1925 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1926 device_type = "pci"; 1927 linux,pci-domain = <1>; 1928 bus-range = <0x00 0xff>; 1929 num-lanes = <2>; 1930 1931 #address-cells = <3>; 1932 #size-cells = <2>; 1933 1934 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1935 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1936 1937 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; 1938 interrupt-names = "msi"; 1939 #interrupt-cells = <1>; 1940 interrupt-map-mask = <0 0 0 0x7>; 1941 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1942 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1943 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1944 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1945 1946 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1947 <&gcc GCC_PCIE_1_AUX_CLK>, 1948 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1949 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1950 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1951 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1952 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1953 clock-names = "pipe", 1954 "aux", 1955 "cfg", 1956 "bus_master", 1957 "bus_slave", 1958 "slave_q2a", 1959 "tbu"; 1960 1961 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1962 assigned-clock-rates = <19200000>; 1963 1964 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 1965 <0x100 &apps_smmu 0x1e01 0x1>; 1966 1967 resets = <&gcc GCC_PCIE_1_BCR>; 1968 reset-names = "pci"; 1969 1970 power-domains = <&gcc PCIE_1_GDSC>; 1971 1972 phys = <&pcie1_phy>; 1973 phy-names = "pciephy"; 1974 1975 perst-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; 1976 enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>; 1977 1978 pinctrl-names = "default"; 1979 pinctrl-0 = <&pcie1_default_state>; 1980 1981 status = "disabled"; 1982 }; 1983 1984 pcie1_phy: phy@1c0e000 { 1985 compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy"; 1986 reg = <0 0x01c0e000 0 0x1000>; 1987 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1988 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1989 <&gcc GCC_PCIE_1_CLKREF_CLK>, 1990 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, 1991 <&gcc GCC_PCIE_1_PIPE_CLK>; 1992 clock-names = "aux", 1993 "cfg_ahb", 1994 "ref", 1995 "refgen", 1996 "pipe"; 1997 1998 clock-output-names = "pcie_1_pipe_clk"; 1999 #clock-cells = <0>; 2000 2001 #phy-cells = <0>; 2002 2003 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2004 reset-names = "phy"; 2005 2006 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2007 assigned-clock-rates = <100000000>; 2008 2009 status = "disabled"; 2010 }; 2011 2012 ufs_mem_hc: ufshc@1d84000 { 2013 compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 2014 "jedec,ufs-2.0"; 2015 reg = <0 0x01d84000 0 0x2500>, 2016 <0 0x01d90000 0 0x8000>; 2017 reg-names = "std", "ice"; 2018 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2019 phys = <&ufs_mem_phy>; 2020 phy-names = "ufsphy"; 2021 lanes-per-direction = <2>; 2022 #reset-cells = <1>; 2023 resets = <&gcc GCC_UFS_PHY_BCR>; 2024 reset-names = "rst"; 2025 2026 iommus = <&apps_smmu 0x300 0>; 2027 2028 clock-names = 2029 "core_clk", 2030 "bus_aggr_clk", 2031 "iface_clk", 2032 "core_clk_unipro", 2033 "ref_clk", 2034 "tx_lane0_sync_clk", 2035 "rx_lane0_sync_clk", 2036 "rx_lane1_sync_clk", 2037 "ice_core_clk"; 2038 clocks = 2039 <&gcc GCC_UFS_PHY_AXI_CLK>, 2040 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2041 <&gcc GCC_UFS_PHY_AHB_CLK>, 2042 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2043 <&rpmhcc RPMH_CXO_CLK>, 2044 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2045 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2046 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 2047 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2048 freq-table-hz = 2049 <37500000 300000000>, 2050 <0 0>, 2051 <0 0>, 2052 <37500000 300000000>, 2053 <0 0>, 2054 <0 0>, 2055 <0 0>, 2056 <0 0>, 2057 <0 300000000>; 2058 2059 status = "disabled"; 2060 }; 2061 2062 ufs_mem_phy: phy@1d87000 { 2063 compatible = "qcom,sm8150-qmp-ufs-phy"; 2064 reg = <0 0x01d87000 0 0x1000>; 2065 2066 clock-names = "ref", 2067 "ref_aux"; 2068 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 2069 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2070 2071 power-domains = <&gcc UFS_PHY_GDSC>; 2072 2073 resets = <&ufs_mem_hc 0>; 2074 reset-names = "ufsphy"; 2075 2076 #phy-cells = <0>; 2077 2078 status = "disabled"; 2079 }; 2080 2081 cryptobam: dma-controller@1dc4000 { 2082 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2083 reg = <0 0x01dc4000 0 0x24000>; 2084 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2085 #dma-cells = <1>; 2086 qcom,ee = <0>; 2087 qcom,controlled-remotely; 2088 num-channels = <8>; 2089 qcom,num-ees = <2>; 2090 iommus = <&apps_smmu 0x502 0x0641>, 2091 <&apps_smmu 0x504 0x0011>, 2092 <&apps_smmu 0x506 0x0011>, 2093 <&apps_smmu 0x508 0x0011>, 2094 <&apps_smmu 0x512 0x0000>; 2095 }; 2096 2097 crypto: crypto@1dfa000 { 2098 compatible = "qcom,sm8150-qce", "qcom,qce"; 2099 reg = <0 0x01dfa000 0 0x6000>; 2100 dmas = <&cryptobam 4>, <&cryptobam 5>; 2101 dma-names = "rx", "tx"; 2102 iommus = <&apps_smmu 0x502 0x0641>, 2103 <&apps_smmu 0x504 0x0011>, 2104 <&apps_smmu 0x506 0x0011>, 2105 <&apps_smmu 0x508 0x0011>, 2106 <&apps_smmu 0x512 0x0000>; 2107 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>; 2108 interconnect-names = "memory"; 2109 }; 2110 2111 tcsr_mutex: hwlock@1f40000 { 2112 compatible = "qcom,tcsr-mutex"; 2113 reg = <0x0 0x01f40000 0x0 0x20000>; 2114 #hwlock-cells = <1>; 2115 }; 2116 2117 tcsr_regs_1: syscon@1f60000 { 2118 compatible = "qcom,sm8150-tcsr", "syscon"; 2119 reg = <0x0 0x01f60000 0x0 0x20000>; 2120 }; 2121 2122 remoteproc_slpi: remoteproc@2400000 { 2123 compatible = "qcom,sm8150-slpi-pas"; 2124 reg = <0x0 0x02400000 0x0 0x4040>; 2125 2126 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 2127 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2128 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2129 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2130 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2131 interrupt-names = "wdog", "fatal", "ready", 2132 "handover", "stop-ack"; 2133 2134 clocks = <&rpmhcc RPMH_CXO_CLK>; 2135 clock-names = "xo"; 2136 2137 power-domains = <&rpmhpd SM8150_LCX>, 2138 <&rpmhpd SM8150_LMX>; 2139 power-domain-names = "lcx", "lmx"; 2140 2141 memory-region = <&slpi_mem>; 2142 2143 qcom,qmp = <&aoss_qmp>; 2144 2145 qcom,smem-states = <&slpi_smp2p_out 0>; 2146 qcom,smem-state-names = "stop"; 2147 2148 status = "disabled"; 2149 2150 glink-edge { 2151 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 2152 label = "dsps"; 2153 qcom,remote-pid = <3>; 2154 mboxes = <&apss_shared 24>; 2155 2156 fastrpc { 2157 compatible = "qcom,fastrpc"; 2158 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2159 label = "sdsp"; 2160 qcom,non-secure-domain; 2161 #address-cells = <1>; 2162 #size-cells = <0>; 2163 2164 compute-cb@1 { 2165 compatible = "qcom,fastrpc-compute-cb"; 2166 reg = <1>; 2167 iommus = <&apps_smmu 0x05a1 0x0>; 2168 }; 2169 2170 compute-cb@2 { 2171 compatible = "qcom,fastrpc-compute-cb"; 2172 reg = <2>; 2173 iommus = <&apps_smmu 0x05a2 0x0>; 2174 }; 2175 2176 compute-cb@3 { 2177 compatible = "qcom,fastrpc-compute-cb"; 2178 reg = <3>; 2179 iommus = <&apps_smmu 0x05a3 0x0>; 2180 /* note: shared-cb = <4> in downstream */ 2181 }; 2182 }; 2183 }; 2184 }; 2185 2186 gpu: gpu@2c00000 { 2187 compatible = "qcom,adreno-640.1", "qcom,adreno"; 2188 reg = <0 0x02c00000 0 0x40000>; 2189 reg-names = "kgsl_3d0_reg_memory"; 2190 2191 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2192 2193 iommus = <&adreno_smmu 0 0x401>; 2194 2195 operating-points-v2 = <&gpu_opp_table>; 2196 2197 qcom,gmu = <&gmu>; 2198 2199 nvmem-cells = <&gpu_speed_bin>; 2200 nvmem-cell-names = "speed_bin"; 2201 2202 status = "disabled"; 2203 2204 zap-shader { 2205 memory-region = <&gpu_mem>; 2206 }; 2207 2208 gpu_opp_table: opp-table { 2209 compatible = "operating-points-v2"; 2210 2211 opp-675000000 { 2212 opp-hz = /bits/ 64 <675000000>; 2213 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2214 opp-supported-hw = <0x2>; 2215 }; 2216 2217 opp-585000000 { 2218 opp-hz = /bits/ 64 <585000000>; 2219 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2220 opp-supported-hw = <0x3>; 2221 }; 2222 2223 opp-499200000 { 2224 opp-hz = /bits/ 64 <499200000>; 2225 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2226 opp-supported-hw = <0x3>; 2227 }; 2228 2229 opp-427000000 { 2230 opp-hz = /bits/ 64 <427000000>; 2231 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2232 opp-supported-hw = <0x3>; 2233 }; 2234 2235 opp-345000000 { 2236 opp-hz = /bits/ 64 <345000000>; 2237 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2238 opp-supported-hw = <0x3>; 2239 }; 2240 2241 opp-257000000 { 2242 opp-hz = /bits/ 64 <257000000>; 2243 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2244 opp-supported-hw = <0x3>; 2245 }; 2246 }; 2247 }; 2248 2249 gmu: gmu@2c6a000 { 2250 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 2251 2252 reg = <0 0x02c6a000 0 0x30000>, 2253 <0 0x0b290000 0 0x10000>, 2254 <0 0x0b490000 0 0x10000>; 2255 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2256 2257 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2258 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2259 interrupt-names = "hfi", "gmu"; 2260 2261 clocks = <&gpucc GPU_CC_AHB_CLK>, 2262 <&gpucc GPU_CC_CX_GMU_CLK>, 2263 <&gpucc GPU_CC_CXO_CLK>, 2264 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2265 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2266 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2267 2268 power-domains = <&gpucc GPU_CX_GDSC>, 2269 <&gpucc GPU_GX_GDSC>; 2270 power-domain-names = "cx", "gx"; 2271 2272 iommus = <&adreno_smmu 5 0x400>; 2273 2274 operating-points-v2 = <&gmu_opp_table>; 2275 2276 status = "disabled"; 2277 2278 gmu_opp_table: opp-table { 2279 compatible = "operating-points-v2"; 2280 2281 opp-200000000 { 2282 opp-hz = /bits/ 64 <200000000>; 2283 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2284 }; 2285 }; 2286 }; 2287 2288 gpucc: clock-controller@2c90000 { 2289 compatible = "qcom,sm8150-gpucc"; 2290 reg = <0 0x02c90000 0 0x9000>; 2291 clocks = <&rpmhcc RPMH_CXO_CLK>, 2292 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2293 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2294 clock-names = "bi_tcxo", 2295 "gcc_gpu_gpll0_clk_src", 2296 "gcc_gpu_gpll0_div_clk_src"; 2297 #clock-cells = <1>; 2298 #reset-cells = <1>; 2299 #power-domain-cells = <1>; 2300 }; 2301 2302 adreno_smmu: iommu@2ca0000 { 2303 compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu", 2304 "qcom,smmu-500", "arm,mmu-500"; 2305 reg = <0 0x02ca0000 0 0x10000>; 2306 #iommu-cells = <2>; 2307 #global-interrupts = <1>; 2308 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 2309 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2310 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2311 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2312 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2313 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2314 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2315 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2316 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 2317 clocks = <&gpucc GPU_CC_AHB_CLK>, 2318 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2319 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2320 clock-names = "ahb", "bus", "iface"; 2321 2322 power-domains = <&gpucc GPU_CX_GDSC>; 2323 }; 2324 2325 tlmm: pinctrl@3100000 { 2326 compatible = "qcom,sm8150-pinctrl"; 2327 reg = <0x0 0x03100000 0x0 0x300000>, 2328 <0x0 0x03500000 0x0 0x300000>, 2329 <0x0 0x03900000 0x0 0x300000>, 2330 <0x0 0x03D00000 0x0 0x300000>; 2331 reg-names = "west", "east", "north", "south"; 2332 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2333 gpio-ranges = <&tlmm 0 0 176>; 2334 gpio-controller; 2335 #gpio-cells = <2>; 2336 interrupt-controller; 2337 #interrupt-cells = <2>; 2338 wakeup-parent = <&pdc>; 2339 2340 qup_i2c0_default: qup-i2c0-default-state { 2341 pins = "gpio0", "gpio1"; 2342 function = "qup0"; 2343 drive-strength = <0x02>; 2344 bias-disable; 2345 }; 2346 2347 qup_spi0_default: qup-spi0-default-state { 2348 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 2349 function = "qup0"; 2350 drive-strength = <6>; 2351 bias-disable; 2352 }; 2353 2354 qup_i2c1_default: qup-i2c1-default-state { 2355 pins = "gpio114", "gpio115"; 2356 function = "qup1"; 2357 drive-strength = <2>; 2358 bias-disable; 2359 }; 2360 2361 qup_spi1_default: qup-spi1-default-state { 2362 pins = "gpio114", "gpio115", "gpio116", "gpio117"; 2363 function = "qup1"; 2364 drive-strength = <6>; 2365 bias-disable; 2366 }; 2367 2368 qup_i2c2_default: qup-i2c2-default-state { 2369 pins = "gpio126", "gpio127"; 2370 function = "qup2"; 2371 drive-strength = <2>; 2372 bias-disable; 2373 }; 2374 2375 qup_spi2_default: qup-spi2-default-state { 2376 pins = "gpio126", "gpio127", "gpio128", "gpio129"; 2377 function = "qup2"; 2378 drive-strength = <6>; 2379 bias-disable; 2380 }; 2381 2382 qup_i2c3_default: qup-i2c3-default-state { 2383 pins = "gpio144", "gpio145"; 2384 function = "qup3"; 2385 drive-strength = <2>; 2386 bias-disable; 2387 }; 2388 2389 qup_spi3_default: qup-spi3-default-state { 2390 pins = "gpio144", "gpio145", "gpio146", "gpio147"; 2391 function = "qup3"; 2392 drive-strength = <6>; 2393 bias-disable; 2394 }; 2395 2396 qup_i2c4_default: qup-i2c4-default-state { 2397 pins = "gpio51", "gpio52"; 2398 function = "qup4"; 2399 drive-strength = <2>; 2400 bias-disable; 2401 }; 2402 2403 qup_spi4_default: qup-spi4-default-state { 2404 pins = "gpio51", "gpio52", "gpio53", "gpio54"; 2405 function = "qup4"; 2406 drive-strength = <6>; 2407 bias-disable; 2408 }; 2409 2410 qup_i2c5_default: qup-i2c5-default-state { 2411 pins = "gpio121", "gpio122"; 2412 function = "qup5"; 2413 drive-strength = <2>; 2414 bias-disable; 2415 }; 2416 2417 qup_spi5_default: qup-spi5-default-state { 2418 pins = "gpio119", "gpio120", "gpio121", "gpio122"; 2419 function = "qup5"; 2420 drive-strength = <6>; 2421 bias-disable; 2422 }; 2423 2424 qup_i2c6_default: qup-i2c6-default-state { 2425 pins = "gpio6", "gpio7"; 2426 function = "qup6"; 2427 drive-strength = <2>; 2428 bias-disable; 2429 }; 2430 2431 qup_spi6_default: qup-spi6_default-state { 2432 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 2433 function = "qup6"; 2434 drive-strength = <6>; 2435 bias-disable; 2436 }; 2437 2438 qup_i2c7_default: qup-i2c7-default-state { 2439 pins = "gpio98", "gpio99"; 2440 function = "qup7"; 2441 drive-strength = <2>; 2442 bias-disable; 2443 }; 2444 2445 qup_spi7_default: qup-spi7_default-state { 2446 pins = "gpio98", "gpio99", "gpio100", "gpio101"; 2447 function = "qup7"; 2448 drive-strength = <6>; 2449 bias-disable; 2450 }; 2451 2452 qup_i2c8_default: qup-i2c8-default-state { 2453 pins = "gpio88", "gpio89"; 2454 function = "qup8"; 2455 drive-strength = <2>; 2456 bias-disable; 2457 }; 2458 2459 qup_spi8_default: qup-spi8-default-state { 2460 pins = "gpio88", "gpio89", "gpio90", "gpio91"; 2461 function = "qup8"; 2462 drive-strength = <6>; 2463 bias-disable; 2464 }; 2465 2466 qup_i2c9_default: qup-i2c9-default-state { 2467 pins = "gpio39", "gpio40"; 2468 function = "qup9"; 2469 drive-strength = <2>; 2470 bias-disable; 2471 }; 2472 2473 qup_spi9_default: qup-spi9-default-state { 2474 pins = "gpio39", "gpio40", "gpio41", "gpio42"; 2475 function = "qup9"; 2476 drive-strength = <6>; 2477 bias-disable; 2478 }; 2479 2480 qup_uart9_default: qup-uart9-default-state { 2481 pins = "gpio41", "gpio42"; 2482 function = "qup9"; 2483 drive-strength = <2>; 2484 bias-disable; 2485 }; 2486 2487 qup_i2c10_default: qup-i2c10-default-state { 2488 pins = "gpio9", "gpio10"; 2489 function = "qup10"; 2490 drive-strength = <2>; 2491 bias-disable; 2492 }; 2493 2494 qup_spi10_default: qup-spi10-default-state { 2495 pins = "gpio9", "gpio10", "gpio11", "gpio12"; 2496 function = "qup10"; 2497 drive-strength = <6>; 2498 bias-disable; 2499 }; 2500 2501 qup_i2c11_default: qup-i2c11-default-state { 2502 pins = "gpio94", "gpio95"; 2503 function = "qup11"; 2504 drive-strength = <2>; 2505 bias-disable; 2506 }; 2507 2508 qup_spi11_default: qup-spi11-default-state { 2509 pins = "gpio92", "gpio93", "gpio94", "gpio95"; 2510 function = "qup11"; 2511 drive-strength = <6>; 2512 bias-disable; 2513 }; 2514 2515 qup_i2c12_default: qup-i2c12-default-state { 2516 pins = "gpio83", "gpio84"; 2517 function = "qup12"; 2518 drive-strength = <2>; 2519 bias-disable; 2520 }; 2521 2522 qup_spi12_default: qup-spi12-default-state { 2523 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2524 function = "qup12"; 2525 drive-strength = <6>; 2526 bias-disable; 2527 }; 2528 2529 qup_i2c13_default: qup-i2c13-default-state { 2530 pins = "gpio43", "gpio44"; 2531 function = "qup13"; 2532 drive-strength = <2>; 2533 bias-disable; 2534 }; 2535 2536 qup_spi13_default: qup-spi13-default-state { 2537 pins = "gpio43", "gpio44", "gpio45", "gpio46"; 2538 function = "qup13"; 2539 drive-strength = <6>; 2540 bias-disable; 2541 }; 2542 2543 qup_i2c14_default: qup-i2c14-default-state { 2544 pins = "gpio47", "gpio48"; 2545 function = "qup14"; 2546 drive-strength = <2>; 2547 bias-disable; 2548 }; 2549 2550 qup_spi14_default: qup-spi14-default-state { 2551 pins = "gpio47", "gpio48", "gpio49", "gpio50"; 2552 function = "qup14"; 2553 drive-strength = <6>; 2554 bias-disable; 2555 }; 2556 2557 qup_i2c15_default: qup-i2c15-default-state { 2558 pins = "gpio27", "gpio28"; 2559 function = "qup15"; 2560 drive-strength = <2>; 2561 bias-disable; 2562 }; 2563 2564 qup_spi15_default: qup-spi15-default-state { 2565 pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2566 function = "qup15"; 2567 drive-strength = <6>; 2568 bias-disable; 2569 }; 2570 2571 qup_i2c16_default: qup-i2c16-default-state { 2572 pins = "gpio86", "gpio85"; 2573 function = "qup16"; 2574 drive-strength = <2>; 2575 bias-disable; 2576 }; 2577 2578 qup_spi16_default: qup-spi16-default-state { 2579 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2580 function = "qup16"; 2581 drive-strength = <6>; 2582 bias-disable; 2583 }; 2584 2585 qup_i2c17_default: qup-i2c17-default-state { 2586 pins = "gpio55", "gpio56"; 2587 function = "qup17"; 2588 drive-strength = <2>; 2589 bias-disable; 2590 }; 2591 2592 qup_spi17_default: qup-spi17-default-state { 2593 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2594 function = "qup17"; 2595 drive-strength = <6>; 2596 bias-disable; 2597 }; 2598 2599 qup_i2c18_default: qup-i2c18-default-state { 2600 pins = "gpio23", "gpio24"; 2601 function = "qup18"; 2602 drive-strength = <2>; 2603 bias-disable; 2604 }; 2605 2606 qup_spi18_default: qup-spi18-default-state { 2607 pins = "gpio23", "gpio24", "gpio25", "gpio26"; 2608 function = "qup18"; 2609 drive-strength = <6>; 2610 bias-disable; 2611 }; 2612 2613 qup_i2c19_default: qup-i2c19-default-state { 2614 pins = "gpio57", "gpio58"; 2615 function = "qup19"; 2616 drive-strength = <2>; 2617 bias-disable; 2618 }; 2619 2620 qup_spi19_default: qup-spi19-default-state { 2621 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2622 function = "qup19"; 2623 drive-strength = <6>; 2624 bias-disable; 2625 }; 2626 2627 pcie0_default_state: pcie0-default-state { 2628 perst-pins { 2629 pins = "gpio35"; 2630 function = "gpio"; 2631 drive-strength = <2>; 2632 bias-pull-down; 2633 }; 2634 2635 clkreq-pins { 2636 pins = "gpio36"; 2637 function = "pci_e0"; 2638 drive-strength = <2>; 2639 bias-pull-up; 2640 }; 2641 2642 wake-pins { 2643 pins = "gpio37"; 2644 function = "gpio"; 2645 drive-strength = <2>; 2646 bias-pull-up; 2647 }; 2648 }; 2649 2650 pcie1_default_state: pcie1-default-state { 2651 perst-pins { 2652 pins = "gpio102"; 2653 function = "gpio"; 2654 drive-strength = <2>; 2655 bias-pull-down; 2656 }; 2657 2658 clkreq-pins { 2659 pins = "gpio103"; 2660 function = "pci_e1"; 2661 drive-strength = <2>; 2662 bias-pull-up; 2663 }; 2664 2665 wake-pins { 2666 pins = "gpio104"; 2667 function = "gpio"; 2668 drive-strength = <2>; 2669 bias-pull-up; 2670 }; 2671 }; 2672 }; 2673 2674 remoteproc_mpss: remoteproc@4080000 { 2675 compatible = "qcom,sm8150-mpss-pas"; 2676 reg = <0x0 0x04080000 0x0 0x4040>; 2677 2678 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2679 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2680 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2681 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2682 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2683 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2684 interrupt-names = "wdog", "fatal", "ready", "handover", 2685 "stop-ack", "shutdown-ack"; 2686 2687 clocks = <&rpmhcc RPMH_CXO_CLK>; 2688 clock-names = "xo"; 2689 2690 power-domains = <&rpmhpd SM8150_CX>, 2691 <&rpmhpd SM8150_MSS>; 2692 power-domain-names = "cx", "mss"; 2693 2694 memory-region = <&mpss_mem>; 2695 2696 qcom,qmp = <&aoss_qmp>; 2697 2698 qcom,smem-states = <&modem_smp2p_out 0>; 2699 qcom,smem-state-names = "stop"; 2700 2701 status = "disabled"; 2702 2703 glink-edge { 2704 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2705 label = "modem"; 2706 qcom,remote-pid = <1>; 2707 mboxes = <&apss_shared 12>; 2708 }; 2709 }; 2710 2711 stm@6002000 { 2712 compatible = "arm,coresight-stm", "arm,primecell"; 2713 reg = <0 0x06002000 0 0x1000>, 2714 <0 0x16280000 0 0x180000>; 2715 reg-names = "stm-base", "stm-stimulus-base"; 2716 2717 clocks = <&aoss_qmp>; 2718 clock-names = "apb_pclk"; 2719 2720 out-ports { 2721 port { 2722 stm_out: endpoint { 2723 remote-endpoint = <&funnel0_in7>; 2724 }; 2725 }; 2726 }; 2727 }; 2728 2729 funnel@6041000 { 2730 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2731 reg = <0 0x06041000 0 0x1000>; 2732 2733 clocks = <&aoss_qmp>; 2734 clock-names = "apb_pclk"; 2735 2736 out-ports { 2737 port { 2738 funnel0_out: endpoint { 2739 remote-endpoint = <&merge_funnel_in0>; 2740 }; 2741 }; 2742 }; 2743 2744 in-ports { 2745 #address-cells = <1>; 2746 #size-cells = <0>; 2747 2748 port@7 { 2749 reg = <7>; 2750 funnel0_in7: endpoint { 2751 remote-endpoint = <&stm_out>; 2752 }; 2753 }; 2754 }; 2755 }; 2756 2757 funnel@6042000 { 2758 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2759 reg = <0 0x06042000 0 0x1000>; 2760 2761 clocks = <&aoss_qmp>; 2762 clock-names = "apb_pclk"; 2763 2764 out-ports { 2765 port { 2766 funnel1_out: endpoint { 2767 remote-endpoint = <&merge_funnel_in1>; 2768 }; 2769 }; 2770 }; 2771 2772 in-ports { 2773 #address-cells = <1>; 2774 #size-cells = <0>; 2775 2776 port@4 { 2777 reg = <4>; 2778 funnel1_in4: endpoint { 2779 remote-endpoint = <&swao_replicator_out>; 2780 }; 2781 }; 2782 }; 2783 }; 2784 2785 funnel@6043000 { 2786 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2787 reg = <0 0x06043000 0 0x1000>; 2788 2789 clocks = <&aoss_qmp>; 2790 clock-names = "apb_pclk"; 2791 2792 out-ports { 2793 port { 2794 funnel2_out: endpoint { 2795 remote-endpoint = <&merge_funnel_in2>; 2796 }; 2797 }; 2798 }; 2799 2800 in-ports { 2801 #address-cells = <1>; 2802 #size-cells = <0>; 2803 2804 port@2 { 2805 reg = <2>; 2806 funnel2_in2: endpoint { 2807 remote-endpoint = <&apss_merge_funnel_out>; 2808 }; 2809 }; 2810 }; 2811 }; 2812 2813 funnel@6045000 { 2814 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2815 reg = <0 0x06045000 0 0x1000>; 2816 2817 clocks = <&aoss_qmp>; 2818 clock-names = "apb_pclk"; 2819 2820 out-ports { 2821 port { 2822 merge_funnel_out: endpoint { 2823 remote-endpoint = <&etf_in>; 2824 }; 2825 }; 2826 }; 2827 2828 in-ports { 2829 #address-cells = <1>; 2830 #size-cells = <0>; 2831 2832 port@0 { 2833 reg = <0>; 2834 merge_funnel_in0: endpoint { 2835 remote-endpoint = <&funnel0_out>; 2836 }; 2837 }; 2838 2839 port@1 { 2840 reg = <1>; 2841 merge_funnel_in1: endpoint { 2842 remote-endpoint = <&funnel1_out>; 2843 }; 2844 }; 2845 2846 port@2 { 2847 reg = <2>; 2848 merge_funnel_in2: endpoint { 2849 remote-endpoint = <&funnel2_out>; 2850 }; 2851 }; 2852 }; 2853 }; 2854 2855 replicator@6046000 { 2856 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2857 reg = <0 0x06046000 0 0x1000>; 2858 2859 clocks = <&aoss_qmp>; 2860 clock-names = "apb_pclk"; 2861 2862 out-ports { 2863 #address-cells = <1>; 2864 #size-cells = <0>; 2865 2866 port@0 { 2867 reg = <0>; 2868 replicator_out0: endpoint { 2869 remote-endpoint = <&etr_in>; 2870 }; 2871 }; 2872 2873 port@1 { 2874 reg = <1>; 2875 replicator_out1: endpoint { 2876 remote-endpoint = <&replicator1_in>; 2877 }; 2878 }; 2879 }; 2880 2881 in-ports { 2882 port { 2883 replicator_in0: endpoint { 2884 remote-endpoint = <&etf_out>; 2885 }; 2886 }; 2887 }; 2888 }; 2889 2890 etf@6047000 { 2891 compatible = "arm,coresight-tmc", "arm,primecell"; 2892 reg = <0 0x06047000 0 0x1000>; 2893 2894 clocks = <&aoss_qmp>; 2895 clock-names = "apb_pclk"; 2896 2897 out-ports { 2898 port { 2899 etf_out: endpoint { 2900 remote-endpoint = <&replicator_in0>; 2901 }; 2902 }; 2903 }; 2904 2905 in-ports { 2906 port { 2907 etf_in: endpoint { 2908 remote-endpoint = <&merge_funnel_out>; 2909 }; 2910 }; 2911 }; 2912 }; 2913 2914 etr@6048000 { 2915 compatible = "arm,coresight-tmc", "arm,primecell"; 2916 reg = <0 0x06048000 0 0x1000>; 2917 iommus = <&apps_smmu 0x05e0 0x0>; 2918 2919 clocks = <&aoss_qmp>; 2920 clock-names = "apb_pclk"; 2921 arm,scatter-gather; 2922 2923 in-ports { 2924 port { 2925 etr_in: endpoint { 2926 remote-endpoint = <&replicator_out0>; 2927 }; 2928 }; 2929 }; 2930 }; 2931 2932 replicator@604a000 { 2933 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2934 reg = <0 0x0604a000 0 0x1000>; 2935 2936 clocks = <&aoss_qmp>; 2937 clock-names = "apb_pclk"; 2938 2939 out-ports { 2940 #address-cells = <1>; 2941 #size-cells = <0>; 2942 2943 port@1 { 2944 reg = <1>; 2945 replicator1_out: endpoint { 2946 remote-endpoint = <&swao_funnel_in>; 2947 }; 2948 }; 2949 }; 2950 2951 in-ports { 2952 2953 port { 2954 replicator1_in: endpoint { 2955 remote-endpoint = <&replicator_out1>; 2956 }; 2957 }; 2958 }; 2959 }; 2960 2961 funnel@6b08000 { 2962 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2963 reg = <0 0x06b08000 0 0x1000>; 2964 2965 clocks = <&aoss_qmp>; 2966 clock-names = "apb_pclk"; 2967 2968 out-ports { 2969 port { 2970 swao_funnel_out: endpoint { 2971 remote-endpoint = <&swao_etf_in>; 2972 }; 2973 }; 2974 }; 2975 2976 in-ports { 2977 #address-cells = <1>; 2978 #size-cells = <0>; 2979 2980 port@6 { 2981 reg = <6>; 2982 swao_funnel_in: endpoint { 2983 remote-endpoint = <&replicator1_out>; 2984 }; 2985 }; 2986 }; 2987 }; 2988 2989 etf@6b09000 { 2990 compatible = "arm,coresight-tmc", "arm,primecell"; 2991 reg = <0 0x06b09000 0 0x1000>; 2992 2993 clocks = <&aoss_qmp>; 2994 clock-names = "apb_pclk"; 2995 2996 out-ports { 2997 port { 2998 swao_etf_out: endpoint { 2999 remote-endpoint = <&swao_replicator_in>; 3000 }; 3001 }; 3002 }; 3003 3004 in-ports { 3005 port { 3006 swao_etf_in: endpoint { 3007 remote-endpoint = <&swao_funnel_out>; 3008 }; 3009 }; 3010 }; 3011 }; 3012 3013 replicator@6b0a000 { 3014 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3015 reg = <0 0x06b0a000 0 0x1000>; 3016 3017 clocks = <&aoss_qmp>; 3018 clock-names = "apb_pclk"; 3019 qcom,replicator-loses-context; 3020 3021 out-ports { 3022 port { 3023 swao_replicator_out: endpoint { 3024 remote-endpoint = <&funnel1_in4>; 3025 }; 3026 }; 3027 }; 3028 3029 in-ports { 3030 port { 3031 swao_replicator_in: endpoint { 3032 remote-endpoint = <&swao_etf_out>; 3033 }; 3034 }; 3035 }; 3036 }; 3037 3038 etm@7040000 { 3039 compatible = "arm,coresight-etm4x", "arm,primecell"; 3040 reg = <0 0x07040000 0 0x1000>; 3041 3042 cpu = <&CPU0>; 3043 3044 clocks = <&aoss_qmp>; 3045 clock-names = "apb_pclk"; 3046 arm,coresight-loses-context-with-cpu; 3047 qcom,skip-power-up; 3048 3049 out-ports { 3050 port { 3051 etm0_out: endpoint { 3052 remote-endpoint = <&apss_funnel_in0>; 3053 }; 3054 }; 3055 }; 3056 }; 3057 3058 etm@7140000 { 3059 compatible = "arm,coresight-etm4x", "arm,primecell"; 3060 reg = <0 0x07140000 0 0x1000>; 3061 3062 cpu = <&CPU1>; 3063 3064 clocks = <&aoss_qmp>; 3065 clock-names = "apb_pclk"; 3066 arm,coresight-loses-context-with-cpu; 3067 qcom,skip-power-up; 3068 3069 out-ports { 3070 port { 3071 etm1_out: endpoint { 3072 remote-endpoint = <&apss_funnel_in1>; 3073 }; 3074 }; 3075 }; 3076 }; 3077 3078 etm@7240000 { 3079 compatible = "arm,coresight-etm4x", "arm,primecell"; 3080 reg = <0 0x07240000 0 0x1000>; 3081 3082 cpu = <&CPU2>; 3083 3084 clocks = <&aoss_qmp>; 3085 clock-names = "apb_pclk"; 3086 arm,coresight-loses-context-with-cpu; 3087 qcom,skip-power-up; 3088 3089 out-ports { 3090 port { 3091 etm2_out: endpoint { 3092 remote-endpoint = <&apss_funnel_in2>; 3093 }; 3094 }; 3095 }; 3096 }; 3097 3098 etm@7340000 { 3099 compatible = "arm,coresight-etm4x", "arm,primecell"; 3100 reg = <0 0x07340000 0 0x1000>; 3101 3102 cpu = <&CPU3>; 3103 3104 clocks = <&aoss_qmp>; 3105 clock-names = "apb_pclk"; 3106 arm,coresight-loses-context-with-cpu; 3107 qcom,skip-power-up; 3108 3109 out-ports { 3110 port { 3111 etm3_out: endpoint { 3112 remote-endpoint = <&apss_funnel_in3>; 3113 }; 3114 }; 3115 }; 3116 }; 3117 3118 etm@7440000 { 3119 compatible = "arm,coresight-etm4x", "arm,primecell"; 3120 reg = <0 0x07440000 0 0x1000>; 3121 3122 cpu = <&CPU4>; 3123 3124 clocks = <&aoss_qmp>; 3125 clock-names = "apb_pclk"; 3126 arm,coresight-loses-context-with-cpu; 3127 qcom,skip-power-up; 3128 3129 out-ports { 3130 port { 3131 etm4_out: endpoint { 3132 remote-endpoint = <&apss_funnel_in4>; 3133 }; 3134 }; 3135 }; 3136 }; 3137 3138 etm@7540000 { 3139 compatible = "arm,coresight-etm4x", "arm,primecell"; 3140 reg = <0 0x07540000 0 0x1000>; 3141 3142 cpu = <&CPU5>; 3143 3144 clocks = <&aoss_qmp>; 3145 clock-names = "apb_pclk"; 3146 arm,coresight-loses-context-with-cpu; 3147 qcom,skip-power-up; 3148 3149 out-ports { 3150 port { 3151 etm5_out: endpoint { 3152 remote-endpoint = <&apss_funnel_in5>; 3153 }; 3154 }; 3155 }; 3156 }; 3157 3158 etm@7640000 { 3159 compatible = "arm,coresight-etm4x", "arm,primecell"; 3160 reg = <0 0x07640000 0 0x1000>; 3161 3162 cpu = <&CPU6>; 3163 3164 clocks = <&aoss_qmp>; 3165 clock-names = "apb_pclk"; 3166 arm,coresight-loses-context-with-cpu; 3167 qcom,skip-power-up; 3168 3169 out-ports { 3170 port { 3171 etm6_out: endpoint { 3172 remote-endpoint = <&apss_funnel_in6>; 3173 }; 3174 }; 3175 }; 3176 }; 3177 3178 etm@7740000 { 3179 compatible = "arm,coresight-etm4x", "arm,primecell"; 3180 reg = <0 0x07740000 0 0x1000>; 3181 3182 cpu = <&CPU7>; 3183 3184 clocks = <&aoss_qmp>; 3185 clock-names = "apb_pclk"; 3186 arm,coresight-loses-context-with-cpu; 3187 qcom,skip-power-up; 3188 3189 out-ports { 3190 port { 3191 etm7_out: endpoint { 3192 remote-endpoint = <&apss_funnel_in7>; 3193 }; 3194 }; 3195 }; 3196 }; 3197 3198 funnel@7800000 { /* APSS Funnel */ 3199 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3200 reg = <0 0x07800000 0 0x1000>; 3201 3202 clocks = <&aoss_qmp>; 3203 clock-names = "apb_pclk"; 3204 3205 out-ports { 3206 port { 3207 apss_funnel_out: endpoint { 3208 remote-endpoint = <&apss_merge_funnel_in>; 3209 }; 3210 }; 3211 }; 3212 3213 in-ports { 3214 #address-cells = <1>; 3215 #size-cells = <0>; 3216 3217 port@0 { 3218 reg = <0>; 3219 apss_funnel_in0: endpoint { 3220 remote-endpoint = <&etm0_out>; 3221 }; 3222 }; 3223 3224 port@1 { 3225 reg = <1>; 3226 apss_funnel_in1: endpoint { 3227 remote-endpoint = <&etm1_out>; 3228 }; 3229 }; 3230 3231 port@2 { 3232 reg = <2>; 3233 apss_funnel_in2: endpoint { 3234 remote-endpoint = <&etm2_out>; 3235 }; 3236 }; 3237 3238 port@3 { 3239 reg = <3>; 3240 apss_funnel_in3: endpoint { 3241 remote-endpoint = <&etm3_out>; 3242 }; 3243 }; 3244 3245 port@4 { 3246 reg = <4>; 3247 apss_funnel_in4: endpoint { 3248 remote-endpoint = <&etm4_out>; 3249 }; 3250 }; 3251 3252 port@5 { 3253 reg = <5>; 3254 apss_funnel_in5: endpoint { 3255 remote-endpoint = <&etm5_out>; 3256 }; 3257 }; 3258 3259 port@6 { 3260 reg = <6>; 3261 apss_funnel_in6: endpoint { 3262 remote-endpoint = <&etm6_out>; 3263 }; 3264 }; 3265 3266 port@7 { 3267 reg = <7>; 3268 apss_funnel_in7: endpoint { 3269 remote-endpoint = <&etm7_out>; 3270 }; 3271 }; 3272 }; 3273 }; 3274 3275 funnel@7810000 { 3276 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3277 reg = <0 0x07810000 0 0x1000>; 3278 3279 clocks = <&aoss_qmp>; 3280 clock-names = "apb_pclk"; 3281 3282 out-ports { 3283 port { 3284 apss_merge_funnel_out: endpoint { 3285 remote-endpoint = <&funnel2_in2>; 3286 }; 3287 }; 3288 }; 3289 3290 in-ports { 3291 port { 3292 apss_merge_funnel_in: endpoint { 3293 remote-endpoint = <&apss_funnel_out>; 3294 }; 3295 }; 3296 }; 3297 }; 3298 3299 remoteproc_cdsp: remoteproc@8300000 { 3300 compatible = "qcom,sm8150-cdsp-pas"; 3301 reg = <0x0 0x08300000 0x0 0x4040>; 3302 3303 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3304 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3305 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3306 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3307 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3308 interrupt-names = "wdog", "fatal", "ready", 3309 "handover", "stop-ack"; 3310 3311 clocks = <&rpmhcc RPMH_CXO_CLK>; 3312 clock-names = "xo"; 3313 3314 power-domains = <&rpmhpd SM8150_CX>; 3315 3316 memory-region = <&cdsp_mem>; 3317 3318 qcom,qmp = <&aoss_qmp>; 3319 3320 qcom,smem-states = <&cdsp_smp2p_out 0>; 3321 qcom,smem-state-names = "stop"; 3322 3323 status = "disabled"; 3324 3325 glink-edge { 3326 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 3327 label = "cdsp"; 3328 qcom,remote-pid = <5>; 3329 mboxes = <&apss_shared 4>; 3330 3331 fastrpc { 3332 compatible = "qcom,fastrpc"; 3333 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3334 label = "cdsp"; 3335 qcom,non-secure-domain; 3336 #address-cells = <1>; 3337 #size-cells = <0>; 3338 3339 compute-cb@1 { 3340 compatible = "qcom,fastrpc-compute-cb"; 3341 reg = <1>; 3342 iommus = <&apps_smmu 0x1001 0x0460>; 3343 }; 3344 3345 compute-cb@2 { 3346 compatible = "qcom,fastrpc-compute-cb"; 3347 reg = <2>; 3348 iommus = <&apps_smmu 0x1002 0x0460>; 3349 }; 3350 3351 compute-cb@3 { 3352 compatible = "qcom,fastrpc-compute-cb"; 3353 reg = <3>; 3354 iommus = <&apps_smmu 0x1003 0x0460>; 3355 }; 3356 3357 compute-cb@4 { 3358 compatible = "qcom,fastrpc-compute-cb"; 3359 reg = <4>; 3360 iommus = <&apps_smmu 0x1004 0x0460>; 3361 }; 3362 3363 compute-cb@5 { 3364 compatible = "qcom,fastrpc-compute-cb"; 3365 reg = <5>; 3366 iommus = <&apps_smmu 0x1005 0x0460>; 3367 }; 3368 3369 compute-cb@6 { 3370 compatible = "qcom,fastrpc-compute-cb"; 3371 reg = <6>; 3372 iommus = <&apps_smmu 0x1006 0x0460>; 3373 }; 3374 3375 compute-cb@7 { 3376 compatible = "qcom,fastrpc-compute-cb"; 3377 reg = <7>; 3378 iommus = <&apps_smmu 0x1007 0x0460>; 3379 }; 3380 3381 compute-cb@8 { 3382 compatible = "qcom,fastrpc-compute-cb"; 3383 reg = <8>; 3384 iommus = <&apps_smmu 0x1008 0x0460>; 3385 }; 3386 3387 /* note: secure cb9 in downstream */ 3388 }; 3389 }; 3390 }; 3391 3392 usb_1_hsphy: phy@88e2000 { 3393 compatible = "qcom,sm8150-usb-hs-phy", 3394 "qcom,usb-snps-hs-7nm-phy"; 3395 reg = <0 0x088e2000 0 0x400>; 3396 status = "disabled"; 3397 #phy-cells = <0>; 3398 3399 clocks = <&rpmhcc RPMH_CXO_CLK>; 3400 clock-names = "ref"; 3401 3402 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3403 }; 3404 3405 usb_2_hsphy: phy@88e3000 { 3406 compatible = "qcom,sm8150-usb-hs-phy", 3407 "qcom,usb-snps-hs-7nm-phy"; 3408 reg = <0 0x088e3000 0 0x400>; 3409 status = "disabled"; 3410 #phy-cells = <0>; 3411 3412 clocks = <&rpmhcc RPMH_CXO_CLK>; 3413 clock-names = "ref"; 3414 3415 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3416 }; 3417 3418 usb_1_qmpphy: phy@88e8000 { 3419 compatible = "qcom,sm8150-qmp-usb3-dp-phy"; 3420 reg = <0 0x088e8000 0 0x3000>; 3421 3422 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3423 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3424 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3425 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3426 clock-names = "aux", 3427 "ref", 3428 "com_aux", 3429 "usb3_pipe"; 3430 3431 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3432 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3433 reset-names = "phy", "common"; 3434 3435 #clock-cells = <1>; 3436 #phy-cells = <1>; 3437 3438 status = "disabled"; 3439 3440 ports { 3441 #address-cells = <1>; 3442 #size-cells = <0>; 3443 3444 port@0 { 3445 reg = <0>; 3446 3447 usb_1_qmpphy_out: endpoint { 3448 }; 3449 }; 3450 3451 port@1 { 3452 reg = <1>; 3453 3454 usb_1_qmpphy_usb_ss_in: endpoint { 3455 }; 3456 }; 3457 3458 port@2 { 3459 reg = <2>; 3460 3461 usb_1_qmpphy_dp_in: endpoint { 3462 }; 3463 }; 3464 }; 3465 }; 3466 3467 usb_2_qmpphy: phy@88eb000 { 3468 compatible = "qcom,sm8150-qmp-usb3-uni-phy"; 3469 reg = <0 0x088eb000 0 0x1000>; 3470 3471 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3472 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 3473 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 3474 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3475 clock-names = "aux", 3476 "ref", 3477 "com_aux", 3478 "pipe"; 3479 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3480 #clock-cells = <0>; 3481 #phy-cells = <0>; 3482 3483 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 3484 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 3485 reset-names = "phy", 3486 "phy_phy"; 3487 3488 status = "disabled"; 3489 }; 3490 3491 sdhc_2: mmc@8804000 { 3492 compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5"; 3493 reg = <0 0x08804000 0 0x1000>; 3494 3495 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3496 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3497 interrupt-names = "hc_irq", "pwr_irq"; 3498 3499 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3500 <&gcc GCC_SDCC2_APPS_CLK>, 3501 <&rpmhcc RPMH_CXO_CLK>; 3502 clock-names = "iface", "core", "xo"; 3503 iommus = <&apps_smmu 0x6a0 0x0>; 3504 qcom,dll-config = <0x0007642c>; 3505 qcom,ddr-config = <0x80040868>; 3506 power-domains = <&rpmhpd 0>; 3507 operating-points-v2 = <&sdhc2_opp_table>; 3508 3509 status = "disabled"; 3510 3511 sdhc2_opp_table: opp-table { 3512 compatible = "operating-points-v2"; 3513 3514 opp-19200000 { 3515 opp-hz = /bits/ 64 <19200000>; 3516 required-opps = <&rpmhpd_opp_min_svs>; 3517 }; 3518 3519 opp-50000000 { 3520 opp-hz = /bits/ 64 <50000000>; 3521 required-opps = <&rpmhpd_opp_low_svs>; 3522 }; 3523 3524 opp-100000000 { 3525 opp-hz = /bits/ 64 <100000000>; 3526 required-opps = <&rpmhpd_opp_svs>; 3527 }; 3528 3529 opp-202000000 { 3530 opp-hz = /bits/ 64 <202000000>; 3531 required-opps = <&rpmhpd_opp_svs_l1>; 3532 }; 3533 }; 3534 }; 3535 3536 dc_noc: interconnect@9160000 { 3537 compatible = "qcom,sm8150-dc-noc"; 3538 reg = <0 0x09160000 0 0x3200>; 3539 #interconnect-cells = <2>; 3540 qcom,bcm-voters = <&apps_bcm_voter>; 3541 }; 3542 3543 gem_noc: interconnect@9680000 { 3544 compatible = "qcom,sm8150-gem-noc"; 3545 reg = <0 0x09680000 0 0x3e200>; 3546 #interconnect-cells = <2>; 3547 qcom,bcm-voters = <&apps_bcm_voter>; 3548 }; 3549 3550 usb_1: usb@a6f8800 { 3551 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3552 reg = <0 0x0a6f8800 0 0x400>; 3553 status = "disabled"; 3554 #address-cells = <2>; 3555 #size-cells = <2>; 3556 ranges; 3557 dma-ranges; 3558 3559 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3560 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3561 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3562 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3563 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3564 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3565 clock-names = "cfg_noc", 3566 "core", 3567 "iface", 3568 "sleep", 3569 "mock_utmi", 3570 "xo"; 3571 3572 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3573 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3574 assigned-clock-rates = <19200000>, <200000000>; 3575 3576 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3577 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 3578 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 3579 <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 3580 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3581 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3582 3583 power-domains = <&gcc USB30_PRIM_GDSC>; 3584 3585 resets = <&gcc GCC_USB30_PRIM_BCR>; 3586 3587 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, 3588 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 3589 interconnect-names = "usb-ddr", "apps-usb"; 3590 3591 usb_1_dwc3: usb@a600000 { 3592 compatible = "snps,dwc3"; 3593 reg = <0 0x0a600000 0 0xcd00>; 3594 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3595 iommus = <&apps_smmu 0x140 0>; 3596 snps,dis_u2_susphy_quirk; 3597 snps,dis_enblslpm_quirk; 3598 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 3599 phy-names = "usb2-phy", "usb3-phy"; 3600 3601 ports { 3602 #address-cells = <1>; 3603 #size-cells = <0>; 3604 3605 port@0 { 3606 reg = <0>; 3607 3608 usb_1_dwc3_hs: endpoint { 3609 }; 3610 }; 3611 3612 port@1 { 3613 reg = <1>; 3614 3615 usb_1_dwc3_ss: endpoint { 3616 }; 3617 }; 3618 }; 3619 }; 3620 }; 3621 3622 usb_2: usb@a8f8800 { 3623 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3624 reg = <0 0x0a8f8800 0 0x400>; 3625 status = "disabled"; 3626 #address-cells = <2>; 3627 #size-cells = <2>; 3628 ranges; 3629 dma-ranges; 3630 3631 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3632 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3633 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3634 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3635 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3636 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3637 clock-names = "cfg_noc", 3638 "core", 3639 "iface", 3640 "sleep", 3641 "mock_utmi", 3642 "xo"; 3643 3644 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3645 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3646 assigned-clock-rates = <19200000>, <200000000>; 3647 3648 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3649 <&pdc 7 IRQ_TYPE_LEVEL_HIGH>, 3650 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 3651 <&pdc 11 IRQ_TYPE_EDGE_BOTH>; 3652 interrupt-names = "hs_phy_irq", "ss_phy_irq", 3653 "dm_hs_phy_irq", "dp_hs_phy_irq"; 3654 3655 power-domains = <&gcc USB30_SEC_GDSC>; 3656 3657 resets = <&gcc GCC_USB30_SEC_BCR>; 3658 3659 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, 3660 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; 3661 interconnect-names = "usb-ddr", "apps-usb"; 3662 3663 usb_2_dwc3: usb@a800000 { 3664 compatible = "snps,dwc3"; 3665 reg = <0 0x0a800000 0 0xcd00>; 3666 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3667 iommus = <&apps_smmu 0x160 0>; 3668 snps,dis_u2_susphy_quirk; 3669 snps,dis_enblslpm_quirk; 3670 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>; 3671 phy-names = "usb2-phy", "usb3-phy"; 3672 }; 3673 }; 3674 3675 camnoc_virt: interconnect@ac00000 { 3676 compatible = "qcom,sm8150-camnoc-virt"; 3677 reg = <0 0x0ac00000 0 0x1000>; 3678 #interconnect-cells = <2>; 3679 qcom,bcm-voters = <&apps_bcm_voter>; 3680 }; 3681 3682 mdss: display-subsystem@ae00000 { 3683 compatible = "qcom,sm8150-mdss"; 3684 reg = <0 0x0ae00000 0 0x1000>; 3685 reg-names = "mdss"; 3686 3687 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>, 3688 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>; 3689 interconnect-names = "mdp0-mem", "mdp1-mem"; 3690 3691 power-domains = <&dispcc MDSS_GDSC>; 3692 3693 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3694 <&gcc GCC_DISP_HF_AXI_CLK>, 3695 <&gcc GCC_DISP_SF_AXI_CLK>, 3696 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3697 clock-names = "iface", "bus", "nrt_bus", "core"; 3698 3699 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3700 interrupt-controller; 3701 #interrupt-cells = <1>; 3702 3703 iommus = <&apps_smmu 0x800 0x420>; 3704 3705 status = "disabled"; 3706 3707 #address-cells = <2>; 3708 #size-cells = <2>; 3709 ranges; 3710 3711 mdss_mdp: display-controller@ae01000 { 3712 compatible = "qcom,sm8150-dpu"; 3713 reg = <0 0x0ae01000 0 0x8f000>, 3714 <0 0x0aeb0000 0 0x2008>; 3715 reg-names = "mdp", "vbif"; 3716 3717 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3718 <&gcc GCC_DISP_HF_AXI_CLK>, 3719 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3720 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3721 clock-names = "iface", "bus", "core", "vsync"; 3722 3723 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3724 assigned-clock-rates = <19200000>; 3725 3726 operating-points-v2 = <&mdp_opp_table>; 3727 power-domains = <&rpmhpd SM8150_MMCX>; 3728 3729 interrupt-parent = <&mdss>; 3730 interrupts = <0>; 3731 3732 ports { 3733 #address-cells = <1>; 3734 #size-cells = <0>; 3735 3736 port@0 { 3737 reg = <0>; 3738 dpu_intf1_out: endpoint { 3739 remote-endpoint = <&mdss_dsi0_in>; 3740 }; 3741 }; 3742 3743 port@1 { 3744 reg = <1>; 3745 dpu_intf2_out: endpoint { 3746 remote-endpoint = <&mdss_dsi1_in>; 3747 }; 3748 }; 3749 3750 port@2 { 3751 reg = <2>; 3752 dpu_intf0_out: endpoint { 3753 remote-endpoint = <&mdss_dp_in>; 3754 }; 3755 }; 3756 }; 3757 3758 mdp_opp_table: opp-table { 3759 compatible = "operating-points-v2"; 3760 3761 opp-171428571 { 3762 opp-hz = /bits/ 64 <171428571>; 3763 required-opps = <&rpmhpd_opp_low_svs>; 3764 }; 3765 3766 opp-300000000 { 3767 opp-hz = /bits/ 64 <300000000>; 3768 required-opps = <&rpmhpd_opp_svs>; 3769 }; 3770 3771 opp-345000000 { 3772 opp-hz = /bits/ 64 <345000000>; 3773 required-opps = <&rpmhpd_opp_svs_l1>; 3774 }; 3775 3776 opp-460000000 { 3777 opp-hz = /bits/ 64 <460000000>; 3778 required-opps = <&rpmhpd_opp_nom>; 3779 }; 3780 }; 3781 }; 3782 3783 mdss_dp: displayport-controller@ae90000 { 3784 compatible = "qcom,sm8150-dp", "qcom,sm8350-dp"; 3785 reg = <0 0xae90000 0 0x200>, 3786 <0 0xae90200 0 0x200>, 3787 <0 0xae90400 0 0x600>, 3788 <0 0x0ae90a00 0 0x600>, 3789 <0 0x0ae91000 0 0x600>; 3790 3791 interrupt-parent = <&mdss>; 3792 interrupts = <12>; 3793 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3794 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3795 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3796 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3797 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3798 clock-names = "core_iface", 3799 "core_aux", 3800 "ctrl_link", 3801 "ctrl_link_iface", 3802 "stream_pixel"; 3803 3804 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3805 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3806 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3807 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3808 3809 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 3810 phy-names = "dp"; 3811 3812 #sound-dai-cells = <0>; 3813 3814 operating-points-v2 = <&dp_opp_table>; 3815 power-domains = <&rpmhpd SM8250_MMCX>; 3816 3817 status = "disabled"; 3818 3819 ports { 3820 #address-cells = <1>; 3821 #size-cells = <0>; 3822 3823 port@0 { 3824 reg = <0>; 3825 mdss_dp_in: endpoint { 3826 remote-endpoint = <&dpu_intf0_out>; 3827 }; 3828 }; 3829 3830 port@1 { 3831 reg = <1>; 3832 3833 mdss_dp_out: endpoint { 3834 }; 3835 }; 3836 }; 3837 3838 dp_opp_table: opp-table { 3839 compatible = "operating-points-v2"; 3840 3841 opp-160000000 { 3842 opp-hz = /bits/ 64 <160000000>; 3843 required-opps = <&rpmhpd_opp_low_svs>; 3844 }; 3845 3846 opp-270000000 { 3847 opp-hz = /bits/ 64 <270000000>; 3848 required-opps = <&rpmhpd_opp_svs>; 3849 }; 3850 3851 opp-540000000 { 3852 opp-hz = /bits/ 64 <540000000>; 3853 required-opps = <&rpmhpd_opp_svs_l1>; 3854 }; 3855 3856 opp-810000000 { 3857 opp-hz = /bits/ 64 <810000000>; 3858 required-opps = <&rpmhpd_opp_nom>; 3859 }; 3860 }; 3861 }; 3862 3863 mdss_dsi0: dsi@ae94000 { 3864 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3865 reg = <0 0x0ae94000 0 0x400>; 3866 reg-names = "dsi_ctrl"; 3867 3868 interrupt-parent = <&mdss>; 3869 interrupts = <4>; 3870 3871 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3872 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3873 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3874 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3875 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3876 <&gcc GCC_DISP_HF_AXI_CLK>; 3877 clock-names = "byte", 3878 "byte_intf", 3879 "pixel", 3880 "core", 3881 "iface", 3882 "bus"; 3883 3884 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 3885 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3886 assigned-clock-parents = <&mdss_dsi0_phy 0>, 3887 <&mdss_dsi0_phy 1>; 3888 3889 operating-points-v2 = <&dsi_opp_table>; 3890 power-domains = <&rpmhpd SM8150_MMCX>; 3891 3892 phys = <&mdss_dsi0_phy>; 3893 3894 status = "disabled"; 3895 3896 #address-cells = <1>; 3897 #size-cells = <0>; 3898 3899 ports { 3900 #address-cells = <1>; 3901 #size-cells = <0>; 3902 3903 port@0 { 3904 reg = <0>; 3905 mdss_dsi0_in: endpoint { 3906 remote-endpoint = <&dpu_intf1_out>; 3907 }; 3908 }; 3909 3910 port@1 { 3911 reg = <1>; 3912 mdss_dsi0_out: endpoint { 3913 }; 3914 }; 3915 }; 3916 3917 dsi_opp_table: opp-table { 3918 compatible = "operating-points-v2"; 3919 3920 opp-187500000 { 3921 opp-hz = /bits/ 64 <187500000>; 3922 required-opps = <&rpmhpd_opp_low_svs>; 3923 }; 3924 3925 opp-300000000 { 3926 opp-hz = /bits/ 64 <300000000>; 3927 required-opps = <&rpmhpd_opp_svs>; 3928 }; 3929 3930 opp-358000000 { 3931 opp-hz = /bits/ 64 <358000000>; 3932 required-opps = <&rpmhpd_opp_svs_l1>; 3933 }; 3934 }; 3935 }; 3936 3937 mdss_dsi0_phy: phy@ae94400 { 3938 compatible = "qcom,dsi-phy-7nm-8150"; 3939 reg = <0 0x0ae94400 0 0x200>, 3940 <0 0x0ae94600 0 0x280>, 3941 <0 0x0ae94900 0 0x260>; 3942 reg-names = "dsi_phy", 3943 "dsi_phy_lane", 3944 "dsi_pll"; 3945 3946 #clock-cells = <1>; 3947 #phy-cells = <0>; 3948 3949 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3950 <&rpmhcc RPMH_CXO_CLK>; 3951 clock-names = "iface", "ref"; 3952 3953 status = "disabled"; 3954 }; 3955 3956 mdss_dsi1: dsi@ae96000 { 3957 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3958 reg = <0 0x0ae96000 0 0x400>; 3959 reg-names = "dsi_ctrl"; 3960 3961 interrupt-parent = <&mdss>; 3962 interrupts = <5>; 3963 3964 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3965 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3966 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3967 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3968 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3969 <&gcc GCC_DISP_HF_AXI_CLK>; 3970 clock-names = "byte", 3971 "byte_intf", 3972 "pixel", 3973 "core", 3974 "iface", 3975 "bus"; 3976 3977 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 3978 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3979 assigned-clock-parents = <&mdss_dsi1_phy 0>, 3980 <&mdss_dsi1_phy 1>; 3981 3982 operating-points-v2 = <&dsi_opp_table>; 3983 power-domains = <&rpmhpd SM8150_MMCX>; 3984 3985 phys = <&mdss_dsi1_phy>; 3986 3987 status = "disabled"; 3988 3989 #address-cells = <1>; 3990 #size-cells = <0>; 3991 3992 ports { 3993 #address-cells = <1>; 3994 #size-cells = <0>; 3995 3996 port@0 { 3997 reg = <0>; 3998 mdss_dsi1_in: endpoint { 3999 remote-endpoint = <&dpu_intf2_out>; 4000 }; 4001 }; 4002 4003 port@1 { 4004 reg = <1>; 4005 mdss_dsi1_out: endpoint { 4006 }; 4007 }; 4008 }; 4009 }; 4010 4011 mdss_dsi1_phy: phy@ae96400 { 4012 compatible = "qcom,dsi-phy-7nm-8150"; 4013 reg = <0 0x0ae96400 0 0x200>, 4014 <0 0x0ae96600 0 0x280>, 4015 <0 0x0ae96900 0 0x260>; 4016 reg-names = "dsi_phy", 4017 "dsi_phy_lane", 4018 "dsi_pll"; 4019 4020 #clock-cells = <1>; 4021 #phy-cells = <0>; 4022 4023 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4024 <&rpmhcc RPMH_CXO_CLK>; 4025 clock-names = "iface", "ref"; 4026 4027 status = "disabled"; 4028 }; 4029 }; 4030 4031 dispcc: clock-controller@af00000 { 4032 compatible = "qcom,sm8150-dispcc"; 4033 reg = <0 0x0af00000 0 0x10000>; 4034 clocks = <&rpmhcc RPMH_CXO_CLK>, 4035 <&mdss_dsi0_phy 0>, 4036 <&mdss_dsi0_phy 1>, 4037 <&mdss_dsi1_phy 0>, 4038 <&mdss_dsi1_phy 1>, 4039 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4040 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4041 clock-names = "bi_tcxo", 4042 "dsi0_phy_pll_out_byteclk", 4043 "dsi0_phy_pll_out_dsiclk", 4044 "dsi1_phy_pll_out_byteclk", 4045 "dsi1_phy_pll_out_dsiclk", 4046 "dp_phy_pll_link_clk", 4047 "dp_phy_pll_vco_div_clk"; 4048 power-domains = <&rpmhpd SM8150_MMCX>; 4049 required-opps = <&rpmhpd_opp_low_svs>; 4050 #clock-cells = <1>; 4051 #reset-cells = <1>; 4052 #power-domain-cells = <1>; 4053 }; 4054 4055 pdc: interrupt-controller@b220000 { 4056 compatible = "qcom,sm8150-pdc", "qcom,pdc"; 4057 reg = <0 0x0b220000 0 0x30000>; 4058 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 4059 <125 63 1>; 4060 #interrupt-cells = <2>; 4061 interrupt-parent = <&intc>; 4062 interrupt-controller; 4063 }; 4064 4065 aoss_qmp: power-management@c300000 { 4066 compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp"; 4067 reg = <0x0 0x0c300000 0x0 0x400>; 4068 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 4069 mboxes = <&apss_shared 0>; 4070 4071 #clock-cells = <0>; 4072 }; 4073 4074 sram@c3f0000 { 4075 compatible = "qcom,rpmh-stats"; 4076 reg = <0 0x0c3f0000 0 0x400>; 4077 }; 4078 4079 tsens0: thermal-sensor@c263000 { 4080 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 4081 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4082 <0 0x0c222000 0 0x1ff>; /* SROT */ 4083 #qcom,sensors = <16>; 4084 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4085 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4086 interrupt-names = "uplow", "critical"; 4087 #thermal-sensor-cells = <1>; 4088 }; 4089 4090 tsens1: thermal-sensor@c265000 { 4091 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 4092 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4093 <0 0x0c223000 0 0x1ff>; /* SROT */ 4094 #qcom,sensors = <8>; 4095 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4096 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4097 interrupt-names = "uplow", "critical"; 4098 #thermal-sensor-cells = <1>; 4099 }; 4100 4101 spmi_bus: spmi@c440000 { 4102 compatible = "qcom,spmi-pmic-arb"; 4103 reg = <0x0 0x0c440000 0x0 0x0001100>, 4104 <0x0 0x0c600000 0x0 0x2000000>, 4105 <0x0 0x0e600000 0x0 0x0100000>, 4106 <0x0 0x0e700000 0x0 0x00a0000>, 4107 <0x0 0x0c40a000 0x0 0x0026000>; 4108 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4109 interrupt-names = "periph_irq"; 4110 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 4111 qcom,ee = <0>; 4112 qcom,channel = <0>; 4113 #address-cells = <2>; 4114 #size-cells = <0>; 4115 interrupt-controller; 4116 #interrupt-cells = <4>; 4117 }; 4118 4119 apps_smmu: iommu@15000000 { 4120 compatible = "qcom,sm8150-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 4121 reg = <0 0x15000000 0 0x100000>; 4122 #iommu-cells = <2>; 4123 #global-interrupts = <1>; 4124 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4125 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4126 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4127 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4128 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4129 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4130 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4131 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4132 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4133 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4134 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4135 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4136 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4137 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4138 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4139 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4140 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4141 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4142 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4143 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4144 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4145 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4146 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4147 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4148 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4149 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4150 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4151 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4152 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4153 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4154 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4155 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4156 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4157 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4158 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4159 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4160 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4161 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4162 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4163 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4164 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4165 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4166 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4167 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4168 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4169 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4170 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4171 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4172 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4173 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4174 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4175 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4176 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4177 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4178 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4179 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4180 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4181 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4182 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4183 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4184 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4185 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4186 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4187 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4188 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4189 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4190 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4191 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4192 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4193 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4194 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4195 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4196 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4197 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4198 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4199 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4200 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4201 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4202 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4203 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4204 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 4205 }; 4206 4207 remoteproc_adsp: remoteproc@17300000 { 4208 compatible = "qcom,sm8150-adsp-pas"; 4209 reg = <0x0 0x17300000 0x0 0x4040>; 4210 4211 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 4212 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4213 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 4214 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 4215 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 4216 interrupt-names = "wdog", "fatal", "ready", 4217 "handover", "stop-ack"; 4218 4219 clocks = <&rpmhcc RPMH_CXO_CLK>; 4220 clock-names = "xo"; 4221 4222 power-domains = <&rpmhpd SM8150_CX>; 4223 4224 memory-region = <&adsp_mem>; 4225 4226 qcom,qmp = <&aoss_qmp>; 4227 4228 qcom,smem-states = <&adsp_smp2p_out 0>; 4229 qcom,smem-state-names = "stop"; 4230 4231 status = "disabled"; 4232 4233 glink-edge { 4234 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 4235 label = "lpass"; 4236 qcom,remote-pid = <2>; 4237 mboxes = <&apss_shared 8>; 4238 4239 fastrpc { 4240 compatible = "qcom,fastrpc"; 4241 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4242 label = "adsp"; 4243 qcom,non-secure-domain; 4244 #address-cells = <1>; 4245 #size-cells = <0>; 4246 4247 compute-cb@3 { 4248 compatible = "qcom,fastrpc-compute-cb"; 4249 reg = <3>; 4250 iommus = <&apps_smmu 0x1b23 0x0>; 4251 }; 4252 4253 compute-cb@4 { 4254 compatible = "qcom,fastrpc-compute-cb"; 4255 reg = <4>; 4256 iommus = <&apps_smmu 0x1b24 0x0>; 4257 }; 4258 4259 compute-cb@5 { 4260 compatible = "qcom,fastrpc-compute-cb"; 4261 reg = <5>; 4262 iommus = <&apps_smmu 0x1b25 0x0>; 4263 }; 4264 }; 4265 }; 4266 }; 4267 4268 intc: interrupt-controller@17a00000 { 4269 compatible = "arm,gic-v3"; 4270 interrupt-controller; 4271 #interrupt-cells = <3>; 4272 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4273 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4274 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4275 }; 4276 4277 apss_shared: mailbox@17c00000 { 4278 compatible = "qcom,sm8150-apss-shared", 4279 "qcom,sdm845-apss-shared"; 4280 reg = <0x0 0x17c00000 0x0 0x1000>; 4281 #mbox-cells = <1>; 4282 }; 4283 4284 watchdog@17c10000 { 4285 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; 4286 reg = <0 0x17c10000 0 0x1000>; 4287 clocks = <&sleep_clk>; 4288 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 4289 }; 4290 4291 timer@17c20000 { 4292 #address-cells = <1>; 4293 #size-cells = <1>; 4294 ranges = <0 0 0 0x20000000>; 4295 compatible = "arm,armv7-timer-mem"; 4296 reg = <0x0 0x17c20000 0x0 0x1000>; 4297 clock-frequency = <19200000>; 4298 4299 frame@17c21000 { 4300 frame-number = <0>; 4301 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4302 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4303 reg = <0x17c21000 0x1000>, 4304 <0x17c22000 0x1000>; 4305 }; 4306 4307 frame@17c23000 { 4308 frame-number = <1>; 4309 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4310 reg = <0x17c23000 0x1000>; 4311 status = "disabled"; 4312 }; 4313 4314 frame@17c25000 { 4315 frame-number = <2>; 4316 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4317 reg = <0x17c25000 0x1000>; 4318 status = "disabled"; 4319 }; 4320 4321 frame@17c27000 { 4322 frame-number = <3>; 4323 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4324 reg = <0x17c26000 0x1000>; 4325 status = "disabled"; 4326 }; 4327 4328 frame@17c29000 { 4329 frame-number = <4>; 4330 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4331 reg = <0x17c29000 0x1000>; 4332 status = "disabled"; 4333 }; 4334 4335 frame@17c2b000 { 4336 frame-number = <5>; 4337 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4338 reg = <0x17c2b000 0x1000>; 4339 status = "disabled"; 4340 }; 4341 4342 frame@17c2d000 { 4343 frame-number = <6>; 4344 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4345 reg = <0x17c2d000 0x1000>; 4346 status = "disabled"; 4347 }; 4348 }; 4349 4350 apps_rsc: rsc@18200000 { 4351 label = "apps_rsc"; 4352 compatible = "qcom,rpmh-rsc"; 4353 reg = <0x0 0x18200000 0x0 0x10000>, 4354 <0x0 0x18210000 0x0 0x10000>, 4355 <0x0 0x18220000 0x0 0x10000>; 4356 reg-names = "drv-0", "drv-1", "drv-2"; 4357 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4358 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4359 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4360 qcom,tcs-offset = <0xd00>; 4361 qcom,drv-id = <2>; 4362 qcom,tcs-config = <ACTIVE_TCS 2>, 4363 <SLEEP_TCS 3>, 4364 <WAKE_TCS 3>, 4365 <CONTROL_TCS 1>; 4366 power-domains = <&CLUSTER_PD>; 4367 4368 rpmhcc: clock-controller { 4369 compatible = "qcom,sm8150-rpmh-clk"; 4370 #clock-cells = <1>; 4371 clock-names = "xo"; 4372 clocks = <&xo_board>; 4373 }; 4374 4375 rpmhpd: power-controller { 4376 compatible = "qcom,sm8150-rpmhpd"; 4377 #power-domain-cells = <1>; 4378 operating-points-v2 = <&rpmhpd_opp_table>; 4379 4380 rpmhpd_opp_table: opp-table { 4381 compatible = "operating-points-v2"; 4382 4383 rpmhpd_opp_ret: opp1 { 4384 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4385 }; 4386 4387 rpmhpd_opp_min_svs: opp2 { 4388 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4389 }; 4390 4391 rpmhpd_opp_low_svs: opp3 { 4392 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4393 }; 4394 4395 rpmhpd_opp_svs: opp4 { 4396 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4397 }; 4398 4399 rpmhpd_opp_svs_l1: opp5 { 4400 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4401 }; 4402 4403 rpmhpd_opp_svs_l2: opp6 { 4404 opp-level = <224>; 4405 }; 4406 4407 rpmhpd_opp_nom: opp7 { 4408 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4409 }; 4410 4411 rpmhpd_opp_nom_l1: opp8 { 4412 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4413 }; 4414 4415 rpmhpd_opp_nom_l2: opp9 { 4416 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4417 }; 4418 4419 rpmhpd_opp_turbo: opp10 { 4420 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4421 }; 4422 4423 rpmhpd_opp_turbo_l1: opp11 { 4424 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4425 }; 4426 }; 4427 }; 4428 4429 apps_bcm_voter: bcm-voter { 4430 compatible = "qcom,bcm-voter"; 4431 }; 4432 }; 4433 4434 osm_l3: interconnect@18321000 { 4435 compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3"; 4436 reg = <0 0x18321000 0 0x1400>; 4437 4438 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4439 clock-names = "xo", "alternate"; 4440 4441 #interconnect-cells = <1>; 4442 }; 4443 4444 cpufreq_hw: cpufreq@18323000 { 4445 compatible = "qcom,sm8150-cpufreq-hw", "qcom,cpufreq-hw"; 4446 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, 4447 <0 0x18327800 0 0x1400>; 4448 reg-names = "freq-domain0", "freq-domain1", 4449 "freq-domain2"; 4450 4451 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4452 clock-names = "xo", "alternate"; 4453 4454 #freq-domain-cells = <1>; 4455 #clock-cells = <1>; 4456 }; 4457 4458 lmh_cluster1: lmh@18350800 { 4459 compatible = "qcom,sm8150-lmh"; 4460 reg = <0 0x18350800 0 0x400>; 4461 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 4462 cpus = <&CPU4>; 4463 qcom,lmh-temp-arm-millicelsius = <60000>; 4464 qcom,lmh-temp-low-millicelsius = <84500>; 4465 qcom,lmh-temp-high-millicelsius = <85000>; 4466 interrupt-controller; 4467 #interrupt-cells = <1>; 4468 }; 4469 4470 lmh_cluster0: lmh@18358800 { 4471 compatible = "qcom,sm8150-lmh"; 4472 reg = <0 0x18358800 0 0x400>; 4473 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 4474 cpus = <&CPU0>; 4475 qcom,lmh-temp-arm-millicelsius = <60000>; 4476 qcom,lmh-temp-low-millicelsius = <84500>; 4477 qcom,lmh-temp-high-millicelsius = <85000>; 4478 interrupt-controller; 4479 #interrupt-cells = <1>; 4480 }; 4481 4482 wifi: wifi@18800000 { 4483 compatible = "qcom,wcn3990-wifi"; 4484 reg = <0 0x18800000 0 0x800000>; 4485 reg-names = "membase"; 4486 memory-region = <&wlan_mem>; 4487 clock-names = "cxo_ref_clk_pin", "qdss"; 4488 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; 4489 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 4490 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 4491 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 4492 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 4493 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4494 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4495 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 4496 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4497 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4498 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4499 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4500 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 4501 iommus = <&apps_smmu 0x0640 0x1>; 4502 status = "disabled"; 4503 }; 4504 }; 4505 4506 timer { 4507 compatible = "arm,armv8-timer"; 4508 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4509 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4510 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4511 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4512 }; 4513 4514 thermal-zones { 4515 cpu0-thermal { 4516 polling-delay-passive = <250>; 4517 polling-delay = <1000>; 4518 4519 thermal-sensors = <&tsens0 1>; 4520 4521 trips { 4522 cpu0_alert0: trip-point0 { 4523 temperature = <90000>; 4524 hysteresis = <2000>; 4525 type = "passive"; 4526 }; 4527 4528 cpu0_alert1: trip-point1 { 4529 temperature = <95000>; 4530 hysteresis = <2000>; 4531 type = "passive"; 4532 }; 4533 4534 cpu0_crit: cpu-crit { 4535 temperature = <110000>; 4536 hysteresis = <1000>; 4537 type = "critical"; 4538 }; 4539 }; 4540 4541 cooling-maps { 4542 map0 { 4543 trip = <&cpu0_alert0>; 4544 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4545 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4546 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4547 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4548 }; 4549 map1 { 4550 trip = <&cpu0_alert1>; 4551 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4552 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4553 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4554 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4555 }; 4556 }; 4557 }; 4558 4559 cpu1-thermal { 4560 polling-delay-passive = <250>; 4561 polling-delay = <1000>; 4562 4563 thermal-sensors = <&tsens0 2>; 4564 4565 trips { 4566 cpu1_alert0: trip-point0 { 4567 temperature = <90000>; 4568 hysteresis = <2000>; 4569 type = "passive"; 4570 }; 4571 4572 cpu1_alert1: trip-point1 { 4573 temperature = <95000>; 4574 hysteresis = <2000>; 4575 type = "passive"; 4576 }; 4577 4578 cpu1_crit: cpu-crit { 4579 temperature = <110000>; 4580 hysteresis = <1000>; 4581 type = "critical"; 4582 }; 4583 }; 4584 4585 cooling-maps { 4586 map0 { 4587 trip = <&cpu1_alert0>; 4588 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4589 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4590 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4591 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4592 }; 4593 map1 { 4594 trip = <&cpu1_alert1>; 4595 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4596 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4597 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4598 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4599 }; 4600 }; 4601 }; 4602 4603 cpu2-thermal { 4604 polling-delay-passive = <250>; 4605 polling-delay = <1000>; 4606 4607 thermal-sensors = <&tsens0 3>; 4608 4609 trips { 4610 cpu2_alert0: trip-point0 { 4611 temperature = <90000>; 4612 hysteresis = <2000>; 4613 type = "passive"; 4614 }; 4615 4616 cpu2_alert1: trip-point1 { 4617 temperature = <95000>; 4618 hysteresis = <2000>; 4619 type = "passive"; 4620 }; 4621 4622 cpu2_crit: cpu-crit { 4623 temperature = <110000>; 4624 hysteresis = <1000>; 4625 type = "critical"; 4626 }; 4627 }; 4628 4629 cooling-maps { 4630 map0 { 4631 trip = <&cpu2_alert0>; 4632 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4633 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4634 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4635 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4636 }; 4637 map1 { 4638 trip = <&cpu2_alert1>; 4639 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4640 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4641 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4642 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4643 }; 4644 }; 4645 }; 4646 4647 cpu3-thermal { 4648 polling-delay-passive = <250>; 4649 polling-delay = <1000>; 4650 4651 thermal-sensors = <&tsens0 4>; 4652 4653 trips { 4654 cpu3_alert0: trip-point0 { 4655 temperature = <90000>; 4656 hysteresis = <2000>; 4657 type = "passive"; 4658 }; 4659 4660 cpu3_alert1: trip-point1 { 4661 temperature = <95000>; 4662 hysteresis = <2000>; 4663 type = "passive"; 4664 }; 4665 4666 cpu3_crit: cpu-crit { 4667 temperature = <110000>; 4668 hysteresis = <1000>; 4669 type = "critical"; 4670 }; 4671 }; 4672 4673 cooling-maps { 4674 map0 { 4675 trip = <&cpu3_alert0>; 4676 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4677 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4678 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4679 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4680 }; 4681 map1 { 4682 trip = <&cpu3_alert1>; 4683 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4684 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4685 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4686 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4687 }; 4688 }; 4689 }; 4690 4691 cpu4-top-thermal { 4692 polling-delay-passive = <250>; 4693 polling-delay = <1000>; 4694 4695 thermal-sensors = <&tsens0 7>; 4696 4697 trips { 4698 cpu4_top_alert0: trip-point0 { 4699 temperature = <90000>; 4700 hysteresis = <2000>; 4701 type = "passive"; 4702 }; 4703 4704 cpu4_top_alert1: trip-point1 { 4705 temperature = <95000>; 4706 hysteresis = <2000>; 4707 type = "passive"; 4708 }; 4709 4710 cpu4_top_crit: cpu-crit { 4711 temperature = <110000>; 4712 hysteresis = <1000>; 4713 type = "critical"; 4714 }; 4715 }; 4716 4717 cooling-maps { 4718 map0 { 4719 trip = <&cpu4_top_alert0>; 4720 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4721 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4722 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4723 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4724 }; 4725 map1 { 4726 trip = <&cpu4_top_alert1>; 4727 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4728 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4729 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4730 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4731 }; 4732 }; 4733 }; 4734 4735 cpu5-top-thermal { 4736 polling-delay-passive = <250>; 4737 polling-delay = <1000>; 4738 4739 thermal-sensors = <&tsens0 8>; 4740 4741 trips { 4742 cpu5_top_alert0: trip-point0 { 4743 temperature = <90000>; 4744 hysteresis = <2000>; 4745 type = "passive"; 4746 }; 4747 4748 cpu5_top_alert1: trip-point1 { 4749 temperature = <95000>; 4750 hysteresis = <2000>; 4751 type = "passive"; 4752 }; 4753 4754 cpu5_top_crit: cpu-crit { 4755 temperature = <110000>; 4756 hysteresis = <1000>; 4757 type = "critical"; 4758 }; 4759 }; 4760 4761 cooling-maps { 4762 map0 { 4763 trip = <&cpu5_top_alert0>; 4764 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4765 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4766 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4767 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4768 }; 4769 map1 { 4770 trip = <&cpu5_top_alert1>; 4771 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4772 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4773 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4774 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4775 }; 4776 }; 4777 }; 4778 4779 cpu6-top-thermal { 4780 polling-delay-passive = <250>; 4781 polling-delay = <1000>; 4782 4783 thermal-sensors = <&tsens0 9>; 4784 4785 trips { 4786 cpu6_top_alert0: trip-point0 { 4787 temperature = <90000>; 4788 hysteresis = <2000>; 4789 type = "passive"; 4790 }; 4791 4792 cpu6_top_alert1: trip-point1 { 4793 temperature = <95000>; 4794 hysteresis = <2000>; 4795 type = "passive"; 4796 }; 4797 4798 cpu6_top_crit: cpu-crit { 4799 temperature = <110000>; 4800 hysteresis = <1000>; 4801 type = "critical"; 4802 }; 4803 }; 4804 4805 cooling-maps { 4806 map0 { 4807 trip = <&cpu6_top_alert0>; 4808 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4809 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4810 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4811 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4812 }; 4813 map1 { 4814 trip = <&cpu6_top_alert1>; 4815 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4816 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4817 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4818 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4819 }; 4820 }; 4821 }; 4822 4823 cpu7-top-thermal { 4824 polling-delay-passive = <250>; 4825 polling-delay = <1000>; 4826 4827 thermal-sensors = <&tsens0 10>; 4828 4829 trips { 4830 cpu7_top_alert0: trip-point0 { 4831 temperature = <90000>; 4832 hysteresis = <2000>; 4833 type = "passive"; 4834 }; 4835 4836 cpu7_top_alert1: trip-point1 { 4837 temperature = <95000>; 4838 hysteresis = <2000>; 4839 type = "passive"; 4840 }; 4841 4842 cpu7_top_crit: cpu-crit { 4843 temperature = <110000>; 4844 hysteresis = <1000>; 4845 type = "critical"; 4846 }; 4847 }; 4848 4849 cooling-maps { 4850 map0 { 4851 trip = <&cpu7_top_alert0>; 4852 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4853 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4854 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4855 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4856 }; 4857 map1 { 4858 trip = <&cpu7_top_alert1>; 4859 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4860 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4861 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4862 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4863 }; 4864 }; 4865 }; 4866 4867 cpu4-bottom-thermal { 4868 polling-delay-passive = <250>; 4869 polling-delay = <1000>; 4870 4871 thermal-sensors = <&tsens0 11>; 4872 4873 trips { 4874 cpu4_bottom_alert0: trip-point0 { 4875 temperature = <90000>; 4876 hysteresis = <2000>; 4877 type = "passive"; 4878 }; 4879 4880 cpu4_bottom_alert1: trip-point1 { 4881 temperature = <95000>; 4882 hysteresis = <2000>; 4883 type = "passive"; 4884 }; 4885 4886 cpu4_bottom_crit: cpu-crit { 4887 temperature = <110000>; 4888 hysteresis = <1000>; 4889 type = "critical"; 4890 }; 4891 }; 4892 4893 cooling-maps { 4894 map0 { 4895 trip = <&cpu4_bottom_alert0>; 4896 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4897 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4898 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4899 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4900 }; 4901 map1 { 4902 trip = <&cpu4_bottom_alert1>; 4903 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4904 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4905 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4906 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4907 }; 4908 }; 4909 }; 4910 4911 cpu5-bottom-thermal { 4912 polling-delay-passive = <250>; 4913 polling-delay = <1000>; 4914 4915 thermal-sensors = <&tsens0 12>; 4916 4917 trips { 4918 cpu5_bottom_alert0: trip-point0 { 4919 temperature = <90000>; 4920 hysteresis = <2000>; 4921 type = "passive"; 4922 }; 4923 4924 cpu5_bottom_alert1: trip-point1 { 4925 temperature = <95000>; 4926 hysteresis = <2000>; 4927 type = "passive"; 4928 }; 4929 4930 cpu5_bottom_crit: cpu-crit { 4931 temperature = <110000>; 4932 hysteresis = <1000>; 4933 type = "critical"; 4934 }; 4935 }; 4936 4937 cooling-maps { 4938 map0 { 4939 trip = <&cpu5_bottom_alert0>; 4940 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4941 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4942 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4943 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4944 }; 4945 map1 { 4946 trip = <&cpu5_bottom_alert1>; 4947 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4948 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4949 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4950 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4951 }; 4952 }; 4953 }; 4954 4955 cpu6-bottom-thermal { 4956 polling-delay-passive = <250>; 4957 polling-delay = <1000>; 4958 4959 thermal-sensors = <&tsens0 13>; 4960 4961 trips { 4962 cpu6_bottom_alert0: trip-point0 { 4963 temperature = <90000>; 4964 hysteresis = <2000>; 4965 type = "passive"; 4966 }; 4967 4968 cpu6_bottom_alert1: trip-point1 { 4969 temperature = <95000>; 4970 hysteresis = <2000>; 4971 type = "passive"; 4972 }; 4973 4974 cpu6_bottom_crit: cpu-crit { 4975 temperature = <110000>; 4976 hysteresis = <1000>; 4977 type = "critical"; 4978 }; 4979 }; 4980 4981 cooling-maps { 4982 map0 { 4983 trip = <&cpu6_bottom_alert0>; 4984 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4985 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4986 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4987 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4988 }; 4989 map1 { 4990 trip = <&cpu6_bottom_alert1>; 4991 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4992 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4993 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4994 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4995 }; 4996 }; 4997 }; 4998 4999 cpu7-bottom-thermal { 5000 polling-delay-passive = <250>; 5001 polling-delay = <1000>; 5002 5003 thermal-sensors = <&tsens0 14>; 5004 5005 trips { 5006 cpu7_bottom_alert0: trip-point0 { 5007 temperature = <90000>; 5008 hysteresis = <2000>; 5009 type = "passive"; 5010 }; 5011 5012 cpu7_bottom_alert1: trip-point1 { 5013 temperature = <95000>; 5014 hysteresis = <2000>; 5015 type = "passive"; 5016 }; 5017 5018 cpu7_bottom_crit: cpu-crit { 5019 temperature = <110000>; 5020 hysteresis = <1000>; 5021 type = "critical"; 5022 }; 5023 }; 5024 5025 cooling-maps { 5026 map0 { 5027 trip = <&cpu7_bottom_alert0>; 5028 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5029 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5030 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5031 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5032 }; 5033 map1 { 5034 trip = <&cpu7_bottom_alert1>; 5035 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5036 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5037 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5038 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5039 }; 5040 }; 5041 }; 5042 5043 aoss0-thermal { 5044 polling-delay-passive = <250>; 5045 polling-delay = <1000>; 5046 5047 thermal-sensors = <&tsens0 0>; 5048 5049 trips { 5050 aoss0_alert0: trip-point0 { 5051 temperature = <90000>; 5052 hysteresis = <2000>; 5053 type = "hot"; 5054 }; 5055 }; 5056 }; 5057 5058 cluster0-thermal { 5059 polling-delay-passive = <250>; 5060 polling-delay = <1000>; 5061 5062 thermal-sensors = <&tsens0 5>; 5063 5064 trips { 5065 cluster0_alert0: trip-point0 { 5066 temperature = <90000>; 5067 hysteresis = <2000>; 5068 type = "hot"; 5069 }; 5070 cluster0_crit: cluster0_crit { 5071 temperature = <110000>; 5072 hysteresis = <2000>; 5073 type = "critical"; 5074 }; 5075 }; 5076 }; 5077 5078 cluster1-thermal { 5079 polling-delay-passive = <250>; 5080 polling-delay = <1000>; 5081 5082 thermal-sensors = <&tsens0 6>; 5083 5084 trips { 5085 cluster1_alert0: trip-point0 { 5086 temperature = <90000>; 5087 hysteresis = <2000>; 5088 type = "hot"; 5089 }; 5090 cluster1_crit: cluster1_crit { 5091 temperature = <110000>; 5092 hysteresis = <2000>; 5093 type = "critical"; 5094 }; 5095 }; 5096 }; 5097 5098 gpu-top-thermal { 5099 polling-delay-passive = <250>; 5100 polling-delay = <1000>; 5101 5102 thermal-sensors = <&tsens0 15>; 5103 5104 trips { 5105 gpu1_alert0: trip-point0 { 5106 temperature = <90000>; 5107 hysteresis = <2000>; 5108 type = "hot"; 5109 }; 5110 }; 5111 }; 5112 5113 aoss1-thermal { 5114 polling-delay-passive = <250>; 5115 polling-delay = <1000>; 5116 5117 thermal-sensors = <&tsens1 0>; 5118 5119 trips { 5120 aoss1_alert0: trip-point0 { 5121 temperature = <90000>; 5122 hysteresis = <2000>; 5123 type = "hot"; 5124 }; 5125 }; 5126 }; 5127 5128 wlan-thermal { 5129 polling-delay-passive = <250>; 5130 polling-delay = <1000>; 5131 5132 thermal-sensors = <&tsens1 1>; 5133 5134 trips { 5135 wlan_alert0: trip-point0 { 5136 temperature = <90000>; 5137 hysteresis = <2000>; 5138 type = "hot"; 5139 }; 5140 }; 5141 }; 5142 5143 video-thermal { 5144 polling-delay-passive = <250>; 5145 polling-delay = <1000>; 5146 5147 thermal-sensors = <&tsens1 2>; 5148 5149 trips { 5150 video_alert0: trip-point0 { 5151 temperature = <90000>; 5152 hysteresis = <2000>; 5153 type = "hot"; 5154 }; 5155 }; 5156 }; 5157 5158 mem-thermal { 5159 polling-delay-passive = <250>; 5160 polling-delay = <1000>; 5161 5162 thermal-sensors = <&tsens1 3>; 5163 5164 trips { 5165 mem_alert0: trip-point0 { 5166 temperature = <90000>; 5167 hysteresis = <2000>; 5168 type = "hot"; 5169 }; 5170 }; 5171 }; 5172 5173 q6-hvx-thermal { 5174 polling-delay-passive = <250>; 5175 polling-delay = <1000>; 5176 5177 thermal-sensors = <&tsens1 4>; 5178 5179 trips { 5180 q6_hvx_alert0: trip-point0 { 5181 temperature = <90000>; 5182 hysteresis = <2000>; 5183 type = "hot"; 5184 }; 5185 }; 5186 }; 5187 5188 camera-thermal { 5189 polling-delay-passive = <250>; 5190 polling-delay = <1000>; 5191 5192 thermal-sensors = <&tsens1 5>; 5193 5194 trips { 5195 camera_alert0: trip-point0 { 5196 temperature = <90000>; 5197 hysteresis = <2000>; 5198 type = "hot"; 5199 }; 5200 }; 5201 }; 5202 5203 compute-thermal { 5204 polling-delay-passive = <250>; 5205 polling-delay = <1000>; 5206 5207 thermal-sensors = <&tsens1 6>; 5208 5209 trips { 5210 compute_alert0: trip-point0 { 5211 temperature = <90000>; 5212 hysteresis = <2000>; 5213 type = "hot"; 5214 }; 5215 }; 5216 }; 5217 5218 modem-thermal { 5219 polling-delay-passive = <250>; 5220 polling-delay = <1000>; 5221 5222 thermal-sensors = <&tsens1 7>; 5223 5224 trips { 5225 modem_alert0: trip-point0 { 5226 temperature = <90000>; 5227 hysteresis = <2000>; 5228 type = "hot"; 5229 }; 5230 }; 5231 }; 5232 5233 npu-thermal { 5234 polling-delay-passive = <250>; 5235 polling-delay = <1000>; 5236 5237 thermal-sensors = <&tsens1 8>; 5238 5239 trips { 5240 npu_alert0: trip-point0 { 5241 temperature = <90000>; 5242 hysteresis = <2000>; 5243 type = "hot"; 5244 }; 5245 }; 5246 }; 5247 5248 modem-vec-thermal { 5249 polling-delay-passive = <250>; 5250 polling-delay = <1000>; 5251 5252 thermal-sensors = <&tsens1 9>; 5253 5254 trips { 5255 modem_vec_alert0: trip-point0 { 5256 temperature = <90000>; 5257 hysteresis = <2000>; 5258 type = "hot"; 5259 }; 5260 }; 5261 }; 5262 5263 modem-scl-thermal { 5264 polling-delay-passive = <250>; 5265 polling-delay = <1000>; 5266 5267 thermal-sensors = <&tsens1 10>; 5268 5269 trips { 5270 modem_scl_alert0: trip-point0 { 5271 temperature = <90000>; 5272 hysteresis = <2000>; 5273 type = "hot"; 5274 }; 5275 }; 5276 }; 5277 5278 gpu-bottom-thermal { 5279 polling-delay-passive = <250>; 5280 polling-delay = <1000>; 5281 5282 thermal-sensors = <&tsens1 11>; 5283 5284 trips { 5285 gpu2_alert0: trip-point0 { 5286 temperature = <90000>; 5287 hysteresis = <2000>; 5288 type = "hot"; 5289 }; 5290 }; 5291 }; 5292 }; 5293}; 5294