1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2019, Linaro Limited 5 */ 6 7#include <dt-bindings/dma/qcom-gpi.h> 8#include <dt-bindings/firmware/qcom,scm.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/phy/phy-qcom-qmp.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/soc/qcom,rpmh-rsc.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,dispcc-sm8150.h> 15#include <dt-bindings/clock/qcom,gcc-sm8150.h> 16#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sm8150.h> 19#include <dt-bindings/thermal/thermal.h> 20 21/ { 22 interrupt-parent = <&intc>; 23 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 chosen { }; 28 29 clocks { 30 xo_board: xo-board { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <38400000>; 34 clock-output-names = "xo_board"; 35 }; 36 37 sleep_clk: sleep-clk { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <32764>; 41 clock-output-names = "sleep_clk"; 42 }; 43 }; 44 45 cpus { 46 #address-cells = <2>; 47 #size-cells = <0>; 48 49 CPU0: cpu@0 { 50 device_type = "cpu"; 51 compatible = "qcom,kryo485"; 52 reg = <0x0 0x0>; 53 clocks = <&cpufreq_hw 0>; 54 enable-method = "psci"; 55 capacity-dmips-mhz = <488>; 56 dynamic-power-coefficient = <232>; 57 next-level-cache = <&L2_0>; 58 qcom,freq-domain = <&cpufreq_hw 0>; 59 operating-points-v2 = <&cpu0_opp_table>; 60 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 61 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 62 power-domains = <&CPU_PD0>; 63 power-domain-names = "psci"; 64 #cooling-cells = <2>; 65 L2_0: l2-cache { 66 compatible = "cache"; 67 cache-level = <2>; 68 cache-unified; 69 next-level-cache = <&L3_0>; 70 L3_0: l3-cache { 71 compatible = "cache"; 72 cache-level = <3>; 73 cache-unified; 74 }; 75 }; 76 }; 77 78 CPU1: cpu@100 { 79 device_type = "cpu"; 80 compatible = "qcom,kryo485"; 81 reg = <0x0 0x100>; 82 clocks = <&cpufreq_hw 0>; 83 enable-method = "psci"; 84 capacity-dmips-mhz = <488>; 85 dynamic-power-coefficient = <232>; 86 next-level-cache = <&L2_100>; 87 qcom,freq-domain = <&cpufreq_hw 0>; 88 operating-points-v2 = <&cpu0_opp_table>; 89 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 90 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 91 power-domains = <&CPU_PD1>; 92 power-domain-names = "psci"; 93 #cooling-cells = <2>; 94 L2_100: l2-cache { 95 compatible = "cache"; 96 cache-level = <2>; 97 cache-unified; 98 next-level-cache = <&L3_0>; 99 }; 100 }; 101 102 CPU2: cpu@200 { 103 device_type = "cpu"; 104 compatible = "qcom,kryo485"; 105 reg = <0x0 0x200>; 106 clocks = <&cpufreq_hw 0>; 107 enable-method = "psci"; 108 capacity-dmips-mhz = <488>; 109 dynamic-power-coefficient = <232>; 110 next-level-cache = <&L2_200>; 111 qcom,freq-domain = <&cpufreq_hw 0>; 112 operating-points-v2 = <&cpu0_opp_table>; 113 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 114 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 115 power-domains = <&CPU_PD2>; 116 power-domain-names = "psci"; 117 #cooling-cells = <2>; 118 L2_200: l2-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 cache-unified; 122 next-level-cache = <&L3_0>; 123 }; 124 }; 125 126 CPU3: cpu@300 { 127 device_type = "cpu"; 128 compatible = "qcom,kryo485"; 129 reg = <0x0 0x300>; 130 clocks = <&cpufreq_hw 0>; 131 enable-method = "psci"; 132 capacity-dmips-mhz = <488>; 133 dynamic-power-coefficient = <232>; 134 next-level-cache = <&L2_300>; 135 qcom,freq-domain = <&cpufreq_hw 0>; 136 operating-points-v2 = <&cpu0_opp_table>; 137 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 138 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 139 power-domains = <&CPU_PD3>; 140 power-domain-names = "psci"; 141 #cooling-cells = <2>; 142 L2_300: l2-cache { 143 compatible = "cache"; 144 cache-level = <2>; 145 cache-unified; 146 next-level-cache = <&L3_0>; 147 }; 148 }; 149 150 CPU4: cpu@400 { 151 device_type = "cpu"; 152 compatible = "qcom,kryo485"; 153 reg = <0x0 0x400>; 154 clocks = <&cpufreq_hw 1>; 155 enable-method = "psci"; 156 capacity-dmips-mhz = <1024>; 157 dynamic-power-coefficient = <369>; 158 next-level-cache = <&L2_400>; 159 qcom,freq-domain = <&cpufreq_hw 1>; 160 operating-points-v2 = <&cpu4_opp_table>; 161 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 162 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 163 power-domains = <&CPU_PD4>; 164 power-domain-names = "psci"; 165 #cooling-cells = <2>; 166 L2_400: l2-cache { 167 compatible = "cache"; 168 cache-level = <2>; 169 cache-unified; 170 next-level-cache = <&L3_0>; 171 }; 172 }; 173 174 CPU5: cpu@500 { 175 device_type = "cpu"; 176 compatible = "qcom,kryo485"; 177 reg = <0x0 0x500>; 178 clocks = <&cpufreq_hw 1>; 179 enable-method = "psci"; 180 capacity-dmips-mhz = <1024>; 181 dynamic-power-coefficient = <369>; 182 next-level-cache = <&L2_500>; 183 qcom,freq-domain = <&cpufreq_hw 1>; 184 operating-points-v2 = <&cpu4_opp_table>; 185 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 186 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 187 power-domains = <&CPU_PD5>; 188 power-domain-names = "psci"; 189 #cooling-cells = <2>; 190 L2_500: l2-cache { 191 compatible = "cache"; 192 cache-level = <2>; 193 cache-unified; 194 next-level-cache = <&L3_0>; 195 }; 196 }; 197 198 CPU6: cpu@600 { 199 device_type = "cpu"; 200 compatible = "qcom,kryo485"; 201 reg = <0x0 0x600>; 202 clocks = <&cpufreq_hw 1>; 203 enable-method = "psci"; 204 capacity-dmips-mhz = <1024>; 205 dynamic-power-coefficient = <369>; 206 next-level-cache = <&L2_600>; 207 qcom,freq-domain = <&cpufreq_hw 1>; 208 operating-points-v2 = <&cpu4_opp_table>; 209 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 210 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 211 power-domains = <&CPU_PD6>; 212 power-domain-names = "psci"; 213 #cooling-cells = <2>; 214 L2_600: l2-cache { 215 compatible = "cache"; 216 cache-level = <2>; 217 cache-unified; 218 next-level-cache = <&L3_0>; 219 }; 220 }; 221 222 CPU7: cpu@700 { 223 device_type = "cpu"; 224 compatible = "qcom,kryo485"; 225 reg = <0x0 0x700>; 226 clocks = <&cpufreq_hw 2>; 227 enable-method = "psci"; 228 capacity-dmips-mhz = <1024>; 229 dynamic-power-coefficient = <421>; 230 next-level-cache = <&L2_700>; 231 qcom,freq-domain = <&cpufreq_hw 2>; 232 operating-points-v2 = <&cpu7_opp_table>; 233 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 234 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 235 power-domains = <&CPU_PD7>; 236 power-domain-names = "psci"; 237 #cooling-cells = <2>; 238 L2_700: l2-cache { 239 compatible = "cache"; 240 cache-level = <2>; 241 cache-unified; 242 next-level-cache = <&L3_0>; 243 }; 244 }; 245 246 cpu-map { 247 cluster0 { 248 core0 { 249 cpu = <&CPU0>; 250 }; 251 252 core1 { 253 cpu = <&CPU1>; 254 }; 255 256 core2 { 257 cpu = <&CPU2>; 258 }; 259 260 core3 { 261 cpu = <&CPU3>; 262 }; 263 264 core4 { 265 cpu = <&CPU4>; 266 }; 267 268 core5 { 269 cpu = <&CPU5>; 270 }; 271 272 core6 { 273 cpu = <&CPU6>; 274 }; 275 276 core7 { 277 cpu = <&CPU7>; 278 }; 279 }; 280 }; 281 282 idle-states { 283 entry-method = "psci"; 284 285 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 286 compatible = "arm,idle-state"; 287 idle-state-name = "little-rail-power-collapse"; 288 arm,psci-suspend-param = <0x40000004>; 289 entry-latency-us = <355>; 290 exit-latency-us = <909>; 291 min-residency-us = <3934>; 292 local-timer-stop; 293 }; 294 295 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 296 compatible = "arm,idle-state"; 297 idle-state-name = "big-rail-power-collapse"; 298 arm,psci-suspend-param = <0x40000004>; 299 entry-latency-us = <241>; 300 exit-latency-us = <1461>; 301 min-residency-us = <4488>; 302 local-timer-stop; 303 }; 304 }; 305 306 domain-idle-states { 307 CLUSTER_SLEEP_0: cluster-sleep-0 { 308 compatible = "domain-idle-state"; 309 arm,psci-suspend-param = <0x4100c244>; 310 entry-latency-us = <3263>; 311 exit-latency-us = <6562>; 312 min-residency-us = <9987>; 313 }; 314 }; 315 }; 316 317 cpu0_opp_table: opp-table-cpu0 { 318 compatible = "operating-points-v2"; 319 opp-shared; 320 321 cpu0_opp1: opp-300000000 { 322 opp-hz = /bits/ 64 <300000000>; 323 opp-peak-kBps = <800000 9600000>; 324 }; 325 326 cpu0_opp2: opp-403200000 { 327 opp-hz = /bits/ 64 <403200000>; 328 opp-peak-kBps = <800000 9600000>; 329 }; 330 331 cpu0_opp3: opp-499200000 { 332 opp-hz = /bits/ 64 <499200000>; 333 opp-peak-kBps = <800000 12902400>; 334 }; 335 336 cpu0_opp4: opp-576000000 { 337 opp-hz = /bits/ 64 <576000000>; 338 opp-peak-kBps = <800000 12902400>; 339 }; 340 341 cpu0_opp5: opp-672000000 { 342 opp-hz = /bits/ 64 <672000000>; 343 opp-peak-kBps = <800000 15974400>; 344 }; 345 346 cpu0_opp6: opp-768000000 { 347 opp-hz = /bits/ 64 <768000000>; 348 opp-peak-kBps = <1804000 19660800>; 349 }; 350 351 cpu0_opp7: opp-844800000 { 352 opp-hz = /bits/ 64 <844800000>; 353 opp-peak-kBps = <1804000 19660800>; 354 }; 355 356 cpu0_opp8: opp-940800000 { 357 opp-hz = /bits/ 64 <940800000>; 358 opp-peak-kBps = <1804000 22732800>; 359 }; 360 361 cpu0_opp9: opp-1036800000 { 362 opp-hz = /bits/ 64 <1036800000>; 363 opp-peak-kBps = <1804000 22732800>; 364 }; 365 366 cpu0_opp10: opp-1113600000 { 367 opp-hz = /bits/ 64 <1113600000>; 368 opp-peak-kBps = <2188000 25804800>; 369 }; 370 371 cpu0_opp11: opp-1209600000 { 372 opp-hz = /bits/ 64 <1209600000>; 373 opp-peak-kBps = <2188000 31948800>; 374 }; 375 376 cpu0_opp12: opp-1305600000 { 377 opp-hz = /bits/ 64 <1305600000>; 378 opp-peak-kBps = <3072000 31948800>; 379 }; 380 381 cpu0_opp13: opp-1382400000 { 382 opp-hz = /bits/ 64 <1382400000>; 383 opp-peak-kBps = <3072000 31948800>; 384 }; 385 386 cpu0_opp14: opp-1478400000 { 387 opp-hz = /bits/ 64 <1478400000>; 388 opp-peak-kBps = <3072000 31948800>; 389 }; 390 391 cpu0_opp15: opp-1555200000 { 392 opp-hz = /bits/ 64 <1555200000>; 393 opp-peak-kBps = <3072000 40550400>; 394 }; 395 396 cpu0_opp16: opp-1632000000 { 397 opp-hz = /bits/ 64 <1632000000>; 398 opp-peak-kBps = <3072000 40550400>; 399 }; 400 401 cpu0_opp17: opp-1708800000 { 402 opp-hz = /bits/ 64 <1708800000>; 403 opp-peak-kBps = <3072000 43008000>; 404 }; 405 406 cpu0_opp18: opp-1785600000 { 407 opp-hz = /bits/ 64 <1785600000>; 408 opp-peak-kBps = <3072000 43008000>; 409 }; 410 }; 411 412 cpu4_opp_table: opp-table-cpu4 { 413 compatible = "operating-points-v2"; 414 opp-shared; 415 416 cpu4_opp1: opp-710400000 { 417 opp-hz = /bits/ 64 <710400000>; 418 opp-peak-kBps = <1804000 15974400>; 419 }; 420 421 cpu4_opp2: opp-825600000 { 422 opp-hz = /bits/ 64 <825600000>; 423 opp-peak-kBps = <2188000 19660800>; 424 }; 425 426 cpu4_opp3: opp-940800000 { 427 opp-hz = /bits/ 64 <940800000>; 428 opp-peak-kBps = <2188000 22732800>; 429 }; 430 431 cpu4_opp4: opp-1056000000 { 432 opp-hz = /bits/ 64 <1056000000>; 433 opp-peak-kBps = <3072000 25804800>; 434 }; 435 436 cpu4_opp5: opp-1171200000 { 437 opp-hz = /bits/ 64 <1171200000>; 438 opp-peak-kBps = <3072000 31948800>; 439 }; 440 441 cpu4_opp6: opp-1286400000 { 442 opp-hz = /bits/ 64 <1286400000>; 443 opp-peak-kBps = <4068000 31948800>; 444 }; 445 446 cpu4_opp7: opp-1401600000 { 447 opp-hz = /bits/ 64 <1401600000>; 448 opp-peak-kBps = <4068000 31948800>; 449 }; 450 451 cpu4_opp8: opp-1497600000 { 452 opp-hz = /bits/ 64 <1497600000>; 453 opp-peak-kBps = <4068000 40550400>; 454 }; 455 456 cpu4_opp9: opp-1612800000 { 457 opp-hz = /bits/ 64 <1612800000>; 458 opp-peak-kBps = <4068000 40550400>; 459 }; 460 461 cpu4_opp10: opp-1708800000 { 462 opp-hz = /bits/ 64 <1708800000>; 463 opp-peak-kBps = <4068000 43008000>; 464 }; 465 466 cpu4_opp11: opp-1804800000 { 467 opp-hz = /bits/ 64 <1804800000>; 468 opp-peak-kBps = <6220000 43008000>; 469 }; 470 471 cpu4_opp12: opp-1920000000 { 472 opp-hz = /bits/ 64 <1920000000>; 473 opp-peak-kBps = <6220000 49152000>; 474 }; 475 476 cpu4_opp13: opp-2016000000 { 477 opp-hz = /bits/ 64 <2016000000>; 478 opp-peak-kBps = <7216000 49152000>; 479 }; 480 481 cpu4_opp14: opp-2131200000 { 482 opp-hz = /bits/ 64 <2131200000>; 483 opp-peak-kBps = <8368000 49152000>; 484 }; 485 486 cpu4_opp15: opp-2227200000 { 487 opp-hz = /bits/ 64 <2227200000>; 488 opp-peak-kBps = <8368000 51609600>; 489 }; 490 491 cpu4_opp16: opp-2323200000 { 492 opp-hz = /bits/ 64 <2323200000>; 493 opp-peak-kBps = <8368000 51609600>; 494 }; 495 496 cpu4_opp17: opp-2419200000 { 497 opp-hz = /bits/ 64 <2419200000>; 498 opp-peak-kBps = <8368000 51609600>; 499 }; 500 }; 501 502 cpu7_opp_table: opp-table-cpu7 { 503 compatible = "operating-points-v2"; 504 opp-shared; 505 506 cpu7_opp1: opp-825600000 { 507 opp-hz = /bits/ 64 <825600000>; 508 opp-peak-kBps = <2188000 19660800>; 509 }; 510 511 cpu7_opp2: opp-940800000 { 512 opp-hz = /bits/ 64 <940800000>; 513 opp-peak-kBps = <2188000 22732800>; 514 }; 515 516 cpu7_opp3: opp-1056000000 { 517 opp-hz = /bits/ 64 <1056000000>; 518 opp-peak-kBps = <3072000 25804800>; 519 }; 520 521 cpu7_opp4: opp-1171200000 { 522 opp-hz = /bits/ 64 <1171200000>; 523 opp-peak-kBps = <3072000 31948800>; 524 }; 525 526 cpu7_opp5: opp-1286400000 { 527 opp-hz = /bits/ 64 <1286400000>; 528 opp-peak-kBps = <4068000 31948800>; 529 }; 530 531 cpu7_opp6: opp-1401600000 { 532 opp-hz = /bits/ 64 <1401600000>; 533 opp-peak-kBps = <4068000 31948800>; 534 }; 535 536 cpu7_opp7: opp-1497600000 { 537 opp-hz = /bits/ 64 <1497600000>; 538 opp-peak-kBps = <4068000 40550400>; 539 }; 540 541 cpu7_opp8: opp-1612800000 { 542 opp-hz = /bits/ 64 <1612800000>; 543 opp-peak-kBps = <4068000 40550400>; 544 }; 545 546 cpu7_opp9: opp-1708800000 { 547 opp-hz = /bits/ 64 <1708800000>; 548 opp-peak-kBps = <4068000 43008000>; 549 }; 550 551 cpu7_opp10: opp-1804800000 { 552 opp-hz = /bits/ 64 <1804800000>; 553 opp-peak-kBps = <6220000 43008000>; 554 }; 555 556 cpu7_opp11: opp-1920000000 { 557 opp-hz = /bits/ 64 <1920000000>; 558 opp-peak-kBps = <6220000 49152000>; 559 }; 560 561 cpu7_opp12: opp-2016000000 { 562 opp-hz = /bits/ 64 <2016000000>; 563 opp-peak-kBps = <7216000 49152000>; 564 }; 565 566 cpu7_opp13: opp-2131200000 { 567 opp-hz = /bits/ 64 <2131200000>; 568 opp-peak-kBps = <8368000 49152000>; 569 }; 570 571 cpu7_opp14: opp-2227200000 { 572 opp-hz = /bits/ 64 <2227200000>; 573 opp-peak-kBps = <8368000 51609600>; 574 }; 575 576 cpu7_opp15: opp-2323200000 { 577 opp-hz = /bits/ 64 <2323200000>; 578 opp-peak-kBps = <8368000 51609600>; 579 }; 580 581 cpu7_opp16: opp-2419200000 { 582 opp-hz = /bits/ 64 <2419200000>; 583 opp-peak-kBps = <8368000 51609600>; 584 }; 585 586 cpu7_opp17: opp-2534400000 { 587 opp-hz = /bits/ 64 <2534400000>; 588 opp-peak-kBps = <8368000 51609600>; 589 }; 590 591 cpu7_opp18: opp-2649600000 { 592 opp-hz = /bits/ 64 <2649600000>; 593 opp-peak-kBps = <8368000 51609600>; 594 }; 595 596 cpu7_opp19: opp-2745600000 { 597 opp-hz = /bits/ 64 <2745600000>; 598 opp-peak-kBps = <8368000 51609600>; 599 }; 600 601 cpu7_opp20: opp-2841600000 { 602 opp-hz = /bits/ 64 <2841600000>; 603 opp-peak-kBps = <8368000 51609600>; 604 }; 605 }; 606 607 firmware { 608 scm: scm { 609 compatible = "qcom,scm-sm8150", "qcom,scm"; 610 #reset-cells = <1>; 611 }; 612 }; 613 614 memory@80000000 { 615 device_type = "memory"; 616 /* We expect the bootloader to fill in the size */ 617 reg = <0x0 0x80000000 0x0 0x0>; 618 }; 619 620 pmu { 621 compatible = "arm,armv8-pmuv3"; 622 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 623 }; 624 625 psci { 626 compatible = "arm,psci-1.0"; 627 method = "smc"; 628 629 CPU_PD0: power-domain-cpu0 { 630 #power-domain-cells = <0>; 631 power-domains = <&CLUSTER_PD>; 632 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 633 }; 634 635 CPU_PD1: power-domain-cpu1 { 636 #power-domain-cells = <0>; 637 power-domains = <&CLUSTER_PD>; 638 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 639 }; 640 641 CPU_PD2: power-domain-cpu2 { 642 #power-domain-cells = <0>; 643 power-domains = <&CLUSTER_PD>; 644 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 645 }; 646 647 CPU_PD3: power-domain-cpu3 { 648 #power-domain-cells = <0>; 649 power-domains = <&CLUSTER_PD>; 650 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 651 }; 652 653 CPU_PD4: power-domain-cpu4 { 654 #power-domain-cells = <0>; 655 power-domains = <&CLUSTER_PD>; 656 domain-idle-states = <&BIG_CPU_SLEEP_0>; 657 }; 658 659 CPU_PD5: power-domain-cpu5 { 660 #power-domain-cells = <0>; 661 power-domains = <&CLUSTER_PD>; 662 domain-idle-states = <&BIG_CPU_SLEEP_0>; 663 }; 664 665 CPU_PD6: power-domain-cpu6 { 666 #power-domain-cells = <0>; 667 power-domains = <&CLUSTER_PD>; 668 domain-idle-states = <&BIG_CPU_SLEEP_0>; 669 }; 670 671 CPU_PD7: power-domain-cpu7 { 672 #power-domain-cells = <0>; 673 power-domains = <&CLUSTER_PD>; 674 domain-idle-states = <&BIG_CPU_SLEEP_0>; 675 }; 676 677 CLUSTER_PD: power-domain-cpu-cluster0 { 678 #power-domain-cells = <0>; 679 domain-idle-states = <&CLUSTER_SLEEP_0>; 680 }; 681 }; 682 683 reserved-memory { 684 #address-cells = <2>; 685 #size-cells = <2>; 686 ranges; 687 688 hyp_mem: memory@85700000 { 689 reg = <0x0 0x85700000 0x0 0x600000>; 690 no-map; 691 }; 692 693 xbl_mem: memory@85d00000 { 694 reg = <0x0 0x85d00000 0x0 0x140000>; 695 no-map; 696 }; 697 698 aop_mem: memory@85f00000 { 699 reg = <0x0 0x85f00000 0x0 0x20000>; 700 no-map; 701 }; 702 703 aop_cmd_db: memory@85f20000 { 704 compatible = "qcom,cmd-db"; 705 reg = <0x0 0x85f20000 0x0 0x20000>; 706 no-map; 707 }; 708 709 smem_mem: memory@86000000 { 710 reg = <0x0 0x86000000 0x0 0x200000>; 711 no-map; 712 }; 713 714 tz_mem: memory@86200000 { 715 reg = <0x0 0x86200000 0x0 0x3900000>; 716 no-map; 717 }; 718 719 rmtfs_mem: memory@89b00000 { 720 compatible = "qcom,rmtfs-mem"; 721 reg = <0x0 0x89b00000 0x0 0x200000>; 722 no-map; 723 724 qcom,client-id = <1>; 725 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 726 }; 727 728 camera_mem: memory@8b700000 { 729 reg = <0x0 0x8b700000 0x0 0x500000>; 730 no-map; 731 }; 732 733 wlan_mem: memory@8bc00000 { 734 reg = <0x0 0x8bc00000 0x0 0x180000>; 735 no-map; 736 }; 737 738 npu_mem: memory@8bd80000 { 739 reg = <0x0 0x8bd80000 0x0 0x80000>; 740 no-map; 741 }; 742 743 adsp_mem: memory@8be00000 { 744 reg = <0x0 0x8be00000 0x0 0x1a00000>; 745 no-map; 746 }; 747 748 mpss_mem: memory@8d800000 { 749 reg = <0x0 0x8d800000 0x0 0x9600000>; 750 no-map; 751 }; 752 753 venus_mem: memory@96e00000 { 754 reg = <0x0 0x96e00000 0x0 0x500000>; 755 no-map; 756 }; 757 758 slpi_mem: memory@97300000 { 759 reg = <0x0 0x97300000 0x0 0x1400000>; 760 no-map; 761 }; 762 763 ipa_fw_mem: memory@98700000 { 764 reg = <0x0 0x98700000 0x0 0x10000>; 765 no-map; 766 }; 767 768 ipa_gsi_mem: memory@98710000 { 769 reg = <0x0 0x98710000 0x0 0x5000>; 770 no-map; 771 }; 772 773 gpu_mem: memory@98715000 { 774 reg = <0x0 0x98715000 0x0 0x2000>; 775 no-map; 776 }; 777 778 spss_mem: memory@98800000 { 779 reg = <0x0 0x98800000 0x0 0x100000>; 780 no-map; 781 }; 782 783 cdsp_mem: memory@98900000 { 784 reg = <0x0 0x98900000 0x0 0x1400000>; 785 no-map; 786 }; 787 788 qseecom_mem: memory@9e400000 { 789 reg = <0x0 0x9e400000 0x0 0x1400000>; 790 no-map; 791 }; 792 }; 793 794 smem { 795 compatible = "qcom,smem"; 796 memory-region = <&smem_mem>; 797 hwlocks = <&tcsr_mutex 3>; 798 }; 799 800 smp2p-cdsp { 801 compatible = "qcom,smp2p"; 802 qcom,smem = <94>, <432>; 803 804 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 805 806 mboxes = <&apss_shared 6>; 807 808 qcom,local-pid = <0>; 809 qcom,remote-pid = <5>; 810 811 cdsp_smp2p_out: master-kernel { 812 qcom,entry-name = "master-kernel"; 813 #qcom,smem-state-cells = <1>; 814 }; 815 816 cdsp_smp2p_in: slave-kernel { 817 qcom,entry-name = "slave-kernel"; 818 819 interrupt-controller; 820 #interrupt-cells = <2>; 821 }; 822 }; 823 824 smp2p-lpass { 825 compatible = "qcom,smp2p"; 826 qcom,smem = <443>, <429>; 827 828 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 829 830 mboxes = <&apss_shared 10>; 831 832 qcom,local-pid = <0>; 833 qcom,remote-pid = <2>; 834 835 adsp_smp2p_out: master-kernel { 836 qcom,entry-name = "master-kernel"; 837 #qcom,smem-state-cells = <1>; 838 }; 839 840 adsp_smp2p_in: slave-kernel { 841 qcom,entry-name = "slave-kernel"; 842 843 interrupt-controller; 844 #interrupt-cells = <2>; 845 }; 846 }; 847 848 smp2p-mpss { 849 compatible = "qcom,smp2p"; 850 qcom,smem = <435>, <428>; 851 852 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 853 854 mboxes = <&apss_shared 14>; 855 856 qcom,local-pid = <0>; 857 qcom,remote-pid = <1>; 858 859 modem_smp2p_out: master-kernel { 860 qcom,entry-name = "master-kernel"; 861 #qcom,smem-state-cells = <1>; 862 }; 863 864 modem_smp2p_in: slave-kernel { 865 qcom,entry-name = "slave-kernel"; 866 867 interrupt-controller; 868 #interrupt-cells = <2>; 869 }; 870 }; 871 872 smp2p-slpi { 873 compatible = "qcom,smp2p"; 874 qcom,smem = <481>, <430>; 875 876 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 877 878 mboxes = <&apss_shared 26>; 879 880 qcom,local-pid = <0>; 881 qcom,remote-pid = <3>; 882 883 slpi_smp2p_out: master-kernel { 884 qcom,entry-name = "master-kernel"; 885 #qcom,smem-state-cells = <1>; 886 }; 887 888 slpi_smp2p_in: slave-kernel { 889 qcom,entry-name = "slave-kernel"; 890 891 interrupt-controller; 892 #interrupt-cells = <2>; 893 }; 894 }; 895 896 soc: soc@0 { 897 #address-cells = <2>; 898 #size-cells = <2>; 899 ranges = <0 0 0 0 0x10 0>; 900 dma-ranges = <0 0 0 0 0x10 0>; 901 compatible = "simple-bus"; 902 903 gcc: clock-controller@100000 { 904 compatible = "qcom,gcc-sm8150"; 905 reg = <0x0 0x00100000 0x0 0x1f0000>; 906 #clock-cells = <1>; 907 #reset-cells = <1>; 908 #power-domain-cells = <1>; 909 clock-names = "bi_tcxo", 910 "sleep_clk"; 911 clocks = <&rpmhcc RPMH_CXO_CLK>, 912 <&sleep_clk>; 913 }; 914 915 gpi_dma0: dma-controller@800000 { 916 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 917 reg = <0 0x00800000 0 0x60000>; 918 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 919 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 920 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 921 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 922 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 923 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 931 dma-channels = <13>; 932 dma-channel-mask = <0xfa>; 933 iommus = <&apps_smmu 0x00d6 0x0>; 934 #dma-cells = <3>; 935 status = "disabled"; 936 }; 937 938 ethernet: ethernet@20000 { 939 compatible = "qcom,sm8150-ethqos"; 940 reg = <0x0 0x00020000 0x0 0x10000>, 941 <0x0 0x00036000 0x0 0x100>; 942 reg-names = "stmmaceth", "rgmii"; 943 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; 944 clocks = <&gcc GCC_EMAC_AXI_CLK>, 945 <&gcc GCC_EMAC_SLV_AHB_CLK>, 946 <&gcc GCC_EMAC_PTP_CLK>, 947 <&gcc GCC_EMAC_RGMII_CLK>; 948 interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; 950 interrupt-names = "macirq", "eth_lpi"; 951 952 power-domains = <&gcc EMAC_GDSC>; 953 resets = <&gcc GCC_EMAC_BCR>; 954 955 iommus = <&apps_smmu 0x3c0 0x0>; 956 957 snps,tso; 958 rx-fifo-depth = <4096>; 959 tx-fifo-depth = <4096>; 960 961 status = "disabled"; 962 }; 963 964 qfprom: efuse@784000 { 965 compatible = "qcom,sm8150-qfprom", "qcom,qfprom"; 966 reg = <0 0x00784000 0 0x8ff>; 967 #address-cells = <1>; 968 #size-cells = <1>; 969 970 gpu_speed_bin: gpu-speed-bin@133 { 971 reg = <0x133 0x1>; 972 bits = <5 3>; 973 }; 974 }; 975 976 qupv3_id_0: geniqup@8c0000 { 977 compatible = "qcom,geni-se-qup"; 978 reg = <0x0 0x008c0000 0x0 0x6000>; 979 clock-names = "m-ahb", "s-ahb"; 980 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 981 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 982 iommus = <&apps_smmu 0xc3 0x0>; 983 #address-cells = <2>; 984 #size-cells = <2>; 985 ranges; 986 status = "disabled"; 987 988 i2c0: i2c@880000 { 989 compatible = "qcom,geni-i2c"; 990 reg = <0 0x00880000 0 0x4000>; 991 clock-names = "se"; 992 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 993 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 994 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 995 dma-names = "tx", "rx"; 996 pinctrl-names = "default"; 997 pinctrl-0 = <&qup_i2c0_default>; 998 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 999 #address-cells = <1>; 1000 #size-cells = <0>; 1001 status = "disabled"; 1002 }; 1003 1004 spi0: spi@880000 { 1005 compatible = "qcom,geni-spi"; 1006 reg = <0 0x00880000 0 0x4000>; 1007 reg-names = "se"; 1008 clock-names = "se"; 1009 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1010 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1011 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1012 dma-names = "tx", "rx"; 1013 pinctrl-names = "default"; 1014 pinctrl-0 = <&qup_spi0_default>; 1015 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1016 spi-max-frequency = <50000000>; 1017 #address-cells = <1>; 1018 #size-cells = <0>; 1019 status = "disabled"; 1020 }; 1021 1022 i2c1: i2c@884000 { 1023 compatible = "qcom,geni-i2c"; 1024 reg = <0 0x00884000 0 0x4000>; 1025 clock-names = "se"; 1026 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1027 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1028 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1029 dma-names = "tx", "rx"; 1030 pinctrl-names = "default"; 1031 pinctrl-0 = <&qup_i2c1_default>; 1032 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1033 #address-cells = <1>; 1034 #size-cells = <0>; 1035 status = "disabled"; 1036 }; 1037 1038 spi1: spi@884000 { 1039 compatible = "qcom,geni-spi"; 1040 reg = <0 0x00884000 0 0x4000>; 1041 reg-names = "se"; 1042 clock-names = "se"; 1043 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1044 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1045 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1046 dma-names = "tx", "rx"; 1047 pinctrl-names = "default"; 1048 pinctrl-0 = <&qup_spi1_default>; 1049 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1050 spi-max-frequency = <50000000>; 1051 #address-cells = <1>; 1052 #size-cells = <0>; 1053 status = "disabled"; 1054 }; 1055 1056 i2c2: i2c@888000 { 1057 compatible = "qcom,geni-i2c"; 1058 reg = <0 0x00888000 0 0x4000>; 1059 clock-names = "se"; 1060 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1061 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1062 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1063 dma-names = "tx", "rx"; 1064 pinctrl-names = "default"; 1065 pinctrl-0 = <&qup_i2c2_default>; 1066 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1067 #address-cells = <1>; 1068 #size-cells = <0>; 1069 status = "disabled"; 1070 }; 1071 1072 spi2: spi@888000 { 1073 compatible = "qcom,geni-spi"; 1074 reg = <0 0x00888000 0 0x4000>; 1075 reg-names = "se"; 1076 clock-names = "se"; 1077 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1078 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1079 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1080 dma-names = "tx", "rx"; 1081 pinctrl-names = "default"; 1082 pinctrl-0 = <&qup_spi2_default>; 1083 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1084 spi-max-frequency = <50000000>; 1085 #address-cells = <1>; 1086 #size-cells = <0>; 1087 status = "disabled"; 1088 }; 1089 1090 i2c3: i2c@88c000 { 1091 compatible = "qcom,geni-i2c"; 1092 reg = <0 0x0088c000 0 0x4000>; 1093 clock-names = "se"; 1094 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1095 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1096 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1097 dma-names = "tx", "rx"; 1098 pinctrl-names = "default"; 1099 pinctrl-0 = <&qup_i2c3_default>; 1100 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1101 #address-cells = <1>; 1102 #size-cells = <0>; 1103 status = "disabled"; 1104 }; 1105 1106 spi3: spi@88c000 { 1107 compatible = "qcom,geni-spi"; 1108 reg = <0 0x0088c000 0 0x4000>; 1109 reg-names = "se"; 1110 clock-names = "se"; 1111 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1112 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1113 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1114 dma-names = "tx", "rx"; 1115 pinctrl-names = "default"; 1116 pinctrl-0 = <&qup_spi3_default>; 1117 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1118 spi-max-frequency = <50000000>; 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 status = "disabled"; 1122 }; 1123 1124 i2c4: i2c@890000 { 1125 compatible = "qcom,geni-i2c"; 1126 reg = <0 0x00890000 0 0x4000>; 1127 clock-names = "se"; 1128 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1129 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1130 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1131 dma-names = "tx", "rx"; 1132 pinctrl-names = "default"; 1133 pinctrl-0 = <&qup_i2c4_default>; 1134 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1135 #address-cells = <1>; 1136 #size-cells = <0>; 1137 status = "disabled"; 1138 }; 1139 1140 spi4: spi@890000 { 1141 compatible = "qcom,geni-spi"; 1142 reg = <0 0x00890000 0 0x4000>; 1143 reg-names = "se"; 1144 clock-names = "se"; 1145 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1146 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1147 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1148 dma-names = "tx", "rx"; 1149 pinctrl-names = "default"; 1150 pinctrl-0 = <&qup_spi4_default>; 1151 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1152 spi-max-frequency = <50000000>; 1153 #address-cells = <1>; 1154 #size-cells = <0>; 1155 status = "disabled"; 1156 }; 1157 1158 i2c5: i2c@894000 { 1159 compatible = "qcom,geni-i2c"; 1160 reg = <0 0x00894000 0 0x4000>; 1161 clock-names = "se"; 1162 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1163 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1164 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1165 dma-names = "tx", "rx"; 1166 pinctrl-names = "default"; 1167 pinctrl-0 = <&qup_i2c5_default>; 1168 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1169 #address-cells = <1>; 1170 #size-cells = <0>; 1171 status = "disabled"; 1172 }; 1173 1174 spi5: spi@894000 { 1175 compatible = "qcom,geni-spi"; 1176 reg = <0 0x00894000 0 0x4000>; 1177 reg-names = "se"; 1178 clock-names = "se"; 1179 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1180 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1181 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1182 dma-names = "tx", "rx"; 1183 pinctrl-names = "default"; 1184 pinctrl-0 = <&qup_spi5_default>; 1185 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1186 spi-max-frequency = <50000000>; 1187 #address-cells = <1>; 1188 #size-cells = <0>; 1189 status = "disabled"; 1190 }; 1191 1192 i2c6: i2c@898000 { 1193 compatible = "qcom,geni-i2c"; 1194 reg = <0 0x00898000 0 0x4000>; 1195 clock-names = "se"; 1196 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1197 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1198 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1199 dma-names = "tx", "rx"; 1200 pinctrl-names = "default"; 1201 pinctrl-0 = <&qup_i2c6_default>; 1202 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1203 #address-cells = <1>; 1204 #size-cells = <0>; 1205 status = "disabled"; 1206 }; 1207 1208 spi6: spi@898000 { 1209 compatible = "qcom,geni-spi"; 1210 reg = <0 0x00898000 0 0x4000>; 1211 reg-names = "se"; 1212 clock-names = "se"; 1213 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1214 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1215 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1216 dma-names = "tx", "rx"; 1217 pinctrl-names = "default"; 1218 pinctrl-0 = <&qup_spi6_default>; 1219 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1220 spi-max-frequency = <50000000>; 1221 #address-cells = <1>; 1222 #size-cells = <0>; 1223 status = "disabled"; 1224 }; 1225 1226 i2c7: i2c@89c000 { 1227 compatible = "qcom,geni-i2c"; 1228 reg = <0 0x0089c000 0 0x4000>; 1229 clock-names = "se"; 1230 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1231 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1232 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1233 dma-names = "tx", "rx"; 1234 pinctrl-names = "default"; 1235 pinctrl-0 = <&qup_i2c7_default>; 1236 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1237 #address-cells = <1>; 1238 #size-cells = <0>; 1239 status = "disabled"; 1240 }; 1241 1242 spi7: spi@89c000 { 1243 compatible = "qcom,geni-spi"; 1244 reg = <0 0x0089c000 0 0x4000>; 1245 reg-names = "se"; 1246 clock-names = "se"; 1247 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1248 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1249 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1250 dma-names = "tx", "rx"; 1251 pinctrl-names = "default"; 1252 pinctrl-0 = <&qup_spi7_default>; 1253 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1254 spi-max-frequency = <50000000>; 1255 #address-cells = <1>; 1256 #size-cells = <0>; 1257 status = "disabled"; 1258 }; 1259 }; 1260 1261 gpi_dma1: dma-controller@a00000 { 1262 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 1263 reg = <0 0x00a00000 0 0x60000>; 1264 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1265 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1266 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1267 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1275 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1276 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1277 dma-channels = <13>; 1278 dma-channel-mask = <0xfa>; 1279 iommus = <&apps_smmu 0x0616 0x0>; 1280 #dma-cells = <3>; 1281 status = "disabled"; 1282 }; 1283 1284 qupv3_id_1: geniqup@ac0000 { 1285 compatible = "qcom,geni-se-qup"; 1286 reg = <0x0 0x00ac0000 0x0 0x6000>; 1287 clock-names = "m-ahb", "s-ahb"; 1288 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1289 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1290 iommus = <&apps_smmu 0x603 0x0>; 1291 #address-cells = <2>; 1292 #size-cells = <2>; 1293 ranges; 1294 status = "disabled"; 1295 1296 i2c8: i2c@a80000 { 1297 compatible = "qcom,geni-i2c"; 1298 reg = <0 0x00a80000 0 0x4000>; 1299 clock-names = "se"; 1300 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1301 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1302 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1303 dma-names = "tx", "rx"; 1304 pinctrl-names = "default"; 1305 pinctrl-0 = <&qup_i2c8_default>; 1306 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1307 #address-cells = <1>; 1308 #size-cells = <0>; 1309 status = "disabled"; 1310 }; 1311 1312 spi8: spi@a80000 { 1313 compatible = "qcom,geni-spi"; 1314 reg = <0 0x00a80000 0 0x4000>; 1315 reg-names = "se"; 1316 clock-names = "se"; 1317 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1318 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1319 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1320 dma-names = "tx", "rx"; 1321 pinctrl-names = "default"; 1322 pinctrl-0 = <&qup_spi8_default>; 1323 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1324 spi-max-frequency = <50000000>; 1325 #address-cells = <1>; 1326 #size-cells = <0>; 1327 status = "disabled"; 1328 }; 1329 1330 i2c9: i2c@a84000 { 1331 compatible = "qcom,geni-i2c"; 1332 reg = <0 0x00a84000 0 0x4000>; 1333 clock-names = "se"; 1334 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1335 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1336 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1337 dma-names = "tx", "rx"; 1338 pinctrl-names = "default"; 1339 pinctrl-0 = <&qup_i2c9_default>; 1340 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1341 #address-cells = <1>; 1342 #size-cells = <0>; 1343 status = "disabled"; 1344 }; 1345 1346 spi9: spi@a84000 { 1347 compatible = "qcom,geni-spi"; 1348 reg = <0 0x00a84000 0 0x4000>; 1349 reg-names = "se"; 1350 clock-names = "se"; 1351 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1352 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1353 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1354 dma-names = "tx", "rx"; 1355 pinctrl-names = "default"; 1356 pinctrl-0 = <&qup_spi9_default>; 1357 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1358 spi-max-frequency = <50000000>; 1359 #address-cells = <1>; 1360 #size-cells = <0>; 1361 status = "disabled"; 1362 }; 1363 1364 uart9: serial@a84000 { 1365 compatible = "qcom,geni-uart"; 1366 reg = <0x0 0x00a84000 0x0 0x4000>; 1367 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1368 clock-names = "se"; 1369 pinctrl-0 = <&qup_uart9_default>; 1370 pinctrl-names = "default"; 1371 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1372 status = "disabled"; 1373 }; 1374 1375 i2c10: i2c@a88000 { 1376 compatible = "qcom,geni-i2c"; 1377 reg = <0 0x00a88000 0 0x4000>; 1378 clock-names = "se"; 1379 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1380 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1381 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1382 dma-names = "tx", "rx"; 1383 pinctrl-names = "default"; 1384 pinctrl-0 = <&qup_i2c10_default>; 1385 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1386 #address-cells = <1>; 1387 #size-cells = <0>; 1388 status = "disabled"; 1389 }; 1390 1391 spi10: spi@a88000 { 1392 compatible = "qcom,geni-spi"; 1393 reg = <0 0x00a88000 0 0x4000>; 1394 reg-names = "se"; 1395 clock-names = "se"; 1396 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1397 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1398 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1399 dma-names = "tx", "rx"; 1400 pinctrl-names = "default"; 1401 pinctrl-0 = <&qup_spi10_default>; 1402 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1403 spi-max-frequency = <50000000>; 1404 #address-cells = <1>; 1405 #size-cells = <0>; 1406 status = "disabled"; 1407 }; 1408 1409 i2c11: i2c@a8c000 { 1410 compatible = "qcom,geni-i2c"; 1411 reg = <0 0x00a8c000 0 0x4000>; 1412 clock-names = "se"; 1413 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1414 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1415 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1416 dma-names = "tx", "rx"; 1417 pinctrl-names = "default"; 1418 pinctrl-0 = <&qup_i2c11_default>; 1419 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1420 #address-cells = <1>; 1421 #size-cells = <0>; 1422 status = "disabled"; 1423 }; 1424 1425 spi11: spi@a8c000 { 1426 compatible = "qcom,geni-spi"; 1427 reg = <0 0x00a8c000 0 0x4000>; 1428 reg-names = "se"; 1429 clock-names = "se"; 1430 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1431 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1432 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1433 dma-names = "tx", "rx"; 1434 pinctrl-names = "default"; 1435 pinctrl-0 = <&qup_spi11_default>; 1436 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1437 spi-max-frequency = <50000000>; 1438 #address-cells = <1>; 1439 #size-cells = <0>; 1440 status = "disabled"; 1441 }; 1442 1443 uart2: serial@a90000 { 1444 compatible = "qcom,geni-debug-uart"; 1445 reg = <0x0 0x00a90000 0x0 0x4000>; 1446 clock-names = "se"; 1447 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1448 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1449 status = "disabled"; 1450 }; 1451 1452 i2c12: i2c@a90000 { 1453 compatible = "qcom,geni-i2c"; 1454 reg = <0 0x00a90000 0 0x4000>; 1455 clock-names = "se"; 1456 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1457 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1458 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1459 dma-names = "tx", "rx"; 1460 pinctrl-names = "default"; 1461 pinctrl-0 = <&qup_i2c12_default>; 1462 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1463 #address-cells = <1>; 1464 #size-cells = <0>; 1465 status = "disabled"; 1466 }; 1467 1468 spi12: spi@a90000 { 1469 compatible = "qcom,geni-spi"; 1470 reg = <0 0x00a90000 0 0x4000>; 1471 reg-names = "se"; 1472 clock-names = "se"; 1473 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1474 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1475 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1476 dma-names = "tx", "rx"; 1477 pinctrl-names = "default"; 1478 pinctrl-0 = <&qup_spi12_default>; 1479 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1480 spi-max-frequency = <50000000>; 1481 #address-cells = <1>; 1482 #size-cells = <0>; 1483 status = "disabled"; 1484 }; 1485 1486 i2c16: i2c@94000 { 1487 compatible = "qcom,geni-i2c"; 1488 reg = <0 0x00094000 0 0x4000>; 1489 clock-names = "se"; 1490 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1491 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1492 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1493 dma-names = "tx", "rx"; 1494 pinctrl-names = "default"; 1495 pinctrl-0 = <&qup_i2c16_default>; 1496 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1497 #address-cells = <1>; 1498 #size-cells = <0>; 1499 status = "disabled"; 1500 }; 1501 1502 spi16: spi@a94000 { 1503 compatible = "qcom,geni-spi"; 1504 reg = <0 0x00a94000 0 0x4000>; 1505 reg-names = "se"; 1506 clock-names = "se"; 1507 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1508 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1509 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1510 dma-names = "tx", "rx"; 1511 pinctrl-names = "default"; 1512 pinctrl-0 = <&qup_spi16_default>; 1513 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1514 spi-max-frequency = <50000000>; 1515 #address-cells = <1>; 1516 #size-cells = <0>; 1517 status = "disabled"; 1518 }; 1519 }; 1520 1521 gpi_dma2: dma-controller@c00000 { 1522 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 1523 reg = <0 0x00c00000 0 0x60000>; 1524 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; 1537 dma-channels = <13>; 1538 dma-channel-mask = <0xfa>; 1539 iommus = <&apps_smmu 0x07b6 0x0>; 1540 #dma-cells = <3>; 1541 status = "disabled"; 1542 }; 1543 1544 qupv3_id_2: geniqup@cc0000 { 1545 compatible = "qcom,geni-se-qup"; 1546 reg = <0x0 0x00cc0000 0x0 0x6000>; 1547 1548 clock-names = "m-ahb", "s-ahb"; 1549 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1550 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1551 iommus = <&apps_smmu 0x7a3 0x0>; 1552 #address-cells = <2>; 1553 #size-cells = <2>; 1554 ranges; 1555 status = "disabled"; 1556 1557 i2c17: i2c@c80000 { 1558 compatible = "qcom,geni-i2c"; 1559 reg = <0 0x00c80000 0 0x4000>; 1560 clock-names = "se"; 1561 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1562 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1563 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1564 dma-names = "tx", "rx"; 1565 pinctrl-names = "default"; 1566 pinctrl-0 = <&qup_i2c17_default>; 1567 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1568 #address-cells = <1>; 1569 #size-cells = <0>; 1570 status = "disabled"; 1571 }; 1572 1573 spi17: spi@c80000 { 1574 compatible = "qcom,geni-spi"; 1575 reg = <0 0x00c80000 0 0x4000>; 1576 reg-names = "se"; 1577 clock-names = "se"; 1578 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1579 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1580 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1581 dma-names = "tx", "rx"; 1582 pinctrl-names = "default"; 1583 pinctrl-0 = <&qup_spi17_default>; 1584 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1585 spi-max-frequency = <50000000>; 1586 #address-cells = <1>; 1587 #size-cells = <0>; 1588 status = "disabled"; 1589 }; 1590 1591 i2c18: i2c@c84000 { 1592 compatible = "qcom,geni-i2c"; 1593 reg = <0 0x00c84000 0 0x4000>; 1594 clock-names = "se"; 1595 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1596 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1597 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1598 dma-names = "tx", "rx"; 1599 pinctrl-names = "default"; 1600 pinctrl-0 = <&qup_i2c18_default>; 1601 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1602 #address-cells = <1>; 1603 #size-cells = <0>; 1604 status = "disabled"; 1605 }; 1606 1607 spi18: spi@c84000 { 1608 compatible = "qcom,geni-spi"; 1609 reg = <0 0x00c84000 0 0x4000>; 1610 reg-names = "se"; 1611 clock-names = "se"; 1612 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1613 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1614 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1615 dma-names = "tx", "rx"; 1616 pinctrl-names = "default"; 1617 pinctrl-0 = <&qup_spi18_default>; 1618 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1619 spi-max-frequency = <50000000>; 1620 #address-cells = <1>; 1621 #size-cells = <0>; 1622 status = "disabled"; 1623 }; 1624 1625 i2c19: i2c@c88000 { 1626 compatible = "qcom,geni-i2c"; 1627 reg = <0 0x00c88000 0 0x4000>; 1628 clock-names = "se"; 1629 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1630 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1631 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1632 dma-names = "tx", "rx"; 1633 pinctrl-names = "default"; 1634 pinctrl-0 = <&qup_i2c19_default>; 1635 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1636 #address-cells = <1>; 1637 #size-cells = <0>; 1638 status = "disabled"; 1639 }; 1640 1641 spi19: spi@c88000 { 1642 compatible = "qcom,geni-spi"; 1643 reg = <0 0x00c88000 0 0x4000>; 1644 reg-names = "se"; 1645 clock-names = "se"; 1646 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1647 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1648 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1649 dma-names = "tx", "rx"; 1650 pinctrl-names = "default"; 1651 pinctrl-0 = <&qup_spi19_default>; 1652 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1653 spi-max-frequency = <50000000>; 1654 #address-cells = <1>; 1655 #size-cells = <0>; 1656 status = "disabled"; 1657 }; 1658 1659 i2c13: i2c@c8c000 { 1660 compatible = "qcom,geni-i2c"; 1661 reg = <0 0x00c8c000 0 0x4000>; 1662 clock-names = "se"; 1663 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1664 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1665 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1666 dma-names = "tx", "rx"; 1667 pinctrl-names = "default"; 1668 pinctrl-0 = <&qup_i2c13_default>; 1669 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1670 #address-cells = <1>; 1671 #size-cells = <0>; 1672 status = "disabled"; 1673 }; 1674 1675 spi13: spi@c8c000 { 1676 compatible = "qcom,geni-spi"; 1677 reg = <0 0x00c8c000 0 0x4000>; 1678 reg-names = "se"; 1679 clock-names = "se"; 1680 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1681 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1682 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1683 dma-names = "tx", "rx"; 1684 pinctrl-names = "default"; 1685 pinctrl-0 = <&qup_spi13_default>; 1686 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1687 spi-max-frequency = <50000000>; 1688 #address-cells = <1>; 1689 #size-cells = <0>; 1690 status = "disabled"; 1691 }; 1692 1693 i2c14: i2c@c90000 { 1694 compatible = "qcom,geni-i2c"; 1695 reg = <0 0x00c90000 0 0x4000>; 1696 clock-names = "se"; 1697 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1698 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1699 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1700 dma-names = "tx", "rx"; 1701 pinctrl-names = "default"; 1702 pinctrl-0 = <&qup_i2c14_default>; 1703 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1704 #address-cells = <1>; 1705 #size-cells = <0>; 1706 status = "disabled"; 1707 }; 1708 1709 spi14: spi@c90000 { 1710 compatible = "qcom,geni-spi"; 1711 reg = <0 0x00c90000 0 0x4000>; 1712 reg-names = "se"; 1713 clock-names = "se"; 1714 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1715 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1716 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1717 dma-names = "tx", "rx"; 1718 pinctrl-names = "default"; 1719 pinctrl-0 = <&qup_spi14_default>; 1720 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1721 spi-max-frequency = <50000000>; 1722 #address-cells = <1>; 1723 #size-cells = <0>; 1724 status = "disabled"; 1725 }; 1726 1727 i2c15: i2c@c94000 { 1728 compatible = "qcom,geni-i2c"; 1729 reg = <0 0x00c94000 0 0x4000>; 1730 clock-names = "se"; 1731 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1732 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1733 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1734 dma-names = "tx", "rx"; 1735 pinctrl-names = "default"; 1736 pinctrl-0 = <&qup_i2c15_default>; 1737 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1738 #address-cells = <1>; 1739 #size-cells = <0>; 1740 status = "disabled"; 1741 }; 1742 1743 spi15: spi@c94000 { 1744 compatible = "qcom,geni-spi"; 1745 reg = <0 0x00c94000 0 0x4000>; 1746 reg-names = "se"; 1747 clock-names = "se"; 1748 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1749 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1750 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1751 dma-names = "tx", "rx"; 1752 pinctrl-names = "default"; 1753 pinctrl-0 = <&qup_spi15_default>; 1754 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1755 spi-max-frequency = <50000000>; 1756 #address-cells = <1>; 1757 #size-cells = <0>; 1758 status = "disabled"; 1759 }; 1760 }; 1761 1762 config_noc: interconnect@1500000 { 1763 compatible = "qcom,sm8150-config-noc"; 1764 reg = <0 0x01500000 0 0x7400>; 1765 #interconnect-cells = <2>; 1766 qcom,bcm-voters = <&apps_bcm_voter>; 1767 }; 1768 1769 system_noc: interconnect@1620000 { 1770 compatible = "qcom,sm8150-system-noc"; 1771 reg = <0 0x01620000 0 0x19400>; 1772 #interconnect-cells = <2>; 1773 qcom,bcm-voters = <&apps_bcm_voter>; 1774 }; 1775 1776 mc_virt: interconnect@163a000 { 1777 compatible = "qcom,sm8150-mc-virt"; 1778 reg = <0 0x0163a000 0 0x1000>; 1779 #interconnect-cells = <2>; 1780 qcom,bcm-voters = <&apps_bcm_voter>; 1781 }; 1782 1783 aggre1_noc: interconnect@16e0000 { 1784 compatible = "qcom,sm8150-aggre1-noc"; 1785 reg = <0 0x016e0000 0 0xd080>; 1786 #interconnect-cells = <2>; 1787 qcom,bcm-voters = <&apps_bcm_voter>; 1788 }; 1789 1790 aggre2_noc: interconnect@1700000 { 1791 compatible = "qcom,sm8150-aggre2-noc"; 1792 reg = <0 0x01700000 0 0x20000>; 1793 #interconnect-cells = <2>; 1794 qcom,bcm-voters = <&apps_bcm_voter>; 1795 }; 1796 1797 compute_noc: interconnect@1720000 { 1798 compatible = "qcom,sm8150-compute-noc"; 1799 reg = <0 0x01720000 0 0x7000>; 1800 #interconnect-cells = <2>; 1801 qcom,bcm-voters = <&apps_bcm_voter>; 1802 }; 1803 1804 mmss_noc: interconnect@1740000 { 1805 compatible = "qcom,sm8150-mmss-noc"; 1806 reg = <0 0x01740000 0 0x1c100>; 1807 #interconnect-cells = <2>; 1808 qcom,bcm-voters = <&apps_bcm_voter>; 1809 }; 1810 1811 system-cache-controller@9200000 { 1812 compatible = "qcom,sm8150-llcc"; 1813 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, 1814 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, 1815 <0 0x09600000 0 0x50000>; 1816 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 1817 "llcc3_base", "llcc_broadcast_base"; 1818 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1819 }; 1820 1821 dma@10a2000 { 1822 compatible = "qcom,sm8150-dcc", "qcom,dcc"; 1823 reg = <0x0 0x010a2000 0x0 0x1000>, 1824 <0x0 0x010ad000 0x0 0x3000>; 1825 }; 1826 1827 pcie0: pcie@1c00000 { 1828 compatible = "qcom,pcie-sm8150"; 1829 reg = <0 0x01c00000 0 0x3000>, 1830 <0 0x60000000 0 0xf1d>, 1831 <0 0x60000f20 0 0xa8>, 1832 <0 0x60001000 0 0x1000>, 1833 <0 0x60100000 0 0x100000>; 1834 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1835 device_type = "pci"; 1836 linux,pci-domain = <0>; 1837 bus-range = <0x00 0xff>; 1838 num-lanes = <1>; 1839 1840 #address-cells = <3>; 1841 #size-cells = <2>; 1842 1843 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1844 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1845 1846 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1854 interrupt-names = "msi0", 1855 "msi1", 1856 "msi2", 1857 "msi3", 1858 "msi4", 1859 "msi5", 1860 "msi6", 1861 "msi7"; 1862 #interrupt-cells = <1>; 1863 interrupt-map-mask = <0 0 0 0x7>; 1864 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1865 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1866 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1867 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1868 1869 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1870 <&gcc GCC_PCIE_0_AUX_CLK>, 1871 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1872 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1873 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1874 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1875 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1876 <&rpmhcc RPMH_CXO_CLK>; 1877 clock-names = "pipe", 1878 "aux", 1879 "cfg", 1880 "bus_master", 1881 "bus_slave", 1882 "slave_q2a", 1883 "tbu", 1884 "ref"; 1885 1886 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, 1887 <0x100 &apps_smmu 0x1d81 0x1>; 1888 1889 resets = <&gcc GCC_PCIE_0_BCR>; 1890 reset-names = "pci"; 1891 1892 power-domains = <&gcc PCIE_0_GDSC>; 1893 1894 phys = <&pcie0_phy>; 1895 phy-names = "pciephy"; 1896 1897 perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>; 1898 wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; 1899 1900 pinctrl-names = "default"; 1901 pinctrl-0 = <&pcie0_default_state>; 1902 1903 status = "disabled"; 1904 }; 1905 1906 pcie0_phy: phy@1c06000 { 1907 compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy"; 1908 reg = <0 0x01c06000 0 0x1000>; 1909 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1910 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1911 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1912 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, 1913 <&gcc GCC_PCIE_0_PIPE_CLK>; 1914 clock-names = "aux", 1915 "cfg_ahb", 1916 "ref", 1917 "refgen", 1918 "pipe"; 1919 1920 clock-output-names = "pcie_0_pipe_clk"; 1921 #clock-cells = <0>; 1922 1923 #phy-cells = <0>; 1924 1925 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1926 reset-names = "phy"; 1927 1928 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1929 assigned-clock-rates = <100000000>; 1930 1931 status = "disabled"; 1932 }; 1933 1934 pcie1: pcie@1c08000 { 1935 compatible = "qcom,pcie-sm8150"; 1936 reg = <0 0x01c08000 0 0x3000>, 1937 <0 0x40000000 0 0xf1d>, 1938 <0 0x40000f20 0 0xa8>, 1939 <0 0x40001000 0 0x1000>, 1940 <0 0x40100000 0 0x100000>; 1941 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1942 device_type = "pci"; 1943 linux,pci-domain = <1>; 1944 bus-range = <0x00 0xff>; 1945 num-lanes = <2>; 1946 1947 #address-cells = <3>; 1948 #size-cells = <2>; 1949 1950 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1951 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1952 1953 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1954 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1955 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1956 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1957 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1958 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1959 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 1960 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1961 interrupt-names = "msi0", 1962 "msi1", 1963 "msi2", 1964 "msi3", 1965 "msi4", 1966 "msi5", 1967 "msi6", 1968 "msi7"; 1969 #interrupt-cells = <1>; 1970 interrupt-map-mask = <0 0 0 0x7>; 1971 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1972 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1973 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1974 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1975 1976 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1977 <&gcc GCC_PCIE_1_AUX_CLK>, 1978 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1979 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1980 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1981 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1982 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1983 <&rpmhcc RPMH_CXO_CLK>; 1984 clock-names = "pipe", 1985 "aux", 1986 "cfg", 1987 "bus_master", 1988 "bus_slave", 1989 "slave_q2a", 1990 "tbu", 1991 "ref"; 1992 1993 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1994 assigned-clock-rates = <19200000>; 1995 1996 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 1997 <0x100 &apps_smmu 0x1e01 0x1>; 1998 1999 resets = <&gcc GCC_PCIE_1_BCR>; 2000 reset-names = "pci"; 2001 2002 power-domains = <&gcc PCIE_1_GDSC>; 2003 2004 phys = <&pcie1_phy>; 2005 phy-names = "pciephy"; 2006 2007 perst-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; 2008 enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>; 2009 2010 pinctrl-names = "default"; 2011 pinctrl-0 = <&pcie1_default_state>; 2012 2013 status = "disabled"; 2014 }; 2015 2016 pcie1_phy: phy@1c0e000 { 2017 compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy"; 2018 reg = <0 0x01c0e000 0 0x1000>; 2019 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2020 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2021 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2022 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, 2023 <&gcc GCC_PCIE_1_PIPE_CLK>; 2024 clock-names = "aux", 2025 "cfg_ahb", 2026 "ref", 2027 "refgen", 2028 "pipe"; 2029 2030 clock-output-names = "pcie_1_pipe_clk"; 2031 #clock-cells = <0>; 2032 2033 #phy-cells = <0>; 2034 2035 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2036 reset-names = "phy"; 2037 2038 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2039 assigned-clock-rates = <100000000>; 2040 2041 status = "disabled"; 2042 }; 2043 2044 ufs_mem_hc: ufshc@1d84000 { 2045 compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 2046 "jedec,ufs-2.0"; 2047 reg = <0 0x01d84000 0 0x2500>, 2048 <0 0x01d90000 0 0x8000>; 2049 reg-names = "std", "ice"; 2050 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2051 phys = <&ufs_mem_phy>; 2052 phy-names = "ufsphy"; 2053 lanes-per-direction = <2>; 2054 #reset-cells = <1>; 2055 resets = <&gcc GCC_UFS_PHY_BCR>; 2056 reset-names = "rst"; 2057 2058 iommus = <&apps_smmu 0x300 0>; 2059 2060 clock-names = 2061 "core_clk", 2062 "bus_aggr_clk", 2063 "iface_clk", 2064 "core_clk_unipro", 2065 "ref_clk", 2066 "tx_lane0_sync_clk", 2067 "rx_lane0_sync_clk", 2068 "rx_lane1_sync_clk", 2069 "ice_core_clk"; 2070 clocks = 2071 <&gcc GCC_UFS_PHY_AXI_CLK>, 2072 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2073 <&gcc GCC_UFS_PHY_AHB_CLK>, 2074 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2075 <&rpmhcc RPMH_CXO_CLK>, 2076 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2077 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2078 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 2079 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2080 freq-table-hz = 2081 <37500000 300000000>, 2082 <0 0>, 2083 <0 0>, 2084 <37500000 300000000>, 2085 <0 0>, 2086 <0 0>, 2087 <0 0>, 2088 <0 0>, 2089 <0 300000000>; 2090 2091 status = "disabled"; 2092 }; 2093 2094 ufs_mem_phy: phy@1d87000 { 2095 compatible = "qcom,sm8150-qmp-ufs-phy"; 2096 reg = <0 0x01d87000 0 0x1000>; 2097 2098 clocks = <&rpmhcc RPMH_CXO_CLK>, 2099 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2100 <&gcc GCC_UFS_MEM_CLKREF_CLK>; 2101 clock-names = "ref", 2102 "ref_aux", 2103 "qref"; 2104 2105 power-domains = <&gcc UFS_PHY_GDSC>; 2106 2107 resets = <&ufs_mem_hc 0>; 2108 reset-names = "ufsphy"; 2109 2110 #phy-cells = <0>; 2111 2112 status = "disabled"; 2113 }; 2114 2115 cryptobam: dma-controller@1dc4000 { 2116 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2117 reg = <0 0x01dc4000 0 0x24000>; 2118 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2119 #dma-cells = <1>; 2120 qcom,ee = <0>; 2121 qcom,controlled-remotely; 2122 num-channels = <8>; 2123 qcom,num-ees = <2>; 2124 iommus = <&apps_smmu 0x502 0x0641>, 2125 <&apps_smmu 0x504 0x0011>, 2126 <&apps_smmu 0x506 0x0011>, 2127 <&apps_smmu 0x508 0x0011>, 2128 <&apps_smmu 0x512 0x0000>; 2129 }; 2130 2131 crypto: crypto@1dfa000 { 2132 compatible = "qcom,sm8150-qce", "qcom,qce"; 2133 reg = <0 0x01dfa000 0 0x6000>; 2134 dmas = <&cryptobam 4>, <&cryptobam 5>; 2135 dma-names = "rx", "tx"; 2136 iommus = <&apps_smmu 0x502 0x0641>, 2137 <&apps_smmu 0x504 0x0011>, 2138 <&apps_smmu 0x506 0x0011>, 2139 <&apps_smmu 0x508 0x0011>, 2140 <&apps_smmu 0x512 0x0000>; 2141 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>; 2142 interconnect-names = "memory"; 2143 }; 2144 2145 tcsr_mutex: hwlock@1f40000 { 2146 compatible = "qcom,tcsr-mutex"; 2147 reg = <0x0 0x01f40000 0x0 0x20000>; 2148 #hwlock-cells = <1>; 2149 }; 2150 2151 tcsr_regs_1: syscon@1f60000 { 2152 compatible = "qcom,sm8150-tcsr", "syscon"; 2153 reg = <0x0 0x01f60000 0x0 0x20000>; 2154 }; 2155 2156 remoteproc_slpi: remoteproc@2400000 { 2157 compatible = "qcom,sm8150-slpi-pas"; 2158 reg = <0x0 0x02400000 0x0 0x4040>; 2159 2160 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 2161 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2162 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2163 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2164 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2165 interrupt-names = "wdog", "fatal", "ready", 2166 "handover", "stop-ack"; 2167 2168 clocks = <&rpmhcc RPMH_CXO_CLK>; 2169 clock-names = "xo"; 2170 2171 power-domains = <&rpmhpd SM8150_LCX>, 2172 <&rpmhpd SM8150_LMX>; 2173 power-domain-names = "lcx", "lmx"; 2174 2175 memory-region = <&slpi_mem>; 2176 2177 qcom,qmp = <&aoss_qmp>; 2178 2179 qcom,smem-states = <&slpi_smp2p_out 0>; 2180 qcom,smem-state-names = "stop"; 2181 2182 status = "disabled"; 2183 2184 glink-edge { 2185 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 2186 label = "dsps"; 2187 qcom,remote-pid = <3>; 2188 mboxes = <&apss_shared 24>; 2189 2190 fastrpc { 2191 compatible = "qcom,fastrpc"; 2192 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2193 label = "sdsp"; 2194 qcom,non-secure-domain; 2195 #address-cells = <1>; 2196 #size-cells = <0>; 2197 2198 compute-cb@1 { 2199 compatible = "qcom,fastrpc-compute-cb"; 2200 reg = <1>; 2201 iommus = <&apps_smmu 0x05a1 0x0>; 2202 }; 2203 2204 compute-cb@2 { 2205 compatible = "qcom,fastrpc-compute-cb"; 2206 reg = <2>; 2207 iommus = <&apps_smmu 0x05a2 0x0>; 2208 }; 2209 2210 compute-cb@3 { 2211 compatible = "qcom,fastrpc-compute-cb"; 2212 reg = <3>; 2213 iommus = <&apps_smmu 0x05a3 0x0>; 2214 /* note: shared-cb = <4> in downstream */ 2215 }; 2216 }; 2217 }; 2218 }; 2219 2220 gpu: gpu@2c00000 { 2221 compatible = "qcom,adreno-640.1", "qcom,adreno"; 2222 reg = <0 0x02c00000 0 0x40000>; 2223 reg-names = "kgsl_3d0_reg_memory"; 2224 2225 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2226 2227 iommus = <&adreno_smmu 0 0x401>; 2228 2229 operating-points-v2 = <&gpu_opp_table>; 2230 2231 qcom,gmu = <&gmu>; 2232 2233 nvmem-cells = <&gpu_speed_bin>; 2234 nvmem-cell-names = "speed_bin"; 2235 #cooling-cells = <2>; 2236 2237 status = "disabled"; 2238 2239 zap-shader { 2240 memory-region = <&gpu_mem>; 2241 }; 2242 2243 gpu_opp_table: opp-table { 2244 compatible = "operating-points-v2"; 2245 2246 opp-675000000 { 2247 opp-hz = /bits/ 64 <675000000>; 2248 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2249 opp-supported-hw = <0x2>; 2250 }; 2251 2252 opp-585000000 { 2253 opp-hz = /bits/ 64 <585000000>; 2254 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2255 opp-supported-hw = <0x3>; 2256 }; 2257 2258 opp-499200000 { 2259 opp-hz = /bits/ 64 <499200000>; 2260 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2261 opp-supported-hw = <0x3>; 2262 }; 2263 2264 opp-427000000 { 2265 opp-hz = /bits/ 64 <427000000>; 2266 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2267 opp-supported-hw = <0x3>; 2268 }; 2269 2270 opp-345000000 { 2271 opp-hz = /bits/ 64 <345000000>; 2272 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2273 opp-supported-hw = <0x3>; 2274 }; 2275 2276 opp-257000000 { 2277 opp-hz = /bits/ 64 <257000000>; 2278 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2279 opp-supported-hw = <0x3>; 2280 }; 2281 }; 2282 }; 2283 2284 gmu: gmu@2c6a000 { 2285 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 2286 2287 reg = <0 0x02c6a000 0 0x30000>, 2288 <0 0x0b290000 0 0x10000>, 2289 <0 0x0b490000 0 0x10000>; 2290 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2291 2292 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2293 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2294 interrupt-names = "hfi", "gmu"; 2295 2296 clocks = <&gpucc GPU_CC_AHB_CLK>, 2297 <&gpucc GPU_CC_CX_GMU_CLK>, 2298 <&gpucc GPU_CC_CXO_CLK>, 2299 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2300 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2301 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2302 2303 power-domains = <&gpucc GPU_CX_GDSC>, 2304 <&gpucc GPU_GX_GDSC>; 2305 power-domain-names = "cx", "gx"; 2306 2307 iommus = <&adreno_smmu 5 0x400>; 2308 2309 operating-points-v2 = <&gmu_opp_table>; 2310 2311 status = "disabled"; 2312 2313 gmu_opp_table: opp-table { 2314 compatible = "operating-points-v2"; 2315 2316 opp-200000000 { 2317 opp-hz = /bits/ 64 <200000000>; 2318 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2319 }; 2320 }; 2321 }; 2322 2323 gpucc: clock-controller@2c90000 { 2324 compatible = "qcom,sm8150-gpucc"; 2325 reg = <0 0x02c90000 0 0x9000>; 2326 clocks = <&rpmhcc RPMH_CXO_CLK>, 2327 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2328 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2329 clock-names = "bi_tcxo", 2330 "gcc_gpu_gpll0_clk_src", 2331 "gcc_gpu_gpll0_div_clk_src"; 2332 #clock-cells = <1>; 2333 #reset-cells = <1>; 2334 #power-domain-cells = <1>; 2335 }; 2336 2337 adreno_smmu: iommu@2ca0000 { 2338 compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu", 2339 "qcom,smmu-500", "arm,mmu-500"; 2340 reg = <0 0x02ca0000 0 0x10000>; 2341 #iommu-cells = <2>; 2342 #global-interrupts = <1>; 2343 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 2344 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2345 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2346 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2347 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2348 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2349 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2350 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2351 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 2352 clocks = <&gpucc GPU_CC_AHB_CLK>, 2353 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2354 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2355 clock-names = "ahb", "bus", "iface"; 2356 2357 power-domains = <&gpucc GPU_CX_GDSC>; 2358 }; 2359 2360 tlmm: pinctrl@3100000 { 2361 compatible = "qcom,sm8150-pinctrl"; 2362 reg = <0x0 0x03100000 0x0 0x300000>, 2363 <0x0 0x03500000 0x0 0x300000>, 2364 <0x0 0x03900000 0x0 0x300000>, 2365 <0x0 0x03D00000 0x0 0x300000>; 2366 reg-names = "west", "east", "north", "south"; 2367 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2368 gpio-ranges = <&tlmm 0 0 176>; 2369 gpio-controller; 2370 #gpio-cells = <2>; 2371 interrupt-controller; 2372 #interrupt-cells = <2>; 2373 wakeup-parent = <&pdc>; 2374 2375 qup_i2c0_default: qup-i2c0-default-state { 2376 pins = "gpio0", "gpio1"; 2377 function = "qup0"; 2378 drive-strength = <0x02>; 2379 bias-disable; 2380 }; 2381 2382 qup_spi0_default: qup-spi0-default-state { 2383 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 2384 function = "qup0"; 2385 drive-strength = <6>; 2386 bias-disable; 2387 }; 2388 2389 qup_i2c1_default: qup-i2c1-default-state { 2390 pins = "gpio114", "gpio115"; 2391 function = "qup1"; 2392 drive-strength = <2>; 2393 bias-disable; 2394 }; 2395 2396 qup_spi1_default: qup-spi1-default-state { 2397 pins = "gpio114", "gpio115", "gpio116", "gpio117"; 2398 function = "qup1"; 2399 drive-strength = <6>; 2400 bias-disable; 2401 }; 2402 2403 qup_i2c2_default: qup-i2c2-default-state { 2404 pins = "gpio126", "gpio127"; 2405 function = "qup2"; 2406 drive-strength = <2>; 2407 bias-disable; 2408 }; 2409 2410 qup_spi2_default: qup-spi2-default-state { 2411 pins = "gpio126", "gpio127", "gpio128", "gpio129"; 2412 function = "qup2"; 2413 drive-strength = <6>; 2414 bias-disable; 2415 }; 2416 2417 qup_i2c3_default: qup-i2c3-default-state { 2418 pins = "gpio144", "gpio145"; 2419 function = "qup3"; 2420 drive-strength = <2>; 2421 bias-disable; 2422 }; 2423 2424 qup_spi3_default: qup-spi3-default-state { 2425 pins = "gpio144", "gpio145", "gpio146", "gpio147"; 2426 function = "qup3"; 2427 drive-strength = <6>; 2428 bias-disable; 2429 }; 2430 2431 qup_i2c4_default: qup-i2c4-default-state { 2432 pins = "gpio51", "gpio52"; 2433 function = "qup4"; 2434 drive-strength = <2>; 2435 bias-disable; 2436 }; 2437 2438 qup_spi4_default: qup-spi4-default-state { 2439 pins = "gpio51", "gpio52", "gpio53", "gpio54"; 2440 function = "qup4"; 2441 drive-strength = <6>; 2442 bias-disable; 2443 }; 2444 2445 qup_i2c5_default: qup-i2c5-default-state { 2446 pins = "gpio121", "gpio122"; 2447 function = "qup5"; 2448 drive-strength = <2>; 2449 bias-disable; 2450 }; 2451 2452 qup_spi5_default: qup-spi5-default-state { 2453 pins = "gpio119", "gpio120", "gpio121", "gpio122"; 2454 function = "qup5"; 2455 drive-strength = <6>; 2456 bias-disable; 2457 }; 2458 2459 qup_i2c6_default: qup-i2c6-default-state { 2460 pins = "gpio6", "gpio7"; 2461 function = "qup6"; 2462 drive-strength = <2>; 2463 bias-disable; 2464 }; 2465 2466 qup_spi6_default: qup-spi6-default-state { 2467 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 2468 function = "qup6"; 2469 drive-strength = <6>; 2470 bias-disable; 2471 }; 2472 2473 qup_i2c7_default: qup-i2c7-default-state { 2474 pins = "gpio98", "gpio99"; 2475 function = "qup7"; 2476 drive-strength = <2>; 2477 bias-disable; 2478 }; 2479 2480 qup_spi7_default: qup-spi7-default-state { 2481 pins = "gpio98", "gpio99", "gpio100", "gpio101"; 2482 function = "qup7"; 2483 drive-strength = <6>; 2484 bias-disable; 2485 }; 2486 2487 qup_i2c8_default: qup-i2c8-default-state { 2488 pins = "gpio88", "gpio89"; 2489 function = "qup8"; 2490 drive-strength = <2>; 2491 bias-disable; 2492 }; 2493 2494 qup_spi8_default: qup-spi8-default-state { 2495 pins = "gpio88", "gpio89", "gpio90", "gpio91"; 2496 function = "qup8"; 2497 drive-strength = <6>; 2498 bias-disable; 2499 }; 2500 2501 qup_i2c9_default: qup-i2c9-default-state { 2502 pins = "gpio39", "gpio40"; 2503 function = "qup9"; 2504 drive-strength = <2>; 2505 bias-disable; 2506 }; 2507 2508 qup_spi9_default: qup-spi9-default-state { 2509 pins = "gpio39", "gpio40", "gpio41", "gpio42"; 2510 function = "qup9"; 2511 drive-strength = <6>; 2512 bias-disable; 2513 }; 2514 2515 qup_uart9_default: qup-uart9-default-state { 2516 pins = "gpio41", "gpio42"; 2517 function = "qup9"; 2518 drive-strength = <2>; 2519 bias-disable; 2520 }; 2521 2522 qup_i2c10_default: qup-i2c10-default-state { 2523 pins = "gpio9", "gpio10"; 2524 function = "qup10"; 2525 drive-strength = <2>; 2526 bias-disable; 2527 }; 2528 2529 qup_spi10_default: qup-spi10-default-state { 2530 pins = "gpio9", "gpio10", "gpio11", "gpio12"; 2531 function = "qup10"; 2532 drive-strength = <6>; 2533 bias-disable; 2534 }; 2535 2536 qup_i2c11_default: qup-i2c11-default-state { 2537 pins = "gpio94", "gpio95"; 2538 function = "qup11"; 2539 drive-strength = <2>; 2540 bias-disable; 2541 }; 2542 2543 qup_spi11_default: qup-spi11-default-state { 2544 pins = "gpio92", "gpio93", "gpio94", "gpio95"; 2545 function = "qup11"; 2546 drive-strength = <6>; 2547 bias-disable; 2548 }; 2549 2550 qup_i2c12_default: qup-i2c12-default-state { 2551 pins = "gpio83", "gpio84"; 2552 function = "qup12"; 2553 drive-strength = <2>; 2554 bias-disable; 2555 }; 2556 2557 qup_spi12_default: qup-spi12-default-state { 2558 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2559 function = "qup12"; 2560 drive-strength = <6>; 2561 bias-disable; 2562 }; 2563 2564 qup_i2c13_default: qup-i2c13-default-state { 2565 pins = "gpio43", "gpio44"; 2566 function = "qup13"; 2567 drive-strength = <2>; 2568 bias-disable; 2569 }; 2570 2571 qup_spi13_default: qup-spi13-default-state { 2572 pins = "gpio43", "gpio44", "gpio45", "gpio46"; 2573 function = "qup13"; 2574 drive-strength = <6>; 2575 bias-disable; 2576 }; 2577 2578 qup_i2c14_default: qup-i2c14-default-state { 2579 pins = "gpio47", "gpio48"; 2580 function = "qup14"; 2581 drive-strength = <2>; 2582 bias-disable; 2583 }; 2584 2585 qup_spi14_default: qup-spi14-default-state { 2586 pins = "gpio47", "gpio48", "gpio49", "gpio50"; 2587 function = "qup14"; 2588 drive-strength = <6>; 2589 bias-disable; 2590 }; 2591 2592 qup_i2c15_default: qup-i2c15-default-state { 2593 pins = "gpio27", "gpio28"; 2594 function = "qup15"; 2595 drive-strength = <2>; 2596 bias-disable; 2597 }; 2598 2599 qup_spi15_default: qup-spi15-default-state { 2600 pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2601 function = "qup15"; 2602 drive-strength = <6>; 2603 bias-disable; 2604 }; 2605 2606 qup_i2c16_default: qup-i2c16-default-state { 2607 pins = "gpio86", "gpio85"; 2608 function = "qup16"; 2609 drive-strength = <2>; 2610 bias-disable; 2611 }; 2612 2613 qup_spi16_default: qup-spi16-default-state { 2614 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2615 function = "qup16"; 2616 drive-strength = <6>; 2617 bias-disable; 2618 }; 2619 2620 qup_i2c17_default: qup-i2c17-default-state { 2621 pins = "gpio55", "gpio56"; 2622 function = "qup17"; 2623 drive-strength = <2>; 2624 bias-disable; 2625 }; 2626 2627 qup_spi17_default: qup-spi17-default-state { 2628 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2629 function = "qup17"; 2630 drive-strength = <6>; 2631 bias-disable; 2632 }; 2633 2634 qup_i2c18_default: qup-i2c18-default-state { 2635 pins = "gpio23", "gpio24"; 2636 function = "qup18"; 2637 drive-strength = <2>; 2638 bias-disable; 2639 }; 2640 2641 qup_spi18_default: qup-spi18-default-state { 2642 pins = "gpio23", "gpio24", "gpio25", "gpio26"; 2643 function = "qup18"; 2644 drive-strength = <6>; 2645 bias-disable; 2646 }; 2647 2648 qup_i2c19_default: qup-i2c19-default-state { 2649 pins = "gpio57", "gpio58"; 2650 function = "qup19"; 2651 drive-strength = <2>; 2652 bias-disable; 2653 }; 2654 2655 qup_spi19_default: qup-spi19-default-state { 2656 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2657 function = "qup19"; 2658 drive-strength = <6>; 2659 bias-disable; 2660 }; 2661 2662 pcie0_default_state: pcie0-default-state { 2663 perst-pins { 2664 pins = "gpio35"; 2665 function = "gpio"; 2666 drive-strength = <2>; 2667 bias-pull-down; 2668 }; 2669 2670 clkreq-pins { 2671 pins = "gpio36"; 2672 function = "pci_e0"; 2673 drive-strength = <2>; 2674 bias-pull-up; 2675 }; 2676 2677 wake-pins { 2678 pins = "gpio37"; 2679 function = "gpio"; 2680 drive-strength = <2>; 2681 bias-pull-up; 2682 }; 2683 }; 2684 2685 pcie1_default_state: pcie1-default-state { 2686 perst-pins { 2687 pins = "gpio102"; 2688 function = "gpio"; 2689 drive-strength = <2>; 2690 bias-pull-down; 2691 }; 2692 2693 clkreq-pins { 2694 pins = "gpio103"; 2695 function = "pci_e1"; 2696 drive-strength = <2>; 2697 bias-pull-up; 2698 }; 2699 2700 wake-pins { 2701 pins = "gpio104"; 2702 function = "gpio"; 2703 drive-strength = <2>; 2704 bias-pull-up; 2705 }; 2706 }; 2707 }; 2708 2709 remoteproc_mpss: remoteproc@4080000 { 2710 compatible = "qcom,sm8150-mpss-pas"; 2711 reg = <0x0 0x04080000 0x0 0x4040>; 2712 2713 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2714 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2715 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2716 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2717 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2718 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2719 interrupt-names = "wdog", "fatal", "ready", "handover", 2720 "stop-ack", "shutdown-ack"; 2721 2722 clocks = <&rpmhcc RPMH_CXO_CLK>; 2723 clock-names = "xo"; 2724 2725 power-domains = <&rpmhpd SM8150_CX>, 2726 <&rpmhpd SM8150_MSS>; 2727 power-domain-names = "cx", "mss"; 2728 2729 memory-region = <&mpss_mem>; 2730 2731 qcom,qmp = <&aoss_qmp>; 2732 2733 qcom,smem-states = <&modem_smp2p_out 0>; 2734 qcom,smem-state-names = "stop"; 2735 2736 status = "disabled"; 2737 2738 glink-edge { 2739 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2740 label = "modem"; 2741 qcom,remote-pid = <1>; 2742 mboxes = <&apss_shared 12>; 2743 }; 2744 }; 2745 2746 stm@6002000 { 2747 compatible = "arm,coresight-stm", "arm,primecell"; 2748 reg = <0 0x06002000 0 0x1000>, 2749 <0 0x16280000 0 0x180000>; 2750 reg-names = "stm-base", "stm-stimulus-base"; 2751 2752 clocks = <&aoss_qmp>; 2753 clock-names = "apb_pclk"; 2754 2755 out-ports { 2756 port { 2757 stm_out: endpoint { 2758 remote-endpoint = <&funnel0_in7>; 2759 }; 2760 }; 2761 }; 2762 }; 2763 2764 funnel@6041000 { 2765 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2766 reg = <0 0x06041000 0 0x1000>; 2767 2768 clocks = <&aoss_qmp>; 2769 clock-names = "apb_pclk"; 2770 2771 out-ports { 2772 port { 2773 funnel0_out: endpoint { 2774 remote-endpoint = <&merge_funnel_in0>; 2775 }; 2776 }; 2777 }; 2778 2779 in-ports { 2780 #address-cells = <1>; 2781 #size-cells = <0>; 2782 2783 port@7 { 2784 reg = <7>; 2785 funnel0_in7: endpoint { 2786 remote-endpoint = <&stm_out>; 2787 }; 2788 }; 2789 }; 2790 }; 2791 2792 funnel@6042000 { 2793 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2794 reg = <0 0x06042000 0 0x1000>; 2795 2796 clocks = <&aoss_qmp>; 2797 clock-names = "apb_pclk"; 2798 2799 out-ports { 2800 port { 2801 funnel1_out: endpoint { 2802 remote-endpoint = <&merge_funnel_in1>; 2803 }; 2804 }; 2805 }; 2806 2807 in-ports { 2808 #address-cells = <1>; 2809 #size-cells = <0>; 2810 2811 port@4 { 2812 reg = <4>; 2813 funnel1_in4: endpoint { 2814 remote-endpoint = <&swao_replicator_out>; 2815 }; 2816 }; 2817 }; 2818 }; 2819 2820 funnel@6043000 { 2821 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2822 reg = <0 0x06043000 0 0x1000>; 2823 2824 clocks = <&aoss_qmp>; 2825 clock-names = "apb_pclk"; 2826 2827 out-ports { 2828 port { 2829 funnel2_out: endpoint { 2830 remote-endpoint = <&merge_funnel_in2>; 2831 }; 2832 }; 2833 }; 2834 2835 in-ports { 2836 #address-cells = <1>; 2837 #size-cells = <0>; 2838 2839 port@2 { 2840 reg = <2>; 2841 funnel2_in2: endpoint { 2842 remote-endpoint = <&apss_merge_funnel_out>; 2843 }; 2844 }; 2845 }; 2846 }; 2847 2848 funnel@6045000 { 2849 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2850 reg = <0 0x06045000 0 0x1000>; 2851 2852 clocks = <&aoss_qmp>; 2853 clock-names = "apb_pclk"; 2854 2855 out-ports { 2856 port { 2857 merge_funnel_out: endpoint { 2858 remote-endpoint = <&etf_in>; 2859 }; 2860 }; 2861 }; 2862 2863 in-ports { 2864 #address-cells = <1>; 2865 #size-cells = <0>; 2866 2867 port@0 { 2868 reg = <0>; 2869 merge_funnel_in0: endpoint { 2870 remote-endpoint = <&funnel0_out>; 2871 }; 2872 }; 2873 2874 port@1 { 2875 reg = <1>; 2876 merge_funnel_in1: endpoint { 2877 remote-endpoint = <&funnel1_out>; 2878 }; 2879 }; 2880 2881 port@2 { 2882 reg = <2>; 2883 merge_funnel_in2: endpoint { 2884 remote-endpoint = <&funnel2_out>; 2885 }; 2886 }; 2887 }; 2888 }; 2889 2890 replicator@6046000 { 2891 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2892 reg = <0 0x06046000 0 0x1000>; 2893 2894 clocks = <&aoss_qmp>; 2895 clock-names = "apb_pclk"; 2896 2897 out-ports { 2898 #address-cells = <1>; 2899 #size-cells = <0>; 2900 2901 port@0 { 2902 reg = <0>; 2903 replicator_out0: endpoint { 2904 remote-endpoint = <&etr_in>; 2905 }; 2906 }; 2907 2908 port@1 { 2909 reg = <1>; 2910 replicator_out1: endpoint { 2911 remote-endpoint = <&replicator1_in>; 2912 }; 2913 }; 2914 }; 2915 2916 in-ports { 2917 port { 2918 replicator_in0: endpoint { 2919 remote-endpoint = <&etf_out>; 2920 }; 2921 }; 2922 }; 2923 }; 2924 2925 etf@6047000 { 2926 compatible = "arm,coresight-tmc", "arm,primecell"; 2927 reg = <0 0x06047000 0 0x1000>; 2928 2929 clocks = <&aoss_qmp>; 2930 clock-names = "apb_pclk"; 2931 2932 out-ports { 2933 port { 2934 etf_out: endpoint { 2935 remote-endpoint = <&replicator_in0>; 2936 }; 2937 }; 2938 }; 2939 2940 in-ports { 2941 port { 2942 etf_in: endpoint { 2943 remote-endpoint = <&merge_funnel_out>; 2944 }; 2945 }; 2946 }; 2947 }; 2948 2949 etr@6048000 { 2950 compatible = "arm,coresight-tmc", "arm,primecell"; 2951 reg = <0 0x06048000 0 0x1000>; 2952 iommus = <&apps_smmu 0x05e0 0x0>; 2953 2954 clocks = <&aoss_qmp>; 2955 clock-names = "apb_pclk"; 2956 arm,scatter-gather; 2957 2958 in-ports { 2959 port { 2960 etr_in: endpoint { 2961 remote-endpoint = <&replicator_out0>; 2962 }; 2963 }; 2964 }; 2965 }; 2966 2967 replicator@604a000 { 2968 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2969 reg = <0 0x0604a000 0 0x1000>; 2970 2971 clocks = <&aoss_qmp>; 2972 clock-names = "apb_pclk"; 2973 2974 out-ports { 2975 #address-cells = <1>; 2976 #size-cells = <0>; 2977 2978 port@1 { 2979 reg = <1>; 2980 replicator1_out: endpoint { 2981 remote-endpoint = <&swao_funnel_in>; 2982 }; 2983 }; 2984 }; 2985 2986 in-ports { 2987 2988 port { 2989 replicator1_in: endpoint { 2990 remote-endpoint = <&replicator_out1>; 2991 }; 2992 }; 2993 }; 2994 }; 2995 2996 funnel@6b08000 { 2997 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2998 reg = <0 0x06b08000 0 0x1000>; 2999 3000 clocks = <&aoss_qmp>; 3001 clock-names = "apb_pclk"; 3002 3003 out-ports { 3004 port { 3005 swao_funnel_out: endpoint { 3006 remote-endpoint = <&swao_etf_in>; 3007 }; 3008 }; 3009 }; 3010 3011 in-ports { 3012 #address-cells = <1>; 3013 #size-cells = <0>; 3014 3015 port@6 { 3016 reg = <6>; 3017 swao_funnel_in: endpoint { 3018 remote-endpoint = <&replicator1_out>; 3019 }; 3020 }; 3021 }; 3022 }; 3023 3024 etf@6b09000 { 3025 compatible = "arm,coresight-tmc", "arm,primecell"; 3026 reg = <0 0x06b09000 0 0x1000>; 3027 3028 clocks = <&aoss_qmp>; 3029 clock-names = "apb_pclk"; 3030 3031 out-ports { 3032 port { 3033 swao_etf_out: endpoint { 3034 remote-endpoint = <&swao_replicator_in>; 3035 }; 3036 }; 3037 }; 3038 3039 in-ports { 3040 port { 3041 swao_etf_in: endpoint { 3042 remote-endpoint = <&swao_funnel_out>; 3043 }; 3044 }; 3045 }; 3046 }; 3047 3048 replicator@6b0a000 { 3049 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3050 reg = <0 0x06b0a000 0 0x1000>; 3051 3052 clocks = <&aoss_qmp>; 3053 clock-names = "apb_pclk"; 3054 qcom,replicator-loses-context; 3055 3056 out-ports { 3057 port { 3058 swao_replicator_out: endpoint { 3059 remote-endpoint = <&funnel1_in4>; 3060 }; 3061 }; 3062 }; 3063 3064 in-ports { 3065 port { 3066 swao_replicator_in: endpoint { 3067 remote-endpoint = <&swao_etf_out>; 3068 }; 3069 }; 3070 }; 3071 }; 3072 3073 etm@7040000 { 3074 compatible = "arm,coresight-etm4x", "arm,primecell"; 3075 reg = <0 0x07040000 0 0x1000>; 3076 3077 cpu = <&CPU0>; 3078 3079 clocks = <&aoss_qmp>; 3080 clock-names = "apb_pclk"; 3081 arm,coresight-loses-context-with-cpu; 3082 qcom,skip-power-up; 3083 3084 out-ports { 3085 port { 3086 etm0_out: endpoint { 3087 remote-endpoint = <&apss_funnel_in0>; 3088 }; 3089 }; 3090 }; 3091 }; 3092 3093 etm@7140000 { 3094 compatible = "arm,coresight-etm4x", "arm,primecell"; 3095 reg = <0 0x07140000 0 0x1000>; 3096 3097 cpu = <&CPU1>; 3098 3099 clocks = <&aoss_qmp>; 3100 clock-names = "apb_pclk"; 3101 arm,coresight-loses-context-with-cpu; 3102 qcom,skip-power-up; 3103 3104 out-ports { 3105 port { 3106 etm1_out: endpoint { 3107 remote-endpoint = <&apss_funnel_in1>; 3108 }; 3109 }; 3110 }; 3111 }; 3112 3113 etm@7240000 { 3114 compatible = "arm,coresight-etm4x", "arm,primecell"; 3115 reg = <0 0x07240000 0 0x1000>; 3116 3117 cpu = <&CPU2>; 3118 3119 clocks = <&aoss_qmp>; 3120 clock-names = "apb_pclk"; 3121 arm,coresight-loses-context-with-cpu; 3122 qcom,skip-power-up; 3123 3124 out-ports { 3125 port { 3126 etm2_out: endpoint { 3127 remote-endpoint = <&apss_funnel_in2>; 3128 }; 3129 }; 3130 }; 3131 }; 3132 3133 etm@7340000 { 3134 compatible = "arm,coresight-etm4x", "arm,primecell"; 3135 reg = <0 0x07340000 0 0x1000>; 3136 3137 cpu = <&CPU3>; 3138 3139 clocks = <&aoss_qmp>; 3140 clock-names = "apb_pclk"; 3141 arm,coresight-loses-context-with-cpu; 3142 qcom,skip-power-up; 3143 3144 out-ports { 3145 port { 3146 etm3_out: endpoint { 3147 remote-endpoint = <&apss_funnel_in3>; 3148 }; 3149 }; 3150 }; 3151 }; 3152 3153 etm@7440000 { 3154 compatible = "arm,coresight-etm4x", "arm,primecell"; 3155 reg = <0 0x07440000 0 0x1000>; 3156 3157 cpu = <&CPU4>; 3158 3159 clocks = <&aoss_qmp>; 3160 clock-names = "apb_pclk"; 3161 arm,coresight-loses-context-with-cpu; 3162 qcom,skip-power-up; 3163 3164 out-ports { 3165 port { 3166 etm4_out: endpoint { 3167 remote-endpoint = <&apss_funnel_in4>; 3168 }; 3169 }; 3170 }; 3171 }; 3172 3173 etm@7540000 { 3174 compatible = "arm,coresight-etm4x", "arm,primecell"; 3175 reg = <0 0x07540000 0 0x1000>; 3176 3177 cpu = <&CPU5>; 3178 3179 clocks = <&aoss_qmp>; 3180 clock-names = "apb_pclk"; 3181 arm,coresight-loses-context-with-cpu; 3182 qcom,skip-power-up; 3183 3184 out-ports { 3185 port { 3186 etm5_out: endpoint { 3187 remote-endpoint = <&apss_funnel_in5>; 3188 }; 3189 }; 3190 }; 3191 }; 3192 3193 etm@7640000 { 3194 compatible = "arm,coresight-etm4x", "arm,primecell"; 3195 reg = <0 0x07640000 0 0x1000>; 3196 3197 cpu = <&CPU6>; 3198 3199 clocks = <&aoss_qmp>; 3200 clock-names = "apb_pclk"; 3201 arm,coresight-loses-context-with-cpu; 3202 qcom,skip-power-up; 3203 3204 out-ports { 3205 port { 3206 etm6_out: endpoint { 3207 remote-endpoint = <&apss_funnel_in6>; 3208 }; 3209 }; 3210 }; 3211 }; 3212 3213 etm@7740000 { 3214 compatible = "arm,coresight-etm4x", "arm,primecell"; 3215 reg = <0 0x07740000 0 0x1000>; 3216 3217 cpu = <&CPU7>; 3218 3219 clocks = <&aoss_qmp>; 3220 clock-names = "apb_pclk"; 3221 arm,coresight-loses-context-with-cpu; 3222 qcom,skip-power-up; 3223 3224 out-ports { 3225 port { 3226 etm7_out: endpoint { 3227 remote-endpoint = <&apss_funnel_in7>; 3228 }; 3229 }; 3230 }; 3231 }; 3232 3233 funnel@7800000 { /* APSS Funnel */ 3234 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3235 reg = <0 0x07800000 0 0x1000>; 3236 3237 clocks = <&aoss_qmp>; 3238 clock-names = "apb_pclk"; 3239 3240 out-ports { 3241 port { 3242 apss_funnel_out: endpoint { 3243 remote-endpoint = <&apss_merge_funnel_in>; 3244 }; 3245 }; 3246 }; 3247 3248 in-ports { 3249 #address-cells = <1>; 3250 #size-cells = <0>; 3251 3252 port@0 { 3253 reg = <0>; 3254 apss_funnel_in0: endpoint { 3255 remote-endpoint = <&etm0_out>; 3256 }; 3257 }; 3258 3259 port@1 { 3260 reg = <1>; 3261 apss_funnel_in1: endpoint { 3262 remote-endpoint = <&etm1_out>; 3263 }; 3264 }; 3265 3266 port@2 { 3267 reg = <2>; 3268 apss_funnel_in2: endpoint { 3269 remote-endpoint = <&etm2_out>; 3270 }; 3271 }; 3272 3273 port@3 { 3274 reg = <3>; 3275 apss_funnel_in3: endpoint { 3276 remote-endpoint = <&etm3_out>; 3277 }; 3278 }; 3279 3280 port@4 { 3281 reg = <4>; 3282 apss_funnel_in4: endpoint { 3283 remote-endpoint = <&etm4_out>; 3284 }; 3285 }; 3286 3287 port@5 { 3288 reg = <5>; 3289 apss_funnel_in5: endpoint { 3290 remote-endpoint = <&etm5_out>; 3291 }; 3292 }; 3293 3294 port@6 { 3295 reg = <6>; 3296 apss_funnel_in6: endpoint { 3297 remote-endpoint = <&etm6_out>; 3298 }; 3299 }; 3300 3301 port@7 { 3302 reg = <7>; 3303 apss_funnel_in7: endpoint { 3304 remote-endpoint = <&etm7_out>; 3305 }; 3306 }; 3307 }; 3308 }; 3309 3310 funnel@7810000 { 3311 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3312 reg = <0 0x07810000 0 0x1000>; 3313 3314 clocks = <&aoss_qmp>; 3315 clock-names = "apb_pclk"; 3316 3317 out-ports { 3318 port { 3319 apss_merge_funnel_out: endpoint { 3320 remote-endpoint = <&funnel2_in2>; 3321 }; 3322 }; 3323 }; 3324 3325 in-ports { 3326 port { 3327 apss_merge_funnel_in: endpoint { 3328 remote-endpoint = <&apss_funnel_out>; 3329 }; 3330 }; 3331 }; 3332 }; 3333 3334 remoteproc_cdsp: remoteproc@8300000 { 3335 compatible = "qcom,sm8150-cdsp-pas"; 3336 reg = <0x0 0x08300000 0x0 0x4040>; 3337 3338 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3339 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3340 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3341 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3342 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3343 interrupt-names = "wdog", "fatal", "ready", 3344 "handover", "stop-ack"; 3345 3346 clocks = <&rpmhcc RPMH_CXO_CLK>; 3347 clock-names = "xo"; 3348 3349 power-domains = <&rpmhpd SM8150_CX>; 3350 3351 memory-region = <&cdsp_mem>; 3352 3353 qcom,qmp = <&aoss_qmp>; 3354 3355 qcom,smem-states = <&cdsp_smp2p_out 0>; 3356 qcom,smem-state-names = "stop"; 3357 3358 status = "disabled"; 3359 3360 glink-edge { 3361 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 3362 label = "cdsp"; 3363 qcom,remote-pid = <5>; 3364 mboxes = <&apss_shared 4>; 3365 3366 fastrpc { 3367 compatible = "qcom,fastrpc"; 3368 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3369 label = "cdsp"; 3370 qcom,non-secure-domain; 3371 #address-cells = <1>; 3372 #size-cells = <0>; 3373 3374 compute-cb@1 { 3375 compatible = "qcom,fastrpc-compute-cb"; 3376 reg = <1>; 3377 iommus = <&apps_smmu 0x1001 0x0460>; 3378 }; 3379 3380 compute-cb@2 { 3381 compatible = "qcom,fastrpc-compute-cb"; 3382 reg = <2>; 3383 iommus = <&apps_smmu 0x1002 0x0460>; 3384 }; 3385 3386 compute-cb@3 { 3387 compatible = "qcom,fastrpc-compute-cb"; 3388 reg = <3>; 3389 iommus = <&apps_smmu 0x1003 0x0460>; 3390 }; 3391 3392 compute-cb@4 { 3393 compatible = "qcom,fastrpc-compute-cb"; 3394 reg = <4>; 3395 iommus = <&apps_smmu 0x1004 0x0460>; 3396 }; 3397 3398 compute-cb@5 { 3399 compatible = "qcom,fastrpc-compute-cb"; 3400 reg = <5>; 3401 iommus = <&apps_smmu 0x1005 0x0460>; 3402 }; 3403 3404 compute-cb@6 { 3405 compatible = "qcom,fastrpc-compute-cb"; 3406 reg = <6>; 3407 iommus = <&apps_smmu 0x1006 0x0460>; 3408 }; 3409 3410 compute-cb@7 { 3411 compatible = "qcom,fastrpc-compute-cb"; 3412 reg = <7>; 3413 iommus = <&apps_smmu 0x1007 0x0460>; 3414 }; 3415 3416 compute-cb@8 { 3417 compatible = "qcom,fastrpc-compute-cb"; 3418 reg = <8>; 3419 iommus = <&apps_smmu 0x1008 0x0460>; 3420 }; 3421 3422 /* note: secure cb9 in downstream */ 3423 }; 3424 }; 3425 }; 3426 3427 usb_1_hsphy: phy@88e2000 { 3428 compatible = "qcom,sm8150-usb-hs-phy", 3429 "qcom,usb-snps-hs-7nm-phy"; 3430 reg = <0 0x088e2000 0 0x400>; 3431 status = "disabled"; 3432 #phy-cells = <0>; 3433 3434 clocks = <&rpmhcc RPMH_CXO_CLK>; 3435 clock-names = "ref"; 3436 3437 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3438 }; 3439 3440 usb_2_hsphy: phy@88e3000 { 3441 compatible = "qcom,sm8150-usb-hs-phy", 3442 "qcom,usb-snps-hs-7nm-phy"; 3443 reg = <0 0x088e3000 0 0x400>; 3444 status = "disabled"; 3445 #phy-cells = <0>; 3446 3447 clocks = <&rpmhcc RPMH_CXO_CLK>; 3448 clock-names = "ref"; 3449 3450 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3451 }; 3452 3453 usb_1_qmpphy: phy@88e8000 { 3454 compatible = "qcom,sm8150-qmp-usb3-dp-phy"; 3455 reg = <0 0x088e8000 0 0x3000>; 3456 3457 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3458 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3459 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3460 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3461 clock-names = "aux", 3462 "ref", 3463 "com_aux", 3464 "usb3_pipe"; 3465 3466 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3467 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3468 reset-names = "phy", "common"; 3469 3470 #clock-cells = <1>; 3471 #phy-cells = <1>; 3472 3473 status = "disabled"; 3474 3475 ports { 3476 #address-cells = <1>; 3477 #size-cells = <0>; 3478 3479 port@0 { 3480 reg = <0>; 3481 3482 usb_1_qmpphy_out: endpoint { 3483 }; 3484 }; 3485 3486 port@1 { 3487 reg = <1>; 3488 3489 usb_1_qmpphy_usb_ss_in: endpoint { 3490 }; 3491 }; 3492 3493 port@2 { 3494 reg = <2>; 3495 3496 usb_1_qmpphy_dp_in: endpoint { 3497 }; 3498 }; 3499 }; 3500 }; 3501 3502 usb_2_qmpphy: phy@88eb000 { 3503 compatible = "qcom,sm8150-qmp-usb3-uni-phy"; 3504 reg = <0 0x088eb000 0 0x1000>; 3505 3506 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3507 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 3508 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 3509 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3510 clock-names = "aux", 3511 "ref", 3512 "com_aux", 3513 "pipe"; 3514 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3515 #clock-cells = <0>; 3516 #phy-cells = <0>; 3517 3518 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 3519 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 3520 reset-names = "phy", 3521 "phy_phy"; 3522 3523 status = "disabled"; 3524 }; 3525 3526 sdhc_2: mmc@8804000 { 3527 compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5"; 3528 reg = <0 0x08804000 0 0x1000>; 3529 3530 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3531 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3532 interrupt-names = "hc_irq", "pwr_irq"; 3533 3534 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3535 <&gcc GCC_SDCC2_APPS_CLK>, 3536 <&rpmhcc RPMH_CXO_CLK>; 3537 clock-names = "iface", "core", "xo"; 3538 iommus = <&apps_smmu 0x6a0 0x0>; 3539 qcom,dll-config = <0x0007642c>; 3540 qcom,ddr-config = <0x80040868>; 3541 power-domains = <&rpmhpd 0>; 3542 operating-points-v2 = <&sdhc2_opp_table>; 3543 3544 status = "disabled"; 3545 3546 sdhc2_opp_table: opp-table { 3547 compatible = "operating-points-v2"; 3548 3549 opp-19200000 { 3550 opp-hz = /bits/ 64 <19200000>; 3551 required-opps = <&rpmhpd_opp_min_svs>; 3552 }; 3553 3554 opp-50000000 { 3555 opp-hz = /bits/ 64 <50000000>; 3556 required-opps = <&rpmhpd_opp_low_svs>; 3557 }; 3558 3559 opp-100000000 { 3560 opp-hz = /bits/ 64 <100000000>; 3561 required-opps = <&rpmhpd_opp_svs>; 3562 }; 3563 3564 opp-202000000 { 3565 opp-hz = /bits/ 64 <202000000>; 3566 required-opps = <&rpmhpd_opp_svs_l1>; 3567 }; 3568 }; 3569 }; 3570 3571 dc_noc: interconnect@9160000 { 3572 compatible = "qcom,sm8150-dc-noc"; 3573 reg = <0 0x09160000 0 0x3200>; 3574 #interconnect-cells = <2>; 3575 qcom,bcm-voters = <&apps_bcm_voter>; 3576 }; 3577 3578 gem_noc: interconnect@9680000 { 3579 compatible = "qcom,sm8150-gem-noc"; 3580 reg = <0 0x09680000 0 0x3e200>; 3581 #interconnect-cells = <2>; 3582 qcom,bcm-voters = <&apps_bcm_voter>; 3583 }; 3584 3585 usb_1: usb@a6f8800 { 3586 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3587 reg = <0 0x0a6f8800 0 0x400>; 3588 status = "disabled"; 3589 #address-cells = <2>; 3590 #size-cells = <2>; 3591 ranges; 3592 dma-ranges; 3593 3594 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3595 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3596 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3597 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3598 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3599 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3600 clock-names = "cfg_noc", 3601 "core", 3602 "iface", 3603 "sleep", 3604 "mock_utmi", 3605 "xo"; 3606 3607 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3608 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3609 assigned-clock-rates = <19200000>, <200000000>; 3610 3611 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 3612 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3613 <&pdc 9 IRQ_TYPE_EDGE_BOTH>, 3614 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 3615 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; 3616 interrupt-names = "pwr_event", 3617 "hs_phy_irq", 3618 "dp_hs_phy_irq", 3619 "dm_hs_phy_irq", 3620 "ss_phy_irq"; 3621 3622 power-domains = <&gcc USB30_PRIM_GDSC>; 3623 3624 resets = <&gcc GCC_USB30_PRIM_BCR>; 3625 3626 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, 3627 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 3628 interconnect-names = "usb-ddr", "apps-usb"; 3629 3630 usb_1_dwc3: usb@a600000 { 3631 compatible = "snps,dwc3"; 3632 reg = <0 0x0a600000 0 0xcd00>; 3633 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3634 iommus = <&apps_smmu 0x140 0>; 3635 snps,dis_u2_susphy_quirk; 3636 snps,dis_enblslpm_quirk; 3637 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 3638 phy-names = "usb2-phy", "usb3-phy"; 3639 3640 ports { 3641 #address-cells = <1>; 3642 #size-cells = <0>; 3643 3644 port@0 { 3645 reg = <0>; 3646 3647 usb_1_dwc3_hs: endpoint { 3648 }; 3649 }; 3650 3651 port@1 { 3652 reg = <1>; 3653 3654 usb_1_dwc3_ss: endpoint { 3655 }; 3656 }; 3657 }; 3658 }; 3659 }; 3660 3661 usb_2: usb@a8f8800 { 3662 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3663 reg = <0 0x0a8f8800 0 0x400>; 3664 status = "disabled"; 3665 #address-cells = <2>; 3666 #size-cells = <2>; 3667 ranges; 3668 dma-ranges; 3669 3670 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3671 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3672 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3673 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3674 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3675 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3676 clock-names = "cfg_noc", 3677 "core", 3678 "iface", 3679 "sleep", 3680 "mock_utmi", 3681 "xo"; 3682 3683 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3684 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3685 assigned-clock-rates = <19200000>, <200000000>; 3686 3687 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 3688 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3689 <&pdc 11 IRQ_TYPE_EDGE_BOTH>, 3690 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 3691 <&pdc 7 IRQ_TYPE_LEVEL_HIGH>; 3692 interrupt-names = "pwr_event", 3693 "hs_phy_irq", 3694 "dp_hs_phy_irq", 3695 "dm_hs_phy_irq", 3696 "ss_phy_irq"; 3697 3698 power-domains = <&gcc USB30_SEC_GDSC>; 3699 3700 resets = <&gcc GCC_USB30_SEC_BCR>; 3701 3702 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, 3703 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; 3704 interconnect-names = "usb-ddr", "apps-usb"; 3705 3706 usb_2_dwc3: usb@a800000 { 3707 compatible = "snps,dwc3"; 3708 reg = <0 0x0a800000 0 0xcd00>; 3709 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3710 iommus = <&apps_smmu 0x160 0>; 3711 snps,dis_u2_susphy_quirk; 3712 snps,dis_enblslpm_quirk; 3713 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>; 3714 phy-names = "usb2-phy", "usb3-phy"; 3715 }; 3716 }; 3717 3718 camnoc_virt: interconnect@ac00000 { 3719 compatible = "qcom,sm8150-camnoc-virt"; 3720 reg = <0 0x0ac00000 0 0x1000>; 3721 #interconnect-cells = <2>; 3722 qcom,bcm-voters = <&apps_bcm_voter>; 3723 }; 3724 3725 mdss: display-subsystem@ae00000 { 3726 compatible = "qcom,sm8150-mdss"; 3727 reg = <0 0x0ae00000 0 0x1000>; 3728 reg-names = "mdss"; 3729 3730 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>, 3731 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>; 3732 interconnect-names = "mdp0-mem", "mdp1-mem"; 3733 3734 power-domains = <&dispcc MDSS_GDSC>; 3735 3736 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3737 <&gcc GCC_DISP_HF_AXI_CLK>, 3738 <&gcc GCC_DISP_SF_AXI_CLK>, 3739 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3740 clock-names = "iface", "bus", "nrt_bus", "core"; 3741 3742 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3743 interrupt-controller; 3744 #interrupt-cells = <1>; 3745 3746 iommus = <&apps_smmu 0x800 0x420>; 3747 3748 status = "disabled"; 3749 3750 #address-cells = <2>; 3751 #size-cells = <2>; 3752 ranges; 3753 3754 mdss_mdp: display-controller@ae01000 { 3755 compatible = "qcom,sm8150-dpu"; 3756 reg = <0 0x0ae01000 0 0x8f000>, 3757 <0 0x0aeb0000 0 0x2008>; 3758 reg-names = "mdp", "vbif"; 3759 3760 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3761 <&gcc GCC_DISP_HF_AXI_CLK>, 3762 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3763 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3764 clock-names = "iface", "bus", "core", "vsync"; 3765 3766 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3767 assigned-clock-rates = <19200000>; 3768 3769 operating-points-v2 = <&mdp_opp_table>; 3770 power-domains = <&rpmhpd SM8150_MMCX>; 3771 3772 interrupt-parent = <&mdss>; 3773 interrupts = <0>; 3774 3775 ports { 3776 #address-cells = <1>; 3777 #size-cells = <0>; 3778 3779 port@0 { 3780 reg = <0>; 3781 dpu_intf1_out: endpoint { 3782 remote-endpoint = <&mdss_dsi0_in>; 3783 }; 3784 }; 3785 3786 port@1 { 3787 reg = <1>; 3788 dpu_intf2_out: endpoint { 3789 remote-endpoint = <&mdss_dsi1_in>; 3790 }; 3791 }; 3792 3793 port@2 { 3794 reg = <2>; 3795 dpu_intf0_out: endpoint { 3796 remote-endpoint = <&mdss_dp_in>; 3797 }; 3798 }; 3799 }; 3800 3801 mdp_opp_table: opp-table { 3802 compatible = "operating-points-v2"; 3803 3804 opp-171428571 { 3805 opp-hz = /bits/ 64 <171428571>; 3806 required-opps = <&rpmhpd_opp_low_svs>; 3807 }; 3808 3809 opp-300000000 { 3810 opp-hz = /bits/ 64 <300000000>; 3811 required-opps = <&rpmhpd_opp_svs>; 3812 }; 3813 3814 opp-345000000 { 3815 opp-hz = /bits/ 64 <345000000>; 3816 required-opps = <&rpmhpd_opp_svs_l1>; 3817 }; 3818 3819 opp-460000000 { 3820 opp-hz = /bits/ 64 <460000000>; 3821 required-opps = <&rpmhpd_opp_nom>; 3822 }; 3823 }; 3824 }; 3825 3826 mdss_dp: displayport-controller@ae90000 { 3827 compatible = "qcom,sm8150-dp", "qcom,sm8350-dp"; 3828 reg = <0 0xae90000 0 0x200>, 3829 <0 0xae90200 0 0x200>, 3830 <0 0xae90400 0 0x600>, 3831 <0 0x0ae90a00 0 0x600>, 3832 <0 0x0ae91000 0 0x600>; 3833 3834 interrupt-parent = <&mdss>; 3835 interrupts = <12>; 3836 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3837 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3838 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3839 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3840 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3841 clock-names = "core_iface", 3842 "core_aux", 3843 "ctrl_link", 3844 "ctrl_link_iface", 3845 "stream_pixel"; 3846 3847 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3848 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3849 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3850 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3851 3852 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 3853 phy-names = "dp"; 3854 3855 #sound-dai-cells = <0>; 3856 3857 operating-points-v2 = <&dp_opp_table>; 3858 power-domains = <&rpmhpd SM8250_MMCX>; 3859 3860 status = "disabled"; 3861 3862 ports { 3863 #address-cells = <1>; 3864 #size-cells = <0>; 3865 3866 port@0 { 3867 reg = <0>; 3868 mdss_dp_in: endpoint { 3869 remote-endpoint = <&dpu_intf0_out>; 3870 }; 3871 }; 3872 3873 port@1 { 3874 reg = <1>; 3875 3876 mdss_dp_out: endpoint { 3877 }; 3878 }; 3879 }; 3880 3881 dp_opp_table: opp-table { 3882 compatible = "operating-points-v2"; 3883 3884 opp-160000000 { 3885 opp-hz = /bits/ 64 <160000000>; 3886 required-opps = <&rpmhpd_opp_low_svs>; 3887 }; 3888 3889 opp-270000000 { 3890 opp-hz = /bits/ 64 <270000000>; 3891 required-opps = <&rpmhpd_opp_svs>; 3892 }; 3893 3894 opp-540000000 { 3895 opp-hz = /bits/ 64 <540000000>; 3896 required-opps = <&rpmhpd_opp_svs_l1>; 3897 }; 3898 3899 opp-810000000 { 3900 opp-hz = /bits/ 64 <810000000>; 3901 required-opps = <&rpmhpd_opp_nom>; 3902 }; 3903 }; 3904 }; 3905 3906 mdss_dsi0: dsi@ae94000 { 3907 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3908 reg = <0 0x0ae94000 0 0x400>; 3909 reg-names = "dsi_ctrl"; 3910 3911 interrupt-parent = <&mdss>; 3912 interrupts = <4>; 3913 3914 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3915 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3916 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3917 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3918 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3919 <&gcc GCC_DISP_HF_AXI_CLK>; 3920 clock-names = "byte", 3921 "byte_intf", 3922 "pixel", 3923 "core", 3924 "iface", 3925 "bus"; 3926 3927 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 3928 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3929 assigned-clock-parents = <&mdss_dsi0_phy 0>, 3930 <&mdss_dsi0_phy 1>; 3931 3932 operating-points-v2 = <&dsi_opp_table>; 3933 power-domains = <&rpmhpd SM8150_MMCX>; 3934 3935 phys = <&mdss_dsi0_phy>; 3936 3937 status = "disabled"; 3938 3939 #address-cells = <1>; 3940 #size-cells = <0>; 3941 3942 ports { 3943 #address-cells = <1>; 3944 #size-cells = <0>; 3945 3946 port@0 { 3947 reg = <0>; 3948 mdss_dsi0_in: endpoint { 3949 remote-endpoint = <&dpu_intf1_out>; 3950 }; 3951 }; 3952 3953 port@1 { 3954 reg = <1>; 3955 mdss_dsi0_out: endpoint { 3956 }; 3957 }; 3958 }; 3959 3960 dsi_opp_table: opp-table { 3961 compatible = "operating-points-v2"; 3962 3963 opp-187500000 { 3964 opp-hz = /bits/ 64 <187500000>; 3965 required-opps = <&rpmhpd_opp_low_svs>; 3966 }; 3967 3968 opp-300000000 { 3969 opp-hz = /bits/ 64 <300000000>; 3970 required-opps = <&rpmhpd_opp_svs>; 3971 }; 3972 3973 opp-358000000 { 3974 opp-hz = /bits/ 64 <358000000>; 3975 required-opps = <&rpmhpd_opp_svs_l1>; 3976 }; 3977 }; 3978 }; 3979 3980 mdss_dsi0_phy: phy@ae94400 { 3981 compatible = "qcom,dsi-phy-7nm-8150"; 3982 reg = <0 0x0ae94400 0 0x200>, 3983 <0 0x0ae94600 0 0x280>, 3984 <0 0x0ae94900 0 0x260>; 3985 reg-names = "dsi_phy", 3986 "dsi_phy_lane", 3987 "dsi_pll"; 3988 3989 #clock-cells = <1>; 3990 #phy-cells = <0>; 3991 3992 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3993 <&rpmhcc RPMH_CXO_CLK>; 3994 clock-names = "iface", "ref"; 3995 3996 status = "disabled"; 3997 }; 3998 3999 mdss_dsi1: dsi@ae96000 { 4000 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 4001 reg = <0 0x0ae96000 0 0x400>; 4002 reg-names = "dsi_ctrl"; 4003 4004 interrupt-parent = <&mdss>; 4005 interrupts = <5>; 4006 4007 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 4008 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 4009 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 4010 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 4011 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4012 <&gcc GCC_DISP_HF_AXI_CLK>; 4013 clock-names = "byte", 4014 "byte_intf", 4015 "pixel", 4016 "core", 4017 "iface", 4018 "bus"; 4019 4020 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 4021 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 4022 assigned-clock-parents = <&mdss_dsi1_phy 0>, 4023 <&mdss_dsi1_phy 1>; 4024 4025 operating-points-v2 = <&dsi_opp_table>; 4026 power-domains = <&rpmhpd SM8150_MMCX>; 4027 4028 phys = <&mdss_dsi1_phy>; 4029 4030 status = "disabled"; 4031 4032 #address-cells = <1>; 4033 #size-cells = <0>; 4034 4035 ports { 4036 #address-cells = <1>; 4037 #size-cells = <0>; 4038 4039 port@0 { 4040 reg = <0>; 4041 mdss_dsi1_in: endpoint { 4042 remote-endpoint = <&dpu_intf2_out>; 4043 }; 4044 }; 4045 4046 port@1 { 4047 reg = <1>; 4048 mdss_dsi1_out: endpoint { 4049 }; 4050 }; 4051 }; 4052 }; 4053 4054 mdss_dsi1_phy: phy@ae96400 { 4055 compatible = "qcom,dsi-phy-7nm-8150"; 4056 reg = <0 0x0ae96400 0 0x200>, 4057 <0 0x0ae96600 0 0x280>, 4058 <0 0x0ae96900 0 0x260>; 4059 reg-names = "dsi_phy", 4060 "dsi_phy_lane", 4061 "dsi_pll"; 4062 4063 #clock-cells = <1>; 4064 #phy-cells = <0>; 4065 4066 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4067 <&rpmhcc RPMH_CXO_CLK>; 4068 clock-names = "iface", "ref"; 4069 4070 status = "disabled"; 4071 }; 4072 }; 4073 4074 dispcc: clock-controller@af00000 { 4075 compatible = "qcom,sm8150-dispcc"; 4076 reg = <0 0x0af00000 0 0x10000>; 4077 clocks = <&rpmhcc RPMH_CXO_CLK>, 4078 <&mdss_dsi0_phy 0>, 4079 <&mdss_dsi0_phy 1>, 4080 <&mdss_dsi1_phy 0>, 4081 <&mdss_dsi1_phy 1>, 4082 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4083 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4084 clock-names = "bi_tcxo", 4085 "dsi0_phy_pll_out_byteclk", 4086 "dsi0_phy_pll_out_dsiclk", 4087 "dsi1_phy_pll_out_byteclk", 4088 "dsi1_phy_pll_out_dsiclk", 4089 "dp_phy_pll_link_clk", 4090 "dp_phy_pll_vco_div_clk"; 4091 power-domains = <&rpmhpd SM8150_MMCX>; 4092 required-opps = <&rpmhpd_opp_low_svs>; 4093 #clock-cells = <1>; 4094 #reset-cells = <1>; 4095 #power-domain-cells = <1>; 4096 }; 4097 4098 pdc: interrupt-controller@b220000 { 4099 compatible = "qcom,sm8150-pdc", "qcom,pdc"; 4100 reg = <0 0x0b220000 0 0x30000>; 4101 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 4102 <125 63 1>; 4103 #interrupt-cells = <2>; 4104 interrupt-parent = <&intc>; 4105 interrupt-controller; 4106 }; 4107 4108 aoss_qmp: power-management@c300000 { 4109 compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp"; 4110 reg = <0x0 0x0c300000 0x0 0x400>; 4111 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 4112 mboxes = <&apss_shared 0>; 4113 4114 #clock-cells = <0>; 4115 }; 4116 4117 sram@c3f0000 { 4118 compatible = "qcom,rpmh-stats"; 4119 reg = <0 0x0c3f0000 0 0x400>; 4120 }; 4121 4122 tsens0: thermal-sensor@c263000 { 4123 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 4124 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4125 <0 0x0c222000 0 0x1ff>; /* SROT */ 4126 #qcom,sensors = <16>; 4127 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4128 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4129 interrupt-names = "uplow", "critical"; 4130 #thermal-sensor-cells = <1>; 4131 }; 4132 4133 tsens1: thermal-sensor@c265000 { 4134 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 4135 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4136 <0 0x0c223000 0 0x1ff>; /* SROT */ 4137 #qcom,sensors = <8>; 4138 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4139 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4140 interrupt-names = "uplow", "critical"; 4141 #thermal-sensor-cells = <1>; 4142 }; 4143 4144 spmi_bus: spmi@c440000 { 4145 compatible = "qcom,spmi-pmic-arb"; 4146 reg = <0x0 0x0c440000 0x0 0x0001100>, 4147 <0x0 0x0c600000 0x0 0x2000000>, 4148 <0x0 0x0e600000 0x0 0x0100000>, 4149 <0x0 0x0e700000 0x0 0x00a0000>, 4150 <0x0 0x0c40a000 0x0 0x0026000>; 4151 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4152 interrupt-names = "periph_irq"; 4153 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 4154 qcom,ee = <0>; 4155 qcom,channel = <0>; 4156 #address-cells = <2>; 4157 #size-cells = <0>; 4158 interrupt-controller; 4159 #interrupt-cells = <4>; 4160 }; 4161 4162 apps_smmu: iommu@15000000 { 4163 compatible = "qcom,sm8150-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 4164 reg = <0 0x15000000 0 0x100000>; 4165 #iommu-cells = <2>; 4166 #global-interrupts = <1>; 4167 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4168 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4169 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4170 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4171 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4172 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4173 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4174 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4175 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4176 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4177 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4178 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4179 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4180 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4181 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4182 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4183 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4184 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4185 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4186 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4187 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4188 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4189 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4190 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4191 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4192 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4193 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4194 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4195 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4196 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4197 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4198 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4199 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4200 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4201 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4202 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4203 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4204 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4205 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4206 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4207 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4208 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4209 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4210 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4211 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4212 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4213 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4214 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4215 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4216 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4217 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4218 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4219 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4220 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4221 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4222 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4223 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4224 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4225 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4226 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4227 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4228 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4229 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4230 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4231 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4232 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4233 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4234 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4235 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4236 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4237 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4238 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4239 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4240 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4241 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4242 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4243 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4244 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4245 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4246 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4247 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 4248 }; 4249 4250 remoteproc_adsp: remoteproc@17300000 { 4251 compatible = "qcom,sm8150-adsp-pas"; 4252 reg = <0x0 0x17300000 0x0 0x4040>; 4253 4254 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 4255 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4256 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 4257 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 4258 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 4259 interrupt-names = "wdog", "fatal", "ready", 4260 "handover", "stop-ack"; 4261 4262 clocks = <&rpmhcc RPMH_CXO_CLK>; 4263 clock-names = "xo"; 4264 4265 power-domains = <&rpmhpd SM8150_CX>; 4266 4267 memory-region = <&adsp_mem>; 4268 4269 qcom,qmp = <&aoss_qmp>; 4270 4271 qcom,smem-states = <&adsp_smp2p_out 0>; 4272 qcom,smem-state-names = "stop"; 4273 4274 status = "disabled"; 4275 4276 glink-edge { 4277 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 4278 label = "lpass"; 4279 qcom,remote-pid = <2>; 4280 mboxes = <&apss_shared 8>; 4281 4282 fastrpc { 4283 compatible = "qcom,fastrpc"; 4284 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4285 label = "adsp"; 4286 qcom,non-secure-domain; 4287 #address-cells = <1>; 4288 #size-cells = <0>; 4289 4290 compute-cb@3 { 4291 compatible = "qcom,fastrpc-compute-cb"; 4292 reg = <3>; 4293 iommus = <&apps_smmu 0x1b23 0x0>; 4294 }; 4295 4296 compute-cb@4 { 4297 compatible = "qcom,fastrpc-compute-cb"; 4298 reg = <4>; 4299 iommus = <&apps_smmu 0x1b24 0x0>; 4300 }; 4301 4302 compute-cb@5 { 4303 compatible = "qcom,fastrpc-compute-cb"; 4304 reg = <5>; 4305 iommus = <&apps_smmu 0x1b25 0x0>; 4306 }; 4307 }; 4308 }; 4309 }; 4310 4311 intc: interrupt-controller@17a00000 { 4312 compatible = "arm,gic-v3"; 4313 interrupt-controller; 4314 #interrupt-cells = <3>; 4315 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4316 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4317 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4318 }; 4319 4320 apss_shared: mailbox@17c00000 { 4321 compatible = "qcom,sm8150-apss-shared", 4322 "qcom,sdm845-apss-shared"; 4323 reg = <0x0 0x17c00000 0x0 0x1000>; 4324 #mbox-cells = <1>; 4325 }; 4326 4327 watchdog@17c10000 { 4328 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; 4329 reg = <0 0x17c10000 0 0x1000>; 4330 clocks = <&sleep_clk>; 4331 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 4332 }; 4333 4334 timer@17c20000 { 4335 #address-cells = <1>; 4336 #size-cells = <1>; 4337 ranges = <0 0 0 0x20000000>; 4338 compatible = "arm,armv7-timer-mem"; 4339 reg = <0x0 0x17c20000 0x0 0x1000>; 4340 clock-frequency = <19200000>; 4341 4342 frame@17c21000 { 4343 frame-number = <0>; 4344 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4345 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4346 reg = <0x17c21000 0x1000>, 4347 <0x17c22000 0x1000>; 4348 }; 4349 4350 frame@17c23000 { 4351 frame-number = <1>; 4352 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4353 reg = <0x17c23000 0x1000>; 4354 status = "disabled"; 4355 }; 4356 4357 frame@17c25000 { 4358 frame-number = <2>; 4359 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4360 reg = <0x17c25000 0x1000>; 4361 status = "disabled"; 4362 }; 4363 4364 frame@17c27000 { 4365 frame-number = <3>; 4366 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4367 reg = <0x17c26000 0x1000>; 4368 status = "disabled"; 4369 }; 4370 4371 frame@17c29000 { 4372 frame-number = <4>; 4373 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4374 reg = <0x17c29000 0x1000>; 4375 status = "disabled"; 4376 }; 4377 4378 frame@17c2b000 { 4379 frame-number = <5>; 4380 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4381 reg = <0x17c2b000 0x1000>; 4382 status = "disabled"; 4383 }; 4384 4385 frame@17c2d000 { 4386 frame-number = <6>; 4387 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4388 reg = <0x17c2d000 0x1000>; 4389 status = "disabled"; 4390 }; 4391 }; 4392 4393 apps_rsc: rsc@18200000 { 4394 label = "apps_rsc"; 4395 compatible = "qcom,rpmh-rsc"; 4396 reg = <0x0 0x18200000 0x0 0x10000>, 4397 <0x0 0x18210000 0x0 0x10000>, 4398 <0x0 0x18220000 0x0 0x10000>; 4399 reg-names = "drv-0", "drv-1", "drv-2"; 4400 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4401 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4402 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4403 qcom,tcs-offset = <0xd00>; 4404 qcom,drv-id = <2>; 4405 qcom,tcs-config = <ACTIVE_TCS 2>, 4406 <SLEEP_TCS 3>, 4407 <WAKE_TCS 3>, 4408 <CONTROL_TCS 1>; 4409 power-domains = <&CLUSTER_PD>; 4410 4411 rpmhcc: clock-controller { 4412 compatible = "qcom,sm8150-rpmh-clk"; 4413 #clock-cells = <1>; 4414 clock-names = "xo"; 4415 clocks = <&xo_board>; 4416 }; 4417 4418 rpmhpd: power-controller { 4419 compatible = "qcom,sm8150-rpmhpd"; 4420 #power-domain-cells = <1>; 4421 operating-points-v2 = <&rpmhpd_opp_table>; 4422 4423 rpmhpd_opp_table: opp-table { 4424 compatible = "operating-points-v2"; 4425 4426 rpmhpd_opp_ret: opp1 { 4427 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4428 }; 4429 4430 rpmhpd_opp_min_svs: opp2 { 4431 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4432 }; 4433 4434 rpmhpd_opp_low_svs: opp3 { 4435 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4436 }; 4437 4438 rpmhpd_opp_svs: opp4 { 4439 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4440 }; 4441 4442 rpmhpd_opp_svs_l1: opp5 { 4443 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4444 }; 4445 4446 rpmhpd_opp_svs_l2: opp6 { 4447 opp-level = <224>; 4448 }; 4449 4450 rpmhpd_opp_nom: opp7 { 4451 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4452 }; 4453 4454 rpmhpd_opp_nom_l1: opp8 { 4455 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4456 }; 4457 4458 rpmhpd_opp_nom_l2: opp9 { 4459 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4460 }; 4461 4462 rpmhpd_opp_turbo: opp10 { 4463 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4464 }; 4465 4466 rpmhpd_opp_turbo_l1: opp11 { 4467 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4468 }; 4469 }; 4470 }; 4471 4472 apps_bcm_voter: bcm-voter { 4473 compatible = "qcom,bcm-voter"; 4474 }; 4475 }; 4476 4477 osm_l3: interconnect@18321000 { 4478 compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3"; 4479 reg = <0 0x18321000 0 0x1400>; 4480 4481 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4482 clock-names = "xo", "alternate"; 4483 4484 #interconnect-cells = <1>; 4485 }; 4486 4487 cpufreq_hw: cpufreq@18323000 { 4488 compatible = "qcom,sm8150-cpufreq-hw", "qcom,cpufreq-hw"; 4489 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, 4490 <0 0x18327800 0 0x1400>; 4491 reg-names = "freq-domain0", "freq-domain1", 4492 "freq-domain2"; 4493 4494 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4495 clock-names = "xo", "alternate"; 4496 4497 #freq-domain-cells = <1>; 4498 #clock-cells = <1>; 4499 }; 4500 4501 lmh_cluster1: lmh@18350800 { 4502 compatible = "qcom,sm8150-lmh"; 4503 reg = <0 0x18350800 0 0x400>; 4504 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 4505 cpus = <&CPU4>; 4506 qcom,lmh-temp-arm-millicelsius = <60000>; 4507 qcom,lmh-temp-low-millicelsius = <84500>; 4508 qcom,lmh-temp-high-millicelsius = <85000>; 4509 interrupt-controller; 4510 #interrupt-cells = <1>; 4511 }; 4512 4513 lmh_cluster0: lmh@18358800 { 4514 compatible = "qcom,sm8150-lmh"; 4515 reg = <0 0x18358800 0 0x400>; 4516 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 4517 cpus = <&CPU0>; 4518 qcom,lmh-temp-arm-millicelsius = <60000>; 4519 qcom,lmh-temp-low-millicelsius = <84500>; 4520 qcom,lmh-temp-high-millicelsius = <85000>; 4521 interrupt-controller; 4522 #interrupt-cells = <1>; 4523 }; 4524 4525 wifi: wifi@18800000 { 4526 compatible = "qcom,wcn3990-wifi"; 4527 reg = <0 0x18800000 0 0x800000>; 4528 reg-names = "membase"; 4529 memory-region = <&wlan_mem>; 4530 clock-names = "cxo_ref_clk_pin", "qdss"; 4531 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; 4532 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 4533 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 4534 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 4535 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 4536 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4537 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4538 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 4539 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4540 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4541 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4542 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4543 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 4544 iommus = <&apps_smmu 0x0640 0x1>; 4545 status = "disabled"; 4546 }; 4547 }; 4548 4549 timer { 4550 compatible = "arm,armv8-timer"; 4551 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4552 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4553 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4554 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4555 }; 4556 4557 thermal-zones { 4558 cpu0-thermal { 4559 polling-delay-passive = <250>; 4560 polling-delay = <1000>; 4561 4562 thermal-sensors = <&tsens0 1>; 4563 4564 trips { 4565 cpu0_alert0: trip-point0 { 4566 temperature = <90000>; 4567 hysteresis = <2000>; 4568 type = "passive"; 4569 }; 4570 4571 cpu0_alert1: trip-point1 { 4572 temperature = <95000>; 4573 hysteresis = <2000>; 4574 type = "passive"; 4575 }; 4576 4577 cpu0_crit: cpu-crit { 4578 temperature = <110000>; 4579 hysteresis = <1000>; 4580 type = "critical"; 4581 }; 4582 }; 4583 4584 cooling-maps { 4585 map0 { 4586 trip = <&cpu0_alert0>; 4587 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4588 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4589 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4590 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4591 }; 4592 map1 { 4593 trip = <&cpu0_alert1>; 4594 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4595 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4596 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4597 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4598 }; 4599 }; 4600 }; 4601 4602 cpu1-thermal { 4603 polling-delay-passive = <250>; 4604 polling-delay = <1000>; 4605 4606 thermal-sensors = <&tsens0 2>; 4607 4608 trips { 4609 cpu1_alert0: trip-point0 { 4610 temperature = <90000>; 4611 hysteresis = <2000>; 4612 type = "passive"; 4613 }; 4614 4615 cpu1_alert1: trip-point1 { 4616 temperature = <95000>; 4617 hysteresis = <2000>; 4618 type = "passive"; 4619 }; 4620 4621 cpu1_crit: cpu-crit { 4622 temperature = <110000>; 4623 hysteresis = <1000>; 4624 type = "critical"; 4625 }; 4626 }; 4627 4628 cooling-maps { 4629 map0 { 4630 trip = <&cpu1_alert0>; 4631 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4632 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4633 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4634 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4635 }; 4636 map1 { 4637 trip = <&cpu1_alert1>; 4638 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4639 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4640 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4641 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4642 }; 4643 }; 4644 }; 4645 4646 cpu2-thermal { 4647 polling-delay-passive = <250>; 4648 polling-delay = <1000>; 4649 4650 thermal-sensors = <&tsens0 3>; 4651 4652 trips { 4653 cpu2_alert0: trip-point0 { 4654 temperature = <90000>; 4655 hysteresis = <2000>; 4656 type = "passive"; 4657 }; 4658 4659 cpu2_alert1: trip-point1 { 4660 temperature = <95000>; 4661 hysteresis = <2000>; 4662 type = "passive"; 4663 }; 4664 4665 cpu2_crit: cpu-crit { 4666 temperature = <110000>; 4667 hysteresis = <1000>; 4668 type = "critical"; 4669 }; 4670 }; 4671 4672 cooling-maps { 4673 map0 { 4674 trip = <&cpu2_alert0>; 4675 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4676 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4677 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4678 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4679 }; 4680 map1 { 4681 trip = <&cpu2_alert1>; 4682 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4683 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4684 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4685 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4686 }; 4687 }; 4688 }; 4689 4690 cpu3-thermal { 4691 polling-delay-passive = <250>; 4692 polling-delay = <1000>; 4693 4694 thermal-sensors = <&tsens0 4>; 4695 4696 trips { 4697 cpu3_alert0: trip-point0 { 4698 temperature = <90000>; 4699 hysteresis = <2000>; 4700 type = "passive"; 4701 }; 4702 4703 cpu3_alert1: trip-point1 { 4704 temperature = <95000>; 4705 hysteresis = <2000>; 4706 type = "passive"; 4707 }; 4708 4709 cpu3_crit: cpu-crit { 4710 temperature = <110000>; 4711 hysteresis = <1000>; 4712 type = "critical"; 4713 }; 4714 }; 4715 4716 cooling-maps { 4717 map0 { 4718 trip = <&cpu3_alert0>; 4719 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4720 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4721 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4722 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4723 }; 4724 map1 { 4725 trip = <&cpu3_alert1>; 4726 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4727 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4728 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4729 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4730 }; 4731 }; 4732 }; 4733 4734 cpu4-top-thermal { 4735 polling-delay-passive = <250>; 4736 polling-delay = <1000>; 4737 4738 thermal-sensors = <&tsens0 7>; 4739 4740 trips { 4741 cpu4_top_alert0: trip-point0 { 4742 temperature = <90000>; 4743 hysteresis = <2000>; 4744 type = "passive"; 4745 }; 4746 4747 cpu4_top_alert1: trip-point1 { 4748 temperature = <95000>; 4749 hysteresis = <2000>; 4750 type = "passive"; 4751 }; 4752 4753 cpu4_top_crit: cpu-crit { 4754 temperature = <110000>; 4755 hysteresis = <1000>; 4756 type = "critical"; 4757 }; 4758 }; 4759 4760 cooling-maps { 4761 map0 { 4762 trip = <&cpu4_top_alert0>; 4763 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4764 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4765 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4766 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4767 }; 4768 map1 { 4769 trip = <&cpu4_top_alert1>; 4770 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4771 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4772 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4773 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4774 }; 4775 }; 4776 }; 4777 4778 cpu5-top-thermal { 4779 polling-delay-passive = <250>; 4780 polling-delay = <1000>; 4781 4782 thermal-sensors = <&tsens0 8>; 4783 4784 trips { 4785 cpu5_top_alert0: trip-point0 { 4786 temperature = <90000>; 4787 hysteresis = <2000>; 4788 type = "passive"; 4789 }; 4790 4791 cpu5_top_alert1: trip-point1 { 4792 temperature = <95000>; 4793 hysteresis = <2000>; 4794 type = "passive"; 4795 }; 4796 4797 cpu5_top_crit: cpu-crit { 4798 temperature = <110000>; 4799 hysteresis = <1000>; 4800 type = "critical"; 4801 }; 4802 }; 4803 4804 cooling-maps { 4805 map0 { 4806 trip = <&cpu5_top_alert0>; 4807 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4808 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4809 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4810 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4811 }; 4812 map1 { 4813 trip = <&cpu5_top_alert1>; 4814 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4815 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4816 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4817 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4818 }; 4819 }; 4820 }; 4821 4822 cpu6-top-thermal { 4823 polling-delay-passive = <250>; 4824 polling-delay = <1000>; 4825 4826 thermal-sensors = <&tsens0 9>; 4827 4828 trips { 4829 cpu6_top_alert0: trip-point0 { 4830 temperature = <90000>; 4831 hysteresis = <2000>; 4832 type = "passive"; 4833 }; 4834 4835 cpu6_top_alert1: trip-point1 { 4836 temperature = <95000>; 4837 hysteresis = <2000>; 4838 type = "passive"; 4839 }; 4840 4841 cpu6_top_crit: cpu-crit { 4842 temperature = <110000>; 4843 hysteresis = <1000>; 4844 type = "critical"; 4845 }; 4846 }; 4847 4848 cooling-maps { 4849 map0 { 4850 trip = <&cpu6_top_alert0>; 4851 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4852 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4853 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4854 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4855 }; 4856 map1 { 4857 trip = <&cpu6_top_alert1>; 4858 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4859 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4860 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4861 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4862 }; 4863 }; 4864 }; 4865 4866 cpu7-top-thermal { 4867 polling-delay-passive = <250>; 4868 polling-delay = <1000>; 4869 4870 thermal-sensors = <&tsens0 10>; 4871 4872 trips { 4873 cpu7_top_alert0: trip-point0 { 4874 temperature = <90000>; 4875 hysteresis = <2000>; 4876 type = "passive"; 4877 }; 4878 4879 cpu7_top_alert1: trip-point1 { 4880 temperature = <95000>; 4881 hysteresis = <2000>; 4882 type = "passive"; 4883 }; 4884 4885 cpu7_top_crit: cpu-crit { 4886 temperature = <110000>; 4887 hysteresis = <1000>; 4888 type = "critical"; 4889 }; 4890 }; 4891 4892 cooling-maps { 4893 map0 { 4894 trip = <&cpu7_top_alert0>; 4895 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4896 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4897 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4898 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4899 }; 4900 map1 { 4901 trip = <&cpu7_top_alert1>; 4902 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4903 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4904 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4905 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4906 }; 4907 }; 4908 }; 4909 4910 cpu4-bottom-thermal { 4911 polling-delay-passive = <250>; 4912 polling-delay = <1000>; 4913 4914 thermal-sensors = <&tsens0 11>; 4915 4916 trips { 4917 cpu4_bottom_alert0: trip-point0 { 4918 temperature = <90000>; 4919 hysteresis = <2000>; 4920 type = "passive"; 4921 }; 4922 4923 cpu4_bottom_alert1: trip-point1 { 4924 temperature = <95000>; 4925 hysteresis = <2000>; 4926 type = "passive"; 4927 }; 4928 4929 cpu4_bottom_crit: cpu-crit { 4930 temperature = <110000>; 4931 hysteresis = <1000>; 4932 type = "critical"; 4933 }; 4934 }; 4935 4936 cooling-maps { 4937 map0 { 4938 trip = <&cpu4_bottom_alert0>; 4939 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4940 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4941 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4942 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4943 }; 4944 map1 { 4945 trip = <&cpu4_bottom_alert1>; 4946 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4947 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4948 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4949 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4950 }; 4951 }; 4952 }; 4953 4954 cpu5-bottom-thermal { 4955 polling-delay-passive = <250>; 4956 polling-delay = <1000>; 4957 4958 thermal-sensors = <&tsens0 12>; 4959 4960 trips { 4961 cpu5_bottom_alert0: trip-point0 { 4962 temperature = <90000>; 4963 hysteresis = <2000>; 4964 type = "passive"; 4965 }; 4966 4967 cpu5_bottom_alert1: trip-point1 { 4968 temperature = <95000>; 4969 hysteresis = <2000>; 4970 type = "passive"; 4971 }; 4972 4973 cpu5_bottom_crit: cpu-crit { 4974 temperature = <110000>; 4975 hysteresis = <1000>; 4976 type = "critical"; 4977 }; 4978 }; 4979 4980 cooling-maps { 4981 map0 { 4982 trip = <&cpu5_bottom_alert0>; 4983 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4984 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4985 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4986 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4987 }; 4988 map1 { 4989 trip = <&cpu5_bottom_alert1>; 4990 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4991 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4992 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4993 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4994 }; 4995 }; 4996 }; 4997 4998 cpu6-bottom-thermal { 4999 polling-delay-passive = <250>; 5000 polling-delay = <1000>; 5001 5002 thermal-sensors = <&tsens0 13>; 5003 5004 trips { 5005 cpu6_bottom_alert0: trip-point0 { 5006 temperature = <90000>; 5007 hysteresis = <2000>; 5008 type = "passive"; 5009 }; 5010 5011 cpu6_bottom_alert1: trip-point1 { 5012 temperature = <95000>; 5013 hysteresis = <2000>; 5014 type = "passive"; 5015 }; 5016 5017 cpu6_bottom_crit: cpu-crit { 5018 temperature = <110000>; 5019 hysteresis = <1000>; 5020 type = "critical"; 5021 }; 5022 }; 5023 5024 cooling-maps { 5025 map0 { 5026 trip = <&cpu6_bottom_alert0>; 5027 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5028 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5029 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5030 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5031 }; 5032 map1 { 5033 trip = <&cpu6_bottom_alert1>; 5034 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5035 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5036 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5037 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5038 }; 5039 }; 5040 }; 5041 5042 cpu7-bottom-thermal { 5043 polling-delay-passive = <250>; 5044 polling-delay = <1000>; 5045 5046 thermal-sensors = <&tsens0 14>; 5047 5048 trips { 5049 cpu7_bottom_alert0: trip-point0 { 5050 temperature = <90000>; 5051 hysteresis = <2000>; 5052 type = "passive"; 5053 }; 5054 5055 cpu7_bottom_alert1: trip-point1 { 5056 temperature = <95000>; 5057 hysteresis = <2000>; 5058 type = "passive"; 5059 }; 5060 5061 cpu7_bottom_crit: cpu-crit { 5062 temperature = <110000>; 5063 hysteresis = <1000>; 5064 type = "critical"; 5065 }; 5066 }; 5067 5068 cooling-maps { 5069 map0 { 5070 trip = <&cpu7_bottom_alert0>; 5071 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5072 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5073 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5074 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5075 }; 5076 map1 { 5077 trip = <&cpu7_bottom_alert1>; 5078 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5079 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5080 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5081 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5082 }; 5083 }; 5084 }; 5085 5086 aoss0-thermal { 5087 polling-delay-passive = <250>; 5088 polling-delay = <1000>; 5089 5090 thermal-sensors = <&tsens0 0>; 5091 5092 trips { 5093 aoss0_alert0: trip-point0 { 5094 temperature = <90000>; 5095 hysteresis = <2000>; 5096 type = "hot"; 5097 }; 5098 }; 5099 }; 5100 5101 cluster0-thermal { 5102 polling-delay-passive = <250>; 5103 polling-delay = <1000>; 5104 5105 thermal-sensors = <&tsens0 5>; 5106 5107 trips { 5108 cluster0_alert0: trip-point0 { 5109 temperature = <90000>; 5110 hysteresis = <2000>; 5111 type = "hot"; 5112 }; 5113 cluster0_crit: cluster0-crit { 5114 temperature = <110000>; 5115 hysteresis = <2000>; 5116 type = "critical"; 5117 }; 5118 }; 5119 }; 5120 5121 cluster1-thermal { 5122 polling-delay-passive = <250>; 5123 polling-delay = <1000>; 5124 5125 thermal-sensors = <&tsens0 6>; 5126 5127 trips { 5128 cluster1_alert0: trip-point0 { 5129 temperature = <90000>; 5130 hysteresis = <2000>; 5131 type = "hot"; 5132 }; 5133 cluster1_crit: cluster1-crit { 5134 temperature = <110000>; 5135 hysteresis = <2000>; 5136 type = "critical"; 5137 }; 5138 }; 5139 }; 5140 5141 gpu-top-thermal { 5142 polling-delay-passive = <250>; 5143 polling-delay = <1000>; 5144 5145 thermal-sensors = <&tsens0 15>; 5146 5147 cooling-maps { 5148 map0 { 5149 trip = <&gpu_top_alert0>; 5150 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5151 }; 5152 }; 5153 5154 trips { 5155 gpu_top_alert0: trip-point0 { 5156 temperature = <90000>; 5157 hysteresis = <2000>; 5158 type = "hot"; 5159 }; 5160 }; 5161 }; 5162 5163 aoss1-thermal { 5164 polling-delay-passive = <250>; 5165 polling-delay = <1000>; 5166 5167 thermal-sensors = <&tsens1 0>; 5168 5169 trips { 5170 aoss1_alert0: trip-point0 { 5171 temperature = <90000>; 5172 hysteresis = <2000>; 5173 type = "hot"; 5174 }; 5175 }; 5176 }; 5177 5178 wlan-thermal { 5179 polling-delay-passive = <250>; 5180 polling-delay = <1000>; 5181 5182 thermal-sensors = <&tsens1 1>; 5183 5184 trips { 5185 wlan_alert0: trip-point0 { 5186 temperature = <90000>; 5187 hysteresis = <2000>; 5188 type = "hot"; 5189 }; 5190 }; 5191 }; 5192 5193 video-thermal { 5194 polling-delay-passive = <250>; 5195 polling-delay = <1000>; 5196 5197 thermal-sensors = <&tsens1 2>; 5198 5199 trips { 5200 video_alert0: trip-point0 { 5201 temperature = <90000>; 5202 hysteresis = <2000>; 5203 type = "hot"; 5204 }; 5205 }; 5206 }; 5207 5208 mem-thermal { 5209 polling-delay-passive = <250>; 5210 polling-delay = <1000>; 5211 5212 thermal-sensors = <&tsens1 3>; 5213 5214 trips { 5215 mem_alert0: trip-point0 { 5216 temperature = <90000>; 5217 hysteresis = <2000>; 5218 type = "hot"; 5219 }; 5220 }; 5221 }; 5222 5223 q6-hvx-thermal { 5224 polling-delay-passive = <250>; 5225 polling-delay = <1000>; 5226 5227 thermal-sensors = <&tsens1 4>; 5228 5229 trips { 5230 q6_hvx_alert0: trip-point0 { 5231 temperature = <90000>; 5232 hysteresis = <2000>; 5233 type = "hot"; 5234 }; 5235 }; 5236 }; 5237 5238 camera-thermal { 5239 polling-delay-passive = <250>; 5240 polling-delay = <1000>; 5241 5242 thermal-sensors = <&tsens1 5>; 5243 5244 trips { 5245 camera_alert0: trip-point0 { 5246 temperature = <90000>; 5247 hysteresis = <2000>; 5248 type = "hot"; 5249 }; 5250 }; 5251 }; 5252 5253 compute-thermal { 5254 polling-delay-passive = <250>; 5255 polling-delay = <1000>; 5256 5257 thermal-sensors = <&tsens1 6>; 5258 5259 trips { 5260 compute_alert0: trip-point0 { 5261 temperature = <90000>; 5262 hysteresis = <2000>; 5263 type = "hot"; 5264 }; 5265 }; 5266 }; 5267 5268 modem-thermal { 5269 polling-delay-passive = <250>; 5270 polling-delay = <1000>; 5271 5272 thermal-sensors = <&tsens1 7>; 5273 5274 trips { 5275 modem_alert0: trip-point0 { 5276 temperature = <90000>; 5277 hysteresis = <2000>; 5278 type = "hot"; 5279 }; 5280 }; 5281 }; 5282 5283 npu-thermal { 5284 polling-delay-passive = <250>; 5285 polling-delay = <1000>; 5286 5287 thermal-sensors = <&tsens1 8>; 5288 5289 trips { 5290 npu_alert0: trip-point0 { 5291 temperature = <90000>; 5292 hysteresis = <2000>; 5293 type = "hot"; 5294 }; 5295 }; 5296 }; 5297 5298 modem-vec-thermal { 5299 polling-delay-passive = <250>; 5300 polling-delay = <1000>; 5301 5302 thermal-sensors = <&tsens1 9>; 5303 5304 trips { 5305 modem_vec_alert0: trip-point0 { 5306 temperature = <90000>; 5307 hysteresis = <2000>; 5308 type = "hot"; 5309 }; 5310 }; 5311 }; 5312 5313 modem-scl-thermal { 5314 polling-delay-passive = <250>; 5315 polling-delay = <1000>; 5316 5317 thermal-sensors = <&tsens1 10>; 5318 5319 trips { 5320 modem_scl_alert0: trip-point0 { 5321 temperature = <90000>; 5322 hysteresis = <2000>; 5323 type = "hot"; 5324 }; 5325 }; 5326 }; 5327 5328 gpu-bottom-thermal { 5329 polling-delay-passive = <250>; 5330 polling-delay = <1000>; 5331 5332 thermal-sensors = <&tsens1 11>; 5333 5334 cooling-maps { 5335 map0 { 5336 trip = <&gpu_bottom_alert0>; 5337 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5338 }; 5339 }; 5340 5341 trips { 5342 gpu_bottom_alert0: trip-point0 { 5343 temperature = <90000>; 5344 hysteresis = <2000>; 5345 type = "hot"; 5346 }; 5347 }; 5348 }; 5349 }; 5350}; 5351