1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2019, Linaro Limited 5 */ 6 7#include <dt-bindings/dma/qcom-gpi.h> 8#include <dt-bindings/firmware/qcom,scm.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/phy/phy-qcom-qmp.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/soc/qcom,rpmh-rsc.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,dispcc-sm8150.h> 15#include <dt-bindings/clock/qcom,gcc-sm8150.h> 16#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sm8150.h> 19#include <dt-bindings/thermal/thermal.h> 20 21/ { 22 interrupt-parent = <&intc>; 23 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 chosen { }; 28 29 clocks { 30 xo_board: xo-board { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <38400000>; 34 clock-output-names = "xo_board"; 35 }; 36 37 sleep_clk: sleep-clk { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <32764>; 41 clock-output-names = "sleep_clk"; 42 }; 43 }; 44 45 cpus { 46 #address-cells = <2>; 47 #size-cells = <0>; 48 49 CPU0: cpu@0 { 50 device_type = "cpu"; 51 compatible = "qcom,kryo485"; 52 reg = <0x0 0x0>; 53 clocks = <&cpufreq_hw 0>; 54 enable-method = "psci"; 55 capacity-dmips-mhz = <488>; 56 dynamic-power-coefficient = <232>; 57 next-level-cache = <&L2_0>; 58 qcom,freq-domain = <&cpufreq_hw 0>; 59 operating-points-v2 = <&cpu0_opp_table>; 60 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 61 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 62 power-domains = <&CPU_PD0>; 63 power-domain-names = "psci"; 64 #cooling-cells = <2>; 65 L2_0: l2-cache { 66 compatible = "cache"; 67 cache-level = <2>; 68 cache-unified; 69 next-level-cache = <&L3_0>; 70 L3_0: l3-cache { 71 compatible = "cache"; 72 cache-level = <3>; 73 cache-unified; 74 }; 75 }; 76 }; 77 78 CPU1: cpu@100 { 79 device_type = "cpu"; 80 compatible = "qcom,kryo485"; 81 reg = <0x0 0x100>; 82 clocks = <&cpufreq_hw 0>; 83 enable-method = "psci"; 84 capacity-dmips-mhz = <488>; 85 dynamic-power-coefficient = <232>; 86 next-level-cache = <&L2_100>; 87 qcom,freq-domain = <&cpufreq_hw 0>; 88 operating-points-v2 = <&cpu0_opp_table>; 89 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 90 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 91 power-domains = <&CPU_PD1>; 92 power-domain-names = "psci"; 93 #cooling-cells = <2>; 94 L2_100: l2-cache { 95 compatible = "cache"; 96 cache-level = <2>; 97 cache-unified; 98 next-level-cache = <&L3_0>; 99 }; 100 }; 101 102 CPU2: cpu@200 { 103 device_type = "cpu"; 104 compatible = "qcom,kryo485"; 105 reg = <0x0 0x200>; 106 clocks = <&cpufreq_hw 0>; 107 enable-method = "psci"; 108 capacity-dmips-mhz = <488>; 109 dynamic-power-coefficient = <232>; 110 next-level-cache = <&L2_200>; 111 qcom,freq-domain = <&cpufreq_hw 0>; 112 operating-points-v2 = <&cpu0_opp_table>; 113 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 114 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 115 power-domains = <&CPU_PD2>; 116 power-domain-names = "psci"; 117 #cooling-cells = <2>; 118 L2_200: l2-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 cache-unified; 122 next-level-cache = <&L3_0>; 123 }; 124 }; 125 126 CPU3: cpu@300 { 127 device_type = "cpu"; 128 compatible = "qcom,kryo485"; 129 reg = <0x0 0x300>; 130 clocks = <&cpufreq_hw 0>; 131 enable-method = "psci"; 132 capacity-dmips-mhz = <488>; 133 dynamic-power-coefficient = <232>; 134 next-level-cache = <&L2_300>; 135 qcom,freq-domain = <&cpufreq_hw 0>; 136 operating-points-v2 = <&cpu0_opp_table>; 137 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 138 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 139 power-domains = <&CPU_PD3>; 140 power-domain-names = "psci"; 141 #cooling-cells = <2>; 142 L2_300: l2-cache { 143 compatible = "cache"; 144 cache-level = <2>; 145 cache-unified; 146 next-level-cache = <&L3_0>; 147 }; 148 }; 149 150 CPU4: cpu@400 { 151 device_type = "cpu"; 152 compatible = "qcom,kryo485"; 153 reg = <0x0 0x400>; 154 clocks = <&cpufreq_hw 1>; 155 enable-method = "psci"; 156 capacity-dmips-mhz = <1024>; 157 dynamic-power-coefficient = <369>; 158 next-level-cache = <&L2_400>; 159 qcom,freq-domain = <&cpufreq_hw 1>; 160 operating-points-v2 = <&cpu4_opp_table>; 161 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 162 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 163 power-domains = <&CPU_PD4>; 164 power-domain-names = "psci"; 165 #cooling-cells = <2>; 166 L2_400: l2-cache { 167 compatible = "cache"; 168 cache-level = <2>; 169 cache-unified; 170 next-level-cache = <&L3_0>; 171 }; 172 }; 173 174 CPU5: cpu@500 { 175 device_type = "cpu"; 176 compatible = "qcom,kryo485"; 177 reg = <0x0 0x500>; 178 clocks = <&cpufreq_hw 1>; 179 enable-method = "psci"; 180 capacity-dmips-mhz = <1024>; 181 dynamic-power-coefficient = <369>; 182 next-level-cache = <&L2_500>; 183 qcom,freq-domain = <&cpufreq_hw 1>; 184 operating-points-v2 = <&cpu4_opp_table>; 185 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 186 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 187 power-domains = <&CPU_PD5>; 188 power-domain-names = "psci"; 189 #cooling-cells = <2>; 190 L2_500: l2-cache { 191 compatible = "cache"; 192 cache-level = <2>; 193 cache-unified; 194 next-level-cache = <&L3_0>; 195 }; 196 }; 197 198 CPU6: cpu@600 { 199 device_type = "cpu"; 200 compatible = "qcom,kryo485"; 201 reg = <0x0 0x600>; 202 clocks = <&cpufreq_hw 1>; 203 enable-method = "psci"; 204 capacity-dmips-mhz = <1024>; 205 dynamic-power-coefficient = <369>; 206 next-level-cache = <&L2_600>; 207 qcom,freq-domain = <&cpufreq_hw 1>; 208 operating-points-v2 = <&cpu4_opp_table>; 209 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 210 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 211 power-domains = <&CPU_PD6>; 212 power-domain-names = "psci"; 213 #cooling-cells = <2>; 214 L2_600: l2-cache { 215 compatible = "cache"; 216 cache-level = <2>; 217 cache-unified; 218 next-level-cache = <&L3_0>; 219 }; 220 }; 221 222 CPU7: cpu@700 { 223 device_type = "cpu"; 224 compatible = "qcom,kryo485"; 225 reg = <0x0 0x700>; 226 clocks = <&cpufreq_hw 2>; 227 enable-method = "psci"; 228 capacity-dmips-mhz = <1024>; 229 dynamic-power-coefficient = <421>; 230 next-level-cache = <&L2_700>; 231 qcom,freq-domain = <&cpufreq_hw 2>; 232 operating-points-v2 = <&cpu7_opp_table>; 233 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 234 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 235 power-domains = <&CPU_PD7>; 236 power-domain-names = "psci"; 237 #cooling-cells = <2>; 238 L2_700: l2-cache { 239 compatible = "cache"; 240 cache-level = <2>; 241 cache-unified; 242 next-level-cache = <&L3_0>; 243 }; 244 }; 245 246 cpu-map { 247 cluster0 { 248 core0 { 249 cpu = <&CPU0>; 250 }; 251 252 core1 { 253 cpu = <&CPU1>; 254 }; 255 256 core2 { 257 cpu = <&CPU2>; 258 }; 259 260 core3 { 261 cpu = <&CPU3>; 262 }; 263 264 core4 { 265 cpu = <&CPU4>; 266 }; 267 268 core5 { 269 cpu = <&CPU5>; 270 }; 271 272 core6 { 273 cpu = <&CPU6>; 274 }; 275 276 core7 { 277 cpu = <&CPU7>; 278 }; 279 }; 280 }; 281 282 idle-states { 283 entry-method = "psci"; 284 285 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 286 compatible = "arm,idle-state"; 287 idle-state-name = "little-rail-power-collapse"; 288 arm,psci-suspend-param = <0x40000004>; 289 entry-latency-us = <355>; 290 exit-latency-us = <909>; 291 min-residency-us = <3934>; 292 local-timer-stop; 293 }; 294 295 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 296 compatible = "arm,idle-state"; 297 idle-state-name = "big-rail-power-collapse"; 298 arm,psci-suspend-param = <0x40000004>; 299 entry-latency-us = <241>; 300 exit-latency-us = <1461>; 301 min-residency-us = <4488>; 302 local-timer-stop; 303 }; 304 }; 305 306 domain-idle-states { 307 CLUSTER_SLEEP_0: cluster-sleep-0 { 308 compatible = "domain-idle-state"; 309 arm,psci-suspend-param = <0x4100c244>; 310 entry-latency-us = <3263>; 311 exit-latency-us = <6562>; 312 min-residency-us = <9987>; 313 }; 314 }; 315 }; 316 317 cpu0_opp_table: opp-table-cpu0 { 318 compatible = "operating-points-v2"; 319 opp-shared; 320 321 cpu0_opp1: opp-300000000 { 322 opp-hz = /bits/ 64 <300000000>; 323 opp-peak-kBps = <800000 9600000>; 324 }; 325 326 cpu0_opp2: opp-403200000 { 327 opp-hz = /bits/ 64 <403200000>; 328 opp-peak-kBps = <800000 9600000>; 329 }; 330 331 cpu0_opp3: opp-499200000 { 332 opp-hz = /bits/ 64 <499200000>; 333 opp-peak-kBps = <800000 12902400>; 334 }; 335 336 cpu0_opp4: opp-576000000 { 337 opp-hz = /bits/ 64 <576000000>; 338 opp-peak-kBps = <800000 12902400>; 339 }; 340 341 cpu0_opp5: opp-672000000 { 342 opp-hz = /bits/ 64 <672000000>; 343 opp-peak-kBps = <800000 15974400>; 344 }; 345 346 cpu0_opp6: opp-768000000 { 347 opp-hz = /bits/ 64 <768000000>; 348 opp-peak-kBps = <1804000 19660800>; 349 }; 350 351 cpu0_opp7: opp-844800000 { 352 opp-hz = /bits/ 64 <844800000>; 353 opp-peak-kBps = <1804000 19660800>; 354 }; 355 356 cpu0_opp8: opp-940800000 { 357 opp-hz = /bits/ 64 <940800000>; 358 opp-peak-kBps = <1804000 22732800>; 359 }; 360 361 cpu0_opp9: opp-1036800000 { 362 opp-hz = /bits/ 64 <1036800000>; 363 opp-peak-kBps = <1804000 22732800>; 364 }; 365 366 cpu0_opp10: opp-1113600000 { 367 opp-hz = /bits/ 64 <1113600000>; 368 opp-peak-kBps = <2188000 25804800>; 369 }; 370 371 cpu0_opp11: opp-1209600000 { 372 opp-hz = /bits/ 64 <1209600000>; 373 opp-peak-kBps = <2188000 31948800>; 374 }; 375 376 cpu0_opp12: opp-1305600000 { 377 opp-hz = /bits/ 64 <1305600000>; 378 opp-peak-kBps = <3072000 31948800>; 379 }; 380 381 cpu0_opp13: opp-1382400000 { 382 opp-hz = /bits/ 64 <1382400000>; 383 opp-peak-kBps = <3072000 31948800>; 384 }; 385 386 cpu0_opp14: opp-1478400000 { 387 opp-hz = /bits/ 64 <1478400000>; 388 opp-peak-kBps = <3072000 31948800>; 389 }; 390 391 cpu0_opp15: opp-1555200000 { 392 opp-hz = /bits/ 64 <1555200000>; 393 opp-peak-kBps = <3072000 40550400>; 394 }; 395 396 cpu0_opp16: opp-1632000000 { 397 opp-hz = /bits/ 64 <1632000000>; 398 opp-peak-kBps = <3072000 40550400>; 399 }; 400 401 cpu0_opp17: opp-1708800000 { 402 opp-hz = /bits/ 64 <1708800000>; 403 opp-peak-kBps = <3072000 43008000>; 404 }; 405 406 cpu0_opp18: opp-1785600000 { 407 opp-hz = /bits/ 64 <1785600000>; 408 opp-peak-kBps = <3072000 43008000>; 409 }; 410 }; 411 412 cpu4_opp_table: opp-table-cpu4 { 413 compatible = "operating-points-v2"; 414 opp-shared; 415 416 cpu4_opp1: opp-710400000 { 417 opp-hz = /bits/ 64 <710400000>; 418 opp-peak-kBps = <1804000 15974400>; 419 }; 420 421 cpu4_opp2: opp-825600000 { 422 opp-hz = /bits/ 64 <825600000>; 423 opp-peak-kBps = <2188000 19660800>; 424 }; 425 426 cpu4_opp3: opp-940800000 { 427 opp-hz = /bits/ 64 <940800000>; 428 opp-peak-kBps = <2188000 22732800>; 429 }; 430 431 cpu4_opp4: opp-1056000000 { 432 opp-hz = /bits/ 64 <1056000000>; 433 opp-peak-kBps = <3072000 25804800>; 434 }; 435 436 cpu4_opp5: opp-1171200000 { 437 opp-hz = /bits/ 64 <1171200000>; 438 opp-peak-kBps = <3072000 31948800>; 439 }; 440 441 cpu4_opp6: opp-1286400000 { 442 opp-hz = /bits/ 64 <1286400000>; 443 opp-peak-kBps = <4068000 31948800>; 444 }; 445 446 cpu4_opp7: opp-1401600000 { 447 opp-hz = /bits/ 64 <1401600000>; 448 opp-peak-kBps = <4068000 31948800>; 449 }; 450 451 cpu4_opp8: opp-1497600000 { 452 opp-hz = /bits/ 64 <1497600000>; 453 opp-peak-kBps = <4068000 40550400>; 454 }; 455 456 cpu4_opp9: opp-1612800000 { 457 opp-hz = /bits/ 64 <1612800000>; 458 opp-peak-kBps = <4068000 40550400>; 459 }; 460 461 cpu4_opp10: opp-1708800000 { 462 opp-hz = /bits/ 64 <1708800000>; 463 opp-peak-kBps = <4068000 43008000>; 464 }; 465 466 cpu4_opp11: opp-1804800000 { 467 opp-hz = /bits/ 64 <1804800000>; 468 opp-peak-kBps = <6220000 43008000>; 469 }; 470 471 cpu4_opp12: opp-1920000000 { 472 opp-hz = /bits/ 64 <1920000000>; 473 opp-peak-kBps = <6220000 49152000>; 474 }; 475 476 cpu4_opp13: opp-2016000000 { 477 opp-hz = /bits/ 64 <2016000000>; 478 opp-peak-kBps = <7216000 49152000>; 479 }; 480 481 cpu4_opp14: opp-2131200000 { 482 opp-hz = /bits/ 64 <2131200000>; 483 opp-peak-kBps = <8368000 49152000>; 484 }; 485 486 cpu4_opp15: opp-2227200000 { 487 opp-hz = /bits/ 64 <2227200000>; 488 opp-peak-kBps = <8368000 51609600>; 489 }; 490 491 cpu4_opp16: opp-2323200000 { 492 opp-hz = /bits/ 64 <2323200000>; 493 opp-peak-kBps = <8368000 51609600>; 494 }; 495 496 cpu4_opp17: opp-2419200000 { 497 opp-hz = /bits/ 64 <2419200000>; 498 opp-peak-kBps = <8368000 51609600>; 499 }; 500 }; 501 502 cpu7_opp_table: opp-table-cpu7 { 503 compatible = "operating-points-v2"; 504 opp-shared; 505 506 cpu7_opp1: opp-825600000 { 507 opp-hz = /bits/ 64 <825600000>; 508 opp-peak-kBps = <2188000 19660800>; 509 }; 510 511 cpu7_opp2: opp-940800000 { 512 opp-hz = /bits/ 64 <940800000>; 513 opp-peak-kBps = <2188000 22732800>; 514 }; 515 516 cpu7_opp3: opp-1056000000 { 517 opp-hz = /bits/ 64 <1056000000>; 518 opp-peak-kBps = <3072000 25804800>; 519 }; 520 521 cpu7_opp4: opp-1171200000 { 522 opp-hz = /bits/ 64 <1171200000>; 523 opp-peak-kBps = <3072000 31948800>; 524 }; 525 526 cpu7_opp5: opp-1286400000 { 527 opp-hz = /bits/ 64 <1286400000>; 528 opp-peak-kBps = <4068000 31948800>; 529 }; 530 531 cpu7_opp6: opp-1401600000 { 532 opp-hz = /bits/ 64 <1401600000>; 533 opp-peak-kBps = <4068000 31948800>; 534 }; 535 536 cpu7_opp7: opp-1497600000 { 537 opp-hz = /bits/ 64 <1497600000>; 538 opp-peak-kBps = <4068000 40550400>; 539 }; 540 541 cpu7_opp8: opp-1612800000 { 542 opp-hz = /bits/ 64 <1612800000>; 543 opp-peak-kBps = <4068000 40550400>; 544 }; 545 546 cpu7_opp9: opp-1708800000 { 547 opp-hz = /bits/ 64 <1708800000>; 548 opp-peak-kBps = <4068000 43008000>; 549 }; 550 551 cpu7_opp10: opp-1804800000 { 552 opp-hz = /bits/ 64 <1804800000>; 553 opp-peak-kBps = <6220000 43008000>; 554 }; 555 556 cpu7_opp11: opp-1920000000 { 557 opp-hz = /bits/ 64 <1920000000>; 558 opp-peak-kBps = <6220000 49152000>; 559 }; 560 561 cpu7_opp12: opp-2016000000 { 562 opp-hz = /bits/ 64 <2016000000>; 563 opp-peak-kBps = <7216000 49152000>; 564 }; 565 566 cpu7_opp13: opp-2131200000 { 567 opp-hz = /bits/ 64 <2131200000>; 568 opp-peak-kBps = <8368000 49152000>; 569 }; 570 571 cpu7_opp14: opp-2227200000 { 572 opp-hz = /bits/ 64 <2227200000>; 573 opp-peak-kBps = <8368000 51609600>; 574 }; 575 576 cpu7_opp15: opp-2323200000 { 577 opp-hz = /bits/ 64 <2323200000>; 578 opp-peak-kBps = <8368000 51609600>; 579 }; 580 581 cpu7_opp16: opp-2419200000 { 582 opp-hz = /bits/ 64 <2419200000>; 583 opp-peak-kBps = <8368000 51609600>; 584 }; 585 586 cpu7_opp17: opp-2534400000 { 587 opp-hz = /bits/ 64 <2534400000>; 588 opp-peak-kBps = <8368000 51609600>; 589 }; 590 591 cpu7_opp18: opp-2649600000 { 592 opp-hz = /bits/ 64 <2649600000>; 593 opp-peak-kBps = <8368000 51609600>; 594 }; 595 596 cpu7_opp19: opp-2745600000 { 597 opp-hz = /bits/ 64 <2745600000>; 598 opp-peak-kBps = <8368000 51609600>; 599 }; 600 601 cpu7_opp20: opp-2841600000 { 602 opp-hz = /bits/ 64 <2841600000>; 603 opp-peak-kBps = <8368000 51609600>; 604 }; 605 }; 606 607 firmware { 608 scm: scm { 609 compatible = "qcom,scm-sm8150", "qcom,scm"; 610 #reset-cells = <1>; 611 }; 612 }; 613 614 memory@80000000 { 615 device_type = "memory"; 616 /* We expect the bootloader to fill in the size */ 617 reg = <0x0 0x80000000 0x0 0x0>; 618 }; 619 620 pmu { 621 compatible = "arm,armv8-pmuv3"; 622 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 623 }; 624 625 psci { 626 compatible = "arm,psci-1.0"; 627 method = "smc"; 628 629 CPU_PD0: power-domain-cpu0 { 630 #power-domain-cells = <0>; 631 power-domains = <&CLUSTER_PD>; 632 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 633 }; 634 635 CPU_PD1: power-domain-cpu1 { 636 #power-domain-cells = <0>; 637 power-domains = <&CLUSTER_PD>; 638 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 639 }; 640 641 CPU_PD2: power-domain-cpu2 { 642 #power-domain-cells = <0>; 643 power-domains = <&CLUSTER_PD>; 644 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 645 }; 646 647 CPU_PD3: power-domain-cpu3 { 648 #power-domain-cells = <0>; 649 power-domains = <&CLUSTER_PD>; 650 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 651 }; 652 653 CPU_PD4: power-domain-cpu4 { 654 #power-domain-cells = <0>; 655 power-domains = <&CLUSTER_PD>; 656 domain-idle-states = <&BIG_CPU_SLEEP_0>; 657 }; 658 659 CPU_PD5: power-domain-cpu5 { 660 #power-domain-cells = <0>; 661 power-domains = <&CLUSTER_PD>; 662 domain-idle-states = <&BIG_CPU_SLEEP_0>; 663 }; 664 665 CPU_PD6: power-domain-cpu6 { 666 #power-domain-cells = <0>; 667 power-domains = <&CLUSTER_PD>; 668 domain-idle-states = <&BIG_CPU_SLEEP_0>; 669 }; 670 671 CPU_PD7: power-domain-cpu7 { 672 #power-domain-cells = <0>; 673 power-domains = <&CLUSTER_PD>; 674 domain-idle-states = <&BIG_CPU_SLEEP_0>; 675 }; 676 677 CLUSTER_PD: power-domain-cpu-cluster0 { 678 #power-domain-cells = <0>; 679 domain-idle-states = <&CLUSTER_SLEEP_0>; 680 }; 681 }; 682 683 reserved-memory { 684 #address-cells = <2>; 685 #size-cells = <2>; 686 ranges; 687 688 hyp_mem: memory@85700000 { 689 reg = <0x0 0x85700000 0x0 0x600000>; 690 no-map; 691 }; 692 693 xbl_mem: memory@85d00000 { 694 reg = <0x0 0x85d00000 0x0 0x140000>; 695 no-map; 696 }; 697 698 aop_mem: memory@85f00000 { 699 reg = <0x0 0x85f00000 0x0 0x20000>; 700 no-map; 701 }; 702 703 aop_cmd_db: memory@85f20000 { 704 compatible = "qcom,cmd-db"; 705 reg = <0x0 0x85f20000 0x0 0x20000>; 706 no-map; 707 }; 708 709 smem_mem: memory@86000000 { 710 reg = <0x0 0x86000000 0x0 0x200000>; 711 no-map; 712 }; 713 714 tz_mem: memory@86200000 { 715 reg = <0x0 0x86200000 0x0 0x3900000>; 716 no-map; 717 }; 718 719 rmtfs_mem: memory@89b00000 { 720 compatible = "qcom,rmtfs-mem"; 721 reg = <0x0 0x89b00000 0x0 0x200000>; 722 no-map; 723 724 qcom,client-id = <1>; 725 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 726 }; 727 728 camera_mem: memory@8b700000 { 729 reg = <0x0 0x8b700000 0x0 0x500000>; 730 no-map; 731 }; 732 733 wlan_mem: memory@8bc00000 { 734 reg = <0x0 0x8bc00000 0x0 0x180000>; 735 no-map; 736 }; 737 738 npu_mem: memory@8bd80000 { 739 reg = <0x0 0x8bd80000 0x0 0x80000>; 740 no-map; 741 }; 742 743 adsp_mem: memory@8be00000 { 744 reg = <0x0 0x8be00000 0x0 0x1a00000>; 745 no-map; 746 }; 747 748 mpss_mem: memory@8d800000 { 749 reg = <0x0 0x8d800000 0x0 0x9600000>; 750 no-map; 751 }; 752 753 venus_mem: memory@96e00000 { 754 reg = <0x0 0x96e00000 0x0 0x500000>; 755 no-map; 756 }; 757 758 slpi_mem: memory@97300000 { 759 reg = <0x0 0x97300000 0x0 0x1400000>; 760 no-map; 761 }; 762 763 ipa_fw_mem: memory@98700000 { 764 reg = <0x0 0x98700000 0x0 0x10000>; 765 no-map; 766 }; 767 768 ipa_gsi_mem: memory@98710000 { 769 reg = <0x0 0x98710000 0x0 0x5000>; 770 no-map; 771 }; 772 773 gpu_mem: memory@98715000 { 774 reg = <0x0 0x98715000 0x0 0x2000>; 775 no-map; 776 }; 777 778 spss_mem: memory@98800000 { 779 reg = <0x0 0x98800000 0x0 0x100000>; 780 no-map; 781 }; 782 783 cdsp_mem: memory@98900000 { 784 reg = <0x0 0x98900000 0x0 0x1400000>; 785 no-map; 786 }; 787 788 qseecom_mem: memory@9e400000 { 789 reg = <0x0 0x9e400000 0x0 0x1400000>; 790 no-map; 791 }; 792 }; 793 794 smem { 795 compatible = "qcom,smem"; 796 memory-region = <&smem_mem>; 797 hwlocks = <&tcsr_mutex 3>; 798 }; 799 800 smp2p-cdsp { 801 compatible = "qcom,smp2p"; 802 qcom,smem = <94>, <432>; 803 804 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 805 806 mboxes = <&apss_shared 6>; 807 808 qcom,local-pid = <0>; 809 qcom,remote-pid = <5>; 810 811 cdsp_smp2p_out: master-kernel { 812 qcom,entry-name = "master-kernel"; 813 #qcom,smem-state-cells = <1>; 814 }; 815 816 cdsp_smp2p_in: slave-kernel { 817 qcom,entry-name = "slave-kernel"; 818 819 interrupt-controller; 820 #interrupt-cells = <2>; 821 }; 822 }; 823 824 smp2p-lpass { 825 compatible = "qcom,smp2p"; 826 qcom,smem = <443>, <429>; 827 828 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 829 830 mboxes = <&apss_shared 10>; 831 832 qcom,local-pid = <0>; 833 qcom,remote-pid = <2>; 834 835 adsp_smp2p_out: master-kernel { 836 qcom,entry-name = "master-kernel"; 837 #qcom,smem-state-cells = <1>; 838 }; 839 840 adsp_smp2p_in: slave-kernel { 841 qcom,entry-name = "slave-kernel"; 842 843 interrupt-controller; 844 #interrupt-cells = <2>; 845 }; 846 }; 847 848 smp2p-mpss { 849 compatible = "qcom,smp2p"; 850 qcom,smem = <435>, <428>; 851 852 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 853 854 mboxes = <&apss_shared 14>; 855 856 qcom,local-pid = <0>; 857 qcom,remote-pid = <1>; 858 859 modem_smp2p_out: master-kernel { 860 qcom,entry-name = "master-kernel"; 861 #qcom,smem-state-cells = <1>; 862 }; 863 864 modem_smp2p_in: slave-kernel { 865 qcom,entry-name = "slave-kernel"; 866 867 interrupt-controller; 868 #interrupt-cells = <2>; 869 }; 870 }; 871 872 smp2p-slpi { 873 compatible = "qcom,smp2p"; 874 qcom,smem = <481>, <430>; 875 876 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 877 878 mboxes = <&apss_shared 26>; 879 880 qcom,local-pid = <0>; 881 qcom,remote-pid = <3>; 882 883 slpi_smp2p_out: master-kernel { 884 qcom,entry-name = "master-kernel"; 885 #qcom,smem-state-cells = <1>; 886 }; 887 888 slpi_smp2p_in: slave-kernel { 889 qcom,entry-name = "slave-kernel"; 890 891 interrupt-controller; 892 #interrupt-cells = <2>; 893 }; 894 }; 895 896 soc: soc@0 { 897 #address-cells = <2>; 898 #size-cells = <2>; 899 ranges = <0 0 0 0 0x10 0>; 900 dma-ranges = <0 0 0 0 0x10 0>; 901 compatible = "simple-bus"; 902 903 gcc: clock-controller@100000 { 904 compatible = "qcom,gcc-sm8150"; 905 reg = <0x0 0x00100000 0x0 0x1f0000>; 906 #clock-cells = <1>; 907 #reset-cells = <1>; 908 #power-domain-cells = <1>; 909 clock-names = "bi_tcxo", 910 "sleep_clk"; 911 clocks = <&rpmhcc RPMH_CXO_CLK>, 912 <&sleep_clk>; 913 }; 914 915 gpi_dma0: dma-controller@800000 { 916 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 917 reg = <0 0x00800000 0 0x60000>; 918 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 919 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 920 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 921 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 922 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 923 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 931 dma-channels = <13>; 932 dma-channel-mask = <0xfa>; 933 iommus = <&apps_smmu 0x00d6 0x0>; 934 #dma-cells = <3>; 935 status = "disabled"; 936 }; 937 938 ethernet: ethernet@20000 { 939 compatible = "qcom,sm8150-ethqos"; 940 reg = <0x0 0x00020000 0x0 0x10000>, 941 <0x0 0x00036000 0x0 0x100>; 942 reg-names = "stmmaceth", "rgmii"; 943 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; 944 clocks = <&gcc GCC_EMAC_AXI_CLK>, 945 <&gcc GCC_EMAC_SLV_AHB_CLK>, 946 <&gcc GCC_EMAC_PTP_CLK>, 947 <&gcc GCC_EMAC_RGMII_CLK>; 948 interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>; 950 interrupt-names = "macirq", "eth_lpi"; 951 952 power-domains = <&gcc EMAC_GDSC>; 953 resets = <&gcc GCC_EMAC_BCR>; 954 955 iommus = <&apps_smmu 0x3c0 0x0>; 956 957 snps,tso; 958 rx-fifo-depth = <4096>; 959 tx-fifo-depth = <4096>; 960 961 status = "disabled"; 962 }; 963 964 qfprom: efuse@784000 { 965 compatible = "qcom,sm8150-qfprom", "qcom,qfprom"; 966 reg = <0 0x00784000 0 0x8ff>; 967 #address-cells = <1>; 968 #size-cells = <1>; 969 970 gpu_speed_bin: gpu-speed-bin@133 { 971 reg = <0x133 0x1>; 972 bits = <5 3>; 973 }; 974 }; 975 976 qupv3_id_0: geniqup@8c0000 { 977 compatible = "qcom,geni-se-qup"; 978 reg = <0x0 0x008c0000 0x0 0x6000>; 979 clock-names = "m-ahb", "s-ahb"; 980 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 981 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 982 iommus = <&apps_smmu 0xc3 0x0>; 983 #address-cells = <2>; 984 #size-cells = <2>; 985 ranges; 986 status = "disabled"; 987 988 i2c0: i2c@880000 { 989 compatible = "qcom,geni-i2c"; 990 reg = <0 0x00880000 0 0x4000>; 991 clock-names = "se"; 992 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 993 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 994 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 995 dma-names = "tx", "rx"; 996 pinctrl-names = "default"; 997 pinctrl-0 = <&qup_i2c0_default>; 998 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 999 #address-cells = <1>; 1000 #size-cells = <0>; 1001 status = "disabled"; 1002 }; 1003 1004 spi0: spi@880000 { 1005 compatible = "qcom,geni-spi"; 1006 reg = <0 0x00880000 0 0x4000>; 1007 reg-names = "se"; 1008 clock-names = "se"; 1009 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1010 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1011 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1012 dma-names = "tx", "rx"; 1013 pinctrl-names = "default"; 1014 pinctrl-0 = <&qup_spi0_default>; 1015 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1016 spi-max-frequency = <50000000>; 1017 #address-cells = <1>; 1018 #size-cells = <0>; 1019 status = "disabled"; 1020 }; 1021 1022 i2c1: i2c@884000 { 1023 compatible = "qcom,geni-i2c"; 1024 reg = <0 0x00884000 0 0x4000>; 1025 clock-names = "se"; 1026 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1027 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1028 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1029 dma-names = "tx", "rx"; 1030 pinctrl-names = "default"; 1031 pinctrl-0 = <&qup_i2c1_default>; 1032 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1033 #address-cells = <1>; 1034 #size-cells = <0>; 1035 status = "disabled"; 1036 }; 1037 1038 spi1: spi@884000 { 1039 compatible = "qcom,geni-spi"; 1040 reg = <0 0x00884000 0 0x4000>; 1041 reg-names = "se"; 1042 clock-names = "se"; 1043 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1044 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1045 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1046 dma-names = "tx", "rx"; 1047 pinctrl-names = "default"; 1048 pinctrl-0 = <&qup_spi1_default>; 1049 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1050 spi-max-frequency = <50000000>; 1051 #address-cells = <1>; 1052 #size-cells = <0>; 1053 status = "disabled"; 1054 }; 1055 1056 i2c2: i2c@888000 { 1057 compatible = "qcom,geni-i2c"; 1058 reg = <0 0x00888000 0 0x4000>; 1059 clock-names = "se"; 1060 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1061 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1062 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1063 dma-names = "tx", "rx"; 1064 pinctrl-names = "default"; 1065 pinctrl-0 = <&qup_i2c2_default>; 1066 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1067 #address-cells = <1>; 1068 #size-cells = <0>; 1069 status = "disabled"; 1070 }; 1071 1072 spi2: spi@888000 { 1073 compatible = "qcom,geni-spi"; 1074 reg = <0 0x00888000 0 0x4000>; 1075 reg-names = "se"; 1076 clock-names = "se"; 1077 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1078 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1079 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1080 dma-names = "tx", "rx"; 1081 pinctrl-names = "default"; 1082 pinctrl-0 = <&qup_spi2_default>; 1083 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1084 spi-max-frequency = <50000000>; 1085 #address-cells = <1>; 1086 #size-cells = <0>; 1087 status = "disabled"; 1088 }; 1089 1090 i2c3: i2c@88c000 { 1091 compatible = "qcom,geni-i2c"; 1092 reg = <0 0x0088c000 0 0x4000>; 1093 clock-names = "se"; 1094 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1095 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1096 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1097 dma-names = "tx", "rx"; 1098 pinctrl-names = "default"; 1099 pinctrl-0 = <&qup_i2c3_default>; 1100 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1101 #address-cells = <1>; 1102 #size-cells = <0>; 1103 status = "disabled"; 1104 }; 1105 1106 spi3: spi@88c000 { 1107 compatible = "qcom,geni-spi"; 1108 reg = <0 0x0088c000 0 0x4000>; 1109 reg-names = "se"; 1110 clock-names = "se"; 1111 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1112 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1113 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1114 dma-names = "tx", "rx"; 1115 pinctrl-names = "default"; 1116 pinctrl-0 = <&qup_spi3_default>; 1117 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1118 spi-max-frequency = <50000000>; 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 status = "disabled"; 1122 }; 1123 1124 i2c4: i2c@890000 { 1125 compatible = "qcom,geni-i2c"; 1126 reg = <0 0x00890000 0 0x4000>; 1127 clock-names = "se"; 1128 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1129 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1130 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1131 dma-names = "tx", "rx"; 1132 pinctrl-names = "default"; 1133 pinctrl-0 = <&qup_i2c4_default>; 1134 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1135 #address-cells = <1>; 1136 #size-cells = <0>; 1137 status = "disabled"; 1138 }; 1139 1140 spi4: spi@890000 { 1141 compatible = "qcom,geni-spi"; 1142 reg = <0 0x00890000 0 0x4000>; 1143 reg-names = "se"; 1144 clock-names = "se"; 1145 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1146 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1147 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1148 dma-names = "tx", "rx"; 1149 pinctrl-names = "default"; 1150 pinctrl-0 = <&qup_spi4_default>; 1151 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1152 spi-max-frequency = <50000000>; 1153 #address-cells = <1>; 1154 #size-cells = <0>; 1155 status = "disabled"; 1156 }; 1157 1158 i2c5: i2c@894000 { 1159 compatible = "qcom,geni-i2c"; 1160 reg = <0 0x00894000 0 0x4000>; 1161 clock-names = "se"; 1162 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1163 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1164 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1165 dma-names = "tx", "rx"; 1166 pinctrl-names = "default"; 1167 pinctrl-0 = <&qup_i2c5_default>; 1168 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1169 #address-cells = <1>; 1170 #size-cells = <0>; 1171 status = "disabled"; 1172 }; 1173 1174 spi5: spi@894000 { 1175 compatible = "qcom,geni-spi"; 1176 reg = <0 0x00894000 0 0x4000>; 1177 reg-names = "se"; 1178 clock-names = "se"; 1179 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1180 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1181 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1182 dma-names = "tx", "rx"; 1183 pinctrl-names = "default"; 1184 pinctrl-0 = <&qup_spi5_default>; 1185 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1186 spi-max-frequency = <50000000>; 1187 #address-cells = <1>; 1188 #size-cells = <0>; 1189 status = "disabled"; 1190 }; 1191 1192 i2c6: i2c@898000 { 1193 compatible = "qcom,geni-i2c"; 1194 reg = <0 0x00898000 0 0x4000>; 1195 clock-names = "se"; 1196 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1197 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1198 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1199 dma-names = "tx", "rx"; 1200 pinctrl-names = "default"; 1201 pinctrl-0 = <&qup_i2c6_default>; 1202 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1203 #address-cells = <1>; 1204 #size-cells = <0>; 1205 status = "disabled"; 1206 }; 1207 1208 spi6: spi@898000 { 1209 compatible = "qcom,geni-spi"; 1210 reg = <0 0x00898000 0 0x4000>; 1211 reg-names = "se"; 1212 clock-names = "se"; 1213 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1214 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1215 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1216 dma-names = "tx", "rx"; 1217 pinctrl-names = "default"; 1218 pinctrl-0 = <&qup_spi6_default>; 1219 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1220 spi-max-frequency = <50000000>; 1221 #address-cells = <1>; 1222 #size-cells = <0>; 1223 status = "disabled"; 1224 }; 1225 1226 i2c7: i2c@89c000 { 1227 compatible = "qcom,geni-i2c"; 1228 reg = <0 0x0089c000 0 0x4000>; 1229 clock-names = "se"; 1230 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1231 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1232 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1233 dma-names = "tx", "rx"; 1234 pinctrl-names = "default"; 1235 pinctrl-0 = <&qup_i2c7_default>; 1236 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1237 #address-cells = <1>; 1238 #size-cells = <0>; 1239 status = "disabled"; 1240 }; 1241 1242 spi7: spi@89c000 { 1243 compatible = "qcom,geni-spi"; 1244 reg = <0 0x0089c000 0 0x4000>; 1245 reg-names = "se"; 1246 clock-names = "se"; 1247 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1248 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1249 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1250 dma-names = "tx", "rx"; 1251 pinctrl-names = "default"; 1252 pinctrl-0 = <&qup_spi7_default>; 1253 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1254 spi-max-frequency = <50000000>; 1255 #address-cells = <1>; 1256 #size-cells = <0>; 1257 status = "disabled"; 1258 }; 1259 }; 1260 1261 gpi_dma1: dma-controller@a00000 { 1262 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 1263 reg = <0 0x00a00000 0 0x60000>; 1264 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1265 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1266 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1267 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1275 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1276 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1277 dma-channels = <13>; 1278 dma-channel-mask = <0xfa>; 1279 iommus = <&apps_smmu 0x0616 0x0>; 1280 #dma-cells = <3>; 1281 status = "disabled"; 1282 }; 1283 1284 qupv3_id_1: geniqup@ac0000 { 1285 compatible = "qcom,geni-se-qup"; 1286 reg = <0x0 0x00ac0000 0x0 0x6000>; 1287 clock-names = "m-ahb", "s-ahb"; 1288 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1289 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1290 iommus = <&apps_smmu 0x603 0x0>; 1291 #address-cells = <2>; 1292 #size-cells = <2>; 1293 ranges; 1294 status = "disabled"; 1295 1296 i2c8: i2c@a80000 { 1297 compatible = "qcom,geni-i2c"; 1298 reg = <0 0x00a80000 0 0x4000>; 1299 clock-names = "se"; 1300 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1301 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1302 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1303 dma-names = "tx", "rx"; 1304 pinctrl-names = "default"; 1305 pinctrl-0 = <&qup_i2c8_default>; 1306 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1307 #address-cells = <1>; 1308 #size-cells = <0>; 1309 status = "disabled"; 1310 }; 1311 1312 spi8: spi@a80000 { 1313 compatible = "qcom,geni-spi"; 1314 reg = <0 0x00a80000 0 0x4000>; 1315 reg-names = "se"; 1316 clock-names = "se"; 1317 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1318 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1319 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1320 dma-names = "tx", "rx"; 1321 pinctrl-names = "default"; 1322 pinctrl-0 = <&qup_spi8_default>; 1323 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1324 spi-max-frequency = <50000000>; 1325 #address-cells = <1>; 1326 #size-cells = <0>; 1327 status = "disabled"; 1328 }; 1329 1330 i2c9: i2c@a84000 { 1331 compatible = "qcom,geni-i2c"; 1332 reg = <0 0x00a84000 0 0x4000>; 1333 clock-names = "se"; 1334 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1335 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1336 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1337 dma-names = "tx", "rx"; 1338 pinctrl-names = "default"; 1339 pinctrl-0 = <&qup_i2c9_default>; 1340 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1341 #address-cells = <1>; 1342 #size-cells = <0>; 1343 status = "disabled"; 1344 }; 1345 1346 spi9: spi@a84000 { 1347 compatible = "qcom,geni-spi"; 1348 reg = <0 0x00a84000 0 0x4000>; 1349 reg-names = "se"; 1350 clock-names = "se"; 1351 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1352 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1353 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1354 dma-names = "tx", "rx"; 1355 pinctrl-names = "default"; 1356 pinctrl-0 = <&qup_spi9_default>; 1357 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1358 spi-max-frequency = <50000000>; 1359 #address-cells = <1>; 1360 #size-cells = <0>; 1361 status = "disabled"; 1362 }; 1363 1364 uart9: serial@a84000 { 1365 compatible = "qcom,geni-uart"; 1366 reg = <0x0 0x00a84000 0x0 0x4000>; 1367 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1368 clock-names = "se"; 1369 pinctrl-0 = <&qup_uart9_default>; 1370 pinctrl-names = "default"; 1371 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1372 status = "disabled"; 1373 }; 1374 1375 i2c10: i2c@a88000 { 1376 compatible = "qcom,geni-i2c"; 1377 reg = <0 0x00a88000 0 0x4000>; 1378 clock-names = "se"; 1379 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1380 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1381 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1382 dma-names = "tx", "rx"; 1383 pinctrl-names = "default"; 1384 pinctrl-0 = <&qup_i2c10_default>; 1385 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1386 #address-cells = <1>; 1387 #size-cells = <0>; 1388 status = "disabled"; 1389 }; 1390 1391 spi10: spi@a88000 { 1392 compatible = "qcom,geni-spi"; 1393 reg = <0 0x00a88000 0 0x4000>; 1394 reg-names = "se"; 1395 clock-names = "se"; 1396 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1397 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1398 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1399 dma-names = "tx", "rx"; 1400 pinctrl-names = "default"; 1401 pinctrl-0 = <&qup_spi10_default>; 1402 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1403 spi-max-frequency = <50000000>; 1404 #address-cells = <1>; 1405 #size-cells = <0>; 1406 status = "disabled"; 1407 }; 1408 1409 i2c11: i2c@a8c000 { 1410 compatible = "qcom,geni-i2c"; 1411 reg = <0 0x00a8c000 0 0x4000>; 1412 clock-names = "se"; 1413 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1414 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1415 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1416 dma-names = "tx", "rx"; 1417 pinctrl-names = "default"; 1418 pinctrl-0 = <&qup_i2c11_default>; 1419 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1420 #address-cells = <1>; 1421 #size-cells = <0>; 1422 status = "disabled"; 1423 }; 1424 1425 spi11: spi@a8c000 { 1426 compatible = "qcom,geni-spi"; 1427 reg = <0 0x00a8c000 0 0x4000>; 1428 reg-names = "se"; 1429 clock-names = "se"; 1430 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1431 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1432 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1433 dma-names = "tx", "rx"; 1434 pinctrl-names = "default"; 1435 pinctrl-0 = <&qup_spi11_default>; 1436 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1437 spi-max-frequency = <50000000>; 1438 #address-cells = <1>; 1439 #size-cells = <0>; 1440 status = "disabled"; 1441 }; 1442 1443 uart2: serial@a90000 { 1444 compatible = "qcom,geni-debug-uart"; 1445 reg = <0x0 0x00a90000 0x0 0x4000>; 1446 clock-names = "se"; 1447 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1448 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1449 status = "disabled"; 1450 }; 1451 1452 i2c12: i2c@a90000 { 1453 compatible = "qcom,geni-i2c"; 1454 reg = <0 0x00a90000 0 0x4000>; 1455 clock-names = "se"; 1456 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1457 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1458 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1459 dma-names = "tx", "rx"; 1460 pinctrl-names = "default"; 1461 pinctrl-0 = <&qup_i2c12_default>; 1462 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1463 #address-cells = <1>; 1464 #size-cells = <0>; 1465 status = "disabled"; 1466 }; 1467 1468 spi12: spi@a90000 { 1469 compatible = "qcom,geni-spi"; 1470 reg = <0 0x00a90000 0 0x4000>; 1471 reg-names = "se"; 1472 clock-names = "se"; 1473 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1474 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1475 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1476 dma-names = "tx", "rx"; 1477 pinctrl-names = "default"; 1478 pinctrl-0 = <&qup_spi12_default>; 1479 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1480 spi-max-frequency = <50000000>; 1481 #address-cells = <1>; 1482 #size-cells = <0>; 1483 status = "disabled"; 1484 }; 1485 1486 i2c16: i2c@94000 { 1487 compatible = "qcom,geni-i2c"; 1488 reg = <0 0x00094000 0 0x4000>; 1489 clock-names = "se"; 1490 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1491 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1492 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1493 dma-names = "tx", "rx"; 1494 pinctrl-names = "default"; 1495 pinctrl-0 = <&qup_i2c16_default>; 1496 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1497 #address-cells = <1>; 1498 #size-cells = <0>; 1499 status = "disabled"; 1500 }; 1501 1502 spi16: spi@a94000 { 1503 compatible = "qcom,geni-spi"; 1504 reg = <0 0x00a94000 0 0x4000>; 1505 reg-names = "se"; 1506 clock-names = "se"; 1507 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1508 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1509 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1510 dma-names = "tx", "rx"; 1511 pinctrl-names = "default"; 1512 pinctrl-0 = <&qup_spi16_default>; 1513 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1514 spi-max-frequency = <50000000>; 1515 #address-cells = <1>; 1516 #size-cells = <0>; 1517 status = "disabled"; 1518 }; 1519 }; 1520 1521 gpi_dma2: dma-controller@c00000 { 1522 compatible = "qcom,sm8150-gpi-dma", "qcom,sdm845-gpi-dma"; 1523 reg = <0 0x00c00000 0 0x60000>; 1524 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>; 1537 dma-channels = <13>; 1538 dma-channel-mask = <0xfa>; 1539 iommus = <&apps_smmu 0x07b6 0x0>; 1540 #dma-cells = <3>; 1541 status = "disabled"; 1542 }; 1543 1544 qupv3_id_2: geniqup@cc0000 { 1545 compatible = "qcom,geni-se-qup"; 1546 reg = <0x0 0x00cc0000 0x0 0x6000>; 1547 1548 clock-names = "m-ahb", "s-ahb"; 1549 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1550 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1551 iommus = <&apps_smmu 0x7a3 0x0>; 1552 #address-cells = <2>; 1553 #size-cells = <2>; 1554 ranges; 1555 status = "disabled"; 1556 1557 i2c17: i2c@c80000 { 1558 compatible = "qcom,geni-i2c"; 1559 reg = <0 0x00c80000 0 0x4000>; 1560 clock-names = "se"; 1561 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1562 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1563 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1564 dma-names = "tx", "rx"; 1565 pinctrl-names = "default"; 1566 pinctrl-0 = <&qup_i2c17_default>; 1567 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1568 #address-cells = <1>; 1569 #size-cells = <0>; 1570 status = "disabled"; 1571 }; 1572 1573 spi17: spi@c80000 { 1574 compatible = "qcom,geni-spi"; 1575 reg = <0 0x00c80000 0 0x4000>; 1576 reg-names = "se"; 1577 clock-names = "se"; 1578 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1579 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1580 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1581 dma-names = "tx", "rx"; 1582 pinctrl-names = "default"; 1583 pinctrl-0 = <&qup_spi17_default>; 1584 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1585 spi-max-frequency = <50000000>; 1586 #address-cells = <1>; 1587 #size-cells = <0>; 1588 status = "disabled"; 1589 }; 1590 1591 i2c18: i2c@c84000 { 1592 compatible = "qcom,geni-i2c"; 1593 reg = <0 0x00c84000 0 0x4000>; 1594 clock-names = "se"; 1595 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1596 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1597 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1598 dma-names = "tx", "rx"; 1599 pinctrl-names = "default"; 1600 pinctrl-0 = <&qup_i2c18_default>; 1601 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1602 #address-cells = <1>; 1603 #size-cells = <0>; 1604 status = "disabled"; 1605 }; 1606 1607 spi18: spi@c84000 { 1608 compatible = "qcom,geni-spi"; 1609 reg = <0 0x00c84000 0 0x4000>; 1610 reg-names = "se"; 1611 clock-names = "se"; 1612 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1613 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1614 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1615 dma-names = "tx", "rx"; 1616 pinctrl-names = "default"; 1617 pinctrl-0 = <&qup_spi18_default>; 1618 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1619 spi-max-frequency = <50000000>; 1620 #address-cells = <1>; 1621 #size-cells = <0>; 1622 status = "disabled"; 1623 }; 1624 1625 i2c19: i2c@c88000 { 1626 compatible = "qcom,geni-i2c"; 1627 reg = <0 0x00c88000 0 0x4000>; 1628 clock-names = "se"; 1629 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1630 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1631 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1632 dma-names = "tx", "rx"; 1633 pinctrl-names = "default"; 1634 pinctrl-0 = <&qup_i2c19_default>; 1635 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1636 #address-cells = <1>; 1637 #size-cells = <0>; 1638 status = "disabled"; 1639 }; 1640 1641 spi19: spi@c88000 { 1642 compatible = "qcom,geni-spi"; 1643 reg = <0 0x00c88000 0 0x4000>; 1644 reg-names = "se"; 1645 clock-names = "se"; 1646 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1647 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1648 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1649 dma-names = "tx", "rx"; 1650 pinctrl-names = "default"; 1651 pinctrl-0 = <&qup_spi19_default>; 1652 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1653 spi-max-frequency = <50000000>; 1654 #address-cells = <1>; 1655 #size-cells = <0>; 1656 status = "disabled"; 1657 }; 1658 1659 i2c13: i2c@c8c000 { 1660 compatible = "qcom,geni-i2c"; 1661 reg = <0 0x00c8c000 0 0x4000>; 1662 clock-names = "se"; 1663 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1664 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1665 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1666 dma-names = "tx", "rx"; 1667 pinctrl-names = "default"; 1668 pinctrl-0 = <&qup_i2c13_default>; 1669 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1670 #address-cells = <1>; 1671 #size-cells = <0>; 1672 status = "disabled"; 1673 }; 1674 1675 spi13: spi@c8c000 { 1676 compatible = "qcom,geni-spi"; 1677 reg = <0 0x00c8c000 0 0x4000>; 1678 reg-names = "se"; 1679 clock-names = "se"; 1680 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1681 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1682 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1683 dma-names = "tx", "rx"; 1684 pinctrl-names = "default"; 1685 pinctrl-0 = <&qup_spi13_default>; 1686 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1687 spi-max-frequency = <50000000>; 1688 #address-cells = <1>; 1689 #size-cells = <0>; 1690 status = "disabled"; 1691 }; 1692 1693 i2c14: i2c@c90000 { 1694 compatible = "qcom,geni-i2c"; 1695 reg = <0 0x00c90000 0 0x4000>; 1696 clock-names = "se"; 1697 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1698 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1699 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1700 dma-names = "tx", "rx"; 1701 pinctrl-names = "default"; 1702 pinctrl-0 = <&qup_i2c14_default>; 1703 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1704 #address-cells = <1>; 1705 #size-cells = <0>; 1706 status = "disabled"; 1707 }; 1708 1709 spi14: spi@c90000 { 1710 compatible = "qcom,geni-spi"; 1711 reg = <0 0x00c90000 0 0x4000>; 1712 reg-names = "se"; 1713 clock-names = "se"; 1714 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1715 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1716 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1717 dma-names = "tx", "rx"; 1718 pinctrl-names = "default"; 1719 pinctrl-0 = <&qup_spi14_default>; 1720 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1721 spi-max-frequency = <50000000>; 1722 #address-cells = <1>; 1723 #size-cells = <0>; 1724 status = "disabled"; 1725 }; 1726 1727 i2c15: i2c@c94000 { 1728 compatible = "qcom,geni-i2c"; 1729 reg = <0 0x00c94000 0 0x4000>; 1730 clock-names = "se"; 1731 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1732 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1733 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1734 dma-names = "tx", "rx"; 1735 pinctrl-names = "default"; 1736 pinctrl-0 = <&qup_i2c15_default>; 1737 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1738 #address-cells = <1>; 1739 #size-cells = <0>; 1740 status = "disabled"; 1741 }; 1742 1743 spi15: spi@c94000 { 1744 compatible = "qcom,geni-spi"; 1745 reg = <0 0x00c94000 0 0x4000>; 1746 reg-names = "se"; 1747 clock-names = "se"; 1748 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1749 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1750 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1751 dma-names = "tx", "rx"; 1752 pinctrl-names = "default"; 1753 pinctrl-0 = <&qup_spi15_default>; 1754 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1755 spi-max-frequency = <50000000>; 1756 #address-cells = <1>; 1757 #size-cells = <0>; 1758 status = "disabled"; 1759 }; 1760 }; 1761 1762 config_noc: interconnect@1500000 { 1763 compatible = "qcom,sm8150-config-noc"; 1764 reg = <0 0x01500000 0 0x7400>; 1765 #interconnect-cells = <2>; 1766 qcom,bcm-voters = <&apps_bcm_voter>; 1767 }; 1768 1769 system_noc: interconnect@1620000 { 1770 compatible = "qcom,sm8150-system-noc"; 1771 reg = <0 0x01620000 0 0x19400>; 1772 #interconnect-cells = <2>; 1773 qcom,bcm-voters = <&apps_bcm_voter>; 1774 }; 1775 1776 mc_virt: interconnect@163a000 { 1777 compatible = "qcom,sm8150-mc-virt"; 1778 reg = <0 0x0163a000 0 0x1000>; 1779 #interconnect-cells = <2>; 1780 qcom,bcm-voters = <&apps_bcm_voter>; 1781 }; 1782 1783 aggre1_noc: interconnect@16e0000 { 1784 compatible = "qcom,sm8150-aggre1-noc"; 1785 reg = <0 0x016e0000 0 0xd080>; 1786 #interconnect-cells = <2>; 1787 qcom,bcm-voters = <&apps_bcm_voter>; 1788 }; 1789 1790 aggre2_noc: interconnect@1700000 { 1791 compatible = "qcom,sm8150-aggre2-noc"; 1792 reg = <0 0x01700000 0 0x20000>; 1793 #interconnect-cells = <2>; 1794 qcom,bcm-voters = <&apps_bcm_voter>; 1795 }; 1796 1797 compute_noc: interconnect@1720000 { 1798 compatible = "qcom,sm8150-compute-noc"; 1799 reg = <0 0x01720000 0 0x7000>; 1800 #interconnect-cells = <2>; 1801 qcom,bcm-voters = <&apps_bcm_voter>; 1802 }; 1803 1804 mmss_noc: interconnect@1740000 { 1805 compatible = "qcom,sm8150-mmss-noc"; 1806 reg = <0 0x01740000 0 0x1c100>; 1807 #interconnect-cells = <2>; 1808 qcom,bcm-voters = <&apps_bcm_voter>; 1809 }; 1810 1811 system-cache-controller@9200000 { 1812 compatible = "qcom,sm8150-llcc"; 1813 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, 1814 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, 1815 <0 0x09600000 0 0x50000>; 1816 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 1817 "llcc3_base", "llcc_broadcast_base"; 1818 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1819 }; 1820 1821 dma@10a2000 { 1822 compatible = "qcom,sm8150-dcc", "qcom,dcc"; 1823 reg = <0x0 0x010a2000 0x0 0x1000>, 1824 <0x0 0x010ad000 0x0 0x3000>; 1825 }; 1826 1827 pcie0: pcie@1c00000 { 1828 compatible = "qcom,pcie-sm8150"; 1829 reg = <0 0x01c00000 0 0x3000>, 1830 <0 0x60000000 0 0xf1d>, 1831 <0 0x60000f20 0 0xa8>, 1832 <0 0x60001000 0 0x1000>, 1833 <0 0x60100000 0 0x100000>; 1834 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1835 device_type = "pci"; 1836 linux,pci-domain = <0>; 1837 bus-range = <0x00 0xff>; 1838 num-lanes = <1>; 1839 1840 #address-cells = <3>; 1841 #size-cells = <2>; 1842 1843 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1844 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1845 1846 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1854 interrupt-names = "msi0", 1855 "msi1", 1856 "msi2", 1857 "msi3", 1858 "msi4", 1859 "msi5", 1860 "msi6", 1861 "msi7"; 1862 #interrupt-cells = <1>; 1863 interrupt-map-mask = <0 0 0 0x7>; 1864 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1865 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1866 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1867 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1868 1869 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1870 <&gcc GCC_PCIE_0_AUX_CLK>, 1871 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1872 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1873 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1874 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1875 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1876 <&rpmhcc RPMH_CXO_CLK>; 1877 clock-names = "pipe", 1878 "aux", 1879 "cfg", 1880 "bus_master", 1881 "bus_slave", 1882 "slave_q2a", 1883 "tbu", 1884 "ref"; 1885 1886 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, 1887 <0x100 &apps_smmu 0x1d81 0x1>; 1888 1889 resets = <&gcc GCC_PCIE_0_BCR>; 1890 reset-names = "pci"; 1891 1892 power-domains = <&gcc PCIE_0_GDSC>; 1893 1894 phys = <&pcie0_phy>; 1895 phy-names = "pciephy"; 1896 1897 perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>; 1898 wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; 1899 1900 pinctrl-names = "default"; 1901 pinctrl-0 = <&pcie0_default_state>; 1902 1903 status = "disabled"; 1904 1905 pcie@0 { 1906 device_type = "pci"; 1907 reg = <0x0 0x0 0x0 0x0 0x0>; 1908 bus-range = <0x01 0xff>; 1909 1910 #address-cells = <3>; 1911 #size-cells = <2>; 1912 ranges; 1913 }; 1914 }; 1915 1916 pcie0_phy: phy@1c06000 { 1917 compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy"; 1918 reg = <0 0x01c06000 0 0x1000>; 1919 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1920 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1921 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1922 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, 1923 <&gcc GCC_PCIE_0_PIPE_CLK>; 1924 clock-names = "aux", 1925 "cfg_ahb", 1926 "ref", 1927 "refgen", 1928 "pipe"; 1929 1930 clock-output-names = "pcie_0_pipe_clk"; 1931 #clock-cells = <0>; 1932 1933 #phy-cells = <0>; 1934 1935 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1936 reset-names = "phy"; 1937 1938 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1939 assigned-clock-rates = <100000000>; 1940 1941 status = "disabled"; 1942 }; 1943 1944 pcie1: pcie@1c08000 { 1945 compatible = "qcom,pcie-sm8150"; 1946 reg = <0 0x01c08000 0 0x3000>, 1947 <0 0x40000000 0 0xf1d>, 1948 <0 0x40000f20 0 0xa8>, 1949 <0 0x40001000 0 0x1000>, 1950 <0 0x40100000 0 0x100000>; 1951 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1952 device_type = "pci"; 1953 linux,pci-domain = <1>; 1954 bus-range = <0x00 0xff>; 1955 num-lanes = <2>; 1956 1957 #address-cells = <3>; 1958 #size-cells = <2>; 1959 1960 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1961 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1962 1963 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1964 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1965 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1966 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1967 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1968 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1969 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 1970 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1971 interrupt-names = "msi0", 1972 "msi1", 1973 "msi2", 1974 "msi3", 1975 "msi4", 1976 "msi5", 1977 "msi6", 1978 "msi7"; 1979 #interrupt-cells = <1>; 1980 interrupt-map-mask = <0 0 0 0x7>; 1981 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1982 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1983 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1984 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1985 1986 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1987 <&gcc GCC_PCIE_1_AUX_CLK>, 1988 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1989 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1990 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1991 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1992 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1993 <&rpmhcc RPMH_CXO_CLK>; 1994 clock-names = "pipe", 1995 "aux", 1996 "cfg", 1997 "bus_master", 1998 "bus_slave", 1999 "slave_q2a", 2000 "tbu", 2001 "ref"; 2002 2003 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2004 assigned-clock-rates = <19200000>; 2005 2006 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 2007 <0x100 &apps_smmu 0x1e01 0x1>; 2008 2009 resets = <&gcc GCC_PCIE_1_BCR>; 2010 reset-names = "pci"; 2011 2012 power-domains = <&gcc PCIE_1_GDSC>; 2013 2014 phys = <&pcie1_phy>; 2015 phy-names = "pciephy"; 2016 2017 perst-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; 2018 enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>; 2019 2020 pinctrl-names = "default"; 2021 pinctrl-0 = <&pcie1_default_state>; 2022 2023 status = "disabled"; 2024 2025 pcie@0 { 2026 device_type = "pci"; 2027 reg = <0x0 0x0 0x0 0x0 0x0>; 2028 bus-range = <0x01 0xff>; 2029 2030 #address-cells = <3>; 2031 #size-cells = <2>; 2032 ranges; 2033 }; 2034 }; 2035 2036 pcie1_phy: phy@1c0e000 { 2037 compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy"; 2038 reg = <0 0x01c0e000 0 0x1000>; 2039 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2040 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2041 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2042 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, 2043 <&gcc GCC_PCIE_1_PIPE_CLK>; 2044 clock-names = "aux", 2045 "cfg_ahb", 2046 "ref", 2047 "refgen", 2048 "pipe"; 2049 2050 clock-output-names = "pcie_1_pipe_clk"; 2051 #clock-cells = <0>; 2052 2053 #phy-cells = <0>; 2054 2055 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2056 reset-names = "phy"; 2057 2058 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2059 assigned-clock-rates = <100000000>; 2060 2061 status = "disabled"; 2062 }; 2063 2064 ufs_mem_hc: ufshc@1d84000 { 2065 compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 2066 "jedec,ufs-2.0"; 2067 reg = <0 0x01d84000 0 0x2500>, 2068 <0 0x01d90000 0 0x8000>; 2069 reg-names = "std", "ice"; 2070 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2071 phys = <&ufs_mem_phy>; 2072 phy-names = "ufsphy"; 2073 lanes-per-direction = <2>; 2074 #reset-cells = <1>; 2075 resets = <&gcc GCC_UFS_PHY_BCR>; 2076 reset-names = "rst"; 2077 2078 iommus = <&apps_smmu 0x300 0>; 2079 2080 clock-names = 2081 "core_clk", 2082 "bus_aggr_clk", 2083 "iface_clk", 2084 "core_clk_unipro", 2085 "ref_clk", 2086 "tx_lane0_sync_clk", 2087 "rx_lane0_sync_clk", 2088 "rx_lane1_sync_clk", 2089 "ice_core_clk"; 2090 clocks = 2091 <&gcc GCC_UFS_PHY_AXI_CLK>, 2092 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2093 <&gcc GCC_UFS_PHY_AHB_CLK>, 2094 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2095 <&rpmhcc RPMH_CXO_CLK>, 2096 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2097 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2098 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 2099 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2100 freq-table-hz = 2101 <37500000 300000000>, 2102 <0 0>, 2103 <0 0>, 2104 <37500000 300000000>, 2105 <0 0>, 2106 <0 0>, 2107 <0 0>, 2108 <0 0>, 2109 <0 300000000>; 2110 2111 status = "disabled"; 2112 }; 2113 2114 ufs_mem_phy: phy@1d87000 { 2115 compatible = "qcom,sm8150-qmp-ufs-phy"; 2116 reg = <0 0x01d87000 0 0x1000>; 2117 2118 clocks = <&rpmhcc RPMH_CXO_CLK>, 2119 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2120 <&gcc GCC_UFS_MEM_CLKREF_CLK>; 2121 clock-names = "ref", 2122 "ref_aux", 2123 "qref"; 2124 2125 power-domains = <&gcc UFS_PHY_GDSC>; 2126 2127 resets = <&ufs_mem_hc 0>; 2128 reset-names = "ufsphy"; 2129 2130 #phy-cells = <0>; 2131 2132 status = "disabled"; 2133 }; 2134 2135 cryptobam: dma-controller@1dc4000 { 2136 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2137 reg = <0 0x01dc4000 0 0x24000>; 2138 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2139 #dma-cells = <1>; 2140 qcom,ee = <0>; 2141 qcom,controlled-remotely; 2142 num-channels = <8>; 2143 qcom,num-ees = <2>; 2144 iommus = <&apps_smmu 0x502 0x0641>, 2145 <&apps_smmu 0x504 0x0011>, 2146 <&apps_smmu 0x506 0x0011>, 2147 <&apps_smmu 0x508 0x0011>, 2148 <&apps_smmu 0x512 0x0000>; 2149 }; 2150 2151 crypto: crypto@1dfa000 { 2152 compatible = "qcom,sm8150-qce", "qcom,qce"; 2153 reg = <0 0x01dfa000 0 0x6000>; 2154 dmas = <&cryptobam 4>, <&cryptobam 5>; 2155 dma-names = "rx", "tx"; 2156 iommus = <&apps_smmu 0x502 0x0641>, 2157 <&apps_smmu 0x504 0x0011>, 2158 <&apps_smmu 0x506 0x0011>, 2159 <&apps_smmu 0x508 0x0011>, 2160 <&apps_smmu 0x512 0x0000>; 2161 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>; 2162 interconnect-names = "memory"; 2163 }; 2164 2165 tcsr_mutex: hwlock@1f40000 { 2166 compatible = "qcom,tcsr-mutex"; 2167 reg = <0x0 0x01f40000 0x0 0x20000>; 2168 #hwlock-cells = <1>; 2169 }; 2170 2171 tcsr_regs_1: syscon@1f60000 { 2172 compatible = "qcom,sm8150-tcsr", "syscon"; 2173 reg = <0x0 0x01f60000 0x0 0x20000>; 2174 }; 2175 2176 remoteproc_slpi: remoteproc@2400000 { 2177 compatible = "qcom,sm8150-slpi-pas"; 2178 reg = <0x0 0x02400000 0x0 0x4040>; 2179 2180 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, 2181 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2182 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2183 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2184 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2185 interrupt-names = "wdog", "fatal", "ready", 2186 "handover", "stop-ack"; 2187 2188 clocks = <&rpmhcc RPMH_CXO_CLK>; 2189 clock-names = "xo"; 2190 2191 power-domains = <&rpmhpd SM8150_LCX>, 2192 <&rpmhpd SM8150_LMX>; 2193 power-domain-names = "lcx", "lmx"; 2194 2195 memory-region = <&slpi_mem>; 2196 2197 qcom,qmp = <&aoss_qmp>; 2198 2199 qcom,smem-states = <&slpi_smp2p_out 0>; 2200 qcom,smem-state-names = "stop"; 2201 2202 status = "disabled"; 2203 2204 glink-edge { 2205 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 2206 label = "dsps"; 2207 qcom,remote-pid = <3>; 2208 mboxes = <&apss_shared 24>; 2209 2210 fastrpc { 2211 compatible = "qcom,fastrpc"; 2212 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2213 label = "sdsp"; 2214 qcom,non-secure-domain; 2215 #address-cells = <1>; 2216 #size-cells = <0>; 2217 2218 compute-cb@1 { 2219 compatible = "qcom,fastrpc-compute-cb"; 2220 reg = <1>; 2221 iommus = <&apps_smmu 0x05a1 0x0>; 2222 }; 2223 2224 compute-cb@2 { 2225 compatible = "qcom,fastrpc-compute-cb"; 2226 reg = <2>; 2227 iommus = <&apps_smmu 0x05a2 0x0>; 2228 }; 2229 2230 compute-cb@3 { 2231 compatible = "qcom,fastrpc-compute-cb"; 2232 reg = <3>; 2233 iommus = <&apps_smmu 0x05a3 0x0>; 2234 /* note: shared-cb = <4> in downstream */ 2235 }; 2236 }; 2237 }; 2238 }; 2239 2240 gpu: gpu@2c00000 { 2241 compatible = "qcom,adreno-640.1", "qcom,adreno"; 2242 reg = <0 0x02c00000 0 0x40000>; 2243 reg-names = "kgsl_3d0_reg_memory"; 2244 2245 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2246 2247 iommus = <&adreno_smmu 0 0x401>; 2248 2249 operating-points-v2 = <&gpu_opp_table>; 2250 2251 qcom,gmu = <&gmu>; 2252 2253 nvmem-cells = <&gpu_speed_bin>; 2254 nvmem-cell-names = "speed_bin"; 2255 #cooling-cells = <2>; 2256 2257 status = "disabled"; 2258 2259 zap-shader { 2260 memory-region = <&gpu_mem>; 2261 }; 2262 2263 gpu_opp_table: opp-table { 2264 compatible = "operating-points-v2"; 2265 2266 opp-675000000 { 2267 opp-hz = /bits/ 64 <675000000>; 2268 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2269 opp-supported-hw = <0x2>; 2270 }; 2271 2272 opp-585000000 { 2273 opp-hz = /bits/ 64 <585000000>; 2274 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2275 opp-supported-hw = <0x3>; 2276 }; 2277 2278 opp-499200000 { 2279 opp-hz = /bits/ 64 <499200000>; 2280 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2281 opp-supported-hw = <0x3>; 2282 }; 2283 2284 opp-427000000 { 2285 opp-hz = /bits/ 64 <427000000>; 2286 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2287 opp-supported-hw = <0x3>; 2288 }; 2289 2290 opp-345000000 { 2291 opp-hz = /bits/ 64 <345000000>; 2292 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2293 opp-supported-hw = <0x3>; 2294 }; 2295 2296 opp-257000000 { 2297 opp-hz = /bits/ 64 <257000000>; 2298 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2299 opp-supported-hw = <0x3>; 2300 }; 2301 }; 2302 }; 2303 2304 gmu: gmu@2c6a000 { 2305 compatible = "qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; 2306 2307 reg = <0 0x02c6a000 0 0x30000>, 2308 <0 0x0b290000 0 0x10000>, 2309 <0 0x0b490000 0 0x10000>; 2310 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2311 2312 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2313 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2314 interrupt-names = "hfi", "gmu"; 2315 2316 clocks = <&gpucc GPU_CC_AHB_CLK>, 2317 <&gpucc GPU_CC_CX_GMU_CLK>, 2318 <&gpucc GPU_CC_CXO_CLK>, 2319 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2320 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2321 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2322 2323 power-domains = <&gpucc GPU_CX_GDSC>, 2324 <&gpucc GPU_GX_GDSC>; 2325 power-domain-names = "cx", "gx"; 2326 2327 iommus = <&adreno_smmu 5 0x400>; 2328 2329 operating-points-v2 = <&gmu_opp_table>; 2330 2331 status = "disabled"; 2332 2333 gmu_opp_table: opp-table { 2334 compatible = "operating-points-v2"; 2335 2336 opp-200000000 { 2337 opp-hz = /bits/ 64 <200000000>; 2338 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2339 }; 2340 }; 2341 }; 2342 2343 gpucc: clock-controller@2c90000 { 2344 compatible = "qcom,sm8150-gpucc"; 2345 reg = <0 0x02c90000 0 0x9000>; 2346 clocks = <&rpmhcc RPMH_CXO_CLK>, 2347 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2348 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2349 clock-names = "bi_tcxo", 2350 "gcc_gpu_gpll0_clk_src", 2351 "gcc_gpu_gpll0_div_clk_src"; 2352 #clock-cells = <1>; 2353 #reset-cells = <1>; 2354 #power-domain-cells = <1>; 2355 }; 2356 2357 adreno_smmu: iommu@2ca0000 { 2358 compatible = "qcom,sm8150-smmu-500", "qcom,adreno-smmu", 2359 "qcom,smmu-500", "arm,mmu-500"; 2360 reg = <0 0x02ca0000 0 0x10000>; 2361 #iommu-cells = <2>; 2362 #global-interrupts = <1>; 2363 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 2364 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2365 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2366 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2367 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2368 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2369 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2370 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2371 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 2372 clocks = <&gpucc GPU_CC_AHB_CLK>, 2373 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2374 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2375 clock-names = "ahb", "bus", "iface"; 2376 2377 power-domains = <&gpucc GPU_CX_GDSC>; 2378 }; 2379 2380 tlmm: pinctrl@3100000 { 2381 compatible = "qcom,sm8150-pinctrl"; 2382 reg = <0x0 0x03100000 0x0 0x300000>, 2383 <0x0 0x03500000 0x0 0x300000>, 2384 <0x0 0x03900000 0x0 0x300000>, 2385 <0x0 0x03D00000 0x0 0x300000>; 2386 reg-names = "west", "east", "north", "south"; 2387 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2388 gpio-ranges = <&tlmm 0 0 176>; 2389 gpio-controller; 2390 #gpio-cells = <2>; 2391 interrupt-controller; 2392 #interrupt-cells = <2>; 2393 wakeup-parent = <&pdc>; 2394 2395 qup_i2c0_default: qup-i2c0-default-state { 2396 pins = "gpio0", "gpio1"; 2397 function = "qup0"; 2398 drive-strength = <0x02>; 2399 bias-disable; 2400 }; 2401 2402 qup_spi0_default: qup-spi0-default-state { 2403 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 2404 function = "qup0"; 2405 drive-strength = <6>; 2406 bias-disable; 2407 }; 2408 2409 qup_i2c1_default: qup-i2c1-default-state { 2410 pins = "gpio114", "gpio115"; 2411 function = "qup1"; 2412 drive-strength = <2>; 2413 bias-disable; 2414 }; 2415 2416 qup_spi1_default: qup-spi1-default-state { 2417 pins = "gpio114", "gpio115", "gpio116", "gpio117"; 2418 function = "qup1"; 2419 drive-strength = <6>; 2420 bias-disable; 2421 }; 2422 2423 qup_i2c2_default: qup-i2c2-default-state { 2424 pins = "gpio126", "gpio127"; 2425 function = "qup2"; 2426 drive-strength = <2>; 2427 bias-disable; 2428 }; 2429 2430 qup_spi2_default: qup-spi2-default-state { 2431 pins = "gpio126", "gpio127", "gpio128", "gpio129"; 2432 function = "qup2"; 2433 drive-strength = <6>; 2434 bias-disable; 2435 }; 2436 2437 qup_i2c3_default: qup-i2c3-default-state { 2438 pins = "gpio144", "gpio145"; 2439 function = "qup3"; 2440 drive-strength = <2>; 2441 bias-disable; 2442 }; 2443 2444 qup_spi3_default: qup-spi3-default-state { 2445 pins = "gpio144", "gpio145", "gpio146", "gpio147"; 2446 function = "qup3"; 2447 drive-strength = <6>; 2448 bias-disable; 2449 }; 2450 2451 qup_i2c4_default: qup-i2c4-default-state { 2452 pins = "gpio51", "gpio52"; 2453 function = "qup4"; 2454 drive-strength = <2>; 2455 bias-disable; 2456 }; 2457 2458 qup_spi4_default: qup-spi4-default-state { 2459 pins = "gpio51", "gpio52", "gpio53", "gpio54"; 2460 function = "qup4"; 2461 drive-strength = <6>; 2462 bias-disable; 2463 }; 2464 2465 qup_i2c5_default: qup-i2c5-default-state { 2466 pins = "gpio121", "gpio122"; 2467 function = "qup5"; 2468 drive-strength = <2>; 2469 bias-disable; 2470 }; 2471 2472 qup_spi5_default: qup-spi5-default-state { 2473 pins = "gpio119", "gpio120", "gpio121", "gpio122"; 2474 function = "qup5"; 2475 drive-strength = <6>; 2476 bias-disable; 2477 }; 2478 2479 qup_i2c6_default: qup-i2c6-default-state { 2480 pins = "gpio6", "gpio7"; 2481 function = "qup6"; 2482 drive-strength = <2>; 2483 bias-disable; 2484 }; 2485 2486 qup_spi6_default: qup-spi6-default-state { 2487 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 2488 function = "qup6"; 2489 drive-strength = <6>; 2490 bias-disable; 2491 }; 2492 2493 qup_i2c7_default: qup-i2c7-default-state { 2494 pins = "gpio98", "gpio99"; 2495 function = "qup7"; 2496 drive-strength = <2>; 2497 bias-disable; 2498 }; 2499 2500 qup_spi7_default: qup-spi7-default-state { 2501 pins = "gpio98", "gpio99", "gpio100", "gpio101"; 2502 function = "qup7"; 2503 drive-strength = <6>; 2504 bias-disable; 2505 }; 2506 2507 qup_i2c8_default: qup-i2c8-default-state { 2508 pins = "gpio88", "gpio89"; 2509 function = "qup8"; 2510 drive-strength = <2>; 2511 bias-disable; 2512 }; 2513 2514 qup_spi8_default: qup-spi8-default-state { 2515 pins = "gpio88", "gpio89", "gpio90", "gpio91"; 2516 function = "qup8"; 2517 drive-strength = <6>; 2518 bias-disable; 2519 }; 2520 2521 qup_i2c9_default: qup-i2c9-default-state { 2522 pins = "gpio39", "gpio40"; 2523 function = "qup9"; 2524 drive-strength = <2>; 2525 bias-disable; 2526 }; 2527 2528 qup_spi9_default: qup-spi9-default-state { 2529 pins = "gpio39", "gpio40", "gpio41", "gpio42"; 2530 function = "qup9"; 2531 drive-strength = <6>; 2532 bias-disable; 2533 }; 2534 2535 qup_uart9_default: qup-uart9-default-state { 2536 pins = "gpio41", "gpio42"; 2537 function = "qup9"; 2538 drive-strength = <2>; 2539 bias-disable; 2540 }; 2541 2542 qup_i2c10_default: qup-i2c10-default-state { 2543 pins = "gpio9", "gpio10"; 2544 function = "qup10"; 2545 drive-strength = <2>; 2546 bias-disable; 2547 }; 2548 2549 qup_spi10_default: qup-spi10-default-state { 2550 pins = "gpio9", "gpio10", "gpio11", "gpio12"; 2551 function = "qup10"; 2552 drive-strength = <6>; 2553 bias-disable; 2554 }; 2555 2556 qup_i2c11_default: qup-i2c11-default-state { 2557 pins = "gpio94", "gpio95"; 2558 function = "qup11"; 2559 drive-strength = <2>; 2560 bias-disable; 2561 }; 2562 2563 qup_spi11_default: qup-spi11-default-state { 2564 pins = "gpio92", "gpio93", "gpio94", "gpio95"; 2565 function = "qup11"; 2566 drive-strength = <6>; 2567 bias-disable; 2568 }; 2569 2570 qup_i2c12_default: qup-i2c12-default-state { 2571 pins = "gpio83", "gpio84"; 2572 function = "qup12"; 2573 drive-strength = <2>; 2574 bias-disable; 2575 }; 2576 2577 qup_spi12_default: qup-spi12-default-state { 2578 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2579 function = "qup12"; 2580 drive-strength = <6>; 2581 bias-disable; 2582 }; 2583 2584 qup_i2c13_default: qup-i2c13-default-state { 2585 pins = "gpio43", "gpio44"; 2586 function = "qup13"; 2587 drive-strength = <2>; 2588 bias-disable; 2589 }; 2590 2591 qup_spi13_default: qup-spi13-default-state { 2592 pins = "gpio43", "gpio44", "gpio45", "gpio46"; 2593 function = "qup13"; 2594 drive-strength = <6>; 2595 bias-disable; 2596 }; 2597 2598 qup_i2c14_default: qup-i2c14-default-state { 2599 pins = "gpio47", "gpio48"; 2600 function = "qup14"; 2601 drive-strength = <2>; 2602 bias-disable; 2603 }; 2604 2605 qup_spi14_default: qup-spi14-default-state { 2606 pins = "gpio47", "gpio48", "gpio49", "gpio50"; 2607 function = "qup14"; 2608 drive-strength = <6>; 2609 bias-disable; 2610 }; 2611 2612 qup_i2c15_default: qup-i2c15-default-state { 2613 pins = "gpio27", "gpio28"; 2614 function = "qup15"; 2615 drive-strength = <2>; 2616 bias-disable; 2617 }; 2618 2619 qup_spi15_default: qup-spi15-default-state { 2620 pins = "gpio27", "gpio28", "gpio29", "gpio30"; 2621 function = "qup15"; 2622 drive-strength = <6>; 2623 bias-disable; 2624 }; 2625 2626 qup_i2c16_default: qup-i2c16-default-state { 2627 pins = "gpio86", "gpio85"; 2628 function = "qup16"; 2629 drive-strength = <2>; 2630 bias-disable; 2631 }; 2632 2633 qup_spi16_default: qup-spi16-default-state { 2634 pins = "gpio83", "gpio84", "gpio85", "gpio86"; 2635 function = "qup16"; 2636 drive-strength = <6>; 2637 bias-disable; 2638 }; 2639 2640 qup_i2c17_default: qup-i2c17-default-state { 2641 pins = "gpio55", "gpio56"; 2642 function = "qup17"; 2643 drive-strength = <2>; 2644 bias-disable; 2645 }; 2646 2647 qup_spi17_default: qup-spi17-default-state { 2648 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2649 function = "qup17"; 2650 drive-strength = <6>; 2651 bias-disable; 2652 }; 2653 2654 qup_i2c18_default: qup-i2c18-default-state { 2655 pins = "gpio23", "gpio24"; 2656 function = "qup18"; 2657 drive-strength = <2>; 2658 bias-disable; 2659 }; 2660 2661 qup_spi18_default: qup-spi18-default-state { 2662 pins = "gpio23", "gpio24", "gpio25", "gpio26"; 2663 function = "qup18"; 2664 drive-strength = <6>; 2665 bias-disable; 2666 }; 2667 2668 qup_i2c19_default: qup-i2c19-default-state { 2669 pins = "gpio57", "gpio58"; 2670 function = "qup19"; 2671 drive-strength = <2>; 2672 bias-disable; 2673 }; 2674 2675 qup_spi19_default: qup-spi19-default-state { 2676 pins = "gpio55", "gpio56", "gpio57", "gpio58"; 2677 function = "qup19"; 2678 drive-strength = <6>; 2679 bias-disable; 2680 }; 2681 2682 pcie0_default_state: pcie0-default-state { 2683 perst-pins { 2684 pins = "gpio35"; 2685 function = "gpio"; 2686 drive-strength = <2>; 2687 bias-pull-down; 2688 }; 2689 2690 clkreq-pins { 2691 pins = "gpio36"; 2692 function = "pci_e0"; 2693 drive-strength = <2>; 2694 bias-pull-up; 2695 }; 2696 2697 wake-pins { 2698 pins = "gpio37"; 2699 function = "gpio"; 2700 drive-strength = <2>; 2701 bias-pull-up; 2702 }; 2703 }; 2704 2705 pcie1_default_state: pcie1-default-state { 2706 perst-pins { 2707 pins = "gpio102"; 2708 function = "gpio"; 2709 drive-strength = <2>; 2710 bias-pull-down; 2711 }; 2712 2713 clkreq-pins { 2714 pins = "gpio103"; 2715 function = "pci_e1"; 2716 drive-strength = <2>; 2717 bias-pull-up; 2718 }; 2719 2720 wake-pins { 2721 pins = "gpio104"; 2722 function = "gpio"; 2723 drive-strength = <2>; 2724 bias-pull-up; 2725 }; 2726 }; 2727 }; 2728 2729 remoteproc_mpss: remoteproc@4080000 { 2730 compatible = "qcom,sm8150-mpss-pas"; 2731 reg = <0x0 0x04080000 0x0 0x4040>; 2732 2733 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2734 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2735 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2736 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2737 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2738 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2739 interrupt-names = "wdog", "fatal", "ready", "handover", 2740 "stop-ack", "shutdown-ack"; 2741 2742 clocks = <&rpmhcc RPMH_CXO_CLK>; 2743 clock-names = "xo"; 2744 2745 power-domains = <&rpmhpd SM8150_CX>, 2746 <&rpmhpd SM8150_MSS>; 2747 power-domain-names = "cx", "mss"; 2748 2749 memory-region = <&mpss_mem>; 2750 2751 qcom,qmp = <&aoss_qmp>; 2752 2753 qcom,smem-states = <&modem_smp2p_out 0>; 2754 qcom,smem-state-names = "stop"; 2755 2756 status = "disabled"; 2757 2758 glink-edge { 2759 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2760 label = "modem"; 2761 qcom,remote-pid = <1>; 2762 mboxes = <&apss_shared 12>; 2763 }; 2764 }; 2765 2766 stm@6002000 { 2767 compatible = "arm,coresight-stm", "arm,primecell"; 2768 reg = <0 0x06002000 0 0x1000>, 2769 <0 0x16280000 0 0x180000>; 2770 reg-names = "stm-base", "stm-stimulus-base"; 2771 2772 clocks = <&aoss_qmp>; 2773 clock-names = "apb_pclk"; 2774 2775 out-ports { 2776 port { 2777 stm_out: endpoint { 2778 remote-endpoint = <&funnel0_in7>; 2779 }; 2780 }; 2781 }; 2782 }; 2783 2784 funnel@6041000 { 2785 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2786 reg = <0 0x06041000 0 0x1000>; 2787 2788 clocks = <&aoss_qmp>; 2789 clock-names = "apb_pclk"; 2790 2791 out-ports { 2792 port { 2793 funnel0_out: endpoint { 2794 remote-endpoint = <&merge_funnel_in0>; 2795 }; 2796 }; 2797 }; 2798 2799 in-ports { 2800 #address-cells = <1>; 2801 #size-cells = <0>; 2802 2803 port@7 { 2804 reg = <7>; 2805 funnel0_in7: endpoint { 2806 remote-endpoint = <&stm_out>; 2807 }; 2808 }; 2809 }; 2810 }; 2811 2812 funnel@6042000 { 2813 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2814 reg = <0 0x06042000 0 0x1000>; 2815 2816 clocks = <&aoss_qmp>; 2817 clock-names = "apb_pclk"; 2818 2819 out-ports { 2820 port { 2821 funnel1_out: endpoint { 2822 remote-endpoint = <&merge_funnel_in1>; 2823 }; 2824 }; 2825 }; 2826 2827 in-ports { 2828 #address-cells = <1>; 2829 #size-cells = <0>; 2830 2831 port@4 { 2832 reg = <4>; 2833 funnel1_in4: endpoint { 2834 remote-endpoint = <&swao_replicator_out>; 2835 }; 2836 }; 2837 }; 2838 }; 2839 2840 funnel@6043000 { 2841 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2842 reg = <0 0x06043000 0 0x1000>; 2843 2844 clocks = <&aoss_qmp>; 2845 clock-names = "apb_pclk"; 2846 2847 out-ports { 2848 port { 2849 funnel2_out: endpoint { 2850 remote-endpoint = <&merge_funnel_in2>; 2851 }; 2852 }; 2853 }; 2854 2855 in-ports { 2856 #address-cells = <1>; 2857 #size-cells = <0>; 2858 2859 port@2 { 2860 reg = <2>; 2861 funnel2_in2: endpoint { 2862 remote-endpoint = <&apss_merge_funnel_out>; 2863 }; 2864 }; 2865 }; 2866 }; 2867 2868 funnel@6045000 { 2869 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2870 reg = <0 0x06045000 0 0x1000>; 2871 2872 clocks = <&aoss_qmp>; 2873 clock-names = "apb_pclk"; 2874 2875 out-ports { 2876 port { 2877 merge_funnel_out: endpoint { 2878 remote-endpoint = <&etf_in>; 2879 }; 2880 }; 2881 }; 2882 2883 in-ports { 2884 #address-cells = <1>; 2885 #size-cells = <0>; 2886 2887 port@0 { 2888 reg = <0>; 2889 merge_funnel_in0: endpoint { 2890 remote-endpoint = <&funnel0_out>; 2891 }; 2892 }; 2893 2894 port@1 { 2895 reg = <1>; 2896 merge_funnel_in1: endpoint { 2897 remote-endpoint = <&funnel1_out>; 2898 }; 2899 }; 2900 2901 port@2 { 2902 reg = <2>; 2903 merge_funnel_in2: endpoint { 2904 remote-endpoint = <&funnel2_out>; 2905 }; 2906 }; 2907 }; 2908 }; 2909 2910 replicator@6046000 { 2911 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2912 reg = <0 0x06046000 0 0x1000>; 2913 2914 clocks = <&aoss_qmp>; 2915 clock-names = "apb_pclk"; 2916 2917 out-ports { 2918 #address-cells = <1>; 2919 #size-cells = <0>; 2920 2921 port@0 { 2922 reg = <0>; 2923 replicator_out0: endpoint { 2924 remote-endpoint = <&etr_in>; 2925 }; 2926 }; 2927 2928 port@1 { 2929 reg = <1>; 2930 replicator_out1: endpoint { 2931 remote-endpoint = <&replicator1_in>; 2932 }; 2933 }; 2934 }; 2935 2936 in-ports { 2937 port { 2938 replicator_in0: endpoint { 2939 remote-endpoint = <&etf_out>; 2940 }; 2941 }; 2942 }; 2943 }; 2944 2945 etf@6047000 { 2946 compatible = "arm,coresight-tmc", "arm,primecell"; 2947 reg = <0 0x06047000 0 0x1000>; 2948 2949 clocks = <&aoss_qmp>; 2950 clock-names = "apb_pclk"; 2951 2952 out-ports { 2953 port { 2954 etf_out: endpoint { 2955 remote-endpoint = <&replicator_in0>; 2956 }; 2957 }; 2958 }; 2959 2960 in-ports { 2961 port { 2962 etf_in: endpoint { 2963 remote-endpoint = <&merge_funnel_out>; 2964 }; 2965 }; 2966 }; 2967 }; 2968 2969 etr@6048000 { 2970 compatible = "arm,coresight-tmc", "arm,primecell"; 2971 reg = <0 0x06048000 0 0x1000>; 2972 iommus = <&apps_smmu 0x05e0 0x0>; 2973 2974 clocks = <&aoss_qmp>; 2975 clock-names = "apb_pclk"; 2976 arm,scatter-gather; 2977 2978 in-ports { 2979 port { 2980 etr_in: endpoint { 2981 remote-endpoint = <&replicator_out0>; 2982 }; 2983 }; 2984 }; 2985 }; 2986 2987 replicator@604a000 { 2988 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2989 reg = <0 0x0604a000 0 0x1000>; 2990 2991 clocks = <&aoss_qmp>; 2992 clock-names = "apb_pclk"; 2993 2994 out-ports { 2995 #address-cells = <1>; 2996 #size-cells = <0>; 2997 2998 port@1 { 2999 reg = <1>; 3000 replicator1_out: endpoint { 3001 remote-endpoint = <&swao_funnel_in>; 3002 }; 3003 }; 3004 }; 3005 3006 in-ports { 3007 3008 port { 3009 replicator1_in: endpoint { 3010 remote-endpoint = <&replicator_out1>; 3011 }; 3012 }; 3013 }; 3014 }; 3015 3016 funnel@6b08000 { 3017 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3018 reg = <0 0x06b08000 0 0x1000>; 3019 3020 clocks = <&aoss_qmp>; 3021 clock-names = "apb_pclk"; 3022 3023 out-ports { 3024 port { 3025 swao_funnel_out: endpoint { 3026 remote-endpoint = <&swao_etf_in>; 3027 }; 3028 }; 3029 }; 3030 3031 in-ports { 3032 #address-cells = <1>; 3033 #size-cells = <0>; 3034 3035 port@6 { 3036 reg = <6>; 3037 swao_funnel_in: endpoint { 3038 remote-endpoint = <&replicator1_out>; 3039 }; 3040 }; 3041 }; 3042 }; 3043 3044 etf@6b09000 { 3045 compatible = "arm,coresight-tmc", "arm,primecell"; 3046 reg = <0 0x06b09000 0 0x1000>; 3047 3048 clocks = <&aoss_qmp>; 3049 clock-names = "apb_pclk"; 3050 3051 out-ports { 3052 port { 3053 swao_etf_out: endpoint { 3054 remote-endpoint = <&swao_replicator_in>; 3055 }; 3056 }; 3057 }; 3058 3059 in-ports { 3060 port { 3061 swao_etf_in: endpoint { 3062 remote-endpoint = <&swao_funnel_out>; 3063 }; 3064 }; 3065 }; 3066 }; 3067 3068 replicator@6b0a000 { 3069 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3070 reg = <0 0x06b0a000 0 0x1000>; 3071 3072 clocks = <&aoss_qmp>; 3073 clock-names = "apb_pclk"; 3074 qcom,replicator-loses-context; 3075 3076 out-ports { 3077 port { 3078 swao_replicator_out: endpoint { 3079 remote-endpoint = <&funnel1_in4>; 3080 }; 3081 }; 3082 }; 3083 3084 in-ports { 3085 port { 3086 swao_replicator_in: endpoint { 3087 remote-endpoint = <&swao_etf_out>; 3088 }; 3089 }; 3090 }; 3091 }; 3092 3093 etm@7040000 { 3094 compatible = "arm,coresight-etm4x", "arm,primecell"; 3095 reg = <0 0x07040000 0 0x1000>; 3096 3097 cpu = <&CPU0>; 3098 3099 clocks = <&aoss_qmp>; 3100 clock-names = "apb_pclk"; 3101 arm,coresight-loses-context-with-cpu; 3102 qcom,skip-power-up; 3103 3104 out-ports { 3105 port { 3106 etm0_out: endpoint { 3107 remote-endpoint = <&apss_funnel_in0>; 3108 }; 3109 }; 3110 }; 3111 }; 3112 3113 etm@7140000 { 3114 compatible = "arm,coresight-etm4x", "arm,primecell"; 3115 reg = <0 0x07140000 0 0x1000>; 3116 3117 cpu = <&CPU1>; 3118 3119 clocks = <&aoss_qmp>; 3120 clock-names = "apb_pclk"; 3121 arm,coresight-loses-context-with-cpu; 3122 qcom,skip-power-up; 3123 3124 out-ports { 3125 port { 3126 etm1_out: endpoint { 3127 remote-endpoint = <&apss_funnel_in1>; 3128 }; 3129 }; 3130 }; 3131 }; 3132 3133 etm@7240000 { 3134 compatible = "arm,coresight-etm4x", "arm,primecell"; 3135 reg = <0 0x07240000 0 0x1000>; 3136 3137 cpu = <&CPU2>; 3138 3139 clocks = <&aoss_qmp>; 3140 clock-names = "apb_pclk"; 3141 arm,coresight-loses-context-with-cpu; 3142 qcom,skip-power-up; 3143 3144 out-ports { 3145 port { 3146 etm2_out: endpoint { 3147 remote-endpoint = <&apss_funnel_in2>; 3148 }; 3149 }; 3150 }; 3151 }; 3152 3153 etm@7340000 { 3154 compatible = "arm,coresight-etm4x", "arm,primecell"; 3155 reg = <0 0x07340000 0 0x1000>; 3156 3157 cpu = <&CPU3>; 3158 3159 clocks = <&aoss_qmp>; 3160 clock-names = "apb_pclk"; 3161 arm,coresight-loses-context-with-cpu; 3162 qcom,skip-power-up; 3163 3164 out-ports { 3165 port { 3166 etm3_out: endpoint { 3167 remote-endpoint = <&apss_funnel_in3>; 3168 }; 3169 }; 3170 }; 3171 }; 3172 3173 etm@7440000 { 3174 compatible = "arm,coresight-etm4x", "arm,primecell"; 3175 reg = <0 0x07440000 0 0x1000>; 3176 3177 cpu = <&CPU4>; 3178 3179 clocks = <&aoss_qmp>; 3180 clock-names = "apb_pclk"; 3181 arm,coresight-loses-context-with-cpu; 3182 qcom,skip-power-up; 3183 3184 out-ports { 3185 port { 3186 etm4_out: endpoint { 3187 remote-endpoint = <&apss_funnel_in4>; 3188 }; 3189 }; 3190 }; 3191 }; 3192 3193 etm@7540000 { 3194 compatible = "arm,coresight-etm4x", "arm,primecell"; 3195 reg = <0 0x07540000 0 0x1000>; 3196 3197 cpu = <&CPU5>; 3198 3199 clocks = <&aoss_qmp>; 3200 clock-names = "apb_pclk"; 3201 arm,coresight-loses-context-with-cpu; 3202 qcom,skip-power-up; 3203 3204 out-ports { 3205 port { 3206 etm5_out: endpoint { 3207 remote-endpoint = <&apss_funnel_in5>; 3208 }; 3209 }; 3210 }; 3211 }; 3212 3213 etm@7640000 { 3214 compatible = "arm,coresight-etm4x", "arm,primecell"; 3215 reg = <0 0x07640000 0 0x1000>; 3216 3217 cpu = <&CPU6>; 3218 3219 clocks = <&aoss_qmp>; 3220 clock-names = "apb_pclk"; 3221 arm,coresight-loses-context-with-cpu; 3222 qcom,skip-power-up; 3223 3224 out-ports { 3225 port { 3226 etm6_out: endpoint { 3227 remote-endpoint = <&apss_funnel_in6>; 3228 }; 3229 }; 3230 }; 3231 }; 3232 3233 etm@7740000 { 3234 compatible = "arm,coresight-etm4x", "arm,primecell"; 3235 reg = <0 0x07740000 0 0x1000>; 3236 3237 cpu = <&CPU7>; 3238 3239 clocks = <&aoss_qmp>; 3240 clock-names = "apb_pclk"; 3241 arm,coresight-loses-context-with-cpu; 3242 qcom,skip-power-up; 3243 3244 out-ports { 3245 port { 3246 etm7_out: endpoint { 3247 remote-endpoint = <&apss_funnel_in7>; 3248 }; 3249 }; 3250 }; 3251 }; 3252 3253 funnel@7800000 { /* APSS Funnel */ 3254 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3255 reg = <0 0x07800000 0 0x1000>; 3256 3257 clocks = <&aoss_qmp>; 3258 clock-names = "apb_pclk"; 3259 3260 out-ports { 3261 port { 3262 apss_funnel_out: endpoint { 3263 remote-endpoint = <&apss_merge_funnel_in>; 3264 }; 3265 }; 3266 }; 3267 3268 in-ports { 3269 #address-cells = <1>; 3270 #size-cells = <0>; 3271 3272 port@0 { 3273 reg = <0>; 3274 apss_funnel_in0: endpoint { 3275 remote-endpoint = <&etm0_out>; 3276 }; 3277 }; 3278 3279 port@1 { 3280 reg = <1>; 3281 apss_funnel_in1: endpoint { 3282 remote-endpoint = <&etm1_out>; 3283 }; 3284 }; 3285 3286 port@2 { 3287 reg = <2>; 3288 apss_funnel_in2: endpoint { 3289 remote-endpoint = <&etm2_out>; 3290 }; 3291 }; 3292 3293 port@3 { 3294 reg = <3>; 3295 apss_funnel_in3: endpoint { 3296 remote-endpoint = <&etm3_out>; 3297 }; 3298 }; 3299 3300 port@4 { 3301 reg = <4>; 3302 apss_funnel_in4: endpoint { 3303 remote-endpoint = <&etm4_out>; 3304 }; 3305 }; 3306 3307 port@5 { 3308 reg = <5>; 3309 apss_funnel_in5: endpoint { 3310 remote-endpoint = <&etm5_out>; 3311 }; 3312 }; 3313 3314 port@6 { 3315 reg = <6>; 3316 apss_funnel_in6: endpoint { 3317 remote-endpoint = <&etm6_out>; 3318 }; 3319 }; 3320 3321 port@7 { 3322 reg = <7>; 3323 apss_funnel_in7: endpoint { 3324 remote-endpoint = <&etm7_out>; 3325 }; 3326 }; 3327 }; 3328 }; 3329 3330 funnel@7810000 { 3331 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3332 reg = <0 0x07810000 0 0x1000>; 3333 3334 clocks = <&aoss_qmp>; 3335 clock-names = "apb_pclk"; 3336 3337 out-ports { 3338 port { 3339 apss_merge_funnel_out: endpoint { 3340 remote-endpoint = <&funnel2_in2>; 3341 }; 3342 }; 3343 }; 3344 3345 in-ports { 3346 port { 3347 apss_merge_funnel_in: endpoint { 3348 remote-endpoint = <&apss_funnel_out>; 3349 }; 3350 }; 3351 }; 3352 }; 3353 3354 remoteproc_cdsp: remoteproc@8300000 { 3355 compatible = "qcom,sm8150-cdsp-pas"; 3356 reg = <0x0 0x08300000 0x0 0x4040>; 3357 3358 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3359 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3360 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3361 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3362 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3363 interrupt-names = "wdog", "fatal", "ready", 3364 "handover", "stop-ack"; 3365 3366 clocks = <&rpmhcc RPMH_CXO_CLK>; 3367 clock-names = "xo"; 3368 3369 power-domains = <&rpmhpd SM8150_CX>; 3370 3371 memory-region = <&cdsp_mem>; 3372 3373 qcom,qmp = <&aoss_qmp>; 3374 3375 qcom,smem-states = <&cdsp_smp2p_out 0>; 3376 qcom,smem-state-names = "stop"; 3377 3378 status = "disabled"; 3379 3380 glink-edge { 3381 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 3382 label = "cdsp"; 3383 qcom,remote-pid = <5>; 3384 mboxes = <&apss_shared 4>; 3385 3386 fastrpc { 3387 compatible = "qcom,fastrpc"; 3388 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3389 label = "cdsp"; 3390 qcom,non-secure-domain; 3391 #address-cells = <1>; 3392 #size-cells = <0>; 3393 3394 compute-cb@1 { 3395 compatible = "qcom,fastrpc-compute-cb"; 3396 reg = <1>; 3397 iommus = <&apps_smmu 0x1001 0x0460>; 3398 }; 3399 3400 compute-cb@2 { 3401 compatible = "qcom,fastrpc-compute-cb"; 3402 reg = <2>; 3403 iommus = <&apps_smmu 0x1002 0x0460>; 3404 }; 3405 3406 compute-cb@3 { 3407 compatible = "qcom,fastrpc-compute-cb"; 3408 reg = <3>; 3409 iommus = <&apps_smmu 0x1003 0x0460>; 3410 }; 3411 3412 compute-cb@4 { 3413 compatible = "qcom,fastrpc-compute-cb"; 3414 reg = <4>; 3415 iommus = <&apps_smmu 0x1004 0x0460>; 3416 }; 3417 3418 compute-cb@5 { 3419 compatible = "qcom,fastrpc-compute-cb"; 3420 reg = <5>; 3421 iommus = <&apps_smmu 0x1005 0x0460>; 3422 }; 3423 3424 compute-cb@6 { 3425 compatible = "qcom,fastrpc-compute-cb"; 3426 reg = <6>; 3427 iommus = <&apps_smmu 0x1006 0x0460>; 3428 }; 3429 3430 compute-cb@7 { 3431 compatible = "qcom,fastrpc-compute-cb"; 3432 reg = <7>; 3433 iommus = <&apps_smmu 0x1007 0x0460>; 3434 }; 3435 3436 compute-cb@8 { 3437 compatible = "qcom,fastrpc-compute-cb"; 3438 reg = <8>; 3439 iommus = <&apps_smmu 0x1008 0x0460>; 3440 }; 3441 3442 /* note: secure cb9 in downstream */ 3443 }; 3444 }; 3445 }; 3446 3447 usb_1_hsphy: phy@88e2000 { 3448 compatible = "qcom,sm8150-usb-hs-phy", 3449 "qcom,usb-snps-hs-7nm-phy"; 3450 reg = <0 0x088e2000 0 0x400>; 3451 status = "disabled"; 3452 #phy-cells = <0>; 3453 3454 clocks = <&rpmhcc RPMH_CXO_CLK>; 3455 clock-names = "ref"; 3456 3457 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3458 }; 3459 3460 usb_2_hsphy: phy@88e3000 { 3461 compatible = "qcom,sm8150-usb-hs-phy", 3462 "qcom,usb-snps-hs-7nm-phy"; 3463 reg = <0 0x088e3000 0 0x400>; 3464 status = "disabled"; 3465 #phy-cells = <0>; 3466 3467 clocks = <&rpmhcc RPMH_CXO_CLK>; 3468 clock-names = "ref"; 3469 3470 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3471 }; 3472 3473 usb_1_qmpphy: phy@88e8000 { 3474 compatible = "qcom,sm8150-qmp-usb3-dp-phy"; 3475 reg = <0 0x088e8000 0 0x3000>; 3476 3477 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3478 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 3479 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3480 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3481 clock-names = "aux", 3482 "ref", 3483 "com_aux", 3484 "usb3_pipe"; 3485 3486 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3487 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3488 reset-names = "phy", "common"; 3489 3490 #clock-cells = <1>; 3491 #phy-cells = <1>; 3492 3493 status = "disabled"; 3494 3495 ports { 3496 #address-cells = <1>; 3497 #size-cells = <0>; 3498 3499 port@0 { 3500 reg = <0>; 3501 3502 usb_1_qmpphy_out: endpoint { 3503 }; 3504 }; 3505 3506 port@1 { 3507 reg = <1>; 3508 3509 usb_1_qmpphy_usb_ss_in: endpoint { 3510 }; 3511 }; 3512 3513 port@2 { 3514 reg = <2>; 3515 3516 usb_1_qmpphy_dp_in: endpoint { 3517 }; 3518 }; 3519 }; 3520 }; 3521 3522 usb_2_qmpphy: phy@88eb000 { 3523 compatible = "qcom,sm8150-qmp-usb3-uni-phy"; 3524 reg = <0 0x088eb000 0 0x1000>; 3525 3526 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3527 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 3528 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 3529 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3530 clock-names = "aux", 3531 "ref", 3532 "com_aux", 3533 "pipe"; 3534 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3535 #clock-cells = <0>; 3536 #phy-cells = <0>; 3537 3538 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 3539 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 3540 reset-names = "phy", 3541 "phy_phy"; 3542 3543 status = "disabled"; 3544 }; 3545 3546 sdhc_2: mmc@8804000 { 3547 compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5"; 3548 reg = <0 0x08804000 0 0x1000>; 3549 3550 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3551 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3552 interrupt-names = "hc_irq", "pwr_irq"; 3553 3554 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3555 <&gcc GCC_SDCC2_APPS_CLK>, 3556 <&rpmhcc RPMH_CXO_CLK>; 3557 clock-names = "iface", "core", "xo"; 3558 iommus = <&apps_smmu 0x6a0 0x0>; 3559 qcom,dll-config = <0x0007642c>; 3560 qcom,ddr-config = <0x80040868>; 3561 power-domains = <&rpmhpd 0>; 3562 operating-points-v2 = <&sdhc2_opp_table>; 3563 3564 status = "disabled"; 3565 3566 sdhc2_opp_table: opp-table { 3567 compatible = "operating-points-v2"; 3568 3569 opp-19200000 { 3570 opp-hz = /bits/ 64 <19200000>; 3571 required-opps = <&rpmhpd_opp_min_svs>; 3572 }; 3573 3574 opp-50000000 { 3575 opp-hz = /bits/ 64 <50000000>; 3576 required-opps = <&rpmhpd_opp_low_svs>; 3577 }; 3578 3579 opp-100000000 { 3580 opp-hz = /bits/ 64 <100000000>; 3581 required-opps = <&rpmhpd_opp_svs>; 3582 }; 3583 3584 opp-202000000 { 3585 opp-hz = /bits/ 64 <202000000>; 3586 required-opps = <&rpmhpd_opp_svs_l1>; 3587 }; 3588 }; 3589 }; 3590 3591 dc_noc: interconnect@9160000 { 3592 compatible = "qcom,sm8150-dc-noc"; 3593 reg = <0 0x09160000 0 0x3200>; 3594 #interconnect-cells = <2>; 3595 qcom,bcm-voters = <&apps_bcm_voter>; 3596 }; 3597 3598 gem_noc: interconnect@9680000 { 3599 compatible = "qcom,sm8150-gem-noc"; 3600 reg = <0 0x09680000 0 0x3e200>; 3601 #interconnect-cells = <2>; 3602 qcom,bcm-voters = <&apps_bcm_voter>; 3603 }; 3604 3605 usb_1: usb@a6f8800 { 3606 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3607 reg = <0 0x0a6f8800 0 0x400>; 3608 status = "disabled"; 3609 #address-cells = <2>; 3610 #size-cells = <2>; 3611 ranges; 3612 dma-ranges; 3613 3614 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3615 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3616 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3617 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3618 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3619 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3620 clock-names = "cfg_noc", 3621 "core", 3622 "iface", 3623 "sleep", 3624 "mock_utmi", 3625 "xo"; 3626 3627 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3628 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3629 assigned-clock-rates = <19200000>, <200000000>; 3630 3631 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 3632 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3633 <&pdc 9 IRQ_TYPE_EDGE_BOTH>, 3634 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 3635 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; 3636 interrupt-names = "pwr_event", 3637 "hs_phy_irq", 3638 "dp_hs_phy_irq", 3639 "dm_hs_phy_irq", 3640 "ss_phy_irq"; 3641 3642 power-domains = <&gcc USB30_PRIM_GDSC>; 3643 3644 resets = <&gcc GCC_USB30_PRIM_BCR>; 3645 3646 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, 3647 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 3648 interconnect-names = "usb-ddr", "apps-usb"; 3649 3650 usb_1_dwc3: usb@a600000 { 3651 compatible = "snps,dwc3"; 3652 reg = <0 0x0a600000 0 0xcd00>; 3653 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3654 iommus = <&apps_smmu 0x140 0>; 3655 snps,dis_u2_susphy_quirk; 3656 snps,dis_enblslpm_quirk; 3657 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 3658 phy-names = "usb2-phy", "usb3-phy"; 3659 3660 ports { 3661 #address-cells = <1>; 3662 #size-cells = <0>; 3663 3664 port@0 { 3665 reg = <0>; 3666 3667 usb_1_dwc3_hs: endpoint { 3668 }; 3669 }; 3670 3671 port@1 { 3672 reg = <1>; 3673 3674 usb_1_dwc3_ss: endpoint { 3675 }; 3676 }; 3677 }; 3678 }; 3679 }; 3680 3681 usb_2: usb@a8f8800 { 3682 compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; 3683 reg = <0 0x0a8f8800 0 0x400>; 3684 status = "disabled"; 3685 #address-cells = <2>; 3686 #size-cells = <2>; 3687 ranges; 3688 dma-ranges; 3689 3690 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3691 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3692 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3693 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3694 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3695 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 3696 clock-names = "cfg_noc", 3697 "core", 3698 "iface", 3699 "sleep", 3700 "mock_utmi", 3701 "xo"; 3702 3703 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3704 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3705 assigned-clock-rates = <19200000>, <200000000>; 3706 3707 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 3708 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3709 <&pdc 11 IRQ_TYPE_EDGE_BOTH>, 3710 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 3711 <&pdc 7 IRQ_TYPE_LEVEL_HIGH>; 3712 interrupt-names = "pwr_event", 3713 "hs_phy_irq", 3714 "dp_hs_phy_irq", 3715 "dm_hs_phy_irq", 3716 "ss_phy_irq"; 3717 3718 power-domains = <&gcc USB30_SEC_GDSC>; 3719 3720 resets = <&gcc GCC_USB30_SEC_BCR>; 3721 3722 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, 3723 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; 3724 interconnect-names = "usb-ddr", "apps-usb"; 3725 3726 usb_2_dwc3: usb@a800000 { 3727 compatible = "snps,dwc3"; 3728 reg = <0 0x0a800000 0 0xcd00>; 3729 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 3730 iommus = <&apps_smmu 0x160 0>; 3731 snps,dis_u2_susphy_quirk; 3732 snps,dis_enblslpm_quirk; 3733 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>; 3734 phy-names = "usb2-phy", "usb3-phy"; 3735 }; 3736 }; 3737 3738 camnoc_virt: interconnect@ac00000 { 3739 compatible = "qcom,sm8150-camnoc-virt"; 3740 reg = <0 0x0ac00000 0 0x1000>; 3741 #interconnect-cells = <2>; 3742 qcom,bcm-voters = <&apps_bcm_voter>; 3743 }; 3744 3745 mdss: display-subsystem@ae00000 { 3746 compatible = "qcom,sm8150-mdss"; 3747 reg = <0 0x0ae00000 0 0x1000>; 3748 reg-names = "mdss"; 3749 3750 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>, 3751 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>; 3752 interconnect-names = "mdp0-mem", "mdp1-mem"; 3753 3754 power-domains = <&dispcc MDSS_GDSC>; 3755 3756 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3757 <&gcc GCC_DISP_HF_AXI_CLK>, 3758 <&gcc GCC_DISP_SF_AXI_CLK>, 3759 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3760 clock-names = "iface", "bus", "nrt_bus", "core"; 3761 3762 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3763 interrupt-controller; 3764 #interrupt-cells = <1>; 3765 3766 iommus = <&apps_smmu 0x800 0x420>; 3767 3768 status = "disabled"; 3769 3770 #address-cells = <2>; 3771 #size-cells = <2>; 3772 ranges; 3773 3774 mdss_mdp: display-controller@ae01000 { 3775 compatible = "qcom,sm8150-dpu"; 3776 reg = <0 0x0ae01000 0 0x8f000>, 3777 <0 0x0aeb0000 0 0x2008>; 3778 reg-names = "mdp", "vbif"; 3779 3780 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3781 <&gcc GCC_DISP_HF_AXI_CLK>, 3782 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3783 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3784 clock-names = "iface", "bus", "core", "vsync"; 3785 3786 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3787 assigned-clock-rates = <19200000>; 3788 3789 operating-points-v2 = <&mdp_opp_table>; 3790 power-domains = <&rpmhpd SM8150_MMCX>; 3791 3792 interrupt-parent = <&mdss>; 3793 interrupts = <0>; 3794 3795 ports { 3796 #address-cells = <1>; 3797 #size-cells = <0>; 3798 3799 port@0 { 3800 reg = <0>; 3801 dpu_intf1_out: endpoint { 3802 remote-endpoint = <&mdss_dsi0_in>; 3803 }; 3804 }; 3805 3806 port@1 { 3807 reg = <1>; 3808 dpu_intf2_out: endpoint { 3809 remote-endpoint = <&mdss_dsi1_in>; 3810 }; 3811 }; 3812 3813 port@2 { 3814 reg = <2>; 3815 dpu_intf0_out: endpoint { 3816 remote-endpoint = <&mdss_dp_in>; 3817 }; 3818 }; 3819 }; 3820 3821 mdp_opp_table: opp-table { 3822 compatible = "operating-points-v2"; 3823 3824 opp-171428571 { 3825 opp-hz = /bits/ 64 <171428571>; 3826 required-opps = <&rpmhpd_opp_low_svs>; 3827 }; 3828 3829 opp-300000000 { 3830 opp-hz = /bits/ 64 <300000000>; 3831 required-opps = <&rpmhpd_opp_svs>; 3832 }; 3833 3834 opp-345000000 { 3835 opp-hz = /bits/ 64 <345000000>; 3836 required-opps = <&rpmhpd_opp_svs_l1>; 3837 }; 3838 3839 opp-460000000 { 3840 opp-hz = /bits/ 64 <460000000>; 3841 required-opps = <&rpmhpd_opp_nom>; 3842 }; 3843 }; 3844 }; 3845 3846 mdss_dp: displayport-controller@ae90000 { 3847 compatible = "qcom,sm8150-dp", "qcom,sm8350-dp"; 3848 reg = <0 0xae90000 0 0x200>, 3849 <0 0xae90200 0 0x200>, 3850 <0 0xae90400 0 0x600>, 3851 <0 0x0ae90a00 0 0x600>, 3852 <0 0x0ae91000 0 0x600>; 3853 3854 interrupt-parent = <&mdss>; 3855 interrupts = <12>; 3856 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3857 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3858 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3859 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3860 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3861 clock-names = "core_iface", 3862 "core_aux", 3863 "ctrl_link", 3864 "ctrl_link_iface", 3865 "stream_pixel"; 3866 3867 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3868 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3869 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3870 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3871 3872 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 3873 phy-names = "dp"; 3874 3875 #sound-dai-cells = <0>; 3876 3877 operating-points-v2 = <&dp_opp_table>; 3878 power-domains = <&rpmhpd SM8250_MMCX>; 3879 3880 status = "disabled"; 3881 3882 ports { 3883 #address-cells = <1>; 3884 #size-cells = <0>; 3885 3886 port@0 { 3887 reg = <0>; 3888 mdss_dp_in: endpoint { 3889 remote-endpoint = <&dpu_intf0_out>; 3890 }; 3891 }; 3892 3893 port@1 { 3894 reg = <1>; 3895 3896 mdss_dp_out: endpoint { 3897 }; 3898 }; 3899 }; 3900 3901 dp_opp_table: opp-table { 3902 compatible = "operating-points-v2"; 3903 3904 opp-160000000 { 3905 opp-hz = /bits/ 64 <160000000>; 3906 required-opps = <&rpmhpd_opp_low_svs>; 3907 }; 3908 3909 opp-270000000 { 3910 opp-hz = /bits/ 64 <270000000>; 3911 required-opps = <&rpmhpd_opp_svs>; 3912 }; 3913 3914 opp-540000000 { 3915 opp-hz = /bits/ 64 <540000000>; 3916 required-opps = <&rpmhpd_opp_svs_l1>; 3917 }; 3918 3919 opp-810000000 { 3920 opp-hz = /bits/ 64 <810000000>; 3921 required-opps = <&rpmhpd_opp_nom>; 3922 }; 3923 }; 3924 }; 3925 3926 mdss_dsi0: dsi@ae94000 { 3927 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3928 reg = <0 0x0ae94000 0 0x400>; 3929 reg-names = "dsi_ctrl"; 3930 3931 interrupt-parent = <&mdss>; 3932 interrupts = <4>; 3933 3934 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3935 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3936 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3937 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3938 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3939 <&gcc GCC_DISP_HF_AXI_CLK>; 3940 clock-names = "byte", 3941 "byte_intf", 3942 "pixel", 3943 "core", 3944 "iface", 3945 "bus"; 3946 3947 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 3948 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3949 assigned-clock-parents = <&mdss_dsi0_phy 0>, 3950 <&mdss_dsi0_phy 1>; 3951 3952 operating-points-v2 = <&dsi_opp_table>; 3953 power-domains = <&rpmhpd SM8150_MMCX>; 3954 3955 phys = <&mdss_dsi0_phy>; 3956 3957 status = "disabled"; 3958 3959 #address-cells = <1>; 3960 #size-cells = <0>; 3961 3962 ports { 3963 #address-cells = <1>; 3964 #size-cells = <0>; 3965 3966 port@0 { 3967 reg = <0>; 3968 mdss_dsi0_in: endpoint { 3969 remote-endpoint = <&dpu_intf1_out>; 3970 }; 3971 }; 3972 3973 port@1 { 3974 reg = <1>; 3975 mdss_dsi0_out: endpoint { 3976 }; 3977 }; 3978 }; 3979 3980 dsi_opp_table: opp-table { 3981 compatible = "operating-points-v2"; 3982 3983 opp-187500000 { 3984 opp-hz = /bits/ 64 <187500000>; 3985 required-opps = <&rpmhpd_opp_low_svs>; 3986 }; 3987 3988 opp-300000000 { 3989 opp-hz = /bits/ 64 <300000000>; 3990 required-opps = <&rpmhpd_opp_svs>; 3991 }; 3992 3993 opp-358000000 { 3994 opp-hz = /bits/ 64 <358000000>; 3995 required-opps = <&rpmhpd_opp_svs_l1>; 3996 }; 3997 }; 3998 }; 3999 4000 mdss_dsi0_phy: phy@ae94400 { 4001 compatible = "qcom,dsi-phy-7nm-8150"; 4002 reg = <0 0x0ae94400 0 0x200>, 4003 <0 0x0ae94600 0 0x280>, 4004 <0 0x0ae94900 0 0x260>; 4005 reg-names = "dsi_phy", 4006 "dsi_phy_lane", 4007 "dsi_pll"; 4008 4009 #clock-cells = <1>; 4010 #phy-cells = <0>; 4011 4012 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4013 <&rpmhcc RPMH_CXO_CLK>; 4014 clock-names = "iface", "ref"; 4015 4016 status = "disabled"; 4017 }; 4018 4019 mdss_dsi1: dsi@ae96000 { 4020 compatible = "qcom,sm8150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 4021 reg = <0 0x0ae96000 0 0x400>; 4022 reg-names = "dsi_ctrl"; 4023 4024 interrupt-parent = <&mdss>; 4025 interrupts = <5>; 4026 4027 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 4028 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 4029 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 4030 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 4031 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4032 <&gcc GCC_DISP_HF_AXI_CLK>; 4033 clock-names = "byte", 4034 "byte_intf", 4035 "pixel", 4036 "core", 4037 "iface", 4038 "bus"; 4039 4040 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 4041 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 4042 assigned-clock-parents = <&mdss_dsi1_phy 0>, 4043 <&mdss_dsi1_phy 1>; 4044 4045 operating-points-v2 = <&dsi_opp_table>; 4046 power-domains = <&rpmhpd SM8150_MMCX>; 4047 4048 phys = <&mdss_dsi1_phy>; 4049 4050 status = "disabled"; 4051 4052 #address-cells = <1>; 4053 #size-cells = <0>; 4054 4055 ports { 4056 #address-cells = <1>; 4057 #size-cells = <0>; 4058 4059 port@0 { 4060 reg = <0>; 4061 mdss_dsi1_in: endpoint { 4062 remote-endpoint = <&dpu_intf2_out>; 4063 }; 4064 }; 4065 4066 port@1 { 4067 reg = <1>; 4068 mdss_dsi1_out: endpoint { 4069 }; 4070 }; 4071 }; 4072 }; 4073 4074 mdss_dsi1_phy: phy@ae96400 { 4075 compatible = "qcom,dsi-phy-7nm-8150"; 4076 reg = <0 0x0ae96400 0 0x200>, 4077 <0 0x0ae96600 0 0x280>, 4078 <0 0x0ae96900 0 0x260>; 4079 reg-names = "dsi_phy", 4080 "dsi_phy_lane", 4081 "dsi_pll"; 4082 4083 #clock-cells = <1>; 4084 #phy-cells = <0>; 4085 4086 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4087 <&rpmhcc RPMH_CXO_CLK>; 4088 clock-names = "iface", "ref"; 4089 4090 status = "disabled"; 4091 }; 4092 }; 4093 4094 dispcc: clock-controller@af00000 { 4095 compatible = "qcom,sm8150-dispcc"; 4096 reg = <0 0x0af00000 0 0x10000>; 4097 clocks = <&rpmhcc RPMH_CXO_CLK>, 4098 <&mdss_dsi0_phy 0>, 4099 <&mdss_dsi0_phy 1>, 4100 <&mdss_dsi1_phy 0>, 4101 <&mdss_dsi1_phy 1>, 4102 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4103 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4104 clock-names = "bi_tcxo", 4105 "dsi0_phy_pll_out_byteclk", 4106 "dsi0_phy_pll_out_dsiclk", 4107 "dsi1_phy_pll_out_byteclk", 4108 "dsi1_phy_pll_out_dsiclk", 4109 "dp_phy_pll_link_clk", 4110 "dp_phy_pll_vco_div_clk"; 4111 power-domains = <&rpmhpd SM8150_MMCX>; 4112 required-opps = <&rpmhpd_opp_low_svs>; 4113 #clock-cells = <1>; 4114 #reset-cells = <1>; 4115 #power-domain-cells = <1>; 4116 }; 4117 4118 pdc: interrupt-controller@b220000 { 4119 compatible = "qcom,sm8150-pdc", "qcom,pdc"; 4120 reg = <0 0x0b220000 0 0x30000>; 4121 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 4122 <125 63 1>; 4123 #interrupt-cells = <2>; 4124 interrupt-parent = <&intc>; 4125 interrupt-controller; 4126 }; 4127 4128 aoss_qmp: power-management@c300000 { 4129 compatible = "qcom,sm8150-aoss-qmp", "qcom,aoss-qmp"; 4130 reg = <0x0 0x0c300000 0x0 0x400>; 4131 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 4132 mboxes = <&apss_shared 0>; 4133 4134 #clock-cells = <0>; 4135 }; 4136 4137 sram@c3f0000 { 4138 compatible = "qcom,rpmh-stats"; 4139 reg = <0 0x0c3f0000 0 0x400>; 4140 }; 4141 4142 tsens0: thermal-sensor@c263000 { 4143 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 4144 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4145 <0 0x0c222000 0 0x1ff>; /* SROT */ 4146 #qcom,sensors = <16>; 4147 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4148 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4149 interrupt-names = "uplow", "critical"; 4150 #thermal-sensor-cells = <1>; 4151 }; 4152 4153 tsens1: thermal-sensor@c265000 { 4154 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; 4155 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4156 <0 0x0c223000 0 0x1ff>; /* SROT */ 4157 #qcom,sensors = <8>; 4158 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4159 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4160 interrupt-names = "uplow", "critical"; 4161 #thermal-sensor-cells = <1>; 4162 }; 4163 4164 spmi_bus: spmi@c440000 { 4165 compatible = "qcom,spmi-pmic-arb"; 4166 reg = <0x0 0x0c440000 0x0 0x0001100>, 4167 <0x0 0x0c600000 0x0 0x2000000>, 4168 <0x0 0x0e600000 0x0 0x0100000>, 4169 <0x0 0x0e700000 0x0 0x00a0000>, 4170 <0x0 0x0c40a000 0x0 0x0026000>; 4171 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4172 interrupt-names = "periph_irq"; 4173 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 4174 qcom,ee = <0>; 4175 qcom,channel = <0>; 4176 #address-cells = <2>; 4177 #size-cells = <0>; 4178 interrupt-controller; 4179 #interrupt-cells = <4>; 4180 }; 4181 4182 apps_smmu: iommu@15000000 { 4183 compatible = "qcom,sm8150-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 4184 reg = <0 0x15000000 0 0x100000>; 4185 #iommu-cells = <2>; 4186 #global-interrupts = <1>; 4187 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4188 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4189 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4190 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4191 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4192 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4193 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4194 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4195 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4196 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4197 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4198 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4199 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4200 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4201 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4202 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4203 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4204 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4205 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4206 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4207 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4208 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4209 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4210 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4211 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4212 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4213 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4214 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4215 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4216 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4217 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4218 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4219 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4220 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4221 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4222 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4223 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4224 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4225 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4226 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4227 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4228 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4229 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4230 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4231 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4232 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4233 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4234 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4235 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4236 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4237 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4238 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4239 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4240 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4241 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4242 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4243 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4244 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4245 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4246 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4247 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4248 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4249 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4250 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4251 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4252 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4253 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4254 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4255 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4256 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4257 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4258 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4259 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4260 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4261 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4262 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4263 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4264 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4265 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4266 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4267 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 4268 }; 4269 4270 remoteproc_adsp: remoteproc@17300000 { 4271 compatible = "qcom,sm8150-adsp-pas"; 4272 reg = <0x0 0x17300000 0x0 0x4040>; 4273 4274 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 4275 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4276 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 4277 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 4278 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 4279 interrupt-names = "wdog", "fatal", "ready", 4280 "handover", "stop-ack"; 4281 4282 clocks = <&rpmhcc RPMH_CXO_CLK>; 4283 clock-names = "xo"; 4284 4285 power-domains = <&rpmhpd SM8150_CX>; 4286 4287 memory-region = <&adsp_mem>; 4288 4289 qcom,qmp = <&aoss_qmp>; 4290 4291 qcom,smem-states = <&adsp_smp2p_out 0>; 4292 qcom,smem-state-names = "stop"; 4293 4294 status = "disabled"; 4295 4296 glink-edge { 4297 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 4298 label = "lpass"; 4299 qcom,remote-pid = <2>; 4300 mboxes = <&apss_shared 8>; 4301 4302 fastrpc { 4303 compatible = "qcom,fastrpc"; 4304 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4305 label = "adsp"; 4306 qcom,non-secure-domain; 4307 #address-cells = <1>; 4308 #size-cells = <0>; 4309 4310 compute-cb@3 { 4311 compatible = "qcom,fastrpc-compute-cb"; 4312 reg = <3>; 4313 iommus = <&apps_smmu 0x1b23 0x0>; 4314 }; 4315 4316 compute-cb@4 { 4317 compatible = "qcom,fastrpc-compute-cb"; 4318 reg = <4>; 4319 iommus = <&apps_smmu 0x1b24 0x0>; 4320 }; 4321 4322 compute-cb@5 { 4323 compatible = "qcom,fastrpc-compute-cb"; 4324 reg = <5>; 4325 iommus = <&apps_smmu 0x1b25 0x0>; 4326 }; 4327 }; 4328 }; 4329 }; 4330 4331 intc: interrupt-controller@17a00000 { 4332 compatible = "arm,gic-v3"; 4333 interrupt-controller; 4334 #interrupt-cells = <3>; 4335 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4336 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4337 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4338 }; 4339 4340 apss_shared: mailbox@17c00000 { 4341 compatible = "qcom,sm8150-apss-shared", 4342 "qcom,sdm845-apss-shared"; 4343 reg = <0x0 0x17c00000 0x0 0x1000>; 4344 #mbox-cells = <1>; 4345 }; 4346 4347 watchdog@17c10000 { 4348 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; 4349 reg = <0 0x17c10000 0 0x1000>; 4350 clocks = <&sleep_clk>; 4351 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 4352 }; 4353 4354 timer@17c20000 { 4355 #address-cells = <1>; 4356 #size-cells = <1>; 4357 ranges = <0 0 0 0x20000000>; 4358 compatible = "arm,armv7-timer-mem"; 4359 reg = <0x0 0x17c20000 0x0 0x1000>; 4360 clock-frequency = <19200000>; 4361 4362 frame@17c21000 { 4363 frame-number = <0>; 4364 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4365 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4366 reg = <0x17c21000 0x1000>, 4367 <0x17c22000 0x1000>; 4368 }; 4369 4370 frame@17c23000 { 4371 frame-number = <1>; 4372 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4373 reg = <0x17c23000 0x1000>; 4374 status = "disabled"; 4375 }; 4376 4377 frame@17c25000 { 4378 frame-number = <2>; 4379 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4380 reg = <0x17c25000 0x1000>; 4381 status = "disabled"; 4382 }; 4383 4384 frame@17c27000 { 4385 frame-number = <3>; 4386 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4387 reg = <0x17c26000 0x1000>; 4388 status = "disabled"; 4389 }; 4390 4391 frame@17c29000 { 4392 frame-number = <4>; 4393 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4394 reg = <0x17c29000 0x1000>; 4395 status = "disabled"; 4396 }; 4397 4398 frame@17c2b000 { 4399 frame-number = <5>; 4400 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4401 reg = <0x17c2b000 0x1000>; 4402 status = "disabled"; 4403 }; 4404 4405 frame@17c2d000 { 4406 frame-number = <6>; 4407 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4408 reg = <0x17c2d000 0x1000>; 4409 status = "disabled"; 4410 }; 4411 }; 4412 4413 apps_rsc: rsc@18200000 { 4414 label = "apps_rsc"; 4415 compatible = "qcom,rpmh-rsc"; 4416 reg = <0x0 0x18200000 0x0 0x10000>, 4417 <0x0 0x18210000 0x0 0x10000>, 4418 <0x0 0x18220000 0x0 0x10000>; 4419 reg-names = "drv-0", "drv-1", "drv-2"; 4420 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4421 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4422 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4423 qcom,tcs-offset = <0xd00>; 4424 qcom,drv-id = <2>; 4425 qcom,tcs-config = <ACTIVE_TCS 2>, 4426 <SLEEP_TCS 3>, 4427 <WAKE_TCS 3>, 4428 <CONTROL_TCS 1>; 4429 power-domains = <&CLUSTER_PD>; 4430 4431 rpmhcc: clock-controller { 4432 compatible = "qcom,sm8150-rpmh-clk"; 4433 #clock-cells = <1>; 4434 clock-names = "xo"; 4435 clocks = <&xo_board>; 4436 }; 4437 4438 rpmhpd: power-controller { 4439 compatible = "qcom,sm8150-rpmhpd"; 4440 #power-domain-cells = <1>; 4441 operating-points-v2 = <&rpmhpd_opp_table>; 4442 4443 rpmhpd_opp_table: opp-table { 4444 compatible = "operating-points-v2"; 4445 4446 rpmhpd_opp_ret: opp1 { 4447 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4448 }; 4449 4450 rpmhpd_opp_min_svs: opp2 { 4451 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4452 }; 4453 4454 rpmhpd_opp_low_svs: opp3 { 4455 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4456 }; 4457 4458 rpmhpd_opp_svs: opp4 { 4459 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4460 }; 4461 4462 rpmhpd_opp_svs_l1: opp5 { 4463 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4464 }; 4465 4466 rpmhpd_opp_svs_l2: opp6 { 4467 opp-level = <224>; 4468 }; 4469 4470 rpmhpd_opp_nom: opp7 { 4471 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4472 }; 4473 4474 rpmhpd_opp_nom_l1: opp8 { 4475 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4476 }; 4477 4478 rpmhpd_opp_nom_l2: opp9 { 4479 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4480 }; 4481 4482 rpmhpd_opp_turbo: opp10 { 4483 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4484 }; 4485 4486 rpmhpd_opp_turbo_l1: opp11 { 4487 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4488 }; 4489 }; 4490 }; 4491 4492 apps_bcm_voter: bcm-voter { 4493 compatible = "qcom,bcm-voter"; 4494 }; 4495 }; 4496 4497 osm_l3: interconnect@18321000 { 4498 compatible = "qcom,sm8150-osm-l3", "qcom,osm-l3"; 4499 reg = <0 0x18321000 0 0x1400>; 4500 4501 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4502 clock-names = "xo", "alternate"; 4503 4504 #interconnect-cells = <1>; 4505 }; 4506 4507 cpufreq_hw: cpufreq@18323000 { 4508 compatible = "qcom,sm8150-cpufreq-hw", "qcom,cpufreq-hw"; 4509 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, 4510 <0 0x18327800 0 0x1400>; 4511 reg-names = "freq-domain0", "freq-domain1", 4512 "freq-domain2"; 4513 4514 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4515 clock-names = "xo", "alternate"; 4516 4517 #freq-domain-cells = <1>; 4518 #clock-cells = <1>; 4519 }; 4520 4521 lmh_cluster1: lmh@18350800 { 4522 compatible = "qcom,sm8150-lmh"; 4523 reg = <0 0x18350800 0 0x400>; 4524 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 4525 cpus = <&CPU4>; 4526 qcom,lmh-temp-arm-millicelsius = <60000>; 4527 qcom,lmh-temp-low-millicelsius = <84500>; 4528 qcom,lmh-temp-high-millicelsius = <85000>; 4529 interrupt-controller; 4530 #interrupt-cells = <1>; 4531 }; 4532 4533 lmh_cluster0: lmh@18358800 { 4534 compatible = "qcom,sm8150-lmh"; 4535 reg = <0 0x18358800 0 0x400>; 4536 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 4537 cpus = <&CPU0>; 4538 qcom,lmh-temp-arm-millicelsius = <60000>; 4539 qcom,lmh-temp-low-millicelsius = <84500>; 4540 qcom,lmh-temp-high-millicelsius = <85000>; 4541 interrupt-controller; 4542 #interrupt-cells = <1>; 4543 }; 4544 4545 wifi: wifi@18800000 { 4546 compatible = "qcom,wcn3990-wifi"; 4547 reg = <0 0x18800000 0 0x800000>; 4548 reg-names = "membase"; 4549 memory-region = <&wlan_mem>; 4550 clock-names = "cxo_ref_clk_pin", "qdss"; 4551 clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; 4552 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 4553 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 4554 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 4555 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 4556 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4557 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4558 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 4559 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4560 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4561 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4562 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4563 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 4564 iommus = <&apps_smmu 0x0640 0x1>; 4565 status = "disabled"; 4566 }; 4567 }; 4568 4569 timer { 4570 compatible = "arm,armv8-timer"; 4571 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4572 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4573 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4574 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4575 }; 4576 4577 thermal-zones { 4578 cpu0-thermal { 4579 polling-delay-passive = <250>; 4580 polling-delay = <1000>; 4581 4582 thermal-sensors = <&tsens0 1>; 4583 4584 trips { 4585 cpu0_alert0: trip-point0 { 4586 temperature = <90000>; 4587 hysteresis = <2000>; 4588 type = "passive"; 4589 }; 4590 4591 cpu0_alert1: trip-point1 { 4592 temperature = <95000>; 4593 hysteresis = <2000>; 4594 type = "passive"; 4595 }; 4596 4597 cpu0_crit: cpu-crit { 4598 temperature = <110000>; 4599 hysteresis = <1000>; 4600 type = "critical"; 4601 }; 4602 }; 4603 4604 cooling-maps { 4605 map0 { 4606 trip = <&cpu0_alert0>; 4607 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4608 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4609 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4610 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4611 }; 4612 map1 { 4613 trip = <&cpu0_alert1>; 4614 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4615 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4616 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4617 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4618 }; 4619 }; 4620 }; 4621 4622 cpu1-thermal { 4623 polling-delay-passive = <250>; 4624 polling-delay = <1000>; 4625 4626 thermal-sensors = <&tsens0 2>; 4627 4628 trips { 4629 cpu1_alert0: trip-point0 { 4630 temperature = <90000>; 4631 hysteresis = <2000>; 4632 type = "passive"; 4633 }; 4634 4635 cpu1_alert1: trip-point1 { 4636 temperature = <95000>; 4637 hysteresis = <2000>; 4638 type = "passive"; 4639 }; 4640 4641 cpu1_crit: cpu-crit { 4642 temperature = <110000>; 4643 hysteresis = <1000>; 4644 type = "critical"; 4645 }; 4646 }; 4647 4648 cooling-maps { 4649 map0 { 4650 trip = <&cpu1_alert0>; 4651 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4652 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4653 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4654 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4655 }; 4656 map1 { 4657 trip = <&cpu1_alert1>; 4658 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4659 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4660 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4661 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4662 }; 4663 }; 4664 }; 4665 4666 cpu2-thermal { 4667 polling-delay-passive = <250>; 4668 polling-delay = <1000>; 4669 4670 thermal-sensors = <&tsens0 3>; 4671 4672 trips { 4673 cpu2_alert0: trip-point0 { 4674 temperature = <90000>; 4675 hysteresis = <2000>; 4676 type = "passive"; 4677 }; 4678 4679 cpu2_alert1: trip-point1 { 4680 temperature = <95000>; 4681 hysteresis = <2000>; 4682 type = "passive"; 4683 }; 4684 4685 cpu2_crit: cpu-crit { 4686 temperature = <110000>; 4687 hysteresis = <1000>; 4688 type = "critical"; 4689 }; 4690 }; 4691 4692 cooling-maps { 4693 map0 { 4694 trip = <&cpu2_alert0>; 4695 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4696 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4697 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4698 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4699 }; 4700 map1 { 4701 trip = <&cpu2_alert1>; 4702 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4703 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4704 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4705 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4706 }; 4707 }; 4708 }; 4709 4710 cpu3-thermal { 4711 polling-delay-passive = <250>; 4712 polling-delay = <1000>; 4713 4714 thermal-sensors = <&tsens0 4>; 4715 4716 trips { 4717 cpu3_alert0: trip-point0 { 4718 temperature = <90000>; 4719 hysteresis = <2000>; 4720 type = "passive"; 4721 }; 4722 4723 cpu3_alert1: trip-point1 { 4724 temperature = <95000>; 4725 hysteresis = <2000>; 4726 type = "passive"; 4727 }; 4728 4729 cpu3_crit: cpu-crit { 4730 temperature = <110000>; 4731 hysteresis = <1000>; 4732 type = "critical"; 4733 }; 4734 }; 4735 4736 cooling-maps { 4737 map0 { 4738 trip = <&cpu3_alert0>; 4739 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4740 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4741 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4742 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4743 }; 4744 map1 { 4745 trip = <&cpu3_alert1>; 4746 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4747 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4748 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4749 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4750 }; 4751 }; 4752 }; 4753 4754 cpu4-top-thermal { 4755 polling-delay-passive = <250>; 4756 polling-delay = <1000>; 4757 4758 thermal-sensors = <&tsens0 7>; 4759 4760 trips { 4761 cpu4_top_alert0: trip-point0 { 4762 temperature = <90000>; 4763 hysteresis = <2000>; 4764 type = "passive"; 4765 }; 4766 4767 cpu4_top_alert1: trip-point1 { 4768 temperature = <95000>; 4769 hysteresis = <2000>; 4770 type = "passive"; 4771 }; 4772 4773 cpu4_top_crit: cpu-crit { 4774 temperature = <110000>; 4775 hysteresis = <1000>; 4776 type = "critical"; 4777 }; 4778 }; 4779 4780 cooling-maps { 4781 map0 { 4782 trip = <&cpu4_top_alert0>; 4783 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4784 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4785 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4786 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4787 }; 4788 map1 { 4789 trip = <&cpu4_top_alert1>; 4790 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4791 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4792 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4793 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4794 }; 4795 }; 4796 }; 4797 4798 cpu5-top-thermal { 4799 polling-delay-passive = <250>; 4800 polling-delay = <1000>; 4801 4802 thermal-sensors = <&tsens0 8>; 4803 4804 trips { 4805 cpu5_top_alert0: trip-point0 { 4806 temperature = <90000>; 4807 hysteresis = <2000>; 4808 type = "passive"; 4809 }; 4810 4811 cpu5_top_alert1: trip-point1 { 4812 temperature = <95000>; 4813 hysteresis = <2000>; 4814 type = "passive"; 4815 }; 4816 4817 cpu5_top_crit: cpu-crit { 4818 temperature = <110000>; 4819 hysteresis = <1000>; 4820 type = "critical"; 4821 }; 4822 }; 4823 4824 cooling-maps { 4825 map0 { 4826 trip = <&cpu5_top_alert0>; 4827 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4828 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4829 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4830 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4831 }; 4832 map1 { 4833 trip = <&cpu5_top_alert1>; 4834 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4835 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4836 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4837 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4838 }; 4839 }; 4840 }; 4841 4842 cpu6-top-thermal { 4843 polling-delay-passive = <250>; 4844 polling-delay = <1000>; 4845 4846 thermal-sensors = <&tsens0 9>; 4847 4848 trips { 4849 cpu6_top_alert0: trip-point0 { 4850 temperature = <90000>; 4851 hysteresis = <2000>; 4852 type = "passive"; 4853 }; 4854 4855 cpu6_top_alert1: trip-point1 { 4856 temperature = <95000>; 4857 hysteresis = <2000>; 4858 type = "passive"; 4859 }; 4860 4861 cpu6_top_crit: cpu-crit { 4862 temperature = <110000>; 4863 hysteresis = <1000>; 4864 type = "critical"; 4865 }; 4866 }; 4867 4868 cooling-maps { 4869 map0 { 4870 trip = <&cpu6_top_alert0>; 4871 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4872 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4873 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4874 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4875 }; 4876 map1 { 4877 trip = <&cpu6_top_alert1>; 4878 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4879 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4880 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4881 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4882 }; 4883 }; 4884 }; 4885 4886 cpu7-top-thermal { 4887 polling-delay-passive = <250>; 4888 polling-delay = <1000>; 4889 4890 thermal-sensors = <&tsens0 10>; 4891 4892 trips { 4893 cpu7_top_alert0: trip-point0 { 4894 temperature = <90000>; 4895 hysteresis = <2000>; 4896 type = "passive"; 4897 }; 4898 4899 cpu7_top_alert1: trip-point1 { 4900 temperature = <95000>; 4901 hysteresis = <2000>; 4902 type = "passive"; 4903 }; 4904 4905 cpu7_top_crit: cpu-crit { 4906 temperature = <110000>; 4907 hysteresis = <1000>; 4908 type = "critical"; 4909 }; 4910 }; 4911 4912 cooling-maps { 4913 map0 { 4914 trip = <&cpu7_top_alert0>; 4915 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4916 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4917 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4918 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4919 }; 4920 map1 { 4921 trip = <&cpu7_top_alert1>; 4922 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4923 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4924 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4925 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4926 }; 4927 }; 4928 }; 4929 4930 cpu4-bottom-thermal { 4931 polling-delay-passive = <250>; 4932 polling-delay = <1000>; 4933 4934 thermal-sensors = <&tsens0 11>; 4935 4936 trips { 4937 cpu4_bottom_alert0: trip-point0 { 4938 temperature = <90000>; 4939 hysteresis = <2000>; 4940 type = "passive"; 4941 }; 4942 4943 cpu4_bottom_alert1: trip-point1 { 4944 temperature = <95000>; 4945 hysteresis = <2000>; 4946 type = "passive"; 4947 }; 4948 4949 cpu4_bottom_crit: cpu-crit { 4950 temperature = <110000>; 4951 hysteresis = <1000>; 4952 type = "critical"; 4953 }; 4954 }; 4955 4956 cooling-maps { 4957 map0 { 4958 trip = <&cpu4_bottom_alert0>; 4959 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4960 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4961 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4962 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4963 }; 4964 map1 { 4965 trip = <&cpu4_bottom_alert1>; 4966 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4967 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4968 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4969 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4970 }; 4971 }; 4972 }; 4973 4974 cpu5-bottom-thermal { 4975 polling-delay-passive = <250>; 4976 polling-delay = <1000>; 4977 4978 thermal-sensors = <&tsens0 12>; 4979 4980 trips { 4981 cpu5_bottom_alert0: trip-point0 { 4982 temperature = <90000>; 4983 hysteresis = <2000>; 4984 type = "passive"; 4985 }; 4986 4987 cpu5_bottom_alert1: trip-point1 { 4988 temperature = <95000>; 4989 hysteresis = <2000>; 4990 type = "passive"; 4991 }; 4992 4993 cpu5_bottom_crit: cpu-crit { 4994 temperature = <110000>; 4995 hysteresis = <1000>; 4996 type = "critical"; 4997 }; 4998 }; 4999 5000 cooling-maps { 5001 map0 { 5002 trip = <&cpu5_bottom_alert0>; 5003 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5004 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5005 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5006 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5007 }; 5008 map1 { 5009 trip = <&cpu5_bottom_alert1>; 5010 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5011 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5012 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5013 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5014 }; 5015 }; 5016 }; 5017 5018 cpu6-bottom-thermal { 5019 polling-delay-passive = <250>; 5020 polling-delay = <1000>; 5021 5022 thermal-sensors = <&tsens0 13>; 5023 5024 trips { 5025 cpu6_bottom_alert0: trip-point0 { 5026 temperature = <90000>; 5027 hysteresis = <2000>; 5028 type = "passive"; 5029 }; 5030 5031 cpu6_bottom_alert1: trip-point1 { 5032 temperature = <95000>; 5033 hysteresis = <2000>; 5034 type = "passive"; 5035 }; 5036 5037 cpu6_bottom_crit: cpu-crit { 5038 temperature = <110000>; 5039 hysteresis = <1000>; 5040 type = "critical"; 5041 }; 5042 }; 5043 5044 cooling-maps { 5045 map0 { 5046 trip = <&cpu6_bottom_alert0>; 5047 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5048 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5049 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5050 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5051 }; 5052 map1 { 5053 trip = <&cpu6_bottom_alert1>; 5054 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5055 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5056 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5057 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5058 }; 5059 }; 5060 }; 5061 5062 cpu7-bottom-thermal { 5063 polling-delay-passive = <250>; 5064 polling-delay = <1000>; 5065 5066 thermal-sensors = <&tsens0 14>; 5067 5068 trips { 5069 cpu7_bottom_alert0: trip-point0 { 5070 temperature = <90000>; 5071 hysteresis = <2000>; 5072 type = "passive"; 5073 }; 5074 5075 cpu7_bottom_alert1: trip-point1 { 5076 temperature = <95000>; 5077 hysteresis = <2000>; 5078 type = "passive"; 5079 }; 5080 5081 cpu7_bottom_crit: cpu-crit { 5082 temperature = <110000>; 5083 hysteresis = <1000>; 5084 type = "critical"; 5085 }; 5086 }; 5087 5088 cooling-maps { 5089 map0 { 5090 trip = <&cpu7_bottom_alert0>; 5091 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5092 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5093 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5094 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5095 }; 5096 map1 { 5097 trip = <&cpu7_bottom_alert1>; 5098 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5099 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5100 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5101 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5102 }; 5103 }; 5104 }; 5105 5106 aoss0-thermal { 5107 polling-delay-passive = <250>; 5108 polling-delay = <1000>; 5109 5110 thermal-sensors = <&tsens0 0>; 5111 5112 trips { 5113 aoss0_alert0: trip-point0 { 5114 temperature = <90000>; 5115 hysteresis = <2000>; 5116 type = "hot"; 5117 }; 5118 }; 5119 }; 5120 5121 cluster0-thermal { 5122 polling-delay-passive = <250>; 5123 polling-delay = <1000>; 5124 5125 thermal-sensors = <&tsens0 5>; 5126 5127 trips { 5128 cluster0_alert0: trip-point0 { 5129 temperature = <90000>; 5130 hysteresis = <2000>; 5131 type = "hot"; 5132 }; 5133 cluster0_crit: cluster0-crit { 5134 temperature = <110000>; 5135 hysteresis = <2000>; 5136 type = "critical"; 5137 }; 5138 }; 5139 }; 5140 5141 cluster1-thermal { 5142 polling-delay-passive = <250>; 5143 polling-delay = <1000>; 5144 5145 thermal-sensors = <&tsens0 6>; 5146 5147 trips { 5148 cluster1_alert0: trip-point0 { 5149 temperature = <90000>; 5150 hysteresis = <2000>; 5151 type = "hot"; 5152 }; 5153 cluster1_crit: cluster1-crit { 5154 temperature = <110000>; 5155 hysteresis = <2000>; 5156 type = "critical"; 5157 }; 5158 }; 5159 }; 5160 5161 gpu-top-thermal { 5162 polling-delay-passive = <250>; 5163 polling-delay = <1000>; 5164 5165 thermal-sensors = <&tsens0 15>; 5166 5167 cooling-maps { 5168 map0 { 5169 trip = <&gpu_top_alert0>; 5170 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5171 }; 5172 }; 5173 5174 trips { 5175 gpu_top_alert0: trip-point0 { 5176 temperature = <90000>; 5177 hysteresis = <2000>; 5178 type = "hot"; 5179 }; 5180 }; 5181 }; 5182 5183 aoss1-thermal { 5184 polling-delay-passive = <250>; 5185 polling-delay = <1000>; 5186 5187 thermal-sensors = <&tsens1 0>; 5188 5189 trips { 5190 aoss1_alert0: trip-point0 { 5191 temperature = <90000>; 5192 hysteresis = <2000>; 5193 type = "hot"; 5194 }; 5195 }; 5196 }; 5197 5198 wlan-thermal { 5199 polling-delay-passive = <250>; 5200 polling-delay = <1000>; 5201 5202 thermal-sensors = <&tsens1 1>; 5203 5204 trips { 5205 wlan_alert0: trip-point0 { 5206 temperature = <90000>; 5207 hysteresis = <2000>; 5208 type = "hot"; 5209 }; 5210 }; 5211 }; 5212 5213 video-thermal { 5214 polling-delay-passive = <250>; 5215 polling-delay = <1000>; 5216 5217 thermal-sensors = <&tsens1 2>; 5218 5219 trips { 5220 video_alert0: trip-point0 { 5221 temperature = <90000>; 5222 hysteresis = <2000>; 5223 type = "hot"; 5224 }; 5225 }; 5226 }; 5227 5228 mem-thermal { 5229 polling-delay-passive = <250>; 5230 polling-delay = <1000>; 5231 5232 thermal-sensors = <&tsens1 3>; 5233 5234 trips { 5235 mem_alert0: trip-point0 { 5236 temperature = <90000>; 5237 hysteresis = <2000>; 5238 type = "hot"; 5239 }; 5240 }; 5241 }; 5242 5243 q6-hvx-thermal { 5244 polling-delay-passive = <250>; 5245 polling-delay = <1000>; 5246 5247 thermal-sensors = <&tsens1 4>; 5248 5249 trips { 5250 q6_hvx_alert0: trip-point0 { 5251 temperature = <90000>; 5252 hysteresis = <2000>; 5253 type = "hot"; 5254 }; 5255 }; 5256 }; 5257 5258 camera-thermal { 5259 polling-delay-passive = <250>; 5260 polling-delay = <1000>; 5261 5262 thermal-sensors = <&tsens1 5>; 5263 5264 trips { 5265 camera_alert0: trip-point0 { 5266 temperature = <90000>; 5267 hysteresis = <2000>; 5268 type = "hot"; 5269 }; 5270 }; 5271 }; 5272 5273 compute-thermal { 5274 polling-delay-passive = <250>; 5275 polling-delay = <1000>; 5276 5277 thermal-sensors = <&tsens1 6>; 5278 5279 trips { 5280 compute_alert0: trip-point0 { 5281 temperature = <90000>; 5282 hysteresis = <2000>; 5283 type = "hot"; 5284 }; 5285 }; 5286 }; 5287 5288 modem-thermal { 5289 polling-delay-passive = <250>; 5290 polling-delay = <1000>; 5291 5292 thermal-sensors = <&tsens1 7>; 5293 5294 trips { 5295 modem_alert0: trip-point0 { 5296 temperature = <90000>; 5297 hysteresis = <2000>; 5298 type = "hot"; 5299 }; 5300 }; 5301 }; 5302 5303 npu-thermal { 5304 polling-delay-passive = <250>; 5305 polling-delay = <1000>; 5306 5307 thermal-sensors = <&tsens1 8>; 5308 5309 trips { 5310 npu_alert0: trip-point0 { 5311 temperature = <90000>; 5312 hysteresis = <2000>; 5313 type = "hot"; 5314 }; 5315 }; 5316 }; 5317 5318 modem-vec-thermal { 5319 polling-delay-passive = <250>; 5320 polling-delay = <1000>; 5321 5322 thermal-sensors = <&tsens1 9>; 5323 5324 trips { 5325 modem_vec_alert0: trip-point0 { 5326 temperature = <90000>; 5327 hysteresis = <2000>; 5328 type = "hot"; 5329 }; 5330 }; 5331 }; 5332 5333 modem-scl-thermal { 5334 polling-delay-passive = <250>; 5335 polling-delay = <1000>; 5336 5337 thermal-sensors = <&tsens1 10>; 5338 5339 trips { 5340 modem_scl_alert0: trip-point0 { 5341 temperature = <90000>; 5342 hysteresis = <2000>; 5343 type = "hot"; 5344 }; 5345 }; 5346 }; 5347 5348 gpu-bottom-thermal { 5349 polling-delay-passive = <250>; 5350 polling-delay = <1000>; 5351 5352 thermal-sensors = <&tsens1 11>; 5353 5354 cooling-maps { 5355 map0 { 5356 trip = <&gpu_bottom_alert0>; 5357 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5358 }; 5359 }; 5360 5361 trips { 5362 gpu_bottom_alert0: trip-point0 { 5363 temperature = <90000>; 5364 hysteresis = <2000>; 5365 type = "hot"; 5366 }; 5367 }; 5368 }; 5369 }; 5370}; 5371