1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> 4 * Copyright (c) 2022, Luca Weiss <luca.weiss@fairphone.com> 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sm6350.h> 8#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 9#include <dt-bindings/clock/qcom,gcc-sm6350.h> 10#include <dt-bindings/clock/qcom,gpucc-sm6350.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,sm6350-camcc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interconnect/qcom,icc.h> 16#include <dt-bindings/interconnect/qcom,osm-l3.h> 17#include <dt-bindings/interconnect/qcom,sm6350.h> 18#include <dt-bindings/interrupt-controller/arm-gic.h> 19#include <dt-bindings/mailbox/qcom-ipcc.h> 20#include <dt-bindings/phy/phy-qcom-qmp.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/soc/qcom,apr.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 25#include <dt-bindings/thermal/thermal.h> 26 27/ { 28 interrupt-parent = <&intc>; 29 #address-cells = <2>; 30 #size-cells = <2>; 31 32 clocks { 33 xo_board: xo-board { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <76800000>; 37 clock-output-names = "xo_board"; 38 }; 39 40 sleep_clk: sleep-clk { 41 compatible = "fixed-clock"; 42 clock-frequency = <32764>; 43 #clock-cells = <0>; 44 }; 45 }; 46 47 cpus { 48 #address-cells = <2>; 49 #size-cells = <0>; 50 51 cpu0: cpu@0 { 52 device_type = "cpu"; 53 compatible = "qcom,kryo560"; 54 reg = <0x0 0x0>; 55 clocks = <&cpufreq_hw 0>; 56 enable-method = "psci"; 57 capacity-dmips-mhz = <1024>; 58 dynamic-power-coefficient = <100>; 59 next-level-cache = <&l2_0>; 60 qcom,freq-domain = <&cpufreq_hw 0>; 61 operating-points-v2 = <&cpu0_opp_table>; 62 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 63 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 64 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 65 power-domains = <&cpu_pd0>; 66 power-domain-names = "psci"; 67 #cooling-cells = <2>; 68 l2_0: l2-cache { 69 compatible = "cache"; 70 cache-level = <2>; 71 cache-unified; 72 next-level-cache = <&l3_0>; 73 l3_0: l3-cache { 74 compatible = "cache"; 75 cache-level = <3>; 76 cache-unified; 77 }; 78 }; 79 }; 80 81 cpu1: cpu@100 { 82 device_type = "cpu"; 83 compatible = "qcom,kryo560"; 84 reg = <0x0 0x100>; 85 clocks = <&cpufreq_hw 0>; 86 enable-method = "psci"; 87 capacity-dmips-mhz = <1024>; 88 dynamic-power-coefficient = <100>; 89 next-level-cache = <&l2_100>; 90 qcom,freq-domain = <&cpufreq_hw 0>; 91 operating-points-v2 = <&cpu0_opp_table>; 92 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 93 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 94 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 95 power-domains = <&cpu_pd1>; 96 power-domain-names = "psci"; 97 #cooling-cells = <2>; 98 l2_100: l2-cache { 99 compatible = "cache"; 100 cache-level = <2>; 101 cache-unified; 102 next-level-cache = <&l3_0>; 103 }; 104 }; 105 106 cpu2: cpu@200 { 107 device_type = "cpu"; 108 compatible = "qcom,kryo560"; 109 reg = <0x0 0x200>; 110 clocks = <&cpufreq_hw 0>; 111 enable-method = "psci"; 112 capacity-dmips-mhz = <1024>; 113 dynamic-power-coefficient = <100>; 114 next-level-cache = <&l2_200>; 115 qcom,freq-domain = <&cpufreq_hw 0>; 116 operating-points-v2 = <&cpu0_opp_table>; 117 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 118 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 119 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 120 power-domains = <&cpu_pd2>; 121 power-domain-names = "psci"; 122 #cooling-cells = <2>; 123 l2_200: l2-cache { 124 compatible = "cache"; 125 cache-level = <2>; 126 cache-unified; 127 next-level-cache = <&l3_0>; 128 }; 129 }; 130 131 cpu3: cpu@300 { 132 device_type = "cpu"; 133 compatible = "qcom,kryo560"; 134 reg = <0x0 0x300>; 135 clocks = <&cpufreq_hw 0>; 136 enable-method = "psci"; 137 capacity-dmips-mhz = <1024>; 138 dynamic-power-coefficient = <100>; 139 next-level-cache = <&l2_300>; 140 qcom,freq-domain = <&cpufreq_hw 0>; 141 operating-points-v2 = <&cpu0_opp_table>; 142 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 143 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 144 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 145 power-domains = <&cpu_pd3>; 146 power-domain-names = "psci"; 147 #cooling-cells = <2>; 148 l2_300: l2-cache { 149 compatible = "cache"; 150 cache-level = <2>; 151 cache-unified; 152 next-level-cache = <&l3_0>; 153 }; 154 }; 155 156 cpu4: cpu@400 { 157 device_type = "cpu"; 158 compatible = "qcom,kryo560"; 159 reg = <0x0 0x400>; 160 clocks = <&cpufreq_hw 0>; 161 enable-method = "psci"; 162 capacity-dmips-mhz = <1024>; 163 dynamic-power-coefficient = <100>; 164 next-level-cache = <&l2_400>; 165 qcom,freq-domain = <&cpufreq_hw 0>; 166 operating-points-v2 = <&cpu0_opp_table>; 167 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 168 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 169 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 170 power-domains = <&cpu_pd4>; 171 power-domain-names = "psci"; 172 #cooling-cells = <2>; 173 l2_400: l2-cache { 174 compatible = "cache"; 175 cache-level = <2>; 176 cache-unified; 177 next-level-cache = <&l3_0>; 178 }; 179 }; 180 181 cpu5: cpu@500 { 182 device_type = "cpu"; 183 compatible = "qcom,kryo560"; 184 reg = <0x0 0x500>; 185 clocks = <&cpufreq_hw 0>; 186 enable-method = "psci"; 187 capacity-dmips-mhz = <1024>; 188 dynamic-power-coefficient = <100>; 189 next-level-cache = <&l2_500>; 190 qcom,freq-domain = <&cpufreq_hw 0>; 191 operating-points-v2 = <&cpu0_opp_table>; 192 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 193 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 194 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 195 power-domains = <&cpu_pd5>; 196 power-domain-names = "psci"; 197 #cooling-cells = <2>; 198 l2_500: l2-cache { 199 compatible = "cache"; 200 cache-level = <2>; 201 cache-unified; 202 next-level-cache = <&l3_0>; 203 }; 204 }; 205 206 cpu6: cpu@600 { 207 device_type = "cpu"; 208 compatible = "qcom,kryo560"; 209 reg = <0x0 0x600>; 210 clocks = <&cpufreq_hw 1>; 211 enable-method = "psci"; 212 capacity-dmips-mhz = <1894>; 213 dynamic-power-coefficient = <703>; 214 next-level-cache = <&l2_600>; 215 qcom,freq-domain = <&cpufreq_hw 1>; 216 operating-points-v2 = <&cpu6_opp_table>; 217 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 218 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 219 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 220 power-domains = <&cpu_pd6>; 221 power-domain-names = "psci"; 222 #cooling-cells = <2>; 223 l2_600: l2-cache { 224 compatible = "cache"; 225 cache-level = <2>; 226 cache-unified; 227 next-level-cache = <&l3_0>; 228 }; 229 }; 230 231 cpu7: cpu@700 { 232 device_type = "cpu"; 233 compatible = "qcom,kryo560"; 234 reg = <0x0 0x700>; 235 clocks = <&cpufreq_hw 1>; 236 enable-method = "psci"; 237 capacity-dmips-mhz = <1894>; 238 dynamic-power-coefficient = <703>; 239 next-level-cache = <&l2_700>; 240 qcom,freq-domain = <&cpufreq_hw 1>; 241 operating-points-v2 = <&cpu6_opp_table>; 242 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 243 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 244 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 245 power-domains = <&cpu_pd7>; 246 power-domain-names = "psci"; 247 #cooling-cells = <2>; 248 l2_700: l2-cache { 249 compatible = "cache"; 250 cache-level = <2>; 251 cache-unified; 252 next-level-cache = <&l3_0>; 253 }; 254 }; 255 256 cpu-map { 257 cluster0 { 258 core0 { 259 cpu = <&cpu0>; 260 }; 261 262 core1 { 263 cpu = <&cpu1>; 264 }; 265 266 core2 { 267 cpu = <&cpu2>; 268 }; 269 270 core3 { 271 cpu = <&cpu3>; 272 }; 273 274 core4 { 275 cpu = <&cpu4>; 276 }; 277 278 core5 { 279 cpu = <&cpu5>; 280 }; 281 282 core6 { 283 cpu = <&cpu6>; 284 }; 285 286 core7 { 287 cpu = <&cpu7>; 288 }; 289 }; 290 }; 291 292 domain-idle-states { 293 cluster_sleep_pc: cluster-sleep-0 { 294 compatible = "domain-idle-state"; 295 arm,psci-suspend-param = <0x41000044>; 296 entry-latency-us = <2752>; 297 exit-latency-us = <3048>; 298 min-residency-us = <6118>; 299 }; 300 301 cluster_sleep_cx_ret: cluster-sleep-1 { 302 compatible = "domain-idle-state"; 303 arm,psci-suspend-param = <0x41001244>; 304 entry-latency-us = <3638>; 305 exit-latency-us = <4562>; 306 min-residency-us = <8467>; 307 }; 308 309 cluster_aoss_sleep: cluster-sleep-2 { 310 compatible = "domain-idle-state"; 311 arm,psci-suspend-param = <0x4100b244>; 312 entry-latency-us = <3263>; 313 exit-latency-us = <6562>; 314 min-residency-us = <9987>; 315 }; 316 }; 317 318 cpu_idle_states: idle-states { 319 entry-method = "psci"; 320 321 little_cpu_sleep_0: cpu-sleep-0-0 { 322 compatible = "arm,idle-state"; 323 idle-state-name = "little-power-collapse"; 324 arm,psci-suspend-param = <0x40000003>; 325 entry-latency-us = <549>; 326 exit-latency-us = <901>; 327 min-residency-us = <1774>; 328 local-timer-stop; 329 }; 330 331 little_cpu_sleep_1: cpu-sleep-0-1 { 332 compatible = "arm,idle-state"; 333 idle-state-name = "little-rail-power-collapse"; 334 arm,psci-suspend-param = <0x40000004>; 335 entry-latency-us = <702>; 336 exit-latency-us = <915>; 337 min-residency-us = <4001>; 338 local-timer-stop; 339 }; 340 341 big_cpu_sleep_0: cpu-sleep-1-0 { 342 compatible = "arm,idle-state"; 343 idle-state-name = "big-power-collapse"; 344 arm,psci-suspend-param = <0x40000003>; 345 entry-latency-us = <523>; 346 exit-latency-us = <1244>; 347 min-residency-us = <2207>; 348 local-timer-stop; 349 }; 350 351 big_cpu_sleep_1: cpu-sleep-1-1 { 352 compatible = "arm,idle-state"; 353 idle-state-name = "big-rail-power-collapse"; 354 arm,psci-suspend-param = <0x40000004>; 355 entry-latency-us = <526>; 356 exit-latency-us = <1854>; 357 min-residency-us = <5555>; 358 local-timer-stop; 359 }; 360 }; 361 }; 362 363 firmware { 364 scm: scm { 365 compatible = "qcom,scm-sm6350", "qcom,scm"; 366 #reset-cells = <1>; 367 }; 368 }; 369 370 memory@80000000 { 371 device_type = "memory"; 372 /* We expect the bootloader to fill in the size */ 373 reg = <0x0 0x80000000 0x0 0x0>; 374 }; 375 376 cpu0_opp_table: opp-table-cpu0 { 377 compatible = "operating-points-v2"; 378 opp-shared; 379 380 opp-300000000 { 381 opp-hz = /bits/ 64 <300000000>; 382 /* DDR: 4-wide, 2 channels, double data rate, L3: 16-wide, 2 channels */ 383 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; 384 }; 385 386 opp-576000000 { 387 opp-hz = /bits/ 64 <576000000>; 388 opp-peak-kBps = <(547000 * 4 * 2 * 2) (556800 * 16 * 2)>; 389 }; 390 391 opp-768000000 { 392 opp-hz = /bits/ 64 <768000000>; 393 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; 394 }; 395 396 opp-1017600000 { 397 opp-hz = /bits/ 64 <1017600000>; 398 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; 399 }; 400 401 opp-1248000000 { 402 opp-hz = /bits/ 64 <1248000000>; 403 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; 404 }; 405 406 opp-1324800000 { 407 opp-hz = /bits/ 64 <1324800000>; 408 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1286400 * 16 * 2)>; 409 }; 410 411 opp-1516800000 { 412 opp-hz = /bits/ 64 <1516800000>; 413 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 414 }; 415 416 opp-1612800000 { 417 opp-hz = /bits/ 64 <1612800000>; 418 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 419 }; 420 421 opp-1708800000 { 422 opp-hz = /bits/ 64 <1708800000>; 423 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 424 }; 425 }; 426 427 cpu6_opp_table: opp-table-cpu6 { 428 compatible = "operating-points-v2"; 429 opp-shared; 430 431 opp-300000000 { 432 opp-hz = /bits/ 64 <300000000>; 433 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; 434 }; 435 436 opp-787200000 { 437 opp-hz = /bits/ 64 <787200000>; 438 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; 439 }; 440 441 opp-979200000 { 442 opp-hz = /bits/ 64 <979200000>; 443 opp-peak-kBps = <(768000 * 4 * 2 * 2) (940800 * 16 * 2)>; 444 }; 445 446 opp-1036800000 { 447 opp-hz = /bits/ 64 <1036800000>; 448 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; 449 }; 450 451 opp-1248000000 { 452 opp-hz = /bits/ 64 <1248000000>; 453 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; 454 }; 455 456 opp-1401600000 { 457 opp-hz = /bits/ 64 <1401600000>; 458 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1401600 * 16 * 2)>; 459 }; 460 461 opp-1555200000 { 462 opp-hz = /bits/ 64 <1555200000>; 463 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 464 }; 465 466 opp-1766400000 { 467 opp-hz = /bits/ 64 <1766400000>; 468 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 469 }; 470 471 opp-1900800000 { 472 opp-hz = /bits/ 64 <1900800000>; 473 opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 474 }; 475 476 opp-2073600000 { 477 opp-hz = /bits/ 64 <2073600000>; 478 opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 479 }; 480 }; 481 482 qup_opp_table: opp-table-qup { 483 compatible = "operating-points-v2"; 484 485 opp-75000000 { 486 opp-hz = /bits/ 64 <75000000>; 487 required-opps = <&rpmhpd_opp_low_svs>; 488 }; 489 490 opp-100000000 { 491 opp-hz = /bits/ 64 <100000000>; 492 required-opps = <&rpmhpd_opp_svs>; 493 }; 494 495 opp-128000000 { 496 opp-hz = /bits/ 64 <128000000>; 497 required-opps = <&rpmhpd_opp_nom>; 498 }; 499 }; 500 501 pmu { 502 compatible = "arm,armv8-pmuv3"; 503 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>; 504 }; 505 506 psci { 507 compatible = "arm,psci-1.0"; 508 method = "smc"; 509 510 cpu_pd0: power-domain-cpu0 { 511 #power-domain-cells = <0>; 512 power-domains = <&cluster_pd>; 513 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 514 }; 515 516 cpu_pd1: power-domain-cpu1 { 517 #power-domain-cells = <0>; 518 power-domains = <&cluster_pd>; 519 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 520 }; 521 522 cpu_pd2: power-domain-cpu2 { 523 #power-domain-cells = <0>; 524 power-domains = <&cluster_pd>; 525 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 526 }; 527 528 cpu_pd3: power-domain-cpu3 { 529 #power-domain-cells = <0>; 530 power-domains = <&cluster_pd>; 531 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 532 }; 533 534 cpu_pd4: power-domain-cpu4 { 535 #power-domain-cells = <0>; 536 power-domains = <&cluster_pd>; 537 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 538 }; 539 540 cpu_pd5: power-domain-cpu5 { 541 #power-domain-cells = <0>; 542 power-domains = <&cluster_pd>; 543 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 544 }; 545 546 cpu_pd6: power-domain-cpu6 { 547 #power-domain-cells = <0>; 548 power-domains = <&cluster_pd>; 549 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 550 }; 551 552 cpu_pd7: power-domain-cpu7 { 553 #power-domain-cells = <0>; 554 power-domains = <&cluster_pd>; 555 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 556 }; 557 558 cluster_pd: power-domain-cpu-cluster0 { 559 #power-domain-cells = <0>; 560 domain-idle-states = <&cluster_sleep_pc 561 &cluster_sleep_cx_ret 562 &cluster_aoss_sleep>; 563 }; 564 }; 565 566 reserved_memory: reserved-memory { 567 #address-cells = <2>; 568 #size-cells = <2>; 569 ranges; 570 571 hyp_mem: memory@80000000 { 572 reg = <0x0 0x80000000 0x0 0x600000>; 573 no-map; 574 }; 575 576 xbl_aop_mem: memory@80700000 { 577 reg = <0x0 0x80700000 0x0 0x160000>; 578 no-map; 579 }; 580 581 cmd_db: memory@80860000 { 582 compatible = "qcom,cmd-db"; 583 reg = <0x0 0x80860000 0x0 0x20000>; 584 no-map; 585 }; 586 587 sec_apps_mem: memory@808ff000 { 588 reg = <0x0 0x808ff000 0x0 0x1000>; 589 no-map; 590 }; 591 592 smem_mem: memory@80900000 { 593 reg = <0x0 0x80900000 0x0 0x200000>; 594 no-map; 595 }; 596 597 cdsp_sec_mem: memory@80b00000 { 598 reg = <0x0 0x80b00000 0x0 0x1e00000>; 599 no-map; 600 }; 601 602 pil_camera_mem: memory@86000000 { 603 reg = <0x0 0x86000000 0x0 0x500000>; 604 no-map; 605 }; 606 607 pil_npu_mem: memory@86500000 { 608 reg = <0x0 0x86500000 0x0 0x500000>; 609 no-map; 610 }; 611 612 pil_video_mem: memory@86a00000 { 613 reg = <0x0 0x86a00000 0x0 0x500000>; 614 no-map; 615 }; 616 617 pil_cdsp_mem: memory@86f00000 { 618 reg = <0x0 0x86f00000 0x0 0x1e00000>; 619 no-map; 620 }; 621 622 pil_adsp_mem: memory@88d00000 { 623 reg = <0x0 0x88d00000 0x0 0x2800000>; 624 no-map; 625 }; 626 627 wlan_fw_mem: memory@8b500000 { 628 reg = <0x0 0x8b500000 0x0 0x200000>; 629 no-map; 630 }; 631 632 pil_ipa_fw_mem: memory@8b700000 { 633 reg = <0x0 0x8b700000 0x0 0x10000>; 634 no-map; 635 }; 636 637 pil_ipa_gsi_mem: memory@8b710000 { 638 reg = <0x0 0x8b710000 0x0 0x5400>; 639 no-map; 640 }; 641 642 pil_modem_mem: memory@8b800000 { 643 reg = <0x0 0x8b800000 0x0 0xf800000>; 644 no-map; 645 }; 646 647 cont_splash_memory: memory@a0000000 { 648 reg = <0x0 0xa0000000 0x0 0x2300000>; 649 no-map; 650 }; 651 652 dfps_data_memory: memory@a2300000 { 653 reg = <0x0 0xa2300000 0x0 0x100000>; 654 no-map; 655 }; 656 657 removed_region: memory@c0000000 { 658 reg = <0x0 0xc0000000 0x0 0x3900000>; 659 no-map; 660 }; 661 662 pil_gpu_mem: memory@f0d00000 { 663 reg = <0x0 0xf0d00000 0x0 0x1000>; 664 no-map; 665 }; 666 667 debug_region: memory@ffb00000 { 668 reg = <0x0 0xffb00000 0x0 0xc0000>; 669 no-map; 670 }; 671 672 last_log_region: memory@ffbc0000 { 673 reg = <0x0 0xffbc0000 0x0 0x40000>; 674 no-map; 675 }; 676 677 ramoops: ramoops@ffc00000 { 678 compatible = "ramoops"; 679 reg = <0x0 0xffc00000 0x0 0x100000>; 680 record-size = <0x1000>; 681 console-size = <0x40000>; 682 pmsg-size = <0x20000>; 683 ecc-size = <16>; 684 no-map; 685 }; 686 687 cmdline_region: memory@ffd00000 { 688 reg = <0x0 0xffd00000 0x0 0x1000>; 689 no-map; 690 }; 691 }; 692 693 smem { 694 compatible = "qcom,smem"; 695 memory-region = <&smem_mem>; 696 hwlocks = <&tcsr_mutex 3>; 697 }; 698 699 smp2p-adsp { 700 compatible = "qcom,smp2p"; 701 qcom,smem = <443>, <429>; 702 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 703 IPCC_MPROC_SIGNAL_SMP2P 704 IRQ_TYPE_EDGE_RISING>; 705 mboxes = <&ipcc IPCC_CLIENT_LPASS 706 IPCC_MPROC_SIGNAL_SMP2P>; 707 708 qcom,local-pid = <0>; 709 qcom,remote-pid = <2>; 710 711 smp2p_adsp_out: master-kernel { 712 qcom,entry-name = "master-kernel"; 713 #qcom,smem-state-cells = <1>; 714 }; 715 716 smp2p_adsp_in: slave-kernel { 717 qcom,entry-name = "slave-kernel"; 718 interrupt-controller; 719 #interrupt-cells = <2>; 720 }; 721 }; 722 723 smp2p-cdsp { 724 compatible = "qcom,smp2p"; 725 qcom,smem = <94>, <432>; 726 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 727 IPCC_MPROC_SIGNAL_SMP2P 728 IRQ_TYPE_EDGE_RISING>; 729 mboxes = <&ipcc IPCC_CLIENT_CDSP 730 IPCC_MPROC_SIGNAL_SMP2P>; 731 732 qcom,local-pid = <0>; 733 qcom,remote-pid = <5>; 734 735 smp2p_cdsp_out: master-kernel { 736 qcom,entry-name = "master-kernel"; 737 #qcom,smem-state-cells = <1>; 738 }; 739 740 smp2p_cdsp_in: slave-kernel { 741 qcom,entry-name = "slave-kernel"; 742 interrupt-controller; 743 #interrupt-cells = <2>; 744 }; 745 }; 746 747 smp2p-mpss { 748 compatible = "qcom,smp2p"; 749 qcom,smem = <435>, <428>; 750 751 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 752 IPCC_MPROC_SIGNAL_SMP2P 753 IRQ_TYPE_EDGE_RISING>; 754 mboxes = <&ipcc IPCC_CLIENT_MPSS 755 IPCC_MPROC_SIGNAL_SMP2P>; 756 757 qcom,local-pid = <0>; 758 qcom,remote-pid = <1>; 759 760 modem_smp2p_out: master-kernel { 761 qcom,entry-name = "master-kernel"; 762 #qcom,smem-state-cells = <1>; 763 }; 764 765 modem_smp2p_in: slave-kernel { 766 qcom,entry-name = "slave-kernel"; 767 interrupt-controller; 768 #interrupt-cells = <2>; 769 }; 770 771 ipa_smp2p_out: ipa-ap-to-modem { 772 qcom,entry-name = "ipa"; 773 #qcom,smem-state-cells = <1>; 774 }; 775 776 ipa_smp2p_in: ipa-modem-to-ap { 777 qcom,entry-name = "ipa"; 778 interrupt-controller; 779 #interrupt-cells = <2>; 780 }; 781 }; 782 783 soc: soc@0 { 784 #address-cells = <2>; 785 #size-cells = <2>; 786 ranges = <0 0 0 0 0x10 0>; 787 dma-ranges = <0 0 0 0 0x10 0>; 788 compatible = "simple-bus"; 789 790 gcc: clock-controller@100000 { 791 compatible = "qcom,gcc-sm6350"; 792 reg = <0x0 0x00100000 0x0 0x1f0000>; 793 #clock-cells = <1>; 794 #reset-cells = <1>; 795 #power-domain-cells = <1>; 796 clock-names = "bi_tcxo", 797 "bi_tcxo_ao", 798 "sleep_clk"; 799 clocks = <&rpmhcc RPMH_CXO_CLK>, 800 <&rpmhcc RPMH_CXO_CLK_A>, 801 <&sleep_clk>; 802 }; 803 804 ipcc: mailbox@408000 { 805 compatible = "qcom,sm6350-ipcc", "qcom,ipcc"; 806 reg = <0x0 0x00408000 0x0 0x1000>; 807 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 808 interrupt-controller; 809 #interrupt-cells = <3>; 810 #mbox-cells = <2>; 811 }; 812 813 qfprom: qfprom@784000 { 814 compatible = "qcom,sm6350-qfprom", "qcom,qfprom"; 815 reg = <0x0 0x00784000 0x0 0x3000>; 816 #address-cells = <1>; 817 #size-cells = <1>; 818 819 gpu_speed_bin: gpu-speed-bin@2015 { 820 reg = <0x2015 0x1>; 821 bits = <0 8>; 822 }; 823 }; 824 825 rng: rng@793000 { 826 compatible = "qcom,prng-ee"; 827 reg = <0x0 0x00793000 0x0 0x1000>; 828 clocks = <&gcc GCC_PRNG_AHB_CLK>; 829 clock-names = "core"; 830 }; 831 832 sdhc_1: mmc@7c4000 { 833 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 834 reg = <0x0 0x007c4000 0x0 0x1000>, 835 <0x0 0x007c5000 0x0 0x1000>, 836 <0x0 0x007c8000 0x0 0x8000>; 837 reg-names = "hc", "cqhci", "ice"; 838 839 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 840 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 841 interrupt-names = "hc_irq", "pwr_irq"; 842 iommus = <&apps_smmu 0x60 0x0>; 843 844 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 845 <&gcc GCC_SDCC1_APPS_CLK>, 846 <&rpmhcc RPMH_CXO_CLK>; 847 clock-names = "iface", "core", "xo"; 848 resets = <&gcc GCC_SDCC1_BCR>; 849 qcom,dll-config = <0x000f642c>; 850 qcom,ddr-config = <0x80040868>; 851 power-domains = <&rpmhpd SM6350_CX>; 852 operating-points-v2 = <&sdhc1_opp_table>; 853 bus-width = <8>; 854 non-removable; 855 supports-cqe; 856 857 status = "disabled"; 858 859 sdhc1_opp_table: opp-table { 860 compatible = "operating-points-v2"; 861 862 opp-19200000 { 863 opp-hz = /bits/ 64 <19200000>; 864 required-opps = <&rpmhpd_opp_min_svs>; 865 }; 866 867 opp-100000000 { 868 opp-hz = /bits/ 64 <100000000>; 869 required-opps = <&rpmhpd_opp_low_svs>; 870 }; 871 872 opp-384000000 { 873 opp-hz = /bits/ 64 <384000000>; 874 required-opps = <&rpmhpd_opp_svs_l1>; 875 }; 876 }; 877 }; 878 879 gpi_dma0: dma-controller@800000 { 880 compatible = "qcom,sm6350-gpi-dma"; 881 reg = <0x0 0x00800000 0x0 0x60000>; 882 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 891 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 892 dma-channels = <10>; 893 dma-channel-mask = <0x1f>; 894 iommus = <&apps_smmu 0x56 0x0>; 895 #dma-cells = <3>; 896 status = "disabled"; 897 }; 898 899 qupv3_id_0: geniqup@8c0000 { 900 compatible = "qcom,geni-se-qup"; 901 reg = <0x0 0x008c0000 0x0 0x2000>; 902 clock-names = "m-ahb", "s-ahb"; 903 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 904 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 905 #address-cells = <2>; 906 #size-cells = <2>; 907 iommus = <&apps_smmu 0x43 0x0>; 908 ranges; 909 status = "disabled"; 910 911 i2c0: i2c@880000 { 912 compatible = "qcom,geni-i2c"; 913 reg = <0x0 0x00880000 0x0 0x4000>; 914 clock-names = "se"; 915 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 916 pinctrl-names = "default"; 917 pinctrl-0 = <&qup_i2c0_default>; 918 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 919 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 920 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 921 dma-names = "tx", "rx"; 922 #address-cells = <1>; 923 #size-cells = <0>; 924 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 925 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 926 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 927 interconnect-names = "qup-core", "qup-config", "qup-memory"; 928 status = "disabled"; 929 }; 930 931 uart1: serial@884000 { 932 compatible = "qcom,geni-uart"; 933 reg = <0x0 0x00884000 0x0 0x4000>; 934 clock-names = "se"; 935 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 936 pinctrl-names = "default"; 937 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 938 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 939 power-domains = <&rpmhpd SM6350_CX>; 940 operating-points-v2 = <&qup_opp_table>; 941 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 942 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 943 interconnect-names = "qup-core", "qup-config"; 944 status = "disabled"; 945 }; 946 947 i2c2: i2c@888000 { 948 compatible = "qcom,geni-i2c"; 949 reg = <0x0 0x00888000 0x0 0x4000>; 950 clock-names = "se"; 951 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 952 pinctrl-names = "default"; 953 pinctrl-0 = <&qup_i2c2_default>; 954 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 955 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 956 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 957 dma-names = "tx", "rx"; 958 #address-cells = <1>; 959 #size-cells = <0>; 960 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 961 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 962 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 963 interconnect-names = "qup-core", "qup-config", "qup-memory"; 964 status = "disabled"; 965 }; 966 }; 967 968 gpi_dma1: dma-controller@900000 { 969 compatible = "qcom,sm6350-gpi-dma"; 970 reg = <0x0 0x00900000 0x0 0x60000>; 971 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 648 IRQ_TYPE_LEVEL_HIGH>, 975 <GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH>, 976 <GIC_SPI 650 IRQ_TYPE_LEVEL_HIGH>, 977 <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>, 978 <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 979 <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>, 980 <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>; 981 dma-channels = <10>; 982 dma-channel-mask = <0x3f>; 983 iommus = <&apps_smmu 0x4d6 0x0>; 984 #dma-cells = <3>; 985 status = "disabled"; 986 }; 987 988 qupv3_id_1: geniqup@9c0000 { 989 compatible = "qcom,geni-se-qup"; 990 reg = <0x0 0x009c0000 0x0 0x2000>; 991 clock-names = "m-ahb", "s-ahb"; 992 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 993 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 994 #address-cells = <2>; 995 #size-cells = <2>; 996 iommus = <&apps_smmu 0x4c3 0x0>; 997 ranges; 998 status = "disabled"; 999 1000 i2c6: i2c@980000 { 1001 compatible = "qcom,geni-i2c"; 1002 reg = <0x0 0x00980000 0x0 0x4000>; 1003 clock-names = "se"; 1004 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1005 pinctrl-names = "default"; 1006 pinctrl-0 = <&qup_i2c6_default>; 1007 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1008 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1009 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1010 dma-names = "tx", "rx"; 1011 #address-cells = <1>; 1012 #size-cells = <0>; 1013 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1014 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1015 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1016 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1017 status = "disabled"; 1018 }; 1019 1020 i2c7: i2c@984000 { 1021 compatible = "qcom,geni-i2c"; 1022 reg = <0x0 0x00984000 0x0 0x4000>; 1023 clock-names = "se"; 1024 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1025 pinctrl-names = "default"; 1026 pinctrl-0 = <&qup_i2c7_default>; 1027 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1028 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1029 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1030 dma-names = "tx", "rx"; 1031 #address-cells = <1>; 1032 #size-cells = <0>; 1033 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1034 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1035 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1036 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1037 status = "disabled"; 1038 }; 1039 1040 i2c8: i2c@988000 { 1041 compatible = "qcom,geni-i2c"; 1042 reg = <0x0 0x00988000 0x0 0x4000>; 1043 clock-names = "se"; 1044 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1045 pinctrl-names = "default"; 1046 pinctrl-0 = <&qup_i2c8_default>; 1047 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1048 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1049 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1050 dma-names = "tx", "rx"; 1051 #address-cells = <1>; 1052 #size-cells = <0>; 1053 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1054 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1055 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1056 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1057 status = "disabled"; 1058 }; 1059 1060 uart9: serial@98c000 { 1061 compatible = "qcom,geni-debug-uart"; 1062 reg = <0x0 0x0098c000 0x0 0x4000>; 1063 clock-names = "se"; 1064 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1065 pinctrl-names = "default"; 1066 pinctrl-0 = <&qup_uart9_default>; 1067 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1068 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1069 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1070 interconnect-names = "qup-core", "qup-config"; 1071 status = "disabled"; 1072 }; 1073 1074 i2c10: i2c@990000 { 1075 compatible = "qcom,geni-i2c"; 1076 reg = <0x0 0x00990000 0x0 0x4000>; 1077 clock-names = "se"; 1078 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1079 pinctrl-names = "default"; 1080 pinctrl-0 = <&qup_i2c10_default>; 1081 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1082 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1083 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1084 dma-names = "tx", "rx"; 1085 #address-cells = <1>; 1086 #size-cells = <0>; 1087 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1088 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1089 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1090 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1091 status = "disabled"; 1092 }; 1093 }; 1094 1095 config_noc: interconnect@1500000 { 1096 compatible = "qcom,sm6350-config-noc"; 1097 reg = <0x0 0x01500000 0x0 0x28000>; 1098 #interconnect-cells = <2>; 1099 qcom,bcm-voters = <&apps_bcm_voter>; 1100 }; 1101 1102 system_noc: interconnect@1620000 { 1103 compatible = "qcom,sm6350-system-noc"; 1104 reg = <0x0 0x01620000 0x0 0x17080>; 1105 #interconnect-cells = <2>; 1106 qcom,bcm-voters = <&apps_bcm_voter>; 1107 1108 clk_virt: interconnect-clk-virt { 1109 compatible = "qcom,sm6350-clk-virt"; 1110 #interconnect-cells = <2>; 1111 qcom,bcm-voters = <&apps_bcm_voter>; 1112 }; 1113 }; 1114 1115 aggre1_noc: interconnect@16e0000 { 1116 compatible = "qcom,sm6350-aggre1-noc"; 1117 reg = <0x0 0x016e0000 0x0 0x15080>; 1118 #interconnect-cells = <2>; 1119 qcom,bcm-voters = <&apps_bcm_voter>; 1120 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; 1121 }; 1122 1123 aggre2_noc: interconnect@1700000 { 1124 compatible = "qcom,sm6350-aggre2-noc"; 1125 reg = <0x0 0x01700000 0x0 0x1f880>; 1126 #interconnect-cells = <2>; 1127 qcom,bcm-voters = <&apps_bcm_voter>; 1128 clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1129 <&rpmhcc RPMH_IPA_CLK>; 1130 1131 compute_noc: interconnect-compute-noc { 1132 compatible = "qcom,sm6350-compute-noc"; 1133 #interconnect-cells = <2>; 1134 qcom,bcm-voters = <&apps_bcm_voter>; 1135 }; 1136 }; 1137 1138 mmss_noc: interconnect@1740000 { 1139 compatible = "qcom,sm6350-mmss-noc"; 1140 reg = <0x0 0x01740000 0x0 0x1c100>; 1141 #interconnect-cells = <2>; 1142 qcom,bcm-voters = <&apps_bcm_voter>; 1143 }; 1144 1145 ufs_mem_hc: ufshc@1d84000 { 1146 compatible = "qcom,sm6350-ufshc", "qcom,ufshc", 1147 "jedec,ufs-2.0"; 1148 reg = <0x0 0x01d84000 0x0 0x3000>, 1149 <0x0 0x01d90000 0x0 0x8000>; 1150 reg-names = "std", "ice"; 1151 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1152 phys = <&ufs_mem_phy>; 1153 phy-names = "ufsphy"; 1154 lanes-per-direction = <2>; 1155 #reset-cells = <1>; 1156 resets = <&gcc GCC_UFS_PHY_BCR>; 1157 reset-names = "rst"; 1158 1159 power-domains = <&gcc UFS_PHY_GDSC>; 1160 1161 iommus = <&apps_smmu 0x80 0x0>; 1162 1163 clock-names = "core_clk", 1164 "bus_aggr_clk", 1165 "iface_clk", 1166 "core_clk_unipro", 1167 "ref_clk", 1168 "tx_lane0_sync_clk", 1169 "rx_lane0_sync_clk", 1170 "rx_lane1_sync_clk", 1171 "ice_core_clk"; 1172 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1173 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1174 <&gcc GCC_UFS_PHY_AHB_CLK>, 1175 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1176 <&rpmhcc RPMH_QLINK_CLK>, 1177 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1178 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1179 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 1180 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1181 1182 operating-points-v2 = <&ufs_opp_table>; 1183 1184 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 1185 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, 1186 <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 1187 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 1188 interconnect-names = "ufs-ddr", 1189 "cpu-ufs"; 1190 1191 status = "disabled"; 1192 1193 ufs_opp_table: opp-table { 1194 compatible = "operating-points-v2"; 1195 1196 opp-50000000 { 1197 opp-hz = /bits/ 64 <50000000>, 1198 /bits/ 64 <0>, 1199 /bits/ 64 <0>, 1200 /bits/ 64 <37500000>, 1201 /bits/ 64 <0>, 1202 /bits/ 64 <0>, 1203 /bits/ 64 <0>, 1204 /bits/ 64 <0>, 1205 /bits/ 64 <75000000>; 1206 required-opps = <&rpmhpd_opp_low_svs>; 1207 }; 1208 1209 opp-200000000 { 1210 opp-hz = /bits/ 64 <200000000>, 1211 /bits/ 64 <0>, 1212 /bits/ 64 <0>, 1213 /bits/ 64 <150000000>, 1214 /bits/ 64 <0>, 1215 /bits/ 64 <0>, 1216 /bits/ 64 <0>, 1217 /bits/ 64 <0>, 1218 /bits/ 64 <300000000>; 1219 required-opps = <&rpmhpd_opp_nom>; 1220 }; 1221 }; 1222 }; 1223 1224 ufs_mem_phy: phy@1d87000 { 1225 compatible = "qcom,sm6350-qmp-ufs-phy"; 1226 reg = <0x0 0x01d87000 0x0 0x1000>; 1227 1228 clocks = <&rpmhcc RPMH_CXO_CLK>, 1229 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1230 <&gcc GCC_UFS_MEM_CLKREF_CLK>; 1231 clock-names = "ref", 1232 "ref_aux", 1233 "qref"; 1234 1235 power-domains = <&gcc UFS_PHY_GDSC>; 1236 1237 resets = <&ufs_mem_hc 0>; 1238 reset-names = "ufsphy"; 1239 1240 #phy-cells = <0>; 1241 1242 status = "disabled"; 1243 }; 1244 1245 cryptobam: dma-controller@1dc4000 { 1246 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1247 reg = <0x0 0x01dc4000 0x0 0x24000>; 1248 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1249 #dma-cells = <1>; 1250 qcom,ee = <0>; 1251 qcom,controlled-remotely; 1252 num-channels = <16>; 1253 qcom,num-ees = <4>; 1254 iommus = <&apps_smmu 0x426 0x11>, 1255 <&apps_smmu 0x432 0x0>, 1256 <&apps_smmu 0x436 0x11>, 1257 <&apps_smmu 0x438 0x1>, 1258 <&apps_smmu 0x43f 0x0>; 1259 }; 1260 1261 crypto: crypto@1dfa000 { 1262 compatible = "qcom,sm6350-qce", "qcom,sm8150-qce", "qcom,qce"; 1263 reg = <0x0 0x01dfa000 0x0 0x6000>; 1264 dmas = <&cryptobam 4>, <&cryptobam 5>; 1265 dma-names = "rx", "tx"; 1266 iommus = <&apps_smmu 0x426 0x11>, 1267 <&apps_smmu 0x432 0x0>, 1268 <&apps_smmu 0x436 0x11>, 1269 <&apps_smmu 0x438 0x1>, 1270 <&apps_smmu 0x43f 0x0>; 1271 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 QCOM_ICC_TAG_ALWAYS 1272 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; 1273 interconnect-names = "memory"; 1274 }; 1275 1276 ipa: ipa@1e40000 { 1277 compatible = "qcom,sm6350-ipa"; 1278 1279 iommus = <&apps_smmu 0x440 0x0>, 1280 <&apps_smmu 0x442 0x0>; 1281 reg = <0x0 0x01e40000 0x0 0x8000>, 1282 <0x0 0x01e50000 0x0 0x3000>, 1283 <0x0 0x01e04000 0x0 0x23000>; 1284 reg-names = "ipa-reg", 1285 "ipa-shared", 1286 "gsi"; 1287 1288 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 1289 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1290 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1291 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1292 interrupt-names = "ipa", 1293 "gsi", 1294 "ipa-clock-query", 1295 "ipa-setup-ready"; 1296 1297 clocks = <&rpmhcc RPMH_IPA_CLK>; 1298 clock-names = "core"; 1299 1300 interconnects = <&aggre2_noc MASTER_IPA 0 &clk_virt SLAVE_EBI_CH0 0>, 1301 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_OCIMEM 0>, 1302 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_IPA_CFG 0>; 1303 interconnect-names = "memory", "imem", "config"; 1304 1305 qcom,smem-states = <&ipa_smp2p_out 0>, 1306 <&ipa_smp2p_out 1>; 1307 qcom,smem-state-names = "ipa-clock-enabled-valid", 1308 "ipa-clock-enabled"; 1309 1310 sram = <&ipa_modem_tables>; 1311 1312 status = "disabled"; 1313 }; 1314 1315 tcsr_mutex: hwlock@1f40000 { 1316 compatible = "qcom,tcsr-mutex"; 1317 reg = <0x0 0x01f40000 0x0 0x40000>; 1318 #hwlock-cells = <1>; 1319 }; 1320 1321 adsp: remoteproc@3000000 { 1322 compatible = "qcom,sm6350-adsp-pas"; 1323 reg = <0x0 0x03000000 0x0 0x10000>; 1324 1325 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 1326 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1327 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1328 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1329 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1330 interrupt-names = "wdog", "fatal", "ready", 1331 "handover", "stop-ack"; 1332 1333 clocks = <&rpmhcc RPMH_CXO_CLK>; 1334 clock-names = "xo"; 1335 1336 power-domains = <&rpmhpd SM6350_LCX>, 1337 <&rpmhpd SM6350_LMX>; 1338 power-domain-names = "lcx", "lmx"; 1339 1340 memory-region = <&pil_adsp_mem>; 1341 1342 qcom,qmp = <&aoss_qmp>; 1343 1344 qcom,smem-states = <&smp2p_adsp_out 0>; 1345 qcom,smem-state-names = "stop"; 1346 1347 status = "disabled"; 1348 1349 glink-edge { 1350 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1351 IPCC_MPROC_SIGNAL_GLINK_QMP 1352 IRQ_TYPE_EDGE_RISING>; 1353 mboxes = <&ipcc IPCC_CLIENT_LPASS 1354 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1355 1356 label = "lpass"; 1357 qcom,remote-pid = <2>; 1358 1359 apr { 1360 compatible = "qcom,apr-v2"; 1361 qcom,glink-channels = "apr_audio_svc"; 1362 qcom,domain = <APR_DOMAIN_ADSP>; 1363 #address-cells = <1>; 1364 #size-cells = <0>; 1365 1366 service@3 { 1367 reg = <APR_SVC_ADSP_CORE>; 1368 compatible = "qcom,q6core"; 1369 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1370 }; 1371 1372 q6afe: service@4 { 1373 compatible = "qcom,q6afe"; 1374 reg = <APR_SVC_AFE>; 1375 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1376 1377 q6afedai: dais { 1378 compatible = "qcom,q6afe-dais"; 1379 #address-cells = <1>; 1380 #size-cells = <0>; 1381 #sound-dai-cells = <1>; 1382 }; 1383 1384 q6afecc: clock-controller { 1385 compatible = "qcom,q6afe-clocks"; 1386 #clock-cells = <2>; 1387 }; 1388 1389 q6usbdai: usbd { 1390 compatible = "qcom,q6usb"; 1391 iommus = <&apps_smmu 0x100f 0x0>; 1392 #sound-dai-cells = <1>; 1393 qcom,usb-audio-intr-idx = /bits/ 16 <2>; 1394 }; 1395 }; 1396 1397 q6asm: service@7 { 1398 compatible = "qcom,q6asm"; 1399 reg = <APR_SVC_ASM>; 1400 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1401 1402 q6asmdai: dais { 1403 compatible = "qcom,q6asm-dais"; 1404 #address-cells = <1>; 1405 #size-cells = <0>; 1406 #sound-dai-cells = <1>; 1407 iommus = <&apps_smmu 0x1001 0x0>; 1408 }; 1409 }; 1410 1411 q6adm: service@8 { 1412 compatible = "qcom,q6adm"; 1413 reg = <APR_SVC_ADM>; 1414 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1415 1416 q6routing: routing { 1417 compatible = "qcom,q6adm-routing"; 1418 #sound-dai-cells = <0>; 1419 }; 1420 }; 1421 }; 1422 1423 fastrpc { 1424 compatible = "qcom,fastrpc"; 1425 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1426 label = "adsp"; 1427 qcom,non-secure-domain; 1428 #address-cells = <1>; 1429 #size-cells = <0>; 1430 1431 compute-cb@3 { 1432 compatible = "qcom,fastrpc-compute-cb"; 1433 reg = <3>; 1434 iommus = <&apps_smmu 0x1003 0x0>; 1435 }; 1436 1437 compute-cb@4 { 1438 compatible = "qcom,fastrpc-compute-cb"; 1439 reg = <4>; 1440 iommus = <&apps_smmu 0x1004 0x0>; 1441 }; 1442 1443 compute-cb@5 { 1444 compatible = "qcom,fastrpc-compute-cb"; 1445 reg = <5>; 1446 iommus = <&apps_smmu 0x1005 0x0>; 1447 qcom,nsessions = <5>; 1448 }; 1449 }; 1450 }; 1451 }; 1452 1453 gpu: gpu@3d00000 { 1454 compatible = "qcom,adreno-619.0", "qcom,adreno"; 1455 reg = <0x0 0x03d00000 0x0 0x40000>, 1456 <0x0 0x03d9e000 0x0 0x1000>; 1457 reg-names = "kgsl_3d0_reg_memory", 1458 "cx_mem"; 1459 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1460 1461 iommus = <&adreno_smmu 0>; 1462 operating-points-v2 = <&gpu_opp_table>; 1463 qcom,gmu = <&gmu>; 1464 nvmem-cells = <&gpu_speed_bin>; 1465 nvmem-cell-names = "speed_bin"; 1466 #cooling-cells = <2>; 1467 1468 status = "disabled"; 1469 1470 gpu_zap_shader: zap-shader { 1471 memory-region = <&pil_gpu_mem>; 1472 }; 1473 1474 gpu_opp_table: opp-table { 1475 compatible = "operating-points-v2"; 1476 1477 opp-850000000 { 1478 opp-hz = /bits/ 64 <850000000>; 1479 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1480 opp-supported-hw = <0x03>; 1481 }; 1482 1483 opp-800000000 { 1484 opp-hz = /bits/ 64 <800000000>; 1485 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1486 opp-supported-hw = <0x07>; 1487 }; 1488 1489 opp-650000000 { 1490 opp-hz = /bits/ 64 <650000000>; 1491 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1492 opp-supported-hw = <0x0f>; 1493 }; 1494 1495 opp-565000000 { 1496 opp-hz = /bits/ 64 <565000000>; 1497 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1498 opp-supported-hw = <0x1f>; 1499 }; 1500 1501 opp-430000000 { 1502 opp-hz = /bits/ 64 <430000000>; 1503 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1504 opp-supported-hw = <0x1f>; 1505 }; 1506 1507 opp-355000000 { 1508 opp-hz = /bits/ 64 <355000000>; 1509 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1510 opp-supported-hw = <0x1f>; 1511 }; 1512 1513 opp-253000000 { 1514 opp-hz = /bits/ 64 <253000000>; 1515 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1516 opp-supported-hw = <0x1f>; 1517 }; 1518 }; 1519 }; 1520 1521 adreno_smmu: iommu@3d40000 { 1522 compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 1523 reg = <0x0 0x03d40000 0x0 0x10000>; 1524 #iommu-cells = <1>; 1525 #global-interrupts = <2>; 1526 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1536 1537 clocks = <&gpucc GPU_CC_AHB_CLK>, 1538 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1539 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1540 clock-names = "ahb", 1541 "bus", 1542 "iface"; 1543 1544 power-domains = <&gpucc GPU_CX_GDSC>; 1545 }; 1546 1547 gmu: gmu@3d6a000 { 1548 compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu"; 1549 reg = <0x0 0x03d6a000 0x0 0x31000>, 1550 <0x0 0x0b290000 0x0 0x10000>, 1551 <0x0 0x0b490000 0x0 0x10000>; 1552 reg-names = "gmu", 1553 "gmu_pdc", 1554 "gmu_pdc_seq"; 1555 1556 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1557 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1558 interrupt-names = "hfi", 1559 "gmu"; 1560 1561 clocks = <&gpucc GPU_CC_AHB_CLK>, 1562 <&gpucc GPU_CC_CX_GMU_CLK>, 1563 <&gpucc GPU_CC_CXO_CLK>, 1564 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1565 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1566 clock-names = "ahb", 1567 "gmu", 1568 "cxo", 1569 "axi", 1570 "memnoc"; 1571 1572 power-domains = <&gpucc GPU_CX_GDSC>, 1573 <&gpucc GPU_GX_GDSC>; 1574 power-domain-names = "cx", 1575 "gx"; 1576 1577 iommus = <&adreno_smmu 5>; 1578 1579 operating-points-v2 = <&gmu_opp_table>; 1580 1581 gmu_opp_table: opp-table { 1582 compatible = "operating-points-v2"; 1583 1584 opp-200000000 { 1585 opp-hz = /bits/ 64 <200000000>; 1586 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1587 }; 1588 }; 1589 }; 1590 1591 gpucc: clock-controller@3d90000 { 1592 compatible = "qcom,sm6350-gpucc"; 1593 reg = <0x0 0x03d90000 0x0 0x9000>; 1594 clocks = <&rpmhcc RPMH_CXO_CLK>, 1595 <&gcc GCC_GPU_GPLL0_CLK>, 1596 <&gcc GCC_GPU_GPLL0_DIV_CLK>; 1597 clock-names = "bi_tcxo", 1598 "gcc_gpu_gpll0_clk_src", 1599 "gcc_gpu_gpll0_div_clk_src"; 1600 #clock-cells = <1>; 1601 #reset-cells = <1>; 1602 #power-domain-cells = <1>; 1603 }; 1604 1605 mpss: remoteproc@4080000 { 1606 compatible = "qcom,sm6350-mpss-pas"; 1607 reg = <0x0 0x04080000 0x0 0x10000>; 1608 1609 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 1610 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1611 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1612 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1613 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1614 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1615 interrupt-names = "wdog", "fatal", "ready", "handover", 1616 "stop-ack", "shutdown-ack"; 1617 1618 clocks = <&rpmhcc RPMH_CXO_CLK>; 1619 clock-names = "xo"; 1620 1621 power-domains = <&rpmhpd SM6350_CX>, 1622 <&rpmhpd SM6350_MSS>; 1623 power-domain-names = "cx", "mss"; 1624 1625 memory-region = <&pil_modem_mem>; 1626 1627 qcom,qmp = <&aoss_qmp>; 1628 1629 qcom,smem-states = <&modem_smp2p_out 0>; 1630 qcom,smem-state-names = "stop"; 1631 1632 status = "disabled"; 1633 1634 glink-edge { 1635 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1636 IPCC_MPROC_SIGNAL_GLINK_QMP 1637 IRQ_TYPE_EDGE_RISING>; 1638 mboxes = <&ipcc IPCC_CLIENT_MPSS 1639 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1640 label = "modem"; 1641 qcom,remote-pid = <1>; 1642 }; 1643 }; 1644 1645 cdsp: remoteproc@8300000 { 1646 compatible = "qcom,sm6350-cdsp-pas"; 1647 reg = <0x0 0x08300000 0x0 0x10000>; 1648 1649 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 1650 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 1651 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 1652 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 1653 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 1654 interrupt-names = "wdog", "fatal", "ready", 1655 "handover", "stop-ack"; 1656 1657 clocks = <&rpmhcc RPMH_CXO_CLK>; 1658 clock-names = "xo"; 1659 1660 power-domains = <&rpmhpd SM6350_CX>, 1661 <&rpmhpd SM6350_MX>; 1662 power-domain-names = "cx", "mx"; 1663 1664 memory-region = <&pil_cdsp_mem>; 1665 1666 qcom,qmp = <&aoss_qmp>; 1667 1668 qcom,smem-states = <&smp2p_cdsp_out 0>; 1669 qcom,smem-state-names = "stop"; 1670 1671 status = "disabled"; 1672 1673 glink-edge { 1674 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 1675 IPCC_MPROC_SIGNAL_GLINK_QMP 1676 IRQ_TYPE_EDGE_RISING>; 1677 mboxes = <&ipcc IPCC_CLIENT_CDSP 1678 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1679 1680 label = "cdsp"; 1681 qcom,remote-pid = <5>; 1682 1683 fastrpc { 1684 compatible = "qcom,fastrpc"; 1685 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1686 label = "cdsp"; 1687 qcom,non-secure-domain; 1688 #address-cells = <1>; 1689 #size-cells = <0>; 1690 1691 compute-cb@1 { 1692 compatible = "qcom,fastrpc-compute-cb"; 1693 reg = <1>; 1694 iommus = <&apps_smmu 0x1401 0x20>; 1695 }; 1696 1697 compute-cb@2 { 1698 compatible = "qcom,fastrpc-compute-cb"; 1699 reg = <2>; 1700 iommus = <&apps_smmu 0x1402 0x20>; 1701 }; 1702 1703 compute-cb@3 { 1704 compatible = "qcom,fastrpc-compute-cb"; 1705 reg = <3>; 1706 iommus = <&apps_smmu 0x1403 0x20>; 1707 }; 1708 1709 compute-cb@4 { 1710 compatible = "qcom,fastrpc-compute-cb"; 1711 reg = <4>; 1712 iommus = <&apps_smmu 0x1404 0x20>; 1713 }; 1714 1715 compute-cb@5 { 1716 compatible = "qcom,fastrpc-compute-cb"; 1717 reg = <5>; 1718 iommus = <&apps_smmu 0x1405 0x20>; 1719 }; 1720 1721 compute-cb@6 { 1722 compatible = "qcom,fastrpc-compute-cb"; 1723 reg = <6>; 1724 iommus = <&apps_smmu 0x1406 0x20>; 1725 }; 1726 1727 compute-cb@7 { 1728 compatible = "qcom,fastrpc-compute-cb"; 1729 reg = <7>; 1730 iommus = <&apps_smmu 0x1407 0x20>; 1731 }; 1732 1733 compute-cb@8 { 1734 compatible = "qcom,fastrpc-compute-cb"; 1735 reg = <8>; 1736 iommus = <&apps_smmu 0x1408 0x20>; 1737 }; 1738 1739 /* note: secure cb9 in downstream */ 1740 }; 1741 }; 1742 }; 1743 1744 sdhc_2: mmc@8804000 { 1745 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 1746 reg = <0x0 0x08804000 0x0 0x1000>; 1747 1748 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1749 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1750 interrupt-names = "hc_irq", "pwr_irq"; 1751 iommus = <&apps_smmu 0x560 0x0>; 1752 1753 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1754 <&gcc GCC_SDCC2_APPS_CLK>, 1755 <&rpmhcc RPMH_CXO_CLK>; 1756 clock-names = "iface", "core", "xo"; 1757 resets = <&gcc GCC_SDCC2_BCR>; 1758 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>, 1759 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>; 1760 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 1761 1762 pinctrl-0 = <&sdc2_on_state>; 1763 pinctrl-1 = <&sdc2_off_state>; 1764 pinctrl-names = "default", "sleep"; 1765 1766 qcom,dll-config = <0x0007642c>; 1767 qcom,ddr-config = <0x80040868>; 1768 power-domains = <&rpmhpd SM6350_CX>; 1769 operating-points-v2 = <&sdhc2_opp_table>; 1770 bus-width = <4>; 1771 1772 status = "disabled"; 1773 1774 sdhc2_opp_table: opp-table { 1775 compatible = "operating-points-v2"; 1776 1777 opp-100000000 { 1778 opp-hz = /bits/ 64 <100000000>; 1779 required-opps = <&rpmhpd_opp_svs_l1>; 1780 opp-peak-kBps = <790000 131000>; 1781 opp-avg-kBps = <50000 50000>; 1782 }; 1783 1784 opp-202000000 { 1785 opp-hz = /bits/ 64 <202000000>; 1786 required-opps = <&rpmhpd_opp_nom>; 1787 opp-peak-kBps = <3190000 294000>; 1788 opp-avg-kBps = <261438 300000>; 1789 }; 1790 }; 1791 }; 1792 1793 usb_1_hsphy: phy@88e3000 { 1794 compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy"; 1795 reg = <0x0 0x088e3000 0x0 0x400>; 1796 status = "disabled"; 1797 #phy-cells = <0>; 1798 1799 clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>; 1800 clock-names = "cfg_ahb", "ref"; 1801 1802 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1803 }; 1804 1805 refgen: regulator@88e7000 { 1806 compatible = "qcom,sm6350-refgen-regulator", 1807 "qcom,sm8250-refgen-regulator"; 1808 reg = <0x0 0x088e7000 0x0 0x84>; 1809 }; 1810 1811 usb_1_qmpphy: phy@88e8000 { 1812 compatible = "qcom,sm6350-qmp-usb3-dp-phy"; 1813 reg = <0x0 0x088e8000 0x0 0x3000>; 1814 1815 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1816 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 1817 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 1818 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1819 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 1820 1821 power-domains = <&gcc USB30_PRIM_GDSC>; 1822 1823 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 1824 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 1825 reset-names = "phy", "common"; 1826 1827 orientation-switch; 1828 1829 #clock-cells = <1>; 1830 #phy-cells = <1>; 1831 1832 status = "disabled"; 1833 1834 ports { 1835 #address-cells = <1>; 1836 #size-cells = <0>; 1837 1838 port@0 { 1839 reg = <0>; 1840 1841 usb_1_qmpphy_out: endpoint { 1842 }; 1843 }; 1844 1845 port@1 { 1846 reg = <1>; 1847 1848 usb_1_qmpphy_usb_ss_in: endpoint { 1849 remote-endpoint = <&usb_1_dwc3_ss_out>; 1850 }; 1851 }; 1852 1853 port@2 { 1854 reg = <2>; 1855 1856 usb_1_qmpphy_dp_in: endpoint { 1857 }; 1858 }; 1859 }; 1860 }; 1861 1862 dc_noc: interconnect@9160000 { 1863 compatible = "qcom,sm6350-dc-noc"; 1864 reg = <0x0 0x09160000 0x0 0x3200>; 1865 #interconnect-cells = <2>; 1866 qcom,bcm-voters = <&apps_bcm_voter>; 1867 }; 1868 1869 system-cache-controller@9200000 { 1870 compatible = "qcom,sm6350-llcc"; 1871 reg = <0x0 0x09200000 0x0 0x50000>, <0x0 0x09600000 0x0 0x50000>; 1872 reg-names = "llcc0_base", "llcc_broadcast_base"; 1873 }; 1874 1875 gem_noc: interconnect@9680000 { 1876 compatible = "qcom,sm6350-gem-noc"; 1877 reg = <0x0 0x09680000 0x0 0x3e200>; 1878 #interconnect-cells = <2>; 1879 qcom,bcm-voters = <&apps_bcm_voter>; 1880 }; 1881 1882 npu_noc: interconnect@9990000 { 1883 compatible = "qcom,sm6350-npu-noc"; 1884 reg = <0x0 0x09990000 0x0 0x1600>; 1885 #interconnect-cells = <2>; 1886 qcom,bcm-voters = <&apps_bcm_voter>; 1887 }; 1888 1889 pmu@90b6300 { 1890 compatible = "qcom,sm6350-llcc-bwmon", "qcom,sdm845-bwmon"; 1891 reg = <0x0 0x090b6300 0x0 0x600>; 1892 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 1893 1894 operating-points-v2 = <&llcc_bwmon_opp_table>; 1895 interconnects = <&clk_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 1896 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>; 1897 1898 llcc_bwmon_opp_table: opp-table { 1899 compatible = "operating-points-v2"; 1900 1901 opp-0 { 1902 opp-peak-kBps = <2288000>; 1903 }; 1904 1905 opp-1 { 1906 opp-peak-kBps = <4577000>; 1907 }; 1908 1909 opp-2 { 1910 opp-peak-kBps = <7110000>; 1911 }; 1912 1913 opp-3 { 1914 opp-peak-kBps = <9155000>; 1915 }; 1916 1917 opp-4 { 1918 opp-peak-kBps = <12298000>; 1919 }; 1920 1921 opp-5 { 1922 opp-peak-kBps = <14236000>; 1923 }; 1924 1925 }; 1926 }; 1927 1928 pmu@90cd000 { 1929 compatible = "qcom,sm6350-cpu-bwmon", "qcom,sc7280-llcc-bwmon"; 1930 reg = <0x0 0x090cd000 0x0 0x1000>; 1931 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1932 1933 operating-points-v2 = <&cpu_bwmon_opp_table>; 1934 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 1935 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>; 1936 1937 cpu_bwmon_opp_table: opp-table { 1938 compatible = "operating-points-v2"; 1939 1940 opp-0 { 1941 opp-peak-kBps = <762000>; 1942 }; 1943 1944 opp-1 { 1945 opp-peak-kBps = <1144000>; 1946 }; 1947 1948 opp-2 { 1949 opp-peak-kBps = <1720000>; 1950 }; 1951 1952 opp-3 { 1953 opp-peak-kBps = <2086000>; 1954 }; 1955 1956 opp-4 { 1957 opp-peak-kBps = <2597000>; 1958 }; 1959 1960 opp-5 { 1961 opp-peak-kBps = <2929000>; 1962 }; 1963 1964 opp-6 { 1965 opp-peak-kBps = <3879000>; 1966 }; 1967 1968 opp-7 { 1969 opp-peak-kBps = <5161000>; 1970 }; 1971 1972 opp-8 { 1973 opp-peak-kBps = <5931000>; 1974 }; 1975 1976 opp-9 { 1977 opp-peak-kBps = <6881000>; 1978 }; 1979 1980 opp-10 { 1981 opp-peak-kBps = <7980000>; 1982 }; 1983 }; 1984 }; 1985 1986 usb_1: usb@a6f8800 { 1987 compatible = "qcom,sm6350-dwc3", "qcom,dwc3"; 1988 reg = <0x0 0x0a6f8800 0x0 0x400>; 1989 status = "disabled"; 1990 #address-cells = <2>; 1991 #size-cells = <2>; 1992 ranges; 1993 1994 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1995 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1996 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1997 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1998 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 1999 clock-names = "cfg_noc", 2000 "core", 2001 "iface", 2002 "sleep", 2003 "mock_utmi"; 2004 2005 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2006 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2007 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2008 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2009 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2010 interrupt-names = "pwr_event", 2011 "hs_phy_irq", 2012 "dp_hs_phy_irq", 2013 "dm_hs_phy_irq", 2014 "ss_phy_irq"; 2015 2016 power-domains = <&gcc USB30_PRIM_GDSC>; 2017 2018 resets = <&gcc GCC_USB30_PRIM_BCR>; 2019 2020 interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>, 2021 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 2022 interconnect-names = "usb-ddr", "apps-usb"; 2023 2024 usb_1_dwc3: usb@a600000 { 2025 compatible = "snps,dwc3"; 2026 reg = <0x0 0x0a600000 0x0 0xcd00>; 2027 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2028 iommus = <&apps_smmu 0x540 0x0>; 2029 num-hc-interrupters = /bits/ 16 <3>; 2030 snps,dis_u2_susphy_quirk; 2031 snps,dis_enblslpm_quirk; 2032 snps,has-lpm-erratum; 2033 snps,hird-threshold = /bits/ 8 <0x10>; 2034 snps,parkmode-disable-ss-quirk; 2035 snps,dis-u1-entry-quirk; 2036 snps,dis-u2-entry-quirk; 2037 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 2038 phy-names = "usb2-phy", "usb3-phy"; 2039 usb-role-switch; 2040 2041 ports { 2042 #address-cells = <1>; 2043 #size-cells = <0>; 2044 2045 port@0 { 2046 reg = <0>; 2047 2048 usb_1_dwc3_hs_out: endpoint { 2049 }; 2050 }; 2051 2052 port@1 { 2053 reg = <1>; 2054 2055 usb_1_dwc3_ss_out: endpoint { 2056 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 2057 }; 2058 }; 2059 }; 2060 }; 2061 }; 2062 2063 videocc: clock-controller@aaf0000 { 2064 compatible = "qcom,sm6350-videocc"; 2065 reg = <0x0 0x0aaf0000 0x0 0x10000>; 2066 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 2067 <&rpmhcc RPMH_CXO_CLK>, 2068 <&sleep_clk>; 2069 clock-names = "iface", 2070 "bi_tcxo", 2071 "sleep_clk"; 2072 #clock-cells = <1>; 2073 #reset-cells = <1>; 2074 #power-domain-cells = <1>; 2075 }; 2076 2077 cci0: cci@ac4a000 { 2078 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; 2079 reg = <0x0 0x0ac4a000 0x0 0x1000>; 2080 interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>; 2081 power-domains = <&camcc TITAN_TOP_GDSC>; 2082 2083 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 2084 <&camcc CAMCC_SOC_AHB_CLK>, 2085 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 2086 <&camcc CAMCC_CPAS_AHB_CLK>, 2087 <&camcc CAMCC_CCI_0_CLK>, 2088 <&camcc CAMCC_CCI_0_CLK_SRC>; 2089 clock-names = "camnoc_axi", 2090 "soc_ahb", 2091 "slow_ahb_src", 2092 "cpas_ahb", 2093 "cci", 2094 "cci_src"; 2095 2096 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 2097 <&camcc CAMCC_CCI_0_CLK>; 2098 assigned-clock-rates = <80000000>, <37500000>; 2099 2100 pinctrl-0 = <&cci0_default &cci1_default>; 2101 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 2102 pinctrl-names = "default", "sleep"; 2103 2104 #address-cells = <1>; 2105 #size-cells = <0>; 2106 2107 status = "disabled"; 2108 2109 cci0_i2c0: i2c-bus@0 { 2110 reg = <0>; 2111 clock-frequency = <1000000>; 2112 #address-cells = <1>; 2113 #size-cells = <0>; 2114 }; 2115 2116 cci0_i2c1: i2c-bus@1 { 2117 reg = <1>; 2118 clock-frequency = <1000000>; 2119 #address-cells = <1>; 2120 #size-cells = <0>; 2121 }; 2122 }; 2123 2124 cci1: cci@ac4b000 { 2125 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; 2126 reg = <0x0 0x0ac4b000 0x0 0x1000>; 2127 interrupts = <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>; 2128 power-domains = <&camcc TITAN_TOP_GDSC>; 2129 2130 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 2131 <&camcc CAMCC_SOC_AHB_CLK>, 2132 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 2133 <&camcc CAMCC_CPAS_AHB_CLK>, 2134 <&camcc CAMCC_CCI_1_CLK>, 2135 <&camcc CAMCC_CCI_1_CLK_SRC>; 2136 clock-names = "camnoc_axi", 2137 "soc_ahb", 2138 "slow_ahb_src", 2139 "cpas_ahb", 2140 "cci", 2141 "cci_src"; 2142 2143 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 2144 <&camcc CAMCC_CCI_1_CLK>; 2145 assigned-clock-rates = <80000000>, <37500000>; 2146 2147 pinctrl-0 = <&cci2_default>; 2148 pinctrl-1 = <&cci2_sleep>; 2149 pinctrl-names = "default", "sleep"; 2150 2151 #address-cells = <1>; 2152 #size-cells = <0>; 2153 2154 status = "disabled"; 2155 2156 cci1_i2c0: i2c-bus@0 { 2157 reg = <0>; 2158 clock-frequency = <1000000>; 2159 #address-cells = <1>; 2160 #size-cells = <0>; 2161 }; 2162 2163 /* SM6350 seems to have cci1_i2c1 on gpio2 & gpio3 but unused downstream */ 2164 }; 2165 2166 camcc: clock-controller@ad00000 { 2167 compatible = "qcom,sm6350-camcc"; 2168 reg = <0x0 0x0ad00000 0x0 0x16000>; 2169 clocks = <&rpmhcc RPMH_CXO_CLK>; 2170 #clock-cells = <1>; 2171 #reset-cells = <1>; 2172 #power-domain-cells = <1>; 2173 }; 2174 2175 mdss: display-subsystem@ae00000 { 2176 compatible = "qcom,sm6350-mdss"; 2177 reg = <0x0 0x0ae00000 0x0 0x1000>; 2178 reg-names = "mdss"; 2179 2180 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2181 interrupt-controller; 2182 #interrupt-cells = <1>; 2183 2184 interconnects = <&mmss_noc MASTER_MDP_PORT0 QCOM_ICC_TAG_ALWAYS 2185 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, 2186 <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 2187 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 2188 interconnect-names = "mdp0-mem", 2189 "cpu-cfg"; 2190 2191 clocks = <&gcc GCC_DISP_AHB_CLK>, 2192 <&gcc GCC_DISP_AXI_CLK>, 2193 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2194 clock-names = "iface", 2195 "bus", 2196 "core"; 2197 2198 power-domains = <&dispcc MDSS_GDSC>; 2199 iommus = <&apps_smmu 0x800 0x2>; 2200 2201 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2202 2203 #address-cells = <2>; 2204 #size-cells = <2>; 2205 ranges; 2206 2207 status = "disabled"; 2208 2209 mdss_mdp: display-controller@ae01000 { 2210 compatible = "qcom,sm6350-dpu"; 2211 reg = <0x0 0x0ae01000 0x0 0x8f000>, 2212 <0x0 0x0aeb0000 0x0 0x2008>; 2213 reg-names = "mdp", "vbif"; 2214 2215 interrupt-parent = <&mdss>; 2216 interrupts = <0>; 2217 2218 clocks = <&gcc GCC_DISP_AXI_CLK>, 2219 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2220 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2221 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2222 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2223 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2224 clock-names = "bus", 2225 "iface", 2226 "rot", 2227 "lut", 2228 "core", 2229 "vsync"; 2230 2231 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2232 assigned-clock-rates = <19200000>; 2233 2234 operating-points-v2 = <&mdp_opp_table>; 2235 power-domains = <&rpmhpd SM6350_CX>; 2236 2237 ports { 2238 #address-cells = <1>; 2239 #size-cells = <0>; 2240 2241 port@0 { 2242 reg = <0>; 2243 2244 dpu_intf1_out: endpoint { 2245 remote-endpoint = <&mdss_dsi0_in>; 2246 }; 2247 }; 2248 2249 port@2 { 2250 reg = <2>; 2251 2252 dpu_intf0_out: endpoint { 2253 remote-endpoint = <&mdss_dp_in>; 2254 }; 2255 }; 2256 }; 2257 2258 mdp_opp_table: opp-table { 2259 compatible = "operating-points-v2"; 2260 2261 opp-19200000 { 2262 opp-hz = /bits/ 64 <19200000>; 2263 required-opps = <&rpmhpd_opp_min_svs>; 2264 }; 2265 2266 opp-200000000 { 2267 opp-hz = /bits/ 64 <200000000>; 2268 required-opps = <&rpmhpd_opp_low_svs>; 2269 }; 2270 2271 opp-300000000 { 2272 opp-hz = /bits/ 64 <300000000>; 2273 required-opps = <&rpmhpd_opp_svs>; 2274 }; 2275 2276 opp-373333333 { 2277 opp-hz = /bits/ 64 <373333333>; 2278 required-opps = <&rpmhpd_opp_svs_l1>; 2279 }; 2280 2281 opp-448000000 { 2282 opp-hz = /bits/ 64 <448000000>; 2283 required-opps = <&rpmhpd_opp_nom>; 2284 }; 2285 2286 opp-560000000 { 2287 opp-hz = /bits/ 64 <560000000>; 2288 required-opps = <&rpmhpd_opp_turbo>; 2289 }; 2290 }; 2291 }; 2292 2293 mdss_dp: displayport-controller@ae90000 { 2294 compatible = "qcom,sm6350-dp", "qcom,sc7180-dp"; 2295 reg = <0x0 0xae90000 0x0 0x200>, 2296 <0x0 0xae90200 0x0 0x200>, 2297 <0x0 0xae90400 0x0 0x600>, 2298 <0x0 0xae91000 0x0 0x400>, 2299 <0x0 0xae91400 0x0 0x400>; 2300 interrupt-parent = <&mdss>; 2301 interrupts = <12>; 2302 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2303 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 2304 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 2305 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 2306 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 2307 clock-names = "core_iface", 2308 "core_aux", 2309 "ctrl_link", 2310 "ctrl_link_iface", 2311 "stream_pixel"; 2312 2313 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 2314 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 2315 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2316 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2317 2318 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 2319 phy-names = "dp"; 2320 2321 #sound-dai-cells = <0>; 2322 2323 operating-points-v2 = <&dp_opp_table>; 2324 power-domains = <&rpmhpd SM6350_CX>; 2325 2326 status = "disabled"; 2327 2328 ports { 2329 #address-cells = <1>; 2330 #size-cells = <0>; 2331 2332 port@0 { 2333 reg = <0>; 2334 2335 mdss_dp_in: endpoint { 2336 remote-endpoint = <&dpu_intf0_out>; 2337 }; 2338 }; 2339 2340 port@1 { 2341 reg = <1>; 2342 2343 mdss_dp_out: endpoint { 2344 }; 2345 }; 2346 }; 2347 2348 dp_opp_table: opp-table { 2349 compatible = "operating-points-v2"; 2350 2351 opp-162000000 { 2352 opp-hz = /bits/ 64 <162000000>; 2353 required-opps = <&rpmhpd_opp_low_svs>; 2354 }; 2355 2356 opp-270000000 { 2357 opp-hz = /bits/ 64 <270000000>; 2358 required-opps = <&rpmhpd_opp_svs>; 2359 }; 2360 2361 opp-540000000 { 2362 opp-hz = /bits/ 64 <540000000>; 2363 required-opps = <&rpmhpd_opp_svs_l1>; 2364 }; 2365 2366 opp-810000000 { 2367 opp-hz = /bits/ 64 <810000000>; 2368 required-opps = <&rpmhpd_opp_nom>; 2369 }; 2370 }; 2371 }; 2372 2373 mdss_dsi0: dsi@ae94000 { 2374 compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2375 reg = <0x0 0x0ae94000 0x0 0x400>; 2376 reg-names = "dsi_ctrl"; 2377 2378 interrupt-parent = <&mdss>; 2379 interrupts = <4>; 2380 2381 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2382 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2383 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2384 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2385 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2386 <&gcc GCC_DISP_AXI_CLK>; 2387 clock-names = "byte", 2388 "byte_intf", 2389 "pixel", 2390 "core", 2391 "iface", 2392 "bus"; 2393 2394 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2395 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2396 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2397 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 2398 2399 operating-points-v2 = <&mdss_dsi_opp_table>; 2400 power-domains = <&rpmhpd SM6350_MX>; 2401 2402 phys = <&mdss_dsi0_phy>; 2403 phy-names = "dsi"; 2404 2405 refgen-supply = <&refgen>; 2406 2407 #address-cells = <1>; 2408 #size-cells = <0>; 2409 2410 status = "disabled"; 2411 2412 ports { 2413 #address-cells = <1>; 2414 #size-cells = <0>; 2415 2416 port@0 { 2417 reg = <0>; 2418 2419 mdss_dsi0_in: endpoint { 2420 remote-endpoint = <&dpu_intf1_out>; 2421 }; 2422 }; 2423 2424 port@1 { 2425 reg = <1>; 2426 2427 mdss_dsi0_out: endpoint { 2428 }; 2429 }; 2430 }; 2431 2432 mdss_dsi_opp_table: opp-table { 2433 compatible = "operating-points-v2"; 2434 2435 opp-187500000 { 2436 opp-hz = /bits/ 64 <187500000>; 2437 required-opps = <&rpmhpd_opp_low_svs>; 2438 }; 2439 2440 opp-300000000 { 2441 opp-hz = /bits/ 64 <300000000>; 2442 required-opps = <&rpmhpd_opp_svs>; 2443 }; 2444 2445 opp-358000000 { 2446 opp-hz = /bits/ 64 <358000000>; 2447 required-opps = <&rpmhpd_opp_svs_l1>; 2448 }; 2449 }; 2450 }; 2451 2452 mdss_dsi0_phy: phy@ae94400 { 2453 compatible = "qcom,dsi-phy-10nm"; 2454 reg = <0x0 0x0ae94400 0x0 0x200>, 2455 <0x0 0x0ae94600 0x0 0x280>, 2456 <0x0 0x0ae94a00 0x0 0x1e0>; 2457 reg-names = "dsi_phy", 2458 "dsi_phy_lane", 2459 "dsi_pll"; 2460 2461 #clock-cells = <1>; 2462 #phy-cells = <0>; 2463 2464 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2465 <&rpmhcc RPMH_CXO_CLK>; 2466 clock-names = "iface", "ref"; 2467 2468 status = "disabled"; 2469 }; 2470 }; 2471 2472 dispcc: clock-controller@af00000 { 2473 compatible = "qcom,sm6350-dispcc"; 2474 reg = <0x0 0x0af00000 0x0 0x20000>; 2475 clocks = <&rpmhcc RPMH_CXO_CLK>, 2476 <&gcc GCC_DISP_GPLL0_CLK>, 2477 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2478 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 2479 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2480 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2481 clock-names = "bi_tcxo", 2482 "gcc_disp_gpll0_clk", 2483 "dsi0_phy_pll_out_byteclk", 2484 "dsi0_phy_pll_out_dsiclk", 2485 "dp_phy_pll_link_clk", 2486 "dp_phy_pll_vco_div_clk"; 2487 #clock-cells = <1>; 2488 #reset-cells = <1>; 2489 #power-domain-cells = <1>; 2490 }; 2491 2492 pdc: interrupt-controller@b220000 { 2493 compatible = "qcom,sm6350-pdc", "qcom,pdc"; 2494 reg = <0x0 0x0b220000 0x0 0x30000>, <0x0 0x17c000f0 0x0 0x64>; 2495 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 2496 <125 63 1>, <126 655 12>, <138 139 15>; 2497 #interrupt-cells = <2>; 2498 interrupt-parent = <&intc>; 2499 interrupt-controller; 2500 }; 2501 2502 tsens0: thermal-sensor@c263000 { 2503 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 2504 reg = <0x0 0x0c263000 0x0 0x1ff>, /* TM */ 2505 <0x0 0x0c222000 0x0 0x8>; /* SROT */ 2506 #qcom,sensors = <16>; 2507 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 2508 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 2509 interrupt-names = "uplow", "critical"; 2510 #thermal-sensor-cells = <1>; 2511 }; 2512 2513 tsens1: thermal-sensor@c265000 { 2514 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 2515 reg = <0x0 0x0c265000 0x0 0x1ff>, /* TM */ 2516 <0x0 0x0c223000 0x0 0x8>; /* SROT */ 2517 #qcom,sensors = <16>; 2518 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 2519 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 2520 interrupt-names = "uplow", "critical"; 2521 #thermal-sensor-cells = <1>; 2522 }; 2523 2524 aoss_qmp: power-management@c300000 { 2525 compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp"; 2526 reg = <0x0 0x0c300000 0x0 0x1000>; 2527 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2528 IRQ_TYPE_EDGE_RISING>; 2529 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2530 2531 #clock-cells = <0>; 2532 }; 2533 2534 sram@c3f0000 { 2535 compatible = "qcom,rpmh-stats"; 2536 reg = <0x0 0x0c3f0000 0x0 0x400>; 2537 }; 2538 2539 spmi_bus: spmi@c440000 { 2540 compatible = "qcom,spmi-pmic-arb"; 2541 reg = <0x0 0x0c440000 0x0 0x1100>, 2542 <0x0 0x0c600000 0x0 0x2000000>, 2543 <0x0 0x0e600000 0x0 0x100000>, 2544 <0x0 0x0e700000 0x0 0xa0000>, 2545 <0x0 0x0c40a000 0x0 0x26000>; 2546 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2547 interrupt-names = "periph_irq"; 2548 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2549 qcom,ee = <0>; 2550 qcom,channel = <0>; 2551 #address-cells = <2>; 2552 #size-cells = <0>; 2553 interrupt-controller; 2554 #interrupt-cells = <4>; 2555 }; 2556 2557 tlmm: pinctrl@f100000 { 2558 compatible = "qcom,sm6350-tlmm"; 2559 reg = <0x0 0x0f100000 0x0 0x300000>; 2560 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 2561 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 2562 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 2563 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 2564 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 2565 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 2566 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 2567 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 2568 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 2569 gpio-controller; 2570 #gpio-cells = <2>; 2571 interrupt-controller; 2572 #interrupt-cells = <2>; 2573 gpio-ranges = <&tlmm 0 0 157>; 2574 wakeup-parent = <&pdc>; 2575 2576 cci0_default: cci0-default-state { 2577 pins = "gpio39", "gpio40"; 2578 function = "cci_i2c"; 2579 drive-strength = <2>; 2580 bias-pull-up; 2581 }; 2582 2583 cci0_sleep: cci0-sleep-state { 2584 pins = "gpio39", "gpio40"; 2585 function = "cci_i2c"; 2586 drive-strength = <2>; 2587 bias-pull-down; 2588 }; 2589 2590 cci1_default: cci1-default-state { 2591 pins = "gpio41", "gpio42"; 2592 function = "cci_i2c"; 2593 drive-strength = <2>; 2594 bias-pull-up; 2595 }; 2596 2597 cci1_sleep: cci1-sleep-state { 2598 pins = "gpio41", "gpio42"; 2599 function = "cci_i2c"; 2600 drive-strength = <2>; 2601 bias-pull-down; 2602 }; 2603 2604 cci2_default: cci2-default-state { 2605 pins = "gpio43", "gpio44"; 2606 function = "cci_i2c"; 2607 drive-strength = <2>; 2608 bias-pull-up; 2609 }; 2610 2611 cci2_sleep: cci2-sleep-state { 2612 pins = "gpio43", "gpio44"; 2613 function = "cci_i2c"; 2614 drive-strength = <2>; 2615 bias-pull-down; 2616 }; 2617 2618 sdc2_off_state: sdc2-off-state { 2619 clk-pins { 2620 pins = "sdc2_clk"; 2621 drive-strength = <2>; 2622 bias-disable; 2623 }; 2624 2625 cmd-pins { 2626 pins = "sdc2_cmd"; 2627 drive-strength = <2>; 2628 bias-pull-up; 2629 }; 2630 2631 data-pins { 2632 pins = "sdc2_data"; 2633 drive-strength = <2>; 2634 bias-pull-up; 2635 }; 2636 }; 2637 2638 sdc2_on_state: sdc2-on-state { 2639 clk-pins { 2640 pins = "sdc2_clk"; 2641 drive-strength = <16>; 2642 bias-disable; 2643 }; 2644 2645 cmd-pins { 2646 pins = "sdc2_cmd"; 2647 drive-strength = <10>; 2648 bias-pull-up; 2649 }; 2650 2651 data-pins { 2652 pins = "sdc2_data"; 2653 drive-strength = <10>; 2654 bias-pull-up; 2655 }; 2656 }; 2657 2658 qup_uart9_default: qup-uart9-default-state { 2659 pins = "gpio25", "gpio26"; 2660 function = "qup13_f2"; 2661 drive-strength = <2>; 2662 bias-disable; 2663 }; 2664 2665 qup_i2c0_default: qup-i2c0-default-state { 2666 pins = "gpio0", "gpio1"; 2667 function = "qup00"; 2668 drive-strength = <2>; 2669 bias-pull-up; 2670 }; 2671 2672 qup_i2c2_default: qup-i2c2-default-state { 2673 pins = "gpio45", "gpio46"; 2674 function = "qup02"; 2675 drive-strength = <2>; 2676 bias-pull-up; 2677 }; 2678 2679 qup_i2c6_default: qup-i2c6-default-state { 2680 pins = "gpio13", "gpio14"; 2681 function = "qup10"; 2682 drive-strength = <2>; 2683 bias-pull-up; 2684 }; 2685 2686 qup_i2c7_default: qup-i2c7-default-state { 2687 pins = "gpio27", "gpio28"; 2688 function = "qup11"; 2689 drive-strength = <2>; 2690 bias-pull-up; 2691 }; 2692 2693 qup_i2c8_default: qup-i2c8-default-state { 2694 pins = "gpio19", "gpio20"; 2695 function = "qup12"; 2696 drive-strength = <2>; 2697 bias-pull-up; 2698 }; 2699 2700 qup_i2c10_default: qup-i2c10-default-state { 2701 pins = "gpio4", "gpio5"; 2702 function = "qup14"; 2703 drive-strength = <2>; 2704 bias-pull-up; 2705 }; 2706 2707 qup_uart1_cts: qup-uart1-cts-default-state { 2708 pins = "gpio61"; 2709 function = "qup01"; 2710 drive-strength = <2>; 2711 bias-disable; 2712 }; 2713 2714 qup_uart1_rts: qup-uart1-rts-default-state { 2715 pins = "gpio62"; 2716 function = "qup01"; 2717 drive-strength = <2>; 2718 bias-pull-down; 2719 }; 2720 2721 qup_uart1_rx: qup-uart1-rx-default-state { 2722 pins = "gpio64"; 2723 function = "qup01"; 2724 drive-strength = <2>; 2725 bias-disable; 2726 }; 2727 2728 qup_uart1_tx: qup-uart1-tx-default-state { 2729 pins = "gpio63"; 2730 function = "qup01"; 2731 drive-strength = <2>; 2732 bias-pull-up; 2733 }; 2734 }; 2735 2736 sram@14680000 { 2737 compatible = "qcom,sm6350-imem", "syscon", "simple-mfd"; 2738 reg = <0 0x14680000 0 0x2e000>; 2739 2740 #address-cells = <1>; 2741 #size-cells = <1>; 2742 2743 ranges = <0 0 0x14680000 0x2e000>; 2744 2745 ipa_modem_tables: modem-tables@28000 { 2746 reg = <0x28000 0x2000>; 2747 }; 2748 }; 2749 2750 apps_smmu: iommu@15000000 { 2751 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500"; 2752 reg = <0x0 0x15000000 0x0 0x100000>; 2753 #iommu-cells = <2>; 2754 #global-interrupts = <1>; 2755 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 2756 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 2757 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 2758 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2759 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2760 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2761 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2762 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2763 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2764 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2765 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2766 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2767 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2768 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2769 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2770 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2771 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2772 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2773 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2774 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2775 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2776 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2777 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2778 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2779 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2780 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 2781 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 2782 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 2783 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 2784 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 2785 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 2786 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 2787 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 2788 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 2789 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 2790 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 2791 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 2792 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 2793 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 2794 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 2795 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 2796 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 2797 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2798 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2799 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2800 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2801 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2802 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2803 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2804 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2805 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2806 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2807 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2808 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2809 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2810 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2811 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2812 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2813 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2814 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2815 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2816 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2817 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2818 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2819 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2820 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2821 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2822 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2823 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2824 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2825 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 2826 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2827 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 2828 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 2829 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 2830 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 2831 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 2832 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 2833 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 2834 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 2835 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 2836 dma-coherent; 2837 }; 2838 2839 intc: interrupt-controller@17a00000 { 2840 compatible = "arm,gic-v3"; 2841 #interrupt-cells = <3>; 2842 interrupt-controller; 2843 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 2844 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 2845 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; 2846 }; 2847 2848 watchdog@17c10000 { 2849 compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt"; 2850 reg = <0x0 0x17c10000 0x0 0x1000>; 2851 clocks = <&sleep_clk>; 2852 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 2853 }; 2854 2855 timer@17c20000 { 2856 compatible = "arm,armv7-timer-mem"; 2857 reg = <0x0 0x17c20000 0x0 0x1000>; 2858 clock-frequency = <19200000>; 2859 #address-cells = <1>; 2860 #size-cells = <1>; 2861 ranges = <0 0 0 0x20000000>; 2862 2863 frame@17c21000 { 2864 frame-number = <0>; 2865 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2866 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 2867 reg = <0x17c21000 0x1000>, 2868 <0x17c22000 0x1000>; 2869 }; 2870 2871 frame@17c23000 { 2872 frame-number = <1>; 2873 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2874 reg = <0x17c23000 0x1000>; 2875 status = "disabled"; 2876 }; 2877 2878 frame@17c25000 { 2879 frame-number = <2>; 2880 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2881 reg = <0x17c25000 0x1000>; 2882 status = "disabled"; 2883 }; 2884 2885 frame@17c27000 { 2886 frame-number = <3>; 2887 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2888 reg = <0x17c27000 0x1000>; 2889 status = "disabled"; 2890 }; 2891 2892 frame@17c29000 { 2893 frame-number = <4>; 2894 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2895 reg = <0x17c29000 0x1000>; 2896 status = "disabled"; 2897 }; 2898 2899 frame@17c2b000 { 2900 frame-number = <5>; 2901 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2902 reg = <0x17c2b000 0x1000>; 2903 status = "disabled"; 2904 }; 2905 2906 frame@17c2d000 { 2907 frame-number = <6>; 2908 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2909 reg = <0x17c2d000 0x1000>; 2910 status = "disabled"; 2911 }; 2912 }; 2913 2914 apps_rsc: rsc@18200000 { 2915 compatible = "qcom,rpmh-rsc"; 2916 label = "apps_rsc"; 2917 reg = <0x0 0x18200000 0x0 0x10000>, 2918 <0x0 0x18210000 0x0 0x10000>, 2919 <0x0 0x18220000 0x0 0x10000>; 2920 reg-names = "drv-0", "drv-1", "drv-2"; 2921 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2922 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2923 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 2924 qcom,tcs-offset = <0xd00>; 2925 qcom,drv-id = <2>; 2926 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 2927 <WAKE_TCS 3>, <CONTROL_TCS 1>; 2928 power-domains = <&cluster_pd>; 2929 2930 rpmhcc: clock-controller { 2931 compatible = "qcom,sm6350-rpmh-clk"; 2932 #clock-cells = <1>; 2933 clock-names = "xo"; 2934 clocks = <&xo_board>; 2935 }; 2936 2937 rpmhpd: power-controller { 2938 compatible = "qcom,sm6350-rpmhpd"; 2939 #power-domain-cells = <1>; 2940 operating-points-v2 = <&rpmhpd_opp_table>; 2941 2942 rpmhpd_opp_table: opp-table { 2943 compatible = "operating-points-v2"; 2944 2945 rpmhpd_opp_ret: opp1 { 2946 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 2947 }; 2948 2949 rpmhpd_opp_min_svs: opp2 { 2950 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2951 }; 2952 2953 rpmhpd_opp_low_svs: opp3 { 2954 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2955 }; 2956 2957 rpmhpd_opp_svs: opp4 { 2958 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2959 }; 2960 2961 rpmhpd_opp_svs_l1: opp5 { 2962 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2963 }; 2964 2965 rpmhpd_opp_nom: opp6 { 2966 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2967 }; 2968 2969 rpmhpd_opp_nom_l1: opp7 { 2970 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2971 }; 2972 2973 rpmhpd_opp_nom_l2: opp8 { 2974 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 2975 }; 2976 2977 rpmhpd_opp_turbo: opp9 { 2978 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2979 }; 2980 2981 rpmhpd_opp_turbo_l1: opp10 { 2982 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2983 }; 2984 }; 2985 }; 2986 2987 apps_bcm_voter: bcm-voter { 2988 compatible = "qcom,bcm-voter"; 2989 }; 2990 }; 2991 2992 osm_l3: interconnect@18321000 { 2993 compatible = "qcom,sm6350-osm-l3", "qcom,osm-l3"; 2994 reg = <0x0 0x18321000 0x0 0x1000>; 2995 2996 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2997 clock-names = "xo", "alternate"; 2998 2999 #interconnect-cells = <1>; 3000 }; 3001 3002 cpufreq_hw: cpufreq@18323000 { 3003 compatible = "qcom,sm6350-cpufreq-hw", "qcom,cpufreq-hw"; 3004 reg = <0x0 0x18323000 0x0 0x1000>, <0x0 0x18325800 0x0 0x1000>; 3005 reg-names = "freq-domain0", "freq-domain1"; 3006 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3007 clock-names = "xo", "alternate"; 3008 3009 #freq-domain-cells = <1>; 3010 #clock-cells = <1>; 3011 }; 3012 3013 wifi: wifi@18800000 { 3014 compatible = "qcom,wcn3990-wifi"; 3015 reg = <0x0 0x18800000 0x0 0x800000>; 3016 reg-names = "membase"; 3017 memory-region = <&wlan_fw_mem>; 3018 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 3019 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 3020 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 3021 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 3022 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3023 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3024 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 3025 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3026 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3027 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3028 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3029 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 3030 iommus = <&apps_smmu 0x20 0x1>; 3031 qcom,msa-fixed-perm; 3032 status = "disabled"; 3033 }; 3034 }; 3035 3036 sound: sound { 3037 }; 3038 3039 thermal-zones { 3040 aoss0-thermal { 3041 thermal-sensors = <&tsens0 0>; 3042 3043 trips { 3044 aoss0-crit { 3045 temperature = <125000>; 3046 hysteresis = <0>; 3047 type = "critical"; 3048 }; 3049 }; 3050 }; 3051 3052 aoss1-thermal { 3053 thermal-sensors = <&tsens1 0>; 3054 3055 trips { 3056 aoss1-crit { 3057 temperature = <125000>; 3058 hysteresis = <0>; 3059 type = "critical"; 3060 }; 3061 }; 3062 }; 3063 3064 audio-thermal { 3065 thermal-sensors = <&tsens1 2>; 3066 3067 trips { 3068 audio-crit { 3069 temperature = <125000>; 3070 hysteresis = <0>; 3071 type = "critical"; 3072 }; 3073 }; 3074 }; 3075 3076 camera-thermal { 3077 thermal-sensors = <&tsens1 5>; 3078 3079 trips { 3080 camera-crit { 3081 temperature = <125000>; 3082 hysteresis = <0>; 3083 type = "critical"; 3084 }; 3085 }; 3086 }; 3087 3088 cpu0-thermal { 3089 thermal-sensors = <&tsens0 1>; 3090 3091 trips { 3092 cpu0_alert0: trip-point0 { 3093 temperature = <95000>; 3094 hysteresis = <2000>; 3095 type = "passive"; 3096 }; 3097 3098 cpu0-crit { 3099 temperature = <115000>; 3100 hysteresis = <0>; 3101 type = "critical"; 3102 }; 3103 }; 3104 3105 cooling-maps { 3106 map0 { 3107 trip = <&cpu0_alert0>; 3108 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3109 }; 3110 }; 3111 }; 3112 3113 cpu1-thermal { 3114 thermal-sensors = <&tsens0 2>; 3115 3116 trips { 3117 cpu1_alert0: trip-point0 { 3118 temperature = <95000>; 3119 hysteresis = <2000>; 3120 type = "passive"; 3121 }; 3122 3123 cpu1-crit { 3124 temperature = <115000>; 3125 hysteresis = <0>; 3126 type = "critical"; 3127 }; 3128 }; 3129 3130 cooling-maps { 3131 map0 { 3132 trip = <&cpu1_alert0>; 3133 cooling-device = <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3134 }; 3135 }; 3136 }; 3137 3138 cpu2-thermal { 3139 thermal-sensors = <&tsens0 3>; 3140 3141 trips { 3142 cpu2_alert0: trip-point0 { 3143 temperature = <95000>; 3144 hysteresis = <2000>; 3145 type = "passive"; 3146 }; 3147 3148 cpu2-crit { 3149 temperature = <115000>; 3150 hysteresis = <0>; 3151 type = "critical"; 3152 }; 3153 }; 3154 3155 cooling-maps { 3156 map0 { 3157 trip = <&cpu2_alert0>; 3158 cooling-device = <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3159 }; 3160 }; 3161 }; 3162 3163 cpu3-thermal { 3164 thermal-sensors = <&tsens0 4>; 3165 3166 trips { 3167 cpu3_alert0: trip-point0 { 3168 temperature = <95000>; 3169 hysteresis = <2000>; 3170 type = "passive"; 3171 }; 3172 3173 cpu3-crit { 3174 temperature = <115000>; 3175 hysteresis = <0>; 3176 type = "critical"; 3177 }; 3178 }; 3179 3180 cooling-maps { 3181 map0 { 3182 trip = <&cpu3_alert0>; 3183 cooling-device = <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3184 }; 3185 }; 3186 }; 3187 3188 cpu4-thermal { 3189 thermal-sensors = <&tsens0 5>; 3190 3191 trips { 3192 cpu4_alert0: trip-point0 { 3193 temperature = <95000>; 3194 hysteresis = <2000>; 3195 type = "passive"; 3196 }; 3197 3198 cpu4-crit { 3199 temperature = <115000>; 3200 hysteresis = <0>; 3201 type = "critical"; 3202 }; 3203 }; 3204 3205 cooling-maps { 3206 map0 { 3207 trip = <&cpu4_alert0>; 3208 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3209 }; 3210 }; 3211 }; 3212 3213 cpu5-thermal { 3214 thermal-sensors = <&tsens0 6>; 3215 3216 trips { 3217 cpu5_alert0: trip-point0 { 3218 temperature = <95000>; 3219 hysteresis = <2000>; 3220 type = "passive"; 3221 }; 3222 3223 cpu5-crit { 3224 temperature = <115000>; 3225 hysteresis = <0>; 3226 type = "critical"; 3227 }; 3228 }; 3229 3230 cooling-maps { 3231 map0 { 3232 trip = <&cpu5_alert0>; 3233 cooling-device = <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3234 }; 3235 }; 3236 }; 3237 3238 cpu6-left-thermal { 3239 thermal-sensors = <&tsens0 9>; 3240 3241 trips { 3242 cpu6_left_alert0: trip-point0 { 3243 temperature = <95000>; 3244 hysteresis = <2000>; 3245 type = "passive"; 3246 }; 3247 3248 cpu6-left-crit { 3249 temperature = <115000>; 3250 hysteresis = <0>; 3251 type = "critical"; 3252 }; 3253 }; 3254 3255 cooling-maps { 3256 map0 { 3257 trip = <&cpu6_left_alert0>; 3258 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3259 }; 3260 }; 3261 }; 3262 3263 cpu6-right-thermal { 3264 thermal-sensors = <&tsens0 10>; 3265 3266 trips { 3267 cpu6_right_alert0: trip-point0 { 3268 temperature = <95000>; 3269 hysteresis = <2000>; 3270 type = "passive"; 3271 }; 3272 3273 cpu6-right-crit { 3274 temperature = <115000>; 3275 hysteresis = <0>; 3276 type = "critical"; 3277 }; 3278 }; 3279 3280 cooling-maps { 3281 map0 { 3282 trip = <&cpu6_right_alert0>; 3283 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3284 }; 3285 }; 3286 }; 3287 3288 cpu7-left-thermal { 3289 thermal-sensors = <&tsens0 11>; 3290 3291 trips { 3292 cpu7_left_alert0: trip-point0 { 3293 temperature = <95000>; 3294 hysteresis = <2000>; 3295 type = "passive"; 3296 }; 3297 3298 cpu7-left-crit { 3299 temperature = <115000>; 3300 hysteresis = <0>; 3301 type = "critical"; 3302 }; 3303 }; 3304 3305 cooling-maps { 3306 map0 { 3307 trip = <&cpu7_left_alert0>; 3308 cooling-device = <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3309 }; 3310 }; 3311 }; 3312 3313 cpu7-right-thermal { 3314 thermal-sensors = <&tsens0 12>; 3315 3316 trips { 3317 cpu7_right_alert0: trip-point0 { 3318 temperature = <95000>; 3319 hysteresis = <2000>; 3320 type = "passive"; 3321 }; 3322 3323 cpu7-right-crit { 3324 temperature = <115000>; 3325 hysteresis = <0>; 3326 type = "critical"; 3327 }; 3328 }; 3329 3330 cooling-maps { 3331 map0 { 3332 trip = <&cpu7_right_alert0>; 3333 cooling-device = <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3334 }; 3335 }; 3336 }; 3337 3338 cpuss0-thermal { 3339 thermal-sensors = <&tsens0 7>; 3340 3341 trips { 3342 cpuss0-crit { 3343 temperature = <125000>; 3344 hysteresis = <0>; 3345 type = "critical"; 3346 }; 3347 }; 3348 }; 3349 3350 cpuss1-thermal { 3351 thermal-sensors = <&tsens0 8>; 3352 3353 trips { 3354 cpuss1-crit { 3355 temperature = <125000>; 3356 hysteresis = <0>; 3357 type = "critical"; 3358 }; 3359 }; 3360 }; 3361 3362 cwlan-thermal { 3363 thermal-sensors = <&tsens1 1>; 3364 3365 trips { 3366 cwlan-crit { 3367 temperature = <125000>; 3368 hysteresis = <0>; 3369 type = "critical"; 3370 }; 3371 }; 3372 }; 3373 3374 ddr-thermal { 3375 thermal-sensors = <&tsens1 3>; 3376 3377 trips { 3378 ddr-crit { 3379 temperature = <125000>; 3380 hysteresis = <0>; 3381 type = "critical"; 3382 }; 3383 }; 3384 }; 3385 3386 gpuss0-thermal { 3387 polling-delay-passive = <250>; 3388 3389 thermal-sensors = <&tsens0 13>; 3390 3391 trips { 3392 gpuss0_alert0: trip-point0 { 3393 temperature = <85000>; 3394 hysteresis = <2000>; 3395 type = "passive"; 3396 }; 3397 3398 gpuss0-crit { 3399 temperature = <110000>; 3400 hysteresis = <1000>; 3401 type = "critical"; 3402 }; 3403 }; 3404 3405 cooling-maps { 3406 map0 { 3407 trip = <&gpuss0_alert0>; 3408 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3409 }; 3410 }; 3411 }; 3412 3413 gpuss1-thermal { 3414 polling-delay-passive = <250>; 3415 3416 thermal-sensors = <&tsens0 14>; 3417 3418 trips { 3419 gpuss1_alert0: trip-point0 { 3420 temperature = <85000>; 3421 hysteresis = <2000>; 3422 type = "passive"; 3423 }; 3424 3425 gpuss1-crit { 3426 temperature = <110000>; 3427 hysteresis = <1000>; 3428 type = "critical"; 3429 }; 3430 }; 3431 3432 cooling-maps { 3433 map0 { 3434 trip = <&gpuss1_alert0>; 3435 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3436 }; 3437 }; 3438 }; 3439 3440 modem-core0-thermal { 3441 thermal-sensors = <&tsens1 6>; 3442 3443 trips { 3444 modem-core0-crit { 3445 temperature = <125000>; 3446 hysteresis = <0>; 3447 type = "critical"; 3448 }; 3449 }; 3450 }; 3451 3452 modem-core1-thermal { 3453 thermal-sensors = <&tsens1 7>; 3454 3455 trips { 3456 modem-core1-crit { 3457 temperature = <125000>; 3458 hysteresis = <0>; 3459 type = "critical"; 3460 }; 3461 }; 3462 }; 3463 3464 modem-scl-thermal { 3465 thermal-sensors = <&tsens1 9>; 3466 3467 trips { 3468 modem-scl-crit { 3469 temperature = <125000>; 3470 hysteresis = <0>; 3471 type = "critical"; 3472 }; 3473 }; 3474 }; 3475 3476 modem-vec-thermal { 3477 thermal-sensors = <&tsens1 8>; 3478 3479 trips { 3480 modem-vec-crit { 3481 temperature = <125000>; 3482 hysteresis = <0>; 3483 type = "critical"; 3484 }; 3485 }; 3486 }; 3487 3488 npu-thermal { 3489 thermal-sensors = <&tsens1 10>; 3490 3491 trips { 3492 npu-crit { 3493 temperature = <125000>; 3494 hysteresis = <0>; 3495 type = "critical"; 3496 }; 3497 }; 3498 }; 3499 3500 q6-hvx-thermal { 3501 thermal-sensors = <&tsens1 4>; 3502 3503 trips { 3504 q6-hvx-crit { 3505 temperature = <125000>; 3506 hysteresis = <0>; 3507 type = "critical"; 3508 }; 3509 }; 3510 }; 3511 3512 video-thermal { 3513 thermal-sensors = <&tsens1 11>; 3514 3515 trips { 3516 video-crit { 3517 temperature = <125000>; 3518 hysteresis = <0>; 3519 type = "critical"; 3520 }; 3521 }; 3522 }; 3523 }; 3524 3525 timer { 3526 compatible = "arm,armv8-timer"; 3527 clock-frequency = <19200000>; 3528 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 3529 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 3530 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 3531 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 3532 }; 3533}; 3534