1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> 4 * Copyright (c) 2022, Luca Weiss <luca.weiss@fairphone.com> 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sm6350.h> 8#include <dt-bindings/clock/qcom,gcc-sm6350.h> 9#include <dt-bindings/clock/qcom,gpucc-sm6350.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sm6350-camcc.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interconnect/qcom,icc.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,sm6350.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/mailbox/qcom-ipcc.h> 19#include <dt-bindings/phy/phy-qcom-qmp.h> 20#include <dt-bindings/power/qcom-rpmpd.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/thermal/thermal.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 clocks { 30 xo_board: xo-board { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <76800000>; 34 clock-output-names = "xo_board"; 35 }; 36 37 sleep_clk: sleep-clk { 38 compatible = "fixed-clock"; 39 clock-frequency = <32764>; 40 #clock-cells = <0>; 41 }; 42 }; 43 44 cpus { 45 #address-cells = <2>; 46 #size-cells = <0>; 47 48 CPU0: cpu@0 { 49 device_type = "cpu"; 50 compatible = "qcom,kryo560"; 51 reg = <0x0 0x0>; 52 clocks = <&cpufreq_hw 0>; 53 enable-method = "psci"; 54 capacity-dmips-mhz = <1024>; 55 dynamic-power-coefficient = <100>; 56 next-level-cache = <&L2_0>; 57 qcom,freq-domain = <&cpufreq_hw 0>; 58 operating-points-v2 = <&cpu0_opp_table>; 59 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 60 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 61 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 62 power-domains = <&CPU_PD0>; 63 power-domain-names = "psci"; 64 #cooling-cells = <2>; 65 L2_0: l2-cache { 66 compatible = "cache"; 67 cache-level = <2>; 68 cache-unified; 69 next-level-cache = <&L3_0>; 70 L3_0: l3-cache { 71 compatible = "cache"; 72 cache-level = <3>; 73 cache-unified; 74 }; 75 }; 76 }; 77 78 CPU1: cpu@100 { 79 device_type = "cpu"; 80 compatible = "qcom,kryo560"; 81 reg = <0x0 0x100>; 82 clocks = <&cpufreq_hw 0>; 83 enable-method = "psci"; 84 capacity-dmips-mhz = <1024>; 85 dynamic-power-coefficient = <100>; 86 next-level-cache = <&L2_100>; 87 qcom,freq-domain = <&cpufreq_hw 0>; 88 operating-points-v2 = <&cpu0_opp_table>; 89 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 90 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 91 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 92 power-domains = <&CPU_PD1>; 93 power-domain-names = "psci"; 94 #cooling-cells = <2>; 95 L2_100: l2-cache { 96 compatible = "cache"; 97 cache-level = <2>; 98 cache-unified; 99 next-level-cache = <&L3_0>; 100 }; 101 }; 102 103 CPU2: cpu@200 { 104 device_type = "cpu"; 105 compatible = "qcom,kryo560"; 106 reg = <0x0 0x200>; 107 clocks = <&cpufreq_hw 0>; 108 enable-method = "psci"; 109 capacity-dmips-mhz = <1024>; 110 dynamic-power-coefficient = <100>; 111 next-level-cache = <&L2_200>; 112 qcom,freq-domain = <&cpufreq_hw 0>; 113 operating-points-v2 = <&cpu0_opp_table>; 114 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 115 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 116 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 117 power-domains = <&CPU_PD2>; 118 power-domain-names = "psci"; 119 #cooling-cells = <2>; 120 L2_200: l2-cache { 121 compatible = "cache"; 122 cache-level = <2>; 123 cache-unified; 124 next-level-cache = <&L3_0>; 125 }; 126 }; 127 128 CPU3: cpu@300 { 129 device_type = "cpu"; 130 compatible = "qcom,kryo560"; 131 reg = <0x0 0x300>; 132 clocks = <&cpufreq_hw 0>; 133 enable-method = "psci"; 134 capacity-dmips-mhz = <1024>; 135 dynamic-power-coefficient = <100>; 136 next-level-cache = <&L2_300>; 137 qcom,freq-domain = <&cpufreq_hw 0>; 138 operating-points-v2 = <&cpu0_opp_table>; 139 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 140 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 141 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 142 power-domains = <&CPU_PD3>; 143 power-domain-names = "psci"; 144 #cooling-cells = <2>; 145 L2_300: l2-cache { 146 compatible = "cache"; 147 cache-level = <2>; 148 cache-unified; 149 next-level-cache = <&L3_0>; 150 }; 151 }; 152 153 CPU4: cpu@400 { 154 device_type = "cpu"; 155 compatible = "qcom,kryo560"; 156 reg = <0x0 0x400>; 157 clocks = <&cpufreq_hw 0>; 158 enable-method = "psci"; 159 capacity-dmips-mhz = <1024>; 160 dynamic-power-coefficient = <100>; 161 next-level-cache = <&L2_400>; 162 qcom,freq-domain = <&cpufreq_hw 0>; 163 operating-points-v2 = <&cpu0_opp_table>; 164 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 165 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 166 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 167 power-domains = <&CPU_PD4>; 168 power-domain-names = "psci"; 169 #cooling-cells = <2>; 170 L2_400: l2-cache { 171 compatible = "cache"; 172 cache-level = <2>; 173 cache-unified; 174 next-level-cache = <&L3_0>; 175 }; 176 }; 177 178 CPU5: cpu@500 { 179 device_type = "cpu"; 180 compatible = "qcom,kryo560"; 181 reg = <0x0 0x500>; 182 clocks = <&cpufreq_hw 0>; 183 enable-method = "psci"; 184 capacity-dmips-mhz = <1024>; 185 dynamic-power-coefficient = <100>; 186 next-level-cache = <&L2_500>; 187 qcom,freq-domain = <&cpufreq_hw 0>; 188 operating-points-v2 = <&cpu0_opp_table>; 189 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 190 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 191 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 192 power-domains = <&CPU_PD5>; 193 power-domain-names = "psci"; 194 #cooling-cells = <2>; 195 L2_500: l2-cache { 196 compatible = "cache"; 197 cache-level = <2>; 198 cache-unified; 199 next-level-cache = <&L3_0>; 200 }; 201 }; 202 203 CPU6: cpu@600 { 204 device_type = "cpu"; 205 compatible = "qcom,kryo560"; 206 reg = <0x0 0x600>; 207 clocks = <&cpufreq_hw 1>; 208 enable-method = "psci"; 209 capacity-dmips-mhz = <1894>; 210 dynamic-power-coefficient = <703>; 211 next-level-cache = <&L2_600>; 212 qcom,freq-domain = <&cpufreq_hw 1>; 213 operating-points-v2 = <&cpu6_opp_table>; 214 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 215 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 216 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 217 power-domains = <&CPU_PD6>; 218 power-domain-names = "psci"; 219 #cooling-cells = <2>; 220 L2_600: l2-cache { 221 compatible = "cache"; 222 cache-level = <2>; 223 cache-unified; 224 next-level-cache = <&L3_0>; 225 }; 226 }; 227 228 CPU7: cpu@700 { 229 device_type = "cpu"; 230 compatible = "qcom,kryo560"; 231 reg = <0x0 0x700>; 232 clocks = <&cpufreq_hw 1>; 233 enable-method = "psci"; 234 capacity-dmips-mhz = <1894>; 235 dynamic-power-coefficient = <703>; 236 next-level-cache = <&L2_700>; 237 qcom,freq-domain = <&cpufreq_hw 1>; 238 operating-points-v2 = <&cpu6_opp_table>; 239 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 240 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 241 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 242 power-domains = <&CPU_PD7>; 243 power-domain-names = "psci"; 244 #cooling-cells = <2>; 245 L2_700: l2-cache { 246 compatible = "cache"; 247 cache-level = <2>; 248 cache-unified; 249 next-level-cache = <&L3_0>; 250 }; 251 }; 252 253 cpu-map { 254 cluster0 { 255 core0 { 256 cpu = <&CPU0>; 257 }; 258 259 core1 { 260 cpu = <&CPU1>; 261 }; 262 263 core2 { 264 cpu = <&CPU2>; 265 }; 266 267 core3 { 268 cpu = <&CPU3>; 269 }; 270 271 core4 { 272 cpu = <&CPU4>; 273 }; 274 275 core5 { 276 cpu = <&CPU5>; 277 }; 278 279 core6 { 280 cpu = <&CPU6>; 281 }; 282 283 core7 { 284 cpu = <&CPU7>; 285 }; 286 }; 287 }; 288 289 domain-idle-states { 290 CLUSTER_SLEEP_PC: cluster-sleep-0 { 291 compatible = "domain-idle-state"; 292 arm,psci-suspend-param = <0x41000044>; 293 entry-latency-us = <2752>; 294 exit-latency-us = <3048>; 295 min-residency-us = <6118>; 296 }; 297 298 CLUSTER_SLEEP_CX_RET: cluster-sleep-1 { 299 compatible = "domain-idle-state"; 300 arm,psci-suspend-param = <0x41001244>; 301 entry-latency-us = <3638>; 302 exit-latency-us = <4562>; 303 min-residency-us = <8467>; 304 }; 305 306 CLUSTER_AOSS_SLEEP: cluster-sleep-2 { 307 compatible = "domain-idle-state"; 308 arm,psci-suspend-param = <0x4100b244>; 309 entry-latency-us = <3263>; 310 exit-latency-us = <6562>; 311 min-residency-us = <9987>; 312 }; 313 }; 314 315 cpu_idle_states: idle-states { 316 entry-method = "psci"; 317 318 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 319 compatible = "arm,idle-state"; 320 idle-state-name = "little-power-collapse"; 321 arm,psci-suspend-param = <0x40000003>; 322 entry-latency-us = <549>; 323 exit-latency-us = <901>; 324 min-residency-us = <1774>; 325 local-timer-stop; 326 }; 327 328 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 329 compatible = "arm,idle-state"; 330 idle-state-name = "little-rail-power-collapse"; 331 arm,psci-suspend-param = <0x40000004>; 332 entry-latency-us = <702>; 333 exit-latency-us = <915>; 334 min-residency-us = <4001>; 335 local-timer-stop; 336 }; 337 338 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 339 compatible = "arm,idle-state"; 340 idle-state-name = "big-power-collapse"; 341 arm,psci-suspend-param = <0x40000003>; 342 entry-latency-us = <523>; 343 exit-latency-us = <1244>; 344 min-residency-us = <2207>; 345 local-timer-stop; 346 }; 347 348 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 349 compatible = "arm,idle-state"; 350 idle-state-name = "big-rail-power-collapse"; 351 arm,psci-suspend-param = <0x40000004>; 352 entry-latency-us = <526>; 353 exit-latency-us = <1854>; 354 min-residency-us = <5555>; 355 local-timer-stop; 356 }; 357 }; 358 }; 359 360 firmware { 361 scm: scm { 362 compatible = "qcom,scm-sm6350", "qcom,scm"; 363 #reset-cells = <1>; 364 }; 365 }; 366 367 memory@80000000 { 368 device_type = "memory"; 369 /* We expect the bootloader to fill in the size */ 370 reg = <0x0 0x80000000 0x0 0x0>; 371 }; 372 373 cpu0_opp_table: opp-table-cpu0 { 374 compatible = "operating-points-v2"; 375 opp-shared; 376 377 opp-300000000 { 378 opp-hz = /bits/ 64 <300000000>; 379 /* DDR: 4-wide, 2 channels, double data rate, L3: 16-wide, 2 channels */ 380 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; 381 }; 382 383 opp-576000000 { 384 opp-hz = /bits/ 64 <576000000>; 385 opp-peak-kBps = <(547000 * 4 * 2 * 2) (556800 * 16 * 2)>; 386 }; 387 388 opp-768000000 { 389 opp-hz = /bits/ 64 <768000000>; 390 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; 391 }; 392 393 opp-1017600000 { 394 opp-hz = /bits/ 64 <1017600000>; 395 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; 396 }; 397 398 opp-1248000000 { 399 opp-hz = /bits/ 64 <1248000000>; 400 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; 401 }; 402 403 opp-1324800000 { 404 opp-hz = /bits/ 64 <1324800000>; 405 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1286400 * 16 * 2)>; 406 }; 407 408 opp-1516800000 { 409 opp-hz = /bits/ 64 <1516800000>; 410 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 411 }; 412 413 opp-1612800000 { 414 opp-hz = /bits/ 64 <1612800000>; 415 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 416 }; 417 418 opp-1708800000 { 419 opp-hz = /bits/ 64 <1708800000>; 420 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 421 }; 422 }; 423 424 cpu6_opp_table: opp-table-cpu6 { 425 compatible = "operating-points-v2"; 426 opp-shared; 427 428 opp-300000000 { 429 opp-hz = /bits/ 64 <300000000>; 430 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; 431 }; 432 433 opp-787200000 { 434 opp-hz = /bits/ 64 <787200000>; 435 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; 436 }; 437 438 opp-979200000 { 439 opp-hz = /bits/ 64 <979200000>; 440 opp-peak-kBps = <(768000 * 4 * 2 * 2) (940800 * 16 * 2)>; 441 }; 442 443 opp-1036800000 { 444 opp-hz = /bits/ 64 <1036800000>; 445 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; 446 }; 447 448 opp-1248000000 { 449 opp-hz = /bits/ 64 <1248000000>; 450 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; 451 }; 452 453 opp-1401600000 { 454 opp-hz = /bits/ 64 <1401600000>; 455 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1401600 * 16 * 2)>; 456 }; 457 458 opp-1555200000 { 459 opp-hz = /bits/ 64 <1555200000>; 460 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 461 }; 462 463 opp-1766400000 { 464 opp-hz = /bits/ 64 <1766400000>; 465 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 466 }; 467 468 opp-1900800000 { 469 opp-hz = /bits/ 64 <1900800000>; 470 opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 471 }; 472 473 opp-2073600000 { 474 opp-hz = /bits/ 64 <2073600000>; 475 opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 476 }; 477 }; 478 479 qup_opp_table: opp-table-qup { 480 compatible = "operating-points-v2"; 481 482 opp-75000000 { 483 opp-hz = /bits/ 64 <75000000>; 484 required-opps = <&rpmhpd_opp_low_svs>; 485 }; 486 487 opp-100000000 { 488 opp-hz = /bits/ 64 <100000000>; 489 required-opps = <&rpmhpd_opp_svs>; 490 }; 491 492 opp-128000000 { 493 opp-hz = /bits/ 64 <128000000>; 494 required-opps = <&rpmhpd_opp_nom>; 495 }; 496 }; 497 498 pmu { 499 compatible = "arm,armv8-pmuv3"; 500 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>; 501 }; 502 503 psci { 504 compatible = "arm,psci-1.0"; 505 method = "smc"; 506 507 CPU_PD0: power-domain-cpu0 { 508 #power-domain-cells = <0>; 509 power-domains = <&CLUSTER_PD>; 510 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 511 }; 512 513 CPU_PD1: power-domain-cpu1 { 514 #power-domain-cells = <0>; 515 power-domains = <&CLUSTER_PD>; 516 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 517 }; 518 519 CPU_PD2: power-domain-cpu2 { 520 #power-domain-cells = <0>; 521 power-domains = <&CLUSTER_PD>; 522 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 523 }; 524 525 CPU_PD3: power-domain-cpu3 { 526 #power-domain-cells = <0>; 527 power-domains = <&CLUSTER_PD>; 528 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 529 }; 530 531 CPU_PD4: power-domain-cpu4 { 532 #power-domain-cells = <0>; 533 power-domains = <&CLUSTER_PD>; 534 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 535 }; 536 537 CPU_PD5: power-domain-cpu5 { 538 #power-domain-cells = <0>; 539 power-domains = <&CLUSTER_PD>; 540 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 541 }; 542 543 CPU_PD6: power-domain-cpu6 { 544 #power-domain-cells = <0>; 545 power-domains = <&CLUSTER_PD>; 546 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 547 }; 548 549 CPU_PD7: power-domain-cpu7 { 550 #power-domain-cells = <0>; 551 power-domains = <&CLUSTER_PD>; 552 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 553 }; 554 555 CLUSTER_PD: power-domain-cpu-cluster0 { 556 #power-domain-cells = <0>; 557 domain-idle-states = <&CLUSTER_SLEEP_PC 558 &CLUSTER_SLEEP_CX_RET 559 &CLUSTER_AOSS_SLEEP>; 560 }; 561 }; 562 563 reserved_memory: reserved-memory { 564 #address-cells = <2>; 565 #size-cells = <2>; 566 ranges; 567 568 hyp_mem: memory@80000000 { 569 reg = <0 0x80000000 0 0x600000>; 570 no-map; 571 }; 572 573 xbl_aop_mem: memory@80700000 { 574 reg = <0 0x80700000 0 0x160000>; 575 no-map; 576 }; 577 578 cmd_db: memory@80860000 { 579 compatible = "qcom,cmd-db"; 580 reg = <0 0x80860000 0 0x20000>; 581 no-map; 582 }; 583 584 sec_apps_mem: memory@808ff000 { 585 reg = <0 0x808ff000 0 0x1000>; 586 no-map; 587 }; 588 589 smem_mem: memory@80900000 { 590 reg = <0 0x80900000 0 0x200000>; 591 no-map; 592 }; 593 594 cdsp_sec_mem: memory@80b00000 { 595 reg = <0 0x80b00000 0 0x1e00000>; 596 no-map; 597 }; 598 599 pil_camera_mem: memory@86000000 { 600 reg = <0 0x86000000 0 0x500000>; 601 no-map; 602 }; 603 604 pil_npu_mem: memory@86500000 { 605 reg = <0 0x86500000 0 0x500000>; 606 no-map; 607 }; 608 609 pil_video_mem: memory@86a00000 { 610 reg = <0 0x86a00000 0 0x500000>; 611 no-map; 612 }; 613 614 pil_cdsp_mem: memory@86f00000 { 615 reg = <0 0x86f00000 0 0x1e00000>; 616 no-map; 617 }; 618 619 pil_adsp_mem: memory@88d00000 { 620 reg = <0 0x88d00000 0 0x2800000>; 621 no-map; 622 }; 623 624 wlan_fw_mem: memory@8b500000 { 625 reg = <0 0x8b500000 0 0x200000>; 626 no-map; 627 }; 628 629 pil_ipa_fw_mem: memory@8b700000 { 630 reg = <0 0x8b700000 0 0x10000>; 631 no-map; 632 }; 633 634 pil_ipa_gsi_mem: memory@8b710000 { 635 reg = <0 0x8b710000 0 0x5400>; 636 no-map; 637 }; 638 639 pil_modem_mem: memory@8b800000 { 640 reg = <0 0x8b800000 0 0xf800000>; 641 no-map; 642 }; 643 644 cont_splash_memory: memory@a0000000 { 645 reg = <0 0xa0000000 0 0x2300000>; 646 no-map; 647 }; 648 649 dfps_data_memory: memory@a2300000 { 650 reg = <0 0xa2300000 0 0x100000>; 651 no-map; 652 }; 653 654 removed_region: memory@c0000000 { 655 reg = <0 0xc0000000 0 0x3900000>; 656 no-map; 657 }; 658 659 pil_gpu_mem: memory@f0d00000 { 660 reg = <0 0xf0d00000 0 0x1000>; 661 no-map; 662 }; 663 664 debug_region: memory@ffb00000 { 665 reg = <0 0xffb00000 0 0xc0000>; 666 no-map; 667 }; 668 669 last_log_region: memory@ffbc0000 { 670 reg = <0 0xffbc0000 0 0x40000>; 671 no-map; 672 }; 673 674 ramoops: ramoops@ffc00000 { 675 compatible = "ramoops"; 676 reg = <0 0xffc00000 0 0x100000>; 677 record-size = <0x1000>; 678 console-size = <0x40000>; 679 pmsg-size = <0x20000>; 680 ecc-size = <16>; 681 no-map; 682 }; 683 684 cmdline_region: memory@ffd00000 { 685 reg = <0 0xffd00000 0 0x1000>; 686 no-map; 687 }; 688 }; 689 690 smem { 691 compatible = "qcom,smem"; 692 memory-region = <&smem_mem>; 693 hwlocks = <&tcsr_mutex 3>; 694 }; 695 696 smp2p-adsp { 697 compatible = "qcom,smp2p"; 698 qcom,smem = <443>, <429>; 699 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 700 IPCC_MPROC_SIGNAL_SMP2P 701 IRQ_TYPE_EDGE_RISING>; 702 mboxes = <&ipcc IPCC_CLIENT_LPASS 703 IPCC_MPROC_SIGNAL_SMP2P>; 704 705 qcom,local-pid = <0>; 706 qcom,remote-pid = <2>; 707 708 smp2p_adsp_out: master-kernel { 709 qcom,entry-name = "master-kernel"; 710 #qcom,smem-state-cells = <1>; 711 }; 712 713 smp2p_adsp_in: slave-kernel { 714 qcom,entry-name = "slave-kernel"; 715 interrupt-controller; 716 #interrupt-cells = <2>; 717 }; 718 }; 719 720 smp2p-cdsp { 721 compatible = "qcom,smp2p"; 722 qcom,smem = <94>, <432>; 723 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 724 IPCC_MPROC_SIGNAL_SMP2P 725 IRQ_TYPE_EDGE_RISING>; 726 mboxes = <&ipcc IPCC_CLIENT_CDSP 727 IPCC_MPROC_SIGNAL_SMP2P>; 728 729 qcom,local-pid = <0>; 730 qcom,remote-pid = <5>; 731 732 smp2p_cdsp_out: master-kernel { 733 qcom,entry-name = "master-kernel"; 734 #qcom,smem-state-cells = <1>; 735 }; 736 737 smp2p_cdsp_in: slave-kernel { 738 qcom,entry-name = "slave-kernel"; 739 interrupt-controller; 740 #interrupt-cells = <2>; 741 }; 742 }; 743 744 smp2p-mpss { 745 compatible = "qcom,smp2p"; 746 qcom,smem = <435>, <428>; 747 748 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 749 IPCC_MPROC_SIGNAL_SMP2P 750 IRQ_TYPE_EDGE_RISING>; 751 mboxes = <&ipcc IPCC_CLIENT_MPSS 752 IPCC_MPROC_SIGNAL_SMP2P>; 753 754 qcom,local-pid = <0>; 755 qcom,remote-pid = <1>; 756 757 modem_smp2p_out: master-kernel { 758 qcom,entry-name = "master-kernel"; 759 #qcom,smem-state-cells = <1>; 760 }; 761 762 modem_smp2p_in: slave-kernel { 763 qcom,entry-name = "slave-kernel"; 764 interrupt-controller; 765 #interrupt-cells = <2>; 766 }; 767 768 ipa_smp2p_out: ipa-ap-to-modem { 769 qcom,entry-name = "ipa"; 770 #qcom,smem-state-cells = <1>; 771 }; 772 773 ipa_smp2p_in: ipa-modem-to-ap { 774 qcom,entry-name = "ipa"; 775 interrupt-controller; 776 #interrupt-cells = <2>; 777 }; 778 }; 779 780 soc: soc@0 { 781 #address-cells = <2>; 782 #size-cells = <2>; 783 ranges = <0 0 0 0 0x10 0>; 784 dma-ranges = <0 0 0 0 0x10 0>; 785 compatible = "simple-bus"; 786 787 gcc: clock-controller@100000 { 788 compatible = "qcom,gcc-sm6350"; 789 reg = <0 0x00100000 0 0x1f0000>; 790 #clock-cells = <1>; 791 #reset-cells = <1>; 792 #power-domain-cells = <1>; 793 clock-names = "bi_tcxo", 794 "bi_tcxo_ao", 795 "sleep_clk"; 796 clocks = <&rpmhcc RPMH_CXO_CLK>, 797 <&rpmhcc RPMH_CXO_CLK_A>, 798 <&sleep_clk>; 799 }; 800 801 ipcc: mailbox@408000 { 802 compatible = "qcom,sm6350-ipcc", "qcom,ipcc"; 803 reg = <0 0x00408000 0 0x1000>; 804 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 805 interrupt-controller; 806 #interrupt-cells = <3>; 807 #mbox-cells = <2>; 808 }; 809 810 qfprom: qfprom@784000 { 811 compatible = "qcom,sm6350-qfprom", "qcom,qfprom"; 812 reg = <0 0x00784000 0 0x3000>; 813 #address-cells = <1>; 814 #size-cells = <1>; 815 816 gpu_speed_bin: gpu-speed-bin@2015 { 817 reg = <0x2015 0x1>; 818 bits = <0 8>; 819 }; 820 }; 821 822 rng: rng@793000 { 823 compatible = "qcom,prng-ee"; 824 reg = <0 0x00793000 0 0x1000>; 825 clocks = <&gcc GCC_PRNG_AHB_CLK>; 826 clock-names = "core"; 827 }; 828 829 sdhc_1: mmc@7c4000 { 830 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 831 reg = <0 0x007c4000 0 0x1000>, 832 <0 0x007c5000 0 0x1000>, 833 <0 0x007c8000 0 0x8000>; 834 reg-names = "hc", "cqhci", "ice"; 835 836 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 838 interrupt-names = "hc_irq", "pwr_irq"; 839 iommus = <&apps_smmu 0x60 0x0>; 840 841 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 842 <&gcc GCC_SDCC1_APPS_CLK>, 843 <&rpmhcc RPMH_CXO_CLK>; 844 clock-names = "iface", "core", "xo"; 845 resets = <&gcc GCC_SDCC1_BCR>; 846 qcom,dll-config = <0x000f642c>; 847 qcom,ddr-config = <0x80040868>; 848 power-domains = <&rpmhpd SM6350_CX>; 849 operating-points-v2 = <&sdhc1_opp_table>; 850 bus-width = <8>; 851 non-removable; 852 supports-cqe; 853 854 status = "disabled"; 855 856 sdhc1_opp_table: opp-table { 857 compatible = "operating-points-v2"; 858 859 opp-19200000 { 860 opp-hz = /bits/ 64 <19200000>; 861 required-opps = <&rpmhpd_opp_min_svs>; 862 }; 863 864 opp-100000000 { 865 opp-hz = /bits/ 64 <100000000>; 866 required-opps = <&rpmhpd_opp_low_svs>; 867 }; 868 869 opp-384000000 { 870 opp-hz = /bits/ 64 <384000000>; 871 required-opps = <&rpmhpd_opp_svs_l1>; 872 }; 873 }; 874 }; 875 876 gpi_dma0: dma-controller@800000 { 877 compatible = "qcom,sm6350-gpi-dma"; 878 reg = <0 0x00800000 0 0x60000>; 879 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 880 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 889 dma-channels = <10>; 890 dma-channel-mask = <0x1f>; 891 iommus = <&apps_smmu 0x56 0x0>; 892 #dma-cells = <3>; 893 status = "disabled"; 894 }; 895 896 qupv3_id_0: geniqup@8c0000 { 897 compatible = "qcom,geni-se-qup"; 898 reg = <0x0 0x008c0000 0x0 0x2000>; 899 clock-names = "m-ahb", "s-ahb"; 900 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 901 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 902 #address-cells = <2>; 903 #size-cells = <2>; 904 iommus = <&apps_smmu 0x43 0x0>; 905 ranges; 906 status = "disabled"; 907 908 i2c0: i2c@880000 { 909 compatible = "qcom,geni-i2c"; 910 reg = <0 0x00880000 0 0x4000>; 911 clock-names = "se"; 912 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 913 pinctrl-names = "default"; 914 pinctrl-0 = <&qup_i2c0_default>; 915 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 916 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 917 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 918 dma-names = "tx", "rx"; 919 #address-cells = <1>; 920 #size-cells = <0>; 921 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 922 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 923 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 924 interconnect-names = "qup-core", "qup-config", "qup-memory"; 925 status = "disabled"; 926 }; 927 928 uart1: serial@884000 { 929 compatible = "qcom,geni-uart"; 930 reg = <0 0x00884000 0 0x4000>; 931 clock-names = "se"; 932 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 933 pinctrl-names = "default"; 934 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 935 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 936 power-domains = <&rpmhpd SM6350_CX>; 937 operating-points-v2 = <&qup_opp_table>; 938 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 939 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 940 interconnect-names = "qup-core", "qup-config"; 941 status = "disabled"; 942 }; 943 944 i2c2: i2c@888000 { 945 compatible = "qcom,geni-i2c"; 946 reg = <0 0x00888000 0 0x4000>; 947 clock-names = "se"; 948 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 949 pinctrl-names = "default"; 950 pinctrl-0 = <&qup_i2c2_default>; 951 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 952 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 953 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 954 dma-names = "tx", "rx"; 955 #address-cells = <1>; 956 #size-cells = <0>; 957 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 958 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 959 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 960 interconnect-names = "qup-core", "qup-config", "qup-memory"; 961 status = "disabled"; 962 }; 963 }; 964 965 gpi_dma1: dma-controller@900000 { 966 compatible = "qcom,sm6350-gpi-dma"; 967 reg = <0 0x00900000 0 0x60000>; 968 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 648 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 650 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>, 975 <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 976 <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>, 977 <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>; 978 dma-channels = <10>; 979 dma-channel-mask = <0x3f>; 980 iommus = <&apps_smmu 0x4d6 0x0>; 981 #dma-cells = <3>; 982 status = "disabled"; 983 }; 984 985 qupv3_id_1: geniqup@9c0000 { 986 compatible = "qcom,geni-se-qup"; 987 reg = <0x0 0x009c0000 0x0 0x2000>; 988 clock-names = "m-ahb", "s-ahb"; 989 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 990 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 991 #address-cells = <2>; 992 #size-cells = <2>; 993 iommus = <&apps_smmu 0x4c3 0x0>; 994 ranges; 995 status = "disabled"; 996 997 i2c6: i2c@980000 { 998 compatible = "qcom,geni-i2c"; 999 reg = <0 0x00980000 0 0x4000>; 1000 clock-names = "se"; 1001 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1002 pinctrl-names = "default"; 1003 pinctrl-0 = <&qup_i2c6_default>; 1004 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1005 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1006 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1007 dma-names = "tx", "rx"; 1008 #address-cells = <1>; 1009 #size-cells = <0>; 1010 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1011 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1012 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1013 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1014 status = "disabled"; 1015 }; 1016 1017 i2c7: i2c@984000 { 1018 compatible = "qcom,geni-i2c"; 1019 reg = <0 0x00984000 0 0x4000>; 1020 clock-names = "se"; 1021 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1022 pinctrl-names = "default"; 1023 pinctrl-0 = <&qup_i2c7_default>; 1024 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1025 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1026 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1027 dma-names = "tx", "rx"; 1028 #address-cells = <1>; 1029 #size-cells = <0>; 1030 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1031 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1032 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1033 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1034 status = "disabled"; 1035 }; 1036 1037 i2c8: i2c@988000 { 1038 compatible = "qcom,geni-i2c"; 1039 reg = <0 0x00988000 0 0x4000>; 1040 clock-names = "se"; 1041 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1042 pinctrl-names = "default"; 1043 pinctrl-0 = <&qup_i2c8_default>; 1044 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1045 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1046 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1047 dma-names = "tx", "rx"; 1048 #address-cells = <1>; 1049 #size-cells = <0>; 1050 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1051 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1052 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1053 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1054 status = "disabled"; 1055 }; 1056 1057 uart9: serial@98c000 { 1058 compatible = "qcom,geni-debug-uart"; 1059 reg = <0 0x0098c000 0 0x4000>; 1060 clock-names = "se"; 1061 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1062 pinctrl-names = "default"; 1063 pinctrl-0 = <&qup_uart9_default>; 1064 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1065 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1066 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1067 interconnect-names = "qup-core", "qup-config"; 1068 status = "disabled"; 1069 }; 1070 1071 i2c10: i2c@990000 { 1072 compatible = "qcom,geni-i2c"; 1073 reg = <0 0x00990000 0 0x4000>; 1074 clock-names = "se"; 1075 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1076 pinctrl-names = "default"; 1077 pinctrl-0 = <&qup_i2c10_default>; 1078 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1079 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1080 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1081 dma-names = "tx", "rx"; 1082 #address-cells = <1>; 1083 #size-cells = <0>; 1084 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1085 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1086 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1087 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1088 status = "disabled"; 1089 }; 1090 }; 1091 1092 config_noc: interconnect@1500000 { 1093 compatible = "qcom,sm6350-config-noc"; 1094 reg = <0 0x01500000 0 0x28000>; 1095 #interconnect-cells = <2>; 1096 qcom,bcm-voters = <&apps_bcm_voter>; 1097 }; 1098 1099 system_noc: interconnect@1620000 { 1100 compatible = "qcom,sm6350-system-noc"; 1101 reg = <0 0x01620000 0 0x17080>; 1102 #interconnect-cells = <2>; 1103 qcom,bcm-voters = <&apps_bcm_voter>; 1104 1105 clk_virt: interconnect-clk-virt { 1106 compatible = "qcom,sm6350-clk-virt"; 1107 #interconnect-cells = <2>; 1108 qcom,bcm-voters = <&apps_bcm_voter>; 1109 }; 1110 }; 1111 1112 aggre1_noc: interconnect@16e0000 { 1113 compatible = "qcom,sm6350-aggre1-noc"; 1114 reg = <0 0x016e0000 0 0x15080>; 1115 #interconnect-cells = <2>; 1116 qcom,bcm-voters = <&apps_bcm_voter>; 1117 }; 1118 1119 aggre2_noc: interconnect@1700000 { 1120 compatible = "qcom,sm6350-aggre2-noc"; 1121 reg = <0 0x01700000 0 0x1f880>; 1122 #interconnect-cells = <2>; 1123 qcom,bcm-voters = <&apps_bcm_voter>; 1124 1125 compute_noc: interconnect-compute-noc { 1126 compatible = "qcom,sm6350-compute-noc"; 1127 #interconnect-cells = <2>; 1128 qcom,bcm-voters = <&apps_bcm_voter>; 1129 }; 1130 }; 1131 1132 mmss_noc: interconnect@1740000 { 1133 compatible = "qcom,sm6350-mmss-noc"; 1134 reg = <0 0x01740000 0 0x1c100>; 1135 #interconnect-cells = <2>; 1136 qcom,bcm-voters = <&apps_bcm_voter>; 1137 }; 1138 1139 ufs_mem_hc: ufs@1d84000 { 1140 compatible = "qcom,sm6350-ufshc", "qcom,ufshc", 1141 "jedec,ufs-2.0"; 1142 reg = <0 0x01d84000 0 0x3000>, 1143 <0 0x01d90000 0 0x8000>; 1144 reg-names = "std", "ice"; 1145 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1146 phys = <&ufs_mem_phy>; 1147 phy-names = "ufsphy"; 1148 lanes-per-direction = <2>; 1149 #reset-cells = <1>; 1150 resets = <&gcc GCC_UFS_PHY_BCR>; 1151 reset-names = "rst"; 1152 1153 power-domains = <&gcc UFS_PHY_GDSC>; 1154 1155 iommus = <&apps_smmu 0x80 0x0>; 1156 1157 clock-names = "core_clk", 1158 "bus_aggr_clk", 1159 "iface_clk", 1160 "core_clk_unipro", 1161 "ref_clk", 1162 "tx_lane0_sync_clk", 1163 "rx_lane0_sync_clk", 1164 "rx_lane1_sync_clk", 1165 "ice_core_clk"; 1166 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1167 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1168 <&gcc GCC_UFS_PHY_AHB_CLK>, 1169 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1170 <&rpmhcc RPMH_QLINK_CLK>, 1171 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1172 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1173 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 1174 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1175 freq-table-hz = 1176 <50000000 200000000>, 1177 <0 0>, 1178 <0 0>, 1179 <37500000 150000000>, 1180 <75000000 300000000>, 1181 <0 0>, 1182 <0 0>, 1183 <0 0>, 1184 <0 0>; 1185 1186 status = "disabled"; 1187 }; 1188 1189 ufs_mem_phy: phy@1d87000 { 1190 compatible = "qcom,sm6350-qmp-ufs-phy"; 1191 reg = <0 0x01d87000 0 0x1000>; 1192 1193 clocks = <&rpmhcc RPMH_CXO_CLK>, 1194 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1195 <&gcc GCC_UFS_MEM_CLKREF_CLK>; 1196 clock-names = "ref", 1197 "ref_aux", 1198 "qref"; 1199 1200 resets = <&ufs_mem_hc 0>; 1201 reset-names = "ufsphy"; 1202 1203 #phy-cells = <0>; 1204 1205 status = "disabled"; 1206 }; 1207 1208 ipa: ipa@1e40000 { 1209 compatible = "qcom,sm6350-ipa"; 1210 1211 iommus = <&apps_smmu 0x440 0x0>, 1212 <&apps_smmu 0x442 0x0>; 1213 reg = <0 0x01e40000 0 0x8000>, 1214 <0 0x01e50000 0 0x3000>, 1215 <0 0x01e04000 0 0x23000>; 1216 reg-names = "ipa-reg", 1217 "ipa-shared", 1218 "gsi"; 1219 1220 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 1221 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1222 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1223 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1224 interrupt-names = "ipa", 1225 "gsi", 1226 "ipa-clock-query", 1227 "ipa-setup-ready"; 1228 1229 clocks = <&rpmhcc RPMH_IPA_CLK>; 1230 clock-names = "core"; 1231 1232 interconnects = <&aggre2_noc MASTER_IPA 0 &clk_virt SLAVE_EBI_CH0 0>, 1233 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_OCIMEM 0>, 1234 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_IPA_CFG 0>; 1235 interconnect-names = "memory", "imem", "config"; 1236 1237 qcom,smem-states = <&ipa_smp2p_out 0>, 1238 <&ipa_smp2p_out 1>; 1239 qcom,smem-state-names = "ipa-clock-enabled-valid", 1240 "ipa-clock-enabled"; 1241 1242 status = "disabled"; 1243 }; 1244 1245 tcsr_mutex: hwlock@1f40000 { 1246 compatible = "qcom,tcsr-mutex"; 1247 reg = <0x0 0x01f40000 0x0 0x40000>; 1248 #hwlock-cells = <1>; 1249 }; 1250 1251 adsp: remoteproc@3000000 { 1252 compatible = "qcom,sm6350-adsp-pas"; 1253 reg = <0 0x03000000 0 0x100>; 1254 1255 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 1256 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1257 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1258 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1259 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1260 interrupt-names = "wdog", "fatal", "ready", 1261 "handover", "stop-ack"; 1262 1263 clocks = <&rpmhcc RPMH_CXO_CLK>; 1264 clock-names = "xo"; 1265 1266 power-domains = <&rpmhpd SM6350_LCX>, 1267 <&rpmhpd SM6350_LMX>; 1268 power-domain-names = "lcx", "lmx"; 1269 1270 memory-region = <&pil_adsp_mem>; 1271 1272 qcom,qmp = <&aoss_qmp>; 1273 1274 qcom,smem-states = <&smp2p_adsp_out 0>; 1275 qcom,smem-state-names = "stop"; 1276 1277 status = "disabled"; 1278 1279 glink-edge { 1280 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1281 IPCC_MPROC_SIGNAL_GLINK_QMP 1282 IRQ_TYPE_EDGE_RISING>; 1283 mboxes = <&ipcc IPCC_CLIENT_LPASS 1284 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1285 1286 label = "lpass"; 1287 qcom,remote-pid = <2>; 1288 1289 fastrpc { 1290 compatible = "qcom,fastrpc"; 1291 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1292 label = "adsp"; 1293 #address-cells = <1>; 1294 #size-cells = <0>; 1295 1296 compute-cb@3 { 1297 compatible = "qcom,fastrpc-compute-cb"; 1298 reg = <3>; 1299 iommus = <&apps_smmu 0x1003 0x0>; 1300 }; 1301 1302 compute-cb@4 { 1303 compatible = "qcom,fastrpc-compute-cb"; 1304 reg = <4>; 1305 iommus = <&apps_smmu 0x1004 0x0>; 1306 }; 1307 1308 compute-cb@5 { 1309 compatible = "qcom,fastrpc-compute-cb"; 1310 reg = <5>; 1311 iommus = <&apps_smmu 0x1005 0x0>; 1312 qcom,nsessions = <5>; 1313 }; 1314 }; 1315 }; 1316 }; 1317 1318 gpu: gpu@3d00000 { 1319 compatible = "qcom,adreno-619.0", "qcom,adreno"; 1320 reg = <0 0x03d00000 0 0x40000>, 1321 <0 0x03d9e000 0 0x1000>; 1322 reg-names = "kgsl_3d0_reg_memory", 1323 "cx_mem"; 1324 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1325 1326 iommus = <&adreno_smmu 0>; 1327 operating-points-v2 = <&gpu_opp_table>; 1328 qcom,gmu = <&gmu>; 1329 nvmem-cells = <&gpu_speed_bin>; 1330 nvmem-cell-names = "speed_bin"; 1331 #cooling-cells = <2>; 1332 1333 status = "disabled"; 1334 1335 gpu_zap_shader: zap-shader { 1336 memory-region = <&pil_gpu_mem>; 1337 }; 1338 1339 gpu_opp_table: opp-table { 1340 compatible = "operating-points-v2"; 1341 1342 opp-850000000 { 1343 opp-hz = /bits/ 64 <850000000>; 1344 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1345 opp-supported-hw = <0x02>; 1346 }; 1347 1348 opp-800000000 { 1349 opp-hz = /bits/ 64 <800000000>; 1350 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1351 opp-supported-hw = <0x04>; 1352 }; 1353 1354 opp-650000000 { 1355 opp-hz = /bits/ 64 <650000000>; 1356 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1357 opp-supported-hw = <0x08>; 1358 }; 1359 1360 opp-565000000 { 1361 opp-hz = /bits/ 64 <565000000>; 1362 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1363 opp-supported-hw = <0x10>; 1364 }; 1365 1366 opp-430000000 { 1367 opp-hz = /bits/ 64 <430000000>; 1368 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1369 opp-supported-hw = <0xff>; 1370 }; 1371 1372 opp-355000000 { 1373 opp-hz = /bits/ 64 <355000000>; 1374 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1375 opp-supported-hw = <0xff>; 1376 }; 1377 1378 opp-253000000 { 1379 opp-hz = /bits/ 64 <253000000>; 1380 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1381 opp-supported-hw = <0xff>; 1382 }; 1383 }; 1384 }; 1385 1386 adreno_smmu: iommu@3d40000 { 1387 compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 1388 reg = <0 0x03d40000 0 0x10000>; 1389 #iommu-cells = <1>; 1390 #global-interrupts = <2>; 1391 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1392 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1393 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 1394 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 1395 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 1396 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 1397 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 1398 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 1399 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 1400 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1401 1402 clocks = <&gpucc GPU_CC_AHB_CLK>, 1403 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1404 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1405 clock-names = "ahb", 1406 "bus", 1407 "iface"; 1408 1409 power-domains = <&gpucc GPU_CX_GDSC>; 1410 }; 1411 1412 gmu: gmu@3d6a000 { 1413 compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu"; 1414 reg = <0 0x03d6a000 0 0x31000>, 1415 <0 0x0b290000 0 0x10000>, 1416 <0 0x0b490000 0 0x10000>; 1417 reg-names = "gmu", 1418 "gmu_pdc", 1419 "gmu_pdc_seq"; 1420 1421 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1422 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1423 interrupt-names = "hfi", 1424 "gmu"; 1425 1426 clocks = <&gpucc GPU_CC_AHB_CLK>, 1427 <&gpucc GPU_CC_CX_GMU_CLK>, 1428 <&gpucc GPU_CC_CXO_CLK>, 1429 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1430 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1431 clock-names = "ahb", 1432 "gmu", 1433 "cxo", 1434 "axi", 1435 "memnoc"; 1436 1437 power-domains = <&gpucc GPU_CX_GDSC>, 1438 <&gpucc GPU_GX_GDSC>; 1439 power-domain-names = "cx", 1440 "gx"; 1441 1442 iommus = <&adreno_smmu 5>; 1443 1444 operating-points-v2 = <&gmu_opp_table>; 1445 1446 gmu_opp_table: opp-table { 1447 compatible = "operating-points-v2"; 1448 1449 opp-200000000 { 1450 opp-hz = /bits/ 64 <200000000>; 1451 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1452 }; 1453 }; 1454 }; 1455 1456 gpucc: clock-controller@3d90000 { 1457 compatible = "qcom,sm6350-gpucc"; 1458 reg = <0 0x03d90000 0 0x9000>; 1459 clocks = <&rpmhcc RPMH_CXO_CLK>, 1460 <&gcc GCC_GPU_GPLL0_CLK>, 1461 <&gcc GCC_GPU_GPLL0_DIV_CLK>; 1462 clock-names = "bi_tcxo", 1463 "gcc_gpu_gpll0_clk_src", 1464 "gcc_gpu_gpll0_div_clk_src"; 1465 #clock-cells = <1>; 1466 #reset-cells = <1>; 1467 #power-domain-cells = <1>; 1468 }; 1469 1470 mpss: remoteproc@4080000 { 1471 compatible = "qcom,sm6350-mpss-pas"; 1472 reg = <0x0 0x04080000 0x0 0x4040>; 1473 1474 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 1475 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1476 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1477 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1478 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1479 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1480 interrupt-names = "wdog", "fatal", "ready", "handover", 1481 "stop-ack", "shutdown-ack"; 1482 1483 clocks = <&rpmhcc RPMH_CXO_CLK>; 1484 clock-names = "xo"; 1485 1486 power-domains = <&rpmhpd SM6350_CX>, 1487 <&rpmhpd SM6350_MSS>; 1488 power-domain-names = "cx", "mss"; 1489 1490 memory-region = <&pil_modem_mem>; 1491 1492 qcom,qmp = <&aoss_qmp>; 1493 1494 qcom,smem-states = <&modem_smp2p_out 0>; 1495 qcom,smem-state-names = "stop"; 1496 1497 status = "disabled"; 1498 1499 glink-edge { 1500 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1501 IPCC_MPROC_SIGNAL_GLINK_QMP 1502 IRQ_TYPE_EDGE_RISING>; 1503 mboxes = <&ipcc IPCC_CLIENT_MPSS 1504 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1505 label = "modem"; 1506 qcom,remote-pid = <1>; 1507 }; 1508 }; 1509 1510 cdsp: remoteproc@8300000 { 1511 compatible = "qcom,sm6350-cdsp-pas"; 1512 reg = <0 0x08300000 0 0x10000>; 1513 1514 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 1515 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 1516 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 1517 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 1518 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 1519 interrupt-names = "wdog", "fatal", "ready", 1520 "handover", "stop-ack"; 1521 1522 clocks = <&rpmhcc RPMH_CXO_CLK>; 1523 clock-names = "xo"; 1524 1525 power-domains = <&rpmhpd SM6350_CX>, 1526 <&rpmhpd SM6350_MX>; 1527 power-domain-names = "cx", "mx"; 1528 1529 memory-region = <&pil_cdsp_mem>; 1530 1531 qcom,qmp = <&aoss_qmp>; 1532 1533 qcom,smem-states = <&smp2p_cdsp_out 0>; 1534 qcom,smem-state-names = "stop"; 1535 1536 status = "disabled"; 1537 1538 glink-edge { 1539 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 1540 IPCC_MPROC_SIGNAL_GLINK_QMP 1541 IRQ_TYPE_EDGE_RISING>; 1542 mboxes = <&ipcc IPCC_CLIENT_CDSP 1543 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1544 1545 label = "cdsp"; 1546 qcom,remote-pid = <5>; 1547 1548 fastrpc { 1549 compatible = "qcom,fastrpc"; 1550 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1551 label = "cdsp"; 1552 #address-cells = <1>; 1553 #size-cells = <0>; 1554 1555 compute-cb@1 { 1556 compatible = "qcom,fastrpc-compute-cb"; 1557 reg = <1>; 1558 iommus = <&apps_smmu 0x1401 0x20>; 1559 }; 1560 1561 compute-cb@2 { 1562 compatible = "qcom,fastrpc-compute-cb"; 1563 reg = <2>; 1564 iommus = <&apps_smmu 0x1402 0x20>; 1565 }; 1566 1567 compute-cb@3 { 1568 compatible = "qcom,fastrpc-compute-cb"; 1569 reg = <3>; 1570 iommus = <&apps_smmu 0x1403 0x20>; 1571 }; 1572 1573 compute-cb@4 { 1574 compatible = "qcom,fastrpc-compute-cb"; 1575 reg = <4>; 1576 iommus = <&apps_smmu 0x1404 0x20>; 1577 }; 1578 1579 compute-cb@5 { 1580 compatible = "qcom,fastrpc-compute-cb"; 1581 reg = <5>; 1582 iommus = <&apps_smmu 0x1405 0x20>; 1583 }; 1584 1585 compute-cb@6 { 1586 compatible = "qcom,fastrpc-compute-cb"; 1587 reg = <6>; 1588 iommus = <&apps_smmu 0x1406 0x20>; 1589 }; 1590 1591 compute-cb@7 { 1592 compatible = "qcom,fastrpc-compute-cb"; 1593 reg = <7>; 1594 iommus = <&apps_smmu 0x1407 0x20>; 1595 }; 1596 1597 compute-cb@8 { 1598 compatible = "qcom,fastrpc-compute-cb"; 1599 reg = <8>; 1600 iommus = <&apps_smmu 0x1408 0x20>; 1601 }; 1602 1603 /* note: secure cb9 in downstream */ 1604 }; 1605 }; 1606 }; 1607 1608 sdhc_2: mmc@8804000 { 1609 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 1610 reg = <0 0x08804000 0 0x1000>; 1611 1612 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1613 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1614 interrupt-names = "hc_irq", "pwr_irq"; 1615 iommus = <&apps_smmu 0x560 0x0>; 1616 1617 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1618 <&gcc GCC_SDCC2_APPS_CLK>, 1619 <&rpmhcc RPMH_CXO_CLK>; 1620 clock-names = "iface", "core", "xo"; 1621 resets = <&gcc GCC_SDCC2_BCR>; 1622 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>, 1623 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>; 1624 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 1625 1626 pinctrl-0 = <&sdc2_on_state>; 1627 pinctrl-1 = <&sdc2_off_state>; 1628 pinctrl-names = "default", "sleep"; 1629 1630 qcom,dll-config = <0x0007642c>; 1631 qcom,ddr-config = <0x80040868>; 1632 power-domains = <&rpmhpd SM6350_CX>; 1633 operating-points-v2 = <&sdhc2_opp_table>; 1634 bus-width = <4>; 1635 1636 status = "disabled"; 1637 1638 sdhc2_opp_table: opp-table { 1639 compatible = "operating-points-v2"; 1640 1641 opp-100000000 { 1642 opp-hz = /bits/ 64 <100000000>; 1643 required-opps = <&rpmhpd_opp_svs_l1>; 1644 opp-peak-kBps = <790000 131000>; 1645 opp-avg-kBps = <50000 50000>; 1646 }; 1647 1648 opp-202000000 { 1649 opp-hz = /bits/ 64 <202000000>; 1650 required-opps = <&rpmhpd_opp_nom>; 1651 opp-peak-kBps = <3190000 294000>; 1652 opp-avg-kBps = <261438 300000>; 1653 }; 1654 }; 1655 }; 1656 1657 usb_1_hsphy: phy@88e3000 { 1658 compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy"; 1659 reg = <0 0x088e3000 0 0x400>; 1660 status = "disabled"; 1661 #phy-cells = <0>; 1662 1663 clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>; 1664 clock-names = "cfg_ahb", "ref"; 1665 1666 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1667 }; 1668 1669 usb_1_qmpphy: phy@88e8000 { 1670 compatible = "qcom,sm6350-qmp-usb3-dp-phy"; 1671 reg = <0 0x088e8000 0 0x3000>; 1672 1673 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1674 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 1675 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 1676 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1677 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 1678 1679 power-domains = <&gcc USB30_PRIM_GDSC>; 1680 1681 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 1682 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 1683 reset-names = "phy", "common"; 1684 1685 #clock-cells = <1>; 1686 #phy-cells = <1>; 1687 1688 status = "disabled"; 1689 }; 1690 1691 dc_noc: interconnect@9160000 { 1692 compatible = "qcom,sm6350-dc-noc"; 1693 reg = <0 0x09160000 0 0x3200>; 1694 #interconnect-cells = <2>; 1695 qcom,bcm-voters = <&apps_bcm_voter>; 1696 }; 1697 1698 system-cache-controller@9200000 { 1699 compatible = "qcom,sm6350-llcc"; 1700 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 1701 reg-names = "llcc0_base", "llcc_broadcast_base"; 1702 }; 1703 1704 gem_noc: interconnect@9680000 { 1705 compatible = "qcom,sm6350-gem-noc"; 1706 reg = <0 0x09680000 0 0x3e200>; 1707 #interconnect-cells = <2>; 1708 qcom,bcm-voters = <&apps_bcm_voter>; 1709 }; 1710 1711 npu_noc: interconnect@9990000 { 1712 compatible = "qcom,sm6350-npu-noc"; 1713 reg = <0 0x09990000 0 0x1600>; 1714 #interconnect-cells = <2>; 1715 qcom,bcm-voters = <&apps_bcm_voter>; 1716 }; 1717 1718 pmu@90b6300 { 1719 compatible = "qcom,sm6350-llcc-bwmon", "qcom,sdm845-bwmon"; 1720 reg = <0x0 0x090b6300 0x0 0x600>; 1721 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 1722 1723 operating-points-v2 = <&llcc_bwmon_opp_table>; 1724 interconnects = <&clk_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 1725 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>; 1726 1727 llcc_bwmon_opp_table: opp-table { 1728 compatible = "operating-points-v2"; 1729 1730 opp-0 { 1731 opp-peak-kBps = <2288000>; 1732 }; 1733 1734 opp-1 { 1735 opp-peak-kBps = <4577000>; 1736 }; 1737 1738 opp-2 { 1739 opp-peak-kBps = <7110000>; 1740 }; 1741 1742 opp-3 { 1743 opp-peak-kBps = <9155000>; 1744 }; 1745 1746 opp-4 { 1747 opp-peak-kBps = <12298000>; 1748 }; 1749 1750 opp-5 { 1751 opp-peak-kBps = <14236000>; 1752 }; 1753 1754 }; 1755 }; 1756 1757 pmu@90cd000 { 1758 compatible = "qcom,sm6350-cpu-bwmon", "qcom,sc7280-llcc-bwmon"; 1759 reg = <0x0 0x090cd000 0x0 0x1000>; 1760 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1761 1762 operating-points-v2 = <&cpu_bwmon_opp_table>; 1763 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 1764 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>; 1765 1766 cpu_bwmon_opp_table: opp-table { 1767 compatible = "operating-points-v2"; 1768 1769 opp-0 { 1770 opp-peak-kBps = <762000>; 1771 }; 1772 1773 opp-1 { 1774 opp-peak-kBps = <1144000>; 1775 }; 1776 1777 opp-2 { 1778 opp-peak-kBps = <1720000>; 1779 }; 1780 1781 opp-3 { 1782 opp-peak-kBps = <2086000>; 1783 }; 1784 1785 opp-4 { 1786 opp-peak-kBps = <2597000>; 1787 }; 1788 1789 opp-5 { 1790 opp-peak-kBps = <2929000>; 1791 }; 1792 1793 opp-6 { 1794 opp-peak-kBps = <3879000>; 1795 }; 1796 1797 opp-7 { 1798 opp-peak-kBps = <5161000>; 1799 }; 1800 1801 opp-8 { 1802 opp-peak-kBps = <5931000>; 1803 }; 1804 1805 opp-9 { 1806 opp-peak-kBps = <6881000>; 1807 }; 1808 1809 opp-10 { 1810 opp-peak-kBps = <7980000>; 1811 }; 1812 }; 1813 }; 1814 1815 usb_1: usb@a6f8800 { 1816 compatible = "qcom,sm6350-dwc3", "qcom,dwc3"; 1817 reg = <0 0x0a6f8800 0 0x400>; 1818 status = "disabled"; 1819 #address-cells = <2>; 1820 #size-cells = <2>; 1821 ranges; 1822 1823 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1824 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1825 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1826 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1827 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 1828 clock-names = "cfg_noc", 1829 "core", 1830 "iface", 1831 "sleep", 1832 "mock_utmi"; 1833 1834 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1835 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1836 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 1837 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1838 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 1839 interrupt-names = "pwr_event", 1840 "hs_phy_irq", 1841 "dp_hs_phy_irq", 1842 "dm_hs_phy_irq", 1843 "ss_phy_irq"; 1844 1845 power-domains = <&gcc USB30_PRIM_GDSC>; 1846 1847 resets = <&gcc GCC_USB30_PRIM_BCR>; 1848 1849 interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>, 1850 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 1851 interconnect-names = "usb-ddr", "apps-usb"; 1852 1853 usb_1_dwc3: usb@a600000 { 1854 compatible = "snps,dwc3"; 1855 reg = <0 0x0a600000 0 0xcd00>; 1856 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1857 iommus = <&apps_smmu 0x540 0x0>; 1858 snps,dis_u2_susphy_quirk; 1859 snps,dis_enblslpm_quirk; 1860 snps,has-lpm-erratum; 1861 snps,hird-threshold = /bits/ 8 <0x10>; 1862 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 1863 phy-names = "usb2-phy", "usb3-phy"; 1864 }; 1865 }; 1866 1867 cci0: cci@ac4a000 { 1868 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; 1869 reg = <0 0x0ac4a000 0 0x1000>; 1870 interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>; 1871 power-domains = <&camcc TITAN_TOP_GDSC>; 1872 1873 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1874 <&camcc CAMCC_SOC_AHB_CLK>, 1875 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 1876 <&camcc CAMCC_CPAS_AHB_CLK>, 1877 <&camcc CAMCC_CCI_0_CLK>, 1878 <&camcc CAMCC_CCI_0_CLK_SRC>; 1879 clock-names = "camnoc_axi", 1880 "soc_ahb", 1881 "slow_ahb_src", 1882 "cpas_ahb", 1883 "cci", 1884 "cci_src"; 1885 1886 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1887 <&camcc CAMCC_CCI_0_CLK>; 1888 assigned-clock-rates = <80000000>, <37500000>; 1889 1890 pinctrl-0 = <&cci0_default &cci1_default>; 1891 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 1892 pinctrl-names = "default", "sleep"; 1893 1894 #address-cells = <1>; 1895 #size-cells = <0>; 1896 1897 status = "disabled"; 1898 1899 cci0_i2c0: i2c-bus@0 { 1900 reg = <0>; 1901 clock-frequency = <1000000>; 1902 #address-cells = <1>; 1903 #size-cells = <0>; 1904 }; 1905 1906 cci0_i2c1: i2c-bus@1 { 1907 reg = <1>; 1908 clock-frequency = <1000000>; 1909 #address-cells = <1>; 1910 #size-cells = <0>; 1911 }; 1912 }; 1913 1914 cci1: cci@ac4b000 { 1915 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; 1916 reg = <0 0x0ac4b000 0 0x1000>; 1917 interrupts = <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>; 1918 power-domains = <&camcc TITAN_TOP_GDSC>; 1919 1920 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1921 <&camcc CAMCC_SOC_AHB_CLK>, 1922 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 1923 <&camcc CAMCC_CPAS_AHB_CLK>, 1924 <&camcc CAMCC_CCI_1_CLK>, 1925 <&camcc CAMCC_CCI_1_CLK_SRC>; 1926 clock-names = "camnoc_axi", 1927 "soc_ahb", 1928 "slow_ahb_src", 1929 "cpas_ahb", 1930 "cci", 1931 "cci_src"; 1932 1933 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1934 <&camcc CAMCC_CCI_1_CLK>; 1935 assigned-clock-rates = <80000000>, <37500000>; 1936 1937 pinctrl-0 = <&cci2_default>; 1938 pinctrl-1 = <&cci2_sleep>; 1939 pinctrl-names = "default", "sleep"; 1940 1941 #address-cells = <1>; 1942 #size-cells = <0>; 1943 1944 status = "disabled"; 1945 1946 cci1_i2c0: i2c-bus@0 { 1947 reg = <0>; 1948 clock-frequency = <1000000>; 1949 #address-cells = <1>; 1950 #size-cells = <0>; 1951 }; 1952 1953 /* SM6350 seems to have cci1_i2c1 on gpio2 & gpio3 but unused downstream */ 1954 }; 1955 1956 camcc: clock-controller@ad00000 { 1957 compatible = "qcom,sm6350-camcc"; 1958 reg = <0 0x0ad00000 0 0x16000>; 1959 clocks = <&rpmhcc RPMH_CXO_CLK>; 1960 #clock-cells = <1>; 1961 #reset-cells = <1>; 1962 #power-domain-cells = <1>; 1963 }; 1964 1965 mdss: display-subsystem@ae00000 { 1966 compatible = "qcom,sm6350-mdss"; 1967 reg = <0 0x0ae00000 0 0x1000>; 1968 reg-names = "mdss"; 1969 1970 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1971 interrupt-controller; 1972 #interrupt-cells = <1>; 1973 1974 interconnects = <&mmss_noc MASTER_MDP_PORT0 QCOM_ICC_TAG_ALWAYS 1975 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, 1976 <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 1977 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 1978 interconnect-names = "mdp0-mem", 1979 "cpu-cfg"; 1980 1981 clocks = <&gcc GCC_DISP_AHB_CLK>, 1982 <&gcc GCC_DISP_AXI_CLK>, 1983 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1984 clock-names = "iface", 1985 "bus", 1986 "core"; 1987 1988 power-domains = <&dispcc MDSS_GDSC>; 1989 iommus = <&apps_smmu 0x800 0x2>; 1990 1991 #address-cells = <2>; 1992 #size-cells = <2>; 1993 ranges; 1994 1995 status = "disabled"; 1996 1997 mdss_mdp: display-controller@ae01000 { 1998 compatible = "qcom,sm6350-dpu"; 1999 reg = <0 0x0ae01000 0 0x8f000>, 2000 <0 0x0aeb0000 0 0x2008>; 2001 reg-names = "mdp", "vbif"; 2002 2003 interrupt-parent = <&mdss>; 2004 interrupts = <0>; 2005 2006 clocks = <&gcc GCC_DISP_AXI_CLK>, 2007 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2008 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2009 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2010 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2011 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2012 clock-names = "bus", 2013 "iface", 2014 "rot", 2015 "lut", 2016 "core", 2017 "vsync"; 2018 2019 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2020 assigned-clock-rates = <19200000>; 2021 2022 operating-points-v2 = <&mdp_opp_table>; 2023 power-domains = <&rpmhpd SM6350_CX>; 2024 2025 ports { 2026 #address-cells = <1>; 2027 #size-cells = <0>; 2028 2029 port@0 { 2030 reg = <0>; 2031 2032 dpu_intf1_out: endpoint { 2033 remote-endpoint = <&mdss_dsi0_in>; 2034 }; 2035 }; 2036 }; 2037 2038 mdp_opp_table: opp-table { 2039 compatible = "operating-points-v2"; 2040 2041 opp-19200000 { 2042 opp-hz = /bits/ 64 <19200000>; 2043 required-opps = <&rpmhpd_opp_min_svs>; 2044 }; 2045 2046 opp-200000000 { 2047 opp-hz = /bits/ 64 <200000000>; 2048 required-opps = <&rpmhpd_opp_low_svs>; 2049 }; 2050 2051 opp-300000000 { 2052 opp-hz = /bits/ 64 <300000000>; 2053 required-opps = <&rpmhpd_opp_svs>; 2054 }; 2055 2056 opp-373333333 { 2057 opp-hz = /bits/ 64 <373333333>; 2058 required-opps = <&rpmhpd_opp_svs_l1>; 2059 }; 2060 2061 opp-448000000 { 2062 opp-hz = /bits/ 64 <448000000>; 2063 required-opps = <&rpmhpd_opp_nom>; 2064 }; 2065 2066 opp-560000000 { 2067 opp-hz = /bits/ 64 <560000000>; 2068 required-opps = <&rpmhpd_opp_turbo>; 2069 }; 2070 }; 2071 }; 2072 2073 mdss_dsi0: dsi@ae94000 { 2074 compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2075 reg = <0 0x0ae94000 0 0x400>; 2076 reg-names = "dsi_ctrl"; 2077 2078 interrupt-parent = <&mdss>; 2079 interrupts = <4>; 2080 2081 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2082 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2083 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2084 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2085 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2086 <&gcc GCC_DISP_AXI_CLK>; 2087 clock-names = "byte", 2088 "byte_intf", 2089 "pixel", 2090 "core", 2091 "iface", 2092 "bus"; 2093 2094 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2095 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2096 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 2097 2098 operating-points-v2 = <&mdss_dsi_opp_table>; 2099 power-domains = <&rpmhpd SM6350_MX>; 2100 2101 phys = <&mdss_dsi0_phy>; 2102 phy-names = "dsi"; 2103 2104 #address-cells = <1>; 2105 #size-cells = <0>; 2106 2107 status = "disabled"; 2108 2109 ports { 2110 #address-cells = <1>; 2111 #size-cells = <0>; 2112 2113 port@0 { 2114 reg = <0>; 2115 2116 mdss_dsi0_in: endpoint { 2117 remote-endpoint = <&dpu_intf1_out>; 2118 }; 2119 }; 2120 2121 port@1 { 2122 reg = <1>; 2123 2124 mdss_dsi0_out: endpoint { 2125 }; 2126 }; 2127 }; 2128 2129 mdss_dsi_opp_table: opp-table { 2130 compatible = "operating-points-v2"; 2131 2132 opp-187500000 { 2133 opp-hz = /bits/ 64 <187500000>; 2134 required-opps = <&rpmhpd_opp_low_svs>; 2135 }; 2136 2137 opp-300000000 { 2138 opp-hz = /bits/ 64 <300000000>; 2139 required-opps = <&rpmhpd_opp_svs>; 2140 }; 2141 2142 opp-358000000 { 2143 opp-hz = /bits/ 64 <358000000>; 2144 required-opps = <&rpmhpd_opp_svs_l1>; 2145 }; 2146 }; 2147 }; 2148 2149 mdss_dsi0_phy: phy@ae94400 { 2150 compatible = "qcom,dsi-phy-10nm"; 2151 reg = <0 0x0ae94400 0 0x200>, 2152 <0 0x0ae94600 0 0x280>, 2153 <0 0x0ae94a00 0 0x1e0>; 2154 reg-names = "dsi_phy", 2155 "dsi_phy_lane", 2156 "dsi_pll"; 2157 2158 #clock-cells = <1>; 2159 #phy-cells = <0>; 2160 2161 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2162 <&rpmhcc RPMH_CXO_CLK>; 2163 clock-names = "iface", "ref"; 2164 2165 status = "disabled"; 2166 }; 2167 }; 2168 2169 dispcc: clock-controller@af00000 { 2170 compatible = "qcom,sm6350-dispcc"; 2171 reg = <0 0x0af00000 0 0x20000>; 2172 clocks = <&rpmhcc RPMH_CXO_CLK>, 2173 <&gcc GCC_DISP_GPLL0_CLK>, 2174 <&mdss_dsi0_phy 0>, 2175 <&mdss_dsi0_phy 1>, 2176 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2177 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2178 clock-names = "bi_tcxo", 2179 "gcc_disp_gpll0_clk", 2180 "dsi0_phy_pll_out_byteclk", 2181 "dsi0_phy_pll_out_dsiclk", 2182 "dp_phy_pll_link_clk", 2183 "dp_phy_pll_vco_div_clk"; 2184 #clock-cells = <1>; 2185 #reset-cells = <1>; 2186 #power-domain-cells = <1>; 2187 }; 2188 2189 pdc: interrupt-controller@b220000 { 2190 compatible = "qcom,sm6350-pdc", "qcom,pdc"; 2191 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>; 2192 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 2193 <125 63 1>, <126 655 12>, <138 139 15>; 2194 #interrupt-cells = <2>; 2195 interrupt-parent = <&intc>; 2196 interrupt-controller; 2197 }; 2198 2199 tsens0: thermal-sensor@c263000 { 2200 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 2201 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2202 <0 0x0c222000 0 0x8>; /* SROT */ 2203 #qcom,sensors = <16>; 2204 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 2205 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 2206 interrupt-names = "uplow", "critical"; 2207 #thermal-sensor-cells = <1>; 2208 }; 2209 2210 tsens1: thermal-sensor@c265000 { 2211 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 2212 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2213 <0 0x0c223000 0 0x8>; /* SROT */ 2214 #qcom,sensors = <16>; 2215 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 2216 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 2217 interrupt-names = "uplow", "critical"; 2218 #thermal-sensor-cells = <1>; 2219 }; 2220 2221 aoss_qmp: power-management@c300000 { 2222 compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp"; 2223 reg = <0 0x0c300000 0 0x1000>; 2224 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2225 IRQ_TYPE_EDGE_RISING>; 2226 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2227 2228 #clock-cells = <0>; 2229 }; 2230 2231 spmi_bus: spmi@c440000 { 2232 compatible = "qcom,spmi-pmic-arb"; 2233 reg = <0 0x0c440000 0 0x1100>, 2234 <0 0x0c600000 0 0x2000000>, 2235 <0 0x0e600000 0 0x100000>, 2236 <0 0x0e700000 0 0xa0000>, 2237 <0 0x0c40a000 0 0x26000>; 2238 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2239 interrupt-names = "periph_irq"; 2240 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2241 qcom,ee = <0>; 2242 qcom,channel = <0>; 2243 #address-cells = <2>; 2244 #size-cells = <0>; 2245 interrupt-controller; 2246 #interrupt-cells = <4>; 2247 }; 2248 2249 tlmm: pinctrl@f100000 { 2250 compatible = "qcom,sm6350-tlmm"; 2251 reg = <0 0x0f100000 0 0x300000>; 2252 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 2253 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 2254 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 2255 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 2256 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 2257 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 2258 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 2259 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 2260 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 2261 gpio-controller; 2262 #gpio-cells = <2>; 2263 interrupt-controller; 2264 #interrupt-cells = <2>; 2265 gpio-ranges = <&tlmm 0 0 157>; 2266 wakeup-parent = <&pdc>; 2267 2268 cci0_default: cci0-default-state { 2269 pins = "gpio39", "gpio40"; 2270 function = "cci_i2c"; 2271 drive-strength = <2>; 2272 bias-pull-up; 2273 }; 2274 2275 cci0_sleep: cci0-sleep-state { 2276 pins = "gpio39", "gpio40"; 2277 function = "cci_i2c"; 2278 drive-strength = <2>; 2279 bias-pull-down; 2280 }; 2281 2282 cci1_default: cci1-default-state { 2283 pins = "gpio41", "gpio42"; 2284 function = "cci_i2c"; 2285 drive-strength = <2>; 2286 bias-pull-up; 2287 }; 2288 2289 cci1_sleep: cci1-sleep-state { 2290 pins = "gpio41", "gpio42"; 2291 function = "cci_i2c"; 2292 drive-strength = <2>; 2293 bias-pull-down; 2294 }; 2295 2296 cci2_default: cci2-default-state { 2297 pins = "gpio43", "gpio44"; 2298 function = "cci_i2c"; 2299 drive-strength = <2>; 2300 bias-pull-up; 2301 }; 2302 2303 cci2_sleep: cci2-sleep-state { 2304 pins = "gpio43", "gpio44"; 2305 function = "cci_i2c"; 2306 drive-strength = <2>; 2307 bias-pull-down; 2308 }; 2309 2310 sdc2_off_state: sdc2-off-state { 2311 clk-pins { 2312 pins = "sdc2_clk"; 2313 drive-strength = <2>; 2314 bias-disable; 2315 }; 2316 2317 cmd-pins { 2318 pins = "sdc2_cmd"; 2319 drive-strength = <2>; 2320 bias-pull-up; 2321 }; 2322 2323 data-pins { 2324 pins = "sdc2_data"; 2325 drive-strength = <2>; 2326 bias-pull-up; 2327 }; 2328 }; 2329 2330 sdc2_on_state: sdc2-on-state { 2331 clk-pins { 2332 pins = "sdc2_clk"; 2333 drive-strength = <16>; 2334 bias-disable; 2335 }; 2336 2337 cmd-pins { 2338 pins = "sdc2_cmd"; 2339 drive-strength = <10>; 2340 bias-pull-up; 2341 }; 2342 2343 data-pins { 2344 pins = "sdc2_data"; 2345 drive-strength = <10>; 2346 bias-pull-up; 2347 }; 2348 }; 2349 2350 qup_uart9_default: qup-uart9-default-state { 2351 pins = "gpio25", "gpio26"; 2352 function = "qup13_f2"; 2353 drive-strength = <2>; 2354 bias-disable; 2355 }; 2356 2357 qup_i2c0_default: qup-i2c0-default-state { 2358 pins = "gpio0", "gpio1"; 2359 function = "qup00"; 2360 drive-strength = <2>; 2361 bias-pull-up; 2362 }; 2363 2364 qup_i2c2_default: qup-i2c2-default-state { 2365 pins = "gpio45", "gpio46"; 2366 function = "qup02"; 2367 drive-strength = <2>; 2368 bias-pull-up; 2369 }; 2370 2371 qup_i2c6_default: qup-i2c6-default-state { 2372 pins = "gpio13", "gpio14"; 2373 function = "qup10"; 2374 drive-strength = <2>; 2375 bias-pull-up; 2376 }; 2377 2378 qup_i2c7_default: qup-i2c7-default-state { 2379 pins = "gpio27", "gpio28"; 2380 function = "qup11"; 2381 drive-strength = <2>; 2382 bias-pull-up; 2383 }; 2384 2385 qup_i2c8_default: qup-i2c8-default-state { 2386 pins = "gpio19", "gpio20"; 2387 function = "qup12"; 2388 drive-strength = <2>; 2389 bias-pull-up; 2390 }; 2391 2392 qup_i2c10_default: qup-i2c10-default-state { 2393 pins = "gpio4", "gpio5"; 2394 function = "qup14"; 2395 drive-strength = <2>; 2396 bias-pull-up; 2397 }; 2398 2399 qup_uart1_cts: qup-uart1-cts-default-state { 2400 pins = "gpio61"; 2401 function = "qup01"; 2402 drive-strength = <2>; 2403 bias-disable; 2404 }; 2405 2406 qup_uart1_rts: qup-uart1-rts-default-state { 2407 pins = "gpio62"; 2408 function = "qup01"; 2409 drive-strength = <2>; 2410 bias-pull-down; 2411 }; 2412 2413 qup_uart1_rx: qup-uart1-rx-default-state { 2414 pins = "gpio64"; 2415 function = "qup01"; 2416 drive-strength = <2>; 2417 bias-disable; 2418 }; 2419 2420 qup_uart1_tx: qup-uart1-tx-default-state { 2421 pins = "gpio63"; 2422 function = "qup01"; 2423 drive-strength = <2>; 2424 bias-pull-up; 2425 }; 2426 }; 2427 2428 apps_smmu: iommu@15000000 { 2429 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500"; 2430 reg = <0 0x15000000 0 0x100000>; 2431 #iommu-cells = <2>; 2432 #global-interrupts = <1>; 2433 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 2434 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 2435 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 2436 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2437 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2438 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2439 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2440 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2441 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2442 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2443 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2444 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2445 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2446 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2447 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2448 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2449 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2450 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2451 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2452 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2453 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2454 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2455 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2456 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2457 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2458 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 2459 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 2460 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 2461 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 2462 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 2463 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 2464 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 2465 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 2466 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 2467 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 2468 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 2469 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 2470 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 2471 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 2472 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 2473 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 2474 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 2475 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2476 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2477 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2478 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2479 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2480 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2481 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2482 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2483 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2484 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2485 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2486 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2487 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2488 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2489 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2490 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2491 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2492 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2493 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2494 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2495 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2496 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2497 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2498 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2499 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2500 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2501 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2502 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2503 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 2504 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2505 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 2506 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 2507 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 2508 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 2509 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 2510 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 2511 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 2512 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 2513 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 2514 }; 2515 2516 intc: interrupt-controller@17a00000 { 2517 compatible = "arm,gic-v3"; 2518 #interrupt-cells = <3>; 2519 interrupt-controller; 2520 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 2521 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 2522 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; 2523 }; 2524 2525 watchdog@17c10000 { 2526 compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt"; 2527 reg = <0 0x17c10000 0 0x1000>; 2528 clocks = <&sleep_clk>; 2529 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 2530 }; 2531 2532 timer@17c20000 { 2533 compatible = "arm,armv7-timer-mem"; 2534 reg = <0x0 0x17c20000 0x0 0x1000>; 2535 clock-frequency = <19200000>; 2536 #address-cells = <1>; 2537 #size-cells = <1>; 2538 ranges = <0 0 0 0x20000000>; 2539 2540 frame@17c21000 { 2541 frame-number = <0>; 2542 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2543 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 2544 reg = <0x17c21000 0x1000>, 2545 <0x17c22000 0x1000>; 2546 }; 2547 2548 frame@17c23000 { 2549 frame-number = <1>; 2550 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2551 reg = <0x17c23000 0x1000>; 2552 status = "disabled"; 2553 }; 2554 2555 frame@17c25000 { 2556 frame-number = <2>; 2557 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2558 reg = <0x17c25000 0x1000>; 2559 status = "disabled"; 2560 }; 2561 2562 frame@17c27000 { 2563 frame-number = <3>; 2564 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2565 reg = <0x17c27000 0x1000>; 2566 status = "disabled"; 2567 }; 2568 2569 frame@17c29000 { 2570 frame-number = <4>; 2571 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2572 reg = <0x17c29000 0x1000>; 2573 status = "disabled"; 2574 }; 2575 2576 frame@17c2b000 { 2577 frame-number = <5>; 2578 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2579 reg = <0x17c2b000 0x1000>; 2580 status = "disabled"; 2581 }; 2582 2583 frame@17c2d000 { 2584 frame-number = <6>; 2585 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2586 reg = <0x17c2d000 0x1000>; 2587 status = "disabled"; 2588 }; 2589 }; 2590 2591 apps_rsc: rsc@18200000 { 2592 compatible = "qcom,rpmh-rsc"; 2593 label = "apps_rsc"; 2594 reg = <0x0 0x18200000 0x0 0x10000>, 2595 <0x0 0x18210000 0x0 0x10000>, 2596 <0x0 0x18220000 0x0 0x10000>; 2597 reg-names = "drv-0", "drv-1", "drv-2"; 2598 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2599 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2600 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 2601 qcom,tcs-offset = <0xd00>; 2602 qcom,drv-id = <2>; 2603 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 2604 <WAKE_TCS 3>, <CONTROL_TCS 1>; 2605 power-domains = <&CLUSTER_PD>; 2606 2607 rpmhcc: clock-controller { 2608 compatible = "qcom,sm6350-rpmh-clk"; 2609 #clock-cells = <1>; 2610 clock-names = "xo"; 2611 clocks = <&xo_board>; 2612 }; 2613 2614 rpmhpd: power-controller { 2615 compatible = "qcom,sm6350-rpmhpd"; 2616 #power-domain-cells = <1>; 2617 operating-points-v2 = <&rpmhpd_opp_table>; 2618 2619 rpmhpd_opp_table: opp-table { 2620 compatible = "operating-points-v2"; 2621 2622 rpmhpd_opp_ret: opp1 { 2623 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 2624 }; 2625 2626 rpmhpd_opp_min_svs: opp2 { 2627 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2628 }; 2629 2630 rpmhpd_opp_low_svs: opp3 { 2631 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2632 }; 2633 2634 rpmhpd_opp_svs: opp4 { 2635 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2636 }; 2637 2638 rpmhpd_opp_svs_l1: opp5 { 2639 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2640 }; 2641 2642 rpmhpd_opp_nom: opp6 { 2643 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2644 }; 2645 2646 rpmhpd_opp_nom_l1: opp7 { 2647 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2648 }; 2649 2650 rpmhpd_opp_nom_l2: opp8 { 2651 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 2652 }; 2653 2654 rpmhpd_opp_turbo: opp9 { 2655 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2656 }; 2657 2658 rpmhpd_opp_turbo_l1: opp10 { 2659 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2660 }; 2661 }; 2662 }; 2663 2664 apps_bcm_voter: bcm-voter { 2665 compatible = "qcom,bcm-voter"; 2666 }; 2667 }; 2668 2669 osm_l3: interconnect@18321000 { 2670 compatible = "qcom,sm6350-osm-l3", "qcom,osm-l3"; 2671 reg = <0x0 0x18321000 0x0 0x1000>; 2672 2673 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2674 clock-names = "xo", "alternate"; 2675 2676 #interconnect-cells = <1>; 2677 }; 2678 2679 cpufreq_hw: cpufreq@18323000 { 2680 compatible = "qcom,sm6350-cpufreq-hw", "qcom,cpufreq-hw"; 2681 reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>; 2682 reg-names = "freq-domain0", "freq-domain1"; 2683 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2684 clock-names = "xo", "alternate"; 2685 2686 #freq-domain-cells = <1>; 2687 #clock-cells = <1>; 2688 }; 2689 2690 wifi: wifi@18800000 { 2691 compatible = "qcom,wcn3990-wifi"; 2692 reg = <0 0x18800000 0 0x800000>; 2693 reg-names = "membase"; 2694 memory-region = <&wlan_fw_mem>; 2695 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 2696 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 2697 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 2698 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 2699 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2700 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 2701 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 2702 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2703 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2704 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2705 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2706 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 2707 iommus = <&apps_smmu 0x20 0x1>; 2708 qcom,msa-fixed-perm; 2709 status = "disabled"; 2710 }; 2711 }; 2712 2713 thermal-zones { 2714 aoss0-thermal { 2715 polling-delay-passive = <0>; 2716 polling-delay = <0>; 2717 2718 thermal-sensors = <&tsens0 0>; 2719 2720 trips { 2721 aoss0-crit { 2722 temperature = <125000>; 2723 hysteresis = <0>; 2724 type = "critical"; 2725 }; 2726 }; 2727 }; 2728 2729 aoss1-thermal { 2730 polling-delay-passive = <0>; 2731 polling-delay = <0>; 2732 2733 thermal-sensors = <&tsens1 0>; 2734 2735 trips { 2736 aoss1-crit { 2737 temperature = <125000>; 2738 hysteresis = <0>; 2739 type = "critical"; 2740 }; 2741 }; 2742 }; 2743 2744 audio-thermal { 2745 polling-delay-passive = <0>; 2746 polling-delay = <0>; 2747 2748 thermal-sensors = <&tsens1 2>; 2749 2750 trips { 2751 audio-crit { 2752 temperature = <125000>; 2753 hysteresis = <0>; 2754 type = "critical"; 2755 }; 2756 }; 2757 }; 2758 2759 camera-thermal { 2760 polling-delay-passive = <0>; 2761 polling-delay = <0>; 2762 2763 thermal-sensors = <&tsens1 5>; 2764 2765 trips { 2766 camera-crit { 2767 temperature = <125000>; 2768 hysteresis = <0>; 2769 type = "critical"; 2770 }; 2771 }; 2772 }; 2773 2774 cpu0-thermal { 2775 polling-delay-passive = <0>; 2776 polling-delay = <0>; 2777 2778 thermal-sensors = <&tsens0 1>; 2779 2780 trips { 2781 cpu0_alert0: trip-point0 { 2782 temperature = <95000>; 2783 hysteresis = <2000>; 2784 type = "passive"; 2785 }; 2786 2787 cpu0-crit { 2788 temperature = <115000>; 2789 hysteresis = <0>; 2790 type = "critical"; 2791 }; 2792 }; 2793 2794 cooling-maps { 2795 map0 { 2796 trip = <&cpu0_alert0>; 2797 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2798 }; 2799 }; 2800 }; 2801 2802 cpu1-thermal { 2803 polling-delay-passive = <0>; 2804 polling-delay = <0>; 2805 2806 thermal-sensors = <&tsens0 2>; 2807 2808 trips { 2809 cpu1_alert0: trip-point0 { 2810 temperature = <95000>; 2811 hysteresis = <2000>; 2812 type = "passive"; 2813 }; 2814 2815 cpu1-crit { 2816 temperature = <115000>; 2817 hysteresis = <0>; 2818 type = "critical"; 2819 }; 2820 }; 2821 2822 cooling-maps { 2823 map0 { 2824 trip = <&cpu1_alert0>; 2825 cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2826 }; 2827 }; 2828 }; 2829 2830 cpu2-thermal { 2831 polling-delay-passive = <0>; 2832 polling-delay = <0>; 2833 2834 thermal-sensors = <&tsens0 3>; 2835 2836 trips { 2837 cpu2_alert0: trip-point0 { 2838 temperature = <95000>; 2839 hysteresis = <2000>; 2840 type = "passive"; 2841 }; 2842 2843 cpu2-crit { 2844 temperature = <115000>; 2845 hysteresis = <0>; 2846 type = "critical"; 2847 }; 2848 }; 2849 2850 cooling-maps { 2851 map0 { 2852 trip = <&cpu2_alert0>; 2853 cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2854 }; 2855 }; 2856 }; 2857 2858 cpu3-thermal { 2859 polling-delay-passive = <0>; 2860 polling-delay = <0>; 2861 2862 thermal-sensors = <&tsens0 4>; 2863 2864 trips { 2865 cpu3_alert0: trip-point0 { 2866 temperature = <95000>; 2867 hysteresis = <2000>; 2868 type = "passive"; 2869 }; 2870 2871 cpu3-crit { 2872 temperature = <115000>; 2873 hysteresis = <0>; 2874 type = "critical"; 2875 }; 2876 }; 2877 2878 cooling-maps { 2879 map0 { 2880 trip = <&cpu3_alert0>; 2881 cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2882 }; 2883 }; 2884 }; 2885 2886 cpu4-thermal { 2887 polling-delay-passive = <0>; 2888 polling-delay = <0>; 2889 2890 thermal-sensors = <&tsens0 5>; 2891 2892 trips { 2893 cpu4_alert0: trip-point0 { 2894 temperature = <95000>; 2895 hysteresis = <2000>; 2896 type = "passive"; 2897 }; 2898 2899 cpu4-crit { 2900 temperature = <115000>; 2901 hysteresis = <0>; 2902 type = "critical"; 2903 }; 2904 }; 2905 2906 cooling-maps { 2907 map0 { 2908 trip = <&cpu4_alert0>; 2909 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2910 }; 2911 }; 2912 }; 2913 2914 cpu5-thermal { 2915 polling-delay-passive = <0>; 2916 polling-delay = <0>; 2917 2918 thermal-sensors = <&tsens0 6>; 2919 2920 trips { 2921 cpu5_alert0: trip-point0 { 2922 temperature = <95000>; 2923 hysteresis = <2000>; 2924 type = "passive"; 2925 }; 2926 2927 cpu5-crit { 2928 temperature = <115000>; 2929 hysteresis = <0>; 2930 type = "critical"; 2931 }; 2932 }; 2933 2934 cooling-maps { 2935 map0 { 2936 trip = <&cpu5_alert0>; 2937 cooling-device = <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2938 }; 2939 }; 2940 }; 2941 2942 cpu6-left-thermal { 2943 polling-delay-passive = <0>; 2944 polling-delay = <0>; 2945 2946 thermal-sensors = <&tsens0 9>; 2947 2948 trips { 2949 cpu6_left_alert0: trip-point0 { 2950 temperature = <95000>; 2951 hysteresis = <2000>; 2952 type = "passive"; 2953 }; 2954 2955 cpu6-left-crit { 2956 temperature = <115000>; 2957 hysteresis = <0>; 2958 type = "critical"; 2959 }; 2960 }; 2961 2962 cooling-maps { 2963 map0 { 2964 trip = <&cpu6_left_alert0>; 2965 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2966 }; 2967 }; 2968 }; 2969 2970 cpu6-right-thermal { 2971 polling-delay-passive = <0>; 2972 polling-delay = <0>; 2973 2974 thermal-sensors = <&tsens0 10>; 2975 2976 trips { 2977 cpu6_right_alert0: trip-point0 { 2978 temperature = <95000>; 2979 hysteresis = <2000>; 2980 type = "passive"; 2981 }; 2982 2983 cpu6-right-crit { 2984 temperature = <115000>; 2985 hysteresis = <0>; 2986 type = "critical"; 2987 }; 2988 }; 2989 2990 cooling-maps { 2991 map0 { 2992 trip = <&cpu6_right_alert0>; 2993 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2994 }; 2995 }; 2996 }; 2997 2998 cpu7-left-thermal { 2999 polling-delay-passive = <0>; 3000 polling-delay = <0>; 3001 3002 thermal-sensors = <&tsens0 11>; 3003 3004 trips { 3005 cpu7_left_alert0: trip-point0 { 3006 temperature = <95000>; 3007 hysteresis = <2000>; 3008 type = "passive"; 3009 }; 3010 3011 cpu7-left-crit { 3012 temperature = <115000>; 3013 hysteresis = <0>; 3014 type = "critical"; 3015 }; 3016 }; 3017 3018 cooling-maps { 3019 map0 { 3020 trip = <&cpu7_left_alert0>; 3021 cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3022 }; 3023 }; 3024 }; 3025 3026 cpu7-right-thermal { 3027 polling-delay-passive = <0>; 3028 polling-delay = <0>; 3029 3030 thermal-sensors = <&tsens0 12>; 3031 3032 trips { 3033 cpu7_right_alert0: trip-point0 { 3034 temperature = <95000>; 3035 hysteresis = <2000>; 3036 type = "passive"; 3037 }; 3038 3039 cpu7-right-crit { 3040 temperature = <115000>; 3041 hysteresis = <0>; 3042 type = "critical"; 3043 }; 3044 }; 3045 3046 cooling-maps { 3047 map0 { 3048 trip = <&cpu7_right_alert0>; 3049 cooling-device = <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3050 }; 3051 }; 3052 }; 3053 3054 cpuss0-thermal { 3055 polling-delay-passive = <0>; 3056 polling-delay = <0>; 3057 3058 thermal-sensors = <&tsens0 7>; 3059 3060 trips { 3061 cpuss0-crit { 3062 temperature = <125000>; 3063 hysteresis = <0>; 3064 type = "critical"; 3065 }; 3066 }; 3067 }; 3068 3069 cpuss1-thermal { 3070 polling-delay-passive = <0>; 3071 polling-delay = <0>; 3072 3073 thermal-sensors = <&tsens0 8>; 3074 3075 trips { 3076 cpuss1-crit { 3077 temperature = <125000>; 3078 hysteresis = <0>; 3079 type = "critical"; 3080 }; 3081 }; 3082 }; 3083 3084 cwlan-thermal { 3085 polling-delay-passive = <0>; 3086 polling-delay = <0>; 3087 3088 thermal-sensors = <&tsens1 1>; 3089 3090 trips { 3091 cwlan-crit { 3092 temperature = <125000>; 3093 hysteresis = <0>; 3094 type = "critical"; 3095 }; 3096 }; 3097 }; 3098 3099 ddr-thermal { 3100 polling-delay-passive = <0>; 3101 polling-delay = <0>; 3102 3103 thermal-sensors = <&tsens1 3>; 3104 3105 trips { 3106 ddr-crit { 3107 temperature = <125000>; 3108 hysteresis = <0>; 3109 type = "critical"; 3110 }; 3111 }; 3112 }; 3113 3114 gpuss0-thermal { 3115 polling-delay-passive = <0>; 3116 polling-delay = <0>; 3117 3118 thermal-sensors = <&tsens0 13>; 3119 3120 trips { 3121 gpuss0_alert0: trip-point0 { 3122 temperature = <95000>; 3123 hysteresis = <2000>; 3124 type = "passive"; 3125 }; 3126 3127 gpuss0-crit { 3128 temperature = <115000>; 3129 hysteresis = <0>; 3130 type = "critical"; 3131 }; 3132 }; 3133 3134 cooling-maps { 3135 map0 { 3136 trip = <&gpuss0_alert0>; 3137 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3138 }; 3139 }; 3140 }; 3141 3142 gpuss1-thermal { 3143 polling-delay-passive = <0>; 3144 polling-delay = <0>; 3145 3146 thermal-sensors = <&tsens0 14>; 3147 3148 trips { 3149 gpuss1_alert0: trip-point0 { 3150 temperature = <95000>; 3151 hysteresis = <2000>; 3152 type = "passive"; 3153 }; 3154 3155 gpuss1-crit { 3156 temperature = <115000>; 3157 hysteresis = <0>; 3158 type = "critical"; 3159 }; 3160 }; 3161 3162 cooling-maps { 3163 map0 { 3164 trip = <&gpuss1_alert0>; 3165 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3166 }; 3167 }; 3168 }; 3169 3170 modem-core0-thermal { 3171 polling-delay-passive = <0>; 3172 polling-delay = <0>; 3173 3174 thermal-sensors = <&tsens1 6>; 3175 3176 trips { 3177 modem-core0-crit { 3178 temperature = <125000>; 3179 hysteresis = <0>; 3180 type = "critical"; 3181 }; 3182 }; 3183 }; 3184 3185 modem-core1-thermal { 3186 polling-delay-passive = <0>; 3187 polling-delay = <0>; 3188 3189 thermal-sensors = <&tsens1 7>; 3190 3191 trips { 3192 modem-core1-crit { 3193 temperature = <125000>; 3194 hysteresis = <0>; 3195 type = "critical"; 3196 }; 3197 }; 3198 }; 3199 3200 modem-scl-thermal { 3201 polling-delay-passive = <0>; 3202 polling-delay = <0>; 3203 3204 thermal-sensors = <&tsens1 9>; 3205 3206 trips { 3207 modem-scl-crit { 3208 temperature = <125000>; 3209 hysteresis = <0>; 3210 type = "critical"; 3211 }; 3212 }; 3213 }; 3214 3215 modem-vec-thermal { 3216 polling-delay-passive = <0>; 3217 polling-delay = <0>; 3218 3219 thermal-sensors = <&tsens1 8>; 3220 3221 trips { 3222 modem-vec-crit { 3223 temperature = <125000>; 3224 hysteresis = <0>; 3225 type = "critical"; 3226 }; 3227 }; 3228 }; 3229 3230 npu-thermal { 3231 polling-delay-passive = <0>; 3232 polling-delay = <0>; 3233 3234 thermal-sensors = <&tsens1 10>; 3235 3236 trips { 3237 npu-crit { 3238 temperature = <125000>; 3239 hysteresis = <0>; 3240 type = "critical"; 3241 }; 3242 }; 3243 }; 3244 3245 q6-hvx-thermal { 3246 polling-delay-passive = <0>; 3247 polling-delay = <0>; 3248 3249 thermal-sensors = <&tsens1 4>; 3250 3251 trips { 3252 q6-hvx-crit { 3253 temperature = <125000>; 3254 hysteresis = <0>; 3255 type = "critical"; 3256 }; 3257 }; 3258 }; 3259 3260 video-thermal { 3261 polling-delay-passive = <0>; 3262 polling-delay = <0>; 3263 3264 thermal-sensors = <&tsens1 11>; 3265 3266 trips { 3267 video-crit { 3268 temperature = <125000>; 3269 hysteresis = <0>; 3270 type = "critical"; 3271 }; 3272 }; 3273 }; 3274 }; 3275 3276 timer { 3277 compatible = "arm,armv8-timer"; 3278 clock-frequency = <19200000>; 3279 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3280 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3281 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3282 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 3283 }; 3284}; 3285