1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> 4 * Copyright (c) 2022, Luca Weiss <luca.weiss@fairphone.com> 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sm6350.h> 8#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 9#include <dt-bindings/clock/qcom,gcc-sm6350.h> 10#include <dt-bindings/clock/qcom,gpucc-sm6350.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,sm6350-camcc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interconnect/qcom,icc.h> 16#include <dt-bindings/interconnect/qcom,osm-l3.h> 17#include <dt-bindings/interconnect/qcom,sm6350.h> 18#include <dt-bindings/interrupt-controller/arm-gic.h> 19#include <dt-bindings/mailbox/qcom-ipcc.h> 20#include <dt-bindings/phy/phy-qcom-qmp.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/soc/qcom,apr.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 25#include <dt-bindings/thermal/thermal.h> 26 27/ { 28 interrupt-parent = <&intc>; 29 #address-cells = <2>; 30 #size-cells = <2>; 31 32 clocks { 33 xo_board: xo-board { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <76800000>; 37 clock-output-names = "xo_board"; 38 }; 39 40 sleep_clk: sleep-clk { 41 compatible = "fixed-clock"; 42 clock-frequency = <32764>; 43 #clock-cells = <0>; 44 }; 45 }; 46 47 cpus { 48 #address-cells = <2>; 49 #size-cells = <0>; 50 51 cpu0: cpu@0 { 52 device_type = "cpu"; 53 compatible = "qcom,kryo560"; 54 reg = <0x0 0x0>; 55 clocks = <&cpufreq_hw 0>; 56 enable-method = "psci"; 57 capacity-dmips-mhz = <1024>; 58 dynamic-power-coefficient = <100>; 59 next-level-cache = <&l2_0>; 60 qcom,freq-domain = <&cpufreq_hw 0>; 61 operating-points-v2 = <&cpu0_opp_table>; 62 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 63 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 64 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 65 power-domains = <&cpu_pd0>; 66 power-domain-names = "psci"; 67 #cooling-cells = <2>; 68 l2_0: l2-cache { 69 compatible = "cache"; 70 cache-level = <2>; 71 cache-unified; 72 next-level-cache = <&l3_0>; 73 l3_0: l3-cache { 74 compatible = "cache"; 75 cache-level = <3>; 76 cache-unified; 77 }; 78 }; 79 }; 80 81 cpu1: cpu@100 { 82 device_type = "cpu"; 83 compatible = "qcom,kryo560"; 84 reg = <0x0 0x100>; 85 clocks = <&cpufreq_hw 0>; 86 enable-method = "psci"; 87 capacity-dmips-mhz = <1024>; 88 dynamic-power-coefficient = <100>; 89 next-level-cache = <&l2_100>; 90 qcom,freq-domain = <&cpufreq_hw 0>; 91 operating-points-v2 = <&cpu0_opp_table>; 92 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 93 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 94 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 95 power-domains = <&cpu_pd1>; 96 power-domain-names = "psci"; 97 #cooling-cells = <2>; 98 l2_100: l2-cache { 99 compatible = "cache"; 100 cache-level = <2>; 101 cache-unified; 102 next-level-cache = <&l3_0>; 103 }; 104 }; 105 106 cpu2: cpu@200 { 107 device_type = "cpu"; 108 compatible = "qcom,kryo560"; 109 reg = <0x0 0x200>; 110 clocks = <&cpufreq_hw 0>; 111 enable-method = "psci"; 112 capacity-dmips-mhz = <1024>; 113 dynamic-power-coefficient = <100>; 114 next-level-cache = <&l2_200>; 115 qcom,freq-domain = <&cpufreq_hw 0>; 116 operating-points-v2 = <&cpu0_opp_table>; 117 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 118 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 119 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 120 power-domains = <&cpu_pd2>; 121 power-domain-names = "psci"; 122 #cooling-cells = <2>; 123 l2_200: l2-cache { 124 compatible = "cache"; 125 cache-level = <2>; 126 cache-unified; 127 next-level-cache = <&l3_0>; 128 }; 129 }; 130 131 cpu3: cpu@300 { 132 device_type = "cpu"; 133 compatible = "qcom,kryo560"; 134 reg = <0x0 0x300>; 135 clocks = <&cpufreq_hw 0>; 136 enable-method = "psci"; 137 capacity-dmips-mhz = <1024>; 138 dynamic-power-coefficient = <100>; 139 next-level-cache = <&l2_300>; 140 qcom,freq-domain = <&cpufreq_hw 0>; 141 operating-points-v2 = <&cpu0_opp_table>; 142 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 143 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 144 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 145 power-domains = <&cpu_pd3>; 146 power-domain-names = "psci"; 147 #cooling-cells = <2>; 148 l2_300: l2-cache { 149 compatible = "cache"; 150 cache-level = <2>; 151 cache-unified; 152 next-level-cache = <&l3_0>; 153 }; 154 }; 155 156 cpu4: cpu@400 { 157 device_type = "cpu"; 158 compatible = "qcom,kryo560"; 159 reg = <0x0 0x400>; 160 clocks = <&cpufreq_hw 0>; 161 enable-method = "psci"; 162 capacity-dmips-mhz = <1024>; 163 dynamic-power-coefficient = <100>; 164 next-level-cache = <&l2_400>; 165 qcom,freq-domain = <&cpufreq_hw 0>; 166 operating-points-v2 = <&cpu0_opp_table>; 167 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 168 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 169 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 170 power-domains = <&cpu_pd4>; 171 power-domain-names = "psci"; 172 #cooling-cells = <2>; 173 l2_400: l2-cache { 174 compatible = "cache"; 175 cache-level = <2>; 176 cache-unified; 177 next-level-cache = <&l3_0>; 178 }; 179 }; 180 181 cpu5: cpu@500 { 182 device_type = "cpu"; 183 compatible = "qcom,kryo560"; 184 reg = <0x0 0x500>; 185 clocks = <&cpufreq_hw 0>; 186 enable-method = "psci"; 187 capacity-dmips-mhz = <1024>; 188 dynamic-power-coefficient = <100>; 189 next-level-cache = <&l2_500>; 190 qcom,freq-domain = <&cpufreq_hw 0>; 191 operating-points-v2 = <&cpu0_opp_table>; 192 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 193 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 194 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 195 power-domains = <&cpu_pd5>; 196 power-domain-names = "psci"; 197 #cooling-cells = <2>; 198 l2_500: l2-cache { 199 compatible = "cache"; 200 cache-level = <2>; 201 cache-unified; 202 next-level-cache = <&l3_0>; 203 }; 204 }; 205 206 cpu6: cpu@600 { 207 device_type = "cpu"; 208 compatible = "qcom,kryo560"; 209 reg = <0x0 0x600>; 210 clocks = <&cpufreq_hw 1>; 211 enable-method = "psci"; 212 capacity-dmips-mhz = <1894>; 213 dynamic-power-coefficient = <703>; 214 next-level-cache = <&l2_600>; 215 qcom,freq-domain = <&cpufreq_hw 1>; 216 operating-points-v2 = <&cpu6_opp_table>; 217 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 218 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 219 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 220 power-domains = <&cpu_pd6>; 221 power-domain-names = "psci"; 222 #cooling-cells = <2>; 223 l2_600: l2-cache { 224 compatible = "cache"; 225 cache-level = <2>; 226 cache-unified; 227 next-level-cache = <&l3_0>; 228 }; 229 }; 230 231 cpu7: cpu@700 { 232 device_type = "cpu"; 233 compatible = "qcom,kryo560"; 234 reg = <0x0 0x700>; 235 clocks = <&cpufreq_hw 1>; 236 enable-method = "psci"; 237 capacity-dmips-mhz = <1894>; 238 dynamic-power-coefficient = <703>; 239 next-level-cache = <&l2_700>; 240 qcom,freq-domain = <&cpufreq_hw 1>; 241 operating-points-v2 = <&cpu6_opp_table>; 242 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 243 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 244 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 245 power-domains = <&cpu_pd7>; 246 power-domain-names = "psci"; 247 #cooling-cells = <2>; 248 l2_700: l2-cache { 249 compatible = "cache"; 250 cache-level = <2>; 251 cache-unified; 252 next-level-cache = <&l3_0>; 253 }; 254 }; 255 256 cpu-map { 257 cluster0 { 258 core0 { 259 cpu = <&cpu0>; 260 }; 261 262 core1 { 263 cpu = <&cpu1>; 264 }; 265 266 core2 { 267 cpu = <&cpu2>; 268 }; 269 270 core3 { 271 cpu = <&cpu3>; 272 }; 273 274 core4 { 275 cpu = <&cpu4>; 276 }; 277 278 core5 { 279 cpu = <&cpu5>; 280 }; 281 282 core6 { 283 cpu = <&cpu6>; 284 }; 285 286 core7 { 287 cpu = <&cpu7>; 288 }; 289 }; 290 }; 291 292 domain-idle-states { 293 cluster_sleep_pc: cluster-sleep-0 { 294 compatible = "domain-idle-state"; 295 arm,psci-suspend-param = <0x41000044>; 296 entry-latency-us = <2752>; 297 exit-latency-us = <3048>; 298 min-residency-us = <6118>; 299 }; 300 301 cluster_sleep_cx_ret: cluster-sleep-1 { 302 compatible = "domain-idle-state"; 303 arm,psci-suspend-param = <0x41001244>; 304 entry-latency-us = <3638>; 305 exit-latency-us = <4562>; 306 min-residency-us = <8467>; 307 }; 308 309 cluster_aoss_sleep: cluster-sleep-2 { 310 compatible = "domain-idle-state"; 311 arm,psci-suspend-param = <0x4100b244>; 312 entry-latency-us = <3263>; 313 exit-latency-us = <6562>; 314 min-residency-us = <9987>; 315 }; 316 }; 317 318 cpu_idle_states: idle-states { 319 entry-method = "psci"; 320 321 little_cpu_sleep_0: cpu-sleep-0-0 { 322 compatible = "arm,idle-state"; 323 idle-state-name = "little-power-collapse"; 324 arm,psci-suspend-param = <0x40000003>; 325 entry-latency-us = <549>; 326 exit-latency-us = <901>; 327 min-residency-us = <1774>; 328 local-timer-stop; 329 }; 330 331 little_cpu_sleep_1: cpu-sleep-0-1 { 332 compatible = "arm,idle-state"; 333 idle-state-name = "little-rail-power-collapse"; 334 arm,psci-suspend-param = <0x40000004>; 335 entry-latency-us = <702>; 336 exit-latency-us = <915>; 337 min-residency-us = <4001>; 338 local-timer-stop; 339 }; 340 341 big_cpu_sleep_0: cpu-sleep-1-0 { 342 compatible = "arm,idle-state"; 343 idle-state-name = "big-power-collapse"; 344 arm,psci-suspend-param = <0x40000003>; 345 entry-latency-us = <523>; 346 exit-latency-us = <1244>; 347 min-residency-us = <2207>; 348 local-timer-stop; 349 }; 350 351 big_cpu_sleep_1: cpu-sleep-1-1 { 352 compatible = "arm,idle-state"; 353 idle-state-name = "big-rail-power-collapse"; 354 arm,psci-suspend-param = <0x40000004>; 355 entry-latency-us = <526>; 356 exit-latency-us = <1854>; 357 min-residency-us = <5555>; 358 local-timer-stop; 359 }; 360 }; 361 }; 362 363 firmware { 364 scm: scm { 365 compatible = "qcom,scm-sm6350", "qcom,scm"; 366 #reset-cells = <1>; 367 }; 368 }; 369 370 memory@80000000 { 371 device_type = "memory"; 372 /* We expect the bootloader to fill in the size */ 373 reg = <0x0 0x80000000 0x0 0x0>; 374 }; 375 376 cpu0_opp_table: opp-table-cpu0 { 377 compatible = "operating-points-v2"; 378 opp-shared; 379 380 opp-300000000 { 381 opp-hz = /bits/ 64 <300000000>; 382 /* DDR: 4-wide, 2 channels, double data rate, L3: 16-wide, 2 channels */ 383 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; 384 }; 385 386 opp-576000000 { 387 opp-hz = /bits/ 64 <576000000>; 388 opp-peak-kBps = <(547000 * 4 * 2 * 2) (556800 * 16 * 2)>; 389 }; 390 391 opp-768000000 { 392 opp-hz = /bits/ 64 <768000000>; 393 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; 394 }; 395 396 opp-1017600000 { 397 opp-hz = /bits/ 64 <1017600000>; 398 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; 399 }; 400 401 opp-1248000000 { 402 opp-hz = /bits/ 64 <1248000000>; 403 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; 404 }; 405 406 opp-1324800000 { 407 opp-hz = /bits/ 64 <1324800000>; 408 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1286400 * 16 * 2)>; 409 }; 410 411 opp-1516800000 { 412 opp-hz = /bits/ 64 <1516800000>; 413 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 414 }; 415 416 opp-1612800000 { 417 opp-hz = /bits/ 64 <1612800000>; 418 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 419 }; 420 421 opp-1708800000 { 422 opp-hz = /bits/ 64 <1708800000>; 423 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 424 }; 425 }; 426 427 cpu6_opp_table: opp-table-cpu6 { 428 compatible = "operating-points-v2"; 429 opp-shared; 430 431 opp-300000000 { 432 opp-hz = /bits/ 64 <300000000>; 433 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; 434 }; 435 436 opp-787200000 { 437 opp-hz = /bits/ 64 <787200000>; 438 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; 439 }; 440 441 opp-979200000 { 442 opp-hz = /bits/ 64 <979200000>; 443 opp-peak-kBps = <(768000 * 4 * 2 * 2) (940800 * 16 * 2)>; 444 }; 445 446 opp-1036800000 { 447 opp-hz = /bits/ 64 <1036800000>; 448 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; 449 }; 450 451 opp-1248000000 { 452 opp-hz = /bits/ 64 <1248000000>; 453 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; 454 }; 455 456 opp-1401600000 { 457 opp-hz = /bits/ 64 <1401600000>; 458 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1401600 * 16 * 2)>; 459 }; 460 461 opp-1555200000 { 462 opp-hz = /bits/ 64 <1555200000>; 463 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 464 }; 465 466 opp-1766400000 { 467 opp-hz = /bits/ 64 <1766400000>; 468 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 469 }; 470 471 opp-1900800000 { 472 opp-hz = /bits/ 64 <1900800000>; 473 opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 474 }; 475 476 opp-2073600000 { 477 opp-hz = /bits/ 64 <2073600000>; 478 opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 479 }; 480 }; 481 482 qup_opp_table: opp-table-qup { 483 compatible = "operating-points-v2"; 484 485 opp-75000000 { 486 opp-hz = /bits/ 64 <75000000>; 487 required-opps = <&rpmhpd_opp_low_svs>; 488 }; 489 490 opp-100000000 { 491 opp-hz = /bits/ 64 <100000000>; 492 required-opps = <&rpmhpd_opp_svs>; 493 }; 494 495 opp-128000000 { 496 opp-hz = /bits/ 64 <128000000>; 497 required-opps = <&rpmhpd_opp_nom>; 498 }; 499 }; 500 501 pmu { 502 compatible = "arm,armv8-pmuv3"; 503 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>; 504 }; 505 506 psci { 507 compatible = "arm,psci-1.0"; 508 method = "smc"; 509 510 cpu_pd0: power-domain-cpu0 { 511 #power-domain-cells = <0>; 512 power-domains = <&cluster_pd>; 513 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 514 }; 515 516 cpu_pd1: power-domain-cpu1 { 517 #power-domain-cells = <0>; 518 power-domains = <&cluster_pd>; 519 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 520 }; 521 522 cpu_pd2: power-domain-cpu2 { 523 #power-domain-cells = <0>; 524 power-domains = <&cluster_pd>; 525 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 526 }; 527 528 cpu_pd3: power-domain-cpu3 { 529 #power-domain-cells = <0>; 530 power-domains = <&cluster_pd>; 531 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 532 }; 533 534 cpu_pd4: power-domain-cpu4 { 535 #power-domain-cells = <0>; 536 power-domains = <&cluster_pd>; 537 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 538 }; 539 540 cpu_pd5: power-domain-cpu5 { 541 #power-domain-cells = <0>; 542 power-domains = <&cluster_pd>; 543 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 544 }; 545 546 cpu_pd6: power-domain-cpu6 { 547 #power-domain-cells = <0>; 548 power-domains = <&cluster_pd>; 549 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 550 }; 551 552 cpu_pd7: power-domain-cpu7 { 553 #power-domain-cells = <0>; 554 power-domains = <&cluster_pd>; 555 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 556 }; 557 558 cluster_pd: power-domain-cpu-cluster0 { 559 #power-domain-cells = <0>; 560 domain-idle-states = <&cluster_sleep_pc 561 &cluster_sleep_cx_ret 562 &cluster_aoss_sleep>; 563 }; 564 }; 565 566 reserved_memory: reserved-memory { 567 #address-cells = <2>; 568 #size-cells = <2>; 569 ranges; 570 571 hyp_mem: memory@80000000 { 572 reg = <0x0 0x80000000 0x0 0x600000>; 573 no-map; 574 }; 575 576 xbl_aop_mem: memory@80700000 { 577 reg = <0x0 0x80700000 0x0 0x160000>; 578 no-map; 579 }; 580 581 cmd_db: memory@80860000 { 582 compatible = "qcom,cmd-db"; 583 reg = <0x0 0x80860000 0x0 0x20000>; 584 no-map; 585 }; 586 587 sec_apps_mem: memory@808ff000 { 588 reg = <0x0 0x808ff000 0x0 0x1000>; 589 no-map; 590 }; 591 592 smem_mem: memory@80900000 { 593 reg = <0x0 0x80900000 0x0 0x200000>; 594 no-map; 595 }; 596 597 cdsp_sec_mem: memory@80b00000 { 598 reg = <0x0 0x80b00000 0x0 0x1e00000>; 599 no-map; 600 }; 601 602 pil_camera_mem: memory@86000000 { 603 reg = <0x0 0x86000000 0x0 0x500000>; 604 no-map; 605 }; 606 607 pil_npu_mem: memory@86500000 { 608 reg = <0x0 0x86500000 0x0 0x500000>; 609 no-map; 610 }; 611 612 pil_video_mem: memory@86a00000 { 613 reg = <0x0 0x86a00000 0x0 0x500000>; 614 no-map; 615 }; 616 617 pil_cdsp_mem: memory@86f00000 { 618 reg = <0x0 0x86f00000 0x0 0x1e00000>; 619 no-map; 620 }; 621 622 pil_adsp_mem: memory@88d00000 { 623 reg = <0x0 0x88d00000 0x0 0x2800000>; 624 no-map; 625 }; 626 627 wlan_fw_mem: memory@8b500000 { 628 reg = <0x0 0x8b500000 0x0 0x200000>; 629 no-map; 630 }; 631 632 pil_ipa_fw_mem: memory@8b700000 { 633 reg = <0x0 0x8b700000 0x0 0x10000>; 634 no-map; 635 }; 636 637 pil_ipa_gsi_mem: memory@8b710000 { 638 reg = <0x0 0x8b710000 0x0 0x5400>; 639 no-map; 640 }; 641 642 pil_modem_mem: memory@8b800000 { 643 reg = <0x0 0x8b800000 0x0 0xf800000>; 644 no-map; 645 }; 646 647 cont_splash_memory: memory@a0000000 { 648 reg = <0x0 0xa0000000 0x0 0x2300000>; 649 no-map; 650 }; 651 652 dfps_data_memory: memory@a2300000 { 653 reg = <0x0 0xa2300000 0x0 0x100000>; 654 no-map; 655 }; 656 657 removed_region: memory@c0000000 { 658 reg = <0x0 0xc0000000 0x0 0x3900000>; 659 no-map; 660 }; 661 662 pil_gpu_mem: memory@f0d00000 { 663 reg = <0x0 0xf0d00000 0x0 0x1000>; 664 no-map; 665 }; 666 667 debug_region: memory@ffb00000 { 668 reg = <0x0 0xffb00000 0x0 0xc0000>; 669 no-map; 670 }; 671 672 last_log_region: memory@ffbc0000 { 673 reg = <0x0 0xffbc0000 0x0 0x40000>; 674 no-map; 675 }; 676 677 ramoops: ramoops@ffc00000 { 678 compatible = "ramoops"; 679 reg = <0x0 0xffc00000 0x0 0x100000>; 680 record-size = <0x1000>; 681 console-size = <0x40000>; 682 pmsg-size = <0x20000>; 683 ecc-size = <16>; 684 no-map; 685 }; 686 687 cmdline_region: memory@ffd00000 { 688 reg = <0x0 0xffd00000 0x0 0x1000>; 689 no-map; 690 }; 691 }; 692 693 smem { 694 compatible = "qcom,smem"; 695 memory-region = <&smem_mem>; 696 hwlocks = <&tcsr_mutex 3>; 697 }; 698 699 smp2p-adsp { 700 compatible = "qcom,smp2p"; 701 qcom,smem = <443>, <429>; 702 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 703 IPCC_MPROC_SIGNAL_SMP2P 704 IRQ_TYPE_EDGE_RISING>; 705 mboxes = <&ipcc IPCC_CLIENT_LPASS 706 IPCC_MPROC_SIGNAL_SMP2P>; 707 708 qcom,local-pid = <0>; 709 qcom,remote-pid = <2>; 710 711 smp2p_adsp_out: master-kernel { 712 qcom,entry-name = "master-kernel"; 713 #qcom,smem-state-cells = <1>; 714 }; 715 716 smp2p_adsp_in: slave-kernel { 717 qcom,entry-name = "slave-kernel"; 718 interrupt-controller; 719 #interrupt-cells = <2>; 720 }; 721 }; 722 723 smp2p-cdsp { 724 compatible = "qcom,smp2p"; 725 qcom,smem = <94>, <432>; 726 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 727 IPCC_MPROC_SIGNAL_SMP2P 728 IRQ_TYPE_EDGE_RISING>; 729 mboxes = <&ipcc IPCC_CLIENT_CDSP 730 IPCC_MPROC_SIGNAL_SMP2P>; 731 732 qcom,local-pid = <0>; 733 qcom,remote-pid = <5>; 734 735 smp2p_cdsp_out: master-kernel { 736 qcom,entry-name = "master-kernel"; 737 #qcom,smem-state-cells = <1>; 738 }; 739 740 smp2p_cdsp_in: slave-kernel { 741 qcom,entry-name = "slave-kernel"; 742 interrupt-controller; 743 #interrupt-cells = <2>; 744 }; 745 }; 746 747 smp2p-mpss { 748 compatible = "qcom,smp2p"; 749 qcom,smem = <435>, <428>; 750 751 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 752 IPCC_MPROC_SIGNAL_SMP2P 753 IRQ_TYPE_EDGE_RISING>; 754 mboxes = <&ipcc IPCC_CLIENT_MPSS 755 IPCC_MPROC_SIGNAL_SMP2P>; 756 757 qcom,local-pid = <0>; 758 qcom,remote-pid = <1>; 759 760 modem_smp2p_out: master-kernel { 761 qcom,entry-name = "master-kernel"; 762 #qcom,smem-state-cells = <1>; 763 }; 764 765 modem_smp2p_in: slave-kernel { 766 qcom,entry-name = "slave-kernel"; 767 interrupt-controller; 768 #interrupt-cells = <2>; 769 }; 770 771 ipa_smp2p_out: ipa-ap-to-modem { 772 qcom,entry-name = "ipa"; 773 #qcom,smem-state-cells = <1>; 774 }; 775 776 ipa_smp2p_in: ipa-modem-to-ap { 777 qcom,entry-name = "ipa"; 778 interrupt-controller; 779 #interrupt-cells = <2>; 780 }; 781 }; 782 783 soc: soc@0 { 784 #address-cells = <2>; 785 #size-cells = <2>; 786 ranges = <0 0 0 0 0x10 0>; 787 dma-ranges = <0 0 0 0 0x10 0>; 788 compatible = "simple-bus"; 789 790 gcc: clock-controller@100000 { 791 compatible = "qcom,gcc-sm6350"; 792 reg = <0x0 0x00100000 0x0 0x1f0000>; 793 #clock-cells = <1>; 794 #reset-cells = <1>; 795 #power-domain-cells = <1>; 796 clock-names = "bi_tcxo", 797 "bi_tcxo_ao", 798 "sleep_clk"; 799 clocks = <&rpmhcc RPMH_CXO_CLK>, 800 <&rpmhcc RPMH_CXO_CLK_A>, 801 <&sleep_clk>; 802 }; 803 804 ipcc: mailbox@408000 { 805 compatible = "qcom,sm6350-ipcc", "qcom,ipcc"; 806 reg = <0x0 0x00408000 0x0 0x1000>; 807 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 808 interrupt-controller; 809 #interrupt-cells = <3>; 810 #mbox-cells = <2>; 811 }; 812 813 qfprom: qfprom@784000 { 814 compatible = "qcom,sm6350-qfprom", "qcom,qfprom"; 815 reg = <0x0 0x00784000 0x0 0x3000>; 816 #address-cells = <1>; 817 #size-cells = <1>; 818 819 gpu_speed_bin: gpu-speed-bin@2015 { 820 reg = <0x2015 0x1>; 821 bits = <0 8>; 822 }; 823 }; 824 825 rng: rng@793000 { 826 compatible = "qcom,prng-ee"; 827 reg = <0x0 0x00793000 0x0 0x1000>; 828 clocks = <&gcc GCC_PRNG_AHB_CLK>; 829 clock-names = "core"; 830 }; 831 832 sdhc_1: mmc@7c4000 { 833 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 834 reg = <0x0 0x007c4000 0x0 0x1000>, 835 <0x0 0x007c5000 0x0 0x1000>, 836 <0x0 0x007c8000 0x0 0x8000>; 837 reg-names = "hc", "cqhci", "ice"; 838 839 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 840 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 841 interrupt-names = "hc_irq", "pwr_irq"; 842 iommus = <&apps_smmu 0x60 0x0>; 843 844 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 845 <&gcc GCC_SDCC1_APPS_CLK>, 846 <&rpmhcc RPMH_CXO_CLK>; 847 clock-names = "iface", "core", "xo"; 848 resets = <&gcc GCC_SDCC1_BCR>; 849 qcom,dll-config = <0x000f642c>; 850 qcom,ddr-config = <0x80040868>; 851 power-domains = <&rpmhpd SM6350_CX>; 852 operating-points-v2 = <&sdhc1_opp_table>; 853 bus-width = <8>; 854 non-removable; 855 supports-cqe; 856 857 status = "disabled"; 858 859 sdhc1_opp_table: opp-table { 860 compatible = "operating-points-v2"; 861 862 opp-19200000 { 863 opp-hz = /bits/ 64 <19200000>; 864 required-opps = <&rpmhpd_opp_min_svs>; 865 }; 866 867 opp-100000000 { 868 opp-hz = /bits/ 64 <100000000>; 869 required-opps = <&rpmhpd_opp_low_svs>; 870 }; 871 872 opp-384000000 { 873 opp-hz = /bits/ 64 <384000000>; 874 required-opps = <&rpmhpd_opp_svs_l1>; 875 }; 876 }; 877 }; 878 879 gpi_dma0: dma-controller@800000 { 880 compatible = "qcom,sm6350-gpi-dma"; 881 reg = <0x0 0x00800000 0x0 0x60000>; 882 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 891 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 892 dma-channels = <10>; 893 dma-channel-mask = <0x1f>; 894 iommus = <&apps_smmu 0x56 0x0>; 895 #dma-cells = <3>; 896 status = "disabled"; 897 }; 898 899 qupv3_id_0: geniqup@8c0000 { 900 compatible = "qcom,geni-se-qup"; 901 reg = <0x0 0x008c0000 0x0 0x2000>; 902 clock-names = "m-ahb", "s-ahb"; 903 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 904 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 905 #address-cells = <2>; 906 #size-cells = <2>; 907 iommus = <&apps_smmu 0x43 0x0>; 908 ranges; 909 status = "disabled"; 910 911 i2c0: i2c@880000 { 912 compatible = "qcom,geni-i2c"; 913 reg = <0x0 0x00880000 0x0 0x4000>; 914 clock-names = "se"; 915 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 916 pinctrl-names = "default"; 917 pinctrl-0 = <&qup_i2c0_default>; 918 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 919 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 920 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 921 dma-names = "tx", "rx"; 922 #address-cells = <1>; 923 #size-cells = <0>; 924 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 925 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 926 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 927 interconnect-names = "qup-core", "qup-config", "qup-memory"; 928 status = "disabled"; 929 }; 930 931 uart1: serial@884000 { 932 compatible = "qcom,geni-uart"; 933 reg = <0x0 0x00884000 0x0 0x4000>; 934 clock-names = "se"; 935 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 936 pinctrl-names = "default"; 937 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 938 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 939 power-domains = <&rpmhpd SM6350_CX>; 940 operating-points-v2 = <&qup_opp_table>; 941 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 942 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 943 interconnect-names = "qup-core", "qup-config"; 944 status = "disabled"; 945 }; 946 947 i2c2: i2c@888000 { 948 compatible = "qcom,geni-i2c"; 949 reg = <0x0 0x00888000 0x0 0x4000>; 950 clock-names = "se"; 951 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 952 pinctrl-names = "default"; 953 pinctrl-0 = <&qup_i2c2_default>; 954 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 955 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 956 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 957 dma-names = "tx", "rx"; 958 #address-cells = <1>; 959 #size-cells = <0>; 960 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 961 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 962 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 963 interconnect-names = "qup-core", "qup-config", "qup-memory"; 964 status = "disabled"; 965 }; 966 }; 967 968 gpi_dma1: dma-controller@900000 { 969 compatible = "qcom,sm6350-gpi-dma"; 970 reg = <0x0 0x00900000 0x0 0x60000>; 971 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 648 IRQ_TYPE_LEVEL_HIGH>, 975 <GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH>, 976 <GIC_SPI 650 IRQ_TYPE_LEVEL_HIGH>, 977 <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>, 978 <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 979 <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>, 980 <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>; 981 dma-channels = <10>; 982 dma-channel-mask = <0x3f>; 983 iommus = <&apps_smmu 0x4d6 0x0>; 984 #dma-cells = <3>; 985 status = "disabled"; 986 }; 987 988 qupv3_id_1: geniqup@9c0000 { 989 compatible = "qcom,geni-se-qup"; 990 reg = <0x0 0x009c0000 0x0 0x2000>; 991 clock-names = "m-ahb", "s-ahb"; 992 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 993 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 994 #address-cells = <2>; 995 #size-cells = <2>; 996 iommus = <&apps_smmu 0x4c3 0x0>; 997 ranges; 998 status = "disabled"; 999 1000 i2c6: i2c@980000 { 1001 compatible = "qcom,geni-i2c"; 1002 reg = <0x0 0x00980000 0x0 0x4000>; 1003 clock-names = "se"; 1004 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1005 pinctrl-names = "default"; 1006 pinctrl-0 = <&qup_i2c6_default>; 1007 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1008 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1009 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1010 dma-names = "tx", "rx"; 1011 #address-cells = <1>; 1012 #size-cells = <0>; 1013 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1014 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1015 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1016 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1017 status = "disabled"; 1018 }; 1019 1020 i2c7: i2c@984000 { 1021 compatible = "qcom,geni-i2c"; 1022 reg = <0x0 0x00984000 0x0 0x4000>; 1023 clock-names = "se"; 1024 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1025 pinctrl-names = "default"; 1026 pinctrl-0 = <&qup_i2c7_default>; 1027 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1028 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1029 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1030 dma-names = "tx", "rx"; 1031 #address-cells = <1>; 1032 #size-cells = <0>; 1033 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1034 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1035 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1036 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1037 status = "disabled"; 1038 }; 1039 1040 i2c8: i2c@988000 { 1041 compatible = "qcom,geni-i2c"; 1042 reg = <0x0 0x00988000 0x0 0x4000>; 1043 clock-names = "se"; 1044 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1045 pinctrl-names = "default"; 1046 pinctrl-0 = <&qup_i2c8_default>; 1047 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1048 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1049 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1050 dma-names = "tx", "rx"; 1051 #address-cells = <1>; 1052 #size-cells = <0>; 1053 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1054 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1055 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1056 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1057 status = "disabled"; 1058 }; 1059 1060 uart9: serial@98c000 { 1061 compatible = "qcom,geni-debug-uart"; 1062 reg = <0x0 0x0098c000 0x0 0x4000>; 1063 clock-names = "se"; 1064 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1065 pinctrl-names = "default"; 1066 pinctrl-0 = <&qup_uart9_default>; 1067 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1068 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1069 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1070 interconnect-names = "qup-core", "qup-config"; 1071 status = "disabled"; 1072 }; 1073 1074 i2c10: i2c@990000 { 1075 compatible = "qcom,geni-i2c"; 1076 reg = <0x0 0x00990000 0x0 0x4000>; 1077 clock-names = "se"; 1078 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1079 pinctrl-names = "default"; 1080 pinctrl-0 = <&qup_i2c10_default>; 1081 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1082 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1083 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1084 dma-names = "tx", "rx"; 1085 #address-cells = <1>; 1086 #size-cells = <0>; 1087 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1088 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1089 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1090 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1091 status = "disabled"; 1092 }; 1093 }; 1094 1095 config_noc: interconnect@1500000 { 1096 compatible = "qcom,sm6350-config-noc"; 1097 reg = <0x0 0x01500000 0x0 0x28000>; 1098 #interconnect-cells = <2>; 1099 qcom,bcm-voters = <&apps_bcm_voter>; 1100 }; 1101 1102 system_noc: interconnect@1620000 { 1103 compatible = "qcom,sm6350-system-noc"; 1104 reg = <0x0 0x01620000 0x0 0x17080>; 1105 #interconnect-cells = <2>; 1106 qcom,bcm-voters = <&apps_bcm_voter>; 1107 1108 clk_virt: interconnect-clk-virt { 1109 compatible = "qcom,sm6350-clk-virt"; 1110 #interconnect-cells = <2>; 1111 qcom,bcm-voters = <&apps_bcm_voter>; 1112 }; 1113 }; 1114 1115 aggre1_noc: interconnect@16e0000 { 1116 compatible = "qcom,sm6350-aggre1-noc"; 1117 reg = <0x0 0x016e0000 0x0 0x15080>; 1118 #interconnect-cells = <2>; 1119 qcom,bcm-voters = <&apps_bcm_voter>; 1120 }; 1121 1122 aggre2_noc: interconnect@1700000 { 1123 compatible = "qcom,sm6350-aggre2-noc"; 1124 reg = <0x0 0x01700000 0x0 0x1f880>; 1125 #interconnect-cells = <2>; 1126 qcom,bcm-voters = <&apps_bcm_voter>; 1127 1128 compute_noc: interconnect-compute-noc { 1129 compatible = "qcom,sm6350-compute-noc"; 1130 #interconnect-cells = <2>; 1131 qcom,bcm-voters = <&apps_bcm_voter>; 1132 }; 1133 }; 1134 1135 mmss_noc: interconnect@1740000 { 1136 compatible = "qcom,sm6350-mmss-noc"; 1137 reg = <0x0 0x01740000 0x0 0x1c100>; 1138 #interconnect-cells = <2>; 1139 qcom,bcm-voters = <&apps_bcm_voter>; 1140 }; 1141 1142 ufs_mem_hc: ufshc@1d84000 { 1143 compatible = "qcom,sm6350-ufshc", "qcom,ufshc", 1144 "jedec,ufs-2.0"; 1145 reg = <0x0 0x01d84000 0x0 0x3000>, 1146 <0x0 0x01d90000 0x0 0x8000>; 1147 reg-names = "std", "ice"; 1148 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1149 phys = <&ufs_mem_phy>; 1150 phy-names = "ufsphy"; 1151 lanes-per-direction = <2>; 1152 #reset-cells = <1>; 1153 resets = <&gcc GCC_UFS_PHY_BCR>; 1154 reset-names = "rst"; 1155 1156 power-domains = <&gcc UFS_PHY_GDSC>; 1157 1158 iommus = <&apps_smmu 0x80 0x0>; 1159 1160 clock-names = "core_clk", 1161 "bus_aggr_clk", 1162 "iface_clk", 1163 "core_clk_unipro", 1164 "ref_clk", 1165 "tx_lane0_sync_clk", 1166 "rx_lane0_sync_clk", 1167 "rx_lane1_sync_clk", 1168 "ice_core_clk"; 1169 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1170 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1171 <&gcc GCC_UFS_PHY_AHB_CLK>, 1172 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1173 <&rpmhcc RPMH_QLINK_CLK>, 1174 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1175 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1176 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 1177 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1178 freq-table-hz = 1179 <50000000 200000000>, 1180 <0 0>, 1181 <0 0>, 1182 <37500000 150000000>, 1183 <75000000 300000000>, 1184 <0 0>, 1185 <0 0>, 1186 <0 0>, 1187 <0 0>; 1188 1189 status = "disabled"; 1190 }; 1191 1192 ufs_mem_phy: phy@1d87000 { 1193 compatible = "qcom,sm6350-qmp-ufs-phy"; 1194 reg = <0x0 0x01d87000 0x0 0x1000>; 1195 1196 clocks = <&rpmhcc RPMH_CXO_CLK>, 1197 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1198 <&gcc GCC_UFS_MEM_CLKREF_CLK>; 1199 clock-names = "ref", 1200 "ref_aux", 1201 "qref"; 1202 1203 power-domains = <&gcc UFS_PHY_GDSC>; 1204 1205 resets = <&ufs_mem_hc 0>; 1206 reset-names = "ufsphy"; 1207 1208 #phy-cells = <0>; 1209 1210 status = "disabled"; 1211 }; 1212 1213 cryptobam: dma-controller@1dc4000 { 1214 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1215 reg = <0x0 0x01dc4000 0x0 0x24000>; 1216 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1217 #dma-cells = <1>; 1218 qcom,ee = <0>; 1219 qcom,controlled-remotely; 1220 num-channels = <16>; 1221 qcom,num-ees = <4>; 1222 iommus = <&apps_smmu 0x426 0x11>, 1223 <&apps_smmu 0x432 0x0>, 1224 <&apps_smmu 0x436 0x11>, 1225 <&apps_smmu 0x438 0x1>, 1226 <&apps_smmu 0x43f 0x0>; 1227 }; 1228 1229 crypto: crypto@1dfa000 { 1230 compatible = "qcom,sm6350-qce", "qcom,sm8150-qce", "qcom,qce"; 1231 reg = <0x0 0x01dfa000 0x0 0x6000>; 1232 dmas = <&cryptobam 4>, <&cryptobam 5>; 1233 dma-names = "rx", "tx"; 1234 iommus = <&apps_smmu 0x426 0x11>, 1235 <&apps_smmu 0x432 0x0>, 1236 <&apps_smmu 0x436 0x11>, 1237 <&apps_smmu 0x438 0x1>, 1238 <&apps_smmu 0x43f 0x0>; 1239 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 QCOM_ICC_TAG_ALWAYS 1240 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; 1241 interconnect-names = "memory"; 1242 }; 1243 1244 ipa: ipa@1e40000 { 1245 compatible = "qcom,sm6350-ipa"; 1246 1247 iommus = <&apps_smmu 0x440 0x0>, 1248 <&apps_smmu 0x442 0x0>; 1249 reg = <0x0 0x01e40000 0x0 0x8000>, 1250 <0x0 0x01e50000 0x0 0x3000>, 1251 <0x0 0x01e04000 0x0 0x23000>; 1252 reg-names = "ipa-reg", 1253 "ipa-shared", 1254 "gsi"; 1255 1256 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 1257 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1258 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1259 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1260 interrupt-names = "ipa", 1261 "gsi", 1262 "ipa-clock-query", 1263 "ipa-setup-ready"; 1264 1265 clocks = <&rpmhcc RPMH_IPA_CLK>; 1266 clock-names = "core"; 1267 1268 interconnects = <&aggre2_noc MASTER_IPA 0 &clk_virt SLAVE_EBI_CH0 0>, 1269 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_OCIMEM 0>, 1270 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_IPA_CFG 0>; 1271 interconnect-names = "memory", "imem", "config"; 1272 1273 qcom,smem-states = <&ipa_smp2p_out 0>, 1274 <&ipa_smp2p_out 1>; 1275 qcom,smem-state-names = "ipa-clock-enabled-valid", 1276 "ipa-clock-enabled"; 1277 1278 status = "disabled"; 1279 }; 1280 1281 tcsr_mutex: hwlock@1f40000 { 1282 compatible = "qcom,tcsr-mutex"; 1283 reg = <0x0 0x01f40000 0x0 0x40000>; 1284 #hwlock-cells = <1>; 1285 }; 1286 1287 adsp: remoteproc@3000000 { 1288 compatible = "qcom,sm6350-adsp-pas"; 1289 reg = <0x0 0x03000000 0x0 0x10000>; 1290 1291 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 1292 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1293 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1294 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1295 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1296 interrupt-names = "wdog", "fatal", "ready", 1297 "handover", "stop-ack"; 1298 1299 clocks = <&rpmhcc RPMH_CXO_CLK>; 1300 clock-names = "xo"; 1301 1302 power-domains = <&rpmhpd SM6350_LCX>, 1303 <&rpmhpd SM6350_LMX>; 1304 power-domain-names = "lcx", "lmx"; 1305 1306 memory-region = <&pil_adsp_mem>; 1307 1308 qcom,qmp = <&aoss_qmp>; 1309 1310 qcom,smem-states = <&smp2p_adsp_out 0>; 1311 qcom,smem-state-names = "stop"; 1312 1313 status = "disabled"; 1314 1315 glink-edge { 1316 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1317 IPCC_MPROC_SIGNAL_GLINK_QMP 1318 IRQ_TYPE_EDGE_RISING>; 1319 mboxes = <&ipcc IPCC_CLIENT_LPASS 1320 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1321 1322 label = "lpass"; 1323 qcom,remote-pid = <2>; 1324 1325 apr { 1326 compatible = "qcom,apr-v2"; 1327 qcom,glink-channels = "apr_audio_svc"; 1328 qcom,domain = <APR_DOMAIN_ADSP>; 1329 #address-cells = <1>; 1330 #size-cells = <0>; 1331 1332 service@3 { 1333 reg = <APR_SVC_ADSP_CORE>; 1334 compatible = "qcom,q6core"; 1335 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1336 }; 1337 1338 q6afe: service@4 { 1339 compatible = "qcom,q6afe"; 1340 reg = <APR_SVC_AFE>; 1341 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1342 1343 q6afedai: dais { 1344 compatible = "qcom,q6afe-dais"; 1345 #address-cells = <1>; 1346 #size-cells = <0>; 1347 #sound-dai-cells = <1>; 1348 }; 1349 1350 q6afecc: clock-controller { 1351 compatible = "qcom,q6afe-clocks"; 1352 #clock-cells = <2>; 1353 }; 1354 1355 q6usbdai: usbd { 1356 compatible = "qcom,q6usb"; 1357 iommus = <&apps_smmu 0x100f 0x0>; 1358 #sound-dai-cells = <1>; 1359 qcom,usb-audio-intr-idx = /bits/ 16 <2>; 1360 }; 1361 }; 1362 1363 q6asm: service@7 { 1364 compatible = "qcom,q6asm"; 1365 reg = <APR_SVC_ASM>; 1366 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1367 1368 q6asmdai: dais { 1369 compatible = "qcom,q6asm-dais"; 1370 #address-cells = <1>; 1371 #size-cells = <0>; 1372 #sound-dai-cells = <1>; 1373 iommus = <&apps_smmu 0x1001 0x0>; 1374 }; 1375 }; 1376 1377 q6adm: service@8 { 1378 compatible = "qcom,q6adm"; 1379 reg = <APR_SVC_ADM>; 1380 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1381 1382 q6routing: routing { 1383 compatible = "qcom,q6adm-routing"; 1384 #sound-dai-cells = <0>; 1385 }; 1386 }; 1387 }; 1388 1389 fastrpc { 1390 compatible = "qcom,fastrpc"; 1391 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1392 label = "adsp"; 1393 qcom,non-secure-domain; 1394 #address-cells = <1>; 1395 #size-cells = <0>; 1396 1397 compute-cb@3 { 1398 compatible = "qcom,fastrpc-compute-cb"; 1399 reg = <3>; 1400 iommus = <&apps_smmu 0x1003 0x0>; 1401 }; 1402 1403 compute-cb@4 { 1404 compatible = "qcom,fastrpc-compute-cb"; 1405 reg = <4>; 1406 iommus = <&apps_smmu 0x1004 0x0>; 1407 }; 1408 1409 compute-cb@5 { 1410 compatible = "qcom,fastrpc-compute-cb"; 1411 reg = <5>; 1412 iommus = <&apps_smmu 0x1005 0x0>; 1413 qcom,nsessions = <5>; 1414 }; 1415 }; 1416 }; 1417 }; 1418 1419 gpu: gpu@3d00000 { 1420 compatible = "qcom,adreno-619.0", "qcom,adreno"; 1421 reg = <0x0 0x03d00000 0x0 0x40000>, 1422 <0x0 0x03d9e000 0x0 0x1000>; 1423 reg-names = "kgsl_3d0_reg_memory", 1424 "cx_mem"; 1425 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1426 1427 iommus = <&adreno_smmu 0>; 1428 operating-points-v2 = <&gpu_opp_table>; 1429 qcom,gmu = <&gmu>; 1430 nvmem-cells = <&gpu_speed_bin>; 1431 nvmem-cell-names = "speed_bin"; 1432 #cooling-cells = <2>; 1433 1434 status = "disabled"; 1435 1436 gpu_zap_shader: zap-shader { 1437 memory-region = <&pil_gpu_mem>; 1438 }; 1439 1440 gpu_opp_table: opp-table { 1441 compatible = "operating-points-v2"; 1442 1443 opp-850000000 { 1444 opp-hz = /bits/ 64 <850000000>; 1445 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1446 opp-supported-hw = <0x03>; 1447 }; 1448 1449 opp-800000000 { 1450 opp-hz = /bits/ 64 <800000000>; 1451 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1452 opp-supported-hw = <0x07>; 1453 }; 1454 1455 opp-650000000 { 1456 opp-hz = /bits/ 64 <650000000>; 1457 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1458 opp-supported-hw = <0x0f>; 1459 }; 1460 1461 opp-565000000 { 1462 opp-hz = /bits/ 64 <565000000>; 1463 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1464 opp-supported-hw = <0x1f>; 1465 }; 1466 1467 opp-430000000 { 1468 opp-hz = /bits/ 64 <430000000>; 1469 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1470 opp-supported-hw = <0x1f>; 1471 }; 1472 1473 opp-355000000 { 1474 opp-hz = /bits/ 64 <355000000>; 1475 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1476 opp-supported-hw = <0x1f>; 1477 }; 1478 1479 opp-253000000 { 1480 opp-hz = /bits/ 64 <253000000>; 1481 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1482 opp-supported-hw = <0x1f>; 1483 }; 1484 }; 1485 }; 1486 1487 adreno_smmu: iommu@3d40000 { 1488 compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 1489 reg = <0x0 0x03d40000 0x0 0x10000>; 1490 #iommu-cells = <1>; 1491 #global-interrupts = <2>; 1492 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1493 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1494 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 1495 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 1496 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 1497 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 1498 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 1499 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 1500 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 1501 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1502 1503 clocks = <&gpucc GPU_CC_AHB_CLK>, 1504 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1505 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1506 clock-names = "ahb", 1507 "bus", 1508 "iface"; 1509 1510 power-domains = <&gpucc GPU_CX_GDSC>; 1511 }; 1512 1513 gmu: gmu@3d6a000 { 1514 compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu"; 1515 reg = <0x0 0x03d6a000 0x0 0x31000>, 1516 <0x0 0x0b290000 0x0 0x10000>, 1517 <0x0 0x0b490000 0x0 0x10000>; 1518 reg-names = "gmu", 1519 "gmu_pdc", 1520 "gmu_pdc_seq"; 1521 1522 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1524 interrupt-names = "hfi", 1525 "gmu"; 1526 1527 clocks = <&gpucc GPU_CC_AHB_CLK>, 1528 <&gpucc GPU_CC_CX_GMU_CLK>, 1529 <&gpucc GPU_CC_CXO_CLK>, 1530 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1531 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1532 clock-names = "ahb", 1533 "gmu", 1534 "cxo", 1535 "axi", 1536 "memnoc"; 1537 1538 power-domains = <&gpucc GPU_CX_GDSC>, 1539 <&gpucc GPU_GX_GDSC>; 1540 power-domain-names = "cx", 1541 "gx"; 1542 1543 iommus = <&adreno_smmu 5>; 1544 1545 operating-points-v2 = <&gmu_opp_table>; 1546 1547 gmu_opp_table: opp-table { 1548 compatible = "operating-points-v2"; 1549 1550 opp-200000000 { 1551 opp-hz = /bits/ 64 <200000000>; 1552 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1553 }; 1554 }; 1555 }; 1556 1557 gpucc: clock-controller@3d90000 { 1558 compatible = "qcom,sm6350-gpucc"; 1559 reg = <0x0 0x03d90000 0x0 0x9000>; 1560 clocks = <&rpmhcc RPMH_CXO_CLK>, 1561 <&gcc GCC_GPU_GPLL0_CLK>, 1562 <&gcc GCC_GPU_GPLL0_DIV_CLK>; 1563 clock-names = "bi_tcxo", 1564 "gcc_gpu_gpll0_clk_src", 1565 "gcc_gpu_gpll0_div_clk_src"; 1566 #clock-cells = <1>; 1567 #reset-cells = <1>; 1568 #power-domain-cells = <1>; 1569 }; 1570 1571 mpss: remoteproc@4080000 { 1572 compatible = "qcom,sm6350-mpss-pas"; 1573 reg = <0x0 0x04080000 0x0 0x10000>; 1574 1575 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 1576 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1577 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1578 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1579 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1580 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1581 interrupt-names = "wdog", "fatal", "ready", "handover", 1582 "stop-ack", "shutdown-ack"; 1583 1584 clocks = <&rpmhcc RPMH_CXO_CLK>; 1585 clock-names = "xo"; 1586 1587 power-domains = <&rpmhpd SM6350_CX>, 1588 <&rpmhpd SM6350_MSS>; 1589 power-domain-names = "cx", "mss"; 1590 1591 memory-region = <&pil_modem_mem>; 1592 1593 qcom,qmp = <&aoss_qmp>; 1594 1595 qcom,smem-states = <&modem_smp2p_out 0>; 1596 qcom,smem-state-names = "stop"; 1597 1598 status = "disabled"; 1599 1600 glink-edge { 1601 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1602 IPCC_MPROC_SIGNAL_GLINK_QMP 1603 IRQ_TYPE_EDGE_RISING>; 1604 mboxes = <&ipcc IPCC_CLIENT_MPSS 1605 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1606 label = "modem"; 1607 qcom,remote-pid = <1>; 1608 }; 1609 }; 1610 1611 cdsp: remoteproc@8300000 { 1612 compatible = "qcom,sm6350-cdsp-pas"; 1613 reg = <0x0 0x08300000 0x0 0x10000>; 1614 1615 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 1616 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 1617 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 1618 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 1619 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 1620 interrupt-names = "wdog", "fatal", "ready", 1621 "handover", "stop-ack"; 1622 1623 clocks = <&rpmhcc RPMH_CXO_CLK>; 1624 clock-names = "xo"; 1625 1626 power-domains = <&rpmhpd SM6350_CX>, 1627 <&rpmhpd SM6350_MX>; 1628 power-domain-names = "cx", "mx"; 1629 1630 memory-region = <&pil_cdsp_mem>; 1631 1632 qcom,qmp = <&aoss_qmp>; 1633 1634 qcom,smem-states = <&smp2p_cdsp_out 0>; 1635 qcom,smem-state-names = "stop"; 1636 1637 status = "disabled"; 1638 1639 glink-edge { 1640 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 1641 IPCC_MPROC_SIGNAL_GLINK_QMP 1642 IRQ_TYPE_EDGE_RISING>; 1643 mboxes = <&ipcc IPCC_CLIENT_CDSP 1644 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1645 1646 label = "cdsp"; 1647 qcom,remote-pid = <5>; 1648 1649 fastrpc { 1650 compatible = "qcom,fastrpc"; 1651 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1652 label = "cdsp"; 1653 qcom,non-secure-domain; 1654 #address-cells = <1>; 1655 #size-cells = <0>; 1656 1657 compute-cb@1 { 1658 compatible = "qcom,fastrpc-compute-cb"; 1659 reg = <1>; 1660 iommus = <&apps_smmu 0x1401 0x20>; 1661 }; 1662 1663 compute-cb@2 { 1664 compatible = "qcom,fastrpc-compute-cb"; 1665 reg = <2>; 1666 iommus = <&apps_smmu 0x1402 0x20>; 1667 }; 1668 1669 compute-cb@3 { 1670 compatible = "qcom,fastrpc-compute-cb"; 1671 reg = <3>; 1672 iommus = <&apps_smmu 0x1403 0x20>; 1673 }; 1674 1675 compute-cb@4 { 1676 compatible = "qcom,fastrpc-compute-cb"; 1677 reg = <4>; 1678 iommus = <&apps_smmu 0x1404 0x20>; 1679 }; 1680 1681 compute-cb@5 { 1682 compatible = "qcom,fastrpc-compute-cb"; 1683 reg = <5>; 1684 iommus = <&apps_smmu 0x1405 0x20>; 1685 }; 1686 1687 compute-cb@6 { 1688 compatible = "qcom,fastrpc-compute-cb"; 1689 reg = <6>; 1690 iommus = <&apps_smmu 0x1406 0x20>; 1691 }; 1692 1693 compute-cb@7 { 1694 compatible = "qcom,fastrpc-compute-cb"; 1695 reg = <7>; 1696 iommus = <&apps_smmu 0x1407 0x20>; 1697 }; 1698 1699 compute-cb@8 { 1700 compatible = "qcom,fastrpc-compute-cb"; 1701 reg = <8>; 1702 iommus = <&apps_smmu 0x1408 0x20>; 1703 }; 1704 1705 /* note: secure cb9 in downstream */ 1706 }; 1707 }; 1708 }; 1709 1710 sdhc_2: mmc@8804000 { 1711 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 1712 reg = <0x0 0x08804000 0x0 0x1000>; 1713 1714 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1715 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1716 interrupt-names = "hc_irq", "pwr_irq"; 1717 iommus = <&apps_smmu 0x560 0x0>; 1718 1719 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1720 <&gcc GCC_SDCC2_APPS_CLK>, 1721 <&rpmhcc RPMH_CXO_CLK>; 1722 clock-names = "iface", "core", "xo"; 1723 resets = <&gcc GCC_SDCC2_BCR>; 1724 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>, 1725 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>; 1726 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 1727 1728 pinctrl-0 = <&sdc2_on_state>; 1729 pinctrl-1 = <&sdc2_off_state>; 1730 pinctrl-names = "default", "sleep"; 1731 1732 qcom,dll-config = <0x0007642c>; 1733 qcom,ddr-config = <0x80040868>; 1734 power-domains = <&rpmhpd SM6350_CX>; 1735 operating-points-v2 = <&sdhc2_opp_table>; 1736 bus-width = <4>; 1737 1738 status = "disabled"; 1739 1740 sdhc2_opp_table: opp-table { 1741 compatible = "operating-points-v2"; 1742 1743 opp-100000000 { 1744 opp-hz = /bits/ 64 <100000000>; 1745 required-opps = <&rpmhpd_opp_svs_l1>; 1746 opp-peak-kBps = <790000 131000>; 1747 opp-avg-kBps = <50000 50000>; 1748 }; 1749 1750 opp-202000000 { 1751 opp-hz = /bits/ 64 <202000000>; 1752 required-opps = <&rpmhpd_opp_nom>; 1753 opp-peak-kBps = <3190000 294000>; 1754 opp-avg-kBps = <261438 300000>; 1755 }; 1756 }; 1757 }; 1758 1759 usb_1_hsphy: phy@88e3000 { 1760 compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy"; 1761 reg = <0x0 0x088e3000 0x0 0x400>; 1762 status = "disabled"; 1763 #phy-cells = <0>; 1764 1765 clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>; 1766 clock-names = "cfg_ahb", "ref"; 1767 1768 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1769 }; 1770 1771 usb_1_qmpphy: phy@88e8000 { 1772 compatible = "qcom,sm6350-qmp-usb3-dp-phy"; 1773 reg = <0x0 0x088e8000 0x0 0x3000>; 1774 1775 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1776 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 1777 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 1778 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1779 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 1780 1781 power-domains = <&gcc USB30_PRIM_GDSC>; 1782 1783 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 1784 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 1785 reset-names = "phy", "common"; 1786 1787 orientation-switch; 1788 1789 #clock-cells = <1>; 1790 #phy-cells = <1>; 1791 1792 status = "disabled"; 1793 1794 ports { 1795 #address-cells = <1>; 1796 #size-cells = <0>; 1797 1798 port@0 { 1799 reg = <0>; 1800 1801 usb_1_qmpphy_out: endpoint { 1802 }; 1803 }; 1804 1805 port@1 { 1806 reg = <1>; 1807 1808 usb_1_qmpphy_usb_ss_in: endpoint { 1809 remote-endpoint = <&usb_1_dwc3_ss_out>; 1810 }; 1811 }; 1812 1813 port@2 { 1814 reg = <2>; 1815 1816 usb_1_qmpphy_dp_in: endpoint { 1817 }; 1818 }; 1819 }; 1820 }; 1821 1822 dc_noc: interconnect@9160000 { 1823 compatible = "qcom,sm6350-dc-noc"; 1824 reg = <0x0 0x09160000 0x0 0x3200>; 1825 #interconnect-cells = <2>; 1826 qcom,bcm-voters = <&apps_bcm_voter>; 1827 }; 1828 1829 system-cache-controller@9200000 { 1830 compatible = "qcom,sm6350-llcc"; 1831 reg = <0x0 0x09200000 0x0 0x50000>, <0x0 0x09600000 0x0 0x50000>; 1832 reg-names = "llcc0_base", "llcc_broadcast_base"; 1833 }; 1834 1835 gem_noc: interconnect@9680000 { 1836 compatible = "qcom,sm6350-gem-noc"; 1837 reg = <0x0 0x09680000 0x0 0x3e200>; 1838 #interconnect-cells = <2>; 1839 qcom,bcm-voters = <&apps_bcm_voter>; 1840 }; 1841 1842 npu_noc: interconnect@9990000 { 1843 compatible = "qcom,sm6350-npu-noc"; 1844 reg = <0x0 0x09990000 0x0 0x1600>; 1845 #interconnect-cells = <2>; 1846 qcom,bcm-voters = <&apps_bcm_voter>; 1847 }; 1848 1849 pmu@90b6300 { 1850 compatible = "qcom,sm6350-llcc-bwmon", "qcom,sdm845-bwmon"; 1851 reg = <0x0 0x090b6300 0x0 0x600>; 1852 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 1853 1854 operating-points-v2 = <&llcc_bwmon_opp_table>; 1855 interconnects = <&clk_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 1856 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>; 1857 1858 llcc_bwmon_opp_table: opp-table { 1859 compatible = "operating-points-v2"; 1860 1861 opp-0 { 1862 opp-peak-kBps = <2288000>; 1863 }; 1864 1865 opp-1 { 1866 opp-peak-kBps = <4577000>; 1867 }; 1868 1869 opp-2 { 1870 opp-peak-kBps = <7110000>; 1871 }; 1872 1873 opp-3 { 1874 opp-peak-kBps = <9155000>; 1875 }; 1876 1877 opp-4 { 1878 opp-peak-kBps = <12298000>; 1879 }; 1880 1881 opp-5 { 1882 opp-peak-kBps = <14236000>; 1883 }; 1884 1885 }; 1886 }; 1887 1888 pmu@90cd000 { 1889 compatible = "qcom,sm6350-cpu-bwmon", "qcom,sc7280-llcc-bwmon"; 1890 reg = <0x0 0x090cd000 0x0 0x1000>; 1891 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1892 1893 operating-points-v2 = <&cpu_bwmon_opp_table>; 1894 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 1895 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>; 1896 1897 cpu_bwmon_opp_table: opp-table { 1898 compatible = "operating-points-v2"; 1899 1900 opp-0 { 1901 opp-peak-kBps = <762000>; 1902 }; 1903 1904 opp-1 { 1905 opp-peak-kBps = <1144000>; 1906 }; 1907 1908 opp-2 { 1909 opp-peak-kBps = <1720000>; 1910 }; 1911 1912 opp-3 { 1913 opp-peak-kBps = <2086000>; 1914 }; 1915 1916 opp-4 { 1917 opp-peak-kBps = <2597000>; 1918 }; 1919 1920 opp-5 { 1921 opp-peak-kBps = <2929000>; 1922 }; 1923 1924 opp-6 { 1925 opp-peak-kBps = <3879000>; 1926 }; 1927 1928 opp-7 { 1929 opp-peak-kBps = <5161000>; 1930 }; 1931 1932 opp-8 { 1933 opp-peak-kBps = <5931000>; 1934 }; 1935 1936 opp-9 { 1937 opp-peak-kBps = <6881000>; 1938 }; 1939 1940 opp-10 { 1941 opp-peak-kBps = <7980000>; 1942 }; 1943 }; 1944 }; 1945 1946 usb_1: usb@a6f8800 { 1947 compatible = "qcom,sm6350-dwc3", "qcom,dwc3"; 1948 reg = <0x0 0x0a6f8800 0x0 0x400>; 1949 status = "disabled"; 1950 #address-cells = <2>; 1951 #size-cells = <2>; 1952 ranges; 1953 1954 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1955 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1956 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1957 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1958 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 1959 clock-names = "cfg_noc", 1960 "core", 1961 "iface", 1962 "sleep", 1963 "mock_utmi"; 1964 1965 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1966 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1967 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 1968 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1969 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 1970 interrupt-names = "pwr_event", 1971 "hs_phy_irq", 1972 "dp_hs_phy_irq", 1973 "dm_hs_phy_irq", 1974 "ss_phy_irq"; 1975 1976 power-domains = <&gcc USB30_PRIM_GDSC>; 1977 1978 resets = <&gcc GCC_USB30_PRIM_BCR>; 1979 1980 interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>, 1981 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 1982 interconnect-names = "usb-ddr", "apps-usb"; 1983 1984 usb_1_dwc3: usb@a600000 { 1985 compatible = "snps,dwc3"; 1986 reg = <0x0 0x0a600000 0x0 0xcd00>; 1987 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1988 iommus = <&apps_smmu 0x540 0x0>; 1989 num-hc-interrupters = /bits/ 16 <3>; 1990 snps,dis_u2_susphy_quirk; 1991 snps,dis_enblslpm_quirk; 1992 snps,has-lpm-erratum; 1993 snps,hird-threshold = /bits/ 8 <0x10>; 1994 snps,parkmode-disable-ss-quirk; 1995 snps,dis-u1-entry-quirk; 1996 snps,dis-u2-entry-quirk; 1997 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 1998 phy-names = "usb2-phy", "usb3-phy"; 1999 usb-role-switch; 2000 2001 ports { 2002 #address-cells = <1>; 2003 #size-cells = <0>; 2004 2005 port@0 { 2006 reg = <0>; 2007 2008 usb_1_dwc3_hs_out: endpoint { 2009 }; 2010 }; 2011 2012 port@1 { 2013 reg = <1>; 2014 2015 usb_1_dwc3_ss_out: endpoint { 2016 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 2017 }; 2018 }; 2019 }; 2020 }; 2021 }; 2022 2023 videocc: clock-controller@aaf0000 { 2024 compatible = "qcom,sm6350-videocc"; 2025 reg = <0x0 0x0aaf0000 0x0 0x10000>; 2026 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 2027 <&rpmhcc RPMH_CXO_CLK>, 2028 <&sleep_clk>; 2029 clock-names = "iface", 2030 "bi_tcxo", 2031 "sleep_clk"; 2032 #clock-cells = <1>; 2033 #reset-cells = <1>; 2034 #power-domain-cells = <1>; 2035 }; 2036 2037 cci0: cci@ac4a000 { 2038 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; 2039 reg = <0x0 0x0ac4a000 0x0 0x1000>; 2040 interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>; 2041 power-domains = <&camcc TITAN_TOP_GDSC>; 2042 2043 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 2044 <&camcc CAMCC_SOC_AHB_CLK>, 2045 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 2046 <&camcc CAMCC_CPAS_AHB_CLK>, 2047 <&camcc CAMCC_CCI_0_CLK>, 2048 <&camcc CAMCC_CCI_0_CLK_SRC>; 2049 clock-names = "camnoc_axi", 2050 "soc_ahb", 2051 "slow_ahb_src", 2052 "cpas_ahb", 2053 "cci", 2054 "cci_src"; 2055 2056 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 2057 <&camcc CAMCC_CCI_0_CLK>; 2058 assigned-clock-rates = <80000000>, <37500000>; 2059 2060 pinctrl-0 = <&cci0_default &cci1_default>; 2061 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 2062 pinctrl-names = "default", "sleep"; 2063 2064 #address-cells = <1>; 2065 #size-cells = <0>; 2066 2067 status = "disabled"; 2068 2069 cci0_i2c0: i2c-bus@0 { 2070 reg = <0>; 2071 clock-frequency = <1000000>; 2072 #address-cells = <1>; 2073 #size-cells = <0>; 2074 }; 2075 2076 cci0_i2c1: i2c-bus@1 { 2077 reg = <1>; 2078 clock-frequency = <1000000>; 2079 #address-cells = <1>; 2080 #size-cells = <0>; 2081 }; 2082 }; 2083 2084 cci1: cci@ac4b000 { 2085 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; 2086 reg = <0x0 0x0ac4b000 0x0 0x1000>; 2087 interrupts = <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>; 2088 power-domains = <&camcc TITAN_TOP_GDSC>; 2089 2090 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 2091 <&camcc CAMCC_SOC_AHB_CLK>, 2092 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 2093 <&camcc CAMCC_CPAS_AHB_CLK>, 2094 <&camcc CAMCC_CCI_1_CLK>, 2095 <&camcc CAMCC_CCI_1_CLK_SRC>; 2096 clock-names = "camnoc_axi", 2097 "soc_ahb", 2098 "slow_ahb_src", 2099 "cpas_ahb", 2100 "cci", 2101 "cci_src"; 2102 2103 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 2104 <&camcc CAMCC_CCI_1_CLK>; 2105 assigned-clock-rates = <80000000>, <37500000>; 2106 2107 pinctrl-0 = <&cci2_default>; 2108 pinctrl-1 = <&cci2_sleep>; 2109 pinctrl-names = "default", "sleep"; 2110 2111 #address-cells = <1>; 2112 #size-cells = <0>; 2113 2114 status = "disabled"; 2115 2116 cci1_i2c0: i2c-bus@0 { 2117 reg = <0>; 2118 clock-frequency = <1000000>; 2119 #address-cells = <1>; 2120 #size-cells = <0>; 2121 }; 2122 2123 /* SM6350 seems to have cci1_i2c1 on gpio2 & gpio3 but unused downstream */ 2124 }; 2125 2126 camcc: clock-controller@ad00000 { 2127 compatible = "qcom,sm6350-camcc"; 2128 reg = <0x0 0x0ad00000 0x0 0x16000>; 2129 clocks = <&rpmhcc RPMH_CXO_CLK>; 2130 #clock-cells = <1>; 2131 #reset-cells = <1>; 2132 #power-domain-cells = <1>; 2133 }; 2134 2135 mdss: display-subsystem@ae00000 { 2136 compatible = "qcom,sm6350-mdss"; 2137 reg = <0x0 0x0ae00000 0x0 0x1000>; 2138 reg-names = "mdss"; 2139 2140 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2141 interrupt-controller; 2142 #interrupt-cells = <1>; 2143 2144 interconnects = <&mmss_noc MASTER_MDP_PORT0 QCOM_ICC_TAG_ALWAYS 2145 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, 2146 <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 2147 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 2148 interconnect-names = "mdp0-mem", 2149 "cpu-cfg"; 2150 2151 clocks = <&gcc GCC_DISP_AHB_CLK>, 2152 <&gcc GCC_DISP_AXI_CLK>, 2153 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2154 clock-names = "iface", 2155 "bus", 2156 "core"; 2157 2158 power-domains = <&dispcc MDSS_GDSC>; 2159 iommus = <&apps_smmu 0x800 0x2>; 2160 2161 #address-cells = <2>; 2162 #size-cells = <2>; 2163 ranges; 2164 2165 status = "disabled"; 2166 2167 mdss_mdp: display-controller@ae01000 { 2168 compatible = "qcom,sm6350-dpu"; 2169 reg = <0x0 0x0ae01000 0x0 0x8f000>, 2170 <0x0 0x0aeb0000 0x0 0x2008>; 2171 reg-names = "mdp", "vbif"; 2172 2173 interrupt-parent = <&mdss>; 2174 interrupts = <0>; 2175 2176 clocks = <&gcc GCC_DISP_AXI_CLK>, 2177 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2178 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2179 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2180 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2181 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2182 clock-names = "bus", 2183 "iface", 2184 "rot", 2185 "lut", 2186 "core", 2187 "vsync"; 2188 2189 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2190 assigned-clock-rates = <19200000>; 2191 2192 operating-points-v2 = <&mdp_opp_table>; 2193 power-domains = <&rpmhpd SM6350_CX>; 2194 2195 ports { 2196 #address-cells = <1>; 2197 #size-cells = <0>; 2198 2199 port@0 { 2200 reg = <0>; 2201 2202 dpu_intf1_out: endpoint { 2203 remote-endpoint = <&mdss_dsi0_in>; 2204 }; 2205 }; 2206 2207 port@2 { 2208 reg = <2>; 2209 2210 dpu_intf0_out: endpoint { 2211 remote-endpoint = <&mdss_dp_in>; 2212 }; 2213 }; 2214 }; 2215 2216 mdp_opp_table: opp-table { 2217 compatible = "operating-points-v2"; 2218 2219 opp-19200000 { 2220 opp-hz = /bits/ 64 <19200000>; 2221 required-opps = <&rpmhpd_opp_min_svs>; 2222 }; 2223 2224 opp-200000000 { 2225 opp-hz = /bits/ 64 <200000000>; 2226 required-opps = <&rpmhpd_opp_low_svs>; 2227 }; 2228 2229 opp-300000000 { 2230 opp-hz = /bits/ 64 <300000000>; 2231 required-opps = <&rpmhpd_opp_svs>; 2232 }; 2233 2234 opp-373333333 { 2235 opp-hz = /bits/ 64 <373333333>; 2236 required-opps = <&rpmhpd_opp_svs_l1>; 2237 }; 2238 2239 opp-448000000 { 2240 opp-hz = /bits/ 64 <448000000>; 2241 required-opps = <&rpmhpd_opp_nom>; 2242 }; 2243 2244 opp-560000000 { 2245 opp-hz = /bits/ 64 <560000000>; 2246 required-opps = <&rpmhpd_opp_turbo>; 2247 }; 2248 }; 2249 }; 2250 2251 mdss_dp: displayport-controller@ae90000 { 2252 compatible = "qcom,sm6350-dp", "qcom,sc7180-dp"; 2253 reg = <0x0 0xae90000 0x0 0x200>, 2254 <0x0 0xae90200 0x0 0x200>, 2255 <0x0 0xae90400 0x0 0x600>, 2256 <0x0 0xae91000 0x0 0x400>, 2257 <0x0 0xae91400 0x0 0x400>; 2258 interrupt-parent = <&mdss>; 2259 interrupts = <12>; 2260 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2261 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 2262 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 2263 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 2264 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 2265 clock-names = "core_iface", 2266 "core_aux", 2267 "ctrl_link", 2268 "ctrl_link_iface", 2269 "stream_pixel"; 2270 2271 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 2272 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 2273 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2274 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2275 2276 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 2277 phy-names = "dp"; 2278 2279 #sound-dai-cells = <0>; 2280 2281 operating-points-v2 = <&dp_opp_table>; 2282 power-domains = <&rpmhpd SM6350_CX>; 2283 2284 status = "disabled"; 2285 2286 ports { 2287 #address-cells = <1>; 2288 #size-cells = <0>; 2289 2290 port@0 { 2291 reg = <0>; 2292 2293 mdss_dp_in: endpoint { 2294 remote-endpoint = <&dpu_intf0_out>; 2295 }; 2296 }; 2297 2298 port@1 { 2299 reg = <1>; 2300 2301 mdss_dp_out: endpoint { 2302 }; 2303 }; 2304 }; 2305 2306 dp_opp_table: opp-table { 2307 compatible = "operating-points-v2"; 2308 2309 opp-160000000 { 2310 opp-hz = /bits/ 64 <160000000>; 2311 required-opps = <&rpmhpd_opp_low_svs>; 2312 }; 2313 2314 opp-270000000 { 2315 opp-hz = /bits/ 64 <270000000>; 2316 required-opps = <&rpmhpd_opp_svs>; 2317 }; 2318 2319 opp-540000000 { 2320 opp-hz = /bits/ 64 <540000000>; 2321 required-opps = <&rpmhpd_opp_svs_l1>; 2322 }; 2323 2324 opp-810000000 { 2325 opp-hz = /bits/ 64 <810000000>; 2326 required-opps = <&rpmhpd_opp_nom>; 2327 }; 2328 }; 2329 }; 2330 2331 mdss_dsi0: dsi@ae94000 { 2332 compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2333 reg = <0x0 0x0ae94000 0x0 0x400>; 2334 reg-names = "dsi_ctrl"; 2335 2336 interrupt-parent = <&mdss>; 2337 interrupts = <4>; 2338 2339 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2340 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2341 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2342 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2343 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2344 <&gcc GCC_DISP_AXI_CLK>; 2345 clock-names = "byte", 2346 "byte_intf", 2347 "pixel", 2348 "core", 2349 "iface", 2350 "bus"; 2351 2352 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2353 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2354 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2355 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 2356 2357 operating-points-v2 = <&mdss_dsi_opp_table>; 2358 power-domains = <&rpmhpd SM6350_MX>; 2359 2360 phys = <&mdss_dsi0_phy>; 2361 phy-names = "dsi"; 2362 2363 #address-cells = <1>; 2364 #size-cells = <0>; 2365 2366 status = "disabled"; 2367 2368 ports { 2369 #address-cells = <1>; 2370 #size-cells = <0>; 2371 2372 port@0 { 2373 reg = <0>; 2374 2375 mdss_dsi0_in: endpoint { 2376 remote-endpoint = <&dpu_intf1_out>; 2377 }; 2378 }; 2379 2380 port@1 { 2381 reg = <1>; 2382 2383 mdss_dsi0_out: endpoint { 2384 }; 2385 }; 2386 }; 2387 2388 mdss_dsi_opp_table: opp-table { 2389 compatible = "operating-points-v2"; 2390 2391 opp-187500000 { 2392 opp-hz = /bits/ 64 <187500000>; 2393 required-opps = <&rpmhpd_opp_low_svs>; 2394 }; 2395 2396 opp-300000000 { 2397 opp-hz = /bits/ 64 <300000000>; 2398 required-opps = <&rpmhpd_opp_svs>; 2399 }; 2400 2401 opp-358000000 { 2402 opp-hz = /bits/ 64 <358000000>; 2403 required-opps = <&rpmhpd_opp_svs_l1>; 2404 }; 2405 }; 2406 }; 2407 2408 mdss_dsi0_phy: phy@ae94400 { 2409 compatible = "qcom,dsi-phy-10nm"; 2410 reg = <0x0 0x0ae94400 0x0 0x200>, 2411 <0x0 0x0ae94600 0x0 0x280>, 2412 <0x0 0x0ae94a00 0x0 0x1e0>; 2413 reg-names = "dsi_phy", 2414 "dsi_phy_lane", 2415 "dsi_pll"; 2416 2417 #clock-cells = <1>; 2418 #phy-cells = <0>; 2419 2420 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2421 <&rpmhcc RPMH_CXO_CLK>; 2422 clock-names = "iface", "ref"; 2423 2424 status = "disabled"; 2425 }; 2426 }; 2427 2428 dispcc: clock-controller@af00000 { 2429 compatible = "qcom,sm6350-dispcc"; 2430 reg = <0x0 0x0af00000 0x0 0x20000>; 2431 clocks = <&rpmhcc RPMH_CXO_CLK>, 2432 <&gcc GCC_DISP_GPLL0_CLK>, 2433 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2434 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 2435 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2436 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2437 clock-names = "bi_tcxo", 2438 "gcc_disp_gpll0_clk", 2439 "dsi0_phy_pll_out_byteclk", 2440 "dsi0_phy_pll_out_dsiclk", 2441 "dp_phy_pll_link_clk", 2442 "dp_phy_pll_vco_div_clk"; 2443 #clock-cells = <1>; 2444 #reset-cells = <1>; 2445 #power-domain-cells = <1>; 2446 }; 2447 2448 pdc: interrupt-controller@b220000 { 2449 compatible = "qcom,sm6350-pdc", "qcom,pdc"; 2450 reg = <0x0 0x0b220000 0x0 0x30000>, <0x0 0x17c000f0 0x0 0x64>; 2451 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 2452 <125 63 1>, <126 655 12>, <138 139 15>; 2453 #interrupt-cells = <2>; 2454 interrupt-parent = <&intc>; 2455 interrupt-controller; 2456 }; 2457 2458 tsens0: thermal-sensor@c263000 { 2459 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 2460 reg = <0x0 0x0c263000 0x0 0x1ff>, /* TM */ 2461 <0x0 0x0c222000 0x0 0x8>; /* SROT */ 2462 #qcom,sensors = <16>; 2463 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 2464 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 2465 interrupt-names = "uplow", "critical"; 2466 #thermal-sensor-cells = <1>; 2467 }; 2468 2469 tsens1: thermal-sensor@c265000 { 2470 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 2471 reg = <0x0 0x0c265000 0x0 0x1ff>, /* TM */ 2472 <0x0 0x0c223000 0x0 0x8>; /* SROT */ 2473 #qcom,sensors = <16>; 2474 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 2475 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 2476 interrupt-names = "uplow", "critical"; 2477 #thermal-sensor-cells = <1>; 2478 }; 2479 2480 aoss_qmp: power-management@c300000 { 2481 compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp"; 2482 reg = <0x0 0x0c300000 0x0 0x1000>; 2483 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2484 IRQ_TYPE_EDGE_RISING>; 2485 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2486 2487 #clock-cells = <0>; 2488 }; 2489 2490 sram@c3f0000 { 2491 compatible = "qcom,rpmh-stats"; 2492 reg = <0x0 0x0c3f0000 0x0 0x400>; 2493 }; 2494 2495 spmi_bus: spmi@c440000 { 2496 compatible = "qcom,spmi-pmic-arb"; 2497 reg = <0x0 0x0c440000 0x0 0x1100>, 2498 <0x0 0x0c600000 0x0 0x2000000>, 2499 <0x0 0x0e600000 0x0 0x100000>, 2500 <0x0 0x0e700000 0x0 0xa0000>, 2501 <0x0 0x0c40a000 0x0 0x26000>; 2502 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2503 interrupt-names = "periph_irq"; 2504 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2505 qcom,ee = <0>; 2506 qcom,channel = <0>; 2507 #address-cells = <2>; 2508 #size-cells = <0>; 2509 interrupt-controller; 2510 #interrupt-cells = <4>; 2511 }; 2512 2513 tlmm: pinctrl@f100000 { 2514 compatible = "qcom,sm6350-tlmm"; 2515 reg = <0x0 0x0f100000 0x0 0x300000>; 2516 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 2517 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 2518 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 2519 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 2520 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 2521 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 2522 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 2523 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 2524 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 2525 gpio-controller; 2526 #gpio-cells = <2>; 2527 interrupt-controller; 2528 #interrupt-cells = <2>; 2529 gpio-ranges = <&tlmm 0 0 157>; 2530 wakeup-parent = <&pdc>; 2531 2532 cci0_default: cci0-default-state { 2533 pins = "gpio39", "gpio40"; 2534 function = "cci_i2c"; 2535 drive-strength = <2>; 2536 bias-pull-up; 2537 }; 2538 2539 cci0_sleep: cci0-sleep-state { 2540 pins = "gpio39", "gpio40"; 2541 function = "cci_i2c"; 2542 drive-strength = <2>; 2543 bias-pull-down; 2544 }; 2545 2546 cci1_default: cci1-default-state { 2547 pins = "gpio41", "gpio42"; 2548 function = "cci_i2c"; 2549 drive-strength = <2>; 2550 bias-pull-up; 2551 }; 2552 2553 cci1_sleep: cci1-sleep-state { 2554 pins = "gpio41", "gpio42"; 2555 function = "cci_i2c"; 2556 drive-strength = <2>; 2557 bias-pull-down; 2558 }; 2559 2560 cci2_default: cci2-default-state { 2561 pins = "gpio43", "gpio44"; 2562 function = "cci_i2c"; 2563 drive-strength = <2>; 2564 bias-pull-up; 2565 }; 2566 2567 cci2_sleep: cci2-sleep-state { 2568 pins = "gpio43", "gpio44"; 2569 function = "cci_i2c"; 2570 drive-strength = <2>; 2571 bias-pull-down; 2572 }; 2573 2574 sdc2_off_state: sdc2-off-state { 2575 clk-pins { 2576 pins = "sdc2_clk"; 2577 drive-strength = <2>; 2578 bias-disable; 2579 }; 2580 2581 cmd-pins { 2582 pins = "sdc2_cmd"; 2583 drive-strength = <2>; 2584 bias-pull-up; 2585 }; 2586 2587 data-pins { 2588 pins = "sdc2_data"; 2589 drive-strength = <2>; 2590 bias-pull-up; 2591 }; 2592 }; 2593 2594 sdc2_on_state: sdc2-on-state { 2595 clk-pins { 2596 pins = "sdc2_clk"; 2597 drive-strength = <16>; 2598 bias-disable; 2599 }; 2600 2601 cmd-pins { 2602 pins = "sdc2_cmd"; 2603 drive-strength = <10>; 2604 bias-pull-up; 2605 }; 2606 2607 data-pins { 2608 pins = "sdc2_data"; 2609 drive-strength = <10>; 2610 bias-pull-up; 2611 }; 2612 }; 2613 2614 qup_uart9_default: qup-uart9-default-state { 2615 pins = "gpio25", "gpio26"; 2616 function = "qup13_f2"; 2617 drive-strength = <2>; 2618 bias-disable; 2619 }; 2620 2621 qup_i2c0_default: qup-i2c0-default-state { 2622 pins = "gpio0", "gpio1"; 2623 function = "qup00"; 2624 drive-strength = <2>; 2625 bias-pull-up; 2626 }; 2627 2628 qup_i2c2_default: qup-i2c2-default-state { 2629 pins = "gpio45", "gpio46"; 2630 function = "qup02"; 2631 drive-strength = <2>; 2632 bias-pull-up; 2633 }; 2634 2635 qup_i2c6_default: qup-i2c6-default-state { 2636 pins = "gpio13", "gpio14"; 2637 function = "qup10"; 2638 drive-strength = <2>; 2639 bias-pull-up; 2640 }; 2641 2642 qup_i2c7_default: qup-i2c7-default-state { 2643 pins = "gpio27", "gpio28"; 2644 function = "qup11"; 2645 drive-strength = <2>; 2646 bias-pull-up; 2647 }; 2648 2649 qup_i2c8_default: qup-i2c8-default-state { 2650 pins = "gpio19", "gpio20"; 2651 function = "qup12"; 2652 drive-strength = <2>; 2653 bias-pull-up; 2654 }; 2655 2656 qup_i2c10_default: qup-i2c10-default-state { 2657 pins = "gpio4", "gpio5"; 2658 function = "qup14"; 2659 drive-strength = <2>; 2660 bias-pull-up; 2661 }; 2662 2663 qup_uart1_cts: qup-uart1-cts-default-state { 2664 pins = "gpio61"; 2665 function = "qup01"; 2666 drive-strength = <2>; 2667 bias-disable; 2668 }; 2669 2670 qup_uart1_rts: qup-uart1-rts-default-state { 2671 pins = "gpio62"; 2672 function = "qup01"; 2673 drive-strength = <2>; 2674 bias-pull-down; 2675 }; 2676 2677 qup_uart1_rx: qup-uart1-rx-default-state { 2678 pins = "gpio64"; 2679 function = "qup01"; 2680 drive-strength = <2>; 2681 bias-disable; 2682 }; 2683 2684 qup_uart1_tx: qup-uart1-tx-default-state { 2685 pins = "gpio63"; 2686 function = "qup01"; 2687 drive-strength = <2>; 2688 bias-pull-up; 2689 }; 2690 }; 2691 2692 apps_smmu: iommu@15000000 { 2693 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500"; 2694 reg = <0x0 0x15000000 0x0 0x100000>; 2695 #iommu-cells = <2>; 2696 #global-interrupts = <1>; 2697 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 2698 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 2699 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 2700 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2701 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2702 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2703 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2704 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2705 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2706 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2707 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2708 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2709 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2710 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2711 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2712 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2713 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2714 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2715 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2716 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2717 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2718 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2719 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2720 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2721 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2722 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 2723 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 2724 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 2725 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 2726 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 2727 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 2728 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 2729 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 2730 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 2731 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 2732 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 2733 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 2734 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 2735 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 2736 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 2737 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 2738 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 2739 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2740 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2741 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2742 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2743 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2744 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2745 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2746 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2747 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2748 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2749 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2750 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2751 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2752 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2753 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2754 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2755 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2756 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2757 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2758 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2759 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2760 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2761 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2762 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2763 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2764 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2765 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2766 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2767 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 2768 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2769 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 2770 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 2771 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 2772 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 2773 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 2774 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 2775 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 2776 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 2777 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 2778 dma-coherent; 2779 }; 2780 2781 intc: interrupt-controller@17a00000 { 2782 compatible = "arm,gic-v3"; 2783 #interrupt-cells = <3>; 2784 interrupt-controller; 2785 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 2786 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 2787 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; 2788 }; 2789 2790 watchdog@17c10000 { 2791 compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt"; 2792 reg = <0x0 0x17c10000 0x0 0x1000>; 2793 clocks = <&sleep_clk>; 2794 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 2795 }; 2796 2797 timer@17c20000 { 2798 compatible = "arm,armv7-timer-mem"; 2799 reg = <0x0 0x17c20000 0x0 0x1000>; 2800 clock-frequency = <19200000>; 2801 #address-cells = <1>; 2802 #size-cells = <1>; 2803 ranges = <0 0 0 0x20000000>; 2804 2805 frame@17c21000 { 2806 frame-number = <0>; 2807 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2808 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 2809 reg = <0x17c21000 0x1000>, 2810 <0x17c22000 0x1000>; 2811 }; 2812 2813 frame@17c23000 { 2814 frame-number = <1>; 2815 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2816 reg = <0x17c23000 0x1000>; 2817 status = "disabled"; 2818 }; 2819 2820 frame@17c25000 { 2821 frame-number = <2>; 2822 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2823 reg = <0x17c25000 0x1000>; 2824 status = "disabled"; 2825 }; 2826 2827 frame@17c27000 { 2828 frame-number = <3>; 2829 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2830 reg = <0x17c27000 0x1000>; 2831 status = "disabled"; 2832 }; 2833 2834 frame@17c29000 { 2835 frame-number = <4>; 2836 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2837 reg = <0x17c29000 0x1000>; 2838 status = "disabled"; 2839 }; 2840 2841 frame@17c2b000 { 2842 frame-number = <5>; 2843 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2844 reg = <0x17c2b000 0x1000>; 2845 status = "disabled"; 2846 }; 2847 2848 frame@17c2d000 { 2849 frame-number = <6>; 2850 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2851 reg = <0x17c2d000 0x1000>; 2852 status = "disabled"; 2853 }; 2854 }; 2855 2856 apps_rsc: rsc@18200000 { 2857 compatible = "qcom,rpmh-rsc"; 2858 label = "apps_rsc"; 2859 reg = <0x0 0x18200000 0x0 0x10000>, 2860 <0x0 0x18210000 0x0 0x10000>, 2861 <0x0 0x18220000 0x0 0x10000>; 2862 reg-names = "drv-0", "drv-1", "drv-2"; 2863 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2864 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2865 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 2866 qcom,tcs-offset = <0xd00>; 2867 qcom,drv-id = <2>; 2868 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 2869 <WAKE_TCS 3>, <CONTROL_TCS 1>; 2870 power-domains = <&cluster_pd>; 2871 2872 rpmhcc: clock-controller { 2873 compatible = "qcom,sm6350-rpmh-clk"; 2874 #clock-cells = <1>; 2875 clock-names = "xo"; 2876 clocks = <&xo_board>; 2877 }; 2878 2879 rpmhpd: power-controller { 2880 compatible = "qcom,sm6350-rpmhpd"; 2881 #power-domain-cells = <1>; 2882 operating-points-v2 = <&rpmhpd_opp_table>; 2883 2884 rpmhpd_opp_table: opp-table { 2885 compatible = "operating-points-v2"; 2886 2887 rpmhpd_opp_ret: opp1 { 2888 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 2889 }; 2890 2891 rpmhpd_opp_min_svs: opp2 { 2892 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2893 }; 2894 2895 rpmhpd_opp_low_svs: opp3 { 2896 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2897 }; 2898 2899 rpmhpd_opp_svs: opp4 { 2900 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2901 }; 2902 2903 rpmhpd_opp_svs_l1: opp5 { 2904 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2905 }; 2906 2907 rpmhpd_opp_nom: opp6 { 2908 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2909 }; 2910 2911 rpmhpd_opp_nom_l1: opp7 { 2912 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2913 }; 2914 2915 rpmhpd_opp_nom_l2: opp8 { 2916 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 2917 }; 2918 2919 rpmhpd_opp_turbo: opp9 { 2920 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2921 }; 2922 2923 rpmhpd_opp_turbo_l1: opp10 { 2924 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2925 }; 2926 }; 2927 }; 2928 2929 apps_bcm_voter: bcm-voter { 2930 compatible = "qcom,bcm-voter"; 2931 }; 2932 }; 2933 2934 osm_l3: interconnect@18321000 { 2935 compatible = "qcom,sm6350-osm-l3", "qcom,osm-l3"; 2936 reg = <0x0 0x18321000 0x0 0x1000>; 2937 2938 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2939 clock-names = "xo", "alternate"; 2940 2941 #interconnect-cells = <1>; 2942 }; 2943 2944 cpufreq_hw: cpufreq@18323000 { 2945 compatible = "qcom,sm6350-cpufreq-hw", "qcom,cpufreq-hw"; 2946 reg = <0x0 0x18323000 0x0 0x1000>, <0x0 0x18325800 0x0 0x1000>; 2947 reg-names = "freq-domain0", "freq-domain1"; 2948 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2949 clock-names = "xo", "alternate"; 2950 2951 #freq-domain-cells = <1>; 2952 #clock-cells = <1>; 2953 }; 2954 2955 wifi: wifi@18800000 { 2956 compatible = "qcom,wcn3990-wifi"; 2957 reg = <0x0 0x18800000 0x0 0x800000>; 2958 reg-names = "membase"; 2959 memory-region = <&wlan_fw_mem>; 2960 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 2961 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 2962 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 2963 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 2964 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2965 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 2966 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 2967 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2968 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2969 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2970 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2971 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 2972 iommus = <&apps_smmu 0x20 0x1>; 2973 qcom,msa-fixed-perm; 2974 status = "disabled"; 2975 }; 2976 }; 2977 2978 sound: sound { 2979 }; 2980 2981 thermal-zones { 2982 aoss0-thermal { 2983 thermal-sensors = <&tsens0 0>; 2984 2985 trips { 2986 aoss0-crit { 2987 temperature = <125000>; 2988 hysteresis = <0>; 2989 type = "critical"; 2990 }; 2991 }; 2992 }; 2993 2994 aoss1-thermal { 2995 thermal-sensors = <&tsens1 0>; 2996 2997 trips { 2998 aoss1-crit { 2999 temperature = <125000>; 3000 hysteresis = <0>; 3001 type = "critical"; 3002 }; 3003 }; 3004 }; 3005 3006 audio-thermal { 3007 thermal-sensors = <&tsens1 2>; 3008 3009 trips { 3010 audio-crit { 3011 temperature = <125000>; 3012 hysteresis = <0>; 3013 type = "critical"; 3014 }; 3015 }; 3016 }; 3017 3018 camera-thermal { 3019 thermal-sensors = <&tsens1 5>; 3020 3021 trips { 3022 camera-crit { 3023 temperature = <125000>; 3024 hysteresis = <0>; 3025 type = "critical"; 3026 }; 3027 }; 3028 }; 3029 3030 cpu0-thermal { 3031 thermal-sensors = <&tsens0 1>; 3032 3033 trips { 3034 cpu0_alert0: trip-point0 { 3035 temperature = <95000>; 3036 hysteresis = <2000>; 3037 type = "passive"; 3038 }; 3039 3040 cpu0-crit { 3041 temperature = <115000>; 3042 hysteresis = <0>; 3043 type = "critical"; 3044 }; 3045 }; 3046 3047 cooling-maps { 3048 map0 { 3049 trip = <&cpu0_alert0>; 3050 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3051 }; 3052 }; 3053 }; 3054 3055 cpu1-thermal { 3056 thermal-sensors = <&tsens0 2>; 3057 3058 trips { 3059 cpu1_alert0: trip-point0 { 3060 temperature = <95000>; 3061 hysteresis = <2000>; 3062 type = "passive"; 3063 }; 3064 3065 cpu1-crit { 3066 temperature = <115000>; 3067 hysteresis = <0>; 3068 type = "critical"; 3069 }; 3070 }; 3071 3072 cooling-maps { 3073 map0 { 3074 trip = <&cpu1_alert0>; 3075 cooling-device = <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3076 }; 3077 }; 3078 }; 3079 3080 cpu2-thermal { 3081 thermal-sensors = <&tsens0 3>; 3082 3083 trips { 3084 cpu2_alert0: trip-point0 { 3085 temperature = <95000>; 3086 hysteresis = <2000>; 3087 type = "passive"; 3088 }; 3089 3090 cpu2-crit { 3091 temperature = <115000>; 3092 hysteresis = <0>; 3093 type = "critical"; 3094 }; 3095 }; 3096 3097 cooling-maps { 3098 map0 { 3099 trip = <&cpu2_alert0>; 3100 cooling-device = <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3101 }; 3102 }; 3103 }; 3104 3105 cpu3-thermal { 3106 thermal-sensors = <&tsens0 4>; 3107 3108 trips { 3109 cpu3_alert0: trip-point0 { 3110 temperature = <95000>; 3111 hysteresis = <2000>; 3112 type = "passive"; 3113 }; 3114 3115 cpu3-crit { 3116 temperature = <115000>; 3117 hysteresis = <0>; 3118 type = "critical"; 3119 }; 3120 }; 3121 3122 cooling-maps { 3123 map0 { 3124 trip = <&cpu3_alert0>; 3125 cooling-device = <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3126 }; 3127 }; 3128 }; 3129 3130 cpu4-thermal { 3131 thermal-sensors = <&tsens0 5>; 3132 3133 trips { 3134 cpu4_alert0: trip-point0 { 3135 temperature = <95000>; 3136 hysteresis = <2000>; 3137 type = "passive"; 3138 }; 3139 3140 cpu4-crit { 3141 temperature = <115000>; 3142 hysteresis = <0>; 3143 type = "critical"; 3144 }; 3145 }; 3146 3147 cooling-maps { 3148 map0 { 3149 trip = <&cpu4_alert0>; 3150 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3151 }; 3152 }; 3153 }; 3154 3155 cpu5-thermal { 3156 thermal-sensors = <&tsens0 6>; 3157 3158 trips { 3159 cpu5_alert0: trip-point0 { 3160 temperature = <95000>; 3161 hysteresis = <2000>; 3162 type = "passive"; 3163 }; 3164 3165 cpu5-crit { 3166 temperature = <115000>; 3167 hysteresis = <0>; 3168 type = "critical"; 3169 }; 3170 }; 3171 3172 cooling-maps { 3173 map0 { 3174 trip = <&cpu5_alert0>; 3175 cooling-device = <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3176 }; 3177 }; 3178 }; 3179 3180 cpu6-left-thermal { 3181 thermal-sensors = <&tsens0 9>; 3182 3183 trips { 3184 cpu6_left_alert0: trip-point0 { 3185 temperature = <95000>; 3186 hysteresis = <2000>; 3187 type = "passive"; 3188 }; 3189 3190 cpu6-left-crit { 3191 temperature = <115000>; 3192 hysteresis = <0>; 3193 type = "critical"; 3194 }; 3195 }; 3196 3197 cooling-maps { 3198 map0 { 3199 trip = <&cpu6_left_alert0>; 3200 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3201 }; 3202 }; 3203 }; 3204 3205 cpu6-right-thermal { 3206 thermal-sensors = <&tsens0 10>; 3207 3208 trips { 3209 cpu6_right_alert0: trip-point0 { 3210 temperature = <95000>; 3211 hysteresis = <2000>; 3212 type = "passive"; 3213 }; 3214 3215 cpu6-right-crit { 3216 temperature = <115000>; 3217 hysteresis = <0>; 3218 type = "critical"; 3219 }; 3220 }; 3221 3222 cooling-maps { 3223 map0 { 3224 trip = <&cpu6_right_alert0>; 3225 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3226 }; 3227 }; 3228 }; 3229 3230 cpu7-left-thermal { 3231 thermal-sensors = <&tsens0 11>; 3232 3233 trips { 3234 cpu7_left_alert0: trip-point0 { 3235 temperature = <95000>; 3236 hysteresis = <2000>; 3237 type = "passive"; 3238 }; 3239 3240 cpu7-left-crit { 3241 temperature = <115000>; 3242 hysteresis = <0>; 3243 type = "critical"; 3244 }; 3245 }; 3246 3247 cooling-maps { 3248 map0 { 3249 trip = <&cpu7_left_alert0>; 3250 cooling-device = <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3251 }; 3252 }; 3253 }; 3254 3255 cpu7-right-thermal { 3256 thermal-sensors = <&tsens0 12>; 3257 3258 trips { 3259 cpu7_right_alert0: trip-point0 { 3260 temperature = <95000>; 3261 hysteresis = <2000>; 3262 type = "passive"; 3263 }; 3264 3265 cpu7-right-crit { 3266 temperature = <115000>; 3267 hysteresis = <0>; 3268 type = "critical"; 3269 }; 3270 }; 3271 3272 cooling-maps { 3273 map0 { 3274 trip = <&cpu7_right_alert0>; 3275 cooling-device = <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3276 }; 3277 }; 3278 }; 3279 3280 cpuss0-thermal { 3281 thermal-sensors = <&tsens0 7>; 3282 3283 trips { 3284 cpuss0-crit { 3285 temperature = <125000>; 3286 hysteresis = <0>; 3287 type = "critical"; 3288 }; 3289 }; 3290 }; 3291 3292 cpuss1-thermal { 3293 thermal-sensors = <&tsens0 8>; 3294 3295 trips { 3296 cpuss1-crit { 3297 temperature = <125000>; 3298 hysteresis = <0>; 3299 type = "critical"; 3300 }; 3301 }; 3302 }; 3303 3304 cwlan-thermal { 3305 thermal-sensors = <&tsens1 1>; 3306 3307 trips { 3308 cwlan-crit { 3309 temperature = <125000>; 3310 hysteresis = <0>; 3311 type = "critical"; 3312 }; 3313 }; 3314 }; 3315 3316 ddr-thermal { 3317 thermal-sensors = <&tsens1 3>; 3318 3319 trips { 3320 ddr-crit { 3321 temperature = <125000>; 3322 hysteresis = <0>; 3323 type = "critical"; 3324 }; 3325 }; 3326 }; 3327 3328 gpuss0-thermal { 3329 polling-delay-passive = <250>; 3330 3331 thermal-sensors = <&tsens0 13>; 3332 3333 trips { 3334 gpuss0_alert0: trip-point0 { 3335 temperature = <85000>; 3336 hysteresis = <2000>; 3337 type = "passive"; 3338 }; 3339 3340 gpuss0-crit { 3341 temperature = <110000>; 3342 hysteresis = <1000>; 3343 type = "critical"; 3344 }; 3345 }; 3346 3347 cooling-maps { 3348 map0 { 3349 trip = <&gpuss0_alert0>; 3350 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3351 }; 3352 }; 3353 }; 3354 3355 gpuss1-thermal { 3356 polling-delay-passive = <250>; 3357 3358 thermal-sensors = <&tsens0 14>; 3359 3360 trips { 3361 gpuss1_alert0: trip-point0 { 3362 temperature = <85000>; 3363 hysteresis = <2000>; 3364 type = "passive"; 3365 }; 3366 3367 gpuss1-crit { 3368 temperature = <110000>; 3369 hysteresis = <1000>; 3370 type = "critical"; 3371 }; 3372 }; 3373 3374 cooling-maps { 3375 map0 { 3376 trip = <&gpuss1_alert0>; 3377 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3378 }; 3379 }; 3380 }; 3381 3382 modem-core0-thermal { 3383 thermal-sensors = <&tsens1 6>; 3384 3385 trips { 3386 modem-core0-crit { 3387 temperature = <125000>; 3388 hysteresis = <0>; 3389 type = "critical"; 3390 }; 3391 }; 3392 }; 3393 3394 modem-core1-thermal { 3395 thermal-sensors = <&tsens1 7>; 3396 3397 trips { 3398 modem-core1-crit { 3399 temperature = <125000>; 3400 hysteresis = <0>; 3401 type = "critical"; 3402 }; 3403 }; 3404 }; 3405 3406 modem-scl-thermal { 3407 thermal-sensors = <&tsens1 9>; 3408 3409 trips { 3410 modem-scl-crit { 3411 temperature = <125000>; 3412 hysteresis = <0>; 3413 type = "critical"; 3414 }; 3415 }; 3416 }; 3417 3418 modem-vec-thermal { 3419 thermal-sensors = <&tsens1 8>; 3420 3421 trips { 3422 modem-vec-crit { 3423 temperature = <125000>; 3424 hysteresis = <0>; 3425 type = "critical"; 3426 }; 3427 }; 3428 }; 3429 3430 npu-thermal { 3431 thermal-sensors = <&tsens1 10>; 3432 3433 trips { 3434 npu-crit { 3435 temperature = <125000>; 3436 hysteresis = <0>; 3437 type = "critical"; 3438 }; 3439 }; 3440 }; 3441 3442 q6-hvx-thermal { 3443 thermal-sensors = <&tsens1 4>; 3444 3445 trips { 3446 q6-hvx-crit { 3447 temperature = <125000>; 3448 hysteresis = <0>; 3449 type = "critical"; 3450 }; 3451 }; 3452 }; 3453 3454 video-thermal { 3455 thermal-sensors = <&tsens1 11>; 3456 3457 trips { 3458 video-crit { 3459 temperature = <125000>; 3460 hysteresis = <0>; 3461 type = "critical"; 3462 }; 3463 }; 3464 }; 3465 }; 3466 3467 timer { 3468 compatible = "arm,armv8-timer"; 3469 clock-frequency = <19200000>; 3470 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3471 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3472 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3473 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 3474 }; 3475}; 3476