1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> 4 * Copyright (c) 2022, Luca Weiss <luca.weiss@fairphone.com> 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sm6350.h> 8#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 9#include <dt-bindings/clock/qcom,gcc-sm6350.h> 10#include <dt-bindings/clock/qcom,gpucc-sm6350.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,sm6350-camcc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interconnect/qcom,icc.h> 16#include <dt-bindings/interconnect/qcom,osm-l3.h> 17#include <dt-bindings/interconnect/qcom,sm6350.h> 18#include <dt-bindings/interrupt-controller/arm-gic.h> 19#include <dt-bindings/mailbox/qcom-ipcc.h> 20#include <dt-bindings/phy/phy-qcom-qmp.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23#include <dt-bindings/thermal/thermal.h> 24 25/ { 26 interrupt-parent = <&intc>; 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 clocks { 31 xo_board: xo-board { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <76800000>; 35 clock-output-names = "xo_board"; 36 }; 37 38 sleep_clk: sleep-clk { 39 compatible = "fixed-clock"; 40 clock-frequency = <32764>; 41 #clock-cells = <0>; 42 }; 43 }; 44 45 cpus { 46 #address-cells = <2>; 47 #size-cells = <0>; 48 49 cpu0: cpu@0 { 50 device_type = "cpu"; 51 compatible = "qcom,kryo560"; 52 reg = <0x0 0x0>; 53 clocks = <&cpufreq_hw 0>; 54 enable-method = "psci"; 55 capacity-dmips-mhz = <1024>; 56 dynamic-power-coefficient = <100>; 57 next-level-cache = <&l2_0>; 58 qcom,freq-domain = <&cpufreq_hw 0>; 59 operating-points-v2 = <&cpu0_opp_table>; 60 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 61 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 62 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 63 power-domains = <&cpu_pd0>; 64 power-domain-names = "psci"; 65 #cooling-cells = <2>; 66 l2_0: l2-cache { 67 compatible = "cache"; 68 cache-level = <2>; 69 cache-unified; 70 next-level-cache = <&l3_0>; 71 l3_0: l3-cache { 72 compatible = "cache"; 73 cache-level = <3>; 74 cache-unified; 75 }; 76 }; 77 }; 78 79 cpu1: cpu@100 { 80 device_type = "cpu"; 81 compatible = "qcom,kryo560"; 82 reg = <0x0 0x100>; 83 clocks = <&cpufreq_hw 0>; 84 enable-method = "psci"; 85 capacity-dmips-mhz = <1024>; 86 dynamic-power-coefficient = <100>; 87 next-level-cache = <&l2_100>; 88 qcom,freq-domain = <&cpufreq_hw 0>; 89 operating-points-v2 = <&cpu0_opp_table>; 90 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 91 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 92 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 93 power-domains = <&cpu_pd1>; 94 power-domain-names = "psci"; 95 #cooling-cells = <2>; 96 l2_100: l2-cache { 97 compatible = "cache"; 98 cache-level = <2>; 99 cache-unified; 100 next-level-cache = <&l3_0>; 101 }; 102 }; 103 104 cpu2: cpu@200 { 105 device_type = "cpu"; 106 compatible = "qcom,kryo560"; 107 reg = <0x0 0x200>; 108 clocks = <&cpufreq_hw 0>; 109 enable-method = "psci"; 110 capacity-dmips-mhz = <1024>; 111 dynamic-power-coefficient = <100>; 112 next-level-cache = <&l2_200>; 113 qcom,freq-domain = <&cpufreq_hw 0>; 114 operating-points-v2 = <&cpu0_opp_table>; 115 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 116 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 117 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 118 power-domains = <&cpu_pd2>; 119 power-domain-names = "psci"; 120 #cooling-cells = <2>; 121 l2_200: l2-cache { 122 compatible = "cache"; 123 cache-level = <2>; 124 cache-unified; 125 next-level-cache = <&l3_0>; 126 }; 127 }; 128 129 cpu3: cpu@300 { 130 device_type = "cpu"; 131 compatible = "qcom,kryo560"; 132 reg = <0x0 0x300>; 133 clocks = <&cpufreq_hw 0>; 134 enable-method = "psci"; 135 capacity-dmips-mhz = <1024>; 136 dynamic-power-coefficient = <100>; 137 next-level-cache = <&l2_300>; 138 qcom,freq-domain = <&cpufreq_hw 0>; 139 operating-points-v2 = <&cpu0_opp_table>; 140 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 141 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 142 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 143 power-domains = <&cpu_pd3>; 144 power-domain-names = "psci"; 145 #cooling-cells = <2>; 146 l2_300: l2-cache { 147 compatible = "cache"; 148 cache-level = <2>; 149 cache-unified; 150 next-level-cache = <&l3_0>; 151 }; 152 }; 153 154 cpu4: cpu@400 { 155 device_type = "cpu"; 156 compatible = "qcom,kryo560"; 157 reg = <0x0 0x400>; 158 clocks = <&cpufreq_hw 0>; 159 enable-method = "psci"; 160 capacity-dmips-mhz = <1024>; 161 dynamic-power-coefficient = <100>; 162 next-level-cache = <&l2_400>; 163 qcom,freq-domain = <&cpufreq_hw 0>; 164 operating-points-v2 = <&cpu0_opp_table>; 165 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 166 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 167 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 168 power-domains = <&cpu_pd4>; 169 power-domain-names = "psci"; 170 #cooling-cells = <2>; 171 l2_400: l2-cache { 172 compatible = "cache"; 173 cache-level = <2>; 174 cache-unified; 175 next-level-cache = <&l3_0>; 176 }; 177 }; 178 179 cpu5: cpu@500 { 180 device_type = "cpu"; 181 compatible = "qcom,kryo560"; 182 reg = <0x0 0x500>; 183 clocks = <&cpufreq_hw 0>; 184 enable-method = "psci"; 185 capacity-dmips-mhz = <1024>; 186 dynamic-power-coefficient = <100>; 187 next-level-cache = <&l2_500>; 188 qcom,freq-domain = <&cpufreq_hw 0>; 189 operating-points-v2 = <&cpu0_opp_table>; 190 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 191 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 192 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 193 power-domains = <&cpu_pd5>; 194 power-domain-names = "psci"; 195 #cooling-cells = <2>; 196 l2_500: l2-cache { 197 compatible = "cache"; 198 cache-level = <2>; 199 cache-unified; 200 next-level-cache = <&l3_0>; 201 }; 202 }; 203 204 cpu6: cpu@600 { 205 device_type = "cpu"; 206 compatible = "qcom,kryo560"; 207 reg = <0x0 0x600>; 208 clocks = <&cpufreq_hw 1>; 209 enable-method = "psci"; 210 capacity-dmips-mhz = <1894>; 211 dynamic-power-coefficient = <703>; 212 next-level-cache = <&l2_600>; 213 qcom,freq-domain = <&cpufreq_hw 1>; 214 operating-points-v2 = <&cpu6_opp_table>; 215 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 216 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 217 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 218 power-domains = <&cpu_pd6>; 219 power-domain-names = "psci"; 220 #cooling-cells = <2>; 221 l2_600: l2-cache { 222 compatible = "cache"; 223 cache-level = <2>; 224 cache-unified; 225 next-level-cache = <&l3_0>; 226 }; 227 }; 228 229 cpu7: cpu@700 { 230 device_type = "cpu"; 231 compatible = "qcom,kryo560"; 232 reg = <0x0 0x700>; 233 clocks = <&cpufreq_hw 1>; 234 enable-method = "psci"; 235 capacity-dmips-mhz = <1894>; 236 dynamic-power-coefficient = <703>; 237 next-level-cache = <&l2_700>; 238 qcom,freq-domain = <&cpufreq_hw 1>; 239 operating-points-v2 = <&cpu6_opp_table>; 240 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 241 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 242 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 243 power-domains = <&cpu_pd7>; 244 power-domain-names = "psci"; 245 #cooling-cells = <2>; 246 l2_700: l2-cache { 247 compatible = "cache"; 248 cache-level = <2>; 249 cache-unified; 250 next-level-cache = <&l3_0>; 251 }; 252 }; 253 254 cpu-map { 255 cluster0 { 256 core0 { 257 cpu = <&cpu0>; 258 }; 259 260 core1 { 261 cpu = <&cpu1>; 262 }; 263 264 core2 { 265 cpu = <&cpu2>; 266 }; 267 268 core3 { 269 cpu = <&cpu3>; 270 }; 271 272 core4 { 273 cpu = <&cpu4>; 274 }; 275 276 core5 { 277 cpu = <&cpu5>; 278 }; 279 280 core6 { 281 cpu = <&cpu6>; 282 }; 283 284 core7 { 285 cpu = <&cpu7>; 286 }; 287 }; 288 }; 289 290 domain-idle-states { 291 cluster_sleep_pc: cluster-sleep-0 { 292 compatible = "domain-idle-state"; 293 arm,psci-suspend-param = <0x41000044>; 294 entry-latency-us = <2752>; 295 exit-latency-us = <3048>; 296 min-residency-us = <6118>; 297 }; 298 299 cluster_sleep_cx_ret: cluster-sleep-1 { 300 compatible = "domain-idle-state"; 301 arm,psci-suspend-param = <0x41001244>; 302 entry-latency-us = <3638>; 303 exit-latency-us = <4562>; 304 min-residency-us = <8467>; 305 }; 306 307 cluster_aoss_sleep: cluster-sleep-2 { 308 compatible = "domain-idle-state"; 309 arm,psci-suspend-param = <0x4100b244>; 310 entry-latency-us = <3263>; 311 exit-latency-us = <6562>; 312 min-residency-us = <9987>; 313 }; 314 }; 315 316 cpu_idle_states: idle-states { 317 entry-method = "psci"; 318 319 little_cpu_sleep_0: cpu-sleep-0-0 { 320 compatible = "arm,idle-state"; 321 idle-state-name = "little-power-collapse"; 322 arm,psci-suspend-param = <0x40000003>; 323 entry-latency-us = <549>; 324 exit-latency-us = <901>; 325 min-residency-us = <1774>; 326 local-timer-stop; 327 }; 328 329 little_cpu_sleep_1: cpu-sleep-0-1 { 330 compatible = "arm,idle-state"; 331 idle-state-name = "little-rail-power-collapse"; 332 arm,psci-suspend-param = <0x40000004>; 333 entry-latency-us = <702>; 334 exit-latency-us = <915>; 335 min-residency-us = <4001>; 336 local-timer-stop; 337 }; 338 339 big_cpu_sleep_0: cpu-sleep-1-0 { 340 compatible = "arm,idle-state"; 341 idle-state-name = "big-power-collapse"; 342 arm,psci-suspend-param = <0x40000003>; 343 entry-latency-us = <523>; 344 exit-latency-us = <1244>; 345 min-residency-us = <2207>; 346 local-timer-stop; 347 }; 348 349 big_cpu_sleep_1: cpu-sleep-1-1 { 350 compatible = "arm,idle-state"; 351 idle-state-name = "big-rail-power-collapse"; 352 arm,psci-suspend-param = <0x40000004>; 353 entry-latency-us = <526>; 354 exit-latency-us = <1854>; 355 min-residency-us = <5555>; 356 local-timer-stop; 357 }; 358 }; 359 }; 360 361 firmware { 362 scm: scm { 363 compatible = "qcom,scm-sm6350", "qcom,scm"; 364 #reset-cells = <1>; 365 }; 366 }; 367 368 memory@80000000 { 369 device_type = "memory"; 370 /* We expect the bootloader to fill in the size */ 371 reg = <0x0 0x80000000 0x0 0x0>; 372 }; 373 374 cpu0_opp_table: opp-table-cpu0 { 375 compatible = "operating-points-v2"; 376 opp-shared; 377 378 opp-300000000 { 379 opp-hz = /bits/ 64 <300000000>; 380 /* DDR: 4-wide, 2 channels, double data rate, L3: 16-wide, 2 channels */ 381 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; 382 }; 383 384 opp-576000000 { 385 opp-hz = /bits/ 64 <576000000>; 386 opp-peak-kBps = <(547000 * 4 * 2 * 2) (556800 * 16 * 2)>; 387 }; 388 389 opp-768000000 { 390 opp-hz = /bits/ 64 <768000000>; 391 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; 392 }; 393 394 opp-1017600000 { 395 opp-hz = /bits/ 64 <1017600000>; 396 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; 397 }; 398 399 opp-1248000000 { 400 opp-hz = /bits/ 64 <1248000000>; 401 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; 402 }; 403 404 opp-1324800000 { 405 opp-hz = /bits/ 64 <1324800000>; 406 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1286400 * 16 * 2)>; 407 }; 408 409 opp-1516800000 { 410 opp-hz = /bits/ 64 <1516800000>; 411 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 412 }; 413 414 opp-1612800000 { 415 opp-hz = /bits/ 64 <1612800000>; 416 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 417 }; 418 419 opp-1708800000 { 420 opp-hz = /bits/ 64 <1708800000>; 421 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 422 }; 423 }; 424 425 cpu6_opp_table: opp-table-cpu6 { 426 compatible = "operating-points-v2"; 427 opp-shared; 428 429 opp-300000000 { 430 opp-hz = /bits/ 64 <300000000>; 431 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; 432 }; 433 434 opp-787200000 { 435 opp-hz = /bits/ 64 <787200000>; 436 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; 437 }; 438 439 opp-979200000 { 440 opp-hz = /bits/ 64 <979200000>; 441 opp-peak-kBps = <(768000 * 4 * 2 * 2) (940800 * 16 * 2)>; 442 }; 443 444 opp-1036800000 { 445 opp-hz = /bits/ 64 <1036800000>; 446 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; 447 }; 448 449 opp-1248000000 { 450 opp-hz = /bits/ 64 <1248000000>; 451 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; 452 }; 453 454 opp-1401600000 { 455 opp-hz = /bits/ 64 <1401600000>; 456 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1401600 * 16 * 2)>; 457 }; 458 459 opp-1555200000 { 460 opp-hz = /bits/ 64 <1555200000>; 461 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 462 }; 463 464 opp-1766400000 { 465 opp-hz = /bits/ 64 <1766400000>; 466 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 467 }; 468 469 opp-1900800000 { 470 opp-hz = /bits/ 64 <1900800000>; 471 opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 472 }; 473 474 opp-2073600000 { 475 opp-hz = /bits/ 64 <2073600000>; 476 opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 477 }; 478 }; 479 480 qup_opp_table: opp-table-qup { 481 compatible = "operating-points-v2"; 482 483 opp-75000000 { 484 opp-hz = /bits/ 64 <75000000>; 485 required-opps = <&rpmhpd_opp_low_svs>; 486 }; 487 488 opp-100000000 { 489 opp-hz = /bits/ 64 <100000000>; 490 required-opps = <&rpmhpd_opp_svs>; 491 }; 492 493 opp-128000000 { 494 opp-hz = /bits/ 64 <128000000>; 495 required-opps = <&rpmhpd_opp_nom>; 496 }; 497 }; 498 499 pmu { 500 compatible = "arm,armv8-pmuv3"; 501 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>; 502 }; 503 504 psci { 505 compatible = "arm,psci-1.0"; 506 method = "smc"; 507 508 cpu_pd0: power-domain-cpu0 { 509 #power-domain-cells = <0>; 510 power-domains = <&cluster_pd>; 511 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 512 }; 513 514 cpu_pd1: power-domain-cpu1 { 515 #power-domain-cells = <0>; 516 power-domains = <&cluster_pd>; 517 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 518 }; 519 520 cpu_pd2: power-domain-cpu2 { 521 #power-domain-cells = <0>; 522 power-domains = <&cluster_pd>; 523 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 524 }; 525 526 cpu_pd3: power-domain-cpu3 { 527 #power-domain-cells = <0>; 528 power-domains = <&cluster_pd>; 529 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 530 }; 531 532 cpu_pd4: power-domain-cpu4 { 533 #power-domain-cells = <0>; 534 power-domains = <&cluster_pd>; 535 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 536 }; 537 538 cpu_pd5: power-domain-cpu5 { 539 #power-domain-cells = <0>; 540 power-domains = <&cluster_pd>; 541 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 542 }; 543 544 cpu_pd6: power-domain-cpu6 { 545 #power-domain-cells = <0>; 546 power-domains = <&cluster_pd>; 547 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 548 }; 549 550 cpu_pd7: power-domain-cpu7 { 551 #power-domain-cells = <0>; 552 power-domains = <&cluster_pd>; 553 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 554 }; 555 556 cluster_pd: power-domain-cpu-cluster0 { 557 #power-domain-cells = <0>; 558 domain-idle-states = <&cluster_sleep_pc 559 &cluster_sleep_cx_ret 560 &cluster_aoss_sleep>; 561 }; 562 }; 563 564 reserved_memory: reserved-memory { 565 #address-cells = <2>; 566 #size-cells = <2>; 567 ranges; 568 569 hyp_mem: memory@80000000 { 570 reg = <0x0 0x80000000 0x0 0x600000>; 571 no-map; 572 }; 573 574 xbl_aop_mem: memory@80700000 { 575 reg = <0x0 0x80700000 0x0 0x160000>; 576 no-map; 577 }; 578 579 cmd_db: memory@80860000 { 580 compatible = "qcom,cmd-db"; 581 reg = <0x0 0x80860000 0x0 0x20000>; 582 no-map; 583 }; 584 585 sec_apps_mem: memory@808ff000 { 586 reg = <0x0 0x808ff000 0x0 0x1000>; 587 no-map; 588 }; 589 590 smem_mem: memory@80900000 { 591 reg = <0x0 0x80900000 0x0 0x200000>; 592 no-map; 593 }; 594 595 cdsp_sec_mem: memory@80b00000 { 596 reg = <0x0 0x80b00000 0x0 0x1e00000>; 597 no-map; 598 }; 599 600 pil_camera_mem: memory@86000000 { 601 reg = <0x0 0x86000000 0x0 0x500000>; 602 no-map; 603 }; 604 605 pil_npu_mem: memory@86500000 { 606 reg = <0x0 0x86500000 0x0 0x500000>; 607 no-map; 608 }; 609 610 pil_video_mem: memory@86a00000 { 611 reg = <0x0 0x86a00000 0x0 0x500000>; 612 no-map; 613 }; 614 615 pil_cdsp_mem: memory@86f00000 { 616 reg = <0x0 0x86f00000 0x0 0x1e00000>; 617 no-map; 618 }; 619 620 pil_adsp_mem: memory@88d00000 { 621 reg = <0x0 0x88d00000 0x0 0x2800000>; 622 no-map; 623 }; 624 625 wlan_fw_mem: memory@8b500000 { 626 reg = <0x0 0x8b500000 0x0 0x200000>; 627 no-map; 628 }; 629 630 pil_ipa_fw_mem: memory@8b700000 { 631 reg = <0x0 0x8b700000 0x0 0x10000>; 632 no-map; 633 }; 634 635 pil_ipa_gsi_mem: memory@8b710000 { 636 reg = <0x0 0x8b710000 0x0 0x5400>; 637 no-map; 638 }; 639 640 pil_modem_mem: memory@8b800000 { 641 reg = <0x0 0x8b800000 0x0 0xf800000>; 642 no-map; 643 }; 644 645 cont_splash_memory: memory@a0000000 { 646 reg = <0x0 0xa0000000 0x0 0x2300000>; 647 no-map; 648 }; 649 650 dfps_data_memory: memory@a2300000 { 651 reg = <0x0 0xa2300000 0x0 0x100000>; 652 no-map; 653 }; 654 655 removed_region: memory@c0000000 { 656 reg = <0x0 0xc0000000 0x0 0x3900000>; 657 no-map; 658 }; 659 660 pil_gpu_mem: memory@f0d00000 { 661 reg = <0x0 0xf0d00000 0x0 0x1000>; 662 no-map; 663 }; 664 665 debug_region: memory@ffb00000 { 666 reg = <0x0 0xffb00000 0x0 0xc0000>; 667 no-map; 668 }; 669 670 last_log_region: memory@ffbc0000 { 671 reg = <0x0 0xffbc0000 0x0 0x40000>; 672 no-map; 673 }; 674 675 ramoops: ramoops@ffc00000 { 676 compatible = "ramoops"; 677 reg = <0x0 0xffc00000 0x0 0x100000>; 678 record-size = <0x1000>; 679 console-size = <0x40000>; 680 pmsg-size = <0x20000>; 681 ecc-size = <16>; 682 no-map; 683 }; 684 685 cmdline_region: memory@ffd00000 { 686 reg = <0x0 0xffd00000 0x0 0x1000>; 687 no-map; 688 }; 689 }; 690 691 smem { 692 compatible = "qcom,smem"; 693 memory-region = <&smem_mem>; 694 hwlocks = <&tcsr_mutex 3>; 695 }; 696 697 smp2p-adsp { 698 compatible = "qcom,smp2p"; 699 qcom,smem = <443>, <429>; 700 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 701 IPCC_MPROC_SIGNAL_SMP2P 702 IRQ_TYPE_EDGE_RISING>; 703 mboxes = <&ipcc IPCC_CLIENT_LPASS 704 IPCC_MPROC_SIGNAL_SMP2P>; 705 706 qcom,local-pid = <0>; 707 qcom,remote-pid = <2>; 708 709 smp2p_adsp_out: master-kernel { 710 qcom,entry-name = "master-kernel"; 711 #qcom,smem-state-cells = <1>; 712 }; 713 714 smp2p_adsp_in: slave-kernel { 715 qcom,entry-name = "slave-kernel"; 716 interrupt-controller; 717 #interrupt-cells = <2>; 718 }; 719 }; 720 721 smp2p-cdsp { 722 compatible = "qcom,smp2p"; 723 qcom,smem = <94>, <432>; 724 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 725 IPCC_MPROC_SIGNAL_SMP2P 726 IRQ_TYPE_EDGE_RISING>; 727 mboxes = <&ipcc IPCC_CLIENT_CDSP 728 IPCC_MPROC_SIGNAL_SMP2P>; 729 730 qcom,local-pid = <0>; 731 qcom,remote-pid = <5>; 732 733 smp2p_cdsp_out: master-kernel { 734 qcom,entry-name = "master-kernel"; 735 #qcom,smem-state-cells = <1>; 736 }; 737 738 smp2p_cdsp_in: slave-kernel { 739 qcom,entry-name = "slave-kernel"; 740 interrupt-controller; 741 #interrupt-cells = <2>; 742 }; 743 }; 744 745 smp2p-mpss { 746 compatible = "qcom,smp2p"; 747 qcom,smem = <435>, <428>; 748 749 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 750 IPCC_MPROC_SIGNAL_SMP2P 751 IRQ_TYPE_EDGE_RISING>; 752 mboxes = <&ipcc IPCC_CLIENT_MPSS 753 IPCC_MPROC_SIGNAL_SMP2P>; 754 755 qcom,local-pid = <0>; 756 qcom,remote-pid = <1>; 757 758 modem_smp2p_out: master-kernel { 759 qcom,entry-name = "master-kernel"; 760 #qcom,smem-state-cells = <1>; 761 }; 762 763 modem_smp2p_in: slave-kernel { 764 qcom,entry-name = "slave-kernel"; 765 interrupt-controller; 766 #interrupt-cells = <2>; 767 }; 768 769 ipa_smp2p_out: ipa-ap-to-modem { 770 qcom,entry-name = "ipa"; 771 #qcom,smem-state-cells = <1>; 772 }; 773 774 ipa_smp2p_in: ipa-modem-to-ap { 775 qcom,entry-name = "ipa"; 776 interrupt-controller; 777 #interrupt-cells = <2>; 778 }; 779 }; 780 781 soc: soc@0 { 782 #address-cells = <2>; 783 #size-cells = <2>; 784 ranges = <0 0 0 0 0x10 0>; 785 dma-ranges = <0 0 0 0 0x10 0>; 786 compatible = "simple-bus"; 787 788 gcc: clock-controller@100000 { 789 compatible = "qcom,gcc-sm6350"; 790 reg = <0x0 0x00100000 0x0 0x1f0000>; 791 #clock-cells = <1>; 792 #reset-cells = <1>; 793 #power-domain-cells = <1>; 794 clock-names = "bi_tcxo", 795 "bi_tcxo_ao", 796 "sleep_clk"; 797 clocks = <&rpmhcc RPMH_CXO_CLK>, 798 <&rpmhcc RPMH_CXO_CLK_A>, 799 <&sleep_clk>; 800 }; 801 802 ipcc: mailbox@408000 { 803 compatible = "qcom,sm6350-ipcc", "qcom,ipcc"; 804 reg = <0x0 0x00408000 0x0 0x1000>; 805 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 806 interrupt-controller; 807 #interrupt-cells = <3>; 808 #mbox-cells = <2>; 809 }; 810 811 qfprom: qfprom@784000 { 812 compatible = "qcom,sm6350-qfprom", "qcom,qfprom"; 813 reg = <0x0 0x00784000 0x0 0x3000>; 814 #address-cells = <1>; 815 #size-cells = <1>; 816 817 gpu_speed_bin: gpu-speed-bin@2015 { 818 reg = <0x2015 0x1>; 819 bits = <0 8>; 820 }; 821 }; 822 823 rng: rng@793000 { 824 compatible = "qcom,prng-ee"; 825 reg = <0x0 0x00793000 0x0 0x1000>; 826 clocks = <&gcc GCC_PRNG_AHB_CLK>; 827 clock-names = "core"; 828 }; 829 830 sdhc_1: mmc@7c4000 { 831 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 832 reg = <0x0 0x007c4000 0x0 0x1000>, 833 <0x0 0x007c5000 0x0 0x1000>, 834 <0x0 0x007c8000 0x0 0x8000>; 835 reg-names = "hc", "cqhci", "ice"; 836 837 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 838 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 839 interrupt-names = "hc_irq", "pwr_irq"; 840 iommus = <&apps_smmu 0x60 0x0>; 841 842 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 843 <&gcc GCC_SDCC1_APPS_CLK>, 844 <&rpmhcc RPMH_CXO_CLK>; 845 clock-names = "iface", "core", "xo"; 846 resets = <&gcc GCC_SDCC1_BCR>; 847 qcom,dll-config = <0x000f642c>; 848 qcom,ddr-config = <0x80040868>; 849 power-domains = <&rpmhpd SM6350_CX>; 850 operating-points-v2 = <&sdhc1_opp_table>; 851 bus-width = <8>; 852 non-removable; 853 supports-cqe; 854 855 status = "disabled"; 856 857 sdhc1_opp_table: opp-table { 858 compatible = "operating-points-v2"; 859 860 opp-19200000 { 861 opp-hz = /bits/ 64 <19200000>; 862 required-opps = <&rpmhpd_opp_min_svs>; 863 }; 864 865 opp-100000000 { 866 opp-hz = /bits/ 64 <100000000>; 867 required-opps = <&rpmhpd_opp_low_svs>; 868 }; 869 870 opp-384000000 { 871 opp-hz = /bits/ 64 <384000000>; 872 required-opps = <&rpmhpd_opp_svs_l1>; 873 }; 874 }; 875 }; 876 877 gpi_dma0: dma-controller@800000 { 878 compatible = "qcom,sm6350-gpi-dma"; 879 reg = <0x0 0x00800000 0x0 0x60000>; 880 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 890 dma-channels = <10>; 891 dma-channel-mask = <0x1f>; 892 iommus = <&apps_smmu 0x56 0x0>; 893 #dma-cells = <3>; 894 status = "disabled"; 895 }; 896 897 qupv3_id_0: geniqup@8c0000 { 898 compatible = "qcom,geni-se-qup"; 899 reg = <0x0 0x008c0000 0x0 0x2000>; 900 clock-names = "m-ahb", "s-ahb"; 901 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 902 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 903 #address-cells = <2>; 904 #size-cells = <2>; 905 iommus = <&apps_smmu 0x43 0x0>; 906 ranges; 907 status = "disabled"; 908 909 i2c0: i2c@880000 { 910 compatible = "qcom,geni-i2c"; 911 reg = <0x0 0x00880000 0x0 0x4000>; 912 clock-names = "se"; 913 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 914 pinctrl-names = "default"; 915 pinctrl-0 = <&qup_i2c0_default>; 916 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 917 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 918 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 919 dma-names = "tx", "rx"; 920 #address-cells = <1>; 921 #size-cells = <0>; 922 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 923 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 924 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 925 interconnect-names = "qup-core", "qup-config", "qup-memory"; 926 status = "disabled"; 927 }; 928 929 uart1: serial@884000 { 930 compatible = "qcom,geni-uart"; 931 reg = <0x0 0x00884000 0x0 0x4000>; 932 clock-names = "se"; 933 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 934 pinctrl-names = "default"; 935 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 936 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 937 power-domains = <&rpmhpd SM6350_CX>; 938 operating-points-v2 = <&qup_opp_table>; 939 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 940 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 941 interconnect-names = "qup-core", "qup-config"; 942 status = "disabled"; 943 }; 944 945 i2c2: i2c@888000 { 946 compatible = "qcom,geni-i2c"; 947 reg = <0x0 0x00888000 0x0 0x4000>; 948 clock-names = "se"; 949 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 950 pinctrl-names = "default"; 951 pinctrl-0 = <&qup_i2c2_default>; 952 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 953 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 954 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 955 dma-names = "tx", "rx"; 956 #address-cells = <1>; 957 #size-cells = <0>; 958 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 959 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 960 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 961 interconnect-names = "qup-core", "qup-config", "qup-memory"; 962 status = "disabled"; 963 }; 964 }; 965 966 gpi_dma1: dma-controller@900000 { 967 compatible = "qcom,sm6350-gpi-dma"; 968 reg = <0x0 0x00900000 0x0 0x60000>; 969 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 648 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 650 IRQ_TYPE_LEVEL_HIGH>, 975 <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>, 976 <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 977 <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>, 978 <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>; 979 dma-channels = <10>; 980 dma-channel-mask = <0x3f>; 981 iommus = <&apps_smmu 0x4d6 0x0>; 982 #dma-cells = <3>; 983 status = "disabled"; 984 }; 985 986 qupv3_id_1: geniqup@9c0000 { 987 compatible = "qcom,geni-se-qup"; 988 reg = <0x0 0x009c0000 0x0 0x2000>; 989 clock-names = "m-ahb", "s-ahb"; 990 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 991 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 992 #address-cells = <2>; 993 #size-cells = <2>; 994 iommus = <&apps_smmu 0x4c3 0x0>; 995 ranges; 996 status = "disabled"; 997 998 i2c6: i2c@980000 { 999 compatible = "qcom,geni-i2c"; 1000 reg = <0x0 0x00980000 0x0 0x4000>; 1001 clock-names = "se"; 1002 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1003 pinctrl-names = "default"; 1004 pinctrl-0 = <&qup_i2c6_default>; 1005 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1006 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1007 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1008 dma-names = "tx", "rx"; 1009 #address-cells = <1>; 1010 #size-cells = <0>; 1011 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1012 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1013 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1014 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1015 status = "disabled"; 1016 }; 1017 1018 i2c7: i2c@984000 { 1019 compatible = "qcom,geni-i2c"; 1020 reg = <0x0 0x00984000 0x0 0x4000>; 1021 clock-names = "se"; 1022 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1023 pinctrl-names = "default"; 1024 pinctrl-0 = <&qup_i2c7_default>; 1025 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1026 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1027 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1028 dma-names = "tx", "rx"; 1029 #address-cells = <1>; 1030 #size-cells = <0>; 1031 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1032 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1033 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1034 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1035 status = "disabled"; 1036 }; 1037 1038 i2c8: i2c@988000 { 1039 compatible = "qcom,geni-i2c"; 1040 reg = <0x0 0x00988000 0x0 0x4000>; 1041 clock-names = "se"; 1042 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1043 pinctrl-names = "default"; 1044 pinctrl-0 = <&qup_i2c8_default>; 1045 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1046 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1047 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1048 dma-names = "tx", "rx"; 1049 #address-cells = <1>; 1050 #size-cells = <0>; 1051 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1052 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1053 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1054 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1055 status = "disabled"; 1056 }; 1057 1058 uart9: serial@98c000 { 1059 compatible = "qcom,geni-debug-uart"; 1060 reg = <0x0 0x0098c000 0x0 0x4000>; 1061 clock-names = "se"; 1062 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1063 pinctrl-names = "default"; 1064 pinctrl-0 = <&qup_uart9_default>; 1065 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1066 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1067 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1068 interconnect-names = "qup-core", "qup-config"; 1069 status = "disabled"; 1070 }; 1071 1072 i2c10: i2c@990000 { 1073 compatible = "qcom,geni-i2c"; 1074 reg = <0x0 0x00990000 0x0 0x4000>; 1075 clock-names = "se"; 1076 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1077 pinctrl-names = "default"; 1078 pinctrl-0 = <&qup_i2c10_default>; 1079 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1080 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1081 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1082 dma-names = "tx", "rx"; 1083 #address-cells = <1>; 1084 #size-cells = <0>; 1085 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1086 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1087 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1088 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1089 status = "disabled"; 1090 }; 1091 }; 1092 1093 config_noc: interconnect@1500000 { 1094 compatible = "qcom,sm6350-config-noc"; 1095 reg = <0x0 0x01500000 0x0 0x28000>; 1096 #interconnect-cells = <2>; 1097 qcom,bcm-voters = <&apps_bcm_voter>; 1098 }; 1099 1100 system_noc: interconnect@1620000 { 1101 compatible = "qcom,sm6350-system-noc"; 1102 reg = <0x0 0x01620000 0x0 0x17080>; 1103 #interconnect-cells = <2>; 1104 qcom,bcm-voters = <&apps_bcm_voter>; 1105 1106 clk_virt: interconnect-clk-virt { 1107 compatible = "qcom,sm6350-clk-virt"; 1108 #interconnect-cells = <2>; 1109 qcom,bcm-voters = <&apps_bcm_voter>; 1110 }; 1111 }; 1112 1113 aggre1_noc: interconnect@16e0000 { 1114 compatible = "qcom,sm6350-aggre1-noc"; 1115 reg = <0x0 0x016e0000 0x0 0x15080>; 1116 #interconnect-cells = <2>; 1117 qcom,bcm-voters = <&apps_bcm_voter>; 1118 }; 1119 1120 aggre2_noc: interconnect@1700000 { 1121 compatible = "qcom,sm6350-aggre2-noc"; 1122 reg = <0x0 0x01700000 0x0 0x1f880>; 1123 #interconnect-cells = <2>; 1124 qcom,bcm-voters = <&apps_bcm_voter>; 1125 1126 compute_noc: interconnect-compute-noc { 1127 compatible = "qcom,sm6350-compute-noc"; 1128 #interconnect-cells = <2>; 1129 qcom,bcm-voters = <&apps_bcm_voter>; 1130 }; 1131 }; 1132 1133 mmss_noc: interconnect@1740000 { 1134 compatible = "qcom,sm6350-mmss-noc"; 1135 reg = <0x0 0x01740000 0x0 0x1c100>; 1136 #interconnect-cells = <2>; 1137 qcom,bcm-voters = <&apps_bcm_voter>; 1138 }; 1139 1140 ufs_mem_hc: ufshc@1d84000 { 1141 compatible = "qcom,sm6350-ufshc", "qcom,ufshc", 1142 "jedec,ufs-2.0"; 1143 reg = <0x0 0x01d84000 0x0 0x3000>, 1144 <0x0 0x01d90000 0x0 0x8000>; 1145 reg-names = "std", "ice"; 1146 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1147 phys = <&ufs_mem_phy>; 1148 phy-names = "ufsphy"; 1149 lanes-per-direction = <2>; 1150 #reset-cells = <1>; 1151 resets = <&gcc GCC_UFS_PHY_BCR>; 1152 reset-names = "rst"; 1153 1154 power-domains = <&gcc UFS_PHY_GDSC>; 1155 1156 iommus = <&apps_smmu 0x80 0x0>; 1157 1158 clock-names = "core_clk", 1159 "bus_aggr_clk", 1160 "iface_clk", 1161 "core_clk_unipro", 1162 "ref_clk", 1163 "tx_lane0_sync_clk", 1164 "rx_lane0_sync_clk", 1165 "rx_lane1_sync_clk", 1166 "ice_core_clk"; 1167 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1168 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1169 <&gcc GCC_UFS_PHY_AHB_CLK>, 1170 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1171 <&rpmhcc RPMH_QLINK_CLK>, 1172 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1173 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1174 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 1175 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1176 freq-table-hz = 1177 <50000000 200000000>, 1178 <0 0>, 1179 <0 0>, 1180 <37500000 150000000>, 1181 <75000000 300000000>, 1182 <0 0>, 1183 <0 0>, 1184 <0 0>, 1185 <0 0>; 1186 1187 status = "disabled"; 1188 }; 1189 1190 ufs_mem_phy: phy@1d87000 { 1191 compatible = "qcom,sm6350-qmp-ufs-phy"; 1192 reg = <0x0 0x01d87000 0x0 0x1000>; 1193 1194 clocks = <&rpmhcc RPMH_CXO_CLK>, 1195 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1196 <&gcc GCC_UFS_MEM_CLKREF_CLK>; 1197 clock-names = "ref", 1198 "ref_aux", 1199 "qref"; 1200 1201 power-domains = <&gcc UFS_PHY_GDSC>; 1202 1203 resets = <&ufs_mem_hc 0>; 1204 reset-names = "ufsphy"; 1205 1206 #phy-cells = <0>; 1207 1208 status = "disabled"; 1209 }; 1210 1211 cryptobam: dma-controller@1dc4000 { 1212 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1213 reg = <0x0 0x01dc4000 0x0 0x24000>; 1214 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1215 #dma-cells = <1>; 1216 qcom,ee = <0>; 1217 qcom,controlled-remotely; 1218 num-channels = <16>; 1219 qcom,num-ees = <4>; 1220 iommus = <&apps_smmu 0x426 0x11>, 1221 <&apps_smmu 0x432 0x0>, 1222 <&apps_smmu 0x436 0x11>, 1223 <&apps_smmu 0x438 0x1>, 1224 <&apps_smmu 0x43f 0x0>; 1225 }; 1226 1227 crypto: crypto@1dfa000 { 1228 compatible = "qcom,sm6350-qce", "qcom,sm8150-qce", "qcom,qce"; 1229 reg = <0x0 0x01dfa000 0x0 0x6000>; 1230 dmas = <&cryptobam 4>, <&cryptobam 5>; 1231 dma-names = "rx", "tx"; 1232 iommus = <&apps_smmu 0x426 0x11>, 1233 <&apps_smmu 0x432 0x0>, 1234 <&apps_smmu 0x436 0x11>, 1235 <&apps_smmu 0x438 0x1>, 1236 <&apps_smmu 0x43f 0x0>; 1237 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 QCOM_ICC_TAG_ALWAYS 1238 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; 1239 interconnect-names = "memory"; 1240 }; 1241 1242 ipa: ipa@1e40000 { 1243 compatible = "qcom,sm6350-ipa"; 1244 1245 iommus = <&apps_smmu 0x440 0x0>, 1246 <&apps_smmu 0x442 0x0>; 1247 reg = <0x0 0x01e40000 0x0 0x8000>, 1248 <0x0 0x01e50000 0x0 0x3000>, 1249 <0x0 0x01e04000 0x0 0x23000>; 1250 reg-names = "ipa-reg", 1251 "ipa-shared", 1252 "gsi"; 1253 1254 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 1255 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1256 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1257 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1258 interrupt-names = "ipa", 1259 "gsi", 1260 "ipa-clock-query", 1261 "ipa-setup-ready"; 1262 1263 clocks = <&rpmhcc RPMH_IPA_CLK>; 1264 clock-names = "core"; 1265 1266 interconnects = <&aggre2_noc MASTER_IPA 0 &clk_virt SLAVE_EBI_CH0 0>, 1267 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_OCIMEM 0>, 1268 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_IPA_CFG 0>; 1269 interconnect-names = "memory", "imem", "config"; 1270 1271 qcom,smem-states = <&ipa_smp2p_out 0>, 1272 <&ipa_smp2p_out 1>; 1273 qcom,smem-state-names = "ipa-clock-enabled-valid", 1274 "ipa-clock-enabled"; 1275 1276 status = "disabled"; 1277 }; 1278 1279 tcsr_mutex: hwlock@1f40000 { 1280 compatible = "qcom,tcsr-mutex"; 1281 reg = <0x0 0x01f40000 0x0 0x40000>; 1282 #hwlock-cells = <1>; 1283 }; 1284 1285 adsp: remoteproc@3000000 { 1286 compatible = "qcom,sm6350-adsp-pas"; 1287 reg = <0x0 0x03000000 0x0 0x10000>; 1288 1289 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 1290 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1291 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1292 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1293 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1294 interrupt-names = "wdog", "fatal", "ready", 1295 "handover", "stop-ack"; 1296 1297 clocks = <&rpmhcc RPMH_CXO_CLK>; 1298 clock-names = "xo"; 1299 1300 power-domains = <&rpmhpd SM6350_LCX>, 1301 <&rpmhpd SM6350_LMX>; 1302 power-domain-names = "lcx", "lmx"; 1303 1304 memory-region = <&pil_adsp_mem>; 1305 1306 qcom,qmp = <&aoss_qmp>; 1307 1308 qcom,smem-states = <&smp2p_adsp_out 0>; 1309 qcom,smem-state-names = "stop"; 1310 1311 status = "disabled"; 1312 1313 glink-edge { 1314 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1315 IPCC_MPROC_SIGNAL_GLINK_QMP 1316 IRQ_TYPE_EDGE_RISING>; 1317 mboxes = <&ipcc IPCC_CLIENT_LPASS 1318 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1319 1320 label = "lpass"; 1321 qcom,remote-pid = <2>; 1322 1323 fastrpc { 1324 compatible = "qcom,fastrpc"; 1325 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1326 label = "adsp"; 1327 qcom,non-secure-domain; 1328 #address-cells = <1>; 1329 #size-cells = <0>; 1330 1331 compute-cb@3 { 1332 compatible = "qcom,fastrpc-compute-cb"; 1333 reg = <3>; 1334 iommus = <&apps_smmu 0x1003 0x0>; 1335 }; 1336 1337 compute-cb@4 { 1338 compatible = "qcom,fastrpc-compute-cb"; 1339 reg = <4>; 1340 iommus = <&apps_smmu 0x1004 0x0>; 1341 }; 1342 1343 compute-cb@5 { 1344 compatible = "qcom,fastrpc-compute-cb"; 1345 reg = <5>; 1346 iommus = <&apps_smmu 0x1005 0x0>; 1347 qcom,nsessions = <5>; 1348 }; 1349 }; 1350 }; 1351 }; 1352 1353 gpu: gpu@3d00000 { 1354 compatible = "qcom,adreno-619.0", "qcom,adreno"; 1355 reg = <0x0 0x03d00000 0x0 0x40000>, 1356 <0x0 0x03d9e000 0x0 0x1000>; 1357 reg-names = "kgsl_3d0_reg_memory", 1358 "cx_mem"; 1359 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1360 1361 iommus = <&adreno_smmu 0>; 1362 operating-points-v2 = <&gpu_opp_table>; 1363 qcom,gmu = <&gmu>; 1364 nvmem-cells = <&gpu_speed_bin>; 1365 nvmem-cell-names = "speed_bin"; 1366 #cooling-cells = <2>; 1367 1368 status = "disabled"; 1369 1370 gpu_zap_shader: zap-shader { 1371 memory-region = <&pil_gpu_mem>; 1372 }; 1373 1374 gpu_opp_table: opp-table { 1375 compatible = "operating-points-v2"; 1376 1377 opp-850000000 { 1378 opp-hz = /bits/ 64 <850000000>; 1379 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1380 opp-supported-hw = <0x03>; 1381 }; 1382 1383 opp-800000000 { 1384 opp-hz = /bits/ 64 <800000000>; 1385 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1386 opp-supported-hw = <0x07>; 1387 }; 1388 1389 opp-650000000 { 1390 opp-hz = /bits/ 64 <650000000>; 1391 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1392 opp-supported-hw = <0x0f>; 1393 }; 1394 1395 opp-565000000 { 1396 opp-hz = /bits/ 64 <565000000>; 1397 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1398 opp-supported-hw = <0x1f>; 1399 }; 1400 1401 opp-430000000 { 1402 opp-hz = /bits/ 64 <430000000>; 1403 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1404 opp-supported-hw = <0x1f>; 1405 }; 1406 1407 opp-355000000 { 1408 opp-hz = /bits/ 64 <355000000>; 1409 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1410 opp-supported-hw = <0x1f>; 1411 }; 1412 1413 opp-253000000 { 1414 opp-hz = /bits/ 64 <253000000>; 1415 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1416 opp-supported-hw = <0x1f>; 1417 }; 1418 }; 1419 }; 1420 1421 adreno_smmu: iommu@3d40000 { 1422 compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 1423 reg = <0x0 0x03d40000 0x0 0x10000>; 1424 #iommu-cells = <1>; 1425 #global-interrupts = <2>; 1426 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1427 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1428 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 1429 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 1430 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 1431 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 1432 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 1433 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 1434 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 1435 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1436 1437 clocks = <&gpucc GPU_CC_AHB_CLK>, 1438 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1439 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1440 clock-names = "ahb", 1441 "bus", 1442 "iface"; 1443 1444 power-domains = <&gpucc GPU_CX_GDSC>; 1445 }; 1446 1447 gmu: gmu@3d6a000 { 1448 compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu"; 1449 reg = <0x0 0x03d6a000 0x0 0x31000>, 1450 <0x0 0x0b290000 0x0 0x10000>, 1451 <0x0 0x0b490000 0x0 0x10000>; 1452 reg-names = "gmu", 1453 "gmu_pdc", 1454 "gmu_pdc_seq"; 1455 1456 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1458 interrupt-names = "hfi", 1459 "gmu"; 1460 1461 clocks = <&gpucc GPU_CC_AHB_CLK>, 1462 <&gpucc GPU_CC_CX_GMU_CLK>, 1463 <&gpucc GPU_CC_CXO_CLK>, 1464 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1465 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1466 clock-names = "ahb", 1467 "gmu", 1468 "cxo", 1469 "axi", 1470 "memnoc"; 1471 1472 power-domains = <&gpucc GPU_CX_GDSC>, 1473 <&gpucc GPU_GX_GDSC>; 1474 power-domain-names = "cx", 1475 "gx"; 1476 1477 iommus = <&adreno_smmu 5>; 1478 1479 operating-points-v2 = <&gmu_opp_table>; 1480 1481 gmu_opp_table: opp-table { 1482 compatible = "operating-points-v2"; 1483 1484 opp-200000000 { 1485 opp-hz = /bits/ 64 <200000000>; 1486 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1487 }; 1488 }; 1489 }; 1490 1491 gpucc: clock-controller@3d90000 { 1492 compatible = "qcom,sm6350-gpucc"; 1493 reg = <0x0 0x03d90000 0x0 0x9000>; 1494 clocks = <&rpmhcc RPMH_CXO_CLK>, 1495 <&gcc GCC_GPU_GPLL0_CLK>, 1496 <&gcc GCC_GPU_GPLL0_DIV_CLK>; 1497 clock-names = "bi_tcxo", 1498 "gcc_gpu_gpll0_clk_src", 1499 "gcc_gpu_gpll0_div_clk_src"; 1500 #clock-cells = <1>; 1501 #reset-cells = <1>; 1502 #power-domain-cells = <1>; 1503 }; 1504 1505 mpss: remoteproc@4080000 { 1506 compatible = "qcom,sm6350-mpss-pas"; 1507 reg = <0x0 0x04080000 0x0 0x10000>; 1508 1509 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 1510 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1511 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1512 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1513 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1514 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1515 interrupt-names = "wdog", "fatal", "ready", "handover", 1516 "stop-ack", "shutdown-ack"; 1517 1518 clocks = <&rpmhcc RPMH_CXO_CLK>; 1519 clock-names = "xo"; 1520 1521 power-domains = <&rpmhpd SM6350_CX>, 1522 <&rpmhpd SM6350_MSS>; 1523 power-domain-names = "cx", "mss"; 1524 1525 memory-region = <&pil_modem_mem>; 1526 1527 qcom,qmp = <&aoss_qmp>; 1528 1529 qcom,smem-states = <&modem_smp2p_out 0>; 1530 qcom,smem-state-names = "stop"; 1531 1532 status = "disabled"; 1533 1534 glink-edge { 1535 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1536 IPCC_MPROC_SIGNAL_GLINK_QMP 1537 IRQ_TYPE_EDGE_RISING>; 1538 mboxes = <&ipcc IPCC_CLIENT_MPSS 1539 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1540 label = "modem"; 1541 qcom,remote-pid = <1>; 1542 }; 1543 }; 1544 1545 cdsp: remoteproc@8300000 { 1546 compatible = "qcom,sm6350-cdsp-pas"; 1547 reg = <0x0 0x08300000 0x0 0x10000>; 1548 1549 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 1550 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 1551 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 1552 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 1553 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 1554 interrupt-names = "wdog", "fatal", "ready", 1555 "handover", "stop-ack"; 1556 1557 clocks = <&rpmhcc RPMH_CXO_CLK>; 1558 clock-names = "xo"; 1559 1560 power-domains = <&rpmhpd SM6350_CX>, 1561 <&rpmhpd SM6350_MX>; 1562 power-domain-names = "cx", "mx"; 1563 1564 memory-region = <&pil_cdsp_mem>; 1565 1566 qcom,qmp = <&aoss_qmp>; 1567 1568 qcom,smem-states = <&smp2p_cdsp_out 0>; 1569 qcom,smem-state-names = "stop"; 1570 1571 status = "disabled"; 1572 1573 glink-edge { 1574 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 1575 IPCC_MPROC_SIGNAL_GLINK_QMP 1576 IRQ_TYPE_EDGE_RISING>; 1577 mboxes = <&ipcc IPCC_CLIENT_CDSP 1578 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1579 1580 label = "cdsp"; 1581 qcom,remote-pid = <5>; 1582 1583 fastrpc { 1584 compatible = "qcom,fastrpc"; 1585 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1586 label = "cdsp"; 1587 qcom,non-secure-domain; 1588 #address-cells = <1>; 1589 #size-cells = <0>; 1590 1591 compute-cb@1 { 1592 compatible = "qcom,fastrpc-compute-cb"; 1593 reg = <1>; 1594 iommus = <&apps_smmu 0x1401 0x20>; 1595 }; 1596 1597 compute-cb@2 { 1598 compatible = "qcom,fastrpc-compute-cb"; 1599 reg = <2>; 1600 iommus = <&apps_smmu 0x1402 0x20>; 1601 }; 1602 1603 compute-cb@3 { 1604 compatible = "qcom,fastrpc-compute-cb"; 1605 reg = <3>; 1606 iommus = <&apps_smmu 0x1403 0x20>; 1607 }; 1608 1609 compute-cb@4 { 1610 compatible = "qcom,fastrpc-compute-cb"; 1611 reg = <4>; 1612 iommus = <&apps_smmu 0x1404 0x20>; 1613 }; 1614 1615 compute-cb@5 { 1616 compatible = "qcom,fastrpc-compute-cb"; 1617 reg = <5>; 1618 iommus = <&apps_smmu 0x1405 0x20>; 1619 }; 1620 1621 compute-cb@6 { 1622 compatible = "qcom,fastrpc-compute-cb"; 1623 reg = <6>; 1624 iommus = <&apps_smmu 0x1406 0x20>; 1625 }; 1626 1627 compute-cb@7 { 1628 compatible = "qcom,fastrpc-compute-cb"; 1629 reg = <7>; 1630 iommus = <&apps_smmu 0x1407 0x20>; 1631 }; 1632 1633 compute-cb@8 { 1634 compatible = "qcom,fastrpc-compute-cb"; 1635 reg = <8>; 1636 iommus = <&apps_smmu 0x1408 0x20>; 1637 }; 1638 1639 /* note: secure cb9 in downstream */ 1640 }; 1641 }; 1642 }; 1643 1644 sdhc_2: mmc@8804000 { 1645 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 1646 reg = <0x0 0x08804000 0x0 0x1000>; 1647 1648 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1649 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1650 interrupt-names = "hc_irq", "pwr_irq"; 1651 iommus = <&apps_smmu 0x560 0x0>; 1652 1653 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1654 <&gcc GCC_SDCC2_APPS_CLK>, 1655 <&rpmhcc RPMH_CXO_CLK>; 1656 clock-names = "iface", "core", "xo"; 1657 resets = <&gcc GCC_SDCC2_BCR>; 1658 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>, 1659 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>; 1660 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 1661 1662 pinctrl-0 = <&sdc2_on_state>; 1663 pinctrl-1 = <&sdc2_off_state>; 1664 pinctrl-names = "default", "sleep"; 1665 1666 qcom,dll-config = <0x0007642c>; 1667 qcom,ddr-config = <0x80040868>; 1668 power-domains = <&rpmhpd SM6350_CX>; 1669 operating-points-v2 = <&sdhc2_opp_table>; 1670 bus-width = <4>; 1671 1672 status = "disabled"; 1673 1674 sdhc2_opp_table: opp-table { 1675 compatible = "operating-points-v2"; 1676 1677 opp-100000000 { 1678 opp-hz = /bits/ 64 <100000000>; 1679 required-opps = <&rpmhpd_opp_svs_l1>; 1680 opp-peak-kBps = <790000 131000>; 1681 opp-avg-kBps = <50000 50000>; 1682 }; 1683 1684 opp-202000000 { 1685 opp-hz = /bits/ 64 <202000000>; 1686 required-opps = <&rpmhpd_opp_nom>; 1687 opp-peak-kBps = <3190000 294000>; 1688 opp-avg-kBps = <261438 300000>; 1689 }; 1690 }; 1691 }; 1692 1693 usb_1_hsphy: phy@88e3000 { 1694 compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy"; 1695 reg = <0x0 0x088e3000 0x0 0x400>; 1696 status = "disabled"; 1697 #phy-cells = <0>; 1698 1699 clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>; 1700 clock-names = "cfg_ahb", "ref"; 1701 1702 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1703 }; 1704 1705 usb_1_qmpphy: phy@88e8000 { 1706 compatible = "qcom,sm6350-qmp-usb3-dp-phy"; 1707 reg = <0x0 0x088e8000 0x0 0x3000>; 1708 1709 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1710 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 1711 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 1712 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1713 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 1714 1715 power-domains = <&gcc USB30_PRIM_GDSC>; 1716 1717 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 1718 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 1719 reset-names = "phy", "common"; 1720 1721 orientation-switch; 1722 1723 #clock-cells = <1>; 1724 #phy-cells = <1>; 1725 1726 status = "disabled"; 1727 1728 ports { 1729 #address-cells = <1>; 1730 #size-cells = <0>; 1731 1732 port@0 { 1733 reg = <0>; 1734 1735 usb_1_qmpphy_out: endpoint { 1736 }; 1737 }; 1738 1739 port@1 { 1740 reg = <1>; 1741 1742 usb_1_qmpphy_usb_ss_in: endpoint { 1743 remote-endpoint = <&usb_1_dwc3_ss_out>; 1744 }; 1745 }; 1746 1747 port@2 { 1748 reg = <2>; 1749 1750 usb_1_qmpphy_dp_in: endpoint { 1751 }; 1752 }; 1753 }; 1754 }; 1755 1756 dc_noc: interconnect@9160000 { 1757 compatible = "qcom,sm6350-dc-noc"; 1758 reg = <0x0 0x09160000 0x0 0x3200>; 1759 #interconnect-cells = <2>; 1760 qcom,bcm-voters = <&apps_bcm_voter>; 1761 }; 1762 1763 system-cache-controller@9200000 { 1764 compatible = "qcom,sm6350-llcc"; 1765 reg = <0x0 0x09200000 0x0 0x50000>, <0x0 0x09600000 0x0 0x50000>; 1766 reg-names = "llcc0_base", "llcc_broadcast_base"; 1767 }; 1768 1769 gem_noc: interconnect@9680000 { 1770 compatible = "qcom,sm6350-gem-noc"; 1771 reg = <0x0 0x09680000 0x0 0x3e200>; 1772 #interconnect-cells = <2>; 1773 qcom,bcm-voters = <&apps_bcm_voter>; 1774 }; 1775 1776 npu_noc: interconnect@9990000 { 1777 compatible = "qcom,sm6350-npu-noc"; 1778 reg = <0x0 0x09990000 0x0 0x1600>; 1779 #interconnect-cells = <2>; 1780 qcom,bcm-voters = <&apps_bcm_voter>; 1781 }; 1782 1783 pmu@90b6300 { 1784 compatible = "qcom,sm6350-llcc-bwmon", "qcom,sdm845-bwmon"; 1785 reg = <0x0 0x090b6300 0x0 0x600>; 1786 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 1787 1788 operating-points-v2 = <&llcc_bwmon_opp_table>; 1789 interconnects = <&clk_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 1790 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>; 1791 1792 llcc_bwmon_opp_table: opp-table { 1793 compatible = "operating-points-v2"; 1794 1795 opp-0 { 1796 opp-peak-kBps = <2288000>; 1797 }; 1798 1799 opp-1 { 1800 opp-peak-kBps = <4577000>; 1801 }; 1802 1803 opp-2 { 1804 opp-peak-kBps = <7110000>; 1805 }; 1806 1807 opp-3 { 1808 opp-peak-kBps = <9155000>; 1809 }; 1810 1811 opp-4 { 1812 opp-peak-kBps = <12298000>; 1813 }; 1814 1815 opp-5 { 1816 opp-peak-kBps = <14236000>; 1817 }; 1818 1819 }; 1820 }; 1821 1822 pmu@90cd000 { 1823 compatible = "qcom,sm6350-cpu-bwmon", "qcom,sc7280-llcc-bwmon"; 1824 reg = <0x0 0x090cd000 0x0 0x1000>; 1825 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1826 1827 operating-points-v2 = <&cpu_bwmon_opp_table>; 1828 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 1829 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>; 1830 1831 cpu_bwmon_opp_table: opp-table { 1832 compatible = "operating-points-v2"; 1833 1834 opp-0 { 1835 opp-peak-kBps = <762000>; 1836 }; 1837 1838 opp-1 { 1839 opp-peak-kBps = <1144000>; 1840 }; 1841 1842 opp-2 { 1843 opp-peak-kBps = <1720000>; 1844 }; 1845 1846 opp-3 { 1847 opp-peak-kBps = <2086000>; 1848 }; 1849 1850 opp-4 { 1851 opp-peak-kBps = <2597000>; 1852 }; 1853 1854 opp-5 { 1855 opp-peak-kBps = <2929000>; 1856 }; 1857 1858 opp-6 { 1859 opp-peak-kBps = <3879000>; 1860 }; 1861 1862 opp-7 { 1863 opp-peak-kBps = <5161000>; 1864 }; 1865 1866 opp-8 { 1867 opp-peak-kBps = <5931000>; 1868 }; 1869 1870 opp-9 { 1871 opp-peak-kBps = <6881000>; 1872 }; 1873 1874 opp-10 { 1875 opp-peak-kBps = <7980000>; 1876 }; 1877 }; 1878 }; 1879 1880 usb_1: usb@a6f8800 { 1881 compatible = "qcom,sm6350-dwc3", "qcom,dwc3"; 1882 reg = <0x0 0x0a6f8800 0x0 0x400>; 1883 status = "disabled"; 1884 #address-cells = <2>; 1885 #size-cells = <2>; 1886 ranges; 1887 1888 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1889 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1890 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1891 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1892 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 1893 clock-names = "cfg_noc", 1894 "core", 1895 "iface", 1896 "sleep", 1897 "mock_utmi"; 1898 1899 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1900 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1901 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 1902 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1903 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 1904 interrupt-names = "pwr_event", 1905 "hs_phy_irq", 1906 "dp_hs_phy_irq", 1907 "dm_hs_phy_irq", 1908 "ss_phy_irq"; 1909 1910 power-domains = <&gcc USB30_PRIM_GDSC>; 1911 1912 resets = <&gcc GCC_USB30_PRIM_BCR>; 1913 1914 interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>, 1915 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 1916 interconnect-names = "usb-ddr", "apps-usb"; 1917 1918 usb_1_dwc3: usb@a600000 { 1919 compatible = "snps,dwc3"; 1920 reg = <0x0 0x0a600000 0x0 0xcd00>; 1921 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1922 iommus = <&apps_smmu 0x540 0x0>; 1923 snps,dis_u2_susphy_quirk; 1924 snps,dis_enblslpm_quirk; 1925 snps,has-lpm-erratum; 1926 snps,hird-threshold = /bits/ 8 <0x10>; 1927 snps,parkmode-disable-ss-quirk; 1928 snps,dis-u1-entry-quirk; 1929 snps,dis-u2-entry-quirk; 1930 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 1931 phy-names = "usb2-phy", "usb3-phy"; 1932 usb-role-switch; 1933 1934 ports { 1935 #address-cells = <1>; 1936 #size-cells = <0>; 1937 1938 port@0 { 1939 reg = <0>; 1940 1941 usb_1_dwc3_hs_out: endpoint { 1942 }; 1943 }; 1944 1945 port@1 { 1946 reg = <1>; 1947 1948 usb_1_dwc3_ss_out: endpoint { 1949 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 1950 }; 1951 }; 1952 }; 1953 }; 1954 }; 1955 1956 cci0: cci@ac4a000 { 1957 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; 1958 reg = <0x0 0x0ac4a000 0x0 0x1000>; 1959 interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>; 1960 power-domains = <&camcc TITAN_TOP_GDSC>; 1961 1962 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1963 <&camcc CAMCC_SOC_AHB_CLK>, 1964 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 1965 <&camcc CAMCC_CPAS_AHB_CLK>, 1966 <&camcc CAMCC_CCI_0_CLK>, 1967 <&camcc CAMCC_CCI_0_CLK_SRC>; 1968 clock-names = "camnoc_axi", 1969 "soc_ahb", 1970 "slow_ahb_src", 1971 "cpas_ahb", 1972 "cci", 1973 "cci_src"; 1974 1975 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1976 <&camcc CAMCC_CCI_0_CLK>; 1977 assigned-clock-rates = <80000000>, <37500000>; 1978 1979 pinctrl-0 = <&cci0_default &cci1_default>; 1980 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 1981 pinctrl-names = "default", "sleep"; 1982 1983 #address-cells = <1>; 1984 #size-cells = <0>; 1985 1986 status = "disabled"; 1987 1988 cci0_i2c0: i2c-bus@0 { 1989 reg = <0>; 1990 clock-frequency = <1000000>; 1991 #address-cells = <1>; 1992 #size-cells = <0>; 1993 }; 1994 1995 cci0_i2c1: i2c-bus@1 { 1996 reg = <1>; 1997 clock-frequency = <1000000>; 1998 #address-cells = <1>; 1999 #size-cells = <0>; 2000 }; 2001 }; 2002 2003 cci1: cci@ac4b000 { 2004 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; 2005 reg = <0x0 0x0ac4b000 0x0 0x1000>; 2006 interrupts = <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>; 2007 power-domains = <&camcc TITAN_TOP_GDSC>; 2008 2009 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 2010 <&camcc CAMCC_SOC_AHB_CLK>, 2011 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 2012 <&camcc CAMCC_CPAS_AHB_CLK>, 2013 <&camcc CAMCC_CCI_1_CLK>, 2014 <&camcc CAMCC_CCI_1_CLK_SRC>; 2015 clock-names = "camnoc_axi", 2016 "soc_ahb", 2017 "slow_ahb_src", 2018 "cpas_ahb", 2019 "cci", 2020 "cci_src"; 2021 2022 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 2023 <&camcc CAMCC_CCI_1_CLK>; 2024 assigned-clock-rates = <80000000>, <37500000>; 2025 2026 pinctrl-0 = <&cci2_default>; 2027 pinctrl-1 = <&cci2_sleep>; 2028 pinctrl-names = "default", "sleep"; 2029 2030 #address-cells = <1>; 2031 #size-cells = <0>; 2032 2033 status = "disabled"; 2034 2035 cci1_i2c0: i2c-bus@0 { 2036 reg = <0>; 2037 clock-frequency = <1000000>; 2038 #address-cells = <1>; 2039 #size-cells = <0>; 2040 }; 2041 2042 /* SM6350 seems to have cci1_i2c1 on gpio2 & gpio3 but unused downstream */ 2043 }; 2044 2045 camcc: clock-controller@ad00000 { 2046 compatible = "qcom,sm6350-camcc"; 2047 reg = <0x0 0x0ad00000 0x0 0x16000>; 2048 clocks = <&rpmhcc RPMH_CXO_CLK>; 2049 #clock-cells = <1>; 2050 #reset-cells = <1>; 2051 #power-domain-cells = <1>; 2052 }; 2053 2054 mdss: display-subsystem@ae00000 { 2055 compatible = "qcom,sm6350-mdss"; 2056 reg = <0x0 0x0ae00000 0x0 0x1000>; 2057 reg-names = "mdss"; 2058 2059 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2060 interrupt-controller; 2061 #interrupt-cells = <1>; 2062 2063 interconnects = <&mmss_noc MASTER_MDP_PORT0 QCOM_ICC_TAG_ALWAYS 2064 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, 2065 <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 2066 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 2067 interconnect-names = "mdp0-mem", 2068 "cpu-cfg"; 2069 2070 clocks = <&gcc GCC_DISP_AHB_CLK>, 2071 <&gcc GCC_DISP_AXI_CLK>, 2072 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2073 clock-names = "iface", 2074 "bus", 2075 "core"; 2076 2077 power-domains = <&dispcc MDSS_GDSC>; 2078 iommus = <&apps_smmu 0x800 0x2>; 2079 2080 #address-cells = <2>; 2081 #size-cells = <2>; 2082 ranges; 2083 2084 status = "disabled"; 2085 2086 mdss_mdp: display-controller@ae01000 { 2087 compatible = "qcom,sm6350-dpu"; 2088 reg = <0x0 0x0ae01000 0x0 0x8f000>, 2089 <0x0 0x0aeb0000 0x0 0x2008>; 2090 reg-names = "mdp", "vbif"; 2091 2092 interrupt-parent = <&mdss>; 2093 interrupts = <0>; 2094 2095 clocks = <&gcc GCC_DISP_AXI_CLK>, 2096 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2097 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2098 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2099 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2100 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2101 clock-names = "bus", 2102 "iface", 2103 "rot", 2104 "lut", 2105 "core", 2106 "vsync"; 2107 2108 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2109 assigned-clock-rates = <19200000>; 2110 2111 operating-points-v2 = <&mdp_opp_table>; 2112 power-domains = <&rpmhpd SM6350_CX>; 2113 2114 ports { 2115 #address-cells = <1>; 2116 #size-cells = <0>; 2117 2118 port@0 { 2119 reg = <0>; 2120 2121 dpu_intf1_out: endpoint { 2122 remote-endpoint = <&mdss_dsi0_in>; 2123 }; 2124 }; 2125 2126 port@2 { 2127 reg = <2>; 2128 2129 dpu_intf0_out: endpoint { 2130 remote-endpoint = <&mdss_dp_in>; 2131 }; 2132 }; 2133 }; 2134 2135 mdp_opp_table: opp-table { 2136 compatible = "operating-points-v2"; 2137 2138 opp-19200000 { 2139 opp-hz = /bits/ 64 <19200000>; 2140 required-opps = <&rpmhpd_opp_min_svs>; 2141 }; 2142 2143 opp-200000000 { 2144 opp-hz = /bits/ 64 <200000000>; 2145 required-opps = <&rpmhpd_opp_low_svs>; 2146 }; 2147 2148 opp-300000000 { 2149 opp-hz = /bits/ 64 <300000000>; 2150 required-opps = <&rpmhpd_opp_svs>; 2151 }; 2152 2153 opp-373333333 { 2154 opp-hz = /bits/ 64 <373333333>; 2155 required-opps = <&rpmhpd_opp_svs_l1>; 2156 }; 2157 2158 opp-448000000 { 2159 opp-hz = /bits/ 64 <448000000>; 2160 required-opps = <&rpmhpd_opp_nom>; 2161 }; 2162 2163 opp-560000000 { 2164 opp-hz = /bits/ 64 <560000000>; 2165 required-opps = <&rpmhpd_opp_turbo>; 2166 }; 2167 }; 2168 }; 2169 2170 mdss_dp: displayport-controller@ae90000 { 2171 compatible = "qcom,sm6350-dp", "qcom,sm8350-dp"; 2172 reg = <0x0 0xae90000 0x0 0x200>, 2173 <0x0 0xae90200 0x0 0x200>, 2174 <0x0 0xae90400 0x0 0x600>, 2175 <0x0 0xae91000 0x0 0x400>, 2176 <0x0 0xae91400 0x0 0x400>; 2177 interrupt-parent = <&mdss>; 2178 interrupts = <12>; 2179 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2180 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 2181 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 2182 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 2183 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 2184 clock-names = "core_iface", 2185 "core_aux", 2186 "ctrl_link", 2187 "ctrl_link_iface", 2188 "stream_pixel"; 2189 2190 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 2191 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 2192 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2193 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2194 2195 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 2196 phy-names = "dp"; 2197 2198 #sound-dai-cells = <0>; 2199 2200 operating-points-v2 = <&dp_opp_table>; 2201 power-domains = <&rpmhpd SM6350_CX>; 2202 2203 status = "disabled"; 2204 2205 ports { 2206 #address-cells = <1>; 2207 #size-cells = <0>; 2208 2209 port@0 { 2210 reg = <0>; 2211 2212 mdss_dp_in: endpoint { 2213 remote-endpoint = <&dpu_intf0_out>; 2214 }; 2215 }; 2216 2217 port@1 { 2218 reg = <1>; 2219 2220 mdss_dp_out: endpoint { 2221 }; 2222 }; 2223 }; 2224 2225 dp_opp_table: opp-table { 2226 compatible = "operating-points-v2"; 2227 2228 opp-160000000 { 2229 opp-hz = /bits/ 64 <160000000>; 2230 required-opps = <&rpmhpd_opp_low_svs>; 2231 }; 2232 2233 opp-270000000 { 2234 opp-hz = /bits/ 64 <270000000>; 2235 required-opps = <&rpmhpd_opp_svs>; 2236 }; 2237 2238 opp-540000000 { 2239 opp-hz = /bits/ 64 <540000000>; 2240 required-opps = <&rpmhpd_opp_svs_l1>; 2241 }; 2242 2243 opp-810000000 { 2244 opp-hz = /bits/ 64 <810000000>; 2245 required-opps = <&rpmhpd_opp_nom>; 2246 }; 2247 }; 2248 }; 2249 2250 mdss_dsi0: dsi@ae94000 { 2251 compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2252 reg = <0x0 0x0ae94000 0x0 0x400>; 2253 reg-names = "dsi_ctrl"; 2254 2255 interrupt-parent = <&mdss>; 2256 interrupts = <4>; 2257 2258 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2259 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2260 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2261 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2262 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2263 <&gcc GCC_DISP_AXI_CLK>; 2264 clock-names = "byte", 2265 "byte_intf", 2266 "pixel", 2267 "core", 2268 "iface", 2269 "bus"; 2270 2271 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2272 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2273 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2274 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 2275 2276 operating-points-v2 = <&mdss_dsi_opp_table>; 2277 power-domains = <&rpmhpd SM6350_MX>; 2278 2279 phys = <&mdss_dsi0_phy>; 2280 phy-names = "dsi"; 2281 2282 #address-cells = <1>; 2283 #size-cells = <0>; 2284 2285 status = "disabled"; 2286 2287 ports { 2288 #address-cells = <1>; 2289 #size-cells = <0>; 2290 2291 port@0 { 2292 reg = <0>; 2293 2294 mdss_dsi0_in: endpoint { 2295 remote-endpoint = <&dpu_intf1_out>; 2296 }; 2297 }; 2298 2299 port@1 { 2300 reg = <1>; 2301 2302 mdss_dsi0_out: endpoint { 2303 }; 2304 }; 2305 }; 2306 2307 mdss_dsi_opp_table: opp-table { 2308 compatible = "operating-points-v2"; 2309 2310 opp-187500000 { 2311 opp-hz = /bits/ 64 <187500000>; 2312 required-opps = <&rpmhpd_opp_low_svs>; 2313 }; 2314 2315 opp-300000000 { 2316 opp-hz = /bits/ 64 <300000000>; 2317 required-opps = <&rpmhpd_opp_svs>; 2318 }; 2319 2320 opp-358000000 { 2321 opp-hz = /bits/ 64 <358000000>; 2322 required-opps = <&rpmhpd_opp_svs_l1>; 2323 }; 2324 }; 2325 }; 2326 2327 mdss_dsi0_phy: phy@ae94400 { 2328 compatible = "qcom,dsi-phy-10nm"; 2329 reg = <0x0 0x0ae94400 0x0 0x200>, 2330 <0x0 0x0ae94600 0x0 0x280>, 2331 <0x0 0x0ae94a00 0x0 0x1e0>; 2332 reg-names = "dsi_phy", 2333 "dsi_phy_lane", 2334 "dsi_pll"; 2335 2336 #clock-cells = <1>; 2337 #phy-cells = <0>; 2338 2339 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2340 <&rpmhcc RPMH_CXO_CLK>; 2341 clock-names = "iface", "ref"; 2342 2343 status = "disabled"; 2344 }; 2345 }; 2346 2347 dispcc: clock-controller@af00000 { 2348 compatible = "qcom,sm6350-dispcc"; 2349 reg = <0x0 0x0af00000 0x0 0x20000>; 2350 clocks = <&rpmhcc RPMH_CXO_CLK>, 2351 <&gcc GCC_DISP_GPLL0_CLK>, 2352 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2353 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 2354 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2355 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2356 clock-names = "bi_tcxo", 2357 "gcc_disp_gpll0_clk", 2358 "dsi0_phy_pll_out_byteclk", 2359 "dsi0_phy_pll_out_dsiclk", 2360 "dp_phy_pll_link_clk", 2361 "dp_phy_pll_vco_div_clk"; 2362 #clock-cells = <1>; 2363 #reset-cells = <1>; 2364 #power-domain-cells = <1>; 2365 }; 2366 2367 pdc: interrupt-controller@b220000 { 2368 compatible = "qcom,sm6350-pdc", "qcom,pdc"; 2369 reg = <0x0 0x0b220000 0x0 0x30000>, <0x0 0x17c000f0 0x0 0x64>; 2370 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 2371 <125 63 1>, <126 655 12>, <138 139 15>; 2372 #interrupt-cells = <2>; 2373 interrupt-parent = <&intc>; 2374 interrupt-controller; 2375 }; 2376 2377 tsens0: thermal-sensor@c263000 { 2378 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 2379 reg = <0x0 0x0c263000 0x0 0x1ff>, /* TM */ 2380 <0x0 0x0c222000 0x0 0x8>; /* SROT */ 2381 #qcom,sensors = <16>; 2382 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 2383 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 2384 interrupt-names = "uplow", "critical"; 2385 #thermal-sensor-cells = <1>; 2386 }; 2387 2388 tsens1: thermal-sensor@c265000 { 2389 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 2390 reg = <0x0 0x0c265000 0x0 0x1ff>, /* TM */ 2391 <0x0 0x0c223000 0x0 0x8>; /* SROT */ 2392 #qcom,sensors = <16>; 2393 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 2394 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 2395 interrupt-names = "uplow", "critical"; 2396 #thermal-sensor-cells = <1>; 2397 }; 2398 2399 aoss_qmp: power-management@c300000 { 2400 compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp"; 2401 reg = <0x0 0x0c300000 0x0 0x1000>; 2402 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2403 IRQ_TYPE_EDGE_RISING>; 2404 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2405 2406 #clock-cells = <0>; 2407 }; 2408 2409 spmi_bus: spmi@c440000 { 2410 compatible = "qcom,spmi-pmic-arb"; 2411 reg = <0x0 0x0c440000 0x0 0x1100>, 2412 <0x0 0x0c600000 0x0 0x2000000>, 2413 <0x0 0x0e600000 0x0 0x100000>, 2414 <0x0 0x0e700000 0x0 0xa0000>, 2415 <0x0 0x0c40a000 0x0 0x26000>; 2416 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2417 interrupt-names = "periph_irq"; 2418 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2419 qcom,ee = <0>; 2420 qcom,channel = <0>; 2421 #address-cells = <2>; 2422 #size-cells = <0>; 2423 interrupt-controller; 2424 #interrupt-cells = <4>; 2425 }; 2426 2427 tlmm: pinctrl@f100000 { 2428 compatible = "qcom,sm6350-tlmm"; 2429 reg = <0x0 0x0f100000 0x0 0x300000>; 2430 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 2431 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 2432 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 2433 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 2434 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 2435 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 2436 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 2437 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 2438 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 2439 gpio-controller; 2440 #gpio-cells = <2>; 2441 interrupt-controller; 2442 #interrupt-cells = <2>; 2443 gpio-ranges = <&tlmm 0 0 157>; 2444 wakeup-parent = <&pdc>; 2445 2446 cci0_default: cci0-default-state { 2447 pins = "gpio39", "gpio40"; 2448 function = "cci_i2c"; 2449 drive-strength = <2>; 2450 bias-pull-up; 2451 }; 2452 2453 cci0_sleep: cci0-sleep-state { 2454 pins = "gpio39", "gpio40"; 2455 function = "cci_i2c"; 2456 drive-strength = <2>; 2457 bias-pull-down; 2458 }; 2459 2460 cci1_default: cci1-default-state { 2461 pins = "gpio41", "gpio42"; 2462 function = "cci_i2c"; 2463 drive-strength = <2>; 2464 bias-pull-up; 2465 }; 2466 2467 cci1_sleep: cci1-sleep-state { 2468 pins = "gpio41", "gpio42"; 2469 function = "cci_i2c"; 2470 drive-strength = <2>; 2471 bias-pull-down; 2472 }; 2473 2474 cci2_default: cci2-default-state { 2475 pins = "gpio43", "gpio44"; 2476 function = "cci_i2c"; 2477 drive-strength = <2>; 2478 bias-pull-up; 2479 }; 2480 2481 cci2_sleep: cci2-sleep-state { 2482 pins = "gpio43", "gpio44"; 2483 function = "cci_i2c"; 2484 drive-strength = <2>; 2485 bias-pull-down; 2486 }; 2487 2488 sdc2_off_state: sdc2-off-state { 2489 clk-pins { 2490 pins = "sdc2_clk"; 2491 drive-strength = <2>; 2492 bias-disable; 2493 }; 2494 2495 cmd-pins { 2496 pins = "sdc2_cmd"; 2497 drive-strength = <2>; 2498 bias-pull-up; 2499 }; 2500 2501 data-pins { 2502 pins = "sdc2_data"; 2503 drive-strength = <2>; 2504 bias-pull-up; 2505 }; 2506 }; 2507 2508 sdc2_on_state: sdc2-on-state { 2509 clk-pins { 2510 pins = "sdc2_clk"; 2511 drive-strength = <16>; 2512 bias-disable; 2513 }; 2514 2515 cmd-pins { 2516 pins = "sdc2_cmd"; 2517 drive-strength = <10>; 2518 bias-pull-up; 2519 }; 2520 2521 data-pins { 2522 pins = "sdc2_data"; 2523 drive-strength = <10>; 2524 bias-pull-up; 2525 }; 2526 }; 2527 2528 qup_uart9_default: qup-uart9-default-state { 2529 pins = "gpio25", "gpio26"; 2530 function = "qup13_f2"; 2531 drive-strength = <2>; 2532 bias-disable; 2533 }; 2534 2535 qup_i2c0_default: qup-i2c0-default-state { 2536 pins = "gpio0", "gpio1"; 2537 function = "qup00"; 2538 drive-strength = <2>; 2539 bias-pull-up; 2540 }; 2541 2542 qup_i2c2_default: qup-i2c2-default-state { 2543 pins = "gpio45", "gpio46"; 2544 function = "qup02"; 2545 drive-strength = <2>; 2546 bias-pull-up; 2547 }; 2548 2549 qup_i2c6_default: qup-i2c6-default-state { 2550 pins = "gpio13", "gpio14"; 2551 function = "qup10"; 2552 drive-strength = <2>; 2553 bias-pull-up; 2554 }; 2555 2556 qup_i2c7_default: qup-i2c7-default-state { 2557 pins = "gpio27", "gpio28"; 2558 function = "qup11"; 2559 drive-strength = <2>; 2560 bias-pull-up; 2561 }; 2562 2563 qup_i2c8_default: qup-i2c8-default-state { 2564 pins = "gpio19", "gpio20"; 2565 function = "qup12"; 2566 drive-strength = <2>; 2567 bias-pull-up; 2568 }; 2569 2570 qup_i2c10_default: qup-i2c10-default-state { 2571 pins = "gpio4", "gpio5"; 2572 function = "qup14"; 2573 drive-strength = <2>; 2574 bias-pull-up; 2575 }; 2576 2577 qup_uart1_cts: qup-uart1-cts-default-state { 2578 pins = "gpio61"; 2579 function = "qup01"; 2580 drive-strength = <2>; 2581 bias-disable; 2582 }; 2583 2584 qup_uart1_rts: qup-uart1-rts-default-state { 2585 pins = "gpio62"; 2586 function = "qup01"; 2587 drive-strength = <2>; 2588 bias-pull-down; 2589 }; 2590 2591 qup_uart1_rx: qup-uart1-rx-default-state { 2592 pins = "gpio64"; 2593 function = "qup01"; 2594 drive-strength = <2>; 2595 bias-disable; 2596 }; 2597 2598 qup_uart1_tx: qup-uart1-tx-default-state { 2599 pins = "gpio63"; 2600 function = "qup01"; 2601 drive-strength = <2>; 2602 bias-pull-up; 2603 }; 2604 }; 2605 2606 apps_smmu: iommu@15000000 { 2607 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500"; 2608 reg = <0x0 0x15000000 0x0 0x100000>; 2609 #iommu-cells = <2>; 2610 #global-interrupts = <1>; 2611 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 2612 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 2613 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 2614 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2615 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2616 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2617 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2618 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2619 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2620 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2621 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2622 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2623 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2624 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2625 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2626 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2627 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2628 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2629 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2630 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2631 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2632 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2633 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2634 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2635 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2636 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 2637 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 2638 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 2639 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 2640 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 2641 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 2642 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 2643 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 2644 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 2645 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 2646 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 2647 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 2648 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 2649 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 2650 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 2651 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 2652 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 2653 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2654 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2655 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2656 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2657 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2658 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2659 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2660 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2661 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2662 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2663 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2664 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2665 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2666 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2667 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2668 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2669 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2670 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2671 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2672 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2673 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2674 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2675 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2676 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2677 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2678 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2679 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2680 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2681 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 2682 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2683 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 2684 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 2685 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 2686 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 2687 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 2688 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 2689 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 2690 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 2691 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 2692 dma-coherent; 2693 }; 2694 2695 intc: interrupt-controller@17a00000 { 2696 compatible = "arm,gic-v3"; 2697 #interrupt-cells = <3>; 2698 interrupt-controller; 2699 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 2700 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 2701 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; 2702 }; 2703 2704 watchdog@17c10000 { 2705 compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt"; 2706 reg = <0x0 0x17c10000 0x0 0x1000>; 2707 clocks = <&sleep_clk>; 2708 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 2709 }; 2710 2711 timer@17c20000 { 2712 compatible = "arm,armv7-timer-mem"; 2713 reg = <0x0 0x17c20000 0x0 0x1000>; 2714 clock-frequency = <19200000>; 2715 #address-cells = <1>; 2716 #size-cells = <1>; 2717 ranges = <0 0 0 0x20000000>; 2718 2719 frame@17c21000 { 2720 frame-number = <0>; 2721 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2722 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 2723 reg = <0x17c21000 0x1000>, 2724 <0x17c22000 0x1000>; 2725 }; 2726 2727 frame@17c23000 { 2728 frame-number = <1>; 2729 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2730 reg = <0x17c23000 0x1000>; 2731 status = "disabled"; 2732 }; 2733 2734 frame@17c25000 { 2735 frame-number = <2>; 2736 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2737 reg = <0x17c25000 0x1000>; 2738 status = "disabled"; 2739 }; 2740 2741 frame@17c27000 { 2742 frame-number = <3>; 2743 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2744 reg = <0x17c27000 0x1000>; 2745 status = "disabled"; 2746 }; 2747 2748 frame@17c29000 { 2749 frame-number = <4>; 2750 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2751 reg = <0x17c29000 0x1000>; 2752 status = "disabled"; 2753 }; 2754 2755 frame@17c2b000 { 2756 frame-number = <5>; 2757 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2758 reg = <0x17c2b000 0x1000>; 2759 status = "disabled"; 2760 }; 2761 2762 frame@17c2d000 { 2763 frame-number = <6>; 2764 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2765 reg = <0x17c2d000 0x1000>; 2766 status = "disabled"; 2767 }; 2768 }; 2769 2770 apps_rsc: rsc@18200000 { 2771 compatible = "qcom,rpmh-rsc"; 2772 label = "apps_rsc"; 2773 reg = <0x0 0x18200000 0x0 0x10000>, 2774 <0x0 0x18210000 0x0 0x10000>, 2775 <0x0 0x18220000 0x0 0x10000>; 2776 reg-names = "drv-0", "drv-1", "drv-2"; 2777 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2778 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2779 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 2780 qcom,tcs-offset = <0xd00>; 2781 qcom,drv-id = <2>; 2782 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 2783 <WAKE_TCS 3>, <CONTROL_TCS 1>; 2784 power-domains = <&cluster_pd>; 2785 2786 rpmhcc: clock-controller { 2787 compatible = "qcom,sm6350-rpmh-clk"; 2788 #clock-cells = <1>; 2789 clock-names = "xo"; 2790 clocks = <&xo_board>; 2791 }; 2792 2793 rpmhpd: power-controller { 2794 compatible = "qcom,sm6350-rpmhpd"; 2795 #power-domain-cells = <1>; 2796 operating-points-v2 = <&rpmhpd_opp_table>; 2797 2798 rpmhpd_opp_table: opp-table { 2799 compatible = "operating-points-v2"; 2800 2801 rpmhpd_opp_ret: opp1 { 2802 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 2803 }; 2804 2805 rpmhpd_opp_min_svs: opp2 { 2806 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2807 }; 2808 2809 rpmhpd_opp_low_svs: opp3 { 2810 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2811 }; 2812 2813 rpmhpd_opp_svs: opp4 { 2814 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2815 }; 2816 2817 rpmhpd_opp_svs_l1: opp5 { 2818 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2819 }; 2820 2821 rpmhpd_opp_nom: opp6 { 2822 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2823 }; 2824 2825 rpmhpd_opp_nom_l1: opp7 { 2826 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2827 }; 2828 2829 rpmhpd_opp_nom_l2: opp8 { 2830 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 2831 }; 2832 2833 rpmhpd_opp_turbo: opp9 { 2834 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2835 }; 2836 2837 rpmhpd_opp_turbo_l1: opp10 { 2838 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2839 }; 2840 }; 2841 }; 2842 2843 apps_bcm_voter: bcm-voter { 2844 compatible = "qcom,bcm-voter"; 2845 }; 2846 }; 2847 2848 osm_l3: interconnect@18321000 { 2849 compatible = "qcom,sm6350-osm-l3", "qcom,osm-l3"; 2850 reg = <0x0 0x18321000 0x0 0x1000>; 2851 2852 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2853 clock-names = "xo", "alternate"; 2854 2855 #interconnect-cells = <1>; 2856 }; 2857 2858 cpufreq_hw: cpufreq@18323000 { 2859 compatible = "qcom,sm6350-cpufreq-hw", "qcom,cpufreq-hw"; 2860 reg = <0x0 0x18323000 0x0 0x1000>, <0x0 0x18325800 0x0 0x1000>; 2861 reg-names = "freq-domain0", "freq-domain1"; 2862 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2863 clock-names = "xo", "alternate"; 2864 2865 #freq-domain-cells = <1>; 2866 #clock-cells = <1>; 2867 }; 2868 2869 wifi: wifi@18800000 { 2870 compatible = "qcom,wcn3990-wifi"; 2871 reg = <0x0 0x18800000 0x0 0x800000>; 2872 reg-names = "membase"; 2873 memory-region = <&wlan_fw_mem>; 2874 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 2875 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 2876 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 2877 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 2878 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2879 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 2880 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 2881 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2882 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2883 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2884 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2885 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 2886 iommus = <&apps_smmu 0x20 0x1>; 2887 qcom,msa-fixed-perm; 2888 status = "disabled"; 2889 }; 2890 }; 2891 2892 thermal-zones { 2893 aoss0-thermal { 2894 thermal-sensors = <&tsens0 0>; 2895 2896 trips { 2897 aoss0-crit { 2898 temperature = <125000>; 2899 hysteresis = <0>; 2900 type = "critical"; 2901 }; 2902 }; 2903 }; 2904 2905 aoss1-thermal { 2906 thermal-sensors = <&tsens1 0>; 2907 2908 trips { 2909 aoss1-crit { 2910 temperature = <125000>; 2911 hysteresis = <0>; 2912 type = "critical"; 2913 }; 2914 }; 2915 }; 2916 2917 audio-thermal { 2918 thermal-sensors = <&tsens1 2>; 2919 2920 trips { 2921 audio-crit { 2922 temperature = <125000>; 2923 hysteresis = <0>; 2924 type = "critical"; 2925 }; 2926 }; 2927 }; 2928 2929 camera-thermal { 2930 thermal-sensors = <&tsens1 5>; 2931 2932 trips { 2933 camera-crit { 2934 temperature = <125000>; 2935 hysteresis = <0>; 2936 type = "critical"; 2937 }; 2938 }; 2939 }; 2940 2941 cpu0-thermal { 2942 thermal-sensors = <&tsens0 1>; 2943 2944 trips { 2945 cpu0_alert0: trip-point0 { 2946 temperature = <95000>; 2947 hysteresis = <2000>; 2948 type = "passive"; 2949 }; 2950 2951 cpu0-crit { 2952 temperature = <115000>; 2953 hysteresis = <0>; 2954 type = "critical"; 2955 }; 2956 }; 2957 2958 cooling-maps { 2959 map0 { 2960 trip = <&cpu0_alert0>; 2961 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2962 }; 2963 }; 2964 }; 2965 2966 cpu1-thermal { 2967 thermal-sensors = <&tsens0 2>; 2968 2969 trips { 2970 cpu1_alert0: trip-point0 { 2971 temperature = <95000>; 2972 hysteresis = <2000>; 2973 type = "passive"; 2974 }; 2975 2976 cpu1-crit { 2977 temperature = <115000>; 2978 hysteresis = <0>; 2979 type = "critical"; 2980 }; 2981 }; 2982 2983 cooling-maps { 2984 map0 { 2985 trip = <&cpu1_alert0>; 2986 cooling-device = <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2987 }; 2988 }; 2989 }; 2990 2991 cpu2-thermal { 2992 thermal-sensors = <&tsens0 3>; 2993 2994 trips { 2995 cpu2_alert0: trip-point0 { 2996 temperature = <95000>; 2997 hysteresis = <2000>; 2998 type = "passive"; 2999 }; 3000 3001 cpu2-crit { 3002 temperature = <115000>; 3003 hysteresis = <0>; 3004 type = "critical"; 3005 }; 3006 }; 3007 3008 cooling-maps { 3009 map0 { 3010 trip = <&cpu2_alert0>; 3011 cooling-device = <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3012 }; 3013 }; 3014 }; 3015 3016 cpu3-thermal { 3017 thermal-sensors = <&tsens0 4>; 3018 3019 trips { 3020 cpu3_alert0: trip-point0 { 3021 temperature = <95000>; 3022 hysteresis = <2000>; 3023 type = "passive"; 3024 }; 3025 3026 cpu3-crit { 3027 temperature = <115000>; 3028 hysteresis = <0>; 3029 type = "critical"; 3030 }; 3031 }; 3032 3033 cooling-maps { 3034 map0 { 3035 trip = <&cpu3_alert0>; 3036 cooling-device = <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3037 }; 3038 }; 3039 }; 3040 3041 cpu4-thermal { 3042 thermal-sensors = <&tsens0 5>; 3043 3044 trips { 3045 cpu4_alert0: trip-point0 { 3046 temperature = <95000>; 3047 hysteresis = <2000>; 3048 type = "passive"; 3049 }; 3050 3051 cpu4-crit { 3052 temperature = <115000>; 3053 hysteresis = <0>; 3054 type = "critical"; 3055 }; 3056 }; 3057 3058 cooling-maps { 3059 map0 { 3060 trip = <&cpu4_alert0>; 3061 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3062 }; 3063 }; 3064 }; 3065 3066 cpu5-thermal { 3067 thermal-sensors = <&tsens0 6>; 3068 3069 trips { 3070 cpu5_alert0: trip-point0 { 3071 temperature = <95000>; 3072 hysteresis = <2000>; 3073 type = "passive"; 3074 }; 3075 3076 cpu5-crit { 3077 temperature = <115000>; 3078 hysteresis = <0>; 3079 type = "critical"; 3080 }; 3081 }; 3082 3083 cooling-maps { 3084 map0 { 3085 trip = <&cpu5_alert0>; 3086 cooling-device = <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3087 }; 3088 }; 3089 }; 3090 3091 cpu6-left-thermal { 3092 thermal-sensors = <&tsens0 9>; 3093 3094 trips { 3095 cpu6_left_alert0: trip-point0 { 3096 temperature = <95000>; 3097 hysteresis = <2000>; 3098 type = "passive"; 3099 }; 3100 3101 cpu6-left-crit { 3102 temperature = <115000>; 3103 hysteresis = <0>; 3104 type = "critical"; 3105 }; 3106 }; 3107 3108 cooling-maps { 3109 map0 { 3110 trip = <&cpu6_left_alert0>; 3111 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3112 }; 3113 }; 3114 }; 3115 3116 cpu6-right-thermal { 3117 thermal-sensors = <&tsens0 10>; 3118 3119 trips { 3120 cpu6_right_alert0: trip-point0 { 3121 temperature = <95000>; 3122 hysteresis = <2000>; 3123 type = "passive"; 3124 }; 3125 3126 cpu6-right-crit { 3127 temperature = <115000>; 3128 hysteresis = <0>; 3129 type = "critical"; 3130 }; 3131 }; 3132 3133 cooling-maps { 3134 map0 { 3135 trip = <&cpu6_right_alert0>; 3136 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3137 }; 3138 }; 3139 }; 3140 3141 cpu7-left-thermal { 3142 thermal-sensors = <&tsens0 11>; 3143 3144 trips { 3145 cpu7_left_alert0: trip-point0 { 3146 temperature = <95000>; 3147 hysteresis = <2000>; 3148 type = "passive"; 3149 }; 3150 3151 cpu7-left-crit { 3152 temperature = <115000>; 3153 hysteresis = <0>; 3154 type = "critical"; 3155 }; 3156 }; 3157 3158 cooling-maps { 3159 map0 { 3160 trip = <&cpu7_left_alert0>; 3161 cooling-device = <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3162 }; 3163 }; 3164 }; 3165 3166 cpu7-right-thermal { 3167 thermal-sensors = <&tsens0 12>; 3168 3169 trips { 3170 cpu7_right_alert0: trip-point0 { 3171 temperature = <95000>; 3172 hysteresis = <2000>; 3173 type = "passive"; 3174 }; 3175 3176 cpu7-right-crit { 3177 temperature = <115000>; 3178 hysteresis = <0>; 3179 type = "critical"; 3180 }; 3181 }; 3182 3183 cooling-maps { 3184 map0 { 3185 trip = <&cpu7_right_alert0>; 3186 cooling-device = <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3187 }; 3188 }; 3189 }; 3190 3191 cpuss0-thermal { 3192 thermal-sensors = <&tsens0 7>; 3193 3194 trips { 3195 cpuss0-crit { 3196 temperature = <125000>; 3197 hysteresis = <0>; 3198 type = "critical"; 3199 }; 3200 }; 3201 }; 3202 3203 cpuss1-thermal { 3204 thermal-sensors = <&tsens0 8>; 3205 3206 trips { 3207 cpuss1-crit { 3208 temperature = <125000>; 3209 hysteresis = <0>; 3210 type = "critical"; 3211 }; 3212 }; 3213 }; 3214 3215 cwlan-thermal { 3216 thermal-sensors = <&tsens1 1>; 3217 3218 trips { 3219 cwlan-crit { 3220 temperature = <125000>; 3221 hysteresis = <0>; 3222 type = "critical"; 3223 }; 3224 }; 3225 }; 3226 3227 ddr-thermal { 3228 thermal-sensors = <&tsens1 3>; 3229 3230 trips { 3231 ddr-crit { 3232 temperature = <125000>; 3233 hysteresis = <0>; 3234 type = "critical"; 3235 }; 3236 }; 3237 }; 3238 3239 gpuss0-thermal { 3240 polling-delay-passive = <250>; 3241 3242 thermal-sensors = <&tsens0 13>; 3243 3244 trips { 3245 gpuss0_alert0: trip-point0 { 3246 temperature = <85000>; 3247 hysteresis = <2000>; 3248 type = "passive"; 3249 }; 3250 3251 gpuss0-crit { 3252 temperature = <110000>; 3253 hysteresis = <1000>; 3254 type = "critical"; 3255 }; 3256 }; 3257 3258 cooling-maps { 3259 map0 { 3260 trip = <&gpuss0_alert0>; 3261 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3262 }; 3263 }; 3264 }; 3265 3266 gpuss1-thermal { 3267 polling-delay-passive = <250>; 3268 3269 thermal-sensors = <&tsens0 14>; 3270 3271 trips { 3272 gpuss1_alert0: trip-point0 { 3273 temperature = <85000>; 3274 hysteresis = <2000>; 3275 type = "passive"; 3276 }; 3277 3278 gpuss1-crit { 3279 temperature = <110000>; 3280 hysteresis = <1000>; 3281 type = "critical"; 3282 }; 3283 }; 3284 3285 cooling-maps { 3286 map0 { 3287 trip = <&gpuss1_alert0>; 3288 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3289 }; 3290 }; 3291 }; 3292 3293 modem-core0-thermal { 3294 thermal-sensors = <&tsens1 6>; 3295 3296 trips { 3297 modem-core0-crit { 3298 temperature = <125000>; 3299 hysteresis = <0>; 3300 type = "critical"; 3301 }; 3302 }; 3303 }; 3304 3305 modem-core1-thermal { 3306 thermal-sensors = <&tsens1 7>; 3307 3308 trips { 3309 modem-core1-crit { 3310 temperature = <125000>; 3311 hysteresis = <0>; 3312 type = "critical"; 3313 }; 3314 }; 3315 }; 3316 3317 modem-scl-thermal { 3318 thermal-sensors = <&tsens1 9>; 3319 3320 trips { 3321 modem-scl-crit { 3322 temperature = <125000>; 3323 hysteresis = <0>; 3324 type = "critical"; 3325 }; 3326 }; 3327 }; 3328 3329 modem-vec-thermal { 3330 thermal-sensors = <&tsens1 8>; 3331 3332 trips { 3333 modem-vec-crit { 3334 temperature = <125000>; 3335 hysteresis = <0>; 3336 type = "critical"; 3337 }; 3338 }; 3339 }; 3340 3341 npu-thermal { 3342 thermal-sensors = <&tsens1 10>; 3343 3344 trips { 3345 npu-crit { 3346 temperature = <125000>; 3347 hysteresis = <0>; 3348 type = "critical"; 3349 }; 3350 }; 3351 }; 3352 3353 q6-hvx-thermal { 3354 thermal-sensors = <&tsens1 4>; 3355 3356 trips { 3357 q6-hvx-crit { 3358 temperature = <125000>; 3359 hysteresis = <0>; 3360 type = "critical"; 3361 }; 3362 }; 3363 }; 3364 3365 video-thermal { 3366 thermal-sensors = <&tsens1 11>; 3367 3368 trips { 3369 video-crit { 3370 temperature = <125000>; 3371 hysteresis = <0>; 3372 type = "critical"; 3373 }; 3374 }; 3375 }; 3376 }; 3377 3378 timer { 3379 compatible = "arm,armv8-timer"; 3380 clock-frequency = <19200000>; 3381 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3382 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3383 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3384 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 3385 }; 3386}; 3387