1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> 4 * Copyright (c) 2022, Luca Weiss <luca.weiss@fairphone.com> 5 */ 6 7#include <dt-bindings/clock/qcom,gcc-sm6350.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/dma/qcom-gpi.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interconnect/qcom,sm6350.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/mailbox/qcom-ipcc.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15#include <dt-bindings/soc/qcom,rpmh-rsc.h> 16 17/ { 18 interrupt-parent = <&intc>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 clocks { 23 xo_board: xo-board { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 clock-frequency = <76800000>; 27 clock-output-names = "xo_board"; 28 }; 29 30 sleep_clk: sleep-clk { 31 compatible = "fixed-clock"; 32 clock-frequency = <32764>; 33 #clock-cells = <0>; 34 }; 35 }; 36 37 cpus { 38 #address-cells = <2>; 39 #size-cells = <0>; 40 41 CPU0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "qcom,kryo560"; 44 reg = <0x0 0x0>; 45 enable-method = "psci"; 46 capacity-dmips-mhz = <1024>; 47 dynamic-power-coefficient = <100>; 48 next-level-cache = <&L2_0>; 49 qcom,freq-domain = <&cpufreq_hw 0>; 50 #cooling-cells = <2>; 51 L2_0: l2-cache { 52 compatible = "cache"; 53 next-level-cache = <&L3_0>; 54 L3_0: l3-cache { 55 compatible = "cache"; 56 }; 57 }; 58 }; 59 60 CPU1: cpu@100 { 61 device_type = "cpu"; 62 compatible = "qcom,kryo560"; 63 reg = <0x0 0x100>; 64 enable-method = "psci"; 65 capacity-dmips-mhz = <1024>; 66 dynamic-power-coefficient = <100>; 67 next-level-cache = <&L2_100>; 68 qcom,freq-domain = <&cpufreq_hw 0>; 69 #cooling-cells = <2>; 70 L2_100: l2-cache { 71 compatible = "cache"; 72 next-level-cache = <&L3_0>; 73 }; 74 }; 75 76 CPU2: cpu@200 { 77 device_type = "cpu"; 78 compatible = "qcom,kryo560"; 79 reg = <0x0 0x200>; 80 enable-method = "psci"; 81 capacity-dmips-mhz = <1024>; 82 dynamic-power-coefficient = <100>; 83 next-level-cache = <&L2_200>; 84 qcom,freq-domain = <&cpufreq_hw 0>; 85 #cooling-cells = <2>; 86 L2_200: l2-cache { 87 compatible = "cache"; 88 next-level-cache = <&L3_0>; 89 }; 90 }; 91 92 CPU3: cpu@300 { 93 device_type = "cpu"; 94 compatible = "qcom,kryo560"; 95 reg = <0x0 0x300>; 96 enable-method = "psci"; 97 capacity-dmips-mhz = <1024>; 98 dynamic-power-coefficient = <100>; 99 next-level-cache = <&L2_300>; 100 qcom,freq-domain = <&cpufreq_hw 0>; 101 #cooling-cells = <2>; 102 L2_300: l2-cache { 103 compatible = "cache"; 104 next-level-cache = <&L3_0>; 105 }; 106 }; 107 108 CPU4: cpu@400 { 109 device_type = "cpu"; 110 compatible = "qcom,kryo560"; 111 reg = <0x0 0x400>; 112 enable-method = "psci"; 113 capacity-dmips-mhz = <1024>; 114 dynamic-power-coefficient = <100>; 115 next-level-cache = <&L2_400>; 116 qcom,freq-domain = <&cpufreq_hw 0>; 117 #cooling-cells = <2>; 118 L2_400: l2-cache { 119 compatible = "cache"; 120 next-level-cache = <&L3_0>; 121 }; 122 }; 123 124 CPU5: cpu@500 { 125 device_type = "cpu"; 126 compatible = "qcom,kryo560"; 127 reg = <0x0 0x500>; 128 enable-method = "psci"; 129 capacity-dmips-mhz = <1024>; 130 dynamic-power-coefficient = <100>; 131 next-level-cache = <&L2_500>; 132 qcom,freq-domain = <&cpufreq_hw 0>; 133 #cooling-cells = <2>; 134 L2_500: l2-cache { 135 compatible = "cache"; 136 next-level-cache = <&L3_0>; 137 }; 138 139 }; 140 141 CPU6: cpu@600 { 142 device_type = "cpu"; 143 compatible = "qcom,kryo560"; 144 reg = <0x0 0x600>; 145 enable-method = "psci"; 146 capacity-dmips-mhz = <1894>; 147 dynamic-power-coefficient = <703>; 148 next-level-cache = <&L2_600>; 149 qcom,freq-domain = <&cpufreq_hw 1>; 150 #cooling-cells = <2>; 151 L2_600: l2-cache { 152 compatible = "cache"; 153 next-level-cache = <&L3_0>; 154 }; 155 }; 156 157 CPU7: cpu@700 { 158 device_type = "cpu"; 159 compatible = "qcom,kryo560"; 160 reg = <0x0 0x700>; 161 enable-method = "psci"; 162 capacity-dmips-mhz = <1894>; 163 dynamic-power-coefficient = <703>; 164 next-level-cache = <&L2_700>; 165 qcom,freq-domain = <&cpufreq_hw 1>; 166 #cooling-cells = <2>; 167 L2_700: l2-cache { 168 compatible = "cache"; 169 next-level-cache = <&L3_0>; 170 }; 171 }; 172 173 cpu-map { 174 cluster0 { 175 core0 { 176 cpu = <&CPU0>; 177 }; 178 179 core1 { 180 cpu = <&CPU1>; 181 }; 182 183 core2 { 184 cpu = <&CPU2>; 185 }; 186 187 core3 { 188 cpu = <&CPU3>; 189 }; 190 191 core4 { 192 cpu = <&CPU4>; 193 }; 194 195 core5 { 196 cpu = <&CPU5>; 197 }; 198 199 core6 { 200 cpu = <&CPU6>; 201 }; 202 203 core7 { 204 cpu = <&CPU7>; 205 }; 206 }; 207 }; 208 }; 209 210 firmware { 211 scm: scm { 212 compatible = "qcom,scm-sm6350", "qcom,scm"; 213 #reset-cells = <1>; 214 }; 215 }; 216 217 memory@80000000 { 218 device_type = "memory"; 219 /* We expect the bootloader to fill in the size */ 220 reg = <0x0 0x80000000 0x0 0x0>; 221 }; 222 223 pmu { 224 compatible = "arm,armv8-pmuv3"; 225 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>; 226 }; 227 228 psci { 229 compatible = "arm,psci-1.0"; 230 method = "smc"; 231 }; 232 233 reserved_memory: reserved-memory { 234 #address-cells = <2>; 235 #size-cells = <2>; 236 ranges; 237 238 hyp_mem: memory@80000000 { 239 reg = <0 0x80000000 0 0x600000>; 240 no-map; 241 }; 242 243 xbl_aop_mem: memory@80700000 { 244 reg = <0 0x80700000 0 0x160000>; 245 no-map; 246 }; 247 248 cmd_db: memory@80860000 { 249 compatible = "qcom,cmd-db"; 250 reg = <0 0x80860000 0 0x20000>; 251 no-map; 252 }; 253 254 sec_apps_mem: memory@808ff000 { 255 reg = <0 0x808ff000 0 0x1000>; 256 no-map; 257 }; 258 259 smem_mem: memory@80900000 { 260 reg = <0 0x80900000 0 0x200000>; 261 no-map; 262 }; 263 264 cdsp_sec_mem: memory@80b00000 { 265 reg = <0 0x80b00000 0 0x1e00000>; 266 no-map; 267 }; 268 269 pil_camera_mem: memory@86000000 { 270 reg = <0 0x86000000 0 0x500000>; 271 no-map; 272 }; 273 274 pil_npu_mem: memory@86500000 { 275 reg = <0 0x86500000 0 0x500000>; 276 no-map; 277 }; 278 279 pil_video_mem: memory@86a00000 { 280 reg = <0 0x86a00000 0 0x500000>; 281 no-map; 282 }; 283 284 pil_cdsp_mem: memory@86f00000 { 285 reg = <0 0x86f00000 0 0x1e00000>; 286 no-map; 287 }; 288 289 pil_adsp_mem: memory@88d00000 { 290 reg = <0 0x88d00000 0 0x2800000>; 291 no-map; 292 }; 293 294 wlan_fw_mem: memory@8b500000 { 295 reg = <0 0x8b500000 0 0x200000>; 296 no-map; 297 }; 298 299 pil_ipa_fw_mem: memory@8b700000 { 300 reg = <0 0x8b700000 0 0x10000>; 301 no-map; 302 }; 303 304 pil_ipa_gsi_mem: memory@8b710000 { 305 reg = <0 0x8b710000 0 0x5400>; 306 no-map; 307 }; 308 309 pil_gpu_mem: memory@8b715400 { 310 reg = <0 0x8b715400 0 0x2000>; 311 no-map; 312 }; 313 314 pil_modem_mem: memory@8b800000 { 315 reg = <0 0x8b800000 0 0xf800000>; 316 no-map; 317 }; 318 319 cont_splash_memory: memory@a0000000 { 320 reg = <0 0xa0000000 0 0x2300000>; 321 no-map; 322 }; 323 324 dfps_data_memory: memory@a2300000 { 325 reg = <0 0xa2300000 0 0x100000>; 326 no-map; 327 }; 328 329 removed_region: memory@c0000000 { 330 reg = <0 0xc0000000 0 0x3900000>; 331 no-map; 332 }; 333 334 debug_region: memory@ffb00000 { 335 reg = <0 0xffb00000 0 0xc0000>; 336 no-map; 337 }; 338 339 last_log_region: memory@ffbc0000 { 340 reg = <0 0xffbc0000 0 0x40000>; 341 no-map; 342 }; 343 344 ramoops: ramoops@ffc00000 { 345 compatible = "removed-dma-pool", "ramoops"; 346 reg = <0 0xffc00000 0 0x00100000>; 347 record-size = <0x1000>; 348 console-size = <0x40000>; 349 ftrace-size = <0x0>; 350 msg-size = <0x20000 0x20000>; 351 cc-size = <0x0>; 352 no-map; 353 }; 354 355 cmdline_region: memory@ffd00000 { 356 reg = <0 0xffd00000 0 0x1000>; 357 no-map; 358 }; 359 }; 360 361 smem { 362 compatible = "qcom,smem"; 363 memory-region = <&smem_mem>; 364 hwlocks = <&tcsr_mutex 3>; 365 }; 366 367 smp2p-adsp { 368 compatible = "qcom,smp2p"; 369 qcom,smem = <443>, <429>; 370 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 371 IPCC_MPROC_SIGNAL_SMP2P 372 IRQ_TYPE_EDGE_RISING>; 373 mboxes = <&ipcc IPCC_CLIENT_LPASS 374 IPCC_MPROC_SIGNAL_SMP2P>; 375 376 qcom,local-pid = <0>; 377 qcom,remote-pid = <2>; 378 379 smp2p_adsp_out: master-kernel { 380 qcom,entry-name = "master-kernel"; 381 #qcom,smem-state-cells = <1>; 382 }; 383 384 smp2p_adsp_in: slave-kernel { 385 qcom,entry-name = "slave-kernel"; 386 interrupt-controller; 387 #interrupt-cells = <2>; 388 }; 389 }; 390 391 smp2p-cdsp { 392 compatible = "qcom,smp2p"; 393 qcom,smem = <94>, <432>; 394 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 395 IPCC_MPROC_SIGNAL_SMP2P 396 IRQ_TYPE_EDGE_RISING>; 397 mboxes = <&ipcc IPCC_CLIENT_CDSP 398 IPCC_MPROC_SIGNAL_SMP2P>; 399 400 qcom,local-pid = <0>; 401 qcom,remote-pid = <5>; 402 403 smp2p_cdsp_out: master-kernel { 404 qcom,entry-name = "master-kernel"; 405 #qcom,smem-state-cells = <1>; 406 }; 407 408 smp2p_cdsp_in: slave-kernel { 409 qcom,entry-name = "slave-kernel"; 410 interrupt-controller; 411 #interrupt-cells = <2>; 412 }; 413 }; 414 415 smp2p-mpss { 416 compatible = "qcom,smp2p"; 417 qcom,smem = <435>, <428>; 418 419 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 420 IPCC_MPROC_SIGNAL_SMP2P 421 IRQ_TYPE_EDGE_RISING>; 422 mboxes = <&ipcc IPCC_CLIENT_MPSS 423 IPCC_MPROC_SIGNAL_SMP2P>; 424 425 qcom,local-pid = <0>; 426 qcom,remote-pid = <1>; 427 428 modem_smp2p_out: master-kernel { 429 qcom,entry-name = "master-kernel"; 430 #qcom,smem-state-cells = <1>; 431 }; 432 433 modem_smp2p_in: slave-kernel { 434 qcom,entry-name = "slave-kernel"; 435 436 interrupt-controller; 437 #interrupt-cells = <2>; 438 }; 439 }; 440 441 soc: soc@0 { 442 #address-cells = <2>; 443 #size-cells = <2>; 444 ranges = <0 0 0 0 0x10 0>; 445 dma-ranges = <0 0 0 0 0x10 0>; 446 compatible = "simple-bus"; 447 448 gcc: clock-controller@100000 { 449 compatible = "qcom,gcc-sm6350"; 450 reg = <0 0x00100000 0 0x1f0000>; 451 #clock-cells = <1>; 452 #reset-cells = <1>; 453 #power-domain-cells = <1>; 454 clock-names = "bi_tcxo", 455 "bi_tcxo_ao", 456 "sleep_clk"; 457 clocks = <&rpmhcc RPMH_CXO_CLK>, 458 <&rpmhcc RPMH_CXO_CLK_A>, 459 <&sleep_clk>; 460 }; 461 462 ipcc: mailbox@408000 { 463 compatible = "qcom,sm6350-ipcc", "qcom,ipcc"; 464 reg = <0 0x00408000 0 0x1000>; 465 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 466 interrupt-controller; 467 #interrupt-cells = <3>; 468 #mbox-cells = <2>; 469 }; 470 471 rng: rng@793000 { 472 compatible = "qcom,prng-ee"; 473 reg = <0 0x00793000 0 0x1000>; 474 clocks = <&gcc GCC_PRNG_AHB_CLK>; 475 clock-names = "core"; 476 }; 477 478 sdhc_1: mmc@7c4000 { 479 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 480 reg = <0 0x007c4000 0 0x1000>, 481 <0 0x007c5000 0 0x1000>, 482 <0 0x007c8000 0 0x8000>; 483 reg-names = "hc", "cqhci", "ice"; 484 485 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 487 interrupt-names = "hc_irq", "pwr_irq"; 488 iommus = <&apps_smmu 0x60 0x0>; 489 490 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 491 <&gcc GCC_SDCC1_APPS_CLK>, 492 <&rpmhcc RPMH_CXO_CLK>; 493 clock-names = "iface", "core", "xo"; 494 resets = <&gcc GCC_SDCC1_BCR>; 495 qcom,dll-config = <0x000f642c>; 496 qcom,ddr-config = <0x80040868>; 497 power-domains = <&rpmhpd SM6350_CX>; 498 operating-points-v2 = <&sdhc1_opp_table>; 499 bus-width = <8>; 500 non-removable; 501 supports-cqe; 502 503 status = "disabled"; 504 505 sdhc1_opp_table: opp-table { 506 compatible = "operating-points-v2"; 507 508 opp-19200000 { 509 opp-hz = /bits/ 64 <19200000>; 510 required-opps = <&rpmhpd_opp_min_svs>; 511 }; 512 513 opp-100000000 { 514 opp-hz = /bits/ 64 <100000000>; 515 required-opps = <&rpmhpd_opp_low_svs>; 516 }; 517 518 opp-384000000 { 519 opp-hz = /bits/ 64 <384000000>; 520 required-opps = <&rpmhpd_opp_svs_l1>; 521 }; 522 }; 523 }; 524 525 gpi_dma0: dma-controller@800000 { 526 compatible = "qcom,sm6350-gpi-dma"; 527 reg = <0 0x00800000 0 0x60000>; 528 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 535 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 536 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 538 dma-channels = <10>; 539 dma-channel-mask = <0x1f>; 540 iommus = <&apps_smmu 0x56 0x0>; 541 #dma-cells = <3>; 542 status = "disabled"; 543 }; 544 545 qupv3_id_0: geniqup@8c0000 { 546 compatible = "qcom,geni-se-qup"; 547 reg = <0x0 0x8c0000 0x0 0x2000>; 548 clock-names = "m-ahb", "s-ahb"; 549 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 550 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 551 #address-cells = <2>; 552 #size-cells = <2>; 553 iommus = <&apps_smmu 0x43 0x0>; 554 ranges; 555 status = "disabled"; 556 557 i2c0: i2c@880000 { 558 compatible = "qcom,geni-i2c"; 559 reg = <0 0x00880000 0 0x4000>; 560 clock-names = "se"; 561 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 562 pinctrl-names = "default"; 563 pinctrl-0 = <&qup_i2c0_default>; 564 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 565 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 566 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 567 dma-names = "tx", "rx"; 568 #address-cells = <1>; 569 #size-cells = <0>; 570 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 571 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 572 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 573 interconnect-names = "qup-core", "qup-config", "qup-memory"; 574 status = "disabled"; 575 }; 576 577 i2c2: i2c@888000 { 578 compatible = "qcom,geni-i2c"; 579 reg = <0 0x00888000 0 0x4000>; 580 clock-names = "se"; 581 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 582 pinctrl-names = "default"; 583 pinctrl-0 = <&qup_i2c2_default>; 584 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 585 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 586 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 587 dma-names = "tx", "rx"; 588 #address-cells = <1>; 589 #size-cells = <0>; 590 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 591 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 592 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 593 interconnect-names = "qup-core", "qup-config", "qup-memory"; 594 status = "disabled"; 595 }; 596 }; 597 598 gpi_dma1: dma-controller@900000 { 599 compatible = "qcom,sm6350-gpi-dma"; 600 reg = <0 0x00900000 0 0x60000>; 601 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 648 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 650 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>; 611 dma-channels = <10>; 612 dma-channel-mask = <0x3f>; 613 iommus = <&apps_smmu 0x4d6 0x0>; 614 #dma-cells = <3>; 615 status = "disabled"; 616 }; 617 618 qupv3_id_1: geniqup@9c0000 { 619 compatible = "qcom,geni-se-qup"; 620 reg = <0x0 0x9c0000 0x0 0x2000>; 621 clock-names = "m-ahb", "s-ahb"; 622 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 623 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 624 #address-cells = <2>; 625 #size-cells = <2>; 626 iommus = <&apps_smmu 0x4c3 0x0>; 627 ranges; 628 status = "disabled"; 629 630 i2c6: i2c@980000 { 631 compatible = "qcom,geni-i2c"; 632 reg = <0 0x00980000 0 0x4000>; 633 clock-names = "se"; 634 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 635 pinctrl-names = "default"; 636 pinctrl-0 = <&qup_i2c6_default>; 637 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 638 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 639 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 640 dma-names = "tx", "rx"; 641 #address-cells = <1>; 642 #size-cells = <0>; 643 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 644 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 645 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 646 interconnect-names = "qup-core", "qup-config", "qup-memory"; 647 status = "disabled"; 648 }; 649 650 i2c7: i2c@984000 { 651 compatible = "qcom,geni-i2c"; 652 reg = <0 0x00984000 0 0x4000>; 653 clock-names = "se"; 654 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 655 pinctrl-names = "default"; 656 pinctrl-0 = <&qup_i2c7_default>; 657 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 658 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 659 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 660 dma-names = "tx", "rx"; 661 #address-cells = <1>; 662 #size-cells = <0>; 663 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 664 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 665 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 666 interconnect-names = "qup-core", "qup-config", "qup-memory"; 667 status = "disabled"; 668 }; 669 670 i2c8: i2c@988000 { 671 compatible = "qcom,geni-i2c"; 672 reg = <0 0x00988000 0 0x4000>; 673 clock-names = "se"; 674 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 675 pinctrl-names = "default"; 676 pinctrl-0 = <&qup_i2c8_default>; 677 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 678 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 679 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 680 dma-names = "tx", "rx"; 681 #address-cells = <1>; 682 #size-cells = <0>; 683 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 684 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 685 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 686 interconnect-names = "qup-core", "qup-config", "qup-memory"; 687 status = "disabled"; 688 }; 689 690 uart9: serial@98c000 { 691 compatible = "qcom,geni-debug-uart"; 692 reg = <0 0x98c000 0 0x4000>; 693 clock-names = "se"; 694 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 695 pinctrl-names = "default"; 696 pinctrl-0 = <&qup_uart9_default>; 697 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 698 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 699 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 700 interconnect-names = "qup-core", "qup-config"; 701 status = "disabled"; 702 }; 703 704 i2c10: i2c@990000 { 705 compatible = "qcom,geni-i2c"; 706 reg = <0 0x00990000 0 0x4000>; 707 clock-names = "se"; 708 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 709 pinctrl-names = "default"; 710 pinctrl-0 = <&qup_i2c10_default>; 711 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 712 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 713 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 714 dma-names = "tx", "rx"; 715 #address-cells = <1>; 716 #size-cells = <0>; 717 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 718 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 719 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 720 interconnect-names = "qup-core", "qup-config", "qup-memory"; 721 status = "disabled"; 722 }; 723 724 }; 725 726 config_noc: interconnect@1500000 { 727 compatible = "qcom,sm6350-config-noc"; 728 reg = <0 0x01500000 0 0x28000>; 729 #interconnect-cells = <2>; 730 qcom,bcm-voters = <&apps_bcm_voter>; 731 }; 732 733 system_noc: interconnect@1620000 { 734 compatible = "qcom,sm6350-system-noc"; 735 reg = <0 0x01620000 0 0x17080>; 736 #interconnect-cells = <2>; 737 qcom,bcm-voters = <&apps_bcm_voter>; 738 739 clk_virt: interconnect-clk-virt { 740 compatible = "qcom,sm6350-clk-virt"; 741 #interconnect-cells = <2>; 742 qcom,bcm-voters = <&apps_bcm_voter>; 743 }; 744 }; 745 746 aggre1_noc: interconnect@16e0000 { 747 compatible = "qcom,sm6350-aggre1-noc"; 748 reg = <0 0x016e0000 0 0x15080>; 749 #interconnect-cells = <2>; 750 qcom,bcm-voters = <&apps_bcm_voter>; 751 }; 752 753 aggre2_noc: interconnect@1700000 { 754 compatible = "qcom,sm6350-aggre2-noc"; 755 reg = <0 0x01700000 0 0x1f880>; 756 #interconnect-cells = <2>; 757 qcom,bcm-voters = <&apps_bcm_voter>; 758 759 compute_noc: interconnect-compute-noc { 760 compatible = "qcom,sm6350-compute-noc"; 761 #interconnect-cells = <2>; 762 qcom,bcm-voters = <&apps_bcm_voter>; 763 }; 764 }; 765 766 mmss_noc: interconnect@1740000 { 767 compatible = "qcom,sm6350-mmss-noc"; 768 reg = <0 0x01740000 0 0x1c100>; 769 #interconnect-cells = <2>; 770 qcom,bcm-voters = <&apps_bcm_voter>; 771 }; 772 773 ufs_mem_hc: ufs@1d84000 { 774 compatible = "qcom,sm6350-ufshc", "qcom,ufshc", 775 "jedec,ufs-2.0"; 776 reg = <0 0x01d84000 0 0x3000>, 777 <0 0x01d90000 0 0x8000>; 778 reg-names = "std", "ice"; 779 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 780 phys = <&ufs_mem_phy_lanes>; 781 phy-names = "ufsphy"; 782 lanes-per-direction = <2>; 783 #reset-cells = <1>; 784 resets = <&gcc GCC_UFS_PHY_BCR>; 785 reset-names = "rst"; 786 787 power-domains = <&gcc UFS_PHY_GDSC>; 788 789 iommus = <&apps_smmu 0x80 0x0>; 790 791 clock-names = "core_clk", 792 "bus_aggr_clk", 793 "iface_clk", 794 "core_clk_unipro", 795 "ref_clk", 796 "tx_lane0_sync_clk", 797 "rx_lane0_sync_clk", 798 "rx_lane1_sync_clk", 799 "ice_core_clk"; 800 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 801 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 802 <&gcc GCC_UFS_PHY_AHB_CLK>, 803 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 804 <&rpmhcc RPMH_QLINK_CLK>, 805 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 806 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 807 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 808 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 809 freq-table-hz = 810 <50000000 200000000>, 811 <0 0>, 812 <0 0>, 813 <37500000 150000000>, 814 <75000000 300000000>, 815 <0 0>, 816 <0 0>, 817 <0 0>, 818 <0 0>; 819 820 status = "disabled"; 821 }; 822 823 ufs_mem_phy: phy@1d87000 { 824 compatible = "qcom,sm6350-qmp-ufs-phy"; 825 reg = <0 0x01d87000 0 0x18c>; 826 #address-cells = <2>; 827 #size-cells = <2>; 828 ranges; 829 830 clock-names = "ref", 831 "ref_aux"; 832 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 833 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 834 835 resets = <&ufs_mem_hc 0>; 836 reset-names = "ufsphy"; 837 838 status = "disabled"; 839 840 ufs_mem_phy_lanes: phy@1d87400 { 841 reg = <0 0x01d87400 0 0x128>, 842 <0 0x01d87600 0 0x1fc>, 843 <0 0x01d87c00 0 0x1dc>, 844 <0 0x01d87800 0 0x128>, 845 <0 0x01d87a00 0 0x1fc>; 846 #phy-cells = <0>; 847 }; 848 }; 849 850 tcsr_mutex: hwlock@1f40000 { 851 compatible = "qcom,tcsr-mutex"; 852 reg = <0x0 0x01f40000 0x0 0x40000>; 853 #hwlock-cells = <1>; 854 }; 855 856 adsp: remoteproc@3000000 { 857 compatible = "qcom,sm6350-adsp-pas"; 858 reg = <0 0x03000000 0 0x100>; 859 860 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 861 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 862 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 863 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 864 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 865 interrupt-names = "wdog", "fatal", "ready", 866 "handover", "stop-ack"; 867 868 clocks = <&rpmhcc RPMH_CXO_CLK>; 869 clock-names = "xo"; 870 871 power-domains = <&rpmhpd SM6350_LCX>, 872 <&rpmhpd SM6350_LMX>; 873 power-domain-names = "lcx", "lmx"; 874 875 memory-region = <&pil_adsp_mem>; 876 877 qcom,qmp = <&aoss_qmp>; 878 879 qcom,smem-states = <&smp2p_adsp_out 0>; 880 qcom,smem-state-names = "stop"; 881 882 status = "disabled"; 883 884 glink-edge { 885 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 886 IPCC_MPROC_SIGNAL_GLINK_QMP 887 IRQ_TYPE_EDGE_RISING>; 888 mboxes = <&ipcc IPCC_CLIENT_LPASS 889 IPCC_MPROC_SIGNAL_GLINK_QMP>; 890 891 label = "lpass"; 892 qcom,remote-pid = <2>; 893 894 fastrpc { 895 compatible = "qcom,fastrpc"; 896 qcom,glink-channels = "fastrpcglink-apps-dsp"; 897 label = "adsp"; 898 #address-cells = <1>; 899 #size-cells = <0>; 900 901 compute-cb@3 { 902 compatible = "qcom,fastrpc-compute-cb"; 903 reg = <3>; 904 iommus = <&apps_smmu 0x1003 0x0>; 905 }; 906 907 compute-cb@4 { 908 compatible = "qcom,fastrpc-compute-cb"; 909 reg = <4>; 910 iommus = <&apps_smmu 0x1004 0x0>; 911 }; 912 913 compute-cb@5 { 914 compatible = "qcom,fastrpc-compute-cb"; 915 reg = <5>; 916 iommus = <&apps_smmu 0x1005 0x0>; 917 qcom,nsessions = <5>; 918 }; 919 }; 920 }; 921 }; 922 923 mpss: remoteproc@4080000 { 924 compatible = "qcom,sm6350-mpss-pas"; 925 reg = <0x0 0x04080000 0x0 0x4040>; 926 927 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 928 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 929 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 930 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 931 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 932 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 933 interrupt-names = "wdog", "fatal", "ready", "handover", 934 "stop-ack", "shutdown-ack"; 935 936 clocks = <&rpmhcc RPMH_CXO_CLK>; 937 clock-names = "xo"; 938 939 power-domains = <&rpmhpd SM6350_CX>, 940 <&rpmhpd SM6350_MSS>; 941 power-domain-names = "cx", "mss"; 942 943 memory-region = <&pil_modem_mem>; 944 945 qcom,qmp = <&aoss_qmp>; 946 947 qcom,smem-states = <&modem_smp2p_out 0>; 948 qcom,smem-state-names = "stop"; 949 950 status = "disabled"; 951 952 glink-edge { 953 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 954 IPCC_MPROC_SIGNAL_GLINK_QMP 955 IRQ_TYPE_EDGE_RISING>; 956 mboxes = <&ipcc IPCC_CLIENT_MPSS 957 IPCC_MPROC_SIGNAL_GLINK_QMP>; 958 label = "modem"; 959 qcom,remote-pid = <1>; 960 }; 961 }; 962 963 cdsp: remoteproc@8300000 { 964 compatible = "qcom,sm6350-cdsp-pas"; 965 reg = <0 0x08300000 0 0x10000>; 966 967 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 968 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 969 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 970 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 971 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 972 interrupt-names = "wdog", "fatal", "ready", 973 "handover", "stop-ack"; 974 975 clocks = <&rpmhcc RPMH_CXO_CLK>; 976 clock-names = "xo"; 977 978 power-domains = <&rpmhpd SM6350_CX>, 979 <&rpmhpd SM6350_MX>; 980 power-domain-names = "cx", "mx"; 981 982 memory-region = <&pil_cdsp_mem>; 983 984 qcom,qmp = <&aoss_qmp>; 985 986 qcom,smem-states = <&smp2p_cdsp_out 0>; 987 qcom,smem-state-names = "stop"; 988 989 status = "disabled"; 990 991 glink-edge { 992 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 993 IPCC_MPROC_SIGNAL_GLINK_QMP 994 IRQ_TYPE_EDGE_RISING>; 995 mboxes = <&ipcc IPCC_CLIENT_CDSP 996 IPCC_MPROC_SIGNAL_GLINK_QMP>; 997 998 label = "cdsp"; 999 qcom,remote-pid = <5>; 1000 1001 fastrpc { 1002 compatible = "qcom,fastrpc"; 1003 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1004 label = "cdsp"; 1005 #address-cells = <1>; 1006 #size-cells = <0>; 1007 1008 compute-cb@1 { 1009 compatible = "qcom,fastrpc-compute-cb"; 1010 reg = <1>; 1011 iommus = <&apps_smmu 0x1401 0x20>; 1012 }; 1013 1014 compute-cb@2 { 1015 compatible = "qcom,fastrpc-compute-cb"; 1016 reg = <2>; 1017 iommus = <&apps_smmu 0x1402 0x20>; 1018 }; 1019 1020 compute-cb@3 { 1021 compatible = "qcom,fastrpc-compute-cb"; 1022 reg = <3>; 1023 iommus = <&apps_smmu 0x1403 0x20>; 1024 }; 1025 1026 compute-cb@4 { 1027 compatible = "qcom,fastrpc-compute-cb"; 1028 reg = <4>; 1029 iommus = <&apps_smmu 0x1404 0x20>; 1030 }; 1031 1032 compute-cb@5 { 1033 compatible = "qcom,fastrpc-compute-cb"; 1034 reg = <5>; 1035 iommus = <&apps_smmu 0x1405 0x20>; 1036 }; 1037 1038 compute-cb@6 { 1039 compatible = "qcom,fastrpc-compute-cb"; 1040 reg = <6>; 1041 iommus = <&apps_smmu 0x1406 0x20>; 1042 }; 1043 1044 compute-cb@7 { 1045 compatible = "qcom,fastrpc-compute-cb"; 1046 reg = <7>; 1047 iommus = <&apps_smmu 0x1407 0x20>; 1048 }; 1049 1050 compute-cb@8 { 1051 compatible = "qcom,fastrpc-compute-cb"; 1052 reg = <8>; 1053 iommus = <&apps_smmu 0x1408 0x20>; 1054 }; 1055 1056 /* note: secure cb9 in downstream */ 1057 }; 1058 }; 1059 }; 1060 1061 sdhc_2: mmc@8804000 { 1062 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 1063 reg = <0 0x08804000 0 0x1000>; 1064 1065 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1066 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1067 interrupt-names = "hc_irq", "pwr_irq"; 1068 iommus = <&apps_smmu 0x560 0x0>; 1069 1070 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1071 <&gcc GCC_SDCC2_APPS_CLK>, 1072 <&rpmhcc RPMH_CXO_CLK>; 1073 clock-names = "iface", "core", "xo"; 1074 resets = <&gcc GCC_SDCC2_BCR>; 1075 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>, 1076 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>; 1077 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 1078 1079 pinctrl-0 = <&sdc2_on_state>; 1080 pinctrl-1 = <&sdc2_off_state>; 1081 pinctrl-names = "default", "sleep"; 1082 1083 qcom,dll-config = <0x0007642c>; 1084 qcom,ddr-config = <0x80040868>; 1085 power-domains = <&rpmhpd SM6350_CX>; 1086 operating-points-v2 = <&sdhc2_opp_table>; 1087 bus-width = <4>; 1088 1089 status = "disabled"; 1090 1091 sdhc2_opp_table: opp-table { 1092 compatible = "operating-points-v2"; 1093 1094 opp-100000000 { 1095 opp-hz = /bits/ 64 <100000000>; 1096 required-opps = <&rpmhpd_opp_svs_l1>; 1097 opp-peak-kBps = <790000 131000>; 1098 opp-avg-kBps = <50000 50000>; 1099 }; 1100 1101 opp-202000000 { 1102 opp-hz = /bits/ 64 <202000000>; 1103 required-opps = <&rpmhpd_opp_nom>; 1104 opp-peak-kBps = <3190000 294000>; 1105 opp-avg-kBps = <261438 300000>; 1106 }; 1107 }; 1108 }; 1109 1110 usb_1_hsphy: phy@88e3000 { 1111 compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy"; 1112 reg = <0 0x088e3000 0 0x400>; 1113 status = "disabled"; 1114 #phy-cells = <0>; 1115 1116 clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>; 1117 clock-names = "cfg_ahb", "ref"; 1118 1119 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1120 }; 1121 1122 usb_1_qmpphy: phy@88e9000 { 1123 compatible = "qcom,sc7180-qmp-usb3-dp-phy"; 1124 reg = <0 0x088e9000 0 0x200>, 1125 <0 0x088e8000 0 0x40>, 1126 <0 0x088ea000 0 0x200>; 1127 status = "disabled"; 1128 #address-cells = <2>; 1129 #size-cells = <2>; 1130 ranges; 1131 1132 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1133 <&xo_board>, 1134 <&rpmhcc RPMH_QLINK_CLK>, 1135 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 1136 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 1137 1138 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 1139 <&gcc GCC_USB3_PHY_PRIM_BCR>; 1140 reset-names = "phy", "common"; 1141 1142 usb_1_ssphy: usb3-phy@88e9200 { 1143 reg = <0 0x088e9200 0 0x200>, 1144 <0 0x088e9400 0 0x200>, 1145 <0 0x088e9c00 0 0x400>, 1146 <0 0x088e9600 0 0x200>, 1147 <0 0x088e9800 0 0x200>, 1148 <0 0x088e9a00 0 0x100>; 1149 #clock-cells = <0>; 1150 #phy-cells = <0>; 1151 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1152 clock-names = "pipe0"; 1153 clock-output-names = "usb3_phy_pipe_clk_src"; 1154 }; 1155 1156 dp_phy: dp-phy@88ea200 { 1157 reg = <0 0x088ea200 0 0x200>, 1158 <0 0x088ea400 0 0x200>, 1159 <0 0x088eaa00 0 0x200>, 1160 <0 0x088ea600 0 0x200>, 1161 <0 0x088ea800 0 0x200>; 1162 #phy-cells = <0>; 1163 #clock-cells = <1>; 1164 }; 1165 }; 1166 1167 dc_noc: interconnect@9160000 { 1168 compatible = "qcom,sm6350-dc-noc"; 1169 reg = <0 0x09160000 0 0x3200>; 1170 #interconnect-cells = <2>; 1171 qcom,bcm-voters = <&apps_bcm_voter>; 1172 }; 1173 1174 system-cache-controller@9200000 { 1175 compatible = "qcom,sm6350-llcc"; 1176 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 1177 reg-names = "llcc_base", "llcc_broadcast_base"; 1178 }; 1179 1180 gem_noc: interconnect@9680000 { 1181 compatible = "qcom,sm6350-gem-noc"; 1182 reg = <0 0x09680000 0 0x3e200>; 1183 #interconnect-cells = <2>; 1184 qcom,bcm-voters = <&apps_bcm_voter>; 1185 }; 1186 1187 npu_noc: interconnect@9990000 { 1188 compatible = "qcom,sm6350-npu-noc"; 1189 reg = <0 0x09990000 0 0x1600>; 1190 #interconnect-cells = <2>; 1191 qcom,bcm-voters = <&apps_bcm_voter>; 1192 }; 1193 1194 usb_1: usb@a6f8800 { 1195 compatible = "qcom,sm6350-dwc3", "qcom,dwc3"; 1196 reg = <0 0x0a6f8800 0 0x400>; 1197 status = "disabled"; 1198 #address-cells = <2>; 1199 #size-cells = <2>; 1200 ranges; 1201 1202 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1203 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1204 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1205 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1206 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 1207 clock-names = "cfg_noc", 1208 "core", 1209 "iface", 1210 "sleep", 1211 "mock_utmi"; 1212 1213 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1214 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 1215 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1216 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 1217 1218 interrupt-names = "hs_phy_irq", "ss_phy_irq", 1219 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1220 1221 power-domains = <&gcc USB30_PRIM_GDSC>; 1222 1223 resets = <&gcc GCC_USB30_PRIM_BCR>; 1224 1225 interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>, 1226 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 1227 interconnect-names = "usb-ddr", "apps-usb"; 1228 1229 usb_1_dwc3: usb@a600000 { 1230 compatible = "snps,dwc3"; 1231 reg = <0 0x0a600000 0 0xcd00>; 1232 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1233 iommus = <&apps_smmu 0x540 0x0>; 1234 snps,dis_u2_susphy_quirk; 1235 snps,dis_enblslpm_quirk; 1236 snps,has-lpm-erratum; 1237 snps,hird-threshold = /bits/ 8 <0x10>; 1238 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 1239 phy-names = "usb2-phy", "usb3-phy"; 1240 }; 1241 }; 1242 1243 pdc: interrupt-controller@b220000 { 1244 compatible = "qcom,sm6350-pdc", "qcom,pdc"; 1245 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>; 1246 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 1247 <125 63 1>, <126 655 12>, <138 139 15>; 1248 #interrupt-cells = <2>; 1249 interrupt-parent = <&intc>; 1250 interrupt-controller; 1251 }; 1252 1253 tsens0: thermal-sensor@c263000 { 1254 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 1255 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 1256 <0 0x0c222000 0 0x8>; /* SROT */ 1257 #qcom,sensors = <16>; 1258 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 1259 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 1260 interrupt-names = "uplow", "critical"; 1261 #thermal-sensor-cells = <1>; 1262 }; 1263 1264 tsens1: thermal-sensor@c265000 { 1265 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 1266 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 1267 <0 0x0c223000 0 0x8>; /* SROT */ 1268 #qcom,sensors = <16>; 1269 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 1270 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 1271 interrupt-names = "uplow", "critical"; 1272 #thermal-sensor-cells = <1>; 1273 }; 1274 1275 aoss_qmp: power-controller@c300000 { 1276 compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp"; 1277 reg = <0 0x0c300000 0 0x1000>; 1278 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 1279 IRQ_TYPE_EDGE_RISING>; 1280 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 1281 1282 #clock-cells = <0>; 1283 }; 1284 1285 spmi_bus: spmi@c440000 { 1286 compatible = "qcom,spmi-pmic-arb"; 1287 reg = <0 0xc440000 0 0x1100>, 1288 <0 0xc600000 0 0x2000000>, 1289 <0 0xe600000 0 0x100000>, 1290 <0 0xe700000 0 0xa0000>, 1291 <0 0xc40a000 0 0x26000>; 1292 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1293 interrupt-names = "periph_irq"; 1294 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 1295 qcom,ee = <0>; 1296 qcom,channel = <0>; 1297 #address-cells = <2>; 1298 #size-cells = <0>; 1299 interrupt-controller; 1300 #interrupt-cells = <4>; 1301 }; 1302 1303 tlmm: pinctrl@f100000 { 1304 compatible = "qcom,sm6350-tlmm"; 1305 reg = <0 0x0f100000 0 0x300000>; 1306 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1307 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 1308 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 1309 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 1310 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1311 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 1312 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 1313 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 1314 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 1315 gpio-controller; 1316 #gpio-cells = <2>; 1317 interrupt-controller; 1318 #interrupt-cells = <2>; 1319 gpio-ranges = <&tlmm 0 0 157>; 1320 1321 sdc2_off_state: sdc2-off-state { 1322 clk-pins { 1323 pins = "sdc2_clk"; 1324 drive-strength = <2>; 1325 bias-disable; 1326 }; 1327 1328 cmd-pins { 1329 pins = "sdc2_cmd"; 1330 drive-strength = <2>; 1331 bias-pull-up; 1332 }; 1333 1334 data-pins { 1335 pins = "sdc2_data"; 1336 drive-strength = <2>; 1337 bias-pull-up; 1338 }; 1339 }; 1340 1341 sdc2_on_state: sdc2-on-state { 1342 clk-pins { 1343 pins = "sdc2_clk"; 1344 drive-strength = <16>; 1345 bias-disable; 1346 }; 1347 1348 cmd-pins { 1349 pins = "sdc2_cmd"; 1350 drive-strength = <10>; 1351 bias-pull-up; 1352 }; 1353 1354 data-pins { 1355 pins = "sdc2_data"; 1356 drive-strength = <10>; 1357 bias-pull-up; 1358 }; 1359 }; 1360 1361 qup_uart9_default: qup-uart9-default-state { 1362 pins = "gpio25", "gpio26"; 1363 function = "qup13_f2"; 1364 drive-strength = <2>; 1365 bias-disable; 1366 }; 1367 1368 qup_i2c0_default: qup-i2c0-default-state { 1369 pins = "gpio0", "gpio1"; 1370 function = "qup00"; 1371 drive-strength = <2>; 1372 bias-pull-up; 1373 }; 1374 1375 qup_i2c2_default: qup-i2c2-default-state { 1376 pins = "gpio45", "gpio46"; 1377 function = "qup02"; 1378 drive-strength = <2>; 1379 bias-pull-up; 1380 }; 1381 1382 qup_i2c6_default: qup-i2c6-default-state { 1383 pins = "gpio13", "gpio14"; 1384 function = "qup10"; 1385 drive-strength = <2>; 1386 bias-pull-up; 1387 }; 1388 1389 qup_i2c7_default: qup-i2c7-default-state { 1390 pins = "gpio27", "gpio28"; 1391 function = "qup11"; 1392 drive-strength = <2>; 1393 bias-pull-up; 1394 }; 1395 1396 qup_i2c8_default: qup-i2c8-default-state { 1397 pins = "gpio19", "gpio20"; 1398 function = "qup12"; 1399 drive-strength = <2>; 1400 bias-pull-up; 1401 }; 1402 1403 qup_i2c10_default: qup-i2c10-default-state { 1404 pins = "gpio4", "gpio5"; 1405 function = "qup14"; 1406 drive-strength = <2>; 1407 bias-pull-up; 1408 }; 1409 }; 1410 1411 apps_smmu: iommu@15000000 { 1412 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500"; 1413 reg = <0 0x15000000 0 0x100000>; 1414 #iommu-cells = <2>; 1415 #global-interrupts = <1>; 1416 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1417 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1418 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1419 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1420 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1421 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1422 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1423 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1424 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1426 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1427 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1428 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1429 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1430 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1431 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1432 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1433 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1434 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1435 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1436 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1437 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1438 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1439 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1440 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1441 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1442 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1443 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1444 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1461 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1464 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1465 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1466 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1471 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1473 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1476 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 1490 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 1491 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 1492 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 1493 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 1494 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 1495 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 1496 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 1497 }; 1498 1499 intc: interrupt-controller@17a00000 { 1500 compatible = "arm,gic-v3"; 1501 #interrupt-cells = <3>; 1502 interrupt-controller; 1503 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 1504 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 1505 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; 1506 }; 1507 1508 watchdog@17c10000 { 1509 compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt"; 1510 reg = <0 0x17c10000 0 0x1000>; 1511 clocks = <&sleep_clk>; 1512 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 1513 }; 1514 1515 timer@17c20000 { 1516 compatible = "arm,armv7-timer-mem"; 1517 reg = <0x0 0x17c20000 0x0 0x1000>; 1518 clock-frequency = <19200000>; 1519 #address-cells = <1>; 1520 #size-cells = <1>; 1521 ranges = <0 0 0 0x20000000>; 1522 1523 frame@17c21000 { 1524 frame-number = <0>; 1525 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1527 reg = <0x17c21000 0x1000>, 1528 <0x17c22000 0x1000>; 1529 }; 1530 1531 frame@17c23000 { 1532 frame-number = <1>; 1533 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1534 reg = <0x17c23000 0x1000>; 1535 status = "disabled"; 1536 }; 1537 1538 frame@17c25000 { 1539 frame-number = <2>; 1540 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1541 reg = <0x17c25000 0x1000>; 1542 status = "disabled"; 1543 }; 1544 1545 frame@17c27000 { 1546 frame-number = <3>; 1547 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1548 reg = <0x17c27000 0x1000>; 1549 status = "disabled"; 1550 }; 1551 1552 frame@17c29000 { 1553 frame-number = <4>; 1554 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1555 reg = <0x17c29000 0x1000>; 1556 status = "disabled"; 1557 }; 1558 1559 frame@17c2b000 { 1560 frame-number = <5>; 1561 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1562 reg = <0x17c2b000 0x1000>; 1563 status = "disabled"; 1564 }; 1565 1566 frame@17c2d000 { 1567 frame-number = <6>; 1568 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1569 reg = <0x17c2d000 0x1000>; 1570 status = "disabled"; 1571 }; 1572 }; 1573 1574 wifi: wifi@18800000 { 1575 compatible = "qcom,wcn3990-wifi"; 1576 reg = <0 0x18800000 0 0x800000>; 1577 reg-names = "membase"; 1578 memory-region = <&wlan_fw_mem>; 1579 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 1580 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 1581 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 1582 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 1583 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 1584 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 1585 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 1586 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 1587 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 1588 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 1589 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 1590 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 1591 iommus = <&apps_smmu 0x20 0x1>; 1592 qcom,msa-fixed-perm; 1593 status = "disabled"; 1594 }; 1595 1596 apps_rsc: rsc@18200000 { 1597 compatible = "qcom,rpmh-rsc"; 1598 label = "apps_rsc"; 1599 reg = <0x0 0x18200000 0x0 0x10000>, 1600 <0x0 0x18210000 0x0 0x10000>, 1601 <0x0 0x18220000 0x0 0x10000>; 1602 reg-names = "drv-0", "drv-1", "drv-2"; 1603 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1604 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1605 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1606 qcom,tcs-offset = <0xd00>; 1607 qcom,drv-id = <2>; 1608 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 1609 <WAKE_TCS 3>, <CONTROL_TCS 1>; 1610 1611 rpmhcc: clock-controller { 1612 compatible = "qcom,sm6350-rpmh-clk"; 1613 #clock-cells = <1>; 1614 clock-names = "xo"; 1615 clocks = <&xo_board>; 1616 }; 1617 1618 rpmhpd: power-controller { 1619 compatible = "qcom,sm6350-rpmhpd"; 1620 #power-domain-cells = <1>; 1621 operating-points-v2 = <&rpmhpd_opp_table>; 1622 1623 rpmhpd_opp_table: opp-table { 1624 compatible = "operating-points-v2"; 1625 1626 rpmhpd_opp_ret: opp1 { 1627 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1628 }; 1629 1630 rpmhpd_opp_min_svs: opp2 { 1631 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1632 }; 1633 1634 rpmhpd_opp_low_svs: opp3 { 1635 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1636 }; 1637 1638 rpmhpd_opp_svs: opp4 { 1639 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1640 }; 1641 1642 rpmhpd_opp_svs_l1: opp5 { 1643 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1644 }; 1645 1646 rpmhpd_opp_nom: opp6 { 1647 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1648 }; 1649 1650 rpmhpd_opp_nom_l1: opp7 { 1651 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1652 }; 1653 1654 rpmhpd_opp_nom_l2: opp8 { 1655 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 1656 }; 1657 1658 rpmhpd_opp_turbo: opp9 { 1659 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1660 }; 1661 1662 rpmhpd_opp_turbo_l1: opp10 { 1663 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1664 }; 1665 }; 1666 }; 1667 1668 apps_bcm_voter: bcm-voter { 1669 compatible = "qcom,bcm-voter"; 1670 }; 1671 }; 1672 1673 cpufreq_hw: cpufreq@18323000 { 1674 compatible = "qcom,cpufreq-hw"; 1675 reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>; 1676 reg-names = "freq-domain0", "freq-domain1"; 1677 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 1678 clock-names = "xo", "alternate"; 1679 1680 #freq-domain-cells = <1>; 1681 }; 1682 }; 1683 1684 timer { 1685 compatible = "arm,armv8-timer"; 1686 clock-frequency = <19200000>; 1687 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1688 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1689 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1690 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1691 }; 1692}; 1693