1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> 4 * Copyright (c) 2022, Luca Weiss <luca.weiss@fairphone.com> 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sm6350.h> 8#include <dt-bindings/clock/qcom,gcc-sm6350.h> 9#include <dt-bindings/clock/qcom,gpucc-sm6350.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sm6350-camcc.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interconnect/qcom,icc.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,sm6350.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/mailbox/qcom-ipcc.h> 19#include <dt-bindings/phy/phy-qcom-qmp.h> 20#include <dt-bindings/power/qcom-rpmpd.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 clocks { 29 xo_board: xo-board { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <76800000>; 33 clock-output-names = "xo_board"; 34 }; 35 36 sleep_clk: sleep-clk { 37 compatible = "fixed-clock"; 38 clock-frequency = <32764>; 39 #clock-cells = <0>; 40 }; 41 }; 42 43 cpus { 44 #address-cells = <2>; 45 #size-cells = <0>; 46 47 CPU0: cpu@0 { 48 device_type = "cpu"; 49 compatible = "qcom,kryo560"; 50 reg = <0x0 0x0>; 51 clocks = <&cpufreq_hw 0>; 52 enable-method = "psci"; 53 capacity-dmips-mhz = <1024>; 54 dynamic-power-coefficient = <100>; 55 next-level-cache = <&L2_0>; 56 qcom,freq-domain = <&cpufreq_hw 0>; 57 operating-points-v2 = <&cpu0_opp_table>; 58 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 59 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 60 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 61 power-domains = <&CPU_PD0>; 62 power-domain-names = "psci"; 63 #cooling-cells = <2>; 64 L2_0: l2-cache { 65 compatible = "cache"; 66 cache-level = <2>; 67 cache-unified; 68 next-level-cache = <&L3_0>; 69 L3_0: l3-cache { 70 compatible = "cache"; 71 cache-level = <3>; 72 cache-unified; 73 }; 74 }; 75 }; 76 77 CPU1: cpu@100 { 78 device_type = "cpu"; 79 compatible = "qcom,kryo560"; 80 reg = <0x0 0x100>; 81 clocks = <&cpufreq_hw 0>; 82 enable-method = "psci"; 83 capacity-dmips-mhz = <1024>; 84 dynamic-power-coefficient = <100>; 85 next-level-cache = <&L2_100>; 86 qcom,freq-domain = <&cpufreq_hw 0>; 87 operating-points-v2 = <&cpu0_opp_table>; 88 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 89 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 90 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 91 power-domains = <&CPU_PD1>; 92 power-domain-names = "psci"; 93 #cooling-cells = <2>; 94 L2_100: l2-cache { 95 compatible = "cache"; 96 cache-level = <2>; 97 cache-unified; 98 next-level-cache = <&L3_0>; 99 }; 100 }; 101 102 CPU2: cpu@200 { 103 device_type = "cpu"; 104 compatible = "qcom,kryo560"; 105 reg = <0x0 0x200>; 106 clocks = <&cpufreq_hw 0>; 107 enable-method = "psci"; 108 capacity-dmips-mhz = <1024>; 109 dynamic-power-coefficient = <100>; 110 next-level-cache = <&L2_200>; 111 qcom,freq-domain = <&cpufreq_hw 0>; 112 operating-points-v2 = <&cpu0_opp_table>; 113 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 114 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 115 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 116 power-domains = <&CPU_PD2>; 117 power-domain-names = "psci"; 118 #cooling-cells = <2>; 119 L2_200: l2-cache { 120 compatible = "cache"; 121 cache-level = <2>; 122 cache-unified; 123 next-level-cache = <&L3_0>; 124 }; 125 }; 126 127 CPU3: cpu@300 { 128 device_type = "cpu"; 129 compatible = "qcom,kryo560"; 130 reg = <0x0 0x300>; 131 clocks = <&cpufreq_hw 0>; 132 enable-method = "psci"; 133 capacity-dmips-mhz = <1024>; 134 dynamic-power-coefficient = <100>; 135 next-level-cache = <&L2_300>; 136 qcom,freq-domain = <&cpufreq_hw 0>; 137 operating-points-v2 = <&cpu0_opp_table>; 138 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 139 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 140 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 141 power-domains = <&CPU_PD3>; 142 power-domain-names = "psci"; 143 #cooling-cells = <2>; 144 L2_300: l2-cache { 145 compatible = "cache"; 146 cache-level = <2>; 147 cache-unified; 148 next-level-cache = <&L3_0>; 149 }; 150 }; 151 152 CPU4: cpu@400 { 153 device_type = "cpu"; 154 compatible = "qcom,kryo560"; 155 reg = <0x0 0x400>; 156 clocks = <&cpufreq_hw 0>; 157 enable-method = "psci"; 158 capacity-dmips-mhz = <1024>; 159 dynamic-power-coefficient = <100>; 160 next-level-cache = <&L2_400>; 161 qcom,freq-domain = <&cpufreq_hw 0>; 162 operating-points-v2 = <&cpu0_opp_table>; 163 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 164 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 165 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 166 power-domains = <&CPU_PD4>; 167 power-domain-names = "psci"; 168 #cooling-cells = <2>; 169 L2_400: l2-cache { 170 compatible = "cache"; 171 cache-level = <2>; 172 cache-unified; 173 next-level-cache = <&L3_0>; 174 }; 175 }; 176 177 CPU5: cpu@500 { 178 device_type = "cpu"; 179 compatible = "qcom,kryo560"; 180 reg = <0x0 0x500>; 181 clocks = <&cpufreq_hw 0>; 182 enable-method = "psci"; 183 capacity-dmips-mhz = <1024>; 184 dynamic-power-coefficient = <100>; 185 next-level-cache = <&L2_500>; 186 qcom,freq-domain = <&cpufreq_hw 0>; 187 operating-points-v2 = <&cpu0_opp_table>; 188 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 189 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 190 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 191 power-domains = <&CPU_PD5>; 192 power-domain-names = "psci"; 193 #cooling-cells = <2>; 194 L2_500: l2-cache { 195 compatible = "cache"; 196 cache-level = <2>; 197 cache-unified; 198 next-level-cache = <&L3_0>; 199 }; 200 }; 201 202 CPU6: cpu@600 { 203 device_type = "cpu"; 204 compatible = "qcom,kryo560"; 205 reg = <0x0 0x600>; 206 clocks = <&cpufreq_hw 1>; 207 enable-method = "psci"; 208 capacity-dmips-mhz = <1894>; 209 dynamic-power-coefficient = <703>; 210 next-level-cache = <&L2_600>; 211 qcom,freq-domain = <&cpufreq_hw 1>; 212 operating-points-v2 = <&cpu6_opp_table>; 213 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 214 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 215 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 216 power-domains = <&CPU_PD6>; 217 power-domain-names = "psci"; 218 #cooling-cells = <2>; 219 L2_600: l2-cache { 220 compatible = "cache"; 221 cache-level = <2>; 222 cache-unified; 223 next-level-cache = <&L3_0>; 224 }; 225 }; 226 227 CPU7: cpu@700 { 228 device_type = "cpu"; 229 compatible = "qcom,kryo560"; 230 reg = <0x0 0x700>; 231 clocks = <&cpufreq_hw 1>; 232 enable-method = "psci"; 233 capacity-dmips-mhz = <1894>; 234 dynamic-power-coefficient = <703>; 235 next-level-cache = <&L2_700>; 236 qcom,freq-domain = <&cpufreq_hw 1>; 237 operating-points-v2 = <&cpu6_opp_table>; 238 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 239 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>, 240 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 241 power-domains = <&CPU_PD7>; 242 power-domain-names = "psci"; 243 #cooling-cells = <2>; 244 L2_700: l2-cache { 245 compatible = "cache"; 246 cache-level = <2>; 247 cache-unified; 248 next-level-cache = <&L3_0>; 249 }; 250 }; 251 252 cpu-map { 253 cluster0 { 254 core0 { 255 cpu = <&CPU0>; 256 }; 257 258 core1 { 259 cpu = <&CPU1>; 260 }; 261 262 core2 { 263 cpu = <&CPU2>; 264 }; 265 266 core3 { 267 cpu = <&CPU3>; 268 }; 269 270 core4 { 271 cpu = <&CPU4>; 272 }; 273 274 core5 { 275 cpu = <&CPU5>; 276 }; 277 278 core6 { 279 cpu = <&CPU6>; 280 }; 281 282 core7 { 283 cpu = <&CPU7>; 284 }; 285 }; 286 }; 287 288 domain-idle-states { 289 CLUSTER_SLEEP_PC: cluster-sleep-0 { 290 compatible = "domain-idle-state"; 291 arm,psci-suspend-param = <0x41000044>; 292 entry-latency-us = <2752>; 293 exit-latency-us = <3048>; 294 min-residency-us = <6118>; 295 }; 296 297 CLUSTER_SLEEP_CX_RET: cluster-sleep-1 { 298 compatible = "domain-idle-state"; 299 arm,psci-suspend-param = <0x41001244>; 300 entry-latency-us = <3638>; 301 exit-latency-us = <4562>; 302 min-residency-us = <8467>; 303 }; 304 305 CLUSTER_AOSS_SLEEP: cluster-sleep-2 { 306 compatible = "domain-idle-state"; 307 arm,psci-suspend-param = <0x4100b244>; 308 entry-latency-us = <3263>; 309 exit-latency-us = <6562>; 310 min-residency-us = <9987>; 311 }; 312 }; 313 314 cpu_idle_states: idle-states { 315 entry-method = "psci"; 316 317 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 318 compatible = "arm,idle-state"; 319 idle-state-name = "little-power-collapse"; 320 arm,psci-suspend-param = <0x40000003>; 321 entry-latency-us = <549>; 322 exit-latency-us = <901>; 323 min-residency-us = <1774>; 324 local-timer-stop; 325 }; 326 327 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 328 compatible = "arm,idle-state"; 329 idle-state-name = "little-rail-power-collapse"; 330 arm,psci-suspend-param = <0x40000004>; 331 entry-latency-us = <702>; 332 exit-latency-us = <915>; 333 min-residency-us = <4001>; 334 local-timer-stop; 335 }; 336 337 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 338 compatible = "arm,idle-state"; 339 idle-state-name = "big-power-collapse"; 340 arm,psci-suspend-param = <0x40000003>; 341 entry-latency-us = <523>; 342 exit-latency-us = <1244>; 343 min-residency-us = <2207>; 344 local-timer-stop; 345 }; 346 347 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 348 compatible = "arm,idle-state"; 349 idle-state-name = "big-rail-power-collapse"; 350 arm,psci-suspend-param = <0x40000004>; 351 entry-latency-us = <526>; 352 exit-latency-us = <1854>; 353 min-residency-us = <5555>; 354 local-timer-stop; 355 }; 356 }; 357 }; 358 359 firmware { 360 scm: scm { 361 compatible = "qcom,scm-sm6350", "qcom,scm"; 362 #reset-cells = <1>; 363 }; 364 }; 365 366 memory@80000000 { 367 device_type = "memory"; 368 /* We expect the bootloader to fill in the size */ 369 reg = <0x0 0x80000000 0x0 0x0>; 370 }; 371 372 cpu0_opp_table: opp-table-cpu0 { 373 compatible = "operating-points-v2"; 374 opp-shared; 375 376 opp-300000000 { 377 opp-hz = /bits/ 64 <300000000>; 378 /* DDR: 4-wide, 2 channels, double data rate, L3: 16-wide, 2 channels */ 379 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; 380 }; 381 382 opp-576000000 { 383 opp-hz = /bits/ 64 <576000000>; 384 opp-peak-kBps = <(547000 * 4 * 2 * 2) (556800 * 16 * 2)>; 385 }; 386 387 opp-768000000 { 388 opp-hz = /bits/ 64 <768000000>; 389 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; 390 }; 391 392 opp-1017600000 { 393 opp-hz = /bits/ 64 <1017600000>; 394 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; 395 }; 396 397 opp-1248000000 { 398 opp-hz = /bits/ 64 <1248000000>; 399 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; 400 }; 401 402 opp-1324800000 { 403 opp-hz = /bits/ 64 <1324800000>; 404 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1286400 * 16 * 2)>; 405 }; 406 407 opp-1516800000 { 408 opp-hz = /bits/ 64 <1516800000>; 409 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 410 }; 411 412 opp-1612800000 { 413 opp-hz = /bits/ 64 <1612800000>; 414 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 415 }; 416 417 opp-1708800000 { 418 opp-hz = /bits/ 64 <1708800000>; 419 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 420 }; 421 }; 422 423 cpu6_opp_table: opp-table-cpu6 { 424 compatible = "operating-points-v2"; 425 opp-shared; 426 427 opp-300000000 { 428 opp-hz = /bits/ 64 <300000000>; 429 opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>; 430 }; 431 432 opp-787200000 { 433 opp-hz = /bits/ 64 <787200000>; 434 opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>; 435 }; 436 437 opp-979200000 { 438 opp-hz = /bits/ 64 <979200000>; 439 opp-peak-kBps = <(768000 * 4 * 2 * 2) (940800 * 16 * 2)>; 440 }; 441 442 opp-1036800000 { 443 opp-hz = /bits/ 64 <1036800000>; 444 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>; 445 }; 446 447 opp-1248000000 { 448 opp-hz = /bits/ 64 <1248000000>; 449 opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>; 450 }; 451 452 opp-1401600000 { 453 opp-hz = /bits/ 64 <1401600000>; 454 opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1401600 * 16 * 2)>; 455 }; 456 457 opp-1555200000 { 458 opp-hz = /bits/ 64 <1555200000>; 459 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 460 }; 461 462 opp-1766400000 { 463 opp-hz = /bits/ 64 <1766400000>; 464 opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 465 }; 466 467 opp-1900800000 { 468 opp-hz = /bits/ 64 <1900800000>; 469 opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 470 }; 471 472 opp-2073600000 { 473 opp-hz = /bits/ 64 <2073600000>; 474 opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>; 475 }; 476 }; 477 478 qup_opp_table: opp-table-qup { 479 compatible = "operating-points-v2"; 480 481 opp-75000000 { 482 opp-hz = /bits/ 64 <75000000>; 483 required-opps = <&rpmhpd_opp_low_svs>; 484 }; 485 486 opp-100000000 { 487 opp-hz = /bits/ 64 <100000000>; 488 required-opps = <&rpmhpd_opp_svs>; 489 }; 490 491 opp-128000000 { 492 opp-hz = /bits/ 64 <128000000>; 493 required-opps = <&rpmhpd_opp_nom>; 494 }; 495 }; 496 497 pmu { 498 compatible = "arm,armv8-pmuv3"; 499 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>; 500 }; 501 502 psci { 503 compatible = "arm,psci-1.0"; 504 method = "smc"; 505 506 CPU_PD0: power-domain-cpu0 { 507 #power-domain-cells = <0>; 508 power-domains = <&CLUSTER_PD>; 509 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 510 }; 511 512 CPU_PD1: power-domain-cpu1 { 513 #power-domain-cells = <0>; 514 power-domains = <&CLUSTER_PD>; 515 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 516 }; 517 518 CPU_PD2: power-domain-cpu2 { 519 #power-domain-cells = <0>; 520 power-domains = <&CLUSTER_PD>; 521 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 522 }; 523 524 CPU_PD3: power-domain-cpu3 { 525 #power-domain-cells = <0>; 526 power-domains = <&CLUSTER_PD>; 527 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 528 }; 529 530 CPU_PD4: power-domain-cpu4 { 531 #power-domain-cells = <0>; 532 power-domains = <&CLUSTER_PD>; 533 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 534 }; 535 536 CPU_PD5: power-domain-cpu5 { 537 #power-domain-cells = <0>; 538 power-domains = <&CLUSTER_PD>; 539 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 540 }; 541 542 CPU_PD6: power-domain-cpu6 { 543 #power-domain-cells = <0>; 544 power-domains = <&CLUSTER_PD>; 545 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 546 }; 547 548 CPU_PD7: power-domain-cpu7 { 549 #power-domain-cells = <0>; 550 power-domains = <&CLUSTER_PD>; 551 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 552 }; 553 554 CLUSTER_PD: power-domain-cpu-cluster0 { 555 #power-domain-cells = <0>; 556 domain-idle-states = <&CLUSTER_SLEEP_PC 557 &CLUSTER_SLEEP_CX_RET 558 &CLUSTER_AOSS_SLEEP>; 559 }; 560 }; 561 562 reserved_memory: reserved-memory { 563 #address-cells = <2>; 564 #size-cells = <2>; 565 ranges; 566 567 hyp_mem: memory@80000000 { 568 reg = <0 0x80000000 0 0x600000>; 569 no-map; 570 }; 571 572 xbl_aop_mem: memory@80700000 { 573 reg = <0 0x80700000 0 0x160000>; 574 no-map; 575 }; 576 577 cmd_db: memory@80860000 { 578 compatible = "qcom,cmd-db"; 579 reg = <0 0x80860000 0 0x20000>; 580 no-map; 581 }; 582 583 sec_apps_mem: memory@808ff000 { 584 reg = <0 0x808ff000 0 0x1000>; 585 no-map; 586 }; 587 588 smem_mem: memory@80900000 { 589 reg = <0 0x80900000 0 0x200000>; 590 no-map; 591 }; 592 593 cdsp_sec_mem: memory@80b00000 { 594 reg = <0 0x80b00000 0 0x1e00000>; 595 no-map; 596 }; 597 598 pil_camera_mem: memory@86000000 { 599 reg = <0 0x86000000 0 0x500000>; 600 no-map; 601 }; 602 603 pil_npu_mem: memory@86500000 { 604 reg = <0 0x86500000 0 0x500000>; 605 no-map; 606 }; 607 608 pil_video_mem: memory@86a00000 { 609 reg = <0 0x86a00000 0 0x500000>; 610 no-map; 611 }; 612 613 pil_cdsp_mem: memory@86f00000 { 614 reg = <0 0x86f00000 0 0x1e00000>; 615 no-map; 616 }; 617 618 pil_adsp_mem: memory@88d00000 { 619 reg = <0 0x88d00000 0 0x2800000>; 620 no-map; 621 }; 622 623 wlan_fw_mem: memory@8b500000 { 624 reg = <0 0x8b500000 0 0x200000>; 625 no-map; 626 }; 627 628 pil_ipa_fw_mem: memory@8b700000 { 629 reg = <0 0x8b700000 0 0x10000>; 630 no-map; 631 }; 632 633 pil_ipa_gsi_mem: memory@8b710000 { 634 reg = <0 0x8b710000 0 0x5400>; 635 no-map; 636 }; 637 638 pil_modem_mem: memory@8b800000 { 639 reg = <0 0x8b800000 0 0xf800000>; 640 no-map; 641 }; 642 643 cont_splash_memory: memory@a0000000 { 644 reg = <0 0xa0000000 0 0x2300000>; 645 no-map; 646 }; 647 648 dfps_data_memory: memory@a2300000 { 649 reg = <0 0xa2300000 0 0x100000>; 650 no-map; 651 }; 652 653 removed_region: memory@c0000000 { 654 reg = <0 0xc0000000 0 0x3900000>; 655 no-map; 656 }; 657 658 pil_gpu_mem: memory@f0d00000 { 659 reg = <0 0xf0d00000 0 0x1000>; 660 no-map; 661 }; 662 663 debug_region: memory@ffb00000 { 664 reg = <0 0xffb00000 0 0xc0000>; 665 no-map; 666 }; 667 668 last_log_region: memory@ffbc0000 { 669 reg = <0 0xffbc0000 0 0x40000>; 670 no-map; 671 }; 672 673 ramoops: ramoops@ffc00000 { 674 compatible = "ramoops"; 675 reg = <0 0xffc00000 0 0x100000>; 676 record-size = <0x1000>; 677 console-size = <0x40000>; 678 pmsg-size = <0x20000>; 679 ecc-size = <16>; 680 no-map; 681 }; 682 683 cmdline_region: memory@ffd00000 { 684 reg = <0 0xffd00000 0 0x1000>; 685 no-map; 686 }; 687 }; 688 689 smem { 690 compatible = "qcom,smem"; 691 memory-region = <&smem_mem>; 692 hwlocks = <&tcsr_mutex 3>; 693 }; 694 695 smp2p-adsp { 696 compatible = "qcom,smp2p"; 697 qcom,smem = <443>, <429>; 698 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 699 IPCC_MPROC_SIGNAL_SMP2P 700 IRQ_TYPE_EDGE_RISING>; 701 mboxes = <&ipcc IPCC_CLIENT_LPASS 702 IPCC_MPROC_SIGNAL_SMP2P>; 703 704 qcom,local-pid = <0>; 705 qcom,remote-pid = <2>; 706 707 smp2p_adsp_out: master-kernel { 708 qcom,entry-name = "master-kernel"; 709 #qcom,smem-state-cells = <1>; 710 }; 711 712 smp2p_adsp_in: slave-kernel { 713 qcom,entry-name = "slave-kernel"; 714 interrupt-controller; 715 #interrupt-cells = <2>; 716 }; 717 }; 718 719 smp2p-cdsp { 720 compatible = "qcom,smp2p"; 721 qcom,smem = <94>, <432>; 722 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 723 IPCC_MPROC_SIGNAL_SMP2P 724 IRQ_TYPE_EDGE_RISING>; 725 mboxes = <&ipcc IPCC_CLIENT_CDSP 726 IPCC_MPROC_SIGNAL_SMP2P>; 727 728 qcom,local-pid = <0>; 729 qcom,remote-pid = <5>; 730 731 smp2p_cdsp_out: master-kernel { 732 qcom,entry-name = "master-kernel"; 733 #qcom,smem-state-cells = <1>; 734 }; 735 736 smp2p_cdsp_in: slave-kernel { 737 qcom,entry-name = "slave-kernel"; 738 interrupt-controller; 739 #interrupt-cells = <2>; 740 }; 741 }; 742 743 smp2p-mpss { 744 compatible = "qcom,smp2p"; 745 qcom,smem = <435>, <428>; 746 747 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 748 IPCC_MPROC_SIGNAL_SMP2P 749 IRQ_TYPE_EDGE_RISING>; 750 mboxes = <&ipcc IPCC_CLIENT_MPSS 751 IPCC_MPROC_SIGNAL_SMP2P>; 752 753 qcom,local-pid = <0>; 754 qcom,remote-pid = <1>; 755 756 modem_smp2p_out: master-kernel { 757 qcom,entry-name = "master-kernel"; 758 #qcom,smem-state-cells = <1>; 759 }; 760 761 modem_smp2p_in: slave-kernel { 762 qcom,entry-name = "slave-kernel"; 763 interrupt-controller; 764 #interrupt-cells = <2>; 765 }; 766 767 ipa_smp2p_out: ipa-ap-to-modem { 768 qcom,entry-name = "ipa"; 769 #qcom,smem-state-cells = <1>; 770 }; 771 772 ipa_smp2p_in: ipa-modem-to-ap { 773 qcom,entry-name = "ipa"; 774 interrupt-controller; 775 #interrupt-cells = <2>; 776 }; 777 }; 778 779 soc: soc@0 { 780 #address-cells = <2>; 781 #size-cells = <2>; 782 ranges = <0 0 0 0 0x10 0>; 783 dma-ranges = <0 0 0 0 0x10 0>; 784 compatible = "simple-bus"; 785 786 gcc: clock-controller@100000 { 787 compatible = "qcom,gcc-sm6350"; 788 reg = <0 0x00100000 0 0x1f0000>; 789 #clock-cells = <1>; 790 #reset-cells = <1>; 791 #power-domain-cells = <1>; 792 clock-names = "bi_tcxo", 793 "bi_tcxo_ao", 794 "sleep_clk"; 795 clocks = <&rpmhcc RPMH_CXO_CLK>, 796 <&rpmhcc RPMH_CXO_CLK_A>, 797 <&sleep_clk>; 798 }; 799 800 ipcc: mailbox@408000 { 801 compatible = "qcom,sm6350-ipcc", "qcom,ipcc"; 802 reg = <0 0x00408000 0 0x1000>; 803 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 804 interrupt-controller; 805 #interrupt-cells = <3>; 806 #mbox-cells = <2>; 807 }; 808 809 qfprom: qfprom@784000 { 810 compatible = "qcom,sm6350-qfprom", "qcom,qfprom"; 811 reg = <0 0x00784000 0 0x3000>; 812 #address-cells = <1>; 813 #size-cells = <1>; 814 815 gpu_speed_bin: gpu-speed-bin@2015 { 816 reg = <0x2015 0x1>; 817 bits = <0 8>; 818 }; 819 }; 820 821 rng: rng@793000 { 822 compatible = "qcom,prng-ee"; 823 reg = <0 0x00793000 0 0x1000>; 824 clocks = <&gcc GCC_PRNG_AHB_CLK>; 825 clock-names = "core"; 826 }; 827 828 sdhc_1: mmc@7c4000 { 829 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 830 reg = <0 0x007c4000 0 0x1000>, 831 <0 0x007c5000 0 0x1000>, 832 <0 0x007c8000 0 0x8000>; 833 reg-names = "hc", "cqhci", "ice"; 834 835 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 837 interrupt-names = "hc_irq", "pwr_irq"; 838 iommus = <&apps_smmu 0x60 0x0>; 839 840 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 841 <&gcc GCC_SDCC1_APPS_CLK>, 842 <&rpmhcc RPMH_CXO_CLK>; 843 clock-names = "iface", "core", "xo"; 844 resets = <&gcc GCC_SDCC1_BCR>; 845 qcom,dll-config = <0x000f642c>; 846 qcom,ddr-config = <0x80040868>; 847 power-domains = <&rpmhpd SM6350_CX>; 848 operating-points-v2 = <&sdhc1_opp_table>; 849 bus-width = <8>; 850 non-removable; 851 supports-cqe; 852 853 status = "disabled"; 854 855 sdhc1_opp_table: opp-table { 856 compatible = "operating-points-v2"; 857 858 opp-19200000 { 859 opp-hz = /bits/ 64 <19200000>; 860 required-opps = <&rpmhpd_opp_min_svs>; 861 }; 862 863 opp-100000000 { 864 opp-hz = /bits/ 64 <100000000>; 865 required-opps = <&rpmhpd_opp_low_svs>; 866 }; 867 868 opp-384000000 { 869 opp-hz = /bits/ 64 <384000000>; 870 required-opps = <&rpmhpd_opp_svs_l1>; 871 }; 872 }; 873 }; 874 875 gpi_dma0: dma-controller@800000 { 876 compatible = "qcom,sm6350-gpi-dma"; 877 reg = <0 0x00800000 0 0x60000>; 878 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 879 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 880 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 888 dma-channels = <10>; 889 dma-channel-mask = <0x1f>; 890 iommus = <&apps_smmu 0x56 0x0>; 891 #dma-cells = <3>; 892 status = "disabled"; 893 }; 894 895 qupv3_id_0: geniqup@8c0000 { 896 compatible = "qcom,geni-se-qup"; 897 reg = <0x0 0x008c0000 0x0 0x2000>; 898 clock-names = "m-ahb", "s-ahb"; 899 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 900 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 901 #address-cells = <2>; 902 #size-cells = <2>; 903 iommus = <&apps_smmu 0x43 0x0>; 904 ranges; 905 status = "disabled"; 906 907 i2c0: i2c@880000 { 908 compatible = "qcom,geni-i2c"; 909 reg = <0 0x00880000 0 0x4000>; 910 clock-names = "se"; 911 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 912 pinctrl-names = "default"; 913 pinctrl-0 = <&qup_i2c0_default>; 914 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 915 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 916 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 917 dma-names = "tx", "rx"; 918 #address-cells = <1>; 919 #size-cells = <0>; 920 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 921 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 922 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 923 interconnect-names = "qup-core", "qup-config", "qup-memory"; 924 status = "disabled"; 925 }; 926 927 uart1: serial@884000 { 928 compatible = "qcom,geni-uart"; 929 reg = <0 0x00884000 0 0x4000>; 930 clock-names = "se"; 931 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 932 pinctrl-names = "default"; 933 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 934 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 935 power-domains = <&rpmhpd SM6350_CX>; 936 operating-points-v2 = <&qup_opp_table>; 937 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 938 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 939 interconnect-names = "qup-core", "qup-config"; 940 status = "disabled"; 941 }; 942 943 i2c2: i2c@888000 { 944 compatible = "qcom,geni-i2c"; 945 reg = <0 0x00888000 0 0x4000>; 946 clock-names = "se"; 947 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 948 pinctrl-names = "default"; 949 pinctrl-0 = <&qup_i2c2_default>; 950 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 951 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 952 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 953 dma-names = "tx", "rx"; 954 #address-cells = <1>; 955 #size-cells = <0>; 956 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 957 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 958 <&aggre1_noc MASTER_QUP_0 0 &clk_virt SLAVE_EBI_CH0 0>; 959 interconnect-names = "qup-core", "qup-config", "qup-memory"; 960 status = "disabled"; 961 }; 962 }; 963 964 gpi_dma1: dma-controller@900000 { 965 compatible = "qcom,sm6350-gpi-dma"; 966 reg = <0 0x00900000 0 0x60000>; 967 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 648 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 650 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 975 <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>, 976 <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>; 977 dma-channels = <10>; 978 dma-channel-mask = <0x3f>; 979 iommus = <&apps_smmu 0x4d6 0x0>; 980 #dma-cells = <3>; 981 status = "disabled"; 982 }; 983 984 qupv3_id_1: geniqup@9c0000 { 985 compatible = "qcom,geni-se-qup"; 986 reg = <0x0 0x009c0000 0x0 0x2000>; 987 clock-names = "m-ahb", "s-ahb"; 988 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 989 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 990 #address-cells = <2>; 991 #size-cells = <2>; 992 iommus = <&apps_smmu 0x4c3 0x0>; 993 ranges; 994 status = "disabled"; 995 996 i2c6: i2c@980000 { 997 compatible = "qcom,geni-i2c"; 998 reg = <0 0x00980000 0 0x4000>; 999 clock-names = "se"; 1000 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1001 pinctrl-names = "default"; 1002 pinctrl-0 = <&qup_i2c6_default>; 1003 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1004 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1005 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1006 dma-names = "tx", "rx"; 1007 #address-cells = <1>; 1008 #size-cells = <0>; 1009 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1010 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1011 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1012 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1013 status = "disabled"; 1014 }; 1015 1016 i2c7: i2c@984000 { 1017 compatible = "qcom,geni-i2c"; 1018 reg = <0 0x00984000 0 0x4000>; 1019 clock-names = "se"; 1020 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1021 pinctrl-names = "default"; 1022 pinctrl-0 = <&qup_i2c7_default>; 1023 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1024 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1025 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1026 dma-names = "tx", "rx"; 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1030 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1031 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1032 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1033 status = "disabled"; 1034 }; 1035 1036 i2c8: i2c@988000 { 1037 compatible = "qcom,geni-i2c"; 1038 reg = <0 0x00988000 0 0x4000>; 1039 clock-names = "se"; 1040 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1041 pinctrl-names = "default"; 1042 pinctrl-0 = <&qup_i2c8_default>; 1043 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1044 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1045 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1046 dma-names = "tx", "rx"; 1047 #address-cells = <1>; 1048 #size-cells = <0>; 1049 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1050 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1051 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1052 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1053 status = "disabled"; 1054 }; 1055 1056 uart9: serial@98c000 { 1057 compatible = "qcom,geni-debug-uart"; 1058 reg = <0 0x0098c000 0 0x4000>; 1059 clock-names = "se"; 1060 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1061 pinctrl-names = "default"; 1062 pinctrl-0 = <&qup_uart9_default>; 1063 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1064 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1065 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1066 interconnect-names = "qup-core", "qup-config"; 1067 status = "disabled"; 1068 }; 1069 1070 i2c10: i2c@990000 { 1071 compatible = "qcom,geni-i2c"; 1072 reg = <0 0x00990000 0 0x4000>; 1073 clock-names = "se"; 1074 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1075 pinctrl-names = "default"; 1076 pinctrl-0 = <&qup_i2c10_default>; 1077 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1078 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1079 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1080 dma-names = "tx", "rx"; 1081 #address-cells = <1>; 1082 #size-cells = <0>; 1083 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1084 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1085 <&aggre2_noc MASTER_QUP_1 0 &clk_virt SLAVE_EBI_CH0 0>; 1086 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1087 status = "disabled"; 1088 }; 1089 }; 1090 1091 config_noc: interconnect@1500000 { 1092 compatible = "qcom,sm6350-config-noc"; 1093 reg = <0 0x01500000 0 0x28000>; 1094 #interconnect-cells = <2>; 1095 qcom,bcm-voters = <&apps_bcm_voter>; 1096 }; 1097 1098 system_noc: interconnect@1620000 { 1099 compatible = "qcom,sm6350-system-noc"; 1100 reg = <0 0x01620000 0 0x17080>; 1101 #interconnect-cells = <2>; 1102 qcom,bcm-voters = <&apps_bcm_voter>; 1103 1104 clk_virt: interconnect-clk-virt { 1105 compatible = "qcom,sm6350-clk-virt"; 1106 #interconnect-cells = <2>; 1107 qcom,bcm-voters = <&apps_bcm_voter>; 1108 }; 1109 }; 1110 1111 aggre1_noc: interconnect@16e0000 { 1112 compatible = "qcom,sm6350-aggre1-noc"; 1113 reg = <0 0x016e0000 0 0x15080>; 1114 #interconnect-cells = <2>; 1115 qcom,bcm-voters = <&apps_bcm_voter>; 1116 }; 1117 1118 aggre2_noc: interconnect@1700000 { 1119 compatible = "qcom,sm6350-aggre2-noc"; 1120 reg = <0 0x01700000 0 0x1f880>; 1121 #interconnect-cells = <2>; 1122 qcom,bcm-voters = <&apps_bcm_voter>; 1123 1124 compute_noc: interconnect-compute-noc { 1125 compatible = "qcom,sm6350-compute-noc"; 1126 #interconnect-cells = <2>; 1127 qcom,bcm-voters = <&apps_bcm_voter>; 1128 }; 1129 }; 1130 1131 mmss_noc: interconnect@1740000 { 1132 compatible = "qcom,sm6350-mmss-noc"; 1133 reg = <0 0x01740000 0 0x1c100>; 1134 #interconnect-cells = <2>; 1135 qcom,bcm-voters = <&apps_bcm_voter>; 1136 }; 1137 1138 ufs_mem_hc: ufs@1d84000 { 1139 compatible = "qcom,sm6350-ufshc", "qcom,ufshc", 1140 "jedec,ufs-2.0"; 1141 reg = <0 0x01d84000 0 0x3000>, 1142 <0 0x01d90000 0 0x8000>; 1143 reg-names = "std", "ice"; 1144 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1145 phys = <&ufs_mem_phy>; 1146 phy-names = "ufsphy"; 1147 lanes-per-direction = <2>; 1148 #reset-cells = <1>; 1149 resets = <&gcc GCC_UFS_PHY_BCR>; 1150 reset-names = "rst"; 1151 1152 power-domains = <&gcc UFS_PHY_GDSC>; 1153 1154 iommus = <&apps_smmu 0x80 0x0>; 1155 1156 clock-names = "core_clk", 1157 "bus_aggr_clk", 1158 "iface_clk", 1159 "core_clk_unipro", 1160 "ref_clk", 1161 "tx_lane0_sync_clk", 1162 "rx_lane0_sync_clk", 1163 "rx_lane1_sync_clk", 1164 "ice_core_clk"; 1165 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1166 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1167 <&gcc GCC_UFS_PHY_AHB_CLK>, 1168 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1169 <&rpmhcc RPMH_QLINK_CLK>, 1170 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1171 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1172 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 1173 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1174 freq-table-hz = 1175 <50000000 200000000>, 1176 <0 0>, 1177 <0 0>, 1178 <37500000 150000000>, 1179 <75000000 300000000>, 1180 <0 0>, 1181 <0 0>, 1182 <0 0>, 1183 <0 0>; 1184 1185 status = "disabled"; 1186 }; 1187 1188 ufs_mem_phy: phy@1d87000 { 1189 compatible = "qcom,sm6350-qmp-ufs-phy"; 1190 reg = <0 0x01d87000 0 0x1000>; 1191 1192 clock-names = "ref", 1193 "ref_aux"; 1194 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 1195 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1196 1197 resets = <&ufs_mem_hc 0>; 1198 reset-names = "ufsphy"; 1199 1200 #phy-cells = <0>; 1201 1202 status = "disabled"; 1203 }; 1204 1205 ipa: ipa@1e40000 { 1206 compatible = "qcom,sm6350-ipa"; 1207 1208 iommus = <&apps_smmu 0x440 0x0>, 1209 <&apps_smmu 0x442 0x0>; 1210 reg = <0 0x01e40000 0 0x8000>, 1211 <0 0x01e50000 0 0x3000>, 1212 <0 0x01e04000 0 0x23000>; 1213 reg-names = "ipa-reg", 1214 "ipa-shared", 1215 "gsi"; 1216 1217 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, 1218 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1219 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1220 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1221 interrupt-names = "ipa", 1222 "gsi", 1223 "ipa-clock-query", 1224 "ipa-setup-ready"; 1225 1226 clocks = <&rpmhcc RPMH_IPA_CLK>; 1227 clock-names = "core"; 1228 1229 interconnects = <&aggre2_noc MASTER_IPA 0 &clk_virt SLAVE_EBI_CH0 0>, 1230 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_OCIMEM 0>, 1231 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_IPA_CFG 0>; 1232 interconnect-names = "memory", "imem", "config"; 1233 1234 qcom,smem-states = <&ipa_smp2p_out 0>, 1235 <&ipa_smp2p_out 1>; 1236 qcom,smem-state-names = "ipa-clock-enabled-valid", 1237 "ipa-clock-enabled"; 1238 1239 status = "disabled"; 1240 }; 1241 1242 tcsr_mutex: hwlock@1f40000 { 1243 compatible = "qcom,tcsr-mutex"; 1244 reg = <0x0 0x01f40000 0x0 0x40000>; 1245 #hwlock-cells = <1>; 1246 }; 1247 1248 adsp: remoteproc@3000000 { 1249 compatible = "qcom,sm6350-adsp-pas"; 1250 reg = <0 0x03000000 0 0x100>; 1251 1252 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 1253 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1254 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1255 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1256 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1257 interrupt-names = "wdog", "fatal", "ready", 1258 "handover", "stop-ack"; 1259 1260 clocks = <&rpmhcc RPMH_CXO_CLK>; 1261 clock-names = "xo"; 1262 1263 power-domains = <&rpmhpd SM6350_LCX>, 1264 <&rpmhpd SM6350_LMX>; 1265 power-domain-names = "lcx", "lmx"; 1266 1267 memory-region = <&pil_adsp_mem>; 1268 1269 qcom,qmp = <&aoss_qmp>; 1270 1271 qcom,smem-states = <&smp2p_adsp_out 0>; 1272 qcom,smem-state-names = "stop"; 1273 1274 status = "disabled"; 1275 1276 glink-edge { 1277 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1278 IPCC_MPROC_SIGNAL_GLINK_QMP 1279 IRQ_TYPE_EDGE_RISING>; 1280 mboxes = <&ipcc IPCC_CLIENT_LPASS 1281 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1282 1283 label = "lpass"; 1284 qcom,remote-pid = <2>; 1285 1286 fastrpc { 1287 compatible = "qcom,fastrpc"; 1288 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1289 label = "adsp"; 1290 #address-cells = <1>; 1291 #size-cells = <0>; 1292 1293 compute-cb@3 { 1294 compatible = "qcom,fastrpc-compute-cb"; 1295 reg = <3>; 1296 iommus = <&apps_smmu 0x1003 0x0>; 1297 }; 1298 1299 compute-cb@4 { 1300 compatible = "qcom,fastrpc-compute-cb"; 1301 reg = <4>; 1302 iommus = <&apps_smmu 0x1004 0x0>; 1303 }; 1304 1305 compute-cb@5 { 1306 compatible = "qcom,fastrpc-compute-cb"; 1307 reg = <5>; 1308 iommus = <&apps_smmu 0x1005 0x0>; 1309 qcom,nsessions = <5>; 1310 }; 1311 }; 1312 }; 1313 }; 1314 1315 gpu: gpu@3d00000 { 1316 compatible = "qcom,adreno-619.0", "qcom,adreno"; 1317 reg = <0 0x03d00000 0 0x40000>, 1318 <0 0x03d9e000 0 0x1000>; 1319 reg-names = "kgsl_3d0_reg_memory", 1320 "cx_mem"; 1321 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1322 1323 iommus = <&adreno_smmu 0>; 1324 operating-points-v2 = <&gpu_opp_table>; 1325 qcom,gmu = <&gmu>; 1326 nvmem-cells = <&gpu_speed_bin>; 1327 nvmem-cell-names = "speed_bin"; 1328 1329 status = "disabled"; 1330 1331 zap-shader { 1332 memory-region = <&pil_gpu_mem>; 1333 }; 1334 1335 gpu_opp_table: opp-table { 1336 compatible = "operating-points-v2"; 1337 1338 opp-850000000 { 1339 opp-hz = /bits/ 64 <850000000>; 1340 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1341 opp-supported-hw = <0x02>; 1342 }; 1343 1344 opp-800000000 { 1345 opp-hz = /bits/ 64 <800000000>; 1346 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1347 opp-supported-hw = <0x04>; 1348 }; 1349 1350 opp-650000000 { 1351 opp-hz = /bits/ 64 <650000000>; 1352 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1353 opp-supported-hw = <0x08>; 1354 }; 1355 1356 opp-565000000 { 1357 opp-hz = /bits/ 64 <565000000>; 1358 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1359 opp-supported-hw = <0x10>; 1360 }; 1361 1362 opp-430000000 { 1363 opp-hz = /bits/ 64 <430000000>; 1364 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1365 opp-supported-hw = <0xff>; 1366 }; 1367 1368 opp-355000000 { 1369 opp-hz = /bits/ 64 <355000000>; 1370 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1371 opp-supported-hw = <0xff>; 1372 }; 1373 1374 opp-253000000 { 1375 opp-hz = /bits/ 64 <253000000>; 1376 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1377 opp-supported-hw = <0xff>; 1378 }; 1379 }; 1380 }; 1381 1382 adreno_smmu: iommu@3d40000 { 1383 compatible = "qcom,sm6350-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 1384 reg = <0 0x03d40000 0 0x10000>; 1385 #iommu-cells = <1>; 1386 #global-interrupts = <2>; 1387 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1388 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1389 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 1390 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 1391 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 1392 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 1393 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 1394 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 1395 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 1396 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1397 1398 clocks = <&gpucc GPU_CC_AHB_CLK>, 1399 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1400 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1401 clock-names = "ahb", 1402 "bus", 1403 "iface"; 1404 1405 power-domains = <&gpucc GPU_CX_GDSC>; 1406 }; 1407 1408 gmu: gmu@3d6a000 { 1409 compatible = "qcom,adreno-gmu-619.0", "qcom,adreno-gmu"; 1410 reg = <0 0x03d6a000 0 0x31000>, 1411 <0 0x0b290000 0 0x10000>, 1412 <0 0x0b490000 0 0x10000>; 1413 reg-names = "gmu", 1414 "gmu_pdc", 1415 "gmu_pdc_seq"; 1416 1417 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1418 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1419 interrupt-names = "hfi", 1420 "gmu"; 1421 1422 clocks = <&gpucc GPU_CC_AHB_CLK>, 1423 <&gpucc GPU_CC_CX_GMU_CLK>, 1424 <&gpucc GPU_CC_CXO_CLK>, 1425 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1426 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1427 clock-names = "ahb", 1428 "gmu", 1429 "cxo", 1430 "axi", 1431 "memnoc"; 1432 1433 power-domains = <&gpucc GPU_CX_GDSC>, 1434 <&gpucc GPU_GX_GDSC>; 1435 power-domain-names = "cx", 1436 "gx"; 1437 1438 iommus = <&adreno_smmu 5>; 1439 1440 operating-points-v2 = <&gmu_opp_table>; 1441 1442 status = "disabled"; 1443 1444 gmu_opp_table: opp-table { 1445 compatible = "operating-points-v2"; 1446 1447 opp-200000000 { 1448 opp-hz = /bits/ 64 <200000000>; 1449 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1450 }; 1451 }; 1452 }; 1453 1454 gpucc: clock-controller@3d90000 { 1455 compatible = "qcom,sm6350-gpucc"; 1456 reg = <0 0x03d90000 0 0x9000>; 1457 clocks = <&rpmhcc RPMH_CXO_CLK>, 1458 <&gcc GCC_GPU_GPLL0_CLK>, 1459 <&gcc GCC_GPU_GPLL0_DIV_CLK>; 1460 clock-names = "bi_tcxo", 1461 "gcc_gpu_gpll0_clk_src", 1462 "gcc_gpu_gpll0_div_clk_src"; 1463 #clock-cells = <1>; 1464 #reset-cells = <1>; 1465 #power-domain-cells = <1>; 1466 }; 1467 1468 mpss: remoteproc@4080000 { 1469 compatible = "qcom,sm6350-mpss-pas"; 1470 reg = <0x0 0x04080000 0x0 0x4040>; 1471 1472 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 1473 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1474 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1475 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1476 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1477 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1478 interrupt-names = "wdog", "fatal", "ready", "handover", 1479 "stop-ack", "shutdown-ack"; 1480 1481 clocks = <&rpmhcc RPMH_CXO_CLK>; 1482 clock-names = "xo"; 1483 1484 power-domains = <&rpmhpd SM6350_CX>, 1485 <&rpmhpd SM6350_MSS>; 1486 power-domain-names = "cx", "mss"; 1487 1488 memory-region = <&pil_modem_mem>; 1489 1490 qcom,qmp = <&aoss_qmp>; 1491 1492 qcom,smem-states = <&modem_smp2p_out 0>; 1493 qcom,smem-state-names = "stop"; 1494 1495 status = "disabled"; 1496 1497 glink-edge { 1498 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 1499 IPCC_MPROC_SIGNAL_GLINK_QMP 1500 IRQ_TYPE_EDGE_RISING>; 1501 mboxes = <&ipcc IPCC_CLIENT_MPSS 1502 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1503 label = "modem"; 1504 qcom,remote-pid = <1>; 1505 }; 1506 }; 1507 1508 cdsp: remoteproc@8300000 { 1509 compatible = "qcom,sm6350-cdsp-pas"; 1510 reg = <0 0x08300000 0 0x10000>; 1511 1512 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 1513 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 1514 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 1515 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 1516 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 1517 interrupt-names = "wdog", "fatal", "ready", 1518 "handover", "stop-ack"; 1519 1520 clocks = <&rpmhcc RPMH_CXO_CLK>; 1521 clock-names = "xo"; 1522 1523 power-domains = <&rpmhpd SM6350_CX>, 1524 <&rpmhpd SM6350_MX>; 1525 power-domain-names = "cx", "mx"; 1526 1527 memory-region = <&pil_cdsp_mem>; 1528 1529 qcom,qmp = <&aoss_qmp>; 1530 1531 qcom,smem-states = <&smp2p_cdsp_out 0>; 1532 qcom,smem-state-names = "stop"; 1533 1534 status = "disabled"; 1535 1536 glink-edge { 1537 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 1538 IPCC_MPROC_SIGNAL_GLINK_QMP 1539 IRQ_TYPE_EDGE_RISING>; 1540 mboxes = <&ipcc IPCC_CLIENT_CDSP 1541 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1542 1543 label = "cdsp"; 1544 qcom,remote-pid = <5>; 1545 1546 fastrpc { 1547 compatible = "qcom,fastrpc"; 1548 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1549 label = "cdsp"; 1550 #address-cells = <1>; 1551 #size-cells = <0>; 1552 1553 compute-cb@1 { 1554 compatible = "qcom,fastrpc-compute-cb"; 1555 reg = <1>; 1556 iommus = <&apps_smmu 0x1401 0x20>; 1557 }; 1558 1559 compute-cb@2 { 1560 compatible = "qcom,fastrpc-compute-cb"; 1561 reg = <2>; 1562 iommus = <&apps_smmu 0x1402 0x20>; 1563 }; 1564 1565 compute-cb@3 { 1566 compatible = "qcom,fastrpc-compute-cb"; 1567 reg = <3>; 1568 iommus = <&apps_smmu 0x1403 0x20>; 1569 }; 1570 1571 compute-cb@4 { 1572 compatible = "qcom,fastrpc-compute-cb"; 1573 reg = <4>; 1574 iommus = <&apps_smmu 0x1404 0x20>; 1575 }; 1576 1577 compute-cb@5 { 1578 compatible = "qcom,fastrpc-compute-cb"; 1579 reg = <5>; 1580 iommus = <&apps_smmu 0x1405 0x20>; 1581 }; 1582 1583 compute-cb@6 { 1584 compatible = "qcom,fastrpc-compute-cb"; 1585 reg = <6>; 1586 iommus = <&apps_smmu 0x1406 0x20>; 1587 }; 1588 1589 compute-cb@7 { 1590 compatible = "qcom,fastrpc-compute-cb"; 1591 reg = <7>; 1592 iommus = <&apps_smmu 0x1407 0x20>; 1593 }; 1594 1595 compute-cb@8 { 1596 compatible = "qcom,fastrpc-compute-cb"; 1597 reg = <8>; 1598 iommus = <&apps_smmu 0x1408 0x20>; 1599 }; 1600 1601 /* note: secure cb9 in downstream */ 1602 }; 1603 }; 1604 }; 1605 1606 sdhc_2: mmc@8804000 { 1607 compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; 1608 reg = <0 0x08804000 0 0x1000>; 1609 1610 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1611 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1612 interrupt-names = "hc_irq", "pwr_irq"; 1613 iommus = <&apps_smmu 0x560 0x0>; 1614 1615 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1616 <&gcc GCC_SDCC2_APPS_CLK>, 1617 <&rpmhcc RPMH_CXO_CLK>; 1618 clock-names = "iface", "core", "xo"; 1619 resets = <&gcc GCC_SDCC2_BCR>; 1620 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>, 1621 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>; 1622 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 1623 1624 pinctrl-0 = <&sdc2_on_state>; 1625 pinctrl-1 = <&sdc2_off_state>; 1626 pinctrl-names = "default", "sleep"; 1627 1628 qcom,dll-config = <0x0007642c>; 1629 qcom,ddr-config = <0x80040868>; 1630 power-domains = <&rpmhpd SM6350_CX>; 1631 operating-points-v2 = <&sdhc2_opp_table>; 1632 bus-width = <4>; 1633 1634 status = "disabled"; 1635 1636 sdhc2_opp_table: opp-table { 1637 compatible = "operating-points-v2"; 1638 1639 opp-100000000 { 1640 opp-hz = /bits/ 64 <100000000>; 1641 required-opps = <&rpmhpd_opp_svs_l1>; 1642 opp-peak-kBps = <790000 131000>; 1643 opp-avg-kBps = <50000 50000>; 1644 }; 1645 1646 opp-202000000 { 1647 opp-hz = /bits/ 64 <202000000>; 1648 required-opps = <&rpmhpd_opp_nom>; 1649 opp-peak-kBps = <3190000 294000>; 1650 opp-avg-kBps = <261438 300000>; 1651 }; 1652 }; 1653 }; 1654 1655 usb_1_hsphy: phy@88e3000 { 1656 compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy"; 1657 reg = <0 0x088e3000 0 0x400>; 1658 status = "disabled"; 1659 #phy-cells = <0>; 1660 1661 clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>; 1662 clock-names = "cfg_ahb", "ref"; 1663 1664 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1665 }; 1666 1667 usb_1_qmpphy: phy@88e8000 { 1668 compatible = "qcom,sm6350-qmp-usb3-dp-phy"; 1669 reg = <0 0x088e8000 0 0x3000>; 1670 1671 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 1672 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 1673 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 1674 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 1675 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 1676 1677 power-domains = <&gcc USB30_PRIM_GDSC>; 1678 1679 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 1680 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 1681 reset-names = "phy", "common"; 1682 1683 #clock-cells = <1>; 1684 #phy-cells = <1>; 1685 1686 status = "disabled"; 1687 }; 1688 1689 dc_noc: interconnect@9160000 { 1690 compatible = "qcom,sm6350-dc-noc"; 1691 reg = <0 0x09160000 0 0x3200>; 1692 #interconnect-cells = <2>; 1693 qcom,bcm-voters = <&apps_bcm_voter>; 1694 }; 1695 1696 system-cache-controller@9200000 { 1697 compatible = "qcom,sm6350-llcc"; 1698 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; 1699 reg-names = "llcc0_base", "llcc_broadcast_base"; 1700 }; 1701 1702 gem_noc: interconnect@9680000 { 1703 compatible = "qcom,sm6350-gem-noc"; 1704 reg = <0 0x09680000 0 0x3e200>; 1705 #interconnect-cells = <2>; 1706 qcom,bcm-voters = <&apps_bcm_voter>; 1707 }; 1708 1709 npu_noc: interconnect@9990000 { 1710 compatible = "qcom,sm6350-npu-noc"; 1711 reg = <0 0x09990000 0 0x1600>; 1712 #interconnect-cells = <2>; 1713 qcom,bcm-voters = <&apps_bcm_voter>; 1714 }; 1715 1716 pmu@90b6300 { 1717 compatible = "qcom,sm6350-llcc-bwmon", "qcom,sdm845-bwmon"; 1718 reg = <0x0 0x090b6300 0x0 0x600>; 1719 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 1720 1721 operating-points-v2 = <&llcc_bwmon_opp_table>; 1722 interconnects = <&clk_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 1723 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>; 1724 1725 llcc_bwmon_opp_table: opp-table { 1726 compatible = "operating-points-v2"; 1727 1728 opp-0 { 1729 opp-peak-kBps = <2288000>; 1730 }; 1731 1732 opp-1 { 1733 opp-peak-kBps = <4577000>; 1734 }; 1735 1736 opp-2 { 1737 opp-peak-kBps = <7110000>; 1738 }; 1739 1740 opp-3 { 1741 opp-peak-kBps = <9155000>; 1742 }; 1743 1744 opp-4 { 1745 opp-peak-kBps = <12298000>; 1746 }; 1747 1748 opp-5 { 1749 opp-peak-kBps = <14236000>; 1750 }; 1751 1752 }; 1753 }; 1754 1755 pmu@90cd000 { 1756 compatible = "qcom,sm6350-cpu-bwmon", "qcom,sc7280-llcc-bwmon"; 1757 reg = <0x0 0x090cd000 0x0 0x1000>; 1758 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1759 1760 operating-points-v2 = <&cpu_bwmon_opp_table>; 1761 interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY 1762 &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>; 1763 1764 cpu_bwmon_opp_table: opp-table { 1765 compatible = "operating-points-v2"; 1766 1767 opp-0 { 1768 opp-peak-kBps = <762000>; 1769 }; 1770 1771 opp-1 { 1772 opp-peak-kBps = <1144000>; 1773 }; 1774 1775 opp-2 { 1776 opp-peak-kBps = <1720000>; 1777 }; 1778 1779 opp-3 { 1780 opp-peak-kBps = <2086000>; 1781 }; 1782 1783 opp-4 { 1784 opp-peak-kBps = <2597000>; 1785 }; 1786 1787 opp-5 { 1788 opp-peak-kBps = <2929000>; 1789 }; 1790 1791 opp-6 { 1792 opp-peak-kBps = <3879000>; 1793 }; 1794 1795 opp-7 { 1796 opp-peak-kBps = <5161000>; 1797 }; 1798 1799 opp-8 { 1800 opp-peak-kBps = <5931000>; 1801 }; 1802 1803 opp-9 { 1804 opp-peak-kBps = <6881000>; 1805 }; 1806 1807 opp-10 { 1808 opp-peak-kBps = <7980000>; 1809 }; 1810 }; 1811 }; 1812 1813 usb_1: usb@a6f8800 { 1814 compatible = "qcom,sm6350-dwc3", "qcom,dwc3"; 1815 reg = <0 0x0a6f8800 0 0x400>; 1816 status = "disabled"; 1817 #address-cells = <2>; 1818 #size-cells = <2>; 1819 ranges; 1820 1821 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1822 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1823 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1824 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1825 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 1826 clock-names = "cfg_noc", 1827 "core", 1828 "iface", 1829 "sleep", 1830 "mock_utmi"; 1831 1832 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1833 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, 1834 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 1835 <&pdc 14 IRQ_TYPE_EDGE_BOTH>; 1836 1837 interrupt-names = "hs_phy_irq", "ss_phy_irq", 1838 "dm_hs_phy_irq", "dp_hs_phy_irq"; 1839 1840 power-domains = <&gcc USB30_PRIM_GDSC>; 1841 1842 resets = <&gcc GCC_USB30_PRIM_BCR>; 1843 1844 interconnects = <&aggre2_noc MASTER_USB3 0 &clk_virt SLAVE_EBI_CH0 0>, 1845 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 1846 interconnect-names = "usb-ddr", "apps-usb"; 1847 1848 usb_1_dwc3: usb@a600000 { 1849 compatible = "snps,dwc3"; 1850 reg = <0 0x0a600000 0 0xcd00>; 1851 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1852 iommus = <&apps_smmu 0x540 0x0>; 1853 snps,dis_u2_susphy_quirk; 1854 snps,dis_enblslpm_quirk; 1855 snps,has-lpm-erratum; 1856 snps,hird-threshold = /bits/ 8 <0x10>; 1857 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 1858 phy-names = "usb2-phy", "usb3-phy"; 1859 }; 1860 }; 1861 1862 cci0: cci@ac4a000 { 1863 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; 1864 reg = <0 0x0ac4a000 0 0x1000>; 1865 interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>; 1866 power-domains = <&camcc TITAN_TOP_GDSC>; 1867 1868 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1869 <&camcc CAMCC_SOC_AHB_CLK>, 1870 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 1871 <&camcc CAMCC_CPAS_AHB_CLK>, 1872 <&camcc CAMCC_CCI_0_CLK>, 1873 <&camcc CAMCC_CCI_0_CLK_SRC>; 1874 clock-names = "camnoc_axi", 1875 "soc_ahb", 1876 "slow_ahb_src", 1877 "cpas_ahb", 1878 "cci", 1879 "cci_src"; 1880 1881 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1882 <&camcc CAMCC_CCI_0_CLK>; 1883 assigned-clock-rates = <80000000>, <37500000>; 1884 1885 pinctrl-0 = <&cci0_default &cci1_default>; 1886 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 1887 pinctrl-names = "default", "sleep"; 1888 1889 #address-cells = <1>; 1890 #size-cells = <0>; 1891 1892 status = "disabled"; 1893 1894 cci0_i2c0: i2c-bus@0 { 1895 reg = <0>; 1896 clock-frequency = <1000000>; 1897 #address-cells = <1>; 1898 #size-cells = <0>; 1899 }; 1900 1901 cci0_i2c1: i2c-bus@1 { 1902 reg = <1>; 1903 clock-frequency = <1000000>; 1904 #address-cells = <1>; 1905 #size-cells = <0>; 1906 }; 1907 }; 1908 1909 cci1: cci@ac4b000 { 1910 compatible = "qcom,sm6350-cci", "qcom,msm8996-cci"; 1911 reg = <0 0x0ac4b000 0 0x1000>; 1912 interrupts = <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>; 1913 power-domains = <&camcc TITAN_TOP_GDSC>; 1914 1915 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1916 <&camcc CAMCC_SOC_AHB_CLK>, 1917 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 1918 <&camcc CAMCC_CPAS_AHB_CLK>, 1919 <&camcc CAMCC_CCI_1_CLK>, 1920 <&camcc CAMCC_CCI_1_CLK_SRC>; 1921 clock-names = "camnoc_axi", 1922 "soc_ahb", 1923 "slow_ahb_src", 1924 "cpas_ahb", 1925 "cci", 1926 "cci_src"; 1927 1928 assigned-clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 1929 <&camcc CAMCC_CCI_1_CLK>; 1930 assigned-clock-rates = <80000000>, <37500000>; 1931 1932 pinctrl-0 = <&cci2_default>; 1933 pinctrl-1 = <&cci2_sleep>; 1934 pinctrl-names = "default", "sleep"; 1935 1936 #address-cells = <1>; 1937 #size-cells = <0>; 1938 1939 status = "disabled"; 1940 1941 cci1_i2c0: i2c-bus@0 { 1942 reg = <0>; 1943 clock-frequency = <1000000>; 1944 #address-cells = <1>; 1945 #size-cells = <0>; 1946 }; 1947 1948 /* SM6350 seems to have cci1_i2c1 on gpio2 & gpio3 but unused downstream */ 1949 }; 1950 1951 camcc: clock-controller@ad00000 { 1952 compatible = "qcom,sm6350-camcc"; 1953 reg = <0 0x0ad00000 0 0x16000>; 1954 clocks = <&rpmhcc RPMH_CXO_CLK>; 1955 #clock-cells = <1>; 1956 #reset-cells = <1>; 1957 #power-domain-cells = <1>; 1958 }; 1959 1960 mdss: display-subsystem@ae00000 { 1961 compatible = "qcom,sm6350-mdss"; 1962 reg = <0 0x0ae00000 0 0x1000>; 1963 reg-names = "mdss"; 1964 1965 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1966 interrupt-controller; 1967 #interrupt-cells = <1>; 1968 1969 clocks = <&gcc GCC_DISP_AHB_CLK>, 1970 <&gcc GCC_DISP_AXI_CLK>, 1971 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1972 clock-names = "iface", 1973 "bus", 1974 "core"; 1975 1976 power-domains = <&dispcc MDSS_GDSC>; 1977 iommus = <&apps_smmu 0x800 0x2>; 1978 1979 #address-cells = <2>; 1980 #size-cells = <2>; 1981 ranges; 1982 1983 status = "disabled"; 1984 1985 mdss_mdp: display-controller@ae01000 { 1986 compatible = "qcom,sm6350-dpu"; 1987 reg = <0 0x0ae01000 0 0x8f000>, 1988 <0 0x0aeb0000 0 0x2008>; 1989 reg-names = "mdp", "vbif"; 1990 1991 interrupt-parent = <&mdss>; 1992 interrupts = <0>; 1993 1994 clocks = <&gcc GCC_DISP_AXI_CLK>, 1995 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1996 <&dispcc DISP_CC_MDSS_ROT_CLK>, 1997 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 1998 <&dispcc DISP_CC_MDSS_MDP_CLK>, 1999 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2000 clock-names = "bus", 2001 "iface", 2002 "rot", 2003 "lut", 2004 "core", 2005 "vsync"; 2006 2007 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2008 assigned-clock-rates = <19200000>; 2009 2010 operating-points-v2 = <&mdp_opp_table>; 2011 power-domains = <&rpmhpd SM6350_CX>; 2012 2013 ports { 2014 #address-cells = <1>; 2015 #size-cells = <0>; 2016 2017 port@0 { 2018 reg = <0>; 2019 2020 dpu_intf1_out: endpoint { 2021 remote-endpoint = <&mdss_dsi0_in>; 2022 }; 2023 }; 2024 }; 2025 2026 mdp_opp_table: opp-table { 2027 compatible = "operating-points-v2"; 2028 2029 opp-19200000 { 2030 opp-hz = /bits/ 64 <19200000>; 2031 required-opps = <&rpmhpd_opp_min_svs>; 2032 }; 2033 2034 opp-200000000 { 2035 opp-hz = /bits/ 64 <200000000>; 2036 required-opps = <&rpmhpd_opp_low_svs>; 2037 }; 2038 2039 opp-300000000 { 2040 opp-hz = /bits/ 64 <300000000>; 2041 required-opps = <&rpmhpd_opp_svs>; 2042 }; 2043 2044 opp-373333333 { 2045 opp-hz = /bits/ 64 <373333333>; 2046 required-opps = <&rpmhpd_opp_svs_l1>; 2047 }; 2048 2049 opp-448000000 { 2050 opp-hz = /bits/ 64 <448000000>; 2051 required-opps = <&rpmhpd_opp_nom>; 2052 }; 2053 2054 opp-560000000 { 2055 opp-hz = /bits/ 64 <560000000>; 2056 required-opps = <&rpmhpd_opp_turbo>; 2057 }; 2058 }; 2059 }; 2060 2061 mdss_dsi0: dsi@ae94000 { 2062 compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2063 reg = <0 0x0ae94000 0 0x400>; 2064 reg-names = "dsi_ctrl"; 2065 2066 interrupt-parent = <&mdss>; 2067 interrupts = <4>; 2068 2069 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2070 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2071 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2072 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2073 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2074 <&gcc GCC_DISP_AXI_CLK>; 2075 clock-names = "byte", 2076 "byte_intf", 2077 "pixel", 2078 "core", 2079 "iface", 2080 "bus"; 2081 2082 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2083 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2084 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 2085 2086 operating-points-v2 = <&mdss_dsi_opp_table>; 2087 power-domains = <&rpmhpd SM6350_MX>; 2088 2089 phys = <&mdss_dsi0_phy>; 2090 phy-names = "dsi"; 2091 2092 #address-cells = <1>; 2093 #size-cells = <0>; 2094 2095 status = "disabled"; 2096 2097 ports { 2098 #address-cells = <1>; 2099 #size-cells = <0>; 2100 2101 port@0 { 2102 reg = <0>; 2103 2104 mdss_dsi0_in: endpoint { 2105 remote-endpoint = <&dpu_intf1_out>; 2106 }; 2107 }; 2108 2109 port@1 { 2110 reg = <1>; 2111 2112 mdss_dsi0_out: endpoint { 2113 }; 2114 }; 2115 }; 2116 2117 mdss_dsi_opp_table: opp-table { 2118 compatible = "operating-points-v2"; 2119 2120 opp-187500000 { 2121 opp-hz = /bits/ 64 <187500000>; 2122 required-opps = <&rpmhpd_opp_low_svs>; 2123 }; 2124 2125 opp-300000000 { 2126 opp-hz = /bits/ 64 <300000000>; 2127 required-opps = <&rpmhpd_opp_svs>; 2128 }; 2129 2130 opp-358000000 { 2131 opp-hz = /bits/ 64 <358000000>; 2132 required-opps = <&rpmhpd_opp_svs_l1>; 2133 }; 2134 }; 2135 }; 2136 2137 mdss_dsi0_phy: phy@ae94400 { 2138 compatible = "qcom,dsi-phy-10nm"; 2139 reg = <0 0x0ae94400 0 0x200>, 2140 <0 0x0ae94600 0 0x280>, 2141 <0 0x0ae94a00 0 0x1e0>; 2142 reg-names = "dsi_phy", 2143 "dsi_phy_lane", 2144 "dsi_pll"; 2145 2146 #clock-cells = <1>; 2147 #phy-cells = <0>; 2148 2149 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2150 <&rpmhcc RPMH_CXO_CLK>; 2151 clock-names = "iface", "ref"; 2152 2153 status = "disabled"; 2154 }; 2155 }; 2156 2157 dispcc: clock-controller@af00000 { 2158 compatible = "qcom,sm6350-dispcc"; 2159 reg = <0 0x0af00000 0 0x20000>; 2160 clocks = <&rpmhcc RPMH_CXO_CLK>, 2161 <&gcc GCC_DISP_GPLL0_CLK>, 2162 <&mdss_dsi0_phy 0>, 2163 <&mdss_dsi0_phy 1>, 2164 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2165 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2166 clock-names = "bi_tcxo", 2167 "gcc_disp_gpll0_clk", 2168 "dsi0_phy_pll_out_byteclk", 2169 "dsi0_phy_pll_out_dsiclk", 2170 "dp_phy_pll_link_clk", 2171 "dp_phy_pll_vco_div_clk"; 2172 #clock-cells = <1>; 2173 #reset-cells = <1>; 2174 #power-domain-cells = <1>; 2175 }; 2176 2177 pdc: interrupt-controller@b220000 { 2178 compatible = "qcom,sm6350-pdc", "qcom,pdc"; 2179 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>; 2180 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 2181 <125 63 1>, <126 655 12>, <138 139 15>; 2182 #interrupt-cells = <2>; 2183 interrupt-parent = <&intc>; 2184 interrupt-controller; 2185 }; 2186 2187 tsens0: thermal-sensor@c263000 { 2188 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 2189 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2190 <0 0x0c222000 0 0x8>; /* SROT */ 2191 #qcom,sensors = <16>; 2192 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 2193 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 2194 interrupt-names = "uplow", "critical"; 2195 #thermal-sensor-cells = <1>; 2196 }; 2197 2198 tsens1: thermal-sensor@c265000 { 2199 compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; 2200 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2201 <0 0x0c223000 0 0x8>; /* SROT */ 2202 #qcom,sensors = <16>; 2203 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 2204 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 2205 interrupt-names = "uplow", "critical"; 2206 #thermal-sensor-cells = <1>; 2207 }; 2208 2209 aoss_qmp: power-management@c300000 { 2210 compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp"; 2211 reg = <0 0x0c300000 0 0x1000>; 2212 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2213 IRQ_TYPE_EDGE_RISING>; 2214 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2215 2216 #clock-cells = <0>; 2217 }; 2218 2219 spmi_bus: spmi@c440000 { 2220 compatible = "qcom,spmi-pmic-arb"; 2221 reg = <0 0x0c440000 0 0x1100>, 2222 <0 0x0c600000 0 0x2000000>, 2223 <0 0x0e600000 0 0x100000>, 2224 <0 0x0e700000 0 0xa0000>, 2225 <0 0x0c40a000 0 0x26000>; 2226 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2227 interrupt-names = "periph_irq"; 2228 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2229 qcom,ee = <0>; 2230 qcom,channel = <0>; 2231 #address-cells = <2>; 2232 #size-cells = <0>; 2233 interrupt-controller; 2234 #interrupt-cells = <4>; 2235 }; 2236 2237 tlmm: pinctrl@f100000 { 2238 compatible = "qcom,sm6350-tlmm"; 2239 reg = <0 0x0f100000 0 0x300000>; 2240 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 2241 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 2242 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 2243 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 2244 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 2245 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 2246 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 2247 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 2248 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 2249 gpio-controller; 2250 #gpio-cells = <2>; 2251 interrupt-controller; 2252 #interrupt-cells = <2>; 2253 gpio-ranges = <&tlmm 0 0 157>; 2254 wakeup-parent = <&pdc>; 2255 2256 cci0_default: cci0-default-state { 2257 pins = "gpio39", "gpio40"; 2258 function = "cci_i2c"; 2259 drive-strength = <2>; 2260 bias-pull-up; 2261 }; 2262 2263 cci0_sleep: cci0-sleep-state { 2264 pins = "gpio39", "gpio40"; 2265 function = "cci_i2c"; 2266 drive-strength = <2>; 2267 bias-pull-down; 2268 }; 2269 2270 cci1_default: cci1-default-state { 2271 pins = "gpio41", "gpio42"; 2272 function = "cci_i2c"; 2273 drive-strength = <2>; 2274 bias-pull-up; 2275 }; 2276 2277 cci1_sleep: cci1-sleep-state { 2278 pins = "gpio41", "gpio42"; 2279 function = "cci_i2c"; 2280 drive-strength = <2>; 2281 bias-pull-down; 2282 }; 2283 2284 cci2_default: cci2-default-state { 2285 pins = "gpio43", "gpio44"; 2286 function = "cci_i2c"; 2287 drive-strength = <2>; 2288 bias-pull-up; 2289 }; 2290 2291 cci2_sleep: cci2-sleep-state { 2292 pins = "gpio43", "gpio44"; 2293 function = "cci_i2c"; 2294 drive-strength = <2>; 2295 bias-pull-down; 2296 }; 2297 2298 sdc2_off_state: sdc2-off-state { 2299 clk-pins { 2300 pins = "sdc2_clk"; 2301 drive-strength = <2>; 2302 bias-disable; 2303 }; 2304 2305 cmd-pins { 2306 pins = "sdc2_cmd"; 2307 drive-strength = <2>; 2308 bias-pull-up; 2309 }; 2310 2311 data-pins { 2312 pins = "sdc2_data"; 2313 drive-strength = <2>; 2314 bias-pull-up; 2315 }; 2316 }; 2317 2318 sdc2_on_state: sdc2-on-state { 2319 clk-pins { 2320 pins = "sdc2_clk"; 2321 drive-strength = <16>; 2322 bias-disable; 2323 }; 2324 2325 cmd-pins { 2326 pins = "sdc2_cmd"; 2327 drive-strength = <10>; 2328 bias-pull-up; 2329 }; 2330 2331 data-pins { 2332 pins = "sdc2_data"; 2333 drive-strength = <10>; 2334 bias-pull-up; 2335 }; 2336 }; 2337 2338 qup_uart9_default: qup-uart9-default-state { 2339 pins = "gpio25", "gpio26"; 2340 function = "qup13_f2"; 2341 drive-strength = <2>; 2342 bias-disable; 2343 }; 2344 2345 qup_i2c0_default: qup-i2c0-default-state { 2346 pins = "gpio0", "gpio1"; 2347 function = "qup00"; 2348 drive-strength = <2>; 2349 bias-pull-up; 2350 }; 2351 2352 qup_i2c2_default: qup-i2c2-default-state { 2353 pins = "gpio45", "gpio46"; 2354 function = "qup02"; 2355 drive-strength = <2>; 2356 bias-pull-up; 2357 }; 2358 2359 qup_i2c6_default: qup-i2c6-default-state { 2360 pins = "gpio13", "gpio14"; 2361 function = "qup10"; 2362 drive-strength = <2>; 2363 bias-pull-up; 2364 }; 2365 2366 qup_i2c7_default: qup-i2c7-default-state { 2367 pins = "gpio27", "gpio28"; 2368 function = "qup11"; 2369 drive-strength = <2>; 2370 bias-pull-up; 2371 }; 2372 2373 qup_i2c8_default: qup-i2c8-default-state { 2374 pins = "gpio19", "gpio20"; 2375 function = "qup12"; 2376 drive-strength = <2>; 2377 bias-pull-up; 2378 }; 2379 2380 qup_i2c10_default: qup-i2c10-default-state { 2381 pins = "gpio4", "gpio5"; 2382 function = "qup14"; 2383 drive-strength = <2>; 2384 bias-pull-up; 2385 }; 2386 2387 qup_uart1_cts: qup-uart1-cts-default-state { 2388 pins = "gpio61"; 2389 function = "qup01"; 2390 drive-strength = <2>; 2391 bias-disable; 2392 }; 2393 2394 qup_uart1_rts: qup-uart1-rts-default-state { 2395 pins = "gpio62"; 2396 function = "qup01"; 2397 drive-strength = <2>; 2398 bias-pull-down; 2399 }; 2400 2401 qup_uart1_rx: qup-uart1-rx-default-state { 2402 pins = "gpio64"; 2403 function = "qup01"; 2404 drive-strength = <2>; 2405 bias-disable; 2406 }; 2407 2408 qup_uart1_tx: qup-uart1-tx-default-state { 2409 pins = "gpio63"; 2410 function = "qup01"; 2411 drive-strength = <2>; 2412 bias-pull-up; 2413 }; 2414 }; 2415 2416 apps_smmu: iommu@15000000 { 2417 compatible = "qcom,sm6350-smmu-500", "arm,mmu-500"; 2418 reg = <0 0x15000000 0 0x100000>; 2419 #iommu-cells = <2>; 2420 #global-interrupts = <1>; 2421 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 2422 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 2423 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 2424 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2425 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2426 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2427 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2428 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2429 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2430 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2431 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2432 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2433 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2434 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2435 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2436 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2437 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2438 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2439 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2440 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2441 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2442 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2443 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2444 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2445 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2446 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 2447 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 2448 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 2449 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 2450 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 2451 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 2452 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 2453 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 2454 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 2455 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 2456 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 2457 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 2458 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 2459 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 2460 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 2461 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 2462 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 2463 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2464 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2465 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2466 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2467 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2468 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2469 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2470 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2471 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2472 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2473 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2474 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2475 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2476 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2477 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2478 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2479 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2480 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2481 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2482 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2483 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2484 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2485 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2486 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2487 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2488 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2489 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2490 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2491 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 2492 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2493 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 2494 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 2495 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 2496 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 2497 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 2498 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 2499 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 2500 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 2501 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 2502 }; 2503 2504 intc: interrupt-controller@17a00000 { 2505 compatible = "arm,gic-v3"; 2506 #interrupt-cells = <3>; 2507 interrupt-controller; 2508 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 2509 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 2510 interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; 2511 }; 2512 2513 watchdog@17c10000 { 2514 compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt"; 2515 reg = <0 0x17c10000 0 0x1000>; 2516 clocks = <&sleep_clk>; 2517 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 2518 }; 2519 2520 timer@17c20000 { 2521 compatible = "arm,armv7-timer-mem"; 2522 reg = <0x0 0x17c20000 0x0 0x1000>; 2523 clock-frequency = <19200000>; 2524 #address-cells = <1>; 2525 #size-cells = <1>; 2526 ranges = <0 0 0 0x20000000>; 2527 2528 frame@17c21000 { 2529 frame-number = <0>; 2530 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2531 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 2532 reg = <0x17c21000 0x1000>, 2533 <0x17c22000 0x1000>; 2534 }; 2535 2536 frame@17c23000 { 2537 frame-number = <1>; 2538 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2539 reg = <0x17c23000 0x1000>; 2540 status = "disabled"; 2541 }; 2542 2543 frame@17c25000 { 2544 frame-number = <2>; 2545 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2546 reg = <0x17c25000 0x1000>; 2547 status = "disabled"; 2548 }; 2549 2550 frame@17c27000 { 2551 frame-number = <3>; 2552 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2553 reg = <0x17c27000 0x1000>; 2554 status = "disabled"; 2555 }; 2556 2557 frame@17c29000 { 2558 frame-number = <4>; 2559 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2560 reg = <0x17c29000 0x1000>; 2561 status = "disabled"; 2562 }; 2563 2564 frame@17c2b000 { 2565 frame-number = <5>; 2566 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2567 reg = <0x17c2b000 0x1000>; 2568 status = "disabled"; 2569 }; 2570 2571 frame@17c2d000 { 2572 frame-number = <6>; 2573 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2574 reg = <0x17c2d000 0x1000>; 2575 status = "disabled"; 2576 }; 2577 }; 2578 2579 apps_rsc: rsc@18200000 { 2580 compatible = "qcom,rpmh-rsc"; 2581 label = "apps_rsc"; 2582 reg = <0x0 0x18200000 0x0 0x10000>, 2583 <0x0 0x18210000 0x0 0x10000>, 2584 <0x0 0x18220000 0x0 0x10000>; 2585 reg-names = "drv-0", "drv-1", "drv-2"; 2586 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2587 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2588 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 2589 qcom,tcs-offset = <0xd00>; 2590 qcom,drv-id = <2>; 2591 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 2592 <WAKE_TCS 3>, <CONTROL_TCS 1>; 2593 power-domains = <&CLUSTER_PD>; 2594 2595 rpmhcc: clock-controller { 2596 compatible = "qcom,sm6350-rpmh-clk"; 2597 #clock-cells = <1>; 2598 clock-names = "xo"; 2599 clocks = <&xo_board>; 2600 }; 2601 2602 rpmhpd: power-controller { 2603 compatible = "qcom,sm6350-rpmhpd"; 2604 #power-domain-cells = <1>; 2605 operating-points-v2 = <&rpmhpd_opp_table>; 2606 2607 rpmhpd_opp_table: opp-table { 2608 compatible = "operating-points-v2"; 2609 2610 rpmhpd_opp_ret: opp1 { 2611 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 2612 }; 2613 2614 rpmhpd_opp_min_svs: opp2 { 2615 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2616 }; 2617 2618 rpmhpd_opp_low_svs: opp3 { 2619 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2620 }; 2621 2622 rpmhpd_opp_svs: opp4 { 2623 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2624 }; 2625 2626 rpmhpd_opp_svs_l1: opp5 { 2627 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2628 }; 2629 2630 rpmhpd_opp_nom: opp6 { 2631 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2632 }; 2633 2634 rpmhpd_opp_nom_l1: opp7 { 2635 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2636 }; 2637 2638 rpmhpd_opp_nom_l2: opp8 { 2639 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 2640 }; 2641 2642 rpmhpd_opp_turbo: opp9 { 2643 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2644 }; 2645 2646 rpmhpd_opp_turbo_l1: opp10 { 2647 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2648 }; 2649 }; 2650 }; 2651 2652 apps_bcm_voter: bcm-voter { 2653 compatible = "qcom,bcm-voter"; 2654 }; 2655 }; 2656 2657 osm_l3: interconnect@18321000 { 2658 compatible = "qcom,sm6350-osm-l3", "qcom,osm-l3"; 2659 reg = <0x0 0x18321000 0x0 0x1000>; 2660 2661 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2662 clock-names = "xo", "alternate"; 2663 2664 #interconnect-cells = <1>; 2665 }; 2666 2667 cpufreq_hw: cpufreq@18323000 { 2668 compatible = "qcom,sm6350-cpufreq-hw", "qcom,cpufreq-hw"; 2669 reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>; 2670 reg-names = "freq-domain0", "freq-domain1"; 2671 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2672 clock-names = "xo", "alternate"; 2673 2674 #freq-domain-cells = <1>; 2675 #clock-cells = <1>; 2676 }; 2677 2678 wifi: wifi@18800000 { 2679 compatible = "qcom,wcn3990-wifi"; 2680 reg = <0 0x18800000 0 0x800000>; 2681 reg-names = "membase"; 2682 memory-region = <&wlan_fw_mem>; 2683 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 2684 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 2685 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 2686 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 2687 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2688 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 2689 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 2690 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2691 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2692 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2693 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2694 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 2695 iommus = <&apps_smmu 0x20 0x1>; 2696 qcom,msa-fixed-perm; 2697 status = "disabled"; 2698 }; 2699 }; 2700 2701 timer { 2702 compatible = "arm,armv8-timer"; 2703 clock-frequency = <19200000>; 2704 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2705 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2706 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2707 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2708 }; 2709}; 2710