1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,qcs615-camcc.h> 7#include <dt-bindings/clock/qcom,qcs615-dispcc.h> 8#include <dt-bindings/clock/qcom,qcs615-gcc.h> 9#include <dt-bindings/clock/qcom,qcs615-gpucc.h> 10#include <dt-bindings/clock/qcom,qcs615-videocc.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/interconnect/qcom,icc.h> 14#include <dt-bindings/interconnect/qcom,qcs615-rpmh.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/power/qcom-rpmpd.h> 17#include <dt-bindings/power/qcom,rpmhpd.h> 18#include <dt-bindings/soc/qcom,rpmh-rsc.h> 19 20/ { 21 interrupt-parent = <&intc>; 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 cpus { 26 #address-cells = <2>; 27 #size-cells = <0>; 28 29 cpu0: cpu@0 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a55"; 32 reg = <0x0 0x0>; 33 enable-method = "psci"; 34 power-domains = <&cpu_pd0>; 35 power-domain-names = "psci"; 36 capacity-dmips-mhz = <1024>; 37 dynamic-power-coefficient = <100>; 38 next-level-cache = <&l2_0>; 39 clocks = <&cpufreq_hw 0>; 40 qcom,freq-domain = <&cpufreq_hw 0>; 41 #cooling-cells = <2>; 42 43 l2_0: l2-cache { 44 compatible = "cache"; 45 cache-level = <2>; 46 cache-unified; 47 next-level-cache = <&l3_0>; 48 }; 49 }; 50 51 cpu1: cpu@100 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a55"; 54 reg = <0x0 0x100>; 55 enable-method = "psci"; 56 power-domains = <&cpu_pd1>; 57 power-domain-names = "psci"; 58 capacity-dmips-mhz = <1024>; 59 dynamic-power-coefficient = <100>; 60 next-level-cache = <&l2_100>; 61 clocks = <&cpufreq_hw 0>; 62 qcom,freq-domain = <&cpufreq_hw 0>; 63 64 l2_100: l2-cache { 65 compatible = "cache"; 66 cache-level = <2>; 67 cache-unified; 68 next-level-cache = <&l3_0>; 69 }; 70 }; 71 72 cpu2: cpu@200 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a55"; 75 reg = <0x0 0x200>; 76 enable-method = "psci"; 77 power-domains = <&cpu_pd2>; 78 power-domain-names = "psci"; 79 capacity-dmips-mhz = <1024>; 80 dynamic-power-coefficient = <100>; 81 next-level-cache = <&l2_200>; 82 clocks = <&cpufreq_hw 0>; 83 qcom,freq-domain = <&cpufreq_hw 0>; 84 85 l2_200: l2-cache { 86 compatible = "cache"; 87 cache-level = <2>; 88 cache-unified; 89 next-level-cache = <&l3_0>; 90 }; 91 }; 92 93 cpu3: cpu@300 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a55"; 96 reg = <0x0 0x300>; 97 enable-method = "psci"; 98 power-domains = <&cpu_pd3>; 99 power-domain-names = "psci"; 100 capacity-dmips-mhz = <1024>; 101 dynamic-power-coefficient = <100>; 102 next-level-cache = <&l2_300>; 103 clocks = <&cpufreq_hw 0>; 104 qcom,freq-domain = <&cpufreq_hw 0>; 105 106 l2_300: l2-cache { 107 compatible = "cache"; 108 cache-level = <2>; 109 cache-unified; 110 next-level-cache = <&l3_0>; 111 }; 112 }; 113 114 cpu4: cpu@400 { 115 device_type = "cpu"; 116 compatible = "arm,cortex-a55"; 117 reg = <0x0 0x400>; 118 enable-method = "psci"; 119 power-domains = <&cpu_pd4>; 120 power-domain-names = "psci"; 121 capacity-dmips-mhz = <1024>; 122 dynamic-power-coefficient = <100>; 123 next-level-cache = <&l2_400>; 124 clocks = <&cpufreq_hw 0>; 125 qcom,freq-domain = <&cpufreq_hw 0>; 126 127 l2_400: l2-cache { 128 compatible = "cache"; 129 cache-level = <2>; 130 cache-unified; 131 next-level-cache = <&l3_0>; 132 }; 133 }; 134 135 cpu5: cpu@500 { 136 device_type = "cpu"; 137 compatible = "arm,cortex-a55"; 138 reg = <0x0 0x500>; 139 enable-method = "psci"; 140 power-domains = <&cpu_pd5>; 141 power-domain-names = "psci"; 142 capacity-dmips-mhz = <1024>; 143 dynamic-power-coefficient = <100>; 144 next-level-cache = <&l2_500>; 145 clocks = <&cpufreq_hw 0>; 146 qcom,freq-domain = <&cpufreq_hw 0>; 147 148 l2_500: l2-cache { 149 compatible = "cache"; 150 cache-level = <2>; 151 cache-unified; 152 next-level-cache = <&l3_0>; 153 }; 154 }; 155 156 cpu6: cpu@600 { 157 device_type = "cpu"; 158 compatible = "arm,cortex-a76"; 159 reg = <0x0 0x600>; 160 enable-method = "psci"; 161 power-domains = <&cpu_pd6>; 162 power-domain-names = "psci"; 163 capacity-dmips-mhz = <1740>; 164 dynamic-power-coefficient = <404>; 165 next-level-cache = <&l2_600>; 166 clocks = <&cpufreq_hw 1>; 167 qcom,freq-domain = <&cpufreq_hw 1>; 168 #cooling-cells = <2>; 169 170 l2_600: l2-cache { 171 compatible = "cache"; 172 cache-level = <2>; 173 cache-unified; 174 next-level-cache = <&l3_0>; 175 }; 176 }; 177 178 cpu7: cpu@700 { 179 device_type = "cpu"; 180 compatible = "arm,cortex-a76"; 181 reg = <0x0 0x700>; 182 enable-method = "psci"; 183 power-domains = <&cpu_pd7>; 184 power-domain-names = "psci"; 185 capacity-dmips-mhz = <1740>; 186 dynamic-power-coefficient = <404>; 187 next-level-cache = <&l2_700>; 188 clocks = <&cpufreq_hw 1>; 189 qcom,freq-domain = <&cpufreq_hw 1>; 190 191 l2_700: l2-cache { 192 compatible = "cache"; 193 cache-level = <2>; 194 cache-unified; 195 next-level-cache = <&l3_0>; 196 }; 197 }; 198 199 cpu-map { 200 cluster0 { 201 core0 { 202 cpu = <&cpu0>; 203 }; 204 205 core1 { 206 cpu = <&cpu1>; 207 }; 208 209 core2 { 210 cpu = <&cpu2>; 211 }; 212 213 core3 { 214 cpu = <&cpu3>; 215 }; 216 217 core4 { 218 cpu = <&cpu4>; 219 }; 220 221 core5 { 222 cpu = <&cpu5>; 223 }; 224 225 core6 { 226 cpu = <&cpu6>; 227 }; 228 229 core7 { 230 cpu = <&cpu7>; 231 }; 232 }; 233 }; 234 235 l3_0: l3-cache { 236 compatible = "cache"; 237 cache-level = <3>; 238 cache-unified; 239 }; 240 }; 241 242 dummy_eud: dummy-sink { 243 compatible = "arm,coresight-dummy-sink"; 244 245 in-ports { 246 port { 247 eud_in: endpoint { 248 remote-endpoint = <&replicator_swao_out1>; 249 }; 250 }; 251 }; 252 }; 253 254 idle-states { 255 entry-method = "psci"; 256 257 little_cpu_sleep_0: cpu-sleep-0-0 { 258 compatible = "arm,idle-state"; 259 idle-state-name = "silver-power-collapse"; 260 arm,psci-suspend-param = <0x40000003>; 261 entry-latency-us = <549>; 262 exit-latency-us = <901>; 263 min-residency-us = <1774>; 264 local-timer-stop; 265 }; 266 267 little_cpu_sleep_1: cpu-sleep-0-1 { 268 compatible = "arm,idle-state"; 269 idle-state-name = "silver-rail-power-collapse"; 270 arm,psci-suspend-param = <0x40000004>; 271 entry-latency-us = <702>; 272 exit-latency-us = <915>; 273 min-residency-us = <4001>; 274 local-timer-stop; 275 }; 276 277 big_cpu_sleep_0: cpu-sleep-1-0 { 278 compatible = "arm,idle-state"; 279 idle-state-name = "gold-power-collapse"; 280 arm,psci-suspend-param = <0x40000003>; 281 entry-latency-us = <523>; 282 exit-latency-us = <1244>; 283 min-residency-us = <2207>; 284 local-timer-stop; 285 }; 286 287 big_cpu_sleep_1: cpu-sleep-1-1 { 288 compatible = "arm,idle-state"; 289 idle-state-name = "gold-rail-power-collapse"; 290 arm,psci-suspend-param = <0x40000004>; 291 entry-latency-us = <526>; 292 exit-latency-us = <1854>; 293 min-residency-us = <5555>; 294 local-timer-stop; 295 }; 296 }; 297 298 domain-idle-states { 299 cluster_sleep_0: cluster-sleep-0 { 300 compatible = "domain-idle-state"; 301 arm,psci-suspend-param = <0x41000044>; 302 entry-latency-us = <2752>; 303 exit-latency-us = <3048>; 304 min-residency-us = <6118>; 305 }; 306 307 cluster_sleep_1: cluster-sleep-1 { 308 compatible = "domain-idle-state"; 309 arm,psci-suspend-param = <0x41001344>; 310 entry-latency-us = <3263>; 311 exit-latency-us = <4562>; 312 min-residency-us = <8467>; 313 }; 314 315 cluster_sleep_2: cluster-sleep-2 { 316 compatible = "domain-idle-state"; 317 arm,psci-suspend-param = <0x4100b344>; 318 entry-latency-us = <3638>; 319 exit-latency-us = <6562>; 320 min-residency-us = <9826>; 321 }; 322 }; 323 324 memory@80000000 { 325 device_type = "memory"; 326 /* We expect the bootloader to fill in the size */ 327 reg = <0 0x80000000 0 0>; 328 }; 329 330 firmware { 331 scm { 332 compatible = "qcom,scm-qcs615", "qcom,scm"; 333 qcom,dload-mode = <&tcsr 0x13000>; 334 }; 335 }; 336 337 camnoc_virt: interconnect-0 { 338 compatible = "qcom,qcs615-camnoc-virt"; 339 #interconnect-cells = <2>; 340 qcom,bcm-voters = <&apps_bcm_voter>; 341 }; 342 343 ipa_virt: interconnect-1 { 344 compatible = "qcom,qcs615-ipa-virt"; 345 #interconnect-cells = <2>; 346 qcom,bcm-voters = <&apps_bcm_voter>; 347 }; 348 349 mc_virt: interconnect-2 { 350 compatible = "qcom,qcs615-mc-virt"; 351 #interconnect-cells = <2>; 352 qcom,bcm-voters = <&apps_bcm_voter>; 353 }; 354 355 smp2p-adsp { 356 compatible = "qcom,smp2p"; 357 qcom,smem = <443>, <429>; 358 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 359 /* On this platform, bit 26 (normally SLPI) is repurposed for ADSP */ 360 mboxes = <&apss_shared 26>; 361 362 qcom,local-pid = <0>; 363 qcom,remote-pid = <2>; 364 365 adsp_smp2p_out: master-kernel { 366 qcom,entry-name = "master-kernel"; 367 #qcom,smem-state-cells = <1>; 368 }; 369 370 adsp_smp2p_in: slave-kernel { 371 qcom,entry-name = "slave-kernel"; 372 interrupt-controller; 373 #interrupt-cells = <2>; 374 }; 375 }; 376 377 smp2p-cdsp { 378 compatible = "qcom,smp2p"; 379 qcom,smem = <94>, <432>; 380 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 381 mboxes = <&apss_shared 6>; 382 383 qcom,local-pid = <0>; 384 qcom,remote-pid = <5>; 385 386 cdsp_smp2p_out: master-kernel { 387 qcom,entry-name = "master-kernel"; 388 #qcom,smem-state-cells = <1>; 389 }; 390 391 cdsp_smp2p_in: slave-kernel { 392 qcom,entry-name = "slave-kernel"; 393 interrupt-controller; 394 #interrupt-cells = <2>; 395 }; 396 397 }; 398 399 qup_opp_table: opp-table-qup { 400 compatible = "operating-points-v2"; 401 opp-shared; 402 403 opp-75000000 { 404 opp-hz = /bits/ 64 <75000000>; 405 required-opps = <&rpmhpd_opp_low_svs>; 406 }; 407 408 opp-100000000 { 409 opp-hz = /bits/ 64 <100000000>; 410 required-opps = <&rpmhpd_opp_svs>; 411 }; 412 413 opp-128000000 { 414 opp-hz = /bits/ 64 <128000000>; 415 required-opps = <&rpmhpd_opp_nom>; 416 }; 417 }; 418 419 psci { 420 compatible = "arm,psci-1.0"; 421 method = "smc"; 422 423 cpu_pd0: power-domain-cpu0 { 424 #power-domain-cells = <0>; 425 power-domains = <&cluster_pd>; 426 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 427 }; 428 429 cpu_pd1: power-domain-cpu1 { 430 #power-domain-cells = <0>; 431 power-domains = <&cluster_pd>; 432 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 433 }; 434 435 cpu_pd2: power-domain-cpu2 { 436 #power-domain-cells = <0>; 437 power-domains = <&cluster_pd>; 438 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 439 }; 440 441 cpu_pd3: power-domain-cpu3 { 442 #power-domain-cells = <0>; 443 power-domains = <&cluster_pd>; 444 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 445 }; 446 447 cpu_pd4: power-domain-cpu4 { 448 #power-domain-cells = <0>; 449 power-domains = <&cluster_pd>; 450 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 451 }; 452 453 cpu_pd5: power-domain-cpu5 { 454 #power-domain-cells = <0>; 455 power-domains = <&cluster_pd>; 456 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 457 }; 458 459 cpu_pd6: power-domain-cpu6 { 460 #power-domain-cells = <0>; 461 power-domains = <&cluster_pd>; 462 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 463 }; 464 465 cpu_pd7: power-domain-cpu7 { 466 #power-domain-cells = <0>; 467 power-domains = <&cluster_pd>; 468 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 469 }; 470 471 cluster_pd: power-domain-cluster { 472 #power-domain-cells = <0>; 473 domain-idle-states = <&cluster_sleep_0 474 &cluster_sleep_1 475 &cluster_sleep_2>; 476 }; 477 }; 478 479 reserved-memory { 480 #address-cells = <2>; 481 #size-cells = <2>; 482 ranges; 483 484 aop_cmd_db_mem: aop-cmd-db@85f20000 { 485 compatible = "qcom,cmd-db"; 486 reg = <0x0 0x85f20000 0x0 0x20000>; 487 no-map; 488 }; 489 490 smem_region: smem@86000000 { 491 compatible = "qcom,smem"; 492 reg = <0x0 0x86000000 0x0 0x200000>; 493 no-map; 494 hwlocks = <&tcsr_mutex 3>; 495 }; 496 497 pil_video_mem: pil-video@93400000 { 498 reg = <0x0 0x93400000 0x0 0x500000>; 499 no-map; 500 }; 501 502 rproc_cdsp_mem: rproc-cdsp@93b00000 { 503 reg = <0x0 0x93b00000 0x0 0x1e00000>; 504 no-map; 505 }; 506 507 rproc_adsp_mem: rproc-adsp@95900000 { 508 reg = <0x0 0x95900000 0x0 0x1e00000>; 509 no-map; 510 }; 511 }; 512 513 soc: soc@0 { 514 compatible = "simple-bus"; 515 ranges = <0 0 0 0 0x10 0>; 516 dma-ranges = <0 0 0 0 0x10 0>; 517 #address-cells = <2>; 518 #size-cells = <2>; 519 520 gcc: clock-controller@100000 { 521 compatible = "qcom,qcs615-gcc"; 522 reg = <0 0x00100000 0 0x1f0000>; 523 clocks = <&rpmhcc RPMH_CXO_CLK>, 524 <&rpmhcc RPMH_CXO_CLK_A>, 525 <&sleep_clk>; 526 527 #clock-cells = <1>; 528 #reset-cells = <1>; 529 #power-domain-cells = <1>; 530 }; 531 532 qfprom: efuse@780000 { 533 compatible = "qcom,qcs615-qfprom", "qcom,qfprom"; 534 reg = <0x0 0x00780000 0x0 0x7000>; 535 #address-cells = <1>; 536 #size-cells = <1>; 537 538 qusb2_hstx_trim: hstx-trim@1f8 { 539 reg = <0x1fb 0x1>; 540 bits = <1 4>; 541 }; 542 }; 543 544 rng@793000 { 545 compatible = "qcom,qcs615-trng", "qcom,trng"; 546 reg = <0x0 0x00793000 0x0 0x1000>; 547 }; 548 549 sdhc_1: mmc@7c4000 { 550 compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5"; 551 reg = <0x0 0x007c4000 0x0 0x1000>, 552 <0x0 0x007c5000 0x0 0x1000>, 553 <0x0 0x007c8000 0x0 0x8000>; 554 reg-names = "hc", 555 "cqhci", 556 "ice"; 557 558 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 560 interrupt-names = "hc_irq", 561 "pwr_irq"; 562 563 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 564 <&gcc GCC_SDCC1_APPS_CLK>, 565 <&rpmhcc RPMH_CXO_CLK>, 566 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 567 clock-names = "iface", 568 "core", 569 "xo", 570 "ice"; 571 572 resets = <&gcc GCC_SDCC1_BCR>; 573 574 power-domains = <&rpmhpd RPMHPD_CX>; 575 operating-points-v2 = <&sdhc1_opp_table>; 576 iommus = <&apps_smmu 0x02c0 0x0>; 577 interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS 578 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 579 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 580 &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 581 interconnect-names = "sdhc-ddr", 582 "cpu-sdhc"; 583 584 qcom,dll-config = <0x000f642c>; 585 qcom,ddr-config = <0x80040868>; 586 supports-cqe; 587 dma-coherent; 588 589 status = "disabled"; 590 591 sdhc1_opp_table: opp-table { 592 compatible = "operating-points-v2"; 593 594 opp-50000000 { 595 opp-hz = /bits/ 64 <50000000>; 596 required-opps = <&rpmhpd_opp_low_svs>; 597 }; 598 599 opp-100000000 { 600 opp-hz = /bits/ 64 <100000000>; 601 required-opps = <&rpmhpd_opp_svs>; 602 }; 603 604 opp-200000000 { 605 opp-hz = /bits/ 64 <200000000>; 606 required-opps = <&rpmhpd_opp_svs_l1>; 607 }; 608 609 opp-384000000 { 610 opp-hz = /bits/ 64 <384000000>; 611 required-opps = <&rpmhpd_opp_nom>; 612 }; 613 }; 614 }; 615 616 gpi_dma0: dma-controller@800000 { 617 compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma"; 618 reg = <0x0 0x800000 0x0 0x60000>; 619 #dma-cells = <3>; 620 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; 628 dma-channels = <8>; 629 dma-channel-mask = <0xf>; 630 iommus = <&apps_smmu 0xd6 0x0>; 631 status = "disabled"; 632 }; 633 634 qupv3_id_0: geniqup@8c0000 { 635 compatible = "qcom,geni-se-qup"; 636 reg = <0x0 0x008c0000 0x0 0x6000>; 637 ranges; 638 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 639 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 640 clock-names = "m-ahb", 641 "s-ahb"; 642 iommus = <&apps_smmu 0xc3 0x0>; 643 #address-cells = <2>; 644 #size-cells = <2>; 645 status = "disabled"; 646 647 uart0: serial@880000 { 648 compatible = "qcom,geni-debug-uart"; 649 reg = <0x0 0x00880000 0x0 0x4000>; 650 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 651 clock-names = "se"; 652 pinctrl-0 = <&qup_uart0_tx>, <&qup_uart0_rx>; 653 pinctrl-names = "default"; 654 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 655 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 656 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 657 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 658 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 659 interconnect-names = "qup-core", 660 "qup-config"; 661 power-domains = <&rpmhpd RPMHPD_CX>; 662 operating-points-v2 = <&qup_opp_table>; 663 status = "disabled"; 664 }; 665 666 i2c1: i2c@884000 { 667 compatible = "qcom,geni-i2c"; 668 reg = <0x0 0x884000 0x0 0x4000>; 669 #address-cells = <1>; 670 #size-cells = <0>; 671 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 672 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 673 clock-names = "se"; 674 pinctrl-0 = <&qup_i2c1_data_clk>; 675 pinctrl-names = "default"; 676 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 677 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 678 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 679 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 680 <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 681 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 682 interconnect-names = "qup-core", 683 "qup-config", 684 "qup-memory"; 685 power-domains = <&rpmhpd RPMHPD_CX>; 686 required-opps = <&rpmhpd_opp_low_svs>; 687 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 688 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 689 dma-names = "tx", 690 "rx"; 691 status = "disabled"; 692 }; 693 694 i2c2: i2c@888000 { 695 compatible = "qcom,geni-i2c"; 696 reg = <0x0 0x888000 0x0 0x4000>; 697 #address-cells = <1>; 698 #size-cells = <0>; 699 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 701 clock-names = "se"; 702 pinctrl-0 = <&qup_i2c2_data_clk>; 703 pinctrl-names = "default"; 704 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 705 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 706 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 707 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 708 <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 709 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 710 interconnect-names = "qup-core", 711 "qup-config", 712 "qup-memory"; 713 power-domains = <&rpmhpd RPMHPD_CX>; 714 required-opps = <&rpmhpd_opp_low_svs>; 715 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 716 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 717 dma-names = "tx", 718 "rx"; 719 status = "disabled"; 720 }; 721 722 spi2: spi@888000 { 723 compatible = "qcom,geni-spi"; 724 reg = <0x0 0x00888000 0x0 0x4000>; 725 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 726 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 727 clock-names = "se"; 728 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 729 pinctrl-names = "default"; 730 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 731 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 732 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 733 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 734 interconnect-names = "qup-core", 735 "qup-config"; 736 power-domains = <&rpmhpd RPMHPD_CX>; 737 operating-points-v2 = <&qup_opp_table>; 738 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 739 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 740 dma-names = "tx", 741 "rx"; 742 #address-cells = <1>; 743 #size-cells = <0>; 744 status = "disabled"; 745 }; 746 747 uart2: serial@888000 { 748 compatible = "qcom,geni-uart"; 749 reg = <0x0 0x00888000 0x0 0x4000>; 750 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 751 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 752 clock-names = "se"; 753 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, 754 <&qup_uart2_tx>, <&qup_uart2_rx>; 755 pinctrl-names = "default"; 756 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 757 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 758 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 759 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 760 interconnect-names = "qup-core", 761 "qup-config"; 762 power-domains = <&rpmhpd RPMHPD_CX>; 763 operating-points-v2 = <&qup_opp_table>; 764 status = "disabled"; 765 }; 766 767 i2c3: i2c@88c000 { 768 compatible = "qcom,geni-i2c"; 769 reg = <0x0 0x88c000 0x0 0x4000>; 770 #address-cells = <1>; 771 #size-cells = <0>; 772 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 773 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 774 clock-names = "se"; 775 pinctrl-0 = <&qup_i2c3_data_clk>; 776 pinctrl-names = "default"; 777 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 778 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 779 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 780 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 781 <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 782 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 783 interconnect-names = "qup-core", 784 "qup-config", 785 "qup-memory"; 786 power-domains = <&rpmhpd RPMHPD_CX>; 787 required-opps = <&rpmhpd_opp_low_svs>; 788 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 789 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 790 dma-names = "tx", 791 "rx"; 792 status = "disabled"; 793 }; 794 }; 795 796 gpi_dma1: dma-controller@a00000 { 797 compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma"; 798 reg = <0x0 0xa00000 0x0 0x60000>; 799 #dma-cells = <3>; 800 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 801 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 802 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 803 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 804 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 805 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 806 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>; 808 dma-channels = <8>; 809 dma-channel-mask = <0xf>; 810 iommus = <&apps_smmu 0x376 0x0>; 811 status = "disabled"; 812 }; 813 814 qupv3_id_1: geniqup@ac0000 { 815 compatible = "qcom,geni-se-qup"; 816 reg = <0x0 0xac0000 0x0 0x2000>; 817 ranges; 818 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 819 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 820 clock-names = "m-ahb", 821 "s-ahb"; 822 iommus = <&apps_smmu 0x363 0x0>; 823 #address-cells = <2>; 824 #size-cells = <2>; 825 status = "disabled"; 826 827 i2c4: i2c@a80000 { 828 compatible = "qcom,geni-i2c"; 829 reg = <0x0 0xa80000 0x0 0x4000>; 830 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 831 clock-names = "se"; 832 pinctrl-0 = <&qup_i2c4_data_clk>; 833 pinctrl-names = "default"; 834 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 835 #address-cells = <1>; 836 #size-cells = <0>; 837 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 838 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 839 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 840 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 841 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 842 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 843 interconnect-names = "qup-core", 844 "qup-config", 845 "qup-memory"; 846 power-domains = <&rpmhpd RPMHPD_CX>; 847 required-opps = <&rpmhpd_opp_low_svs>; 848 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 849 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 850 dma-names = "tx", 851 "rx"; 852 status = "disabled"; 853 }; 854 855 spi4: spi@a80000 { 856 compatible = "qcom,geni-spi"; 857 reg = <0x0 0xa80000 0x0 0x4000>; 858 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 859 clock-names = "se"; 860 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 861 pinctrl-names = "default"; 862 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 863 #address-cells = <1>; 864 #size-cells = <0>; 865 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 866 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 867 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 868 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 869 interconnect-names = "qup-core", 870 "qup-config"; 871 power-domains = <&rpmhpd RPMHPD_CX>; 872 operating-points-v2 = <&qup_opp_table>; 873 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 874 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 875 dma-names = "tx", 876 "rx"; 877 status = "disabled"; 878 }; 879 880 uart4: serial@a80000 { 881 compatible = "qcom,geni-uart"; 882 reg = <0x0 0xa80000 0x0 0x4000>; 883 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 884 clock-names = "se"; 885 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, 886 <&qup_uart4_tx>, <&qup_uart4_rx>; 887 pinctrl-names = "default"; 888 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 889 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 890 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 891 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 892 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 893 interconnect-names = "qup-core", 894 "qup-config"; 895 power-domains = <&rpmhpd RPMHPD_CX>; 896 operating-points-v2 = <&qup_opp_table>; 897 status = "disabled"; 898 }; 899 900 i2c5: i2c@a84000 { 901 compatible = "qcom,geni-i2c"; 902 reg = <0x0 0xa84000 0x0 0x4000>; 903 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 904 clock-names = "se"; 905 pinctrl-0 = <&qup_i2c5_data_clk>; 906 pinctrl-names = "default"; 907 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 908 #address-cells = <1>; 909 #size-cells = <0>; 910 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 911 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 912 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 913 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 914 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 915 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 916 interconnect-names = "qup-core", 917 "qup-config", 918 "qup-memory"; 919 power-domains = <&rpmhpd RPMHPD_CX>; 920 required-opps = <&rpmhpd_opp_low_svs>; 921 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 922 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 923 dma-names = "tx", 924 "rx"; 925 status = "disabled"; 926 }; 927 928 i2c6: i2c@a88000 { 929 compatible = "qcom,geni-i2c"; 930 reg = <0x0 0xa88000 0x0 0x4000>; 931 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 932 clock-names = "se"; 933 pinctrl-0 = <&qup_i2c6_data_clk>; 934 pinctrl-names = "default"; 935 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 936 #address-cells = <1>; 937 #size-cells = <0>; 938 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 939 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 940 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 941 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 942 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 943 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 944 interconnect-names = "qup-core", 945 "qup-config", 946 "qup-memory"; 947 power-domains = <&rpmhpd RPMHPD_CX>; 948 required-opps = <&rpmhpd_opp_low_svs>; 949 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 950 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 951 dma-names = "tx", 952 "rx"; 953 status = "disabled"; 954 }; 955 956 spi6: spi@a88000 { 957 compatible = "qcom,geni-spi"; 958 reg = <0x0 0xa88000 0x0 0x4000>; 959 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 960 clock-names = "se"; 961 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 962 pinctrl-names = "default"; 963 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 964 #address-cells = <1>; 965 #size-cells = <0>; 966 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 967 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 968 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 969 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 970 interconnect-names = "qup-core", 971 "qup-config"; 972 power-domains = <&rpmhpd RPMHPD_CX>; 973 operating-points-v2 = <&qup_opp_table>; 974 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 975 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 976 dma-names = "tx", 977 "rx"; 978 status = "disabled"; 979 }; 980 981 uart6: serial@a88000 { 982 compatible = "qcom,geni-uart"; 983 reg = <0x0 0xa88000 0x0 0x4000>; 984 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 985 clock-names = "se"; 986 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, 987 <&qup_uart6_tx>, <&qup_uart6_rx>; 988 pinctrl-names = "default"; 989 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 990 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 991 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 992 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 993 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 994 interconnect-names = "qup-core", 995 "qup-config"; 996 power-domains = <&rpmhpd RPMHPD_CX>; 997 operating-points-v2 = <&qup_opp_table>; 998 status = "disabled"; 999 }; 1000 1001 i2c7: i2c@a8c000 { 1002 compatible = "qcom,geni-i2c"; 1003 reg = <0x0 0xa8c000 0x0 0x4000>; 1004 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1005 clock-names = "se"; 1006 pinctrl-0 = <&qup_i2c7_data_clk>; 1007 pinctrl-names = "default"; 1008 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1009 #address-cells = <1>; 1010 #size-cells = <0>; 1011 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1012 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1013 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1014 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1015 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1016 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1017 interconnect-names = "qup-core", 1018 "qup-config", 1019 "qup-memory"; 1020 power-domains = <&rpmhpd RPMHPD_CX>; 1021 required-opps = <&rpmhpd_opp_low_svs>; 1022 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1023 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1024 dma-names = "tx", 1025 "rx"; 1026 status = "disabled"; 1027 }; 1028 1029 spi7: spi@a8c000 { 1030 compatible = "qcom,geni-spi"; 1031 reg = <0x0 0xa8c000 0x0 0x4000>; 1032 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1033 clock-names = "se"; 1034 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1035 pinctrl-names = "default"; 1036 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1037 #address-cells = <1>; 1038 #size-cells = <0>; 1039 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1040 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1041 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1042 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1043 interconnect-names = "qup-core", 1044 "qup-config"; 1045 power-domains = <&rpmhpd RPMHPD_CX>; 1046 operating-points-v2 = <&qup_opp_table>; 1047 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1048 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1049 dma-names = "tx", 1050 "rx"; 1051 status = "disabled"; 1052 }; 1053 1054 uart7: serial@a8c000 { 1055 compatible = "qcom,geni-uart"; 1056 reg = <0x0 0xa8c000 0x0 0x4000>; 1057 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1058 clock-names = "se"; 1059 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, 1060 <&qup_uart7_tx>, <&qup_uart7_rx>; 1061 pinctrl-names = "default"; 1062 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1063 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1064 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1065 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1066 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1067 interconnect-names = "qup-core", 1068 "qup-config"; 1069 power-domains = <&rpmhpd RPMHPD_CX>; 1070 operating-points-v2 = <&qup_opp_table>; 1071 status = "disabled"; 1072 }; 1073 }; 1074 1075 config_noc: interconnect@1500000 { 1076 reg = <0x0 0x01500000 0x0 0x5080>; 1077 compatible = "qcom,qcs615-config-noc"; 1078 #interconnect-cells = <2>; 1079 qcom,bcm-voters = <&apps_bcm_voter>; 1080 }; 1081 1082 system_noc: interconnect@1620000 { 1083 reg = <0x0 0x01620000 0x0 0x1f300>; 1084 compatible = "qcom,qcs615-system-noc"; 1085 #interconnect-cells = <2>; 1086 qcom,bcm-voters = <&apps_bcm_voter>; 1087 }; 1088 1089 aggre1_noc: interconnect@1700000 { 1090 reg = <0x0 0x01700000 0x0 0x3f200>; 1091 compatible = "qcom,qcs615-aggre1-noc"; 1092 #interconnect-cells = <2>; 1093 qcom,bcm-voters = <&apps_bcm_voter>; 1094 }; 1095 1096 mmss_noc: interconnect@1740000 { 1097 reg = <0x0 0x01740000 0x0 0x1c100>; 1098 compatible = "qcom,qcs615-mmss-noc"; 1099 #interconnect-cells = <2>; 1100 qcom,bcm-voters = <&apps_bcm_voter>; 1101 }; 1102 1103 pcie: pcie@1c08000 { 1104 device_type = "pci"; 1105 compatible = "qcom,pcie-qcs615", "qcom,pcie-sm8150"; 1106 reg = <0x0 0x01c08000 0x0 0x3000>, 1107 <0x0 0x40000000 0x0 0xf1d>, 1108 <0x0 0x40000f20 0x0 0xa8>, 1109 <0x0 0x40001000 0x0 0x1000>, 1110 <0x0 0x40100000 0x0 0x100000>, 1111 <0x0 0x01c0b000 0x0 0x1000>; 1112 reg-names = "parf", 1113 "dbi", 1114 "elbi", 1115 "atu", 1116 "config", 1117 "mhi"; 1118 #address-cells = <3>; 1119 #size-cells = <2>; 1120 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1121 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1122 bus-range = <0x00 0xff>; 1123 1124 dma-coherent; 1125 1126 linux,pci-domain = <0>; 1127 num-lanes = <1>; 1128 1129 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1130 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1131 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1132 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1133 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1134 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1135 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1136 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1137 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1138 interrupt-names = "msi0", 1139 "msi1", 1140 "msi2", 1141 "msi3", 1142 "msi4", 1143 "msi5", 1144 "msi6", 1145 "msi7", 1146 "global"; 1147 1148 #interrupt-cells = <1>; 1149 interrupt-map-mask = <0 0 0 0x7>; 1150 interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1151 <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1152 <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1153 <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1154 1155 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1156 <&gcc GCC_PCIE_0_AUX_CLK>, 1157 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1158 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1159 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1160 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 1161 clock-names = "pipe", 1162 "aux", 1163 "cfg", 1164 "bus_master", 1165 "bus_slave", 1166 "slave_q2a"; 1167 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 1168 assigned-clock-rates = <19200000>; 1169 1170 interconnects = <&aggre1_noc MASTER_PCIE QCOM_ICC_TAG_ALWAYS 1171 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1172 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1173 &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 1174 interconnect-names = "pcie-mem", "cpu-pcie"; 1175 1176 iommu-map = <0x0 &apps_smmu 0x400 0x1>, 1177 <0x100 &apps_smmu 0x401 0x1>; 1178 1179 resets = <&gcc GCC_PCIE_0_BCR>; 1180 reset-names = "pci"; 1181 1182 power-domains = <&gcc PCIE_0_GDSC>; 1183 1184 phys = <&pcie_phy>; 1185 phy-names = "pciephy"; 1186 1187 max-link-speed = <2>; 1188 1189 operating-points-v2 = <&pcie_opp_table>; 1190 1191 status = "disabled"; 1192 1193 pcie_opp_table: opp-table { 1194 compatible = "operating-points-v2"; 1195 1196 /* GEN 1 x1 */ 1197 opp-2500000 { 1198 opp-hz = /bits/ 64 <2500000>; 1199 required-opps = <&rpmhpd_opp_low_svs>; 1200 opp-peak-kBps = <250000 1>; 1201 }; 1202 1203 /* GEN 2 x1 */ 1204 opp-5000000 { 1205 opp-hz = /bits/ 64 <5000000>; 1206 required-opps = <&rpmhpd_opp_low_svs>; 1207 opp-peak-kBps = <500000 1>; 1208 }; 1209 }; 1210 1211 pcie_port0: pcie@0 { 1212 device_type = "pci"; 1213 reg = <0x0 0x0 0x0 0x0 0x0>; 1214 #address-cells = <3>; 1215 #size-cells = <2>; 1216 ranges; 1217 bus-range = <0x01 0xff>; 1218 }; 1219 }; 1220 1221 pcie_phy: phy@1c0e000 { 1222 compatible = "qcom,qcs615-qmp-gen3x1-pcie-phy"; 1223 reg = <0x0 0x01c0e000 0x0 0x1000>; 1224 1225 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1226 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1227 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1228 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, 1229 <&gcc GCC_PCIE_0_PIPE_CLK>; 1230 clock-names = "aux", 1231 "cfg_ahb", 1232 "ref", 1233 "refgen", 1234 "pipe"; 1235 1236 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1237 reset-names = "phy"; 1238 1239 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1240 assigned-clock-rates = <100000000>; 1241 1242 #clock-cells = <0>; 1243 clock-output-names = "pcie_0_pipe_clk"; 1244 1245 #phy-cells = <0>; 1246 1247 status = "disabled"; 1248 }; 1249 1250 ufs_mem_hc: ufshc@1d84000 { 1251 compatible = "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 1252 reg = <0x0 0x01d84000 0x0 0x3000>, 1253 <0x0 0x01d90000 0x0 0x8000>; 1254 reg-names = "std", 1255 "ice"; 1256 1257 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1258 1259 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1260 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1261 <&gcc GCC_UFS_PHY_AHB_CLK>, 1262 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1263 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, 1264 <&rpmhcc RPMH_CXO_CLK>, 1265 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1266 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; 1267 clock-names = "core_clk", 1268 "bus_aggr_clk", 1269 "iface_clk", 1270 "core_clk_unipro", 1271 "ref_clk", 1272 "tx_lane0_sync_clk", 1273 "rx_lane0_sync_clk", 1274 "ice_core_clk"; 1275 1276 resets = <&gcc GCC_UFS_PHY_BCR>; 1277 reset-names = "rst"; 1278 1279 operating-points-v2 = <&ufs_opp_table>; 1280 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 1281 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1282 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1283 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 1284 interconnect-names = "ufs-ddr", 1285 "cpu-ufs"; 1286 1287 power-domains = <&gcc UFS_PHY_GDSC>; 1288 1289 iommus = <&apps_smmu 0x300 0x0>; 1290 dma-coherent; 1291 1292 lanes-per-direction = <1>; 1293 1294 phys = <&ufs_mem_phy>; 1295 phy-names = "ufsphy"; 1296 1297 #reset-cells = <1>; 1298 1299 status = "disabled"; 1300 1301 ufs_opp_table: opp-table { 1302 compatible = "operating-points-v2"; 1303 1304 opp-50000000 { 1305 opp-hz = /bits/ 64 <50000000>, 1306 /bits/ 64 <0>, 1307 /bits/ 64 <0>, 1308 /bits/ 64 <37500000>, 1309 /bits/ 64 <0>, 1310 /bits/ 64 <0>, 1311 /bits/ 64 <0>, 1312 /bits/ 64 <75000000>; 1313 required-opps = <&rpmhpd_opp_low_svs>; 1314 }; 1315 1316 opp-100000000 { 1317 opp-hz = /bits/ 64 <100000000>, 1318 /bits/ 64 <0>, 1319 /bits/ 64 <0>, 1320 /bits/ 64 <75000000>, 1321 /bits/ 64 <0>, 1322 /bits/ 64 <0>, 1323 /bits/ 64 <0>, 1324 /bits/ 64 <150000000>; 1325 required-opps = <&rpmhpd_opp_svs>; 1326 }; 1327 1328 opp-200000000 { 1329 opp-hz = /bits/ 64 <200000000>, 1330 /bits/ 64 <0>, 1331 /bits/ 64 <0>, 1332 /bits/ 64 <150000000>, 1333 /bits/ 64 <0>, 1334 /bits/ 64 <0>, 1335 /bits/ 64 <0>, 1336 /bits/ 64 <300000000>; 1337 required-opps = <&rpmhpd_opp_nom>; 1338 }; 1339 }; 1340 }; 1341 1342 ufs_mem_phy: phy@1d87000 { 1343 compatible = "qcom,qcs615-qmp-ufs-phy", "qcom,sm6115-qmp-ufs-phy"; 1344 reg = <0x0 0x01d87000 0x0 0xe00>; 1345 clocks = <&rpmhcc RPMH_CXO_CLK>, 1346 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1347 <&gcc GCC_UFS_MEM_CLKREF_CLK>; 1348 clock-names = "ref", 1349 "ref_aux", 1350 "qref"; 1351 1352 power-domains = <&gcc UFS_PHY_GDSC>; 1353 1354 resets = <&ufs_mem_hc 0>; 1355 reset-names = "ufsphy"; 1356 1357 #clock-cells = <1>; 1358 #phy-cells = <0>; 1359 1360 status = "disabled"; 1361 }; 1362 1363 cryptobam: dma-controller@1dc4000 { 1364 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1365 reg = <0x0 0x01dc4000 0x0 0x24000>; 1366 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1367 #dma-cells = <1>; 1368 qcom,ee = <0>; 1369 qcom,controlled-remotely; 1370 num-channels = <16>; 1371 qcom,num-ees = <4>; 1372 iommus = <&apps_smmu 0x0104 0x0011>; 1373 }; 1374 1375 crypto: crypto@1dfa000 { 1376 compatible = "qcom,qcs615-qce", "qcom,sm8150-qce", "qcom,qce"; 1377 reg = <0x0 0x01dfa000 0x0 0x6000>; 1378 dmas = <&cryptobam 4>, <&cryptobam 5>; 1379 dma-names = "rx", "tx"; 1380 iommus = <&apps_smmu 0x0104 0x0011>; 1381 interconnects = <&aggre1_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 1382 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1383 interconnect-names = "memory"; 1384 }; 1385 1386 tcsr_mutex: hwlock@1f40000 { 1387 compatible = "qcom,tcsr-mutex"; 1388 reg = <0x0 0x01f40000 0x0 0x20000>; 1389 #hwlock-cells = <1>; 1390 }; 1391 1392 tcsr: syscon@1fc0000 { 1393 compatible = "qcom,qcs615-tcsr", "syscon"; 1394 reg = <0x0 0x01fc0000 0x0 0x30000>; 1395 }; 1396 1397 tlmm: pinctrl@3100000 { 1398 compatible = "qcom,qcs615-tlmm"; 1399 reg = <0x0 0x03100000 0x0 0x300000>, 1400 <0x0 0x03500000 0x0 0x300000>, 1401 <0x0 0x03d00000 0x0 0x300000>; 1402 reg-names = "east", 1403 "west", 1404 "south"; 1405 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1406 gpio-ranges = <&tlmm 0 0 124>; 1407 gpio-controller; 1408 #gpio-cells = <2>; 1409 interrupt-controller; 1410 #interrupt-cells = <2>; 1411 wakeup-parent = <&pdc>; 1412 1413 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 1414 pins = "gpio4", "gpio5"; 1415 function = "qup0"; 1416 1417 }; 1418 1419 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 1420 pins = "gpio0", "gpio1"; 1421 function = "qup0"; 1422 }; 1423 1424 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 1425 pins = "gpio18", "gpio19"; 1426 function = "qup0"; 1427 }; 1428 1429 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 1430 pins = "gpio20", "gpio21"; 1431 function = "qup1"; 1432 }; 1433 1434 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 1435 pins = "gpio14", "gpio15"; 1436 function = "qup1"; 1437 }; 1438 1439 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 1440 pins = "gpio6", "gpio7"; 1441 function = "qup1"; 1442 }; 1443 1444 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 1445 pins = "gpio10", "gpio11"; 1446 function = "qup1"; 1447 }; 1448 1449 qup_spi2_data_clk: qup-spi2-data-clk-state { 1450 pins = "gpio0", "gpio1", "gpio2"; 1451 function = "qup0"; 1452 }; 1453 1454 qup_spi2_cs: qup-spi2-cs-state { 1455 pins = "gpio3"; 1456 function = "qup0"; 1457 }; 1458 1459 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 1460 pins = "gpio3"; 1461 function = "gpio"; 1462 }; 1463 1464 qup_spi4_data_clk: qup-spi4-data-clk-state { 1465 pins = "gpio20", "gpio21", "gpio22"; 1466 function = "qup1"; 1467 }; 1468 1469 qup_spi4_cs: qup-spi4-cs-state { 1470 pins = "gpio23"; 1471 function = "qup1"; 1472 }; 1473 1474 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 1475 pins = "gpio23"; 1476 function = "gpio"; 1477 }; 1478 1479 qup_spi6_data_clk: qup-spi6-data-clk-state { 1480 pins = "gpio6", "gpio7", "gpio8"; 1481 function = "qup1"; 1482 }; 1483 1484 qup_spi6_cs: qup-spi6-cs-state { 1485 pins = "gpio9"; 1486 function = "qup1"; 1487 }; 1488 1489 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 1490 pins = "gpio9"; 1491 function = "gpio"; 1492 }; 1493 1494 qup_spi7_data_clk: qup-spi7-data-clk-state { 1495 pins = "gpio10", "gpio11", "gpio12"; 1496 function = "qup1"; 1497 }; 1498 1499 qup_spi7_cs: qup-spi7-cs-state { 1500 pins = "gpio13"; 1501 function = "qup1"; 1502 }; 1503 1504 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 1505 pins = "gpio13"; 1506 function = "gpio"; 1507 }; 1508 1509 qup_uart0_tx: qup-uart0-tx-state { 1510 pins = "gpio16"; 1511 function = "qup0"; 1512 }; 1513 1514 qup_uart0_rx: qup-uart0-rx-state { 1515 pins = "gpio17"; 1516 function = "qup0"; 1517 }; 1518 1519 qup_uart2_cts: qup-uart2-cts-state { 1520 pins = "gpio0"; 1521 function = "qup0"; 1522 }; 1523 1524 qup_uart2_rts: qup-uart2-rts-state { 1525 pins = "gpio1"; 1526 function = "qup0"; 1527 }; 1528 1529 qup_uart2_tx: qup-uart2-tx-state { 1530 pins = "gpio2"; 1531 function = "qup0"; 1532 }; 1533 1534 qup_uart2_rx: qup-uart2-rx-state { 1535 pins = "gpio3"; 1536 function = "qup0"; 1537 }; 1538 1539 qup_uart4_cts: qup-uart4-cts-state { 1540 pins = "gpio20"; 1541 function = "qup1"; 1542 }; 1543 1544 qup_uart4_rts: qup-uart4-rts-state { 1545 pins = "gpio21"; 1546 function = "qup1"; 1547 }; 1548 1549 qup_uart4_tx: qup-uart4-tx-state { 1550 pins = "gpio22"; 1551 function = "qup1"; 1552 }; 1553 1554 qup_uart4_rx: qup-uart4-rx-state { 1555 pins = "gpio23"; 1556 function = "qup1"; 1557 }; 1558 1559 qup_uart6_cts: qup-uart6-cts-state { 1560 pins = "gpio6"; 1561 function = "qup1"; 1562 }; 1563 1564 qup_uart6_rts: qup-uart6-rts-state { 1565 pins = "gpio7"; 1566 function = "qup1"; 1567 }; 1568 1569 qup_uart6_tx: qup-uart6-tx-state { 1570 pins = "gpio8"; 1571 function = "qup1"; 1572 }; 1573 1574 qup_uart6_rx: qup-uart6-rx-state { 1575 pins = "gpio9"; 1576 function = "qup1"; 1577 }; 1578 1579 qup_uart7_cts: qup-uart7-cts-state { 1580 pins = "gpio10"; 1581 function = "qup1"; 1582 }; 1583 1584 qup_uart7_rts: qup-uart7-rts-state { 1585 pins = "gpio11"; 1586 function = "qup1"; 1587 }; 1588 1589 qup_uart7_tx: qup-uart7-tx-state { 1590 pins = "gpio12"; 1591 function = "qup1"; 1592 }; 1593 1594 qup_uart7_rx: qup-uart7-rx-state { 1595 pins = "gpio13"; 1596 function = "qup1"; 1597 }; 1598 1599 sdc1_state_on: sdc1-on-state { 1600 clk-pins { 1601 pins = "sdc1_clk"; 1602 bias-disable; 1603 drive-strength = <16>; 1604 }; 1605 1606 cmd-pins { 1607 pins = "sdc1_cmd"; 1608 bias-pull-up; 1609 drive-strength = <10>; 1610 }; 1611 1612 data-pins { 1613 pins = "sdc1_data"; 1614 bias-pull-up; 1615 drive-strength = <10>; 1616 }; 1617 1618 rclk-pins { 1619 pins = "sdc1_rclk"; 1620 bias-pull-down; 1621 }; 1622 }; 1623 1624 sdc1_state_off: sdc1-off-state { 1625 clk-pins { 1626 pins = "sdc1_clk"; 1627 bias-disable; 1628 drive-strength = <2>; 1629 }; 1630 1631 cmd-pins { 1632 pins = "sdc1_cmd"; 1633 bias-pull-up; 1634 drive-strength = <2>; 1635 }; 1636 1637 data-pins { 1638 pins = "sdc1_data"; 1639 bias-pull-up; 1640 drive-strength = <2>; 1641 }; 1642 1643 rclk-pins { 1644 pins = "sdc1_rclk"; 1645 bias-pull-down; 1646 }; 1647 }; 1648 1649 sdc2_state_on: sdc2-on-state { 1650 clk-pins { 1651 pins = "sdc2_clk"; 1652 bias-disable; 1653 drive-strength = <16>; 1654 }; 1655 1656 cmd-pins { 1657 pins = "sdc2_cmd"; 1658 bias-pull-up; 1659 drive-strength = <10>; 1660 }; 1661 1662 data-pins { 1663 pins = "sdc2_data"; 1664 bias-pull-up; 1665 drive-strength = <10>; 1666 }; 1667 }; 1668 1669 sdc2_state_off: sdc2-off-state { 1670 clk-pins { 1671 pins = "sdc2_clk"; 1672 bias-disable; 1673 drive-strength = <2>; 1674 }; 1675 1676 cmd-pins { 1677 pins = "sdc2_cmd"; 1678 bias-pull-up; 1679 drive-strength = <2>; 1680 }; 1681 1682 data-pins { 1683 pins = "sdc2_data"; 1684 bias-pull-up; 1685 drive-strength = <2>; 1686 }; 1687 }; 1688 }; 1689 1690 gpucc: clock-controller@5090000 { 1691 compatible = "qcom,qcs615-gpucc"; 1692 reg = <0 0x05090000 0 0x9000>; 1693 1694 clocks = <&rpmhcc RPMH_CXO_CLK>, 1695 <&gcc GPLL0>, 1696 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1697 1698 #clock-cells = <1>; 1699 #reset-cells = <1>; 1700 #power-domain-cells = <1>; 1701 }; 1702 1703 stm@6002000 { 1704 compatible = "arm,coresight-stm", "arm,primecell"; 1705 reg = <0x0 0x06002000 0x0 0x1000>, 1706 <0x0 0x16280000 0x0 0x180000>; 1707 reg-names = "stm-base", 1708 "stm-stimulus-base"; 1709 1710 clocks = <&aoss_qmp>; 1711 clock-names = "apb_pclk"; 1712 1713 out-ports { 1714 port { 1715 stm_out: endpoint { 1716 remote-endpoint = <&funnel_in0_in7>; 1717 }; 1718 }; 1719 }; 1720 }; 1721 1722 tpda@6004000 { 1723 compatible = "qcom,coresight-tpda", "arm,primecell"; 1724 reg = <0x0 0x06004000 0x0 0x1000>; 1725 1726 clocks = <&aoss_qmp>; 1727 clock-names = "apb_pclk"; 1728 1729 in-ports { 1730 #address-cells = <1>; 1731 #size-cells = <0>; 1732 1733 port@0 { 1734 reg = <0>; 1735 1736 tpda_qdss_in0: endpoint { 1737 remote-endpoint = <&tpdm_center_out>; 1738 }; 1739 }; 1740 1741 port@4 { 1742 reg = <4>; 1743 1744 tpda_qdss_in4: endpoint { 1745 remote-endpoint = <&funnel_monaq_out>; 1746 }; 1747 }; 1748 1749 port@5 { 1750 reg = <5>; 1751 1752 tpda_qdss_in5: endpoint { 1753 remote-endpoint = <&funnel_ddr_0_out>; 1754 }; 1755 }; 1756 1757 port@6 { 1758 reg = <6>; 1759 1760 tpda_qdss_in6: endpoint { 1761 remote-endpoint = <&funnel_turing_out>; 1762 }; 1763 }; 1764 1765 port@7 { 1766 reg = <7>; 1767 1768 tpda_qdss_in7: endpoint { 1769 remote-endpoint = <&tpdm_vsense_out>; 1770 }; 1771 }; 1772 1773 port@8 { 1774 reg = <8>; 1775 1776 tpda_qdss_in8: endpoint { 1777 remote-endpoint = <&tpdm_dcc_out>; 1778 }; 1779 }; 1780 1781 port@9 { 1782 reg = <9>; 1783 1784 tpda_qdss_in9: endpoint { 1785 remote-endpoint = <&tpdm_prng_out>; 1786 }; 1787 }; 1788 1789 port@b { 1790 reg = <11>; 1791 1792 tpda_qdss_in11: endpoint { 1793 remote-endpoint = <&tpdm_qm_out>; 1794 }; 1795 }; 1796 1797 port@c { 1798 reg = <12>; 1799 1800 tpda_qdss_in12: endpoint { 1801 remote-endpoint = <&tpdm_west_out>; 1802 }; 1803 }; 1804 1805 port@d { 1806 reg = <13>; 1807 1808 tpda_qdss_in13: endpoint { 1809 remote-endpoint = <&tpdm_pimem_out>; 1810 }; 1811 }; 1812 }; 1813 1814 out-ports { 1815 port { 1816 tpda_qdss_out: endpoint { 1817 remote-endpoint = <&funnel_qatb_in>; 1818 }; 1819 }; 1820 }; 1821 }; 1822 1823 funnel@6005000 { 1824 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1825 reg = <0x0 0x06005000 0x0 0x1000>; 1826 1827 clocks = <&aoss_qmp>; 1828 clock-names = "apb_pclk"; 1829 1830 in-ports { 1831 port { 1832 funnel_qatb_in: endpoint { 1833 remote-endpoint = <&tpda_qdss_out>; 1834 }; 1835 }; 1836 }; 1837 1838 out-ports { 1839 port { 1840 funnel_qatb_out: endpoint { 1841 remote-endpoint = <&funnel_in0_in6>; 1842 }; 1843 }; 1844 }; 1845 }; 1846 1847 cti@6010000 { 1848 compatible = "arm,coresight-cti", "arm,primecell"; 1849 reg = <0x0 0x06010000 0x0 0x1000>; 1850 1851 clocks = <&aoss_qmp>; 1852 clock-names = "apb_pclk"; 1853 }; 1854 1855 cti@6011000 { 1856 compatible = "arm,coresight-cti", "arm,primecell"; 1857 reg = <0x0 0x06011000 0x0 0x1000>; 1858 1859 clocks = <&aoss_qmp>; 1860 clock-names = "apb_pclk"; 1861 }; 1862 1863 cti@6012000 { 1864 compatible = "arm,coresight-cti", "arm,primecell"; 1865 reg = <0x0 0x06012000 0x0 0x1000>; 1866 1867 clocks = <&aoss_qmp>; 1868 clock-names = "apb_pclk"; 1869 }; 1870 1871 cti@6013000 { 1872 compatible = "arm,coresight-cti", "arm,primecell"; 1873 reg = <0x0 0x06013000 0x0 0x1000>; 1874 1875 clocks = <&aoss_qmp>; 1876 clock-names = "apb_pclk"; 1877 }; 1878 1879 cti@6014000 { 1880 compatible = "arm,coresight-cti", "arm,primecell"; 1881 reg = <0x0 0x06014000 0x0 0x1000>; 1882 1883 clocks = <&aoss_qmp>; 1884 clock-names = "apb_pclk"; 1885 }; 1886 1887 cti@6015000 { 1888 compatible = "arm,coresight-cti", "arm,primecell"; 1889 reg = <0x0 0x06015000 0x0 0x1000>; 1890 1891 clocks = <&aoss_qmp>; 1892 clock-names = "apb_pclk"; 1893 }; 1894 1895 cti@6016000 { 1896 compatible = "arm,coresight-cti", "arm,primecell"; 1897 reg = <0x0 0x06016000 0x0 0x1000>; 1898 1899 clocks = <&aoss_qmp>; 1900 clock-names = "apb_pclk"; 1901 }; 1902 1903 cti@6017000 { 1904 compatible = "arm,coresight-cti", "arm,primecell"; 1905 reg = <0x0 0x06017000 0x0 0x1000>; 1906 1907 clocks = <&aoss_qmp>; 1908 clock-names = "apb_pclk"; 1909 }; 1910 1911 cti@6018000 { 1912 compatible = "arm,coresight-cti", "arm,primecell"; 1913 reg = <0x0 0x06018000 0x0 0x1000>; 1914 1915 clocks = <&aoss_qmp>; 1916 clock-names = "apb_pclk"; 1917 }; 1918 1919 cti@6019000 { 1920 compatible = "arm,coresight-cti", "arm,primecell"; 1921 reg = <0x0 0x06019000 0x0 0x1000>; 1922 1923 clocks = <&aoss_qmp>; 1924 clock-names = "apb_pclk"; 1925 }; 1926 1927 cti@601a000 { 1928 compatible = "arm,coresight-cti", "arm,primecell"; 1929 reg = <0x0 0x0601a000 0x0 0x1000>; 1930 1931 clocks = <&aoss_qmp>; 1932 clock-names = "apb_pclk"; 1933 }; 1934 1935 cti@601b000 { 1936 compatible = "arm,coresight-cti", "arm,primecell"; 1937 reg = <0x0 0x0601b000 0x0 0x1000>; 1938 1939 clocks = <&aoss_qmp>; 1940 clock-names = "apb_pclk"; 1941 }; 1942 1943 cti@601c000 { 1944 compatible = "arm,coresight-cti", "arm,primecell"; 1945 reg = <0x0 0x0601c000 0x0 0x1000>; 1946 1947 clocks = <&aoss_qmp>; 1948 clock-names = "apb_pclk"; 1949 }; 1950 1951 cti@601d000 { 1952 compatible = "arm,coresight-cti", "arm,primecell"; 1953 reg = <0x0 0x0601d000 0x0 0x1000>; 1954 1955 clocks = <&aoss_qmp>; 1956 clock-names = "apb_pclk"; 1957 }; 1958 1959 cti@601e000 { 1960 compatible = "arm,coresight-cti", "arm,primecell"; 1961 reg = <0x0 0x0601e000 0x0 0x1000>; 1962 1963 clocks = <&aoss_qmp>; 1964 clock-names = "apb_pclk"; 1965 }; 1966 1967 cti@601f000 { 1968 compatible = "arm,coresight-cti", "arm,primecell"; 1969 reg = <0x0 0x0601f000 0x0 0x1000>; 1970 1971 clocks = <&aoss_qmp>; 1972 clock-names = "apb_pclk"; 1973 }; 1974 1975 funnel@6041000 { 1976 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1977 reg = <0x0 0x06041000 0x0 0x1000>; 1978 1979 clocks = <&aoss_qmp>; 1980 clock-names = "apb_pclk"; 1981 1982 in-ports { 1983 #address-cells = <1>; 1984 #size-cells = <0>; 1985 1986 port@6 { 1987 reg = <6>; 1988 1989 funnel_in0_in6: endpoint { 1990 remote-endpoint = <&funnel_qatb_out>; 1991 }; 1992 }; 1993 1994 port@7 { 1995 reg = <7>; 1996 1997 funnel_in0_in7: endpoint { 1998 remote-endpoint = <&stm_out>; 1999 }; 2000 }; 2001 }; 2002 2003 out-ports { 2004 port { 2005 funnel_in0_out: endpoint { 2006 remote-endpoint = <&funnel_merg_in0>; 2007 }; 2008 }; 2009 }; 2010 }; 2011 2012 funnel@6042000 { 2013 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2014 reg = <0x0 0x06042000 0x0 0x1000>; 2015 2016 clocks = <&aoss_qmp>; 2017 clock-names = "apb_pclk"; 2018 2019 in-ports { 2020 #address-cells = <1>; 2021 #size-cells = <0>; 2022 2023 port@3 { 2024 reg = <3>; 2025 2026 funnel_in1_in3: endpoint { 2027 remote-endpoint = <&replicator_swao_out0>; 2028 }; 2029 }; 2030 2031 port@4 { 2032 reg = <4>; 2033 2034 funnel_in1_in4: endpoint { 2035 remote-endpoint = <&tpdm_wcss_out>; 2036 }; 2037 }; 2038 2039 port@7 { 2040 reg = <7>; 2041 2042 funnel_in1_in7: endpoint { 2043 remote-endpoint = <&funnel_apss_merg_out>; 2044 }; 2045 }; 2046 }; 2047 2048 out-ports { 2049 port { 2050 funnel_in1_out: endpoint { 2051 remote-endpoint = <&funnel_merg_in1>; 2052 }; 2053 }; 2054 }; 2055 }; 2056 2057 funnel@6045000 { 2058 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2059 reg = <0x0 0x06045000 0x0 0x1000>; 2060 2061 clocks = <&aoss_qmp>; 2062 clock-names = "apb_pclk"; 2063 2064 in-ports { 2065 #address-cells = <1>; 2066 #size-cells = <0>; 2067 2068 port@0 { 2069 reg = <0>; 2070 2071 funnel_merg_in0: endpoint { 2072 remote-endpoint = <&funnel_in0_out>; 2073 }; 2074 }; 2075 2076 port@1 { 2077 reg = <1>; 2078 2079 funnel_merg_in1: endpoint { 2080 remote-endpoint = <&funnel_in1_out>; 2081 }; 2082 }; 2083 }; 2084 2085 out-ports { 2086 port { 2087 funnel_merg_out: endpoint { 2088 remote-endpoint = <&tmc_etf_in>; 2089 }; 2090 }; 2091 }; 2092 }; 2093 2094 replicator@6046000 { 2095 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2096 reg = <0x0 0x06046000 0x0 0x1000>; 2097 2098 clocks = <&aoss_qmp>; 2099 clock-names = "apb_pclk"; 2100 2101 in-ports { 2102 port { 2103 replicator0_in: endpoint { 2104 remote-endpoint = <&tmc_etf_out>; 2105 }; 2106 }; 2107 }; 2108 2109 out-ports { 2110 #address-cells = <1>; 2111 #size-cells = <0>; 2112 2113 port@1 { 2114 reg = <1>; 2115 2116 replicator0_out1: endpoint { 2117 remote-endpoint = <&replicator1_in>; 2118 }; 2119 }; 2120 }; 2121 }; 2122 2123 tmc@6047000 { 2124 compatible = "arm,coresight-tmc", "arm,primecell"; 2125 reg = <0x0 0x06047000 0x0 0x1000>; 2126 2127 clocks = <&aoss_qmp>; 2128 clock-names = "apb_pclk"; 2129 2130 in-ports { 2131 port { 2132 tmc_etf_in: endpoint { 2133 remote-endpoint = <&funnel_merg_out>; 2134 }; 2135 }; 2136 }; 2137 2138 out-ports { 2139 port { 2140 tmc_etf_out: endpoint { 2141 remote-endpoint = <&replicator0_in>; 2142 }; 2143 }; 2144 }; 2145 }; 2146 2147 replicator@604a000 { 2148 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2149 reg = <0x0 0x0604a000 0x0 0x1000>; 2150 2151 clocks = <&aoss_qmp>; 2152 clock-names = "apb_pclk"; 2153 status = "disabled"; 2154 2155 in-ports { 2156 port { 2157 replicator1_in: endpoint { 2158 remote-endpoint = <&replicator0_out1>; 2159 }; 2160 }; 2161 }; 2162 2163 out-ports { 2164 port { 2165 replicator1_out: endpoint { 2166 remote-endpoint = <&funnel_swao_in6>; 2167 }; 2168 }; 2169 }; 2170 }; 2171 2172 cti@683b000 { 2173 compatible = "arm,coresight-cti", "arm,primecell"; 2174 reg = <0x0 0x0683b000 0x0 0x1000>; 2175 2176 clocks = <&aoss_qmp>; 2177 clock-names = "apb_pclk"; 2178 }; 2179 2180 tpdm@6840000 { 2181 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2182 reg = <0x0 0x06840000 0x0 0x1000>; 2183 2184 clocks = <&aoss_qmp>; 2185 clock-names = "apb_pclk"; 2186 2187 qcom,cmb-element-bits = <64>; 2188 qcom,cmb-msrs-num = <32>; 2189 status = "disabled"; 2190 2191 out-ports { 2192 port { 2193 tpdm_vsense_out: endpoint { 2194 remote-endpoint = <&tpda_qdss_in7>; 2195 }; 2196 }; 2197 }; 2198 }; 2199 2200 tpdm@684c000 { 2201 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2202 reg = <0x0 0x0684c000 0x0 0x1000>; 2203 2204 clocks = <&aoss_qmp>; 2205 clock-names = "apb_pclk"; 2206 2207 qcom,cmb-element-bits = <32>; 2208 qcom,cmb-msrs-num = <32>; 2209 2210 out-ports { 2211 port { 2212 tpdm_prng_out: endpoint { 2213 remote-endpoint = <&tpda_qdss_in9>; 2214 }; 2215 }; 2216 }; 2217 }; 2218 2219 tpdm@6850000 { 2220 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2221 reg = <0x0 0x06850000 0x0 0x1000>; 2222 2223 clocks = <&aoss_qmp>; 2224 clock-names = "apb_pclk"; 2225 2226 qcom,cmb-element-bits = <64>; 2227 qcom,cmb-msrs-num = <32>; 2228 qcom,dsb-element-bits = <32>; 2229 qcom,dsb-msrs-num = <32>; 2230 2231 out-ports { 2232 port { 2233 tpdm_pimem_out: endpoint { 2234 remote-endpoint = <&tpda_qdss_in13>; 2235 }; 2236 }; 2237 }; 2238 }; 2239 2240 tpdm@6860000 { 2241 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2242 reg = <0x0 0x06860000 0x0 0x1000>; 2243 2244 clocks = <&aoss_qmp>; 2245 clock-names = "apb_pclk"; 2246 2247 qcom,dsb-element-bits = <32>; 2248 qcom,dsb-msrs-num = <32>; 2249 2250 out-ports { 2251 port { 2252 tpdm_turing_out: endpoint { 2253 remote-endpoint = <&funnel_turing_in>; 2254 }; 2255 }; 2256 }; 2257 }; 2258 2259 funnel@6861000 { 2260 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2261 reg = <0x0 0x06861000 0x0 0x1000>; 2262 2263 clocks = <&aoss_qmp>; 2264 clock-names = "apb_pclk"; 2265 2266 in-ports { 2267 port { 2268 funnel_turing_in: endpoint { 2269 remote-endpoint = <&tpdm_turing_out>; 2270 }; 2271 }; 2272 }; 2273 2274 out-ports { 2275 port { 2276 funnel_turing_out: endpoint { 2277 remote-endpoint = <&tpda_qdss_in6>; 2278 }; 2279 }; 2280 }; 2281 }; 2282 2283 cti@6867000 { 2284 compatible = "arm,coresight-cti", "arm,primecell"; 2285 reg = <0x0 0x06867000 0x0 0x1000>; 2286 2287 clocks = <&aoss_qmp>; 2288 clock-names = "apb_pclk"; 2289 }; 2290 2291 tpdm@6870000 { 2292 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2293 reg = <0x0 0x06870000 0x0 0x1000>; 2294 2295 clocks = <&aoss_qmp>; 2296 clock-names = "apb_pclk"; 2297 2298 qcom,cmb-element-bits = <32>; 2299 qcom,cmb-msrs-num = <32>; 2300 status = "disabled"; 2301 2302 out-ports { 2303 port { 2304 tpdm_dcc_out: endpoint { 2305 remote-endpoint = <&tpda_qdss_in8>; 2306 }; 2307 }; 2308 }; 2309 }; 2310 2311 tpdm@699c000 { 2312 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2313 reg = <0x0 0x0699c000 0x0 0x1000>; 2314 2315 clocks = <&aoss_qmp>; 2316 clock-names = "apb_pclk"; 2317 2318 qcom,cmb-element-bits = <32>; 2319 qcom,cmb-msrs-num = <32>; 2320 qcom,dsb-element-bits = <32>; 2321 qcom,dsb-msrs-num = <32>; 2322 status = "disabled"; 2323 2324 out-ports { 2325 port { 2326 tpdm_wcss_out: endpoint { 2327 remote-endpoint = <&funnel_in1_in4>; 2328 }; 2329 }; 2330 }; 2331 }; 2332 2333 tpdm@69c0000 { 2334 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2335 reg = <0x0 0x069c0000 0x0 0x1000>; 2336 2337 clocks = <&aoss_qmp>; 2338 clock-names = "apb_pclk"; 2339 2340 qcom,dsb-element-bits = <32>; 2341 qcom,dsb-msrs-num = <32>; 2342 2343 out-ports { 2344 port { 2345 tpdm_monaq_out: endpoint { 2346 remote-endpoint = <&funnel_monaq_in>; 2347 }; 2348 }; 2349 }; 2350 }; 2351 2352 funnel@69c3000 { 2353 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2354 reg = <0x0 0x069c3000 0x0 0x1000>; 2355 2356 clocks = <&aoss_qmp>; 2357 clock-names = "apb_pclk"; 2358 2359 in-ports { 2360 port { 2361 funnel_monaq_in: endpoint { 2362 remote-endpoint = <&tpdm_monaq_out>; 2363 }; 2364 }; 2365 }; 2366 2367 out-ports { 2368 port { 2369 funnel_monaq_out: endpoint { 2370 remote-endpoint = <&tpda_qdss_in4>; 2371 }; 2372 }; 2373 }; 2374 }; 2375 2376 tpdm@69d0000 { 2377 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2378 reg = <0x0 0x069d0000 0x0 0x1000>; 2379 2380 clocks = <&aoss_qmp>; 2381 clock-names = "apb_pclk"; 2382 2383 qcom,dsb-element-bits = <32>; 2384 qcom,dsb-msrs-num = <32>; 2385 status = "disabled"; 2386 2387 out-ports { 2388 port { 2389 tpdm_qm_out: endpoint { 2390 remote-endpoint = <&tpda_qdss_in11>; 2391 }; 2392 }; 2393 }; 2394 }; 2395 2396 tpdm@6a00000 { 2397 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2398 reg = <0x0 0x06a00000 0x0 0x1000>; 2399 2400 clocks = <&aoss_qmp>; 2401 clock-names = "apb_pclk"; 2402 2403 qcom,dsb-element-bits = <32>; 2404 qcom,dsb-msrs-num = <32>; 2405 status = "disabled"; 2406 2407 out-ports { 2408 port { 2409 tpdm_ddr_out: endpoint { 2410 remote-endpoint = <&funnel_ddr_0_in>; 2411 }; 2412 }; 2413 }; 2414 }; 2415 2416 cti@6a02000 { 2417 compatible = "arm,coresight-cti", "arm,primecell"; 2418 reg = <0x0 0x06a02000 0x0 0x1000>; 2419 2420 clocks = <&aoss_qmp>; 2421 clock-names = "apb_pclk"; 2422 }; 2423 2424 cti@6a03000 { 2425 compatible = "arm,coresight-cti", "arm,primecell"; 2426 reg = <0x0 0x06a03000 0x0 0x1000>; 2427 2428 clocks = <&aoss_qmp>; 2429 clock-names = "apb_pclk"; 2430 }; 2431 2432 cti@6a10000 { 2433 compatible = "arm,coresight-cti", "arm,primecell"; 2434 reg = <0x0 0x06a10000 0x0 0x1000>; 2435 2436 clocks = <&aoss_qmp>; 2437 clock-names = "apb_pclk"; 2438 }; 2439 2440 cti@6a11000 { 2441 compatible = "arm,coresight-cti", "arm,primecell"; 2442 reg = <0x0 0x06a11000 0x0 0x1000>; 2443 2444 clocks = <&aoss_qmp>; 2445 clock-names = "apb_pclk"; 2446 }; 2447 2448 funnel@6a05000 { 2449 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2450 reg = <0x0 0x06a05000 0x0 0x1000>; 2451 2452 clocks = <&aoss_qmp>; 2453 clock-names = "apb_pclk"; 2454 2455 in-ports { 2456 port { 2457 funnel_ddr_0_in: endpoint { 2458 remote-endpoint = <&tpdm_ddr_out>; 2459 }; 2460 }; 2461 }; 2462 2463 out-ports { 2464 port { 2465 funnel_ddr_0_out: endpoint { 2466 remote-endpoint = <&tpda_qdss_in5>; 2467 }; 2468 }; 2469 }; 2470 }; 2471 2472 tpda@6b01000 { 2473 compatible = "qcom,coresight-tpda", "arm,primecell"; 2474 reg = <0x0 0x06b01000 0x0 0x1000>; 2475 2476 clocks = <&aoss_qmp>; 2477 clock-names = "apb_pclk"; 2478 2479 in-ports { 2480 #address-cells = <1>; 2481 #size-cells = <0>; 2482 2483 port@0 { 2484 reg = <0>; 2485 2486 tpda_swao_in0: endpoint { 2487 remote-endpoint = <&tpdm_swao0_out>; 2488 }; 2489 }; 2490 2491 port@1 { 2492 reg = <1>; 2493 2494 tpda_swao_in1: endpoint { 2495 remote-endpoint = <&tpdm_swao1_out>; 2496 }; 2497 2498 }; 2499 }; 2500 2501 out-ports { 2502 port { 2503 tpda_swao_out: endpoint { 2504 remote-endpoint = <&funnel_swao_in7>; 2505 }; 2506 }; 2507 }; 2508 }; 2509 2510 tpdm@6b02000 { 2511 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2512 reg = <0x0 0x06b02000 0x0 0x1000>; 2513 2514 clocks = <&aoss_qmp>; 2515 clock-names = "apb_pclk"; 2516 2517 qcom,cmb-element-bits = <64>; 2518 qcom,cmb-msrs-num = <32>; 2519 status = "disabled"; 2520 2521 out-ports { 2522 port { 2523 tpdm_swao0_out: endpoint { 2524 remote-endpoint = <&tpda_swao_in0>; 2525 }; 2526 }; 2527 }; 2528 }; 2529 2530 tpdm@6b03000 { 2531 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2532 reg = <0x0 0x06b03000 0x0 0x1000>; 2533 2534 clocks = <&aoss_qmp>; 2535 clock-names = "apb_pclk"; 2536 2537 qcom,dsb-element-bits = <32>; 2538 qcom,dsb-msrs-num = <32>; 2539 status = "disabled"; 2540 2541 out-ports { 2542 port { 2543 tpdm_swao1_out: endpoint { 2544 remote-endpoint = <&tpda_swao_in1>; 2545 }; 2546 }; 2547 }; 2548 }; 2549 2550 cti@6b04000 { 2551 compatible = "arm,coresight-cti", "arm,primecell"; 2552 reg = <0x0 0x06b04000 0x0 0x1000>; 2553 2554 clocks = <&aoss_qmp>; 2555 clock-names = "apb_pclk"; 2556 }; 2557 2558 cti@6b05000 { 2559 compatible = "arm,coresight-cti", "arm,primecell"; 2560 reg = <0x0 0x06b05000 0x0 0x1000>; 2561 2562 clocks = <&aoss_qmp>; 2563 clock-names = "apb_pclk"; 2564 }; 2565 2566 cti@6b06000 { 2567 compatible = "arm,coresight-cti", "arm,primecell"; 2568 reg = <0x0 0x06b06000 0x0 0x1000>; 2569 2570 clocks = <&aoss_qmp>; 2571 clock-names = "apb_pclk"; 2572 }; 2573 2574 cti@6b07000 { 2575 compatible = "arm,coresight-cti", "arm,primecell"; 2576 reg = <0x0 0x06b07000 0x0 0x1000>; 2577 2578 clocks = <&aoss_qmp>; 2579 clock-names = "apb_pclk"; 2580 }; 2581 2582 funnel@6b08000 { 2583 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2584 reg = <0x0 0x06b08000 0x0 0x1000>; 2585 2586 clocks = <&aoss_qmp>; 2587 clock-names = "apb_pclk"; 2588 2589 in-ports { 2590 #address-cells = <1>; 2591 #size-cells = <0>; 2592 2593 port@6 { 2594 reg = <6>; 2595 2596 funnel_swao_in6: endpoint { 2597 remote-endpoint = <&replicator1_out>; 2598 }; 2599 }; 2600 2601 port@7 { 2602 reg = <7>; 2603 2604 funnel_swao_in7: endpoint { 2605 remote-endpoint = <&tpda_swao_out>; 2606 }; 2607 }; 2608 }; 2609 2610 out-ports { 2611 port { 2612 funnel_swao_out: endpoint { 2613 remote-endpoint = <&tmc_etf_swao_in>; 2614 }; 2615 }; 2616 }; 2617 }; 2618 2619 tmc@6b09000 { 2620 compatible = "arm,coresight-tmc", "arm,primecell"; 2621 reg = <0x0 0x06b09000 0x0 0x1000>; 2622 2623 clocks = <&aoss_qmp>; 2624 clock-names = "apb_pclk"; 2625 2626 in-ports { 2627 port { 2628 tmc_etf_swao_in: endpoint { 2629 remote-endpoint = <&funnel_swao_out>; 2630 }; 2631 }; 2632 }; 2633 2634 out-ports { 2635 port { 2636 tmc_etf_swao_out: endpoint { 2637 remote-endpoint = <&replicator_swao_in>; 2638 }; 2639 }; 2640 }; 2641 }; 2642 2643 replicator@6b0a000 { 2644 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2645 reg = <0x0 0x06b0a000 0x0 0x1000>; 2646 2647 clocks = <&aoss_qmp>; 2648 clock-names = "apb_pclk"; 2649 2650 in-ports { 2651 port { 2652 replicator_swao_in: endpoint { 2653 remote-endpoint = <&tmc_etf_swao_out>; 2654 }; 2655 }; 2656 }; 2657 2658 out-ports { 2659 #address-cells = <1>; 2660 #size-cells = <0>; 2661 2662 port@0 { 2663 reg = <0>; 2664 2665 replicator_swao_out0: endpoint { 2666 remote-endpoint = <&funnel_in1_in3>; 2667 }; 2668 }; 2669 2670 port@1 { 2671 reg = <1>; 2672 2673 replicator_swao_out1: endpoint { 2674 remote-endpoint = <&eud_in>; 2675 }; 2676 }; 2677 }; 2678 }; 2679 2680 cti@6b21000 { 2681 compatible = "arm,coresight-cti", "arm,primecell"; 2682 reg = <0x0 0x06b21000 0x0 0x1000>; 2683 2684 clocks = <&aoss_qmp>; 2685 clock-names = "apb_pclk"; 2686 }; 2687 2688 tpdm@6b48000 { 2689 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2690 reg = <0x0 0x06b48000 0x0 0x1000>; 2691 2692 clocks = <&aoss_qmp>; 2693 clock-names = "apb_pclk"; 2694 2695 qcom,dsb-element-bits = <32>; 2696 qcom,dsb-msrs-num = <32>; 2697 2698 out-ports { 2699 port { 2700 tpdm_west_out: endpoint { 2701 remote-endpoint = <&tpda_qdss_in12>; 2702 }; 2703 }; 2704 }; 2705 }; 2706 2707 cti@6c13000 { 2708 compatible = "arm,coresight-cti", "arm,primecell"; 2709 reg = <0x0 0x06c13000 0x0 0x1000>; 2710 2711 clocks = <&aoss_qmp>; 2712 clock-names = "apb_pclk"; 2713 2714 /* Not all required clocks can be enabled from the OS */ 2715 status = "fail"; 2716 }; 2717 2718 cti@6c20000 { 2719 compatible = "arm,coresight-cti", "arm,primecell"; 2720 reg = <0x0 0x06c20000 0x0 0x1000>; 2721 2722 clocks = <&aoss_qmp>; 2723 clock-names = "apb_pclk"; 2724 status = "disabled"; 2725 }; 2726 2727 tpdm@6c28000 { 2728 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2729 reg = <0x0 0x06c28000 0x0 0x1000>; 2730 2731 clocks = <&aoss_qmp>; 2732 clock-names = "apb_pclk"; 2733 2734 qcom,dsb-element-bits = <32>; 2735 qcom,dsb-msrs-num = <32>; 2736 2737 out-ports { 2738 port { 2739 tpdm_center_out: endpoint { 2740 remote-endpoint = <&tpda_qdss_in0>; 2741 }; 2742 }; 2743 }; 2744 }; 2745 2746 cti@6c29000 { 2747 compatible = "arm,coresight-cti", "arm,primecell"; 2748 reg = <0x0 0x06c29000 0x0 0x1000>; 2749 2750 clocks = <&aoss_qmp>; 2751 clock-names = "apb_pclk"; 2752 }; 2753 2754 cti@6c2a000 { 2755 compatible = "arm,coresight-cti", "arm,primecell"; 2756 reg = <0x0 0x06c2a000 0x0 0x1000>; 2757 2758 clocks = <&aoss_qmp>; 2759 clock-names = "apb_pclk"; 2760 }; 2761 2762 cti@7020000 { 2763 compatible = "arm,coresight-cti", "arm,primecell"; 2764 reg = <0x0 0x07020000 0x0 0x1000>; 2765 2766 clocks = <&aoss_qmp>; 2767 clock-names = "apb_pclk"; 2768 }; 2769 2770 etm@7040000 { 2771 compatible = "arm,primecell"; 2772 reg = <0x0 0x07040000 0x0 0x1000>; 2773 cpu = <&cpu0>; 2774 2775 clocks = <&aoss_qmp>; 2776 clock-names = "apb_pclk"; 2777 2778 arm,coresight-loses-context-with-cpu; 2779 qcom,skip-power-up; 2780 2781 out-ports { 2782 port { 2783 etm0_out: endpoint { 2784 remote-endpoint = <&funnel_apss_in0>; 2785 }; 2786 }; 2787 }; 2788 }; 2789 2790 cti@7120000 { 2791 compatible = "arm,coresight-cti", "arm,primecell"; 2792 reg = <0x0 0x07120000 0x0 0x1000>; 2793 2794 clocks = <&aoss_qmp>; 2795 clock-names = "apb_pclk"; 2796 }; 2797 2798 etm@7140000 { 2799 compatible = "arm,primecell"; 2800 reg = <0x0 0x07140000 0x0 0x1000>; 2801 cpu = <&cpu1>; 2802 2803 clocks = <&aoss_qmp>; 2804 clock-names = "apb_pclk"; 2805 2806 arm,coresight-loses-context-with-cpu; 2807 qcom,skip-power-up; 2808 2809 out-ports { 2810 port { 2811 etm1_out: endpoint { 2812 remote-endpoint = <&funnel_apss_in1>; 2813 }; 2814 }; 2815 }; 2816 }; 2817 2818 cti@7220000 { 2819 compatible = "arm,coresight-cti", "arm,primecell"; 2820 reg = <0x0 0x07220000 0x0 0x1000>; 2821 2822 clocks = <&aoss_qmp>; 2823 clock-names = "apb_pclk"; 2824 }; 2825 2826 etm@7240000 { 2827 compatible = "arm,primecell"; 2828 reg = <0x0 0x07240000 0x0 0x1000>; 2829 cpu = <&cpu2>; 2830 2831 clocks = <&aoss_qmp>; 2832 clock-names = "apb_pclk"; 2833 2834 arm,coresight-loses-context-with-cpu; 2835 qcom,skip-power-up; 2836 2837 out-ports { 2838 port { 2839 etm2_out: endpoint { 2840 remote-endpoint = <&funnel_apss_in2>; 2841 }; 2842 }; 2843 }; 2844 }; 2845 2846 cti@7320000 { 2847 compatible = "arm,coresight-cti", "arm,primecell"; 2848 reg = <0x0 0x07320000 0x0 0x1000>; 2849 2850 clocks = <&aoss_qmp>; 2851 clock-names = "apb_pclk"; 2852 }; 2853 2854 etm@7340000 { 2855 compatible = "arm,primecell"; 2856 reg = <0x0 0x07340000 0x0 0x1000>; 2857 cpu = <&cpu3>; 2858 2859 clocks = <&aoss_qmp>; 2860 clock-names = "apb_pclk"; 2861 2862 arm,coresight-loses-context-with-cpu; 2863 qcom,skip-power-up; 2864 2865 out-ports { 2866 port { 2867 etm3_out: endpoint { 2868 remote-endpoint = <&funnel_apss_in3>; 2869 }; 2870 }; 2871 }; 2872 }; 2873 2874 cti@7420000 { 2875 compatible = "arm,coresight-cti", "arm,primecell"; 2876 reg = <0x0 0x07420000 0x0 0x1000>; 2877 2878 clocks = <&aoss_qmp>; 2879 clock-names = "apb_pclk"; 2880 }; 2881 2882 etm@7440000 { 2883 compatible = "arm,primecell"; 2884 reg = <0x0 0x07440000 0x0 0x1000>; 2885 cpu = <&cpu4>; 2886 2887 clocks = <&aoss_qmp>; 2888 clock-names = "apb_pclk"; 2889 2890 arm,coresight-loses-context-with-cpu; 2891 qcom,skip-power-up; 2892 2893 out-ports { 2894 port { 2895 etm4_out: endpoint { 2896 remote-endpoint = <&funnel_apss_in4>; 2897 }; 2898 }; 2899 }; 2900 }; 2901 2902 cti@7520000 { 2903 compatible = "arm,coresight-cti", "arm,primecell"; 2904 reg = <0x0 0x07520000 0x0 0x1000>; 2905 2906 clocks = <&aoss_qmp>; 2907 clock-names = "apb_pclk"; 2908 }; 2909 2910 etm@7540000 { 2911 compatible = "arm,primecell"; 2912 reg = <0x0 0x07540000 0x0 0x1000>; 2913 cpu = <&cpu5>; 2914 2915 clocks = <&aoss_qmp>; 2916 clock-names = "apb_pclk"; 2917 2918 arm,coresight-loses-context-with-cpu; 2919 qcom,skip-power-up; 2920 2921 out-ports { 2922 port { 2923 etm5_out: endpoint { 2924 remote-endpoint = <&funnel_apss_in5>; 2925 }; 2926 }; 2927 }; 2928 }; 2929 2930 cti@7620000 { 2931 compatible = "arm,coresight-cti", "arm,primecell"; 2932 reg = <0x0 0x07620000 0x0 0x1000>; 2933 2934 clocks = <&aoss_qmp>; 2935 clock-names = "apb_pclk"; 2936 }; 2937 2938 etm@7640000 { 2939 compatible = "arm,primecell"; 2940 reg = <0x0 0x07640000 0x0 0x1000>; 2941 cpu = <&cpu6>; 2942 2943 clocks = <&aoss_qmp>; 2944 clock-names = "apb_pclk"; 2945 2946 arm,coresight-loses-context-with-cpu; 2947 qcom,skip-power-up; 2948 2949 out-ports { 2950 port { 2951 etm6_out: endpoint { 2952 remote-endpoint = <&funnel_apss_in6>; 2953 }; 2954 }; 2955 }; 2956 }; 2957 2958 cti@7720000 { 2959 compatible = "arm,coresight-cti", "arm,primecell"; 2960 reg = <0x0 0x07720000 0x0 0x1000>; 2961 2962 clocks = <&aoss_qmp>; 2963 clock-names = "apb_pclk"; 2964 }; 2965 2966 etm@7740000 { 2967 compatible = "arm,primecell"; 2968 reg = <0x0 0x07740000 0x0 0x1000>; 2969 cpu = <&cpu7>; 2970 2971 clocks = <&aoss_qmp>; 2972 clock-names = "apb_pclk"; 2973 2974 arm,coresight-loses-context-with-cpu; 2975 qcom,skip-power-up; 2976 2977 out-ports { 2978 port { 2979 etm7_out: endpoint { 2980 remote-endpoint = <&funnel_apss_in7>; 2981 }; 2982 }; 2983 }; 2984 }; 2985 2986 funnel@7800000 { 2987 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2988 reg = <0x0 0x07800000 0x0 0x1000>; 2989 2990 clocks = <&aoss_qmp>; 2991 clock-names = "apb_pclk"; 2992 2993 in-ports { 2994 #address-cells = <1>; 2995 #size-cells = <0>; 2996 2997 port@0 { 2998 reg = <0>; 2999 3000 funnel_apss_in0: endpoint { 3001 remote-endpoint = <&etm0_out>; 3002 }; 3003 }; 3004 3005 port@1 { 3006 reg = <1>; 3007 3008 funnel_apss_in1: endpoint { 3009 remote-endpoint = <&etm1_out>; 3010 }; 3011 }; 3012 3013 port@2 { 3014 reg = <2>; 3015 3016 funnel_apss_in2: endpoint { 3017 remote-endpoint = <&etm2_out>; 3018 }; 3019 }; 3020 3021 port@3 { 3022 reg = <3>; 3023 3024 funnel_apss_in3: endpoint { 3025 remote-endpoint = <&etm3_out>; 3026 }; 3027 }; 3028 3029 port@4 { 3030 reg = <4>; 3031 3032 funnel_apss_in4: endpoint { 3033 remote-endpoint = <&etm4_out>; 3034 }; 3035 }; 3036 3037 port@5 { 3038 reg = <5>; 3039 3040 funnel_apss_in5: endpoint { 3041 remote-endpoint = <&etm5_out>; 3042 }; 3043 }; 3044 3045 port@6 { 3046 reg = <6>; 3047 3048 funnel_apss_in6: endpoint { 3049 remote-endpoint = <&etm6_out>; 3050 }; 3051 }; 3052 3053 port@7 { 3054 reg = <7>; 3055 3056 funnel_apss_in7: endpoint { 3057 remote-endpoint = <&etm7_out>; 3058 }; 3059 }; 3060 }; 3061 3062 out-ports { 3063 port { 3064 funnel_apss_out: endpoint { 3065 remote-endpoint = <&funnel_apss_merg_in0>; 3066 }; 3067 }; 3068 }; 3069 }; 3070 3071 funnel@7810000 { 3072 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3073 reg = <0x0 0x07810000 0x0 0x1000>; 3074 3075 clocks = <&aoss_qmp>; 3076 clock-names = "apb_pclk"; 3077 3078 in-ports { 3079 #address-cells = <1>; 3080 #size-cells = <0>; 3081 3082 port@0 { 3083 reg = <0>; 3084 3085 funnel_apss_merg_in0: endpoint { 3086 remote-endpoint = <&funnel_apss_out>; 3087 }; 3088 }; 3089 3090 port@2 { 3091 reg = <2>; 3092 3093 funnel_apss_merg_in2: endpoint { 3094 remote-endpoint = <&tpda_olc_out>; 3095 }; 3096 }; 3097 3098 port@3 { 3099 reg = <3>; 3100 3101 funnel_apss_merg_in3: endpoint { 3102 remote-endpoint = <&tpda_llm_silver_out>; 3103 }; 3104 }; 3105 3106 port@4 { 3107 reg = <4>; 3108 3109 funnel_apss_merg_in4: endpoint { 3110 remote-endpoint = <&tpda_llm_gold_out>; 3111 }; 3112 }; 3113 3114 port@5 { 3115 reg = <5>; 3116 3117 funnel_apss_merg_in5: endpoint { 3118 remote-endpoint = <&tpda_apss_out>; 3119 }; 3120 }; 3121 }; 3122 3123 out-ports { 3124 port { 3125 funnel_apss_merg_out: endpoint { 3126 remote-endpoint = <&funnel_in1_in7>; 3127 }; 3128 }; 3129 }; 3130 }; 3131 3132 tpdm@7830000 { 3133 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3134 reg = <0x0 0x07830000 0x0 0x1000>; 3135 3136 clocks = <&aoss_qmp>; 3137 clock-names = "apb_pclk"; 3138 3139 qcom,cmb-element-bits = <64>; 3140 qcom,cmb-msrs-num = <32>; 3141 3142 out-ports { 3143 port { 3144 tpdm_olc_out: endpoint { 3145 remote-endpoint = <&tpda_olc_in>; 3146 }; 3147 }; 3148 }; 3149 }; 3150 3151 tpda@7832000 { 3152 compatible = "qcom,coresight-tpda", "arm,primecell"; 3153 reg = <0x0 0x07832000 0x0 0x1000>; 3154 3155 clocks = <&aoss_qmp>; 3156 clock-names = "apb_pclk"; 3157 3158 in-ports { 3159 port { 3160 tpda_olc_in: endpoint { 3161 remote-endpoint = <&tpdm_olc_out>; 3162 }; 3163 }; 3164 }; 3165 3166 out-ports { 3167 port { 3168 tpda_olc_out: endpoint { 3169 remote-endpoint = <&funnel_apss_merg_in2>; 3170 }; 3171 }; 3172 }; 3173 }; 3174 3175 tpdm@7860000 { 3176 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3177 reg = <0x0 0x07860000 0x0 0x1000>; 3178 3179 clocks = <&aoss_qmp>; 3180 clock-names = "apb_pclk"; 3181 3182 qcom,dsb-element-bits = <32>; 3183 qcom,dsb-msrs-num = <32>; 3184 3185 out-ports { 3186 port { 3187 tpdm_apss_out: endpoint { 3188 remote-endpoint = <&tpda_apss_in>; 3189 }; 3190 }; 3191 }; 3192 }; 3193 3194 tpda@7862000 { 3195 compatible = "qcom,coresight-tpda", "arm,primecell"; 3196 reg = <0x0 0x07862000 0x0 0x1000>; 3197 3198 clocks = <&aoss_qmp>; 3199 clock-names = "apb_pclk"; 3200 3201 in-ports { 3202 port { 3203 tpda_apss_in: endpoint { 3204 remote-endpoint = <&tpdm_apss_out>; 3205 }; 3206 }; 3207 }; 3208 3209 out-ports { 3210 port { 3211 tpda_apss_out: endpoint { 3212 remote-endpoint = <&funnel_apss_merg_in5>; 3213 }; 3214 }; 3215 }; 3216 }; 3217 3218 tpdm@78a0000 { 3219 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3220 reg = <0x0 0x078a0000 0x0 0x1000>; 3221 3222 clocks = <&aoss_qmp>; 3223 clock-names = "apb_pclk"; 3224 3225 qcom,cmb-element-bits = <32>; 3226 qcom,cmb-msrs-num = <32>; 3227 3228 out-ports { 3229 port { 3230 tpdm_llm_silver_out: endpoint { 3231 remote-endpoint = <&tpda_llm_silver_in>; 3232 }; 3233 }; 3234 }; 3235 }; 3236 3237 tpdm@78b0000 { 3238 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3239 reg = <0x0 0x078b0000 0x0 0x1000>; 3240 3241 clocks = <&aoss_qmp>; 3242 clock-names = "apb_pclk"; 3243 3244 qcom,cmb-element-bits = <32>; 3245 qcom,cmb-msrs-num = <32>; 3246 3247 out-ports { 3248 port { 3249 tpdm_llm_gold_out: endpoint { 3250 remote-endpoint = <&tpda_llm_gold_in>; 3251 }; 3252 }; 3253 }; 3254 }; 3255 3256 tpda@78c0000 { 3257 compatible = "qcom,coresight-tpda", "arm,primecell"; 3258 reg = <0x0 0x078c0000 0x0 0x1000>; 3259 3260 clocks = <&aoss_qmp>; 3261 clock-names = "apb_pclk"; 3262 3263 in-ports { 3264 port { 3265 tpda_llm_silver_in: endpoint { 3266 remote-endpoint = <&tpdm_llm_silver_out>; 3267 }; 3268 }; 3269 }; 3270 3271 out-ports { 3272 port { 3273 tpda_llm_silver_out: endpoint { 3274 remote-endpoint = <&funnel_apss_merg_in3>; 3275 }; 3276 }; 3277 }; 3278 }; 3279 3280 tpda@78d0000 { 3281 compatible = "qcom,coresight-tpda", "arm,primecell"; 3282 reg = <0x0 0x078d0000 0x0 0x1000>; 3283 3284 clocks = <&aoss_qmp>; 3285 clock-names = "apb_pclk"; 3286 3287 in-ports { 3288 port { 3289 tpda_llm_gold_in: endpoint { 3290 remote-endpoint = <&tpdm_llm_gold_out>; 3291 }; 3292 }; 3293 }; 3294 3295 out-ports { 3296 port { 3297 tpda_llm_gold_out: endpoint { 3298 remote-endpoint = <&funnel_apss_merg_in4>; 3299 }; 3300 }; 3301 }; 3302 }; 3303 3304 cti@78e0000 { 3305 compatible = "arm,coresight-cti", "arm,primecell"; 3306 reg = <0x0 0x078e0000 0x0 0x1000>; 3307 3308 clocks = <&aoss_qmp>; 3309 clock-names = "apb_pclk"; 3310 }; 3311 3312 cti@78f0000 { 3313 compatible = "arm,coresight-cti", "arm,primecell"; 3314 reg = <0x0 0x078f0000 0x0 0x1000>; 3315 3316 clocks = <&aoss_qmp>; 3317 clock-names = "apb_pclk"; 3318 }; 3319 3320 cti@7900000 { 3321 compatible = "arm,coresight-cti", "arm,primecell"; 3322 reg = <0x0 0x07900000 0x0 0x1000>; 3323 3324 clocks = <&aoss_qmp>; 3325 clock-names = "apb_pclk"; 3326 }; 3327 3328 remoteproc_cdsp: remoteproc@8300000 { 3329 compatible = "qcom,qcs615-cdsp-pas", "qcom,sm8150-cdsp-pas"; 3330 reg = <0x0 0x08300000 0x0 0x4040>; 3331 3332 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3333 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3334 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3335 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3336 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3337 interrupt-names = "wdog", 3338 "fatal", 3339 "ready", 3340 "handover", 3341 "stop-ack"; 3342 3343 clocks = <&rpmhcc RPMH_CXO_CLK>; 3344 clock-names = "xo"; 3345 3346 power-domains = <&rpmhpd RPMHPD_CX>; 3347 power-domain-names = "cx"; 3348 3349 memory-region = <&rproc_cdsp_mem>; 3350 3351 qcom,qmp = <&aoss_qmp>; 3352 3353 qcom,smem-states = <&cdsp_smp2p_out 0>; 3354 qcom,smem-state-names = "stop"; 3355 3356 status = "disabled"; 3357 3358 glink-edge { 3359 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 3360 mboxes = <&apss_shared 4>; 3361 label = "cdsp"; 3362 qcom,remote-pid = <5>; 3363 3364 fastrpc { 3365 compatible = "qcom,fastrpc"; 3366 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3367 label = "cdsp"; 3368 #address-cells = <1>; 3369 #size-cells = <0>; 3370 3371 compute-cb@1 { 3372 compatible = "qcom,fastrpc-compute-cb"; 3373 reg = <1>; 3374 iommus = <&apps_smmu 0x1081 0x0>; 3375 dma-coherent; 3376 }; 3377 3378 compute-cb@2 { 3379 compatible = "qcom,fastrpc-compute-cb"; 3380 reg = <2>; 3381 iommus = <&apps_smmu 0x1082 0x0>; 3382 dma-coherent; 3383 }; 3384 3385 compute-cb@3 { 3386 compatible = "qcom,fastrpc-compute-cb"; 3387 reg = <3>; 3388 iommus = <&apps_smmu 0x1083 0x0>; 3389 dma-coherent; 3390 }; 3391 3392 compute-cb@4 { 3393 compatible = "qcom,fastrpc-compute-cb"; 3394 reg = <4>; 3395 iommus = <&apps_smmu 0x1084 0x0>; 3396 dma-coherent; 3397 }; 3398 3399 compute-cb@5 { 3400 compatible = "qcom,fastrpc-compute-cb"; 3401 reg = <5>; 3402 iommus = <&apps_smmu 0x1085 0x0>; 3403 dma-coherent; 3404 }; 3405 3406 compute-cb@6 { 3407 compatible = "qcom,fastrpc-compute-cb"; 3408 reg = <6>; 3409 iommus = <&apps_smmu 0x1086 0x0>; 3410 dma-coherent; 3411 }; 3412 }; 3413 }; 3414 }; 3415 3416 pmu@90b6300 { 3417 compatible = "qcom,qcs615-cpu-bwmon", "qcom,sdm845-bwmon"; 3418 reg = <0x0 0x090b6300 0x0 0x600>; 3419 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3420 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3421 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 3422 3423 operating-points-v2 = <&cpu_bwmon_opp_table>; 3424 3425 cpu_bwmon_opp_table: opp-table { 3426 compatible = "operating-points-v2"; 3427 3428 opp-0 { 3429 opp-peak-kBps = <12896000>; 3430 }; 3431 3432 opp-1 { 3433 opp-peak-kBps = <14928000>; 3434 }; 3435 }; 3436 }; 3437 3438 pmu@90cd000 { 3439 compatible = "qcom,qcs615-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3440 reg = <0x0 0x090cd000 0x0 0x1000>; 3441 interrupts = <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>; 3442 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 3443 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 3444 3445 operating-points-v2 = <&llcc_bwmon_opp_table>; 3446 3447 llcc_bwmon_opp_table: opp-table { 3448 compatible = "operating-points-v2"; 3449 3450 opp-0 { 3451 opp-peak-kBps = <800000>; 3452 }; 3453 3454 opp-1 { 3455 opp-peak-kBps = <1200000>; 3456 }; 3457 3458 opp-2 { 3459 opp-peak-kBps = <1804800>; 3460 }; 3461 3462 opp-3 { 3463 opp-peak-kBps = <2188800>; 3464 }; 3465 3466 opp-4 { 3467 opp-peak-kBps = <2726400>; 3468 }; 3469 3470 opp-5 { 3471 opp-peak-kBps = <3072000>; 3472 }; 3473 3474 opp-6 { 3475 opp-peak-kBps = <4070400>; 3476 }; 3477 3478 opp-7 { 3479 opp-peak-kBps = <5414400>; 3480 }; 3481 3482 opp-8 { 3483 opp-peak-kBps = <6220800>; 3484 }; 3485 }; 3486 }; 3487 3488 sdhc_2: mmc@8804000 { 3489 compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5"; 3490 reg = <0x0 0x08804000 0x0 0x1000>; 3491 reg-names = "hc"; 3492 3493 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3494 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3495 interrupt-names = "hc_irq", 3496 "pwr_irq"; 3497 3498 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3499 <&gcc GCC_SDCC2_APPS_CLK>, 3500 <&rpmhcc RPMH_CXO_CLK>; 3501 clock-names = "iface", 3502 "core", 3503 "xo"; 3504 3505 power-domains = <&rpmhpd RPMHPD_CX>; 3506 operating-points-v2 = <&sdhc2_opp_table>; 3507 iommus = <&apps_smmu 0x02a0 0x0>; 3508 resets = <&gcc GCC_SDCC2_BCR>; 3509 interconnects = <&aggre1_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 3510 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3511 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3512 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 3513 interconnect-names = "sdhc-ddr", 3514 "cpu-sdhc"; 3515 3516 qcom,dll-config = <0x0007642c>; 3517 qcom,ddr-config = <0x80040868>; 3518 dma-coherent; 3519 3520 status = "disabled"; 3521 3522 sdhc2_opp_table: opp-table { 3523 compatible = "operating-points-v2"; 3524 3525 opp-50000000 { 3526 opp-hz = /bits/ 64 <50000000>; 3527 required-opps = <&rpmhpd_opp_low_svs>; 3528 }; 3529 3530 opp-100000000 { 3531 opp-hz = /bits/ 64 <100000000>; 3532 required-opps = <&rpmhpd_opp_svs>; 3533 }; 3534 3535 opp-202000000 { 3536 opp-hz = /bits/ 64 <202000000>; 3537 required-opps = <&rpmhpd_opp_nom>; 3538 }; 3539 }; 3540 }; 3541 3542 dc_noc: interconnect@9160000 { 3543 reg = <0x0 0x09160000 0x0 0x3200>; 3544 compatible = "qcom,qcs615-dc-noc"; 3545 #interconnect-cells = <2>; 3546 qcom,bcm-voters = <&apps_bcm_voter>; 3547 }; 3548 3549 llcc: system-cache-controller@9200000 { 3550 compatible = "qcom,qcs615-llcc"; 3551 reg = <0x0 0x09200000 0x0 0x50000>, 3552 <0x0 0x09600000 0x0 0x50000>; 3553 reg-names = "llcc0_base", 3554 "llcc_broadcast_base"; 3555 }; 3556 3557 gem_noc: interconnect@9680000 { 3558 reg = <0x0 0x09680000 0x0 0x3e200>; 3559 compatible = "qcom,qcs615-gem-noc"; 3560 #interconnect-cells = <2>; 3561 qcom,bcm-voters = <&apps_bcm_voter>; 3562 }; 3563 3564 venus: video-codec@aa00000 { 3565 compatible = "qcom,qcs615-venus", "qcom,sc7180-venus"; 3566 reg = <0x0 0x0aa00000 0x0 0x100000>; 3567 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3568 3569 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 3570 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3571 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 3572 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 3573 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 3574 clock-names = "core", 3575 "iface", 3576 "bus", 3577 "vcodec0_core", 3578 "vcodec0_bus"; 3579 3580 power-domains = <&videocc VENUS_GDSC>, 3581 <&videocc VCODEC0_GDSC>, 3582 <&rpmhpd RPMHPD_CX>; 3583 power-domain-names = "venus", 3584 "vcodec0", 3585 "cx"; 3586 3587 operating-points-v2 = <&venus_opp_table>; 3588 3589 interconnects = <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS 3590 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3591 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3592 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 3593 interconnect-names = "video-mem", 3594 "cpu-cfg"; 3595 3596 iommus = <&apps_smmu 0xe60 0x20>; 3597 3598 memory-region = <&pil_video_mem>; 3599 3600 status = "disabled"; 3601 3602 venus_opp_table: opp-table { 3603 compatible = "operating-points-v2"; 3604 3605 opp-133330000 { 3606 opp-hz = /bits/ 64 <133330000>; 3607 required-opps = <&rpmhpd_opp_low_svs>; 3608 }; 3609 3610 opp-240000000 { 3611 opp-hz = /bits/ 64 <240000000>; 3612 required-opps = <&rpmhpd_opp_svs>; 3613 }; 3614 3615 opp-300000000 { 3616 opp-hz = /bits/ 64 <300000000>; 3617 required-opps = <&rpmhpd_opp_svs_l1>; 3618 }; 3619 3620 opp-380000000 { 3621 opp-hz = /bits/ 64 <380000000>; 3622 required-opps = <&rpmhpd_opp_nom>; 3623 }; 3624 3625 opp-410000000 { 3626 opp-hz = /bits/ 64 <410000000>; 3627 required-opps = <&rpmhpd_opp_nom_l1>; 3628 }; 3629 3630 opp-460000000 { 3631 opp-hz = /bits/ 64 <460000000>; 3632 required-opps = <&rpmhpd_opp_turbo>; 3633 }; 3634 }; 3635 }; 3636 3637 videocc: clock-controller@ab00000 { 3638 compatible = "qcom,qcs615-videocc"; 3639 reg = <0 0x0ab00000 0 0x10000>; 3640 3641 clocks = <&rpmhcc RPMH_CXO_CLK>, 3642 <&sleep_clk>; 3643 3644 #clock-cells = <1>; 3645 #reset-cells = <1>; 3646 #power-domain-cells = <1>; 3647 }; 3648 3649 camcc: clock-controller@ad00000 { 3650 compatible = "qcom,qcs615-camcc"; 3651 reg = <0 0x0ad00000 0 0x10000>; 3652 3653 clocks = <&rpmhcc RPMH_CXO_CLK>; 3654 3655 #clock-cells = <1>; 3656 #reset-cells = <1>; 3657 #power-domain-cells = <1>; 3658 }; 3659 3660 dispcc: clock-controller@af00000 { 3661 compatible = "qcom,qcs615-dispcc"; 3662 reg = <0 0x0af00000 0 0x20000>; 3663 3664 clocks = <&rpmhcc RPMH_CXO_CLK>, 3665 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 3666 <0>, 3667 <0>, 3668 <0>, 3669 <0>, 3670 <0>; 3671 3672 #clock-cells = <1>; 3673 #reset-cells = <1>; 3674 #power-domain-cells = <1>; 3675 }; 3676 3677 pdc: interrupt-controller@b220000 { 3678 compatible = "qcom,qcs615-pdc", "qcom,pdc"; 3679 reg = <0x0 0x0b220000 0x0 0x30000>, 3680 <0x0 0x17c000f0 0x0 0x64>; 3681 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; 3682 interrupt-parent = <&intc>; 3683 #interrupt-cells = <2>; 3684 interrupt-controller; 3685 }; 3686 3687 aoss_qmp: power-management@c300000 { 3688 compatible = "qcom,qcs615-aoss-qmp", "qcom,aoss-qmp"; 3689 reg = <0x0 0x0c300000 0x0 0x400>; 3690 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3691 mboxes = <&apss_shared 0>; 3692 3693 #clock-cells = <0>; 3694 }; 3695 3696 sram@c3f0000 { 3697 compatible = "qcom,rpmh-stats"; 3698 reg = <0x0 0x0c3f0000 0x0 0x400>; 3699 }; 3700 3701 sram@14680000 { 3702 compatible = "qcom,qcs615-imem", "syscon", "simple-mfd"; 3703 reg = <0x0 0x14680000 0x0 0x2c000>; 3704 ranges = <0 0 0x14680000 0x2c000>; 3705 3706 #address-cells = <1>; 3707 #size-cells = <1>; 3708 3709 pil-reloc@2a94c { 3710 compatible = "qcom,pil-reloc-info"; 3711 reg = <0x2a94c 0xc8>; 3712 }; 3713 }; 3714 3715 apps_smmu: iommu@15000000 { 3716 compatible = "qcom,qcs615-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 3717 reg = <0x0 0x15000000 0x0 0x80000>; 3718 #iommu-cells = <2>; 3719 #global-interrupts = <1>; 3720 dma-coherent; 3721 3722 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3723 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 3724 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 3725 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3726 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3727 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3728 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3729 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3730 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3731 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3732 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3733 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3734 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3735 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3736 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3737 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3738 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3739 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3740 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3741 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3742 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3743 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3744 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3745 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3746 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3747 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3748 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3749 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3750 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3751 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3752 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3753 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3754 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3755 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3756 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3757 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3758 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3759 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3760 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3761 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3762 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3763 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3764 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3765 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3766 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3767 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3768 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3769 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3770 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3771 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3772 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3773 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3774 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3775 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3776 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3777 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3778 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3779 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3780 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3781 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3782 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3783 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3784 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3785 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3786 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 3787 }; 3788 3789 spmi_bus: spmi@c440000 { 3790 compatible = "qcom,spmi-pmic-arb"; 3791 reg = <0x0 0x0c440000 0x0 0x1100>, 3792 <0x0 0x0c600000 0x0 0x2000000>, 3793 <0x0 0x0e600000 0x0 0x100000>, 3794 <0x0 0x0e700000 0x0 0xa0000>, 3795 <0x0 0x0c40a000 0x0 0x26000>; 3796 reg-names = "core", 3797 "chnls", 3798 "obsrvr", 3799 "intr", 3800 "cnfg"; 3801 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3802 interrupt-names = "periph_irq"; 3803 interrupt-controller; 3804 #interrupt-cells = <4>; 3805 #address-cells = <2>; 3806 #size-cells = <0>; 3807 qcom,channel = <0>; 3808 qcom,ee = <0>; 3809 }; 3810 3811 intc: interrupt-controller@17a00000 { 3812 compatible = "arm,gic-v3"; 3813 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3814 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3815 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3816 #address-cells = <0>; 3817 #interrupt-cells = <3>; 3818 interrupt-controller; 3819 #redistributor-regions = <1>; 3820 redistributor-stride = <0x0 0x20000>; 3821 }; 3822 3823 apss_shared: mailbox@17c00000 { 3824 compatible = "qcom,qcs615-apss-shared", 3825 "qcom,sdm845-apss-shared"; 3826 reg = <0x0 0x17c00000 0x0 0x1000>; 3827 #mbox-cells = <1>; 3828 }; 3829 3830 watchdog: watchdog@17c10000 { 3831 compatible = "qcom,apss-wdt-qcs615", "qcom,kpss-wdt"; 3832 reg = <0x0 0x17c10000 0x0 0x1000>; 3833 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 3834 clocks = <&sleep_clk>; 3835 }; 3836 3837 timer@17c20000 { 3838 compatible = "arm,armv7-timer-mem"; 3839 reg = <0x0 0x17c20000 0x0 0x1000>; 3840 ranges = <0 0 0 0x20000000>; 3841 #address-cells = <1>; 3842 #size-cells = <1>; 3843 3844 frame@17c21000 { 3845 reg = <0x17c21000 0x1000>, 3846 <0x17c22000 0x1000>; 3847 frame-number = <0>; 3848 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3849 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3850 }; 3851 3852 frame@17c23000 { 3853 reg = <0x17c23000 0x1000>; 3854 frame-number = <1>; 3855 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3856 status = "disabled"; 3857 }; 3858 3859 frame@17c25000 { 3860 reg = <0x17c25000 0x1000>; 3861 frame-number = <2>; 3862 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3863 status = "disabled"; 3864 }; 3865 3866 frame@17c27000 { 3867 reg = <0x17c27000 0x1000>; 3868 frame-number = <3>; 3869 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3870 status = "disabled"; 3871 }; 3872 3873 frame@17c29000 { 3874 reg = <0x17c29000 0x1000>; 3875 frame-number = <4>; 3876 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3877 status = "disabled"; 3878 }; 3879 3880 frame@17c2b000 { 3881 reg = <0x17c2b000 0x1000>; 3882 frame-number = <5>; 3883 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3884 status = "disabled"; 3885 }; 3886 3887 frame@17c2d000 { 3888 reg = <0x17c2d000 0x1000>; 3889 frame-number = <6>; 3890 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3891 status = "disabled"; 3892 }; 3893 }; 3894 3895 apps_rsc: rsc@18200000 { 3896 compatible = "qcom,rpmh-rsc"; 3897 reg = <0x0 0x18200000 0x0 0x10000>, 3898 <0x0 0x18210000 0x0 0x10000>, 3899 <0x0 0x18220000 0x0 0x10000>; 3900 reg-names = "drv-0", 3901 "drv-1", 3902 "drv-2"; 3903 3904 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3905 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3906 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3907 3908 qcom,drv-id = <2>; 3909 qcom,tcs-offset = <0xd00>; 3910 qcom,tcs-config = <ACTIVE_TCS 2>, 3911 <SLEEP_TCS 3>, 3912 <WAKE_TCS 3>, 3913 <CONTROL_TCS 1>; 3914 3915 label = "apps_rsc"; 3916 power-domains = <&cluster_pd>; 3917 3918 apps_bcm_voter: bcm-voter { 3919 compatible = "qcom,bcm-voter"; 3920 }; 3921 3922 rpmhcc: clock-controller { 3923 compatible = "qcom,qcs615-rpmh-clk"; 3924 clocks = <&xo_board_clk>; 3925 clock-names = "xo"; 3926 3927 #clock-cells = <1>; 3928 }; 3929 3930 rpmhpd: power-controller { 3931 compatible = "qcom,qcs615-rpmhpd"; 3932 #power-domain-cells = <1>; 3933 operating-points-v2 = <&rpmhpd_opp_table>; 3934 3935 rpmhpd_opp_table: opp-table { 3936 compatible = "operating-points-v2"; 3937 3938 rpmhpd_opp_ret: opp-0 { 3939 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3940 }; 3941 3942 rpmhpd_opp_min_svs: opp-1 { 3943 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3944 }; 3945 3946 rpmhpd_opp_low_svs: opp-2 { 3947 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3948 }; 3949 3950 rpmhpd_opp_svs: opp-3 { 3951 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3952 }; 3953 3954 rpmhpd_opp_svs_l1: opp-4 { 3955 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3956 }; 3957 3958 rpmhpd_opp_nom: opp-5 { 3959 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3960 }; 3961 3962 rpmhpd_opp_nom_l1: opp-6 { 3963 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3964 }; 3965 3966 rpmhpd_opp_nom_l2: opp-7 { 3967 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3968 }; 3969 3970 rpmhpd_opp_turbo: opp-8 { 3971 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3972 }; 3973 3974 rpmhpd_opp_turbo_l1: opp-9 { 3975 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3976 }; 3977 }; 3978 }; 3979 }; 3980 3981 usb_1_hsphy: phy@88e2000 { 3982 compatible = "qcom,qcs615-qusb2-phy"; 3983 reg = <0x0 0x88e2000 0x0 0x180>; 3984 3985 clocks = <&gcc GCC_AHB2PHY_WEST_CLK>, <&rpmhcc RPMH_CXO_CLK>; 3986 clock-names = "cfg_ahb", "ref"; 3987 3988 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3989 nvmem-cells = <&qusb2_hstx_trim>; 3990 3991 #phy-cells = <0>; 3992 3993 status = "disabled"; 3994 }; 3995 3996 usb_hsphy_2: phy@88e3000 { 3997 compatible = "qcom,qcs615-qusb2-phy"; 3998 reg = <0x0 0x088e3000 0x0 0x180>; 3999 4000 clocks = <&gcc GCC_AHB2PHY_WEST_CLK>, 4001 <&rpmhcc RPMH_CXO_CLK>; 4002 clock-names = "cfg_ahb", 4003 "ref"; 4004 4005 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 4006 4007 #phy-cells = <0>; 4008 4009 status = "disabled"; 4010 }; 4011 4012 usb_qmpphy: phy@88e6000 { 4013 compatible = "qcom,qcs615-qmp-usb3-phy"; 4014 reg = <0x0 0x88e6000 0x0 0x1000>; 4015 4016 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 4017 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 4018 <&gcc GCC_AHB2PHY_WEST_CLK>, 4019 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 4020 clock-names = "aux", 4021 "ref", 4022 "cfg_ahb", 4023 "pipe"; 4024 4025 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, 4026 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; 4027 reset-names = "phy", "phy_phy"; 4028 4029 qcom,tcsr-reg = <&tcsr 0xb244>; 4030 4031 clock-output-names = "usb3_phy_pipe_clk_src"; 4032 #clock-cells = <0>; 4033 4034 #phy-cells = <0>; 4035 4036 status = "disabled"; 4037 }; 4038 4039 usb_1: usb@a6f8800 { 4040 compatible = "qcom,qcs615-dwc3", "qcom,dwc3"; 4041 reg = <0x0 0x0a6f8800 0x0 0x400>; 4042 4043 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4044 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4045 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4046 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4047 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4048 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 4049 clock-names = "cfg_noc", 4050 "core", 4051 "iface", 4052 "sleep", 4053 "mock_utmi", 4054 "xo"; 4055 4056 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4057 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4058 assigned-clock-rates = <19200000>, <200000000>; 4059 4060 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4061 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4062 <&pdc 9 IRQ_TYPE_EDGE_BOTH>, 4063 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 4064 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; 4065 interrupt-names = "pwr_event", 4066 "hs_phy_irq", 4067 "dp_hs_phy_irq", 4068 "dm_hs_phy_irq", 4069 "ss_phy_irq"; 4070 4071 power-domains = <&gcc USB30_PRIM_GDSC>; 4072 required-opps = <&rpmhpd_opp_nom>; 4073 4074 resets = <&gcc GCC_USB30_PRIM_BCR>; 4075 4076 #address-cells = <2>; 4077 #size-cells = <2>; 4078 ranges; 4079 4080 status = "disabled"; 4081 4082 usb_1_dwc3: usb@a600000 { 4083 compatible = "snps,dwc3"; 4084 reg = <0x0 0x0a600000 0x0 0xcd00>; 4085 4086 iommus = <&apps_smmu 0x140 0x0>; 4087 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4088 4089 phys = <&usb_1_hsphy>, <&usb_qmpphy>; 4090 phy-names = "usb2-phy", "usb3-phy"; 4091 4092 snps,dis-u1-entry-quirk; 4093 snps,dis-u2-entry-quirk; 4094 snps,dis_u2_susphy_quirk; 4095 snps,dis_u3_susphy_quirk; 4096 snps,dis_enblslpm_quirk; 4097 snps,has-lpm-erratum; 4098 snps,hird-threshold = /bits/ 8 <0x10>; 4099 snps,usb3_lpm_capable; 4100 }; 4101 }; 4102 4103 usb_2: usb@a8f8800 { 4104 compatible = "qcom,qcs615-dwc3", "qcom,dwc3"; 4105 reg = <0x0 0x0a8f8800 0x0 0x400>; 4106 4107 clocks = <&gcc GCC_CFG_NOC_USB2_SEC_AXI_CLK>, 4108 <&gcc GCC_USB20_SEC_MASTER_CLK>, 4109 <&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>, 4110 <&gcc GCC_USB20_SEC_SLEEP_CLK>, 4111 <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>, 4112 <&gcc GCC_USB2_PRIM_CLKREF_CLK>; 4113 clock-names = "cfg_noc", 4114 "core", 4115 "iface", 4116 "sleep", 4117 "mock_utmi", 4118 "xo"; 4119 4120 assigned-clocks = <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>, 4121 <&gcc GCC_USB20_SEC_MASTER_CLK>; 4122 assigned-clock-rates = <19200000>, <200000000>; 4123 4124 interrupts-extended = <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH>, 4125 <&intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>, 4126 <&pdc 11 IRQ_TYPE_EDGE_BOTH>, 4127 <&pdc 10 IRQ_TYPE_EDGE_BOTH>; 4128 interrupt-names = "pwr_event", 4129 "hs_phy_irq", 4130 "dp_hs_phy_irq", 4131 "dm_hs_phy_irq"; 4132 4133 power-domains = <&gcc USB20_SEC_GDSC>; 4134 required-opps = <&rpmhpd_opp_nom>; 4135 4136 resets = <&gcc GCC_USB20_SEC_BCR>; 4137 4138 qcom,select-utmi-as-pipe-clk; 4139 4140 #address-cells = <2>; 4141 #size-cells = <2>; 4142 ranges; 4143 4144 status = "disabled"; 4145 4146 usb_2_dwc3: usb@a800000 { 4147 compatible = "snps,dwc3"; 4148 reg = <0x0 0x0a800000 0x0 0xcd00>; 4149 4150 iommus = <&apps_smmu 0xe0 0x0>; 4151 interrupts = <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>; 4152 4153 phys = <&usb_hsphy_2>; 4154 phy-names = "usb2-phy"; 4155 4156 snps,dis_u2_susphy_quirk; 4157 snps,dis_u3_susphy_quirk; 4158 snps,dis_enblslpm_quirk; 4159 snps,has-lpm-erratum; 4160 snps,hird-threshold = /bits/ 8 <0x10>; 4161 4162 maximum-speed = "high-speed"; 4163 }; 4164 }; 4165 4166 tsens0: thermal-sensor@c263000 { 4167 compatible = "qcom,qcs615-tsens", "qcom,tsens-v2"; 4168 reg = <0x0 0x0c263000 0x0 0x1000>, 4169 <0x0 0x0c222000 0x0 0x1000>; 4170 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4171 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4172 interrupt-names = "uplow", "critical"; 4173 #qcom,sensors = <16>; 4174 #thermal-sensor-cells = <1>; 4175 }; 4176 4177 remoteproc_adsp: remoteproc@62400000 { 4178 compatible = "qcom,qcs615-adsp-pas", "qcom,sm8150-adsp-pas"; 4179 reg = <0x0 0x62400000 0x0 0x4040>; 4180 4181 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 4182 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4183 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 4184 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 4185 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 4186 interrupt-names = "wdog", 4187 "fatal", 4188 "ready", 4189 "handover", 4190 "stop-ack"; 4191 4192 clocks = <&rpmhcc RPMH_CXO_CLK>; 4193 clock-names = "xo"; 4194 4195 power-domains = <&rpmhpd RPMHPD_CX>; 4196 power-domain-names = "cx"; 4197 4198 memory-region = <&rproc_adsp_mem>; 4199 4200 qcom,qmp = <&aoss_qmp>; 4201 4202 qcom,smem-states = <&adsp_smp2p_out 0>; 4203 qcom,smem-state-names = "stop"; 4204 4205 status = "disabled"; 4206 4207 glink_edge: glink-edge { 4208 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 4209 mboxes = <&apss_shared 24>; 4210 label = "lpass"; 4211 qcom,remote-pid = <2>; 4212 4213 fastrpc { 4214 compatible = "qcom,fastrpc"; 4215 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4216 label = "adsp"; 4217 #address-cells = <1>; 4218 #size-cells = <0>; 4219 4220 compute-cb@3 { 4221 compatible = "qcom,fastrpc-compute-cb"; 4222 reg = <3>; 4223 iommus = <&apps_smmu 0x1723 0x0>; 4224 dma-coherent; 4225 }; 4226 4227 compute-cb@4 { 4228 compatible = "qcom,fastrpc-compute-cb"; 4229 reg = <4>; 4230 iommus = <&apps_smmu 0x1724 0x0>; 4231 dma-coherent; 4232 }; 4233 4234 compute-cb@5 { 4235 compatible = "qcom,fastrpc-compute-cb"; 4236 reg = <5>; 4237 iommus = <&apps_smmu 0x1725 0x0>; 4238 dma-coherent; 4239 }; 4240 4241 compute-cb@6 { 4242 compatible = "qcom,fastrpc-compute-cb"; 4243 reg = <6>; 4244 iommus = <&apps_smmu 0x1726 0x0>; 4245 qcom,nsessions = <5>; 4246 dma-coherent; 4247 }; 4248 }; 4249 }; 4250 }; 4251 4252 cpufreq_hw: cpufreq@18323000 { 4253 compatible = "qcom,qcs615-cpufreq-hw", "qcom,cpufreq-hw"; 4254 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 4255 reg-names = "freq-domain0", "freq-domain1"; 4256 4257 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4258 clock-names = "xo", "alternate"; 4259 4260 #freq-domain-cells = <1>; 4261 #clock-cells = <1>; 4262 }; 4263 }; 4264 4265 arch_timer: timer { 4266 compatible = "arm,armv8-timer"; 4267 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4268 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4269 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4270 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4271 }; 4272 4273 thermal-zones { 4274 aoss-thermal { 4275 thermal-sensors = <&tsens0 0>; 4276 4277 trips { 4278 aoss-critical { 4279 temperature = <115000>; 4280 hysteresis = <1000>; 4281 type = "critical"; 4282 }; 4283 }; 4284 }; 4285 4286 cpuss-0-thermal { 4287 thermal-sensors = <&tsens0 1>; 4288 4289 trips { 4290 cpuss0-critical { 4291 temperature = <115000>; 4292 hysteresis = <1000>; 4293 type = "critical"; 4294 }; 4295 }; 4296 }; 4297 4298 cpuss-1-thermal { 4299 thermal-sensors = <&tsens0 2>; 4300 4301 trips { 4302 cpuss1-critical { 4303 temperature = <115000>; 4304 hysteresis = <1000>; 4305 type = "critical"; 4306 }; 4307 }; 4308 }; 4309 4310 cpuss-2-thermal { 4311 thermal-sensors = <&tsens0 3>; 4312 4313 trips { 4314 cpuss2-critical { 4315 temperature = <115000>; 4316 hysteresis = <1000>; 4317 type = "critical"; 4318 }; 4319 }; 4320 }; 4321 4322 cpuss-3-thermal { 4323 thermal-sensors = <&tsens0 4>; 4324 4325 trips { 4326 cpuss3-critical { 4327 temperature = <115000>; 4328 hysteresis = <1000>; 4329 type = "critical"; 4330 }; 4331 }; 4332 }; 4333 4334 cpu-1-0-thermal { 4335 thermal-sensors = <&tsens0 5>; 4336 4337 trips { 4338 cpu-critical { 4339 temperature = <115000>; 4340 hysteresis = <1000>; 4341 type = "critical"; 4342 }; 4343 }; 4344 }; 4345 4346 cpu-1-1-thermal { 4347 thermal-sensors = <&tsens0 6>; 4348 4349 trips { 4350 cpu-critical { 4351 temperature = <115000>; 4352 hysteresis = <1000>; 4353 type = "critical"; 4354 }; 4355 }; 4356 }; 4357 4358 cpu-1-2-thermal { 4359 thermal-sensors = <&tsens0 7>; 4360 4361 trips { 4362 cpu-critical { 4363 temperature = <115000>; 4364 hysteresis = <1000>; 4365 type = "critical"; 4366 }; 4367 }; 4368 }; 4369 4370 cpu-1-3-thermal { 4371 thermal-sensors = <&tsens0 8>; 4372 4373 trips { 4374 cpu-critical { 4375 temperature = <115000>; 4376 hysteresis = <1000>; 4377 type = "critical"; 4378 }; 4379 }; 4380 }; 4381 4382 gpu-thermal { 4383 thermal-sensors = <&tsens0 9>; 4384 4385 trips { 4386 gpu-critical { 4387 temperature = <115000>; 4388 hysteresis = <1000>; 4389 type = "critical"; 4390 }; 4391 }; 4392 }; 4393 4394 q6-hvx-thermal { 4395 thermal-sensors = <&tsens0 10>; 4396 4397 trips { 4398 q6-hvx-critical { 4399 temperature = <115000>; 4400 hysteresis = <1000>; 4401 type = "critical"; 4402 }; 4403 }; 4404 }; 4405 4406 mdm-core-thermal { 4407 thermal-sensors = <&tsens0 11>; 4408 4409 trips { 4410 mdm-core-critical { 4411 temperature = <115000>; 4412 hysteresis = <1000>; 4413 type = "critical"; 4414 }; 4415 }; 4416 }; 4417 4418 camera-thermal { 4419 thermal-sensors = <&tsens0 12>; 4420 4421 trips { 4422 camera-critical { 4423 temperature = <115000>; 4424 hysteresis = <1000>; 4425 type = "critical"; 4426 }; 4427 }; 4428 }; 4429 4430 wlan-thermal { 4431 thermal-sensors = <&tsens0 13>; 4432 4433 trips { 4434 wlan-critical { 4435 temperature = <115000>; 4436 hysteresis = <1000>; 4437 type = "critical"; 4438 }; 4439 }; 4440 }; 4441 4442 display-thermal { 4443 thermal-sensors = <&tsens0 14>; 4444 4445 trips { 4446 display-critical { 4447 temperature = <115000>; 4448 hysteresis = <1000>; 4449 type = "critical"; 4450 }; 4451 }; 4452 }; 4453 4454 video-thermal { 4455 thermal-sensors = <&tsens0 15>; 4456 4457 trips { 4458 video-critical { 4459 temperature = <115000>; 4460 hysteresis = <1000>; 4461 type = "critical"; 4462 }; 4463 }; 4464 }; 4465 }; 4466}; 4467