1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org> 4 */ 5 6#include <dt-bindings/clock/qcom,gcc-sm6125.h> 7#include <dt-bindings/clock/qcom,rpmcc.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/qcom-rpmpd.h> 11 12/ { 13 interrupt-parent = <&intc>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 chosen { }; 18 19 clocks { 20 xo_board: xo-board { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <19200000>; 24 clock-output-names = "xo_board"; 25 }; 26 27 sleep_clk: sleep-clk { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <32000>; 31 clock-output-names = "sleep_clk"; 32 }; 33 }; 34 35 cpus { 36 #address-cells = <2>; 37 #size-cells = <0>; 38 39 CPU0: cpu@0 { 40 device_type = "cpu"; 41 compatible = "qcom,kryo260"; 42 reg = <0x0 0x0>; 43 enable-method = "psci"; 44 capacity-dmips-mhz = <1024>; 45 next-level-cache = <&L2_0>; 46 L2_0: l2-cache { 47 compatible = "cache"; 48 }; 49 }; 50 51 CPU1: cpu@1 { 52 device_type = "cpu"; 53 compatible = "qcom,kryo260"; 54 reg = <0x0 0x1>; 55 enable-method = "psci"; 56 capacity-dmips-mhz = <1024>; 57 next-level-cache = <&L2_0>; 58 }; 59 60 CPU2: cpu@2 { 61 device_type = "cpu"; 62 compatible = "qcom,kryo260"; 63 reg = <0x0 0x2>; 64 enable-method = "psci"; 65 capacity-dmips-mhz = <1024>; 66 next-level-cache = <&L2_0>; 67 }; 68 69 CPU3: cpu@3 { 70 device_type = "cpu"; 71 compatible = "qcom,kryo260"; 72 reg = <0x0 0x3>; 73 enable-method = "psci"; 74 capacity-dmips-mhz = <1024>; 75 next-level-cache = <&L2_0>; 76 }; 77 78 CPU4: cpu@100 { 79 device_type = "cpu"; 80 compatible = "qcom,kryo260"; 81 reg = <0x0 0x100>; 82 enable-method = "psci"; 83 capacity-dmips-mhz = <1638>; 84 next-level-cache = <&L2_1>; 85 L2_1: l2-cache { 86 compatible = "cache"; 87 }; 88 }; 89 90 CPU5: cpu@101 { 91 device_type = "cpu"; 92 compatible = "qcom,kryo260"; 93 reg = <0x0 0x101>; 94 enable-method = "psci"; 95 capacity-dmips-mhz = <1638>; 96 next-level-cache = <&L2_1>; 97 }; 98 99 CPU6: cpu@102 { 100 device_type = "cpu"; 101 compatible = "qcom,kryo260"; 102 reg = <0x0 0x102>; 103 enable-method = "psci"; 104 capacity-dmips-mhz = <1638>; 105 next-level-cache = <&L2_1>; 106 }; 107 108 CPU7: cpu@103 { 109 device_type = "cpu"; 110 compatible = "qcom,kryo260"; 111 reg = <0x0 0x103>; 112 enable-method = "psci"; 113 capacity-dmips-mhz = <1638>; 114 next-level-cache = <&L2_1>; 115 }; 116 117 cpu-map { 118 cluster0 { 119 core0 { 120 cpu = <&CPU0>; 121 }; 122 123 core1 { 124 cpu = <&CPU1>; 125 }; 126 127 core2 { 128 cpu = <&CPU2>; 129 }; 130 131 core3 { 132 cpu = <&CPU3>; 133 }; 134 }; 135 136 cluster1 { 137 core0 { 138 cpu = <&CPU4>; 139 }; 140 141 core1 { 142 cpu = <&CPU5>; 143 }; 144 145 core2 { 146 cpu = <&CPU6>; 147 }; 148 149 core3 { 150 cpu = <&CPU7>; 151 }; 152 }; 153 }; 154 }; 155 156 firmware { 157 scm: scm { 158 compatible = "qcom,scm-sm6125", "qcom,scm"; 159 #reset-cells = <1>; 160 }; 161 }; 162 163 memory@40000000 { 164 /* We expect the bootloader to fill in the size */ 165 reg = <0x0 0x40000000 0x0 0x0>; 166 device_type = "memory"; 167 }; 168 169 pmu { 170 compatible = "arm,armv8-pmuv3"; 171 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 172 }; 173 174 psci { 175 compatible = "arm,psci-1.0"; 176 method = "smc"; 177 }; 178 179 reserved_memory: reserved-memory { 180 #address-cells = <2>; 181 #size-cells = <2>; 182 ranges; 183 184 hyp_mem: memory@45700000 { 185 reg = <0x0 0x45700000 0x0 0x600000>; 186 no-map; 187 }; 188 189 xbl_aop_mem: memory@45e00000 { 190 reg = <0x0 0x45e00000 0x0 0x140000>; 191 no-map; 192 }; 193 194 sec_apps_mem: memory@45fff000 { 195 reg = <0x0 0x45fff000 0x0 0x1000>; 196 no-map; 197 }; 198 199 smem_mem: memory@46000000 { 200 reg = <0x0 0x46000000 0x0 0x200000>; 201 no-map; 202 }; 203 204 reserved_mem1: memory@46200000 { 205 reg = <0x0 0x46200000 0x0 0x2d00000>; 206 no-map; 207 }; 208 209 camera_mem: memory@4ab00000 { 210 reg = <0x0 0x4ab00000 0x0 0x500000>; 211 no-map; 212 }; 213 214 modem_mem: memory@4b000000 { 215 reg = <0x0 0x4b000000 0x0 0x7e00000>; 216 no-map; 217 }; 218 219 venus_mem: memory@52e00000 { 220 reg = <0x0 0x52e00000 0x0 0x500000>; 221 no-map; 222 }; 223 224 wlan_msa_mem: memory@53300000 { 225 reg = <0x0 0x53300000 0x0 0x200000>; 226 no-map; 227 }; 228 229 cdsp_mem: memory@53500000 { 230 reg = <0x0 0x53500000 0x0 0x1e00000>; 231 no-map; 232 }; 233 234 adsp_pil_mem: memory@55300000 { 235 reg = <0x0 0x55300000 0x0 0x1e00000>; 236 no-map; 237 }; 238 239 ipa_fw_mem: memory@57100000 { 240 reg = <0x0 0x57100000 0x0 0x10000>; 241 no-map; 242 }; 243 244 ipa_gsi_mem: memory@57110000 { 245 reg = <0x0 0x57110000 0x0 0x5000>; 246 no-map; 247 }; 248 249 gpu_mem: memory@57115000 { 250 reg = <0x0 0x57115000 0x0 0x2000>; 251 no-map; 252 }; 253 254 cont_splash_mem: memory@5c000000 { 255 reg = <0x0 0x5c000000 0x0 0x00f00000>; 256 no-map; 257 }; 258 259 dfps_data_mem: memory@5cf00000 { 260 reg = <0x0 0x5cf00000 0x0 0x0100000>; 261 no-map; 262 }; 263 264 cdsp_sec_mem: memory@5f800000 { 265 reg = <0x0 0x5f800000 0x0 0x1e00000>; 266 no-map; 267 }; 268 269 qseecom_mem: memory@5e400000 { 270 reg = <0x0 0x5e400000 0x0 0x1400000>; 271 no-map; 272 }; 273 274 sdsp_mem: memory@f3000000 { 275 reg = <0x0 0xf3000000 0x0 0x400000>; 276 no-map; 277 }; 278 279 adsp_mem: memory@f3400000 { 280 reg = <0x0 0xf3400000 0x0 0x800000>; 281 no-map; 282 }; 283 284 qseecom_ta_mem: memory@13fc00000 { 285 reg = <0x1 0x3fc00000 0x0 0x400000>; 286 no-map; 287 }; 288 }; 289 290 rpm-glink { 291 compatible = "qcom,glink-rpm"; 292 293 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 294 qcom,rpm-msg-ram = <&rpm_msg_ram>; 295 mboxes = <&apcs_glb 0>; 296 297 rpm_requests: rpm-requests { 298 compatible = "qcom,rpm-sm6125"; 299 qcom,glink-channels = "rpm_requests"; 300 301 rpmcc: clock-controller { 302 compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc"; 303 #clock-cells = <1>; 304 }; 305 306 rpmpd: power-controller { 307 compatible = "qcom,sm6125-rpmpd"; 308 #power-domain-cells = <1>; 309 operating-points-v2 = <&rpmpd_opp_table>; 310 311 rpmpd_opp_table: opp-table { 312 compatible = "operating-points-v2"; 313 314 rpmpd_opp_ret: opp1 { 315 opp-level = <RPM_SMD_LEVEL_RETENTION>; 316 }; 317 318 rpmpd_opp_ret_plus: opp2 { 319 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 320 }; 321 322 rpmpd_opp_min_svs: opp3 { 323 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 324 }; 325 326 rpmpd_opp_low_svs: opp4 { 327 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 328 }; 329 330 rpmpd_opp_svs: opp5 { 331 opp-level = <RPM_SMD_LEVEL_SVS>; 332 }; 333 334 rpmpd_opp_svs_plus: opp6 { 335 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 336 }; 337 338 rpmpd_opp_nom: opp7 { 339 opp-level = <RPM_SMD_LEVEL_NOM>; 340 }; 341 342 rpmpd_opp_nom_plus: opp8 { 343 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 344 }; 345 346 rpmpd_opp_turbo: opp9 { 347 opp-level = <RPM_SMD_LEVEL_TURBO>; 348 }; 349 350 rpmpd_opp_turbo_no_cpr: opp10 { 351 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 352 }; 353 }; 354 }; 355 }; 356 }; 357 358 smem: smem { 359 compatible = "qcom,smem"; 360 memory-region = <&smem_mem>; 361 hwlocks = <&tcsr_mutex 3>; 362 }; 363 364 soc { 365 #address-cells = <1>; 366 #size-cells = <1>; 367 ranges = <0x00 0x00 0x00 0xffffffff>; 368 compatible = "simple-bus"; 369 370 tcsr_mutex: hwlock@340000 { 371 compatible = "qcom,tcsr-mutex"; 372 reg = <0x00340000 0x20000>; 373 #hwlock-cells = <1>; 374 }; 375 376 tlmm: pinctrl@500000 { 377 compatible = "qcom,sm6125-tlmm"; 378 reg = <0x00500000 0x400000>, 379 <0x00900000 0x400000>, 380 <0x00d00000 0x400000>; 381 reg-names = "west", "south", "east"; 382 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 383 gpio-controller; 384 gpio-ranges = <&tlmm 0 0 134>; 385 #gpio-cells = <2>; 386 interrupt-controller; 387 #interrupt-cells = <2>; 388 389 sdc2_state_off: sdc2-off { 390 clk { 391 pins = "sdc2_clk"; 392 bias-disable; 393 drive-strength = <2>; 394 }; 395 396 cmd { 397 pins = "sdc2_cmd"; 398 bias-pull-up; 399 drive-strength = <2>; 400 }; 401 402 data { 403 pins = "sdc2_data"; 404 bias-pull-up; 405 drive-strength = <2>; 406 }; 407 }; 408 }; 409 410 gcc: clock-controller@1400000 { 411 compatible = "qcom,gcc-sm6125"; 412 reg = <0x01400000 0x1f0000>; 413 #clock-cells = <1>; 414 #reset-cells = <1>; 415 #power-domain-cells = <1>; 416 clock-names = "bi_tcxo", "sleep_clk"; 417 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 418 }; 419 420 hsusb_phy1: phy@1613000 { 421 compatible = "qcom,msm8996-qusb2-phy"; 422 reg = <0x01613000 0x180>; 423 #phy-cells = <0>; 424 425 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 426 <&gcc GCC_AHB2PHY_USB_CLK>; 427 clock-names = "ref", "cfg_ahb"; 428 429 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 430 status = "disabled"; 431 }; 432 433 rpm_msg_ram: sram@45f0000 { 434 compatible = "qcom,rpm-msg-ram"; 435 reg = <0x045f0000 0x7000>; 436 }; 437 438 sdhc_1: sdhci@4744000 { 439 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; 440 reg = <0x04744000 0x1000>, <0x04745000 0x1000>; 441 reg-names = "hc", "core"; 442 443 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 445 interrupt-names = "hc_irq", "pwr_irq"; 446 447 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 448 <&gcc GCC_SDCC1_APPS_CLK>, 449 <&xo_board>; 450 clock-names = "iface", "core", "xo"; 451 452 power-domains = <&rpmpd 0>; 453 454 bus-width = <8>; 455 non-removable; 456 status = "disabled"; 457 }; 458 459 sdhc_2: sdhci@4784000 { 460 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; 461 reg = <0x04784000 0x1000>; 462 reg-names = "hc"; 463 464 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 466 interrupt-names = "hc_irq", "pwr_irq"; 467 468 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 469 <&gcc GCC_SDCC2_APPS_CLK>, 470 <&xo_board>; 471 clock-names = "iface", "core", "xo"; 472 473 pinctrl-0 = <&sdc2_state_on>; 474 pinctrl-1 = <&sdc2_state_off>; 475 pinctrl-names = "default", "sleep"; 476 477 power-domains = <&rpmpd 0>; 478 479 bus-width = <4>; 480 status = "disabled"; 481 }; 482 483 usb3: usb@4ef8800 { 484 compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; 485 reg = <0x04ef8800 0x400>; 486 #address-cells = <1>; 487 #size-cells = <1>; 488 ranges; 489 490 clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, 491 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 492 <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 493 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 494 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 495 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 496 497 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 498 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 499 assigned-clock-rates = <19200000>, <66666667>; 500 501 power-domains = <&gcc USB30_PRIM_GDSC>; 502 qcom,select-utmi-as-pipe-clk; 503 status = "disabled"; 504 505 usb3_dwc3: usb@4e00000 { 506 compatible = "snps,dwc3"; 507 reg = <0x04e00000 0xcd00>; 508 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 509 phys = <&hsusb_phy1>; 510 phy-names = "usb2-phy"; 511 snps,dis_u2_susphy_quirk; 512 snps,dis_enblslpm_quirk; 513 maximum-speed = "high-speed"; 514 dr_mode = "peripheral"; 515 }; 516 }; 517 518 sram@4690000 { 519 compatible = "qcom,rpm-stats"; 520 reg = <0x04690000 0x10000>; 521 }; 522 523 spmi_bus: spmi@1c40000 { 524 compatible = "qcom,spmi-pmic-arb"; 525 reg = <0x01c40000 0x1100>, 526 <0x01e00000 0x2000000>, 527 <0x03e00000 0x100000>, 528 <0x03f00000 0xa0000>, 529 <0x01c0a000 0x26000>; 530 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 531 interrupt-names = "periph_irq"; 532 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 533 qcom,ee = <0>; 534 qcom,channel = <0>; 535 #address-cells = <2>; 536 #size-cells = <0>; 537 interrupt-controller; 538 #interrupt-cells = <4>; 539 cell-index = <0>; 540 }; 541 542 apcs_glb: mailbox@f111000 { 543 compatible = "qcom,sm6125-apcs-hmss-global"; 544 reg = <0x0f111000 0x1000>; 545 546 #mbox-cells = <1>; 547 }; 548 549 timer@f120000 { 550 compatible = "arm,armv7-timer-mem"; 551 #address-cells = <1>; 552 #size-cells = <1>; 553 ranges; 554 reg = <0x0f120000 0x1000>; 555 clock-frequency = <19200000>; 556 557 frame@f121000 { 558 frame-number = <0>; 559 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 561 reg = <0x0f121000 0x1000>, 562 <0x0f122000 0x1000>; 563 }; 564 565 frame@f123000 { 566 frame-number = <1>; 567 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 568 reg = <0x0f123000 0x1000>; 569 status = "disabled"; 570 }; 571 572 frame@f124000 { 573 frame-number = <2>; 574 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 575 reg = <0x0f124000 0x1000>; 576 status = "disabled"; 577 }; 578 579 frame@f125000 { 580 frame-number = <3>; 581 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 582 reg = <0x0f125000 0x1000>; 583 status = "disabled"; 584 }; 585 586 frame@f126000 { 587 frame-number = <4>; 588 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 589 reg = <0x0f126000 0x1000>; 590 status = "disabled"; 591 }; 592 593 frame@f127000 { 594 frame-number = <5>; 595 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 596 reg = <0x0f127000 0x1000>; 597 status = "disabled"; 598 }; 599 600 frame@f128000 { 601 frame-number = <6>; 602 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 603 reg = <0x0f128000 0x1000>; 604 status = "disabled"; 605 }; 606 }; 607 608 intc: interrupt-controller@f200000 { 609 compatible = "arm,gic-v3"; 610 reg = <0x0f200000 0x20000>, 611 <0x0f300000 0x100000>; 612 #interrupt-cells = <3>; 613 interrupt-controller; 614 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 615 }; 616 }; 617 618 timer { 619 compatible = "arm,armv8-timer"; 620 interrupts = <GIC_PPI 1 0xf08 621 GIC_PPI 2 0xf08 622 GIC_PPI 3 0xf08 623 GIC_PPI 0 0xf08>; 624 clock-frequency = <19200000>; 625 }; 626}; 627