1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com> 4 */ 5 6#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 7#include <dt-bindings/clock/qcom,gcc-sm6115.h> 8#include <dt-bindings/clock/qcom,sm6115-dispcc.h> 9#include <dt-bindings/clock/qcom,sm6115-gpucc.h> 10#include <dt-bindings/clock/qcom,rpmcc.h> 11#include <dt-bindings/dma/qcom-gpi.h> 12#include <dt-bindings/firmware/qcom,scm.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/interconnect/qcom,rpm-icc.h> 15#include <dt-bindings/interconnect/qcom,sm6115.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/soc/qcom,apr.h> 19#include <dt-bindings/sound/qcom,q6asm.h> 20#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 21#include <dt-bindings/thermal/thermal.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 chosen { }; 30 31 clocks { 32 xo_board: xo-board { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 }; 36 37 sleep_clk: sleep-clk { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 }; 41 }; 42 43 cpus { 44 #address-cells = <2>; 45 #size-cells = <0>; 46 47 cpu0: cpu@0 { 48 device_type = "cpu"; 49 compatible = "qcom,kryo260"; 50 reg = <0x0 0x0>; 51 clocks = <&cpufreq_hw 0>; 52 capacity-dmips-mhz = <1024>; 53 dynamic-power-coefficient = <100>; 54 enable-method = "psci"; 55 next-level-cache = <&l2_0>; 56 qcom,freq-domain = <&cpufreq_hw 0>; 57 power-domains = <&cpu_pd0>; 58 power-domain-names = "psci"; 59 l2_0: l2-cache { 60 compatible = "cache"; 61 cache-level = <2>; 62 cache-unified; 63 }; 64 }; 65 66 cpu1: cpu@1 { 67 device_type = "cpu"; 68 compatible = "qcom,kryo260"; 69 reg = <0x0 0x1>; 70 clocks = <&cpufreq_hw 0>; 71 capacity-dmips-mhz = <1024>; 72 dynamic-power-coefficient = <100>; 73 enable-method = "psci"; 74 next-level-cache = <&l2_0>; 75 qcom,freq-domain = <&cpufreq_hw 0>; 76 power-domains = <&cpu_pd1>; 77 power-domain-names = "psci"; 78 }; 79 80 cpu2: cpu@2 { 81 device_type = "cpu"; 82 compatible = "qcom,kryo260"; 83 reg = <0x0 0x2>; 84 clocks = <&cpufreq_hw 0>; 85 capacity-dmips-mhz = <1024>; 86 dynamic-power-coefficient = <100>; 87 enable-method = "psci"; 88 next-level-cache = <&l2_0>; 89 qcom,freq-domain = <&cpufreq_hw 0>; 90 power-domains = <&cpu_pd2>; 91 power-domain-names = "psci"; 92 }; 93 94 cpu3: cpu@3 { 95 device_type = "cpu"; 96 compatible = "qcom,kryo260"; 97 reg = <0x0 0x3>; 98 clocks = <&cpufreq_hw 0>; 99 capacity-dmips-mhz = <1024>; 100 dynamic-power-coefficient = <100>; 101 enable-method = "psci"; 102 next-level-cache = <&l2_0>; 103 qcom,freq-domain = <&cpufreq_hw 0>; 104 power-domains = <&cpu_pd3>; 105 power-domain-names = "psci"; 106 }; 107 108 cpu4: cpu@100 { 109 device_type = "cpu"; 110 compatible = "qcom,kryo260"; 111 reg = <0x0 0x100>; 112 clocks = <&cpufreq_hw 1>; 113 enable-method = "psci"; 114 capacity-dmips-mhz = <1638>; 115 dynamic-power-coefficient = <282>; 116 next-level-cache = <&l2_1>; 117 qcom,freq-domain = <&cpufreq_hw 1>; 118 power-domains = <&cpu_pd4>; 119 power-domain-names = "psci"; 120 l2_1: l2-cache { 121 compatible = "cache"; 122 cache-level = <2>; 123 cache-unified; 124 }; 125 }; 126 127 cpu5: cpu@101 { 128 device_type = "cpu"; 129 compatible = "qcom,kryo260"; 130 reg = <0x0 0x101>; 131 clocks = <&cpufreq_hw 1>; 132 capacity-dmips-mhz = <1638>; 133 dynamic-power-coefficient = <282>; 134 enable-method = "psci"; 135 next-level-cache = <&l2_1>; 136 qcom,freq-domain = <&cpufreq_hw 1>; 137 power-domains = <&cpu_pd5>; 138 power-domain-names = "psci"; 139 }; 140 141 cpu6: cpu@102 { 142 device_type = "cpu"; 143 compatible = "qcom,kryo260"; 144 reg = <0x0 0x102>; 145 clocks = <&cpufreq_hw 1>; 146 capacity-dmips-mhz = <1638>; 147 dynamic-power-coefficient = <282>; 148 enable-method = "psci"; 149 next-level-cache = <&l2_1>; 150 qcom,freq-domain = <&cpufreq_hw 1>; 151 power-domains = <&cpu_pd6>; 152 power-domain-names = "psci"; 153 }; 154 155 cpu7: cpu@103 { 156 device_type = "cpu"; 157 compatible = "qcom,kryo260"; 158 reg = <0x0 0x103>; 159 clocks = <&cpufreq_hw 1>; 160 capacity-dmips-mhz = <1638>; 161 dynamic-power-coefficient = <282>; 162 enable-method = "psci"; 163 next-level-cache = <&l2_1>; 164 qcom,freq-domain = <&cpufreq_hw 1>; 165 power-domains = <&cpu_pd7>; 166 power-domain-names = "psci"; 167 }; 168 169 cpu-map { 170 cluster0 { 171 core0 { 172 cpu = <&cpu0>; 173 }; 174 175 core1 { 176 cpu = <&cpu1>; 177 }; 178 179 core2 { 180 cpu = <&cpu2>; 181 }; 182 183 core3 { 184 cpu = <&cpu3>; 185 }; 186 }; 187 188 cluster1 { 189 core0 { 190 cpu = <&cpu4>; 191 }; 192 193 core1 { 194 cpu = <&cpu5>; 195 }; 196 197 core2 { 198 cpu = <&cpu6>; 199 }; 200 201 core3 { 202 cpu = <&cpu7>; 203 }; 204 }; 205 }; 206 207 idle-states { 208 entry-method = "psci"; 209 210 little_cpu_sleep_0: cpu-sleep-0-0 { 211 compatible = "arm,idle-state"; 212 idle-state-name = "silver-rail-power-collapse"; 213 arm,psci-suspend-param = <0x40000003>; 214 entry-latency-us = <290>; 215 exit-latency-us = <376>; 216 min-residency-us = <1182>; 217 local-timer-stop; 218 }; 219 220 big_cpu_sleep_0: cpu-sleep-1-0 { 221 compatible = "arm,idle-state"; 222 idle-state-name = "gold-rail-power-collapse"; 223 arm,psci-suspend-param = <0x40000003>; 224 entry-latency-us = <297>; 225 exit-latency-us = <324>; 226 min-residency-us = <1110>; 227 local-timer-stop; 228 }; 229 }; 230 231 domain-idle-states { 232 cluster_0_sleep_0: cluster-sleep-0-0 { 233 /* GDHS */ 234 compatible = "domain-idle-state"; 235 arm,psci-suspend-param = <0x40000022>; 236 entry-latency-us = <360>; 237 exit-latency-us = <421>; 238 min-residency-us = <782>; 239 }; 240 241 cluster_0_sleep_1: cluster-sleep-0-1 { 242 /* Power Collapse */ 243 compatible = "domain-idle-state"; 244 arm,psci-suspend-param = <0x41000044>; 245 entry-latency-us = <800>; 246 exit-latency-us = <2118>; 247 min-residency-us = <7376>; 248 }; 249 250 cluster_1_sleep_0: cluster-sleep-1-0 { 251 /* GDHS */ 252 compatible = "domain-idle-state"; 253 arm,psci-suspend-param = <0x40000042>; 254 entry-latency-us = <314>; 255 exit-latency-us = <345>; 256 min-residency-us = <660>; 257 }; 258 259 cluster_1_sleep_1: cluster-sleep-1-1 { 260 /* Power Collapse */ 261 compatible = "domain-idle-state"; 262 arm,psci-suspend-param = <0x41000044>; 263 entry-latency-us = <640>; 264 exit-latency-us = <1654>; 265 min-residency-us = <8094>; 266 }; 267 }; 268 }; 269 270 firmware { 271 scm: scm { 272 compatible = "qcom,scm-sm6115", "qcom,scm"; 273 #reset-cells = <1>; 274 interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG 275 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 276 }; 277 }; 278 279 memory@80000000 { 280 device_type = "memory"; 281 /* We expect the bootloader to fill in the size */ 282 reg = <0 0x80000000 0 0>; 283 }; 284 285 qup_opp_table: opp-table-qup { 286 compatible = "operating-points-v2"; 287 288 opp-75000000 { 289 opp-hz = /bits/ 64 <75000000>; 290 required-opps = <&rpmpd_opp_low_svs>; 291 }; 292 293 opp-100000000 { 294 opp-hz = /bits/ 64 <100000000>; 295 required-opps = <&rpmpd_opp_svs>; 296 }; 297 298 opp-128000000 { 299 opp-hz = /bits/ 64 <128000000>; 300 required-opps = <&rpmpd_opp_nom>; 301 }; 302 }; 303 304 pmu { 305 compatible = "arm,armv8-pmuv3"; 306 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 307 }; 308 309 psci { 310 compatible = "arm,psci-1.0"; 311 method = "smc"; 312 313 cpu_pd0: power-domain-cpu0 { 314 #power-domain-cells = <0>; 315 power-domains = <&cluster_0_pd>; 316 domain-idle-states = <&little_cpu_sleep_0>; 317 }; 318 319 cpu_pd1: power-domain-cpu1 { 320 #power-domain-cells = <0>; 321 power-domains = <&cluster_0_pd>; 322 domain-idle-states = <&little_cpu_sleep_0>; 323 }; 324 325 cpu_pd2: power-domain-cpu2 { 326 #power-domain-cells = <0>; 327 power-domains = <&cluster_0_pd>; 328 domain-idle-states = <&little_cpu_sleep_0>; 329 }; 330 331 cpu_pd3: power-domain-cpu3 { 332 #power-domain-cells = <0>; 333 power-domains = <&cluster_0_pd>; 334 domain-idle-states = <&little_cpu_sleep_0>; 335 }; 336 337 cpu_pd4: power-domain-cpu4 { 338 #power-domain-cells = <0>; 339 power-domains = <&cluster_1_pd>; 340 domain-idle-states = <&big_cpu_sleep_0>; 341 }; 342 343 cpu_pd5: power-domain-cpu5 { 344 #power-domain-cells = <0>; 345 power-domains = <&cluster_1_pd>; 346 domain-idle-states = <&big_cpu_sleep_0>; 347 }; 348 349 cpu_pd6: power-domain-cpu6 { 350 #power-domain-cells = <0>; 351 power-domains = <&cluster_1_pd>; 352 domain-idle-states = <&big_cpu_sleep_0>; 353 }; 354 355 cpu_pd7: power-domain-cpu7 { 356 #power-domain-cells = <0>; 357 power-domains = <&cluster_1_pd>; 358 domain-idle-states = <&big_cpu_sleep_0>; 359 }; 360 361 cluster_0_pd: power-domain-cpu-cluster0 { 362 #power-domain-cells = <0>; 363 domain-idle-states = <&cluster_0_sleep_0>, <&cluster_0_sleep_1>; 364 }; 365 366 cluster_1_pd: power-domain-cpu-cluster1 { 367 #power-domain-cells = <0>; 368 domain-idle-states = <&cluster_1_sleep_0>, <&cluster_1_sleep_1>; 369 }; 370 }; 371 372 rpm: remoteproc { 373 compatible = "qcom,sm6115-rpm-proc", "qcom,rpm-proc"; 374 375 glink-edge { 376 compatible = "qcom,glink-rpm"; 377 378 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 379 qcom,rpm-msg-ram = <&rpm_msg_ram>; 380 mboxes = <&apcs_glb 0>; 381 382 rpm_requests: rpm-requests { 383 compatible = "qcom,rpm-sm6115", "qcom,glink-smd-rpm"; 384 qcom,glink-channels = "rpm_requests"; 385 386 rpmcc: clock-controller { 387 compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc"; 388 clocks = <&xo_board>; 389 clock-names = "xo"; 390 #clock-cells = <1>; 391 }; 392 393 rpmpd: power-controller { 394 compatible = "qcom,sm6115-rpmpd"; 395 #power-domain-cells = <1>; 396 operating-points-v2 = <&rpmpd_opp_table>; 397 398 rpmpd_opp_table: opp-table { 399 compatible = "operating-points-v2"; 400 401 rpmpd_opp_min_svs: opp1 { 402 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 403 }; 404 405 rpmpd_opp_low_svs: opp2 { 406 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 407 }; 408 409 rpmpd_opp_svs: opp3 { 410 opp-level = <RPM_SMD_LEVEL_SVS>; 411 }; 412 413 rpmpd_opp_svs_plus: opp4 { 414 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 415 }; 416 417 rpmpd_opp_nom: opp5 { 418 opp-level = <RPM_SMD_LEVEL_NOM>; 419 }; 420 421 rpmpd_opp_nom_plus: opp6 { 422 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 423 }; 424 425 rpmpd_opp_turbo: opp7 { 426 opp-level = <RPM_SMD_LEVEL_TURBO>; 427 }; 428 429 rpmpd_opp_turbo_plus: opp8 { 430 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 431 }; 432 }; 433 }; 434 }; 435 }; 436 }; 437 438 reserved_memory: reserved-memory { 439 #address-cells = <2>; 440 #size-cells = <2>; 441 ranges; 442 443 hyp_mem: memory@45700000 { 444 reg = <0x0 0x45700000 0x0 0x600000>; 445 no-map; 446 }; 447 448 xbl_aop_mem: memory@45e00000 { 449 reg = <0x0 0x45e00000 0x0 0x140000>; 450 no-map; 451 }; 452 453 sec_apps_mem: memory@45fff000 { 454 reg = <0x0 0x45fff000 0x0 0x1000>; 455 no-map; 456 }; 457 458 smem_mem: memory@46000000 { 459 compatible = "qcom,smem"; 460 reg = <0x0 0x46000000 0x0 0x200000>; 461 no-map; 462 463 hwlocks = <&tcsr_mutex 3>; 464 qcom,rpm-msg-ram = <&rpm_msg_ram>; 465 }; 466 467 cdsp_sec_mem: memory@46200000 { 468 reg = <0x0 0x46200000 0x0 0x1e00000>; 469 no-map; 470 }; 471 472 pil_modem_mem: memory@4ab00000 { 473 reg = <0x0 0x4ab00000 0x0 0x6900000>; 474 no-map; 475 }; 476 477 pil_video_mem: memory@51400000 { 478 reg = <0x0 0x51400000 0x0 0x500000>; 479 no-map; 480 }; 481 482 wlan_msa_mem: memory@51900000 { 483 reg = <0x0 0x51900000 0x0 0x100000>; 484 no-map; 485 }; 486 487 pil_cdsp_mem: memory@51a00000 { 488 reg = <0x0 0x51a00000 0x0 0x1e00000>; 489 no-map; 490 }; 491 492 pil_adsp_mem: memory@53800000 { 493 reg = <0x0 0x53800000 0x0 0x2800000>; 494 no-map; 495 }; 496 497 pil_ipa_fw_mem: memory@56100000 { 498 reg = <0x0 0x56100000 0x0 0x10000>; 499 no-map; 500 }; 501 502 pil_ipa_gsi_mem: memory@56110000 { 503 reg = <0x0 0x56110000 0x0 0x5000>; 504 no-map; 505 }; 506 507 pil_gpu_mem: memory@56115000 { 508 reg = <0x0 0x56115000 0x0 0x2000>; 509 no-map; 510 }; 511 512 cont_splash_memory: memory@5c000000 { 513 reg = <0x0 0x5c000000 0x0 0x00f00000>; 514 no-map; 515 }; 516 517 dfps_data_memory: memory@5cf00000 { 518 reg = <0x0 0x5cf00000 0x0 0x0100000>; 519 no-map; 520 }; 521 522 removed_mem: memory@60000000 { 523 reg = <0x0 0x60000000 0x0 0x3900000>; 524 no-map; 525 }; 526 527 rmtfs_mem: memory@89b01000 { 528 compatible = "qcom,rmtfs-mem"; 529 reg = <0x0 0x89b01000 0x0 0x200000>; 530 no-map; 531 532 qcom,client-id = <1>; 533 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; 534 }; 535 }; 536 537 smp2p-adsp { 538 compatible = "qcom,smp2p"; 539 qcom,smem = <443>, <429>; 540 541 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>; 542 543 mboxes = <&apcs_glb 10>; 544 545 qcom,local-pid = <0>; 546 qcom,remote-pid = <2>; 547 548 adsp_smp2p_out: master-kernel { 549 qcom,entry-name = "master-kernel"; 550 #qcom,smem-state-cells = <1>; 551 }; 552 553 adsp_smp2p_in: slave-kernel { 554 qcom,entry-name = "slave-kernel"; 555 556 interrupt-controller; 557 #interrupt-cells = <2>; 558 }; 559 }; 560 561 smp2p-cdsp { 562 compatible = "qcom,smp2p"; 563 qcom,smem = <94>, <432>; 564 565 interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>; 566 567 mboxes = <&apcs_glb 30>; 568 569 qcom,local-pid = <0>; 570 qcom,remote-pid = <5>; 571 572 cdsp_smp2p_out: master-kernel { 573 qcom,entry-name = "master-kernel"; 574 #qcom,smem-state-cells = <1>; 575 }; 576 577 cdsp_smp2p_in: slave-kernel { 578 qcom,entry-name = "slave-kernel"; 579 580 interrupt-controller; 581 #interrupt-cells = <2>; 582 }; 583 }; 584 585 smp2p-mpss { 586 compatible = "qcom,smp2p"; 587 qcom,smem = <435>, <428>; 588 589 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; 590 591 mboxes = <&apcs_glb 14>; 592 593 qcom,local-pid = <0>; 594 qcom,remote-pid = <1>; 595 596 modem_smp2p_out: master-kernel { 597 qcom,entry-name = "master-kernel"; 598 #qcom,smem-state-cells = <1>; 599 }; 600 601 modem_smp2p_in: slave-kernel { 602 qcom,entry-name = "slave-kernel"; 603 604 interrupt-controller; 605 #interrupt-cells = <2>; 606 }; 607 }; 608 609 soc: soc@0 { 610 compatible = "simple-bus"; 611 #address-cells = <2>; 612 #size-cells = <2>; 613 ranges = <0 0 0 0 0x10 0>; 614 dma-ranges = <0 0 0 0 0x10 0>; 615 616 tcsr_mutex: hwlock@340000 { 617 compatible = "qcom,tcsr-mutex"; 618 reg = <0x0 0x00340000 0x0 0x20000>; 619 #hwlock-cells = <1>; 620 }; 621 622 tcsr_regs: syscon@3c0000 { 623 compatible = "qcom,sm6115-tcsr", "syscon"; 624 reg = <0x0 0x003c0000 0x0 0x40000>; 625 }; 626 627 tlmm: pinctrl@500000 { 628 compatible = "qcom,sm6115-tlmm"; 629 reg = <0x0 0x00500000 0x0 0x400000>, 630 <0x0 0x00900000 0x0 0x400000>, 631 <0x0 0x00d00000 0x0 0x400000>; 632 reg-names = "west", "south", "east"; 633 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 634 gpio-controller; 635 gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */ 636 #gpio-cells = <2>; 637 interrupt-controller; 638 #interrupt-cells = <2>; 639 640 qup_i2c0_default: qup-i2c0-default-state { 641 pins = "gpio0", "gpio1"; 642 function = "qup0"; 643 drive-strength = <2>; 644 bias-pull-up; 645 }; 646 647 qup_i2c1_default: qup-i2c1-default-state { 648 pins = "gpio4", "gpio5"; 649 function = "qup1"; 650 drive-strength = <2>; 651 bias-pull-up; 652 }; 653 654 qup_i2c2_default: qup-i2c2-default-state { 655 pins = "gpio6", "gpio7"; 656 function = "qup2"; 657 drive-strength = <2>; 658 bias-pull-up; 659 }; 660 661 qup_i2c3_default: qup-i2c3-default-state { 662 pins = "gpio8", "gpio9"; 663 function = "qup3"; 664 drive-strength = <2>; 665 bias-pull-up; 666 }; 667 668 qup_i2c4_default: qup-i2c4-default-state { 669 pins = "gpio12", "gpio13"; 670 function = "qup4"; 671 drive-strength = <2>; 672 bias-pull-up; 673 }; 674 675 qup_i2c5_default: qup-i2c5-default-state { 676 pins = "gpio14", "gpio15"; 677 function = "qup5"; 678 drive-strength = <2>; 679 bias-pull-up; 680 }; 681 682 qup_spi0_default: qup-spi0-default-state { 683 pins = "gpio0", "gpio1","gpio2", "gpio3"; 684 function = "qup0"; 685 drive-strength = <2>; 686 bias-pull-up; 687 }; 688 689 qup_spi1_default: qup-spi1-default-state { 690 pins = "gpio4", "gpio5", "gpio69", "gpio70"; 691 function = "qup1"; 692 drive-strength = <2>; 693 bias-pull-up; 694 }; 695 696 qup_spi2_default: qup-spi2-default-state { 697 pins = "gpio6", "gpio7", "gpio71", "gpio80"; 698 function = "qup2"; 699 drive-strength = <2>; 700 bias-pull-up; 701 }; 702 703 qup_spi3_default: qup-spi3-default-state { 704 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 705 function = "qup3"; 706 drive-strength = <2>; 707 bias-pull-up; 708 }; 709 710 qup_spi4_default: qup-spi4-default-state { 711 pins = "gpio12", "gpio13", "gpio96", "gpio97"; 712 function = "qup4"; 713 drive-strength = <2>; 714 bias-pull-up; 715 }; 716 717 qup_spi5_default: qup-spi5-default-state { 718 pins = "gpio14", "gpio15", "gpio16", "gpio17"; 719 function = "qup5"; 720 drive-strength = <2>; 721 bias-pull-up; 722 }; 723 724 qup_uart4_default: qup-uart4-default-state { 725 pins = "gpio12", "gpio13"; 726 function = "qup4"; 727 drive-strength = <2>; 728 bias-disable; 729 }; 730 731 sdc1_state_on: sdc1-on-state { 732 clk-pins { 733 pins = "sdc1_clk"; 734 bias-disable; 735 drive-strength = <16>; 736 }; 737 738 cmd-pins { 739 pins = "sdc1_cmd"; 740 bias-pull-up; 741 drive-strength = <10>; 742 }; 743 744 data-pins { 745 pins = "sdc1_data"; 746 bias-pull-up; 747 drive-strength = <10>; 748 }; 749 750 rclk-pins { 751 pins = "sdc1_rclk"; 752 bias-pull-down; 753 }; 754 }; 755 756 sdc1_state_off: sdc1-off-state { 757 clk-pins { 758 pins = "sdc1_clk"; 759 bias-disable; 760 drive-strength = <2>; 761 }; 762 763 cmd-pins { 764 pins = "sdc1_cmd"; 765 bias-pull-up; 766 drive-strength = <2>; 767 }; 768 769 data-pins { 770 pins = "sdc1_data"; 771 bias-pull-up; 772 drive-strength = <2>; 773 }; 774 775 rclk-pins { 776 pins = "sdc1_rclk"; 777 bias-pull-down; 778 }; 779 }; 780 781 sdc2_state_on: sdc2-on-state { 782 clk-pins { 783 pins = "sdc2_clk"; 784 bias-disable; 785 drive-strength = <16>; 786 }; 787 788 cmd-pins { 789 pins = "sdc2_cmd"; 790 bias-pull-up; 791 drive-strength = <10>; 792 }; 793 794 data-pins { 795 pins = "sdc2_data"; 796 bias-pull-up; 797 drive-strength = <10>; 798 }; 799 }; 800 801 sdc2_state_off: sdc2-off-state { 802 clk-pins { 803 pins = "sdc2_clk"; 804 bias-disable; 805 drive-strength = <2>; 806 }; 807 808 cmd-pins { 809 pins = "sdc2_cmd"; 810 bias-pull-up; 811 drive-strength = <2>; 812 }; 813 814 data-pins { 815 pins = "sdc2_data"; 816 bias-pull-up; 817 drive-strength = <2>; 818 }; 819 }; 820 }; 821 822 lpass_tlmm: pinctrl@a7c0000 { 823 compatible = "qcom,sm6115-lpass-lpi-pinctrl"; 824 reg = <0x0 0x0a7c0000 0x0 0x20000>, 825 <0x0 0x0a950000 0x0 0x10000>; 826 827 clocks = <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 828 clock-names = "audio"; 829 830 gpio-controller; 831 #gpio-cells = <2>; 832 gpio-ranges = <&lpass_tlmm 0 0 19>; 833 834 }; 835 836 gcc: clock-controller@1400000 { 837 compatible = "qcom,gcc-sm6115"; 838 reg = <0x0 0x01400000 0x0 0x1f0000>; 839 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 840 clock-names = "bi_tcxo", "sleep_clk"; 841 #clock-cells = <1>; 842 #reset-cells = <1>; 843 #power-domain-cells = <1>; 844 }; 845 846 usb_hsphy: phy@1613000 { 847 compatible = "qcom,sm6115-qusb2-phy"; 848 reg = <0x0 0x01613000 0x0 0x180>; 849 #phy-cells = <0>; 850 851 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 852 clock-names = "cfg_ahb", "ref"; 853 854 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 855 nvmem-cells = <&qusb2_hstx_trim>; 856 857 status = "disabled"; 858 }; 859 860 cryptobam: dma-controller@1b04000 { 861 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 862 reg = <0x0 0x01b04000 0x0 0x24000>; 863 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 864 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 865 clock-names = "bam_clk"; 866 #dma-cells = <1>; 867 qcom,ee = <0>; 868 qcom,controlled-remotely; 869 iommus = <&apps_smmu 0x92 0>, 870 <&apps_smmu 0x94 0x11>, 871 <&apps_smmu 0x96 0x11>, 872 <&apps_smmu 0x98 0x1>, 873 <&apps_smmu 0x9f 0>; 874 }; 875 876 crypto: crypto@1b3a000 { 877 compatible = "qcom,sm6115-qce", "qcom,ipq4019-qce", "qcom,qce"; 878 reg = <0x0 0x01b3a000 0x0 0x6000>; 879 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 880 clock-names = "core"; 881 882 dmas = <&cryptobam 6>, <&cryptobam 7>; 883 dma-names = "rx", "tx"; 884 iommus = <&apps_smmu 0x92 0>, 885 <&apps_smmu 0x94 0x11>, 886 <&apps_smmu 0x96 0x11>, 887 <&apps_smmu 0x98 0x1>, 888 <&apps_smmu 0x9f 0>; 889 }; 890 891 usb_qmpphy: phy@1615000 { 892 compatible = "qcom,sm6115-qmp-usb3-phy"; 893 reg = <0x0 0x01615000 0x0 0x1000>; 894 895 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 896 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 897 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 898 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 899 clock-names = "cfg_ahb", 900 "ref", 901 "com_aux", 902 "pipe"; 903 904 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, 905 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; 906 reset-names = "phy", "phy_phy"; 907 908 #clock-cells = <0>; 909 clock-output-names = "usb3_phy_pipe_clk_src"; 910 911 #phy-cells = <0>; 912 orientation-switch; 913 914 qcom,tcsr-reg = <&tcsr_regs 0xb244>; 915 916 status = "disabled"; 917 918 ports { 919 #address-cells = <1>; 920 #size-cells = <0>; 921 922 port@0 { 923 reg = <0>; 924 925 usb_qmpphy_out: endpoint { 926 }; 927 }; 928 929 port@1 { 930 reg = <1>; 931 932 usb_qmpphy_usb_ss_in: endpoint { 933 remote-endpoint = <&usb_dwc3_ss>; 934 }; 935 }; 936 }; 937 }; 938 939 system_noc: interconnect@1880000 { 940 compatible = "qcom,sm6115-snoc"; 941 reg = <0x0 0x01880000 0x0 0x5f080>; 942 clocks = <&gcc GCC_SYS_NOC_CPUSS_AHB_CLK>, 943 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, 944 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 945 <&rpmcc RPM_SMD_IPA_CLK>; 946 clock-names = "cpu_axi", 947 "ufs_axi", 948 "usb_axi", 949 "ipa"; 950 #interconnect-cells = <2>; 951 952 clk_virt: interconnect-clk { 953 compatible = "qcom,sm6115-clk-virt"; 954 #interconnect-cells = <2>; 955 }; 956 957 mmrt_virt: interconnect-mmrt { 958 compatible = "qcom,sm6115-mmrt-virt"; 959 #interconnect-cells = <2>; 960 }; 961 962 mmnrt_virt: interconnect-mmnrt { 963 compatible = "qcom,sm6115-mmnrt-virt"; 964 #interconnect-cells = <2>; 965 }; 966 }; 967 968 config_noc: interconnect@1900000 { 969 compatible = "qcom,sm6115-cnoc"; 970 reg = <0x0 0x01900000 0x0 0x6200>; 971 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>; 972 clock-names = "usb_axi"; 973 #interconnect-cells = <2>; 974 }; 975 976 qfprom@1b40000 { 977 compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; 978 reg = <0x0 0x01b40000 0x0 0x7000>; 979 #address-cells = <1>; 980 #size-cells = <1>; 981 982 qusb2_hstx_trim: hstx-trim@25b { 983 reg = <0x25b 0x1>; 984 bits = <1 4>; 985 }; 986 987 gpu_speed_bin: gpu-speed-bin@6006 { 988 reg = <0x6006 0x2>; 989 bits = <5 8>; 990 }; 991 }; 992 993 rng: rng@1b53000 { 994 compatible = "qcom,prng-ee"; 995 reg = <0x0 0x01b53000 0x0 0x1000>; 996 clocks = <&gcc GCC_PRNG_AHB_CLK>; 997 clock-names = "core"; 998 }; 999 1000 pmu@1b8e300 { 1001 compatible = "qcom,sm6115-cpu-bwmon", "qcom,sdm845-bwmon"; 1002 reg = <0x0 0x01b8e300 0x0 0x600>; 1003 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 1004 1005 operating-points-v2 = <&cpu_bwmon_opp_table>; 1006 interconnects = <&bimc MASTER_AMPSS_M0 RPM_ACTIVE_TAG 1007 &bimc SLAVE_EBI_CH0 RPM_ACTIVE_TAG>; 1008 1009 cpu_bwmon_opp_table: opp-table { 1010 compatible = "operating-points-v2"; 1011 1012 opp-0 { 1013 opp-peak-kBps = <(200 * 4 * 1000)>; 1014 }; 1015 1016 opp-1 { 1017 opp-peak-kBps = <(300 * 4 * 1000)>; 1018 }; 1019 1020 opp-2 { 1021 opp-peak-kBps = <(451 * 4 * 1000)>; 1022 }; 1023 1024 opp-3 { 1025 opp-peak-kBps = <(547 * 4 * 1000)>; 1026 }; 1027 1028 opp-4 { 1029 opp-peak-kBps = <(681 * 4 * 1000)>; 1030 }; 1031 1032 opp-5 { 1033 opp-peak-kBps = <(768 * 4 * 1000)>; 1034 }; 1035 1036 opp-6 { 1037 opp-peak-kBps = <(1017 * 4 * 1000)>; 1038 }; 1039 1040 opp-7 { 1041 opp-peak-kBps = <(1353 * 4 * 1000)>; 1042 }; 1043 1044 opp-8 { 1045 opp-peak-kBps = <(1555 * 4 * 1000)>; 1046 }; 1047 1048 opp-9 { 1049 opp-peak-kBps = <(1804 * 4 * 1000)>; 1050 }; 1051 }; 1052 }; 1053 1054 spmi_bus: spmi@1c40000 { 1055 compatible = "qcom,spmi-pmic-arb"; 1056 reg = <0x0 0x01c40000 0x0 0x1100>, 1057 <0x0 0x01e00000 0x0 0x2000000>, 1058 <0x0 0x03e00000 0x0 0x100000>, 1059 <0x0 0x03f00000 0x0 0xa0000>, 1060 <0x0 0x01c0a000 0x0 0x26000>; 1061 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1062 interrupt-names = "periph_irq"; 1063 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 1064 qcom,ee = <0>; 1065 qcom,channel = <0>; 1066 #address-cells = <2>; 1067 #size-cells = <0>; 1068 interrupt-controller; 1069 #interrupt-cells = <4>; 1070 }; 1071 1072 tsens0: thermal-sensor@4411000 { 1073 compatible = "qcom,sm6115-tsens", "qcom,tsens-v2"; 1074 reg = <0x0 0x04411000 0x0 0x1ff>, /* TM */ 1075 <0x0 0x04410000 0x0 0x8>; /* SROT */ 1076 #qcom,sensors = <16>; 1077 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 1078 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1079 interrupt-names = "uplow", "critical"; 1080 #thermal-sensor-cells = <1>; 1081 }; 1082 1083 bimc: interconnect@4480000 { 1084 compatible = "qcom,sm6115-bimc"; 1085 reg = <0x0 0x04480000 0x0 0x80000>; 1086 #interconnect-cells = <2>; 1087 }; 1088 1089 rpm_msg_ram: sram@45f0000 { 1090 compatible = "qcom,rpm-msg-ram"; 1091 reg = <0x0 0x045f0000 0x0 0x7000>; 1092 }; 1093 1094 sram@4690000 { 1095 compatible = "qcom,rpm-stats"; 1096 reg = <0x0 0x04690000 0x0 0x10000>; 1097 }; 1098 1099 sdhc_1: mmc@4744000 { 1100 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; 1101 reg = <0x0 0x04744000 0x0 0x1000>, 1102 <0x0 0x04745000 0x0 0x1000>, 1103 <0x0 0x04748000 0x0 0x8000>; 1104 reg-names = "hc", "cqhci", "ice"; 1105 1106 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1108 interrupt-names = "hc_irq", "pwr_irq"; 1109 1110 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1111 <&gcc GCC_SDCC1_APPS_CLK>, 1112 <&rpmcc RPM_SMD_XO_CLK_SRC>, 1113 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 1114 clock-names = "iface", "core", "xo", "ice"; 1115 1116 resets = <&gcc GCC_SDCC1_BCR>; 1117 1118 power-domains = <&rpmpd SM6115_VDDCX>; 1119 operating-points-v2 = <&sdhc1_opp_table>; 1120 iommus = <&apps_smmu 0x00c0 0x0>; 1121 interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG 1122 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, 1123 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1124 &config_noc SLAVE_SDCC_1 RPM_ALWAYS_TAG>; 1125 interconnect-names = "sdhc-ddr", 1126 "cpu-sdhc"; 1127 1128 bus-width = <8>; 1129 status = "disabled"; 1130 1131 sdhc1_opp_table: opp-table { 1132 compatible = "operating-points-v2"; 1133 1134 opp-100000000 { 1135 opp-hz = /bits/ 64 <100000000>; 1136 required-opps = <&rpmpd_opp_low_svs>; 1137 opp-peak-kBps = <250000 133320>; 1138 opp-avg-kBps = <102400 65000>; 1139 }; 1140 1141 opp-192000000 { 1142 opp-hz = /bits/ 64 <192000000>; 1143 required-opps = <&rpmpd_opp_low_svs>; 1144 opp-peak-kBps = <800000 300000>; 1145 opp-avg-kBps = <204800 200000>; 1146 }; 1147 1148 opp-384000000 { 1149 opp-hz = /bits/ 64 <384000000>; 1150 required-opps = <&rpmpd_opp_svs_plus>; 1151 opp-peak-kBps = <800000 300000>; 1152 opp-avg-kBps = <204800 200000>; 1153 }; 1154 }; 1155 }; 1156 1157 sdhc_2: mmc@4784000 { 1158 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; 1159 reg = <0x0 0x04784000 0x0 0x1000>; 1160 reg-names = "hc"; 1161 1162 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1164 interrupt-names = "hc_irq", "pwr_irq"; 1165 1166 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1167 <&gcc GCC_SDCC2_APPS_CLK>, 1168 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1169 clock-names = "iface", "core", "xo"; 1170 1171 power-domains = <&rpmpd SM6115_VDDCX>; 1172 operating-points-v2 = <&sdhc2_opp_table>; 1173 iommus = <&apps_smmu 0x00a0 0x0>; 1174 resets = <&gcc GCC_SDCC2_BCR>; 1175 interconnects = <&system_noc MASTER_SDCC_2 RPM_ALWAYS_TAG 1176 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, 1177 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1178 &config_noc SLAVE_SDCC_2 RPM_ALWAYS_TAG>; 1179 interconnect-names = "sdhc-ddr", 1180 "cpu-sdhc"; 1181 1182 bus-width = <4>; 1183 qcom,dll-config = <0x0007642c>; 1184 qcom,ddr-config = <0x80040868>; 1185 status = "disabled"; 1186 1187 sdhc2_opp_table: opp-table { 1188 compatible = "operating-points-v2"; 1189 1190 opp-100000000 { 1191 opp-hz = /bits/ 64 <100000000>; 1192 required-opps = <&rpmpd_opp_low_svs>; 1193 opp-peak-kBps = <250000 133320>; 1194 opp-avg-kBps = <261438 150000>; 1195 }; 1196 1197 opp-202000000 { 1198 opp-hz = /bits/ 64 <202000000>; 1199 required-opps = <&rpmpd_opp_nom>; 1200 opp-peak-kBps = <800000 300000>; 1201 opp-avg-kBps = <261438 300000>; 1202 }; 1203 }; 1204 }; 1205 1206 ufs_mem_hc: ufshc@4804000 { 1207 compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 1208 reg = <0x0 0x04804000 0x0 0x3000>, <0x0 0x04810000 0x0 0x8000>; 1209 reg-names = "std", "ice"; 1210 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1211 phys = <&ufs_mem_phy>; 1212 phy-names = "ufsphy"; 1213 lanes-per-direction = <1>; 1214 #reset-cells = <1>; 1215 resets = <&gcc GCC_UFS_PHY_BCR>; 1216 reset-names = "rst"; 1217 1218 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 1219 iommus = <&apps_smmu 0x100 0>; 1220 1221 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1222 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, 1223 <&gcc GCC_UFS_PHY_AHB_CLK>, 1224 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1225 <&rpmcc RPM_SMD_XO_CLK_SRC>, 1226 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1227 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1228 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1229 clock-names = "core_clk", 1230 "bus_aggr_clk", 1231 "iface_clk", 1232 "core_clk_unipro", 1233 "ref_clk", 1234 "tx_lane0_sync_clk", 1235 "rx_lane0_sync_clk", 1236 "ice_core_clk"; 1237 1238 freq-table-hz = <50000000 200000000>, 1239 <0 0>, 1240 <0 0>, 1241 <37500000 150000000>, 1242 <0 0>, 1243 <0 0>, 1244 <0 0>, 1245 <75000000 300000000>; 1246 1247 status = "disabled"; 1248 }; 1249 1250 ufs_mem_phy: phy@4807000 { 1251 compatible = "qcom,sm6115-qmp-ufs-phy"; 1252 reg = <0x0 0x04807000 0x0 0x1000>; 1253 1254 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1255 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1256 <&gcc GCC_UFS_CLKREF_CLK>; 1257 clock-names = "ref", 1258 "ref_aux", 1259 "qref"; 1260 1261 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 1262 1263 resets = <&ufs_mem_hc 0>; 1264 reset-names = "ufsphy"; 1265 1266 #phy-cells = <0>; 1267 1268 status = "disabled"; 1269 }; 1270 1271 gpi_dma0: dma-controller@4a00000 { 1272 compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma"; 1273 reg = <0x0 0x04a00000 0x0 0x60000>; 1274 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1275 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1276 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1277 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1278 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1279 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1280 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1281 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1282 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1283 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1284 dma-channels = <10>; 1285 dma-channel-mask = <0xf>; 1286 iommus = <&apps_smmu 0xf6 0x0>; 1287 #dma-cells = <3>; 1288 status = "disabled"; 1289 }; 1290 1291 qupv3_id_0: geniqup@4ac0000 { 1292 compatible = "qcom,geni-se-qup"; 1293 reg = <0x0 0x04ac0000 0x0 0x2000>; 1294 clock-names = "m-ahb", "s-ahb"; 1295 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1296 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1297 #address-cells = <2>; 1298 #size-cells = <2>; 1299 iommus = <&apps_smmu 0xe3 0x0>; 1300 ranges; 1301 status = "disabled"; 1302 1303 i2c0: i2c@4a80000 { 1304 compatible = "qcom,geni-i2c"; 1305 reg = <0x0 0x04a80000 0x0 0x4000>; 1306 clock-names = "se"; 1307 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1308 pinctrl-names = "default"; 1309 pinctrl-0 = <&qup_i2c0_default>; 1310 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1311 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1312 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1313 dma-names = "tx", "rx"; 1314 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1315 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1316 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1317 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1318 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1319 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1320 interconnect-names = "qup-core", 1321 "qup-config", 1322 "qup-memory"; 1323 #address-cells = <1>; 1324 #size-cells = <0>; 1325 status = "disabled"; 1326 }; 1327 1328 spi0: spi@4a80000 { 1329 compatible = "qcom,geni-spi"; 1330 reg = <0x0 0x04a80000 0x0 0x4000>; 1331 clock-names = "se"; 1332 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1333 pinctrl-names = "default"; 1334 pinctrl-0 = <&qup_spi0_default>; 1335 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1336 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1337 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1338 dma-names = "tx", "rx"; 1339 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1340 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1341 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1342 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1343 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1344 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1345 interconnect-names = "qup-core", 1346 "qup-config", 1347 "qup-memory"; 1348 #address-cells = <1>; 1349 #size-cells = <0>; 1350 status = "disabled"; 1351 }; 1352 1353 i2c1: i2c@4a84000 { 1354 compatible = "qcom,geni-i2c"; 1355 reg = <0x0 0x04a84000 0x0 0x4000>; 1356 clock-names = "se"; 1357 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1358 pinctrl-names = "default"; 1359 pinctrl-0 = <&qup_i2c1_default>; 1360 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1361 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1362 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1363 dma-names = "tx", "rx"; 1364 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1365 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1366 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1367 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1368 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1369 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1370 interconnect-names = "qup-core", 1371 "qup-config", 1372 "qup-memory"; 1373 #address-cells = <1>; 1374 #size-cells = <0>; 1375 status = "disabled"; 1376 }; 1377 1378 spi1: spi@4a84000 { 1379 compatible = "qcom,geni-spi"; 1380 reg = <0x0 0x04a84000 0x0 0x4000>; 1381 clock-names = "se"; 1382 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1383 pinctrl-names = "default"; 1384 pinctrl-0 = <&qup_spi1_default>; 1385 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1386 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1387 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1388 dma-names = "tx", "rx"; 1389 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1390 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1391 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1392 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1393 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1394 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1395 interconnect-names = "qup-core", 1396 "qup-config", 1397 "qup-memory"; 1398 #address-cells = <1>; 1399 #size-cells = <0>; 1400 status = "disabled"; 1401 }; 1402 1403 i2c2: i2c@4a88000 { 1404 compatible = "qcom,geni-i2c"; 1405 reg = <0x0 0x04a88000 0x0 0x4000>; 1406 clock-names = "se"; 1407 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1408 pinctrl-names = "default"; 1409 pinctrl-0 = <&qup_i2c2_default>; 1410 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1411 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1412 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1413 dma-names = "tx", "rx"; 1414 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1415 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1416 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1417 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1418 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1419 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1420 interconnect-names = "qup-core", 1421 "qup-config", 1422 "qup-memory"; 1423 #address-cells = <1>; 1424 #size-cells = <0>; 1425 status = "disabled"; 1426 }; 1427 1428 spi2: spi@4a88000 { 1429 compatible = "qcom,geni-spi"; 1430 reg = <0x0 0x04a88000 0x0 0x4000>; 1431 clock-names = "se"; 1432 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1433 pinctrl-names = "default"; 1434 pinctrl-0 = <&qup_spi2_default>; 1435 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1436 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1437 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1438 dma-names = "tx", "rx"; 1439 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1440 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1441 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1442 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1443 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1444 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1445 interconnect-names = "qup-core", 1446 "qup-config", 1447 "qup-memory"; 1448 #address-cells = <1>; 1449 #size-cells = <0>; 1450 status = "disabled"; 1451 }; 1452 1453 i2c3: i2c@4a8c000 { 1454 compatible = "qcom,geni-i2c"; 1455 reg = <0x0 0x04a8c000 0x0 0x4000>; 1456 clock-names = "se"; 1457 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1458 pinctrl-names = "default"; 1459 pinctrl-0 = <&qup_i2c3_default>; 1460 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1461 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1462 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1463 dma-names = "tx", "rx"; 1464 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1465 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1466 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1467 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1468 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1469 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1470 interconnect-names = "qup-core", 1471 "qup-config", 1472 "qup-memory"; 1473 #address-cells = <1>; 1474 #size-cells = <0>; 1475 status = "disabled"; 1476 }; 1477 1478 spi3: spi@4a8c000 { 1479 compatible = "qcom,geni-spi"; 1480 reg = <0x0 0x04a8c000 0x0 0x4000>; 1481 clock-names = "se"; 1482 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1483 pinctrl-names = "default"; 1484 pinctrl-0 = <&qup_spi3_default>; 1485 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1486 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1487 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1488 dma-names = "tx", "rx"; 1489 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1490 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1491 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1492 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1493 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1494 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1495 interconnect-names = "qup-core", 1496 "qup-config", 1497 "qup-memory"; 1498 #address-cells = <1>; 1499 #size-cells = <0>; 1500 status = "disabled"; 1501 }; 1502 1503 uart3: serial@4a8c000 { 1504 compatible = "qcom,geni-uart"; 1505 reg = <0x0 0x04a8c000 0x0 0x4000>; 1506 interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1507 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1508 clock-names = "se"; 1509 power-domains = <&rpmpd SM6115_VDDCX>; 1510 operating-points-v2 = <&qup_opp_table>; 1511 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1512 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1513 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1514 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1515 interconnect-names = "qup-core", 1516 "qup-config"; 1517 status = "disabled"; 1518 }; 1519 1520 i2c4: i2c@4a90000 { 1521 compatible = "qcom,geni-i2c"; 1522 reg = <0x0 0x04a90000 0x0 0x4000>; 1523 clock-names = "se"; 1524 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1525 pinctrl-names = "default"; 1526 pinctrl-0 = <&qup_i2c4_default>; 1527 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1528 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1529 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1530 dma-names = "tx", "rx"; 1531 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1532 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1533 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1534 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1535 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1536 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1537 interconnect-names = "qup-core", 1538 "qup-config", 1539 "qup-memory"; 1540 #address-cells = <1>; 1541 #size-cells = <0>; 1542 status = "disabled"; 1543 }; 1544 1545 spi4: spi@4a90000 { 1546 compatible = "qcom,geni-spi"; 1547 reg = <0x0 0x04a90000 0x0 0x4000>; 1548 clock-names = "se"; 1549 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1550 pinctrl-names = "default"; 1551 pinctrl-0 = <&qup_spi4_default>; 1552 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1553 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1554 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1555 dma-names = "tx", "rx"; 1556 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1557 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1558 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1559 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1560 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1561 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1562 interconnect-names = "qup-core", 1563 "qup-config", 1564 "qup-memory"; 1565 #address-cells = <1>; 1566 #size-cells = <0>; 1567 status = "disabled"; 1568 }; 1569 1570 uart4: serial@4a90000 { 1571 compatible = "qcom,geni-debug-uart"; 1572 reg = <0x0 0x04a90000 0x0 0x4000>; 1573 clock-names = "se"; 1574 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1575 pinctrl-names = "default"; 1576 pinctrl-0 = <&qup_uart4_default>; 1577 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1578 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1579 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1580 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1581 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1582 interconnect-names = "qup-core", 1583 "qup-config"; 1584 status = "disabled"; 1585 }; 1586 1587 i2c5: i2c@4a94000 { 1588 compatible = "qcom,geni-i2c"; 1589 reg = <0x0 0x04a94000 0x0 0x4000>; 1590 clock-names = "se"; 1591 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1592 pinctrl-names = "default"; 1593 pinctrl-0 = <&qup_i2c5_default>; 1594 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1595 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1596 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1597 dma-names = "tx", "rx"; 1598 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1599 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1600 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1601 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1602 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1603 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1604 interconnect-names = "qup-core", 1605 "qup-config", 1606 "qup-memory"; 1607 #address-cells = <1>; 1608 #size-cells = <0>; 1609 status = "disabled"; 1610 }; 1611 1612 spi5: spi@4a94000 { 1613 compatible = "qcom,geni-spi"; 1614 reg = <0x0 0x04a94000 0x0 0x4000>; 1615 clock-names = "se"; 1616 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1617 pinctrl-names = "default"; 1618 pinctrl-0 = <&qup_spi5_default>; 1619 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1620 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1621 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1622 dma-names = "tx", "rx"; 1623 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1624 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1625 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1626 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1627 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1628 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1629 interconnect-names = "qup-core", 1630 "qup-config", 1631 "qup-memory"; 1632 #address-cells = <1>; 1633 #size-cells = <0>; 1634 status = "disabled"; 1635 }; 1636 }; 1637 1638 usb: usb@4ef8800 { 1639 compatible = "qcom,sm6115-dwc3", "qcom,dwc3"; 1640 reg = <0x0 0x04ef8800 0x0 0x400>; 1641 #address-cells = <2>; 1642 #size-cells = <2>; 1643 ranges; 1644 1645 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1646 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1647 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1648 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1649 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1650 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1651 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo"; 1652 1653 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1654 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1655 assigned-clock-rates = <19200000>, <66666667>; 1656 1657 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 1658 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1659 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1660 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 1661 interrupt-names = "pwr_event", 1662 "qusb2_phy", 1663 "hs_phy_irq", 1664 "ss_phy_irq"; 1665 1666 resets = <&gcc GCC_USB30_PRIM_BCR>; 1667 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1668 /* TODO: USB<->IPA path */ 1669 interconnects = <&system_noc MASTER_USB3 RPM_ALWAYS_TAG 1670 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, 1671 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1672 &config_noc SLAVE_USB3 RPM_ALWAYS_TAG>; 1673 interconnect-names = "usb-ddr", 1674 "apps-usb"; 1675 1676 status = "disabled"; 1677 1678 usb_dwc3: usb@4e00000 { 1679 compatible = "snps,dwc3"; 1680 reg = <0x0 0x04e00000 0x0 0xcd00>; 1681 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1682 phys = <&usb_hsphy>, <&usb_qmpphy>; 1683 phy-names = "usb2-phy", "usb3-phy"; 1684 iommus = <&apps_smmu 0x120 0x0>; 1685 snps,dis_u2_susphy_quirk; 1686 snps,dis_enblslpm_quirk; 1687 snps,has-lpm-erratum; 1688 snps,hird-threshold = /bits/ 8 <0x10>; 1689 snps,usb3_lpm_capable; 1690 snps,parkmode-disable-ss-quirk; 1691 1692 usb-role-switch; 1693 1694 ports { 1695 #address-cells = <1>; 1696 #size-cells = <0>; 1697 1698 port@0 { 1699 reg = <0>; 1700 1701 usb_dwc3_hs: endpoint { 1702 }; 1703 }; 1704 1705 port@1 { 1706 reg = <1>; 1707 1708 usb_dwc3_ss: endpoint { 1709 remote-endpoint = <&usb_qmpphy_usb_ss_in>; 1710 }; 1711 }; 1712 }; 1713 }; 1714 }; 1715 1716 gpu: gpu@5900000 { 1717 compatible = "qcom,adreno-610.0", "qcom,adreno"; 1718 reg = <0x0 0x05900000 0x0 0x40000>, 1719 <0x0 0x0599e000 0x0 0x1000>, 1720 <0x0 0x05961000 0x0 0x800>; 1721 reg-names = "kgsl_3d0_reg_memory", 1722 "cx_mem", 1723 "cx_dbgc"; 1724 1725 /* There's no (real) GMU, so we have to handle quite a bunch of clocks! */ 1726 clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, 1727 <&gpucc GPU_CC_AHB_CLK>, 1728 <&gcc GCC_BIMC_GPU_AXI_CLK>, 1729 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1730 <&gpucc GPU_CC_CX_GMU_CLK>, 1731 <&gpucc GPU_CC_CXO_CLK>; 1732 clock-names = "core", 1733 "iface", 1734 "mem_iface", 1735 "alt_mem_iface", 1736 "gmu", 1737 "xo"; 1738 1739 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 1740 1741 iommus = <&adreno_smmu 0 1>; 1742 operating-points-v2 = <&gpu_opp_table>; 1743 power-domains = <&rpmpd SM6115_VDDCX>; 1744 qcom,gmu = <&gmu_wrapper>; 1745 1746 nvmem-cells = <&gpu_speed_bin>; 1747 nvmem-cell-names = "speed_bin"; 1748 #cooling-cells = <2>; 1749 1750 status = "disabled"; 1751 1752 gpu_zap_shader: zap-shader { 1753 memory-region = <&pil_gpu_mem>; 1754 }; 1755 1756 gpu_opp_table: opp-table { 1757 compatible = "operating-points-v2"; 1758 1759 opp-320000000 { 1760 opp-hz = /bits/ 64 <320000000>; 1761 required-opps = <&rpmpd_opp_low_svs>; 1762 opp-supported-hw = <0x1f>; 1763 }; 1764 1765 opp-465000000 { 1766 opp-hz = /bits/ 64 <465000000>; 1767 required-opps = <&rpmpd_opp_svs>; 1768 opp-supported-hw = <0x1f>; 1769 }; 1770 1771 opp-600000000 { 1772 opp-hz = /bits/ 64 <600000000>; 1773 required-opps = <&rpmpd_opp_svs_plus>; 1774 opp-supported-hw = <0x1f>; 1775 }; 1776 1777 opp-745000000 { 1778 opp-hz = /bits/ 64 <745000000>; 1779 required-opps = <&rpmpd_opp_nom>; 1780 opp-supported-hw = <0xf>; 1781 }; 1782 1783 opp-820000000 { 1784 opp-hz = /bits/ 64 <820000000>; 1785 required-opps = <&rpmpd_opp_nom_plus>; 1786 opp-supported-hw = <0x7>; 1787 }; 1788 1789 opp-900000000 { 1790 opp-hz = /bits/ 64 <900000000>; 1791 required-opps = <&rpmpd_opp_turbo>; 1792 opp-supported-hw = <0x7>; 1793 }; 1794 1795 /* Speed bin 2 can reach 950 Mhz instead of 980 like the rest. */ 1796 opp-950000000 { 1797 opp-hz = /bits/ 64 <950000000>; 1798 required-opps = <&rpmpd_opp_turbo_plus>; 1799 opp-supported-hw = <0x4>; 1800 }; 1801 1802 opp-980000000 { 1803 opp-hz = /bits/ 64 <980000000>; 1804 required-opps = <&rpmpd_opp_turbo_plus>; 1805 opp-supported-hw = <0x3>; 1806 }; 1807 }; 1808 }; 1809 1810 gmu_wrapper: gmu@596a000 { 1811 compatible = "qcom,adreno-gmu-wrapper"; 1812 reg = <0x0 0x0596a000 0x0 0x30000>; 1813 reg-names = "gmu"; 1814 power-domains = <&gpucc GPU_CX_GDSC>, 1815 <&gpucc GPU_GX_GDSC>; 1816 power-domain-names = "cx", "gx"; 1817 }; 1818 1819 gpucc: clock-controller@5990000 { 1820 compatible = "qcom,sm6115-gpucc"; 1821 reg = <0x0 0x05990000 0x0 0x9000>; 1822 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1823 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1824 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1825 #clock-cells = <1>; 1826 #reset-cells = <1>; 1827 #power-domain-cells = <1>; 1828 }; 1829 1830 adreno_smmu: iommu@59a0000 { 1831 compatible = "qcom,sm6115-smmu-500", "qcom,adreno-smmu", 1832 "qcom,smmu-500", "arm,mmu-500"; 1833 reg = <0x0 0x059a0000 0x0 0x10000>; 1834 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 1836 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1839 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1840 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 1841 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1843 1844 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1845 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1846 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1847 clock-names = "mem", 1848 "hlos", 1849 "iface"; 1850 power-domains = <&gpucc GPU_CX_GDSC>; 1851 1852 #global-interrupts = <1>; 1853 #iommu-cells = <2>; 1854 }; 1855 1856 mdss: display-subsystem@5e00000 { 1857 compatible = "qcom,sm6115-mdss"; 1858 reg = <0x0 0x05e00000 0x0 0x1000>; 1859 reg-names = "mdss"; 1860 1861 power-domains = <&dispcc MDSS_GDSC>; 1862 1863 clocks = <&gcc GCC_DISP_AHB_CLK>, 1864 <&gcc GCC_DISP_HF_AXI_CLK>, 1865 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1866 1867 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 1868 1869 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1870 interrupt-controller; 1871 #interrupt-cells = <1>; 1872 1873 iommus = <&apps_smmu 0x420 0x2>, 1874 <&apps_smmu 0x421 0x0>; 1875 1876 interconnects = <&mmrt_virt MASTER_MDP_PORT0 RPM_ALWAYS_TAG 1877 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, 1878 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1879 &config_noc SLAVE_DISPLAY_CFG RPM_ALWAYS_TAG>; 1880 interconnect-names = "mdp0-mem", 1881 "cpu-cfg"; 1882 1883 #address-cells = <2>; 1884 #size-cells = <2>; 1885 ranges; 1886 1887 status = "disabled"; 1888 1889 mdp: display-controller@5e01000 { 1890 compatible = "qcom,sm6115-dpu"; 1891 reg = <0x0 0x05e01000 0x0 0x8f000>, 1892 <0x0 0x05eb0000 0x0 0x3000>; 1893 reg-names = "mdp", "vbif"; 1894 1895 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 1896 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1897 <&dispcc DISP_CC_MDSS_MDP_CLK>, 1898 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 1899 <&dispcc DISP_CC_MDSS_ROT_CLK>, 1900 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1901 clock-names = "bus", 1902 "iface", 1903 "core", 1904 "lut", 1905 "rot", 1906 "vsync"; 1907 1908 operating-points-v2 = <&mdp_opp_table>; 1909 power-domains = <&rpmpd SM6115_VDDCX>; 1910 1911 interrupt-parent = <&mdss>; 1912 interrupts = <0>; 1913 1914 ports { 1915 #address-cells = <1>; 1916 #size-cells = <0>; 1917 1918 port@0 { 1919 reg = <0>; 1920 dpu_intf1_out: endpoint { 1921 remote-endpoint = <&mdss_dsi0_in>; 1922 }; 1923 }; 1924 }; 1925 1926 mdp_opp_table: opp-table { 1927 compatible = "operating-points-v2"; 1928 1929 opp-19200000 { 1930 opp-hz = /bits/ 64 <19200000>; 1931 required-opps = <&rpmpd_opp_min_svs>; 1932 }; 1933 1934 opp-192000000 { 1935 opp-hz = /bits/ 64 <192000000>; 1936 required-opps = <&rpmpd_opp_low_svs>; 1937 }; 1938 1939 opp-256000000 { 1940 opp-hz = /bits/ 64 <256000000>; 1941 required-opps = <&rpmpd_opp_svs>; 1942 }; 1943 1944 opp-307200000 { 1945 opp-hz = /bits/ 64 <307200000>; 1946 required-opps = <&rpmpd_opp_svs_plus>; 1947 }; 1948 1949 opp-384000000 { 1950 opp-hz = /bits/ 64 <384000000>; 1951 required-opps = <&rpmpd_opp_nom>; 1952 }; 1953 }; 1954 }; 1955 1956 mdss_dsi0: dsi@5e94000 { 1957 compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 1958 reg = <0x0 0x05e94000 0x0 0x400>; 1959 reg-names = "dsi_ctrl"; 1960 1961 interrupt-parent = <&mdss>; 1962 interrupts = <4>; 1963 1964 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 1965 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 1966 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 1967 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 1968 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1969 <&gcc GCC_DISP_HF_AXI_CLK>; 1970 clock-names = "byte", 1971 "byte_intf", 1972 "pixel", 1973 "core", 1974 "iface", 1975 "bus"; 1976 1977 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 1978 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 1979 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1980 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 1981 1982 operating-points-v2 = <&dsi_opp_table>; 1983 power-domains = <&rpmpd SM6115_VDDCX>; 1984 phys = <&mdss_dsi0_phy>; 1985 1986 #address-cells = <1>; 1987 #size-cells = <0>; 1988 1989 status = "disabled"; 1990 1991 ports { 1992 #address-cells = <1>; 1993 #size-cells = <0>; 1994 1995 port@0 { 1996 reg = <0>; 1997 mdss_dsi0_in: endpoint { 1998 remote-endpoint = <&dpu_intf1_out>; 1999 }; 2000 }; 2001 2002 port@1 { 2003 reg = <1>; 2004 mdss_dsi0_out: endpoint { 2005 }; 2006 }; 2007 }; 2008 2009 dsi_opp_table: opp-table { 2010 compatible = "operating-points-v2"; 2011 2012 opp-19200000 { 2013 opp-hz = /bits/ 64 <19200000>; 2014 required-opps = <&rpmpd_opp_min_svs>; 2015 }; 2016 2017 opp-164000000 { 2018 opp-hz = /bits/ 64 <164000000>; 2019 required-opps = <&rpmpd_opp_low_svs>; 2020 }; 2021 2022 opp-187500000 { 2023 opp-hz = /bits/ 64 <187500000>; 2024 required-opps = <&rpmpd_opp_svs>; 2025 }; 2026 }; 2027 }; 2028 2029 mdss_dsi0_phy: phy@5e94400 { 2030 compatible = "qcom,dsi-phy-14nm-2290"; 2031 reg = <0x0 0x05e94400 0x0 0x100>, 2032 <0x0 0x05e94500 0x0 0x300>, 2033 <0x0 0x05e94800 0x0 0x188>; 2034 reg-names = "dsi_phy", 2035 "dsi_phy_lane", 2036 "dsi_pll"; 2037 2038 #clock-cells = <1>; 2039 #phy-cells = <0>; 2040 2041 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2042 <&rpmcc RPM_SMD_XO_CLK_SRC>; 2043 clock-names = "iface", "ref"; 2044 2045 status = "disabled"; 2046 }; 2047 }; 2048 2049 dispcc: clock-controller@5f00000 { 2050 compatible = "qcom,sm6115-dispcc"; 2051 reg = <0x0 0x05f00000 0 0x20000>; 2052 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 2053 <&sleep_clk>, 2054 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2055 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 2056 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; 2057 #clock-cells = <1>; 2058 #reset-cells = <1>; 2059 #power-domain-cells = <1>; 2060 }; 2061 2062 remoteproc_mpss: remoteproc@6080000 { 2063 compatible = "qcom,sm6115-mpss-pas"; 2064 reg = <0x0 0x06080000 0x0 0x10000>; 2065 2066 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, 2067 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2068 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2069 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2070 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2071 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2072 interrupt-names = "wdog", "fatal", "ready", "handover", 2073 "stop-ack", "shutdown-ack"; 2074 2075 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2076 clock-names = "xo"; 2077 2078 power-domains = <&rpmpd SM6115_VDDCX>; 2079 2080 memory-region = <&pil_modem_mem>; 2081 2082 qcom,smem-states = <&modem_smp2p_out 0>; 2083 qcom,smem-state-names = "stop"; 2084 2085 status = "disabled"; 2086 2087 glink-edge { 2088 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; 2089 label = "mpss"; 2090 qcom,remote-pid = <1>; 2091 mboxes = <&apcs_glb 12>; 2092 }; 2093 }; 2094 2095 stm@8002000 { 2096 compatible = "arm,coresight-stm", "arm,primecell"; 2097 reg = <0x0 0x08002000 0x0 0x1000>, 2098 <0x0 0x0e280000 0x0 0x180000>; 2099 reg-names = "stm-base", "stm-stimulus-base"; 2100 2101 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2102 clock-names = "apb_pclk"; 2103 2104 status = "disabled"; 2105 2106 out-ports { 2107 port { 2108 stm_out: endpoint { 2109 remote-endpoint = <&funnel_in0_in>; 2110 }; 2111 }; 2112 }; 2113 }; 2114 2115 cti0: cti@8010000 { 2116 compatible = "arm,coresight-cti", "arm,primecell"; 2117 reg = <0x0 0x08010000 0x0 0x1000>; 2118 2119 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2120 clock-names = "apb_pclk"; 2121 2122 status = "disabled"; 2123 }; 2124 2125 cti1: cti@8011000 { 2126 compatible = "arm,coresight-cti", "arm,primecell"; 2127 reg = <0x0 0x08011000 0x0 0x1000>; 2128 2129 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2130 clock-names = "apb_pclk"; 2131 2132 status = "disabled"; 2133 }; 2134 2135 cti2: cti@8012000 { 2136 compatible = "arm,coresight-cti", "arm,primecell"; 2137 reg = <0x0 0x08012000 0x0 0x1000>; 2138 2139 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2140 clock-names = "apb_pclk"; 2141 2142 status = "disabled"; 2143 }; 2144 2145 cti3: cti@8013000 { 2146 compatible = "arm,coresight-cti", "arm,primecell"; 2147 reg = <0x0 0x08013000 0x0 0x1000>; 2148 2149 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2150 clock-names = "apb_pclk"; 2151 2152 status = "disabled"; 2153 }; 2154 2155 cti4: cti@8014000 { 2156 compatible = "arm,coresight-cti", "arm,primecell"; 2157 reg = <0x0 0x08014000 0x0 0x1000>; 2158 2159 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2160 clock-names = "apb_pclk"; 2161 2162 status = "disabled"; 2163 }; 2164 2165 cti5: cti@8015000 { 2166 compatible = "arm,coresight-cti", "arm,primecell"; 2167 reg = <0x0 0x08015000 0x0 0x1000>; 2168 2169 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2170 clock-names = "apb_pclk"; 2171 2172 status = "disabled"; 2173 }; 2174 2175 cti6: cti@8016000 { 2176 compatible = "arm,coresight-cti", "arm,primecell"; 2177 reg = <0x0 0x08016000 0x0 0x1000>; 2178 2179 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2180 clock-names = "apb_pclk"; 2181 2182 status = "disabled"; 2183 }; 2184 2185 cti7: cti@8017000 { 2186 compatible = "arm,coresight-cti", "arm,primecell"; 2187 reg = <0x0 0x08017000 0x0 0x1000>; 2188 2189 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2190 clock-names = "apb_pclk"; 2191 2192 status = "disabled"; 2193 }; 2194 2195 cti8: cti@8018000 { 2196 compatible = "arm,coresight-cti", "arm,primecell"; 2197 reg = <0x0 0x08018000 0x0 0x1000>; 2198 2199 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2200 clock-names = "apb_pclk"; 2201 2202 status = "disabled"; 2203 }; 2204 2205 cti9: cti@8019000 { 2206 compatible = "arm,coresight-cti", "arm,primecell"; 2207 reg = <0x0 0x08019000 0x0 0x1000>; 2208 2209 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2210 clock-names = "apb_pclk"; 2211 2212 status = "disabled"; 2213 }; 2214 2215 cti10: cti@801a000 { 2216 compatible = "arm,coresight-cti", "arm,primecell"; 2217 reg = <0x0 0x0801a000 0x0 0x1000>; 2218 2219 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2220 clock-names = "apb_pclk"; 2221 2222 status = "disabled"; 2223 }; 2224 2225 cti11: cti@801b000 { 2226 compatible = "arm,coresight-cti", "arm,primecell"; 2227 reg = <0x0 0x0801b000 0x0 0x1000>; 2228 2229 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2230 clock-names = "apb_pclk"; 2231 2232 status = "disabled"; 2233 }; 2234 2235 cti12: cti@801c000 { 2236 compatible = "arm,coresight-cti", "arm,primecell"; 2237 reg = <0x0 0x0801c000 0x0 0x1000>; 2238 2239 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2240 clock-names = "apb_pclk"; 2241 2242 status = "disabled"; 2243 }; 2244 2245 cti13: cti@801d000 { 2246 compatible = "arm,coresight-cti", "arm,primecell"; 2247 reg = <0x0 0x0801d000 0x0 0x1000>; 2248 2249 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2250 clock-names = "apb_pclk"; 2251 2252 status = "disabled"; 2253 }; 2254 2255 cti14: cti@801e000 { 2256 compatible = "arm,coresight-cti", "arm,primecell"; 2257 reg = <0x0 0x0801e000 0x0 0x1000>; 2258 2259 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2260 clock-names = "apb_pclk"; 2261 2262 status = "disabled"; 2263 }; 2264 2265 cti15: cti@801f000 { 2266 compatible = "arm,coresight-cti", "arm,primecell"; 2267 reg = <0x0 0x0801f000 0x0 0x1000>; 2268 2269 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2270 clock-names = "apb_pclk"; 2271 2272 status = "disabled"; 2273 }; 2274 2275 replicator@8046000 { 2276 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2277 reg = <0x0 0x08046000 0x0 0x1000>; 2278 2279 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2280 clock-names = "apb_pclk"; 2281 2282 status = "disabled"; 2283 2284 out-ports { 2285 port { 2286 replicator_out: endpoint { 2287 remote-endpoint = <&etr_in>; 2288 }; 2289 }; 2290 }; 2291 2292 in-ports { 2293 port { 2294 replicator_in: endpoint { 2295 remote-endpoint = <&etf_out>; 2296 }; 2297 }; 2298 }; 2299 }; 2300 2301 etf@8047000 { 2302 compatible = "arm,coresight-tmc", "arm,primecell"; 2303 reg = <0x0 0x08047000 0x0 0x1000>; 2304 2305 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2306 clock-names = "apb_pclk"; 2307 2308 status = "disabled"; 2309 2310 in-ports { 2311 port { 2312 etf_in: endpoint { 2313 remote-endpoint = <&merge_funnel_out>; 2314 }; 2315 }; 2316 }; 2317 2318 out-ports { 2319 port { 2320 etf_out: endpoint { 2321 remote-endpoint = <&replicator_in>; 2322 }; 2323 }; 2324 }; 2325 }; 2326 2327 etr@8048000 { 2328 compatible = "arm,coresight-tmc", "arm,primecell"; 2329 reg = <0x0 0x08048000 0x0 0x1000>; 2330 2331 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2332 clock-names = "apb_pclk"; 2333 2334 status = "disabled"; 2335 2336 in-ports { 2337 port { 2338 etr_in: endpoint { 2339 remote-endpoint = <&replicator_out>; 2340 }; 2341 }; 2342 }; 2343 }; 2344 2345 funnel@8041000 { 2346 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2347 reg = <0x0 0x08041000 0x0 0x1000>; 2348 2349 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2350 clock-names = "apb_pclk"; 2351 2352 status = "disabled"; 2353 2354 out-ports { 2355 port { 2356 funnel_in0_out: endpoint { 2357 remote-endpoint = <&merge_funnel_in0>; 2358 }; 2359 }; 2360 }; 2361 2362 in-ports { 2363 port { 2364 funnel_in0_in: endpoint { 2365 remote-endpoint = <&stm_out>; 2366 }; 2367 }; 2368 }; 2369 }; 2370 2371 funnel@8042000 { 2372 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2373 reg = <0x0 0x08042000 0x0 0x1000>; 2374 2375 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2376 clock-names = "apb_pclk"; 2377 2378 status = "disabled"; 2379 2380 out-ports { 2381 port { 2382 funnel_in1_out: endpoint { 2383 remote-endpoint = <&merge_funnel_in1>; 2384 }; 2385 }; 2386 }; 2387 2388 in-ports { 2389 port { 2390 funnel_in1_in: endpoint { 2391 remote-endpoint = <&funnel_apss1_out>; 2392 }; 2393 }; 2394 }; 2395 }; 2396 2397 funnel@8045000 { 2398 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2399 reg = <0x0 0x08045000 0x0 0x1000>; 2400 2401 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2402 clock-names = "apb_pclk"; 2403 2404 status = "disabled"; 2405 2406 out-ports { 2407 port { 2408 merge_funnel_out: endpoint { 2409 remote-endpoint = <&etf_in>; 2410 }; 2411 }; 2412 }; 2413 2414 in-ports { 2415 #address-cells = <1>; 2416 #size-cells = <0>; 2417 2418 port@0 { 2419 reg = <0>; 2420 merge_funnel_in0: endpoint { 2421 remote-endpoint = <&funnel_in0_out>; 2422 }; 2423 }; 2424 2425 port@1 { 2426 reg = <1>; 2427 merge_funnel_in1: endpoint { 2428 remote-endpoint = <&funnel_in1_out>; 2429 }; 2430 }; 2431 }; 2432 }; 2433 2434 etm@9040000 { 2435 compatible = "arm,coresight-etm4x", "arm,primecell"; 2436 reg = <0x0 0x09040000 0x0 0x1000>; 2437 2438 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2439 clock-names = "apb_pclk"; 2440 arm,coresight-loses-context-with-cpu; 2441 2442 cpu = <&cpu0>; 2443 2444 status = "disabled"; 2445 2446 out-ports { 2447 port { 2448 etm0_out: endpoint { 2449 remote-endpoint = <&funnel_apss0_in0>; 2450 }; 2451 }; 2452 }; 2453 }; 2454 2455 etm@9140000 { 2456 compatible = "arm,coresight-etm4x", "arm,primecell"; 2457 reg = <0x0 0x09140000 0x0 0x1000>; 2458 2459 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2460 clock-names = "apb_pclk"; 2461 arm,coresight-loses-context-with-cpu; 2462 2463 cpu = <&cpu1>; 2464 2465 status = "disabled"; 2466 2467 out-ports { 2468 port { 2469 etm1_out: endpoint { 2470 remote-endpoint = <&funnel_apss0_in1>; 2471 }; 2472 }; 2473 }; 2474 }; 2475 2476 etm@9240000 { 2477 compatible = "arm,coresight-etm4x", "arm,primecell"; 2478 reg = <0x0 0x09240000 0x0 0x1000>; 2479 2480 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2481 clock-names = "apb_pclk"; 2482 arm,coresight-loses-context-with-cpu; 2483 2484 cpu = <&cpu2>; 2485 2486 status = "disabled"; 2487 2488 out-ports { 2489 port { 2490 etm2_out: endpoint { 2491 remote-endpoint = <&funnel_apss0_in2>; 2492 }; 2493 }; 2494 }; 2495 }; 2496 2497 etm@9340000 { 2498 compatible = "arm,coresight-etm4x", "arm,primecell"; 2499 reg = <0x0 0x09340000 0x0 0x1000>; 2500 2501 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2502 clock-names = "apb_pclk"; 2503 arm,coresight-loses-context-with-cpu; 2504 2505 cpu = <&cpu3>; 2506 2507 status = "disabled"; 2508 2509 out-ports { 2510 port { 2511 etm3_out: endpoint { 2512 remote-endpoint = <&funnel_apss0_in3>; 2513 }; 2514 }; 2515 }; 2516 }; 2517 2518 etm@9440000 { 2519 compatible = "arm,coresight-etm4x", "arm,primecell"; 2520 reg = <0x0 0x09440000 0x0 0x1000>; 2521 2522 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2523 clock-names = "apb_pclk"; 2524 arm,coresight-loses-context-with-cpu; 2525 2526 cpu = <&cpu4>; 2527 2528 status = "disabled"; 2529 2530 out-ports { 2531 port { 2532 etm4_out: endpoint { 2533 remote-endpoint = <&funnel_apss0_in4>; 2534 }; 2535 }; 2536 }; 2537 }; 2538 2539 etm@9540000 { 2540 compatible = "arm,coresight-etm4x", "arm,primecell"; 2541 reg = <0x0 0x09540000 0x0 0x1000>; 2542 2543 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2544 clock-names = "apb_pclk"; 2545 arm,coresight-loses-context-with-cpu; 2546 2547 cpu = <&cpu5>; 2548 2549 status = "disabled"; 2550 2551 out-ports { 2552 port { 2553 etm5_out: endpoint { 2554 remote-endpoint = <&funnel_apss0_in5>; 2555 }; 2556 }; 2557 }; 2558 }; 2559 2560 etm@9640000 { 2561 compatible = "arm,coresight-etm4x", "arm,primecell"; 2562 reg = <0x0 0x09640000 0x0 0x1000>; 2563 2564 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2565 clock-names = "apb_pclk"; 2566 arm,coresight-loses-context-with-cpu; 2567 2568 cpu = <&cpu6>; 2569 2570 status = "disabled"; 2571 2572 out-ports { 2573 port { 2574 etm6_out: endpoint { 2575 remote-endpoint = <&funnel_apss0_in6>; 2576 }; 2577 }; 2578 }; 2579 }; 2580 2581 etm@9740000 { 2582 compatible = "arm,coresight-etm4x", "arm,primecell"; 2583 reg = <0x0 0x09740000 0x0 0x1000>; 2584 2585 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2586 clock-names = "apb_pclk"; 2587 arm,coresight-loses-context-with-cpu; 2588 2589 cpu = <&cpu7>; 2590 2591 status = "disabled"; 2592 2593 out-ports { 2594 port { 2595 etm7_out: endpoint { 2596 remote-endpoint = <&funnel_apss0_in7>; 2597 }; 2598 }; 2599 }; 2600 }; 2601 2602 funnel@9800000 { 2603 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2604 reg = <0x0 0x09800000 0x0 0x1000>; 2605 2606 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2607 clock-names = "apb_pclk"; 2608 2609 status = "disabled"; 2610 2611 out-ports { 2612 port { 2613 funnel_apss0_out: endpoint { 2614 remote-endpoint = <&funnel_apss1_in>; 2615 }; 2616 }; 2617 }; 2618 2619 in-ports { 2620 #address-cells = <1>; 2621 #size-cells = <0>; 2622 2623 port@0 { 2624 reg = <0>; 2625 funnel_apss0_in0: endpoint { 2626 remote-endpoint = <&etm0_out>; 2627 }; 2628 }; 2629 2630 port@1 { 2631 reg = <1>; 2632 funnel_apss0_in1: endpoint { 2633 remote-endpoint = <&etm1_out>; 2634 }; 2635 }; 2636 2637 port@2 { 2638 reg = <2>; 2639 funnel_apss0_in2: endpoint { 2640 remote-endpoint = <&etm2_out>; 2641 }; 2642 }; 2643 2644 port@3 { 2645 reg = <3>; 2646 funnel_apss0_in3: endpoint { 2647 remote-endpoint = <&etm3_out>; 2648 }; 2649 }; 2650 2651 port@4 { 2652 reg = <4>; 2653 funnel_apss0_in4: endpoint { 2654 remote-endpoint = <&etm4_out>; 2655 }; 2656 }; 2657 2658 port@5 { 2659 reg = <5>; 2660 funnel_apss0_in5: endpoint { 2661 remote-endpoint = <&etm5_out>; 2662 }; 2663 }; 2664 2665 port@6 { 2666 reg = <6>; 2667 funnel_apss0_in6: endpoint { 2668 remote-endpoint = <&etm6_out>; 2669 }; 2670 }; 2671 2672 port@7 { 2673 reg = <7>; 2674 funnel_apss0_in7: endpoint { 2675 remote-endpoint = <&etm7_out>; 2676 }; 2677 }; 2678 }; 2679 }; 2680 2681 funnel@9810000 { 2682 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2683 reg = <0x0 0x09810000 0x0 0x1000>; 2684 2685 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2686 clock-names = "apb_pclk"; 2687 2688 status = "disabled"; 2689 2690 out-ports { 2691 port { 2692 funnel_apss1_out: endpoint { 2693 remote-endpoint = <&funnel_in1_in>; 2694 }; 2695 }; 2696 }; 2697 2698 in-ports { 2699 port { 2700 funnel_apss1_in: endpoint { 2701 remote-endpoint = <&funnel_apss0_out>; 2702 }; 2703 }; 2704 }; 2705 }; 2706 2707 remoteproc_adsp: remoteproc@a400000 { 2708 compatible = "qcom,sm6115-adsp-pas"; 2709 reg = <0x0 0x0a400000 0x0 0x4040>; 2710 2711 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, 2712 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2713 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2714 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2715 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2716 interrupt-names = "wdog", "fatal", "ready", 2717 "handover", "stop-ack"; 2718 2719 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2720 clock-names = "xo"; 2721 2722 power-domains = <&rpmpd SM6115_VDD_LPI_CX>, 2723 <&rpmpd SM6115_VDD_LPI_MX>; 2724 2725 memory-region = <&pil_adsp_mem>; 2726 2727 qcom,smem-states = <&adsp_smp2p_out 0>; 2728 qcom,smem-state-names = "stop"; 2729 2730 status = "disabled"; 2731 2732 glink-edge { 2733 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; 2734 label = "lpass"; 2735 qcom,remote-pid = <2>; 2736 mboxes = <&apcs_glb 8>; 2737 2738 apr { 2739 compatible = "qcom,apr-v2"; 2740 qcom,glink-channels = "apr_audio_svc"; 2741 qcom,domain = <APR_DOMAIN_ADSP>; 2742 #address-cells = <1>; 2743 #size-cells = <0>; 2744 2745 service@3 { 2746 reg = <APR_SVC_ADSP_CORE>; 2747 compatible = "qcom,q6core"; 2748 qcom,protection-domain = "avs/audio", 2749 "msm/adsp/audio_pd"; 2750 }; 2751 2752 q6afe: service@4 { 2753 compatible = "qcom,q6afe"; 2754 reg = <APR_SVC_AFE>; 2755 qcom,protection-domain = "avs/audio", 2756 "msm/adsp/audio_pd"; 2757 q6afedai: dais { 2758 compatible = "qcom,q6afe-dais"; 2759 #address-cells = <1>; 2760 #size-cells = <0>; 2761 #sound-dai-cells = <1>; 2762 }; 2763 2764 q6afecc: clock-controller { 2765 compatible = "qcom,q6afe-clocks"; 2766 #clock-cells = <2>; 2767 }; 2768 }; 2769 2770 q6asm: service@7 { 2771 compatible = "qcom,q6asm"; 2772 reg = <APR_SVC_ASM>; 2773 qcom,protection-domain = "avs/audio", 2774 "msm/adsp/audio_pd"; 2775 q6asmdai: dais { 2776 compatible = "qcom,q6asm-dais"; 2777 #address-cells = <1>; 2778 #size-cells = <0>; 2779 #sound-dai-cells = <1>; 2780 iommus = <&apps_smmu 0x1c1 0x0>; 2781 2782 dai@0 { 2783 reg = <MSM_FRONTEND_DAI_MULTIMEDIA1>; 2784 }; 2785 2786 dai@1 { 2787 reg = <MSM_FRONTEND_DAI_MULTIMEDIA2>; 2788 }; 2789 2790 dai@2 { 2791 reg = <MSM_FRONTEND_DAI_MULTIMEDIA3>; 2792 }; 2793 }; 2794 }; 2795 2796 q6adm: service@8 { 2797 compatible = "qcom,q6adm"; 2798 reg = <APR_SVC_ADM>; 2799 qcom,protection-domain = "avs/audio", 2800 "msm/adsp/audio_pd"; 2801 q6routing: routing { 2802 compatible = "qcom,q6adm-routing"; 2803 #sound-dai-cells = <0>; 2804 }; 2805 }; 2806 }; 2807 2808 fastrpc { 2809 compatible = "qcom,fastrpc"; 2810 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2811 label = "adsp"; 2812 qcom,non-secure-domain; 2813 #address-cells = <1>; 2814 #size-cells = <0>; 2815 2816 compute-cb@3 { 2817 compatible = "qcom,fastrpc-compute-cb"; 2818 reg = <3>; 2819 iommus = <&apps_smmu 0x01c3 0x0>; 2820 }; 2821 2822 compute-cb@4 { 2823 compatible = "qcom,fastrpc-compute-cb"; 2824 reg = <4>; 2825 iommus = <&apps_smmu 0x01c4 0x0>; 2826 }; 2827 2828 compute-cb@5 { 2829 compatible = "qcom,fastrpc-compute-cb"; 2830 reg = <5>; 2831 iommus = <&apps_smmu 0x01c5 0x0>; 2832 }; 2833 2834 compute-cb@6 { 2835 compatible = "qcom,fastrpc-compute-cb"; 2836 reg = <6>; 2837 iommus = <&apps_smmu 0x01c6 0x0>; 2838 }; 2839 2840 compute-cb@7 { 2841 compatible = "qcom,fastrpc-compute-cb"; 2842 reg = <7>; 2843 iommus = <&apps_smmu 0x01c7 0x0>; 2844 }; 2845 }; 2846 }; 2847 }; 2848 2849 remoteproc_cdsp: remoteproc@b300000 { 2850 compatible = "qcom,sm6115-cdsp-pas"; 2851 reg = <0x0 0x0b300000 0x0 0x4040>; 2852 2853 interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 2854 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2855 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2856 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2857 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2858 interrupt-names = "wdog", "fatal", "ready", 2859 "handover", "stop-ack"; 2860 2861 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2862 clock-names = "xo"; 2863 2864 power-domains = <&rpmpd SM6115_VDDCX>; 2865 2866 memory-region = <&pil_cdsp_mem>; 2867 2868 qcom,smem-states = <&cdsp_smp2p_out 0>; 2869 qcom,smem-state-names = "stop"; 2870 2871 status = "disabled"; 2872 2873 glink-edge { 2874 interrupts = <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>; 2875 label = "cdsp"; 2876 qcom,remote-pid = <5>; 2877 mboxes = <&apcs_glb 28>; 2878 2879 fastrpc { 2880 compatible = "qcom,fastrpc"; 2881 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2882 label = "cdsp"; 2883 qcom,non-secure-domain; 2884 #address-cells = <1>; 2885 #size-cells = <0>; 2886 2887 compute-cb@1 { 2888 compatible = "qcom,fastrpc-compute-cb"; 2889 reg = <1>; 2890 iommus = <&apps_smmu 0x0c01 0x0>; 2891 }; 2892 2893 compute-cb@2 { 2894 compatible = "qcom,fastrpc-compute-cb"; 2895 reg = <2>; 2896 iommus = <&apps_smmu 0x0c02 0x0>; 2897 }; 2898 2899 compute-cb@3 { 2900 compatible = "qcom,fastrpc-compute-cb"; 2901 reg = <3>; 2902 iommus = <&apps_smmu 0x0c03 0x0>; 2903 }; 2904 2905 compute-cb@4 { 2906 compatible = "qcom,fastrpc-compute-cb"; 2907 reg = <4>; 2908 iommus = <&apps_smmu 0x0c04 0x0>; 2909 }; 2910 2911 compute-cb@5 { 2912 compatible = "qcom,fastrpc-compute-cb"; 2913 reg = <5>; 2914 iommus = <&apps_smmu 0x0c05 0x0>; 2915 }; 2916 2917 compute-cb@6 { 2918 compatible = "qcom,fastrpc-compute-cb"; 2919 reg = <6>; 2920 iommus = <&apps_smmu 0x0c06 0x0>; 2921 }; 2922 2923 /* note: secure cb9 in downstream */ 2924 }; 2925 }; 2926 }; 2927 2928 apps_smmu: iommu@c600000 { 2929 compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 2930 reg = <0x0 0x0c600000 0x0 0x80000>; 2931 #iommu-cells = <2>; 2932 #global-interrupts = <1>; 2933 2934 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 2935 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 2936 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 2937 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 2938 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 2939 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 2940 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 2941 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 2942 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 2943 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 2944 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2945 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2946 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2947 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2948 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2949 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2950 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2951 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2952 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2953 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2954 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2955 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2956 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2957 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2958 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2959 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2960 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2961 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2962 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2963 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2964 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2965 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2966 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 2967 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 2968 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 2969 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 2970 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 2971 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 2972 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2973 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 2974 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 2975 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 2976 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 2977 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2978 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2979 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 2980 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 2981 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 2982 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 2983 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2984 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 2985 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 2986 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 2987 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 2988 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2989 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2990 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2991 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2992 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2993 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2994 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2995 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2996 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2997 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 2998 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 2999 }; 3000 3001 wifi: wifi@c800000 { 3002 compatible = "qcom,wcn3990-wifi"; 3003 reg = <0x0 0x0c800000 0x0 0x800000>; 3004 reg-names = "membase"; 3005 memory-region = <&wlan_msa_mem>; 3006 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 3007 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 3008 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 3009 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 3010 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 3011 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 3012 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 3013 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 3014 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 3015 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 3016 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 3017 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 3018 iommus = <&apps_smmu 0x1a0 0x1>; 3019 qcom,msa-fixed-perm; 3020 status = "disabled"; 3021 }; 3022 3023 watchdog@f017000 { 3024 compatible = "qcom,apss-wdt-sm6115", "qcom,kpss-wdt"; 3025 reg = <0x0 0x0f017000 0x0 0x1000>; 3026 clocks = <&sleep_clk>; 3027 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 3028 }; 3029 3030 apcs_glb: mailbox@f111000 { 3031 compatible = "qcom,sm6115-apcs-hmss-global", 3032 "qcom,msm8994-apcs-kpss-global"; 3033 reg = <0x0 0x0f111000 0x0 0x1000>; 3034 3035 #mbox-cells = <1>; 3036 }; 3037 3038 timer@f120000 { 3039 compatible = "arm,armv7-timer-mem"; 3040 reg = <0x0 0x0f120000 0x0 0x1000>; 3041 #address-cells = <2>; 3042 #size-cells = <1>; 3043 ranges = <0x0 0x0 0x0 0x0 0x20000000>; 3044 clock-frequency = <19200000>; 3045 3046 frame@f121000 { 3047 reg = <0x0 0x0f121000 0x1000>, <0x0 0x0f122000 0x1000>; 3048 frame-number = <0>; 3049 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3050 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 3051 }; 3052 3053 frame@f123000 { 3054 reg = <0x0 0x0f123000 0x1000>; 3055 frame-number = <1>; 3056 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3057 status = "disabled"; 3058 }; 3059 3060 frame@f124000 { 3061 reg = <0x0 0x0f124000 0x1000>; 3062 frame-number = <2>; 3063 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3064 status = "disabled"; 3065 }; 3066 3067 frame@f125000 { 3068 reg = <0x0 0x0f125000 0x1000>; 3069 frame-number = <3>; 3070 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3071 status = "disabled"; 3072 }; 3073 3074 frame@f126000 { 3075 reg = <0x0 0x0f126000 0x1000>; 3076 frame-number = <4>; 3077 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3078 status = "disabled"; 3079 }; 3080 3081 frame@f127000 { 3082 reg = <0x0 0x0f127000 0x1000>; 3083 frame-number = <5>; 3084 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3085 status = "disabled"; 3086 }; 3087 3088 frame@f128000 { 3089 reg = <0x0 0x0f128000 0x1000>; 3090 frame-number = <6>; 3091 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3092 status = "disabled"; 3093 }; 3094 }; 3095 3096 intc: interrupt-controller@f200000 { 3097 compatible = "arm,gic-v3"; 3098 reg = <0x0 0x0f200000 0x0 0x10000>, 3099 <0x0 0x0f300000 0x0 0x100000>; 3100 #interrupt-cells = <3>; 3101 interrupt-controller; 3102 interrupt-parent = <&intc>; 3103 #redistributor-regions = <1>; 3104 redistributor-stride = <0x0 0x20000>; 3105 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3106 }; 3107 3108 cpufreq_hw: cpufreq@f521000 { 3109 compatible = "qcom,sm6115-cpufreq-hw", "qcom,cpufreq-hw"; 3110 reg = <0x0 0x0f521000 0x0 0x1000>, 3111 <0x0 0x0f523000 0x0 0x1000>; 3112 3113 reg-names = "freq-domain0", "freq-domain1"; 3114 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 3115 clock-names = "xo", "alternate"; 3116 3117 #freq-domain-cells = <1>; 3118 #clock-cells = <1>; 3119 }; 3120 }; 3121 3122 thermal-zones { 3123 mapss-thermal { 3124 thermal-sensors = <&tsens0 0>; 3125 3126 trips { 3127 trip-point0 { 3128 temperature = <115000>; 3129 hysteresis = <5000>; 3130 type = "passive"; 3131 }; 3132 3133 trip-point1 { 3134 temperature = <125000>; 3135 hysteresis = <1000>; 3136 type = "passive"; 3137 }; 3138 }; 3139 }; 3140 3141 cdsp-hvx-thermal { 3142 thermal-sensors = <&tsens0 1>; 3143 3144 trips { 3145 trip-point0 { 3146 temperature = <115000>; 3147 hysteresis = <5000>; 3148 type = "passive"; 3149 }; 3150 3151 trip-point1 { 3152 temperature = <125000>; 3153 hysteresis = <1000>; 3154 type = "passive"; 3155 }; 3156 }; 3157 }; 3158 3159 wlan-thermal { 3160 thermal-sensors = <&tsens0 2>; 3161 3162 trips { 3163 trip-point0 { 3164 temperature = <115000>; 3165 hysteresis = <5000>; 3166 type = "passive"; 3167 }; 3168 3169 trip-point1 { 3170 temperature = <125000>; 3171 hysteresis = <1000>; 3172 type = "passive"; 3173 }; 3174 }; 3175 }; 3176 3177 camera-thermal { 3178 thermal-sensors = <&tsens0 3>; 3179 3180 trips { 3181 trip-point0 { 3182 temperature = <115000>; 3183 hysteresis = <5000>; 3184 type = "passive"; 3185 }; 3186 3187 trip-point1 { 3188 temperature = <125000>; 3189 hysteresis = <1000>; 3190 type = "passive"; 3191 }; 3192 }; 3193 }; 3194 3195 video-thermal { 3196 thermal-sensors = <&tsens0 4>; 3197 3198 trips { 3199 trip-point0 { 3200 temperature = <115000>; 3201 hysteresis = <5000>; 3202 type = "passive"; 3203 }; 3204 3205 trip-point1 { 3206 temperature = <125000>; 3207 hysteresis = <1000>; 3208 type = "passive"; 3209 }; 3210 }; 3211 }; 3212 3213 modem1-thermal { 3214 thermal-sensors = <&tsens0 5>; 3215 3216 trips { 3217 trip-point0 { 3218 temperature = <115000>; 3219 hysteresis = <5000>; 3220 type = "passive"; 3221 }; 3222 3223 trip-point1 { 3224 temperature = <125000>; 3225 hysteresis = <1000>; 3226 type = "passive"; 3227 }; 3228 }; 3229 }; 3230 3231 cpu4-thermal { 3232 thermal-sensors = <&tsens0 6>; 3233 3234 trips { 3235 cpu4_alert0: trip-point0 { 3236 temperature = <90000>; 3237 hysteresis = <2000>; 3238 type = "passive"; 3239 }; 3240 3241 cpu4_alert1: trip-point1 { 3242 temperature = <95000>; 3243 hysteresis = <2000>; 3244 type = "passive"; 3245 }; 3246 3247 cpu4_crit: cpu-crit { 3248 temperature = <110000>; 3249 hysteresis = <1000>; 3250 type = "critical"; 3251 }; 3252 }; 3253 }; 3254 3255 cpu5-thermal { 3256 thermal-sensors = <&tsens0 7>; 3257 3258 trips { 3259 cpu5_alert0: trip-point0 { 3260 temperature = <90000>; 3261 hysteresis = <2000>; 3262 type = "passive"; 3263 }; 3264 3265 cpu5_alert1: trip-point1 { 3266 temperature = <95000>; 3267 hysteresis = <2000>; 3268 type = "passive"; 3269 }; 3270 3271 cpu5_crit: cpu-crit { 3272 temperature = <110000>; 3273 hysteresis = <1000>; 3274 type = "critical"; 3275 }; 3276 }; 3277 }; 3278 3279 cpu6-thermal { 3280 thermal-sensors = <&tsens0 8>; 3281 3282 trips { 3283 cpu6_alert0: trip-point0 { 3284 temperature = <90000>; 3285 hysteresis = <2000>; 3286 type = "passive"; 3287 }; 3288 3289 cpu6_alert1: trip-point1 { 3290 temperature = <95000>; 3291 hysteresis = <2000>; 3292 type = "passive"; 3293 }; 3294 3295 cpu6_crit: cpu-crit { 3296 temperature = <110000>; 3297 hysteresis = <1000>; 3298 type = "critical"; 3299 }; 3300 }; 3301 }; 3302 3303 cpu7-thermal { 3304 thermal-sensors = <&tsens0 9>; 3305 3306 trips { 3307 cpu7_alert0: trip-point0 { 3308 temperature = <90000>; 3309 hysteresis = <2000>; 3310 type = "passive"; 3311 }; 3312 3313 cpu7_alert1: trip-point1 { 3314 temperature = <95000>; 3315 hysteresis = <2000>; 3316 type = "passive"; 3317 }; 3318 3319 cpu7_crit: cpu-crit { 3320 temperature = <110000>; 3321 hysteresis = <1000>; 3322 type = "critical"; 3323 }; 3324 }; 3325 }; 3326 3327 cpu45-thermal { 3328 thermal-sensors = <&tsens0 10>; 3329 3330 trips { 3331 cpu45_alert0: trip-point0 { 3332 temperature = <90000>; 3333 hysteresis = <2000>; 3334 type = "passive"; 3335 }; 3336 3337 cpu45_alert1: trip-point1 { 3338 temperature = <95000>; 3339 hysteresis = <2000>; 3340 type = "passive"; 3341 }; 3342 3343 cpu45_crit: cpu-crit { 3344 temperature = <110000>; 3345 hysteresis = <1000>; 3346 type = "critical"; 3347 }; 3348 }; 3349 }; 3350 3351 cpu67-thermal { 3352 thermal-sensors = <&tsens0 11>; 3353 3354 trips { 3355 cpu67_alert0: trip-point0 { 3356 temperature = <90000>; 3357 hysteresis = <2000>; 3358 type = "passive"; 3359 }; 3360 3361 cpu67_alert1: trip-point1 { 3362 temperature = <95000>; 3363 hysteresis = <2000>; 3364 type = "passive"; 3365 }; 3366 3367 cpu67_crit: cpu-crit { 3368 temperature = <110000>; 3369 hysteresis = <1000>; 3370 type = "critical"; 3371 }; 3372 }; 3373 }; 3374 3375 cpu0123-thermal { 3376 thermal-sensors = <&tsens0 12>; 3377 3378 trips { 3379 cpu0123_alert0: trip-point0 { 3380 temperature = <90000>; 3381 hysteresis = <2000>; 3382 type = "passive"; 3383 }; 3384 3385 cpu0123_alert1: trip-point1 { 3386 temperature = <95000>; 3387 hysteresis = <2000>; 3388 type = "passive"; 3389 }; 3390 3391 cpu0123_crit: cpu-crit { 3392 temperature = <110000>; 3393 hysteresis = <1000>; 3394 type = "critical"; 3395 }; 3396 }; 3397 }; 3398 3399 modem0-thermal { 3400 thermal-sensors = <&tsens0 13>; 3401 3402 trips { 3403 trip-point0 { 3404 temperature = <115000>; 3405 hysteresis = <5000>; 3406 type = "passive"; 3407 }; 3408 3409 trip-point1 { 3410 temperature = <125000>; 3411 hysteresis = <1000>; 3412 type = "passive"; 3413 }; 3414 }; 3415 }; 3416 3417 display-thermal { 3418 thermal-sensors = <&tsens0 14>; 3419 3420 trips { 3421 trip-point0 { 3422 temperature = <115000>; 3423 hysteresis = <5000>; 3424 type = "passive"; 3425 }; 3426 3427 trip-point1 { 3428 temperature = <125000>; 3429 hysteresis = <1000>; 3430 type = "passive"; 3431 }; 3432 }; 3433 }; 3434 3435 gpu-thermal { 3436 polling-delay-passive = <250>; 3437 3438 thermal-sensors = <&tsens0 15>; 3439 3440 cooling-maps { 3441 map0 { 3442 trip = <&gpu_alert0>; 3443 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3444 }; 3445 }; 3446 3447 trips { 3448 gpu_alert0: trip-point0 { 3449 temperature = <85000>; 3450 hysteresis = <1000>; 3451 type = "passive"; 3452 }; 3453 3454 trip-point1 { 3455 temperature = <110000>; 3456 hysteresis = <1000>; 3457 type = "critical"; 3458 }; 3459 }; 3460 }; 3461 }; 3462 3463 timer { 3464 compatible = "arm,armv8-timer"; 3465 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 3466 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 3467 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 3468 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 3469 }; 3470}; 3471