1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com> 4 */ 5 6#include <dt-bindings/clock/qcom,gcc-sm6115.h> 7#include <dt-bindings/clock/qcom,sm6115-dispcc.h> 8#include <dt-bindings/clock/qcom,sm6115-gpucc.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/dma/qcom-gpi.h> 11#include <dt-bindings/firmware/qcom,scm.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interconnect/qcom,rpm-icc.h> 14#include <dt-bindings/interconnect/qcom,sm6115.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/power/qcom-rpmpd.h> 17#include <dt-bindings/thermal/thermal.h> 18 19/ { 20 interrupt-parent = <&intc>; 21 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 chosen { }; 26 27 clocks { 28 xo_board: xo-board { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 }; 32 33 sleep_clk: sleep-clk { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 }; 37 }; 38 39 cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 cpu0: cpu@0 { 44 device_type = "cpu"; 45 compatible = "qcom,kryo260"; 46 reg = <0x0 0x0>; 47 clocks = <&cpufreq_hw 0>; 48 capacity-dmips-mhz = <1024>; 49 dynamic-power-coefficient = <100>; 50 enable-method = "psci"; 51 next-level-cache = <&l2_0>; 52 qcom,freq-domain = <&cpufreq_hw 0>; 53 power-domains = <&cpu_pd0>; 54 power-domain-names = "psci"; 55 l2_0: l2-cache { 56 compatible = "cache"; 57 cache-level = <2>; 58 cache-unified; 59 }; 60 }; 61 62 cpu1: cpu@1 { 63 device_type = "cpu"; 64 compatible = "qcom,kryo260"; 65 reg = <0x0 0x1>; 66 clocks = <&cpufreq_hw 0>; 67 capacity-dmips-mhz = <1024>; 68 dynamic-power-coefficient = <100>; 69 enable-method = "psci"; 70 next-level-cache = <&l2_0>; 71 qcom,freq-domain = <&cpufreq_hw 0>; 72 power-domains = <&cpu_pd1>; 73 power-domain-names = "psci"; 74 }; 75 76 cpu2: cpu@2 { 77 device_type = "cpu"; 78 compatible = "qcom,kryo260"; 79 reg = <0x0 0x2>; 80 clocks = <&cpufreq_hw 0>; 81 capacity-dmips-mhz = <1024>; 82 dynamic-power-coefficient = <100>; 83 enable-method = "psci"; 84 next-level-cache = <&l2_0>; 85 qcom,freq-domain = <&cpufreq_hw 0>; 86 power-domains = <&cpu_pd2>; 87 power-domain-names = "psci"; 88 }; 89 90 cpu3: cpu@3 { 91 device_type = "cpu"; 92 compatible = "qcom,kryo260"; 93 reg = <0x0 0x3>; 94 clocks = <&cpufreq_hw 0>; 95 capacity-dmips-mhz = <1024>; 96 dynamic-power-coefficient = <100>; 97 enable-method = "psci"; 98 next-level-cache = <&l2_0>; 99 qcom,freq-domain = <&cpufreq_hw 0>; 100 power-domains = <&cpu_pd3>; 101 power-domain-names = "psci"; 102 }; 103 104 cpu4: cpu@100 { 105 device_type = "cpu"; 106 compatible = "qcom,kryo260"; 107 reg = <0x0 0x100>; 108 clocks = <&cpufreq_hw 1>; 109 enable-method = "psci"; 110 capacity-dmips-mhz = <1638>; 111 dynamic-power-coefficient = <282>; 112 next-level-cache = <&l2_1>; 113 qcom,freq-domain = <&cpufreq_hw 1>; 114 power-domains = <&cpu_pd4>; 115 power-domain-names = "psci"; 116 l2_1: l2-cache { 117 compatible = "cache"; 118 cache-level = <2>; 119 cache-unified; 120 }; 121 }; 122 123 cpu5: cpu@101 { 124 device_type = "cpu"; 125 compatible = "qcom,kryo260"; 126 reg = <0x0 0x101>; 127 clocks = <&cpufreq_hw 1>; 128 capacity-dmips-mhz = <1638>; 129 dynamic-power-coefficient = <282>; 130 enable-method = "psci"; 131 next-level-cache = <&l2_1>; 132 qcom,freq-domain = <&cpufreq_hw 1>; 133 power-domains = <&cpu_pd5>; 134 power-domain-names = "psci"; 135 }; 136 137 cpu6: cpu@102 { 138 device_type = "cpu"; 139 compatible = "qcom,kryo260"; 140 reg = <0x0 0x102>; 141 clocks = <&cpufreq_hw 1>; 142 capacity-dmips-mhz = <1638>; 143 dynamic-power-coefficient = <282>; 144 enable-method = "psci"; 145 next-level-cache = <&l2_1>; 146 qcom,freq-domain = <&cpufreq_hw 1>; 147 power-domains = <&cpu_pd6>; 148 power-domain-names = "psci"; 149 }; 150 151 cpu7: cpu@103 { 152 device_type = "cpu"; 153 compatible = "qcom,kryo260"; 154 reg = <0x0 0x103>; 155 clocks = <&cpufreq_hw 1>; 156 capacity-dmips-mhz = <1638>; 157 dynamic-power-coefficient = <282>; 158 enable-method = "psci"; 159 next-level-cache = <&l2_1>; 160 qcom,freq-domain = <&cpufreq_hw 1>; 161 power-domains = <&cpu_pd7>; 162 power-domain-names = "psci"; 163 }; 164 165 cpu-map { 166 cluster0 { 167 core0 { 168 cpu = <&cpu0>; 169 }; 170 171 core1 { 172 cpu = <&cpu1>; 173 }; 174 175 core2 { 176 cpu = <&cpu2>; 177 }; 178 179 core3 { 180 cpu = <&cpu3>; 181 }; 182 }; 183 184 cluster1 { 185 core0 { 186 cpu = <&cpu4>; 187 }; 188 189 core1 { 190 cpu = <&cpu5>; 191 }; 192 193 core2 { 194 cpu = <&cpu6>; 195 }; 196 197 core3 { 198 cpu = <&cpu7>; 199 }; 200 }; 201 }; 202 203 idle-states { 204 entry-method = "psci"; 205 206 little_cpu_sleep_0: cpu-sleep-0-0 { 207 compatible = "arm,idle-state"; 208 idle-state-name = "silver-rail-power-collapse"; 209 arm,psci-suspend-param = <0x40000003>; 210 entry-latency-us = <290>; 211 exit-latency-us = <376>; 212 min-residency-us = <1182>; 213 local-timer-stop; 214 }; 215 216 big_cpu_sleep_0: cpu-sleep-1-0 { 217 compatible = "arm,idle-state"; 218 idle-state-name = "gold-rail-power-collapse"; 219 arm,psci-suspend-param = <0x40000003>; 220 entry-latency-us = <297>; 221 exit-latency-us = <324>; 222 min-residency-us = <1110>; 223 local-timer-stop; 224 }; 225 }; 226 227 domain-idle-states { 228 cluster_0_sleep_0: cluster-sleep-0-0 { 229 /* GDHS */ 230 compatible = "domain-idle-state"; 231 arm,psci-suspend-param = <0x40000022>; 232 entry-latency-us = <360>; 233 exit-latency-us = <421>; 234 min-residency-us = <782>; 235 }; 236 237 cluster_0_sleep_1: cluster-sleep-0-1 { 238 /* Power Collapse */ 239 compatible = "domain-idle-state"; 240 arm,psci-suspend-param = <0x41000044>; 241 entry-latency-us = <800>; 242 exit-latency-us = <2118>; 243 min-residency-us = <7376>; 244 }; 245 246 cluster_1_sleep_0: cluster-sleep-1-0 { 247 /* GDHS */ 248 compatible = "domain-idle-state"; 249 arm,psci-suspend-param = <0x40000042>; 250 entry-latency-us = <314>; 251 exit-latency-us = <345>; 252 min-residency-us = <660>; 253 }; 254 255 cluster_1_sleep_1: cluster-sleep-1-1 { 256 /* Power Collapse */ 257 compatible = "domain-idle-state"; 258 arm,psci-suspend-param = <0x41000044>; 259 entry-latency-us = <640>; 260 exit-latency-us = <1654>; 261 min-residency-us = <8094>; 262 }; 263 }; 264 }; 265 266 firmware { 267 scm: scm { 268 compatible = "qcom,scm-sm6115", "qcom,scm"; 269 #reset-cells = <1>; 270 interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG 271 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 272 }; 273 }; 274 275 memory@80000000 { 276 device_type = "memory"; 277 /* We expect the bootloader to fill in the size */ 278 reg = <0 0x80000000 0 0>; 279 }; 280 281 qup_opp_table: opp-table-qup { 282 compatible = "operating-points-v2"; 283 284 opp-75000000 { 285 opp-hz = /bits/ 64 <75000000>; 286 required-opps = <&rpmpd_opp_low_svs>; 287 }; 288 289 opp-100000000 { 290 opp-hz = /bits/ 64 <100000000>; 291 required-opps = <&rpmpd_opp_svs>; 292 }; 293 294 opp-128000000 { 295 opp-hz = /bits/ 64 <128000000>; 296 required-opps = <&rpmpd_opp_nom>; 297 }; 298 }; 299 300 pmu { 301 compatible = "arm,armv8-pmuv3"; 302 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 303 }; 304 305 psci { 306 compatible = "arm,psci-1.0"; 307 method = "smc"; 308 309 cpu_pd0: power-domain-cpu0 { 310 #power-domain-cells = <0>; 311 power-domains = <&cluster_0_pd>; 312 domain-idle-states = <&little_cpu_sleep_0>; 313 }; 314 315 cpu_pd1: power-domain-cpu1 { 316 #power-domain-cells = <0>; 317 power-domains = <&cluster_0_pd>; 318 domain-idle-states = <&little_cpu_sleep_0>; 319 }; 320 321 cpu_pd2: power-domain-cpu2 { 322 #power-domain-cells = <0>; 323 power-domains = <&cluster_0_pd>; 324 domain-idle-states = <&little_cpu_sleep_0>; 325 }; 326 327 cpu_pd3: power-domain-cpu3 { 328 #power-domain-cells = <0>; 329 power-domains = <&cluster_0_pd>; 330 domain-idle-states = <&little_cpu_sleep_0>; 331 }; 332 333 cpu_pd4: power-domain-cpu4 { 334 #power-domain-cells = <0>; 335 power-domains = <&cluster_1_pd>; 336 domain-idle-states = <&big_cpu_sleep_0>; 337 }; 338 339 cpu_pd5: power-domain-cpu5 { 340 #power-domain-cells = <0>; 341 power-domains = <&cluster_1_pd>; 342 domain-idle-states = <&big_cpu_sleep_0>; 343 }; 344 345 cpu_pd6: power-domain-cpu6 { 346 #power-domain-cells = <0>; 347 power-domains = <&cluster_1_pd>; 348 domain-idle-states = <&big_cpu_sleep_0>; 349 }; 350 351 cpu_pd7: power-domain-cpu7 { 352 #power-domain-cells = <0>; 353 power-domains = <&cluster_1_pd>; 354 domain-idle-states = <&big_cpu_sleep_0>; 355 }; 356 357 cluster_0_pd: power-domain-cpu-cluster0 { 358 #power-domain-cells = <0>; 359 domain-idle-states = <&cluster_0_sleep_0>, <&cluster_0_sleep_1>; 360 }; 361 362 cluster_1_pd: power-domain-cpu-cluster1 { 363 #power-domain-cells = <0>; 364 domain-idle-states = <&cluster_1_sleep_0>, <&cluster_1_sleep_1>; 365 }; 366 }; 367 368 rpm: remoteproc { 369 compatible = "qcom,sm6115-rpm-proc", "qcom,rpm-proc"; 370 371 glink-edge { 372 compatible = "qcom,glink-rpm"; 373 374 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 375 qcom,rpm-msg-ram = <&rpm_msg_ram>; 376 mboxes = <&apcs_glb 0>; 377 378 rpm_requests: rpm-requests { 379 compatible = "qcom,rpm-sm6115", "qcom,glink-smd-rpm"; 380 qcom,glink-channels = "rpm_requests"; 381 382 rpmcc: clock-controller { 383 compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc"; 384 clocks = <&xo_board>; 385 clock-names = "xo"; 386 #clock-cells = <1>; 387 }; 388 389 rpmpd: power-controller { 390 compatible = "qcom,sm6115-rpmpd"; 391 #power-domain-cells = <1>; 392 operating-points-v2 = <&rpmpd_opp_table>; 393 394 rpmpd_opp_table: opp-table { 395 compatible = "operating-points-v2"; 396 397 rpmpd_opp_min_svs: opp1 { 398 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 399 }; 400 401 rpmpd_opp_low_svs: opp2 { 402 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 403 }; 404 405 rpmpd_opp_svs: opp3 { 406 opp-level = <RPM_SMD_LEVEL_SVS>; 407 }; 408 409 rpmpd_opp_svs_plus: opp4 { 410 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 411 }; 412 413 rpmpd_opp_nom: opp5 { 414 opp-level = <RPM_SMD_LEVEL_NOM>; 415 }; 416 417 rpmpd_opp_nom_plus: opp6 { 418 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 419 }; 420 421 rpmpd_opp_turbo: opp7 { 422 opp-level = <RPM_SMD_LEVEL_TURBO>; 423 }; 424 425 rpmpd_opp_turbo_plus: opp8 { 426 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 427 }; 428 }; 429 }; 430 }; 431 }; 432 }; 433 434 reserved_memory: reserved-memory { 435 #address-cells = <2>; 436 #size-cells = <2>; 437 ranges; 438 439 hyp_mem: memory@45700000 { 440 reg = <0x0 0x45700000 0x0 0x600000>; 441 no-map; 442 }; 443 444 xbl_aop_mem: memory@45e00000 { 445 reg = <0x0 0x45e00000 0x0 0x140000>; 446 no-map; 447 }; 448 449 sec_apps_mem: memory@45fff000 { 450 reg = <0x0 0x45fff000 0x0 0x1000>; 451 no-map; 452 }; 453 454 smem_mem: memory@46000000 { 455 compatible = "qcom,smem"; 456 reg = <0x0 0x46000000 0x0 0x200000>; 457 no-map; 458 459 hwlocks = <&tcsr_mutex 3>; 460 qcom,rpm-msg-ram = <&rpm_msg_ram>; 461 }; 462 463 cdsp_sec_mem: memory@46200000 { 464 reg = <0x0 0x46200000 0x0 0x1e00000>; 465 no-map; 466 }; 467 468 pil_modem_mem: memory@4ab00000 { 469 reg = <0x0 0x4ab00000 0x0 0x6900000>; 470 no-map; 471 }; 472 473 pil_video_mem: memory@51400000 { 474 reg = <0x0 0x51400000 0x0 0x500000>; 475 no-map; 476 }; 477 478 wlan_msa_mem: memory@51900000 { 479 reg = <0x0 0x51900000 0x0 0x100000>; 480 no-map; 481 }; 482 483 pil_cdsp_mem: memory@51a00000 { 484 reg = <0x0 0x51a00000 0x0 0x1e00000>; 485 no-map; 486 }; 487 488 pil_adsp_mem: memory@53800000 { 489 reg = <0x0 0x53800000 0x0 0x2800000>; 490 no-map; 491 }; 492 493 pil_ipa_fw_mem: memory@56100000 { 494 reg = <0x0 0x56100000 0x0 0x10000>; 495 no-map; 496 }; 497 498 pil_ipa_gsi_mem: memory@56110000 { 499 reg = <0x0 0x56110000 0x0 0x5000>; 500 no-map; 501 }; 502 503 pil_gpu_mem: memory@56115000 { 504 reg = <0x0 0x56115000 0x0 0x2000>; 505 no-map; 506 }; 507 508 cont_splash_memory: memory@5c000000 { 509 reg = <0x0 0x5c000000 0x0 0x00f00000>; 510 no-map; 511 }; 512 513 dfps_data_memory: memory@5cf00000 { 514 reg = <0x0 0x5cf00000 0x0 0x0100000>; 515 no-map; 516 }; 517 518 removed_mem: memory@60000000 { 519 reg = <0x0 0x60000000 0x0 0x3900000>; 520 no-map; 521 }; 522 523 rmtfs_mem: memory@89b01000 { 524 compatible = "qcom,rmtfs-mem"; 525 reg = <0x0 0x89b01000 0x0 0x200000>; 526 no-map; 527 528 qcom,client-id = <1>; 529 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; 530 }; 531 }; 532 533 smp2p-adsp { 534 compatible = "qcom,smp2p"; 535 qcom,smem = <443>, <429>; 536 537 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>; 538 539 mboxes = <&apcs_glb 10>; 540 541 qcom,local-pid = <0>; 542 qcom,remote-pid = <2>; 543 544 adsp_smp2p_out: master-kernel { 545 qcom,entry-name = "master-kernel"; 546 #qcom,smem-state-cells = <1>; 547 }; 548 549 adsp_smp2p_in: slave-kernel { 550 qcom,entry-name = "slave-kernel"; 551 552 interrupt-controller; 553 #interrupt-cells = <2>; 554 }; 555 }; 556 557 smp2p-cdsp { 558 compatible = "qcom,smp2p"; 559 qcom,smem = <94>, <432>; 560 561 interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>; 562 563 mboxes = <&apcs_glb 30>; 564 565 qcom,local-pid = <0>; 566 qcom,remote-pid = <5>; 567 568 cdsp_smp2p_out: master-kernel { 569 qcom,entry-name = "master-kernel"; 570 #qcom,smem-state-cells = <1>; 571 }; 572 573 cdsp_smp2p_in: slave-kernel { 574 qcom,entry-name = "slave-kernel"; 575 576 interrupt-controller; 577 #interrupt-cells = <2>; 578 }; 579 }; 580 581 smp2p-mpss { 582 compatible = "qcom,smp2p"; 583 qcom,smem = <435>, <428>; 584 585 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; 586 587 mboxes = <&apcs_glb 14>; 588 589 qcom,local-pid = <0>; 590 qcom,remote-pid = <1>; 591 592 modem_smp2p_out: master-kernel { 593 qcom,entry-name = "master-kernel"; 594 #qcom,smem-state-cells = <1>; 595 }; 596 597 modem_smp2p_in: slave-kernel { 598 qcom,entry-name = "slave-kernel"; 599 600 interrupt-controller; 601 #interrupt-cells = <2>; 602 }; 603 }; 604 605 soc: soc@0 { 606 compatible = "simple-bus"; 607 #address-cells = <2>; 608 #size-cells = <2>; 609 ranges = <0 0 0 0 0x10 0>; 610 dma-ranges = <0 0 0 0 0x10 0>; 611 612 tcsr_mutex: hwlock@340000 { 613 compatible = "qcom,tcsr-mutex"; 614 reg = <0x0 0x00340000 0x0 0x20000>; 615 #hwlock-cells = <1>; 616 }; 617 618 tcsr_regs: syscon@3c0000 { 619 compatible = "qcom,sm6115-tcsr", "syscon"; 620 reg = <0x0 0x003c0000 0x0 0x40000>; 621 }; 622 623 tlmm: pinctrl@500000 { 624 compatible = "qcom,sm6115-tlmm"; 625 reg = <0x0 0x00500000 0x0 0x400000>, 626 <0x0 0x00900000 0x0 0x400000>, 627 <0x0 0x00d00000 0x0 0x400000>; 628 reg-names = "west", "south", "east"; 629 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 630 gpio-controller; 631 gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */ 632 #gpio-cells = <2>; 633 interrupt-controller; 634 #interrupt-cells = <2>; 635 636 qup_i2c0_default: qup-i2c0-default-state { 637 pins = "gpio0", "gpio1"; 638 function = "qup0"; 639 drive-strength = <2>; 640 bias-pull-up; 641 }; 642 643 qup_i2c1_default: qup-i2c1-default-state { 644 pins = "gpio4", "gpio5"; 645 function = "qup1"; 646 drive-strength = <2>; 647 bias-pull-up; 648 }; 649 650 qup_i2c2_default: qup-i2c2-default-state { 651 pins = "gpio6", "gpio7"; 652 function = "qup2"; 653 drive-strength = <2>; 654 bias-pull-up; 655 }; 656 657 qup_i2c3_default: qup-i2c3-default-state { 658 pins = "gpio8", "gpio9"; 659 function = "qup3"; 660 drive-strength = <2>; 661 bias-pull-up; 662 }; 663 664 qup_i2c4_default: qup-i2c4-default-state { 665 pins = "gpio12", "gpio13"; 666 function = "qup4"; 667 drive-strength = <2>; 668 bias-pull-up; 669 }; 670 671 qup_i2c5_default: qup-i2c5-default-state { 672 pins = "gpio14", "gpio15"; 673 function = "qup5"; 674 drive-strength = <2>; 675 bias-pull-up; 676 }; 677 678 qup_spi0_default: qup-spi0-default-state { 679 pins = "gpio0", "gpio1","gpio2", "gpio3"; 680 function = "qup0"; 681 drive-strength = <2>; 682 bias-pull-up; 683 }; 684 685 qup_spi1_default: qup-spi1-default-state { 686 pins = "gpio4", "gpio5", "gpio69", "gpio70"; 687 function = "qup1"; 688 drive-strength = <2>; 689 bias-pull-up; 690 }; 691 692 qup_spi2_default: qup-spi2-default-state { 693 pins = "gpio6", "gpio7", "gpio71", "gpio80"; 694 function = "qup2"; 695 drive-strength = <2>; 696 bias-pull-up; 697 }; 698 699 qup_spi3_default: qup-spi3-default-state { 700 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 701 function = "qup3"; 702 drive-strength = <2>; 703 bias-pull-up; 704 }; 705 706 qup_spi4_default: qup-spi4-default-state { 707 pins = "gpio12", "gpio13", "gpio96", "gpio97"; 708 function = "qup4"; 709 drive-strength = <2>; 710 bias-pull-up; 711 }; 712 713 qup_spi5_default: qup-spi5-default-state { 714 pins = "gpio14", "gpio15", "gpio16", "gpio17"; 715 function = "qup5"; 716 drive-strength = <2>; 717 bias-pull-up; 718 }; 719 720 sdc1_state_on: sdc1-on-state { 721 clk-pins { 722 pins = "sdc1_clk"; 723 bias-disable; 724 drive-strength = <16>; 725 }; 726 727 cmd-pins { 728 pins = "sdc1_cmd"; 729 bias-pull-up; 730 drive-strength = <10>; 731 }; 732 733 data-pins { 734 pins = "sdc1_data"; 735 bias-pull-up; 736 drive-strength = <10>; 737 }; 738 739 rclk-pins { 740 pins = "sdc1_rclk"; 741 bias-pull-down; 742 }; 743 }; 744 745 sdc1_state_off: sdc1-off-state { 746 clk-pins { 747 pins = "sdc1_clk"; 748 bias-disable; 749 drive-strength = <2>; 750 }; 751 752 cmd-pins { 753 pins = "sdc1_cmd"; 754 bias-pull-up; 755 drive-strength = <2>; 756 }; 757 758 data-pins { 759 pins = "sdc1_data"; 760 bias-pull-up; 761 drive-strength = <2>; 762 }; 763 764 rclk-pins { 765 pins = "sdc1_rclk"; 766 bias-pull-down; 767 }; 768 }; 769 770 sdc2_state_on: sdc2-on-state { 771 clk-pins { 772 pins = "sdc2_clk"; 773 bias-disable; 774 drive-strength = <16>; 775 }; 776 777 cmd-pins { 778 pins = "sdc2_cmd"; 779 bias-pull-up; 780 drive-strength = <10>; 781 }; 782 783 data-pins { 784 pins = "sdc2_data"; 785 bias-pull-up; 786 drive-strength = <10>; 787 }; 788 }; 789 790 sdc2_state_off: sdc2-off-state { 791 clk-pins { 792 pins = "sdc2_clk"; 793 bias-disable; 794 drive-strength = <2>; 795 }; 796 797 cmd-pins { 798 pins = "sdc2_cmd"; 799 bias-pull-up; 800 drive-strength = <2>; 801 }; 802 803 data-pins { 804 pins = "sdc2_data"; 805 bias-pull-up; 806 drive-strength = <2>; 807 }; 808 }; 809 }; 810 811 gcc: clock-controller@1400000 { 812 compatible = "qcom,gcc-sm6115"; 813 reg = <0x0 0x01400000 0x0 0x1f0000>; 814 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 815 clock-names = "bi_tcxo", "sleep_clk"; 816 #clock-cells = <1>; 817 #reset-cells = <1>; 818 #power-domain-cells = <1>; 819 }; 820 821 usb_hsphy: phy@1613000 { 822 compatible = "qcom,sm6115-qusb2-phy"; 823 reg = <0x0 0x01613000 0x0 0x180>; 824 #phy-cells = <0>; 825 826 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 827 clock-names = "cfg_ahb", "ref"; 828 829 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 830 nvmem-cells = <&qusb2_hstx_trim>; 831 832 status = "disabled"; 833 }; 834 835 cryptobam: dma-controller@1b04000 { 836 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 837 reg = <0x0 0x01b04000 0x0 0x24000>; 838 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 839 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 840 clock-names = "bam_clk"; 841 #dma-cells = <1>; 842 qcom,ee = <0>; 843 qcom,controlled-remotely; 844 iommus = <&apps_smmu 0x92 0>, 845 <&apps_smmu 0x94 0x11>, 846 <&apps_smmu 0x96 0x11>, 847 <&apps_smmu 0x98 0x1>, 848 <&apps_smmu 0x9F 0>; 849 }; 850 851 crypto: crypto@1b3a000 { 852 compatible = "qcom,sm6115-qce", "qcom,ipq4019-qce", "qcom,qce"; 853 reg = <0x0 0x01b3a000 0x0 0x6000>; 854 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 855 clock-names = "core"; 856 857 dmas = <&cryptobam 6>, <&cryptobam 7>; 858 dma-names = "rx", "tx"; 859 iommus = <&apps_smmu 0x92 0>, 860 <&apps_smmu 0x94 0x11>, 861 <&apps_smmu 0x96 0x11>, 862 <&apps_smmu 0x98 0x1>, 863 <&apps_smmu 0x9F 0>; 864 }; 865 866 usb_qmpphy: phy@1615000 { 867 compatible = "qcom,sm6115-qmp-usb3-phy"; 868 reg = <0x0 0x01615000 0x0 0x1000>; 869 870 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 871 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 872 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 873 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 874 clock-names = "cfg_ahb", 875 "ref", 876 "com_aux", 877 "pipe"; 878 879 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, 880 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; 881 reset-names = "phy", "phy_phy"; 882 883 #clock-cells = <0>; 884 clock-output-names = "usb3_phy_pipe_clk_src"; 885 886 #phy-cells = <0>; 887 orientation-switch; 888 889 qcom,tcsr-reg = <&tcsr_regs 0xb244>; 890 891 status = "disabled"; 892 893 ports { 894 #address-cells = <1>; 895 #size-cells = <0>; 896 897 port@0 { 898 reg = <0>; 899 900 usb_qmpphy_out: endpoint { 901 }; 902 }; 903 904 port@1 { 905 reg = <1>; 906 907 usb_qmpphy_usb_ss_in: endpoint { 908 remote-endpoint = <&usb_dwc3_ss>; 909 }; 910 }; 911 }; 912 }; 913 914 system_noc: interconnect@1880000 { 915 compatible = "qcom,sm6115-snoc"; 916 reg = <0x0 0x01880000 0x0 0x5f080>; 917 clocks = <&gcc GCC_SYS_NOC_CPUSS_AHB_CLK>, 918 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, 919 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 920 <&rpmcc RPM_SMD_IPA_CLK>; 921 clock-names = "cpu_axi", 922 "ufs_axi", 923 "usb_axi", 924 "ipa"; 925 #interconnect-cells = <2>; 926 927 clk_virt: interconnect-clk { 928 compatible = "qcom,sm6115-clk-virt"; 929 #interconnect-cells = <2>; 930 }; 931 932 mmrt_virt: interconnect-mmrt { 933 compatible = "qcom,sm6115-mmrt-virt"; 934 #interconnect-cells = <2>; 935 }; 936 937 mmnrt_virt: interconnect-mmnrt { 938 compatible = "qcom,sm6115-mmnrt-virt"; 939 #interconnect-cells = <2>; 940 }; 941 }; 942 943 config_noc: interconnect@1900000 { 944 compatible = "qcom,sm6115-cnoc"; 945 reg = <0x0 0x01900000 0x0 0x6200>; 946 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>; 947 clock-names = "usb_axi"; 948 #interconnect-cells = <2>; 949 }; 950 951 qfprom@1b40000 { 952 compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; 953 reg = <0x0 0x01b40000 0x0 0x7000>; 954 #address-cells = <1>; 955 #size-cells = <1>; 956 957 qusb2_hstx_trim: hstx-trim@25b { 958 reg = <0x25b 0x1>; 959 bits = <1 4>; 960 }; 961 962 gpu_speed_bin: gpu-speed-bin@6006 { 963 reg = <0x6006 0x2>; 964 bits = <5 8>; 965 }; 966 }; 967 968 rng: rng@1b53000 { 969 compatible = "qcom,prng-ee"; 970 reg = <0x0 0x01b53000 0x0 0x1000>; 971 clocks = <&gcc GCC_PRNG_AHB_CLK>; 972 clock-names = "core"; 973 }; 974 975 pmu@1b8e300 { 976 compatible = "qcom,sm6115-cpu-bwmon", "qcom,sdm845-bwmon"; 977 reg = <0x0 0x01b8e300 0x0 0x600>; 978 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 979 980 operating-points-v2 = <&cpu_bwmon_opp_table>; 981 interconnects = <&bimc MASTER_AMPSS_M0 RPM_ACTIVE_TAG 982 &bimc SLAVE_EBI_CH0 RPM_ACTIVE_TAG>; 983 984 cpu_bwmon_opp_table: opp-table { 985 compatible = "operating-points-v2"; 986 987 opp-0 { 988 opp-peak-kBps = <(200 * 4 * 1000)>; 989 }; 990 991 opp-1 { 992 opp-peak-kBps = <(300 * 4 * 1000)>; 993 }; 994 995 opp-2 { 996 opp-peak-kBps = <(451 * 4 * 1000)>; 997 }; 998 999 opp-3 { 1000 opp-peak-kBps = <(547 * 4 * 1000)>; 1001 }; 1002 1003 opp-4 { 1004 opp-peak-kBps = <(681 * 4 * 1000)>; 1005 }; 1006 1007 opp-5 { 1008 opp-peak-kBps = <(768 * 4 * 1000)>; 1009 }; 1010 1011 opp-6 { 1012 opp-peak-kBps = <(1017 * 4 * 1000)>; 1013 }; 1014 1015 opp-7 { 1016 opp-peak-kBps = <(1353 * 4 * 1000)>; 1017 }; 1018 1019 opp-8 { 1020 opp-peak-kBps = <(1555 * 4 * 1000)>; 1021 }; 1022 1023 opp-9 { 1024 opp-peak-kBps = <(1804 * 4 * 1000)>; 1025 }; 1026 }; 1027 }; 1028 1029 spmi_bus: spmi@1c40000 { 1030 compatible = "qcom,spmi-pmic-arb"; 1031 reg = <0x0 0x01c40000 0x0 0x1100>, 1032 <0x0 0x01e00000 0x0 0x2000000>, 1033 <0x0 0x03e00000 0x0 0x100000>, 1034 <0x0 0x03f00000 0x0 0xa0000>, 1035 <0x0 0x01c0a000 0x0 0x26000>; 1036 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1037 interrupt-names = "periph_irq"; 1038 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 1039 qcom,ee = <0>; 1040 qcom,channel = <0>; 1041 #address-cells = <2>; 1042 #size-cells = <0>; 1043 interrupt-controller; 1044 #interrupt-cells = <4>; 1045 }; 1046 1047 tsens0: thermal-sensor@4411000 { 1048 compatible = "qcom,sm6115-tsens", "qcom,tsens-v2"; 1049 reg = <0x0 0x04411000 0x0 0x1ff>, /* TM */ 1050 <0x0 0x04410000 0x0 0x8>; /* SROT */ 1051 #qcom,sensors = <16>; 1052 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 1053 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1054 interrupt-names = "uplow", "critical"; 1055 #thermal-sensor-cells = <1>; 1056 }; 1057 1058 bimc: interconnect@4480000 { 1059 compatible = "qcom,sm6115-bimc"; 1060 reg = <0x0 0x04480000 0x0 0x80000>; 1061 #interconnect-cells = <2>; 1062 }; 1063 1064 rpm_msg_ram: sram@45f0000 { 1065 compatible = "qcom,rpm-msg-ram"; 1066 reg = <0x0 0x045f0000 0x0 0x7000>; 1067 }; 1068 1069 sram@4690000 { 1070 compatible = "qcom,rpm-stats"; 1071 reg = <0x0 0x04690000 0x0 0x10000>; 1072 }; 1073 1074 sdhc_1: mmc@4744000 { 1075 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; 1076 reg = <0x0 0x04744000 0x0 0x1000>, 1077 <0x0 0x04745000 0x0 0x1000>, 1078 <0x0 0x04748000 0x0 0x8000>; 1079 reg-names = "hc", "cqhci", "ice"; 1080 1081 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 1082 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1083 interrupt-names = "hc_irq", "pwr_irq"; 1084 1085 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1086 <&gcc GCC_SDCC1_APPS_CLK>, 1087 <&rpmcc RPM_SMD_XO_CLK_SRC>, 1088 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 1089 clock-names = "iface", "core", "xo", "ice"; 1090 1091 resets = <&gcc GCC_SDCC1_BCR>; 1092 1093 power-domains = <&rpmpd SM6115_VDDCX>; 1094 operating-points-v2 = <&sdhc1_opp_table>; 1095 iommus = <&apps_smmu 0x00c0 0x0>; 1096 interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG 1097 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, 1098 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1099 &config_noc SLAVE_SDCC_1 RPM_ALWAYS_TAG>; 1100 interconnect-names = "sdhc-ddr", 1101 "cpu-sdhc"; 1102 1103 bus-width = <8>; 1104 status = "disabled"; 1105 1106 sdhc1_opp_table: opp-table { 1107 compatible = "operating-points-v2"; 1108 1109 opp-100000000 { 1110 opp-hz = /bits/ 64 <100000000>; 1111 required-opps = <&rpmpd_opp_low_svs>; 1112 opp-peak-kBps = <250000 133320>; 1113 opp-avg-kBps = <102400 65000>; 1114 }; 1115 1116 opp-192000000 { 1117 opp-hz = /bits/ 64 <192000000>; 1118 required-opps = <&rpmpd_opp_low_svs>; 1119 opp-peak-kBps = <800000 300000>; 1120 opp-avg-kBps = <204800 200000>; 1121 }; 1122 1123 opp-384000000 { 1124 opp-hz = /bits/ 64 <384000000>; 1125 required-opps = <&rpmpd_opp_svs_plus>; 1126 opp-peak-kBps = <800000 300000>; 1127 opp-avg-kBps = <204800 200000>; 1128 }; 1129 }; 1130 }; 1131 1132 sdhc_2: mmc@4784000 { 1133 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; 1134 reg = <0x0 0x04784000 0x0 0x1000>; 1135 reg-names = "hc"; 1136 1137 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 1138 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1139 interrupt-names = "hc_irq", "pwr_irq"; 1140 1141 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1142 <&gcc GCC_SDCC2_APPS_CLK>, 1143 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1144 clock-names = "iface", "core", "xo"; 1145 1146 power-domains = <&rpmpd SM6115_VDDCX>; 1147 operating-points-v2 = <&sdhc2_opp_table>; 1148 iommus = <&apps_smmu 0x00a0 0x0>; 1149 resets = <&gcc GCC_SDCC2_BCR>; 1150 interconnects = <&system_noc MASTER_SDCC_2 RPM_ALWAYS_TAG 1151 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, 1152 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1153 &config_noc SLAVE_SDCC_2 RPM_ALWAYS_TAG>; 1154 interconnect-names = "sdhc-ddr", 1155 "cpu-sdhc"; 1156 1157 bus-width = <4>; 1158 qcom,dll-config = <0x0007642c>; 1159 qcom,ddr-config = <0x80040868>; 1160 status = "disabled"; 1161 1162 sdhc2_opp_table: opp-table { 1163 compatible = "operating-points-v2"; 1164 1165 opp-100000000 { 1166 opp-hz = /bits/ 64 <100000000>; 1167 required-opps = <&rpmpd_opp_low_svs>; 1168 opp-peak-kBps = <250000 133320>; 1169 opp-avg-kBps = <261438 150000>; 1170 }; 1171 1172 opp-202000000 { 1173 opp-hz = /bits/ 64 <202000000>; 1174 required-opps = <&rpmpd_opp_nom>; 1175 opp-peak-kBps = <800000 300000>; 1176 opp-avg-kBps = <261438 300000>; 1177 }; 1178 }; 1179 }; 1180 1181 ufs_mem_hc: ufshc@4804000 { 1182 compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 1183 reg = <0x0 0x04804000 0x0 0x3000>, <0x0 0x04810000 0x0 0x8000>; 1184 reg-names = "std", "ice"; 1185 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1186 phys = <&ufs_mem_phy>; 1187 phy-names = "ufsphy"; 1188 lanes-per-direction = <1>; 1189 #reset-cells = <1>; 1190 resets = <&gcc GCC_UFS_PHY_BCR>; 1191 reset-names = "rst"; 1192 1193 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 1194 iommus = <&apps_smmu 0x100 0>; 1195 1196 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1197 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, 1198 <&gcc GCC_UFS_PHY_AHB_CLK>, 1199 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1200 <&rpmcc RPM_SMD_XO_CLK_SRC>, 1201 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1202 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1203 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1204 clock-names = "core_clk", 1205 "bus_aggr_clk", 1206 "iface_clk", 1207 "core_clk_unipro", 1208 "ref_clk", 1209 "tx_lane0_sync_clk", 1210 "rx_lane0_sync_clk", 1211 "ice_core_clk"; 1212 1213 freq-table-hz = <50000000 200000000>, 1214 <0 0>, 1215 <0 0>, 1216 <37500000 150000000>, 1217 <0 0>, 1218 <0 0>, 1219 <0 0>, 1220 <75000000 300000000>; 1221 1222 status = "disabled"; 1223 }; 1224 1225 ufs_mem_phy: phy@4807000 { 1226 compatible = "qcom,sm6115-qmp-ufs-phy"; 1227 reg = <0x0 0x04807000 0x0 0x1000>; 1228 1229 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1230 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1231 <&gcc GCC_UFS_CLKREF_CLK>; 1232 clock-names = "ref", 1233 "ref_aux", 1234 "qref"; 1235 1236 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 1237 1238 resets = <&ufs_mem_hc 0>; 1239 reset-names = "ufsphy"; 1240 1241 #phy-cells = <0>; 1242 1243 status = "disabled"; 1244 }; 1245 1246 gpi_dma0: dma-controller@4a00000 { 1247 compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma"; 1248 reg = <0x0 0x04a00000 0x0 0x60000>; 1249 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1254 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1255 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1256 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1257 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1258 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1259 dma-channels = <10>; 1260 dma-channel-mask = <0xf>; 1261 iommus = <&apps_smmu 0xf6 0x0>; 1262 #dma-cells = <3>; 1263 status = "disabled"; 1264 }; 1265 1266 qupv3_id_0: geniqup@4ac0000 { 1267 compatible = "qcom,geni-se-qup"; 1268 reg = <0x0 0x04ac0000 0x0 0x2000>; 1269 clock-names = "m-ahb", "s-ahb"; 1270 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1271 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1272 #address-cells = <2>; 1273 #size-cells = <2>; 1274 iommus = <&apps_smmu 0xe3 0x0>; 1275 ranges; 1276 status = "disabled"; 1277 1278 i2c0: i2c@4a80000 { 1279 compatible = "qcom,geni-i2c"; 1280 reg = <0x0 0x04a80000 0x0 0x4000>; 1281 clock-names = "se"; 1282 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1283 pinctrl-names = "default"; 1284 pinctrl-0 = <&qup_i2c0_default>; 1285 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1286 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1287 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1288 dma-names = "tx", "rx"; 1289 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1290 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1291 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1292 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1293 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1294 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1295 interconnect-names = "qup-core", 1296 "qup-config", 1297 "qup-memory"; 1298 #address-cells = <1>; 1299 #size-cells = <0>; 1300 status = "disabled"; 1301 }; 1302 1303 spi0: spi@4a80000 { 1304 compatible = "qcom,geni-spi"; 1305 reg = <0x0 0x04a80000 0x0 0x4000>; 1306 clock-names = "se"; 1307 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1308 pinctrl-names = "default"; 1309 pinctrl-0 = <&qup_spi0_default>; 1310 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1311 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1312 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1313 dma-names = "tx", "rx"; 1314 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1315 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1316 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1317 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1318 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1319 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1320 interconnect-names = "qup-core", 1321 "qup-config", 1322 "qup-memory"; 1323 #address-cells = <1>; 1324 #size-cells = <0>; 1325 status = "disabled"; 1326 }; 1327 1328 i2c1: i2c@4a84000 { 1329 compatible = "qcom,geni-i2c"; 1330 reg = <0x0 0x04a84000 0x0 0x4000>; 1331 clock-names = "se"; 1332 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1333 pinctrl-names = "default"; 1334 pinctrl-0 = <&qup_i2c1_default>; 1335 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1336 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1337 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1338 dma-names = "tx", "rx"; 1339 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1340 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1341 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1342 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1343 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1344 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1345 interconnect-names = "qup-core", 1346 "qup-config", 1347 "qup-memory"; 1348 #address-cells = <1>; 1349 #size-cells = <0>; 1350 status = "disabled"; 1351 }; 1352 1353 spi1: spi@4a84000 { 1354 compatible = "qcom,geni-spi"; 1355 reg = <0x0 0x04a84000 0x0 0x4000>; 1356 clock-names = "se"; 1357 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1358 pinctrl-names = "default"; 1359 pinctrl-0 = <&qup_spi1_default>; 1360 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1361 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1362 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1363 dma-names = "tx", "rx"; 1364 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1365 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1366 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1367 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1368 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1369 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1370 interconnect-names = "qup-core", 1371 "qup-config", 1372 "qup-memory"; 1373 #address-cells = <1>; 1374 #size-cells = <0>; 1375 status = "disabled"; 1376 }; 1377 1378 i2c2: i2c@4a88000 { 1379 compatible = "qcom,geni-i2c"; 1380 reg = <0x0 0x04a88000 0x0 0x4000>; 1381 clock-names = "se"; 1382 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1383 pinctrl-names = "default"; 1384 pinctrl-0 = <&qup_i2c2_default>; 1385 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1386 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1387 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1388 dma-names = "tx", "rx"; 1389 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1390 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1391 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1392 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1393 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1394 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1395 interconnect-names = "qup-core", 1396 "qup-config", 1397 "qup-memory"; 1398 #address-cells = <1>; 1399 #size-cells = <0>; 1400 status = "disabled"; 1401 }; 1402 1403 spi2: spi@4a88000 { 1404 compatible = "qcom,geni-spi"; 1405 reg = <0x0 0x04a88000 0x0 0x4000>; 1406 clock-names = "se"; 1407 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1408 pinctrl-names = "default"; 1409 pinctrl-0 = <&qup_spi2_default>; 1410 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1411 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1412 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1413 dma-names = "tx", "rx"; 1414 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1415 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1416 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1417 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1418 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1419 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1420 interconnect-names = "qup-core", 1421 "qup-config", 1422 "qup-memory"; 1423 #address-cells = <1>; 1424 #size-cells = <0>; 1425 status = "disabled"; 1426 }; 1427 1428 i2c3: i2c@4a8c000 { 1429 compatible = "qcom,geni-i2c"; 1430 reg = <0x0 0x04a8c000 0x0 0x4000>; 1431 clock-names = "se"; 1432 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1433 pinctrl-names = "default"; 1434 pinctrl-0 = <&qup_i2c3_default>; 1435 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1436 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1437 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1438 dma-names = "tx", "rx"; 1439 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1440 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1441 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1442 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1443 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1444 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1445 interconnect-names = "qup-core", 1446 "qup-config", 1447 "qup-memory"; 1448 #address-cells = <1>; 1449 #size-cells = <0>; 1450 status = "disabled"; 1451 }; 1452 1453 spi3: spi@4a8c000 { 1454 compatible = "qcom,geni-spi"; 1455 reg = <0x0 0x04a8c000 0x0 0x4000>; 1456 clock-names = "se"; 1457 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1458 pinctrl-names = "default"; 1459 pinctrl-0 = <&qup_spi3_default>; 1460 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1461 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1462 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1463 dma-names = "tx", "rx"; 1464 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1465 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1466 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1467 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1468 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1469 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1470 interconnect-names = "qup-core", 1471 "qup-config", 1472 "qup-memory"; 1473 #address-cells = <1>; 1474 #size-cells = <0>; 1475 status = "disabled"; 1476 }; 1477 1478 uart3: serial@4a8c000 { 1479 compatible = "qcom,geni-uart"; 1480 reg = <0x0 0x04a8c000 0x0 0x4000>; 1481 interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1482 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1483 clock-names = "se"; 1484 power-domains = <&rpmpd SM6115_VDDCX>; 1485 operating-points-v2 = <&qup_opp_table>; 1486 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1487 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1488 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1489 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1490 interconnect-names = "qup-core", 1491 "qup-config"; 1492 status = "disabled"; 1493 }; 1494 1495 i2c4: i2c@4a90000 { 1496 compatible = "qcom,geni-i2c"; 1497 reg = <0x0 0x04a90000 0x0 0x4000>; 1498 clock-names = "se"; 1499 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1500 pinctrl-names = "default"; 1501 pinctrl-0 = <&qup_i2c4_default>; 1502 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1503 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1504 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1505 dma-names = "tx", "rx"; 1506 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1507 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1508 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1509 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1510 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1511 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1512 interconnect-names = "qup-core", 1513 "qup-config", 1514 "qup-memory"; 1515 #address-cells = <1>; 1516 #size-cells = <0>; 1517 status = "disabled"; 1518 }; 1519 1520 spi4: spi@4a90000 { 1521 compatible = "qcom,geni-spi"; 1522 reg = <0x0 0x04a90000 0x0 0x4000>; 1523 clock-names = "se"; 1524 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1525 pinctrl-names = "default"; 1526 pinctrl-0 = <&qup_spi4_default>; 1527 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1528 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1529 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1530 dma-names = "tx", "rx"; 1531 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1532 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1533 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1534 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1535 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1536 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1537 interconnect-names = "qup-core", 1538 "qup-config", 1539 "qup-memory"; 1540 #address-cells = <1>; 1541 #size-cells = <0>; 1542 status = "disabled"; 1543 }; 1544 1545 uart4: serial@4a90000 { 1546 compatible = "qcom,geni-debug-uart"; 1547 reg = <0x0 0x04a90000 0x0 0x4000>; 1548 clock-names = "se"; 1549 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1550 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1551 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1552 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1553 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1554 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1555 interconnect-names = "qup-core", 1556 "qup-config"; 1557 status = "disabled"; 1558 }; 1559 1560 i2c5: i2c@4a94000 { 1561 compatible = "qcom,geni-i2c"; 1562 reg = <0x0 0x04a94000 0x0 0x4000>; 1563 clock-names = "se"; 1564 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1565 pinctrl-names = "default"; 1566 pinctrl-0 = <&qup_i2c5_default>; 1567 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1568 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1569 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1570 dma-names = "tx", "rx"; 1571 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1572 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1573 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1574 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1575 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1576 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1577 interconnect-names = "qup-core", 1578 "qup-config", 1579 "qup-memory"; 1580 #address-cells = <1>; 1581 #size-cells = <0>; 1582 status = "disabled"; 1583 }; 1584 1585 spi5: spi@4a94000 { 1586 compatible = "qcom,geni-spi"; 1587 reg = <0x0 0x04a94000 0x0 0x4000>; 1588 clock-names = "se"; 1589 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1590 pinctrl-names = "default"; 1591 pinctrl-0 = <&qup_spi5_default>; 1592 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1593 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1594 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1595 dma-names = "tx", "rx"; 1596 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1597 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1598 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1599 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1600 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1601 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1602 interconnect-names = "qup-core", 1603 "qup-config", 1604 "qup-memory"; 1605 #address-cells = <1>; 1606 #size-cells = <0>; 1607 status = "disabled"; 1608 }; 1609 }; 1610 1611 usb: usb@4ef8800 { 1612 compatible = "qcom,sm6115-dwc3", "qcom,dwc3"; 1613 reg = <0x0 0x04ef8800 0x0 0x400>; 1614 #address-cells = <2>; 1615 #size-cells = <2>; 1616 ranges; 1617 1618 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1619 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1620 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1621 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1622 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1623 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1624 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo"; 1625 1626 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1627 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1628 assigned-clock-rates = <19200000>, <66666667>; 1629 1630 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 1631 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1632 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1633 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 1634 interrupt-names = "pwr_event", 1635 "qusb2_phy", 1636 "hs_phy_irq", 1637 "ss_phy_irq"; 1638 1639 resets = <&gcc GCC_USB30_PRIM_BCR>; 1640 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1641 /* TODO: USB<->IPA path */ 1642 interconnects = <&system_noc MASTER_USB3 RPM_ALWAYS_TAG 1643 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, 1644 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1645 &config_noc SLAVE_USB3 RPM_ALWAYS_TAG>; 1646 interconnect-names = "usb-ddr", 1647 "apps-usb"; 1648 1649 status = "disabled"; 1650 1651 usb_dwc3: usb@4e00000 { 1652 compatible = "snps,dwc3"; 1653 reg = <0x0 0x04e00000 0x0 0xcd00>; 1654 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1655 phys = <&usb_hsphy>, <&usb_qmpphy>; 1656 phy-names = "usb2-phy", "usb3-phy"; 1657 iommus = <&apps_smmu 0x120 0x0>; 1658 snps,dis_u2_susphy_quirk; 1659 snps,dis_enblslpm_quirk; 1660 snps,has-lpm-erratum; 1661 snps,hird-threshold = /bits/ 8 <0x10>; 1662 snps,usb3_lpm_capable; 1663 snps,parkmode-disable-ss-quirk; 1664 1665 usb-role-switch; 1666 1667 ports { 1668 #address-cells = <1>; 1669 #size-cells = <0>; 1670 1671 port@0 { 1672 reg = <0>; 1673 1674 usb_dwc3_hs: endpoint { 1675 }; 1676 }; 1677 1678 port@1 { 1679 reg = <1>; 1680 1681 usb_dwc3_ss: endpoint { 1682 remote-endpoint = <&usb_qmpphy_usb_ss_in>; 1683 }; 1684 }; 1685 }; 1686 }; 1687 }; 1688 1689 gpu: gpu@5900000 { 1690 compatible = "qcom,adreno-610.0", "qcom,adreno"; 1691 reg = <0x0 0x05900000 0x0 0x40000>; 1692 reg-names = "kgsl_3d0_reg_memory"; 1693 1694 /* There's no (real) GMU, so we have to handle quite a bunch of clocks! */ 1695 clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, 1696 <&gpucc GPU_CC_AHB_CLK>, 1697 <&gcc GCC_BIMC_GPU_AXI_CLK>, 1698 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1699 <&gpucc GPU_CC_CX_GMU_CLK>, 1700 <&gpucc GPU_CC_CXO_CLK>; 1701 clock-names = "core", 1702 "iface", 1703 "mem_iface", 1704 "alt_mem_iface", 1705 "gmu", 1706 "xo"; 1707 1708 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 1709 1710 iommus = <&adreno_smmu 0 1>; 1711 operating-points-v2 = <&gpu_opp_table>; 1712 power-domains = <&rpmpd SM6115_VDDCX>; 1713 qcom,gmu = <&gmu_wrapper>; 1714 1715 nvmem-cells = <&gpu_speed_bin>; 1716 nvmem-cell-names = "speed_bin"; 1717 #cooling-cells = <2>; 1718 1719 status = "disabled"; 1720 1721 zap-shader { 1722 memory-region = <&pil_gpu_mem>; 1723 }; 1724 1725 gpu_opp_table: opp-table { 1726 compatible = "operating-points-v2"; 1727 1728 opp-320000000 { 1729 opp-hz = /bits/ 64 <320000000>; 1730 required-opps = <&rpmpd_opp_low_svs>; 1731 opp-supported-hw = <0x1f>; 1732 }; 1733 1734 opp-465000000 { 1735 opp-hz = /bits/ 64 <465000000>; 1736 required-opps = <&rpmpd_opp_svs>; 1737 opp-supported-hw = <0x1f>; 1738 }; 1739 1740 opp-600000000 { 1741 opp-hz = /bits/ 64 <600000000>; 1742 required-opps = <&rpmpd_opp_svs_plus>; 1743 opp-supported-hw = <0x1f>; 1744 }; 1745 1746 opp-745000000 { 1747 opp-hz = /bits/ 64 <745000000>; 1748 required-opps = <&rpmpd_opp_nom>; 1749 opp-supported-hw = <0xf>; 1750 }; 1751 1752 opp-820000000 { 1753 opp-hz = /bits/ 64 <820000000>; 1754 required-opps = <&rpmpd_opp_nom_plus>; 1755 opp-supported-hw = <0x7>; 1756 }; 1757 1758 opp-900000000 { 1759 opp-hz = /bits/ 64 <900000000>; 1760 required-opps = <&rpmpd_opp_turbo>; 1761 opp-supported-hw = <0x7>; 1762 }; 1763 1764 /* Speed bin 2 can reach 950 Mhz instead of 980 like the rest. */ 1765 opp-950000000 { 1766 opp-hz = /bits/ 64 <950000000>; 1767 required-opps = <&rpmpd_opp_turbo_plus>; 1768 opp-supported-hw = <0x4>; 1769 }; 1770 1771 opp-980000000 { 1772 opp-hz = /bits/ 64 <980000000>; 1773 required-opps = <&rpmpd_opp_turbo_plus>; 1774 opp-supported-hw = <0x3>; 1775 }; 1776 }; 1777 }; 1778 1779 gmu_wrapper: gmu@596a000 { 1780 compatible = "qcom,adreno-gmu-wrapper"; 1781 reg = <0x0 0x0596a000 0x0 0x30000>; 1782 reg-names = "gmu"; 1783 power-domains = <&gpucc GPU_CX_GDSC>, 1784 <&gpucc GPU_GX_GDSC>; 1785 power-domain-names = "cx", "gx"; 1786 }; 1787 1788 gpucc: clock-controller@5990000 { 1789 compatible = "qcom,sm6115-gpucc"; 1790 reg = <0x0 0x05990000 0x0 0x9000>; 1791 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1792 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1793 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1794 #clock-cells = <1>; 1795 #reset-cells = <1>; 1796 #power-domain-cells = <1>; 1797 }; 1798 1799 adreno_smmu: iommu@59a0000 { 1800 compatible = "qcom,sm6115-smmu-500", "qcom,adreno-smmu", 1801 "qcom,smmu-500", "arm,mmu-500"; 1802 reg = <0x0 0x059a0000 0x0 0x10000>; 1803 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1804 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 1805 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1806 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1807 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1808 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1809 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 1810 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1811 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1812 1813 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1814 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1815 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1816 clock-names = "mem", 1817 "hlos", 1818 "iface"; 1819 power-domains = <&gpucc GPU_CX_GDSC>; 1820 1821 #global-interrupts = <1>; 1822 #iommu-cells = <2>; 1823 }; 1824 1825 mdss: display-subsystem@5e00000 { 1826 compatible = "qcom,sm6115-mdss"; 1827 reg = <0x0 0x05e00000 0x0 0x1000>; 1828 reg-names = "mdss"; 1829 1830 power-domains = <&dispcc MDSS_GDSC>; 1831 1832 clocks = <&gcc GCC_DISP_AHB_CLK>, 1833 <&gcc GCC_DISP_HF_AXI_CLK>, 1834 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1835 1836 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1837 interrupt-controller; 1838 #interrupt-cells = <1>; 1839 1840 iommus = <&apps_smmu 0x420 0x2>, 1841 <&apps_smmu 0x421 0x0>; 1842 1843 interconnects = <&mmrt_virt MASTER_MDP_PORT0 RPM_ALWAYS_TAG 1844 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, 1845 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1846 &config_noc SLAVE_DISPLAY_CFG RPM_ALWAYS_TAG>; 1847 interconnect-names = "mdp0-mem", 1848 "cpu-cfg"; 1849 1850 #address-cells = <2>; 1851 #size-cells = <2>; 1852 ranges; 1853 1854 status = "disabled"; 1855 1856 mdp: display-controller@5e01000 { 1857 compatible = "qcom,sm6115-dpu"; 1858 reg = <0x0 0x05e01000 0x0 0x8f000>, 1859 <0x0 0x05eb0000 0x0 0x2008>; 1860 reg-names = "mdp", "vbif"; 1861 1862 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 1863 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1864 <&dispcc DISP_CC_MDSS_MDP_CLK>, 1865 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 1866 <&dispcc DISP_CC_MDSS_ROT_CLK>, 1867 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1868 clock-names = "bus", 1869 "iface", 1870 "core", 1871 "lut", 1872 "rot", 1873 "vsync"; 1874 1875 operating-points-v2 = <&mdp_opp_table>; 1876 power-domains = <&rpmpd SM6115_VDDCX>; 1877 1878 interrupt-parent = <&mdss>; 1879 interrupts = <0>; 1880 1881 ports { 1882 #address-cells = <1>; 1883 #size-cells = <0>; 1884 1885 port@0 { 1886 reg = <0>; 1887 dpu_intf1_out: endpoint { 1888 remote-endpoint = <&mdss_dsi0_in>; 1889 }; 1890 }; 1891 }; 1892 1893 mdp_opp_table: opp-table { 1894 compatible = "operating-points-v2"; 1895 1896 opp-19200000 { 1897 opp-hz = /bits/ 64 <19200000>; 1898 required-opps = <&rpmpd_opp_min_svs>; 1899 }; 1900 1901 opp-192000000 { 1902 opp-hz = /bits/ 64 <192000000>; 1903 required-opps = <&rpmpd_opp_low_svs>; 1904 }; 1905 1906 opp-256000000 { 1907 opp-hz = /bits/ 64 <256000000>; 1908 required-opps = <&rpmpd_opp_svs>; 1909 }; 1910 1911 opp-307200000 { 1912 opp-hz = /bits/ 64 <307200000>; 1913 required-opps = <&rpmpd_opp_svs_plus>; 1914 }; 1915 1916 opp-384000000 { 1917 opp-hz = /bits/ 64 <384000000>; 1918 required-opps = <&rpmpd_opp_nom>; 1919 }; 1920 }; 1921 }; 1922 1923 mdss_dsi0: dsi@5e94000 { 1924 compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 1925 reg = <0x0 0x05e94000 0x0 0x400>; 1926 reg-names = "dsi_ctrl"; 1927 1928 interrupt-parent = <&mdss>; 1929 interrupts = <4>; 1930 1931 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 1932 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 1933 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 1934 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 1935 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1936 <&gcc GCC_DISP_HF_AXI_CLK>; 1937 clock-names = "byte", 1938 "byte_intf", 1939 "pixel", 1940 "core", 1941 "iface", 1942 "bus"; 1943 1944 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 1945 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 1946 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 1947 1948 operating-points-v2 = <&dsi_opp_table>; 1949 power-domains = <&rpmpd SM6115_VDDCX>; 1950 phys = <&mdss_dsi0_phy>; 1951 1952 #address-cells = <1>; 1953 #size-cells = <0>; 1954 1955 status = "disabled"; 1956 1957 ports { 1958 #address-cells = <1>; 1959 #size-cells = <0>; 1960 1961 port@0 { 1962 reg = <0>; 1963 mdss_dsi0_in: endpoint { 1964 remote-endpoint = <&dpu_intf1_out>; 1965 }; 1966 }; 1967 1968 port@1 { 1969 reg = <1>; 1970 mdss_dsi0_out: endpoint { 1971 }; 1972 }; 1973 }; 1974 1975 dsi_opp_table: opp-table { 1976 compatible = "operating-points-v2"; 1977 1978 opp-19200000 { 1979 opp-hz = /bits/ 64 <19200000>; 1980 required-opps = <&rpmpd_opp_min_svs>; 1981 }; 1982 1983 opp-164000000 { 1984 opp-hz = /bits/ 64 <164000000>; 1985 required-opps = <&rpmpd_opp_low_svs>; 1986 }; 1987 1988 opp-187500000 { 1989 opp-hz = /bits/ 64 <187500000>; 1990 required-opps = <&rpmpd_opp_svs>; 1991 }; 1992 }; 1993 }; 1994 1995 mdss_dsi0_phy: phy@5e94400 { 1996 compatible = "qcom,dsi-phy-14nm-2290"; 1997 reg = <0x0 0x05e94400 0x0 0x100>, 1998 <0x0 0x05e94500 0x0 0x300>, 1999 <0x0 0x05e94800 0x0 0x188>; 2000 reg-names = "dsi_phy", 2001 "dsi_phy_lane", 2002 "dsi_pll"; 2003 2004 #clock-cells = <1>; 2005 #phy-cells = <0>; 2006 2007 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2008 <&rpmcc RPM_SMD_XO_CLK_SRC>; 2009 clock-names = "iface", "ref"; 2010 2011 status = "disabled"; 2012 }; 2013 }; 2014 2015 dispcc: clock-controller@5f00000 { 2016 compatible = "qcom,sm6115-dispcc"; 2017 reg = <0x0 0x05f00000 0 0x20000>; 2018 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 2019 <&sleep_clk>, 2020 <&mdss_dsi0_phy 0>, 2021 <&mdss_dsi0_phy 1>, 2022 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; 2023 #clock-cells = <1>; 2024 #reset-cells = <1>; 2025 #power-domain-cells = <1>; 2026 }; 2027 2028 remoteproc_mpss: remoteproc@6080000 { 2029 compatible = "qcom,sm6115-mpss-pas"; 2030 reg = <0x0 0x06080000 0x0 0x100>; 2031 2032 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, 2033 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2034 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2035 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2036 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2037 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2038 interrupt-names = "wdog", "fatal", "ready", "handover", 2039 "stop-ack", "shutdown-ack"; 2040 2041 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2042 clock-names = "xo"; 2043 2044 power-domains = <&rpmpd SM6115_VDDCX>; 2045 2046 memory-region = <&pil_modem_mem>; 2047 2048 qcom,smem-states = <&modem_smp2p_out 0>; 2049 qcom,smem-state-names = "stop"; 2050 2051 status = "disabled"; 2052 2053 glink-edge { 2054 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; 2055 label = "mpss"; 2056 qcom,remote-pid = <1>; 2057 mboxes = <&apcs_glb 12>; 2058 }; 2059 }; 2060 2061 stm@8002000 { 2062 compatible = "arm,coresight-stm", "arm,primecell"; 2063 reg = <0x0 0x08002000 0x0 0x1000>, 2064 <0x0 0x0e280000 0x0 0x180000>; 2065 reg-names = "stm-base", "stm-stimulus-base"; 2066 2067 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2068 clock-names = "apb_pclk"; 2069 2070 status = "disabled"; 2071 2072 out-ports { 2073 port { 2074 stm_out: endpoint { 2075 remote-endpoint = <&funnel_in0_in>; 2076 }; 2077 }; 2078 }; 2079 }; 2080 2081 cti0: cti@8010000 { 2082 compatible = "arm,coresight-cti", "arm,primecell"; 2083 reg = <0x0 0x08010000 0x0 0x1000>; 2084 2085 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2086 clock-names = "apb_pclk"; 2087 2088 status = "disabled"; 2089 }; 2090 2091 cti1: cti@8011000 { 2092 compatible = "arm,coresight-cti", "arm,primecell"; 2093 reg = <0x0 0x08011000 0x0 0x1000>; 2094 2095 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2096 clock-names = "apb_pclk"; 2097 2098 status = "disabled"; 2099 }; 2100 2101 cti2: cti@8012000 { 2102 compatible = "arm,coresight-cti", "arm,primecell"; 2103 reg = <0x0 0x08012000 0x0 0x1000>; 2104 2105 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2106 clock-names = "apb_pclk"; 2107 2108 status = "disabled"; 2109 }; 2110 2111 cti3: cti@8013000 { 2112 compatible = "arm,coresight-cti", "arm,primecell"; 2113 reg = <0x0 0x08013000 0x0 0x1000>; 2114 2115 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2116 clock-names = "apb_pclk"; 2117 2118 status = "disabled"; 2119 }; 2120 2121 cti4: cti@8014000 { 2122 compatible = "arm,coresight-cti", "arm,primecell"; 2123 reg = <0x0 0x08014000 0x0 0x1000>; 2124 2125 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2126 clock-names = "apb_pclk"; 2127 2128 status = "disabled"; 2129 }; 2130 2131 cti5: cti@8015000 { 2132 compatible = "arm,coresight-cti", "arm,primecell"; 2133 reg = <0x0 0x08015000 0x0 0x1000>; 2134 2135 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2136 clock-names = "apb_pclk"; 2137 2138 status = "disabled"; 2139 }; 2140 2141 cti6: cti@8016000 { 2142 compatible = "arm,coresight-cti", "arm,primecell"; 2143 reg = <0x0 0x08016000 0x0 0x1000>; 2144 2145 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2146 clock-names = "apb_pclk"; 2147 2148 status = "disabled"; 2149 }; 2150 2151 cti7: cti@8017000 { 2152 compatible = "arm,coresight-cti", "arm,primecell"; 2153 reg = <0x0 0x08017000 0x0 0x1000>; 2154 2155 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2156 clock-names = "apb_pclk"; 2157 2158 status = "disabled"; 2159 }; 2160 2161 cti8: cti@8018000 { 2162 compatible = "arm,coresight-cti", "arm,primecell"; 2163 reg = <0x0 0x08018000 0x0 0x1000>; 2164 2165 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2166 clock-names = "apb_pclk"; 2167 2168 status = "disabled"; 2169 }; 2170 2171 cti9: cti@8019000 { 2172 compatible = "arm,coresight-cti", "arm,primecell"; 2173 reg = <0x0 0x08019000 0x0 0x1000>; 2174 2175 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2176 clock-names = "apb_pclk"; 2177 2178 status = "disabled"; 2179 }; 2180 2181 cti10: cti@801a000 { 2182 compatible = "arm,coresight-cti", "arm,primecell"; 2183 reg = <0x0 0x0801a000 0x0 0x1000>; 2184 2185 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2186 clock-names = "apb_pclk"; 2187 2188 status = "disabled"; 2189 }; 2190 2191 cti11: cti@801b000 { 2192 compatible = "arm,coresight-cti", "arm,primecell"; 2193 reg = <0x0 0x0801b000 0x0 0x1000>; 2194 2195 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2196 clock-names = "apb_pclk"; 2197 2198 status = "disabled"; 2199 }; 2200 2201 cti12: cti@801c000 { 2202 compatible = "arm,coresight-cti", "arm,primecell"; 2203 reg = <0x0 0x0801c000 0x0 0x1000>; 2204 2205 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2206 clock-names = "apb_pclk"; 2207 2208 status = "disabled"; 2209 }; 2210 2211 cti13: cti@801d000 { 2212 compatible = "arm,coresight-cti", "arm,primecell"; 2213 reg = <0x0 0x0801d000 0x0 0x1000>; 2214 2215 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2216 clock-names = "apb_pclk"; 2217 2218 status = "disabled"; 2219 }; 2220 2221 cti14: cti@801e000 { 2222 compatible = "arm,coresight-cti", "arm,primecell"; 2223 reg = <0x0 0x0801e000 0x0 0x1000>; 2224 2225 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2226 clock-names = "apb_pclk"; 2227 2228 status = "disabled"; 2229 }; 2230 2231 cti15: cti@801f000 { 2232 compatible = "arm,coresight-cti", "arm,primecell"; 2233 reg = <0x0 0x0801f000 0x0 0x1000>; 2234 2235 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2236 clock-names = "apb_pclk"; 2237 2238 status = "disabled"; 2239 }; 2240 2241 replicator@8046000 { 2242 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2243 reg = <0x0 0x08046000 0x0 0x1000>; 2244 2245 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2246 clock-names = "apb_pclk"; 2247 2248 status = "disabled"; 2249 2250 out-ports { 2251 port { 2252 replicator_out: endpoint { 2253 remote-endpoint = <&etr_in>; 2254 }; 2255 }; 2256 }; 2257 2258 in-ports { 2259 port { 2260 replicator_in: endpoint { 2261 remote-endpoint = <&etf_out>; 2262 }; 2263 }; 2264 }; 2265 }; 2266 2267 etf@8047000 { 2268 compatible = "arm,coresight-tmc", "arm,primecell"; 2269 reg = <0x0 0x08047000 0x0 0x1000>; 2270 2271 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2272 clock-names = "apb_pclk"; 2273 2274 status = "disabled"; 2275 2276 in-ports { 2277 port { 2278 etf_in: endpoint { 2279 remote-endpoint = <&merge_funnel_out>; 2280 }; 2281 }; 2282 }; 2283 2284 out-ports { 2285 port { 2286 etf_out: endpoint { 2287 remote-endpoint = <&replicator_in>; 2288 }; 2289 }; 2290 }; 2291 }; 2292 2293 etr@8048000 { 2294 compatible = "arm,coresight-tmc", "arm,primecell"; 2295 reg = <0x0 0x08048000 0x0 0x1000>; 2296 2297 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2298 clock-names = "apb_pclk"; 2299 2300 status = "disabled"; 2301 2302 in-ports { 2303 port { 2304 etr_in: endpoint { 2305 remote-endpoint = <&replicator_out>; 2306 }; 2307 }; 2308 }; 2309 }; 2310 2311 funnel@8041000 { 2312 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2313 reg = <0x0 0x08041000 0x0 0x1000>; 2314 2315 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2316 clock-names = "apb_pclk"; 2317 2318 status = "disabled"; 2319 2320 out-ports { 2321 port { 2322 funnel_in0_out: endpoint { 2323 remote-endpoint = <&merge_funnel_in0>; 2324 }; 2325 }; 2326 }; 2327 2328 in-ports { 2329 port { 2330 funnel_in0_in: endpoint { 2331 remote-endpoint = <&stm_out>; 2332 }; 2333 }; 2334 }; 2335 }; 2336 2337 funnel@8042000 { 2338 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2339 reg = <0x0 0x08042000 0x0 0x1000>; 2340 2341 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2342 clock-names = "apb_pclk"; 2343 2344 status = "disabled"; 2345 2346 out-ports { 2347 port { 2348 funnel_in1_out: endpoint { 2349 remote-endpoint = <&merge_funnel_in1>; 2350 }; 2351 }; 2352 }; 2353 2354 in-ports { 2355 port { 2356 funnel_in1_in: endpoint { 2357 remote-endpoint = <&funnel_apss1_out>; 2358 }; 2359 }; 2360 }; 2361 }; 2362 2363 funnel@8045000 { 2364 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2365 reg = <0x0 0x08045000 0x0 0x1000>; 2366 2367 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2368 clock-names = "apb_pclk"; 2369 2370 status = "disabled"; 2371 2372 out-ports { 2373 port { 2374 merge_funnel_out: endpoint { 2375 remote-endpoint = <&etf_in>; 2376 }; 2377 }; 2378 }; 2379 2380 in-ports { 2381 #address-cells = <1>; 2382 #size-cells = <0>; 2383 2384 port@0 { 2385 reg = <0>; 2386 merge_funnel_in0: endpoint { 2387 remote-endpoint = <&funnel_in0_out>; 2388 }; 2389 }; 2390 2391 port@1 { 2392 reg = <1>; 2393 merge_funnel_in1: endpoint { 2394 remote-endpoint = <&funnel_in1_out>; 2395 }; 2396 }; 2397 }; 2398 }; 2399 2400 etm@9040000 { 2401 compatible = "arm,coresight-etm4x", "arm,primecell"; 2402 reg = <0x0 0x09040000 0x0 0x1000>; 2403 2404 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2405 clock-names = "apb_pclk"; 2406 arm,coresight-loses-context-with-cpu; 2407 2408 cpu = <&cpu0>; 2409 2410 status = "disabled"; 2411 2412 out-ports { 2413 port { 2414 etm0_out: endpoint { 2415 remote-endpoint = <&funnel_apss0_in0>; 2416 }; 2417 }; 2418 }; 2419 }; 2420 2421 etm@9140000 { 2422 compatible = "arm,coresight-etm4x", "arm,primecell"; 2423 reg = <0x0 0x09140000 0x0 0x1000>; 2424 2425 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2426 clock-names = "apb_pclk"; 2427 arm,coresight-loses-context-with-cpu; 2428 2429 cpu = <&cpu1>; 2430 2431 status = "disabled"; 2432 2433 out-ports { 2434 port { 2435 etm1_out: endpoint { 2436 remote-endpoint = <&funnel_apss0_in1>; 2437 }; 2438 }; 2439 }; 2440 }; 2441 2442 etm@9240000 { 2443 compatible = "arm,coresight-etm4x", "arm,primecell"; 2444 reg = <0x0 0x09240000 0x0 0x1000>; 2445 2446 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2447 clock-names = "apb_pclk"; 2448 arm,coresight-loses-context-with-cpu; 2449 2450 cpu = <&cpu2>; 2451 2452 status = "disabled"; 2453 2454 out-ports { 2455 port { 2456 etm2_out: endpoint { 2457 remote-endpoint = <&funnel_apss0_in2>; 2458 }; 2459 }; 2460 }; 2461 }; 2462 2463 etm@9340000 { 2464 compatible = "arm,coresight-etm4x", "arm,primecell"; 2465 reg = <0x0 0x09340000 0x0 0x1000>; 2466 2467 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2468 clock-names = "apb_pclk"; 2469 arm,coresight-loses-context-with-cpu; 2470 2471 cpu = <&cpu3>; 2472 2473 status = "disabled"; 2474 2475 out-ports { 2476 port { 2477 etm3_out: endpoint { 2478 remote-endpoint = <&funnel_apss0_in3>; 2479 }; 2480 }; 2481 }; 2482 }; 2483 2484 etm@9440000 { 2485 compatible = "arm,coresight-etm4x", "arm,primecell"; 2486 reg = <0x0 0x09440000 0x0 0x1000>; 2487 2488 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2489 clock-names = "apb_pclk"; 2490 arm,coresight-loses-context-with-cpu; 2491 2492 cpu = <&cpu4>; 2493 2494 status = "disabled"; 2495 2496 out-ports { 2497 port { 2498 etm4_out: endpoint { 2499 remote-endpoint = <&funnel_apss0_in4>; 2500 }; 2501 }; 2502 }; 2503 }; 2504 2505 etm@9540000 { 2506 compatible = "arm,coresight-etm4x", "arm,primecell"; 2507 reg = <0x0 0x09540000 0x0 0x1000>; 2508 2509 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2510 clock-names = "apb_pclk"; 2511 arm,coresight-loses-context-with-cpu; 2512 2513 cpu = <&cpu5>; 2514 2515 status = "disabled"; 2516 2517 out-ports { 2518 port { 2519 etm5_out: endpoint { 2520 remote-endpoint = <&funnel_apss0_in5>; 2521 }; 2522 }; 2523 }; 2524 }; 2525 2526 etm@9640000 { 2527 compatible = "arm,coresight-etm4x", "arm,primecell"; 2528 reg = <0x0 0x09640000 0x0 0x1000>; 2529 2530 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2531 clock-names = "apb_pclk"; 2532 arm,coresight-loses-context-with-cpu; 2533 2534 cpu = <&cpu6>; 2535 2536 status = "disabled"; 2537 2538 out-ports { 2539 port { 2540 etm6_out: endpoint { 2541 remote-endpoint = <&funnel_apss0_in6>; 2542 }; 2543 }; 2544 }; 2545 }; 2546 2547 etm@9740000 { 2548 compatible = "arm,coresight-etm4x", "arm,primecell"; 2549 reg = <0x0 0x09740000 0x0 0x1000>; 2550 2551 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2552 clock-names = "apb_pclk"; 2553 arm,coresight-loses-context-with-cpu; 2554 2555 cpu = <&cpu7>; 2556 2557 status = "disabled"; 2558 2559 out-ports { 2560 port { 2561 etm7_out: endpoint { 2562 remote-endpoint = <&funnel_apss0_in7>; 2563 }; 2564 }; 2565 }; 2566 }; 2567 2568 funnel@9800000 { 2569 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2570 reg = <0x0 0x09800000 0x0 0x1000>; 2571 2572 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2573 clock-names = "apb_pclk"; 2574 2575 status = "disabled"; 2576 2577 out-ports { 2578 port { 2579 funnel_apss0_out: endpoint { 2580 remote-endpoint = <&funnel_apss1_in>; 2581 }; 2582 }; 2583 }; 2584 2585 in-ports { 2586 #address-cells = <1>; 2587 #size-cells = <0>; 2588 2589 port@0 { 2590 reg = <0>; 2591 funnel_apss0_in0: endpoint { 2592 remote-endpoint = <&etm0_out>; 2593 }; 2594 }; 2595 2596 port@1 { 2597 reg = <1>; 2598 funnel_apss0_in1: endpoint { 2599 remote-endpoint = <&etm1_out>; 2600 }; 2601 }; 2602 2603 port@2 { 2604 reg = <2>; 2605 funnel_apss0_in2: endpoint { 2606 remote-endpoint = <&etm2_out>; 2607 }; 2608 }; 2609 2610 port@3 { 2611 reg = <3>; 2612 funnel_apss0_in3: endpoint { 2613 remote-endpoint = <&etm3_out>; 2614 }; 2615 }; 2616 2617 port@4 { 2618 reg = <4>; 2619 funnel_apss0_in4: endpoint { 2620 remote-endpoint = <&etm4_out>; 2621 }; 2622 }; 2623 2624 port@5 { 2625 reg = <5>; 2626 funnel_apss0_in5: endpoint { 2627 remote-endpoint = <&etm5_out>; 2628 }; 2629 }; 2630 2631 port@6 { 2632 reg = <6>; 2633 funnel_apss0_in6: endpoint { 2634 remote-endpoint = <&etm6_out>; 2635 }; 2636 }; 2637 2638 port@7 { 2639 reg = <7>; 2640 funnel_apss0_in7: endpoint { 2641 remote-endpoint = <&etm7_out>; 2642 }; 2643 }; 2644 }; 2645 }; 2646 2647 funnel@9810000 { 2648 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2649 reg = <0x0 0x09810000 0x0 0x1000>; 2650 2651 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2652 clock-names = "apb_pclk"; 2653 2654 status = "disabled"; 2655 2656 out-ports { 2657 port { 2658 funnel_apss1_out: endpoint { 2659 remote-endpoint = <&funnel_in1_in>; 2660 }; 2661 }; 2662 }; 2663 2664 in-ports { 2665 port { 2666 funnel_apss1_in: endpoint { 2667 remote-endpoint = <&funnel_apss0_out>; 2668 }; 2669 }; 2670 }; 2671 }; 2672 2673 remoteproc_adsp: remoteproc@ab00000 { 2674 compatible = "qcom,sm6115-adsp-pas"; 2675 reg = <0x0 0x0ab00000 0x0 0x100>; 2676 2677 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, 2678 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2679 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2680 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2681 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2682 interrupt-names = "wdog", "fatal", "ready", 2683 "handover", "stop-ack"; 2684 2685 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2686 clock-names = "xo"; 2687 2688 power-domains = <&rpmpd SM6115_VDD_LPI_CX>, 2689 <&rpmpd SM6115_VDD_LPI_MX>; 2690 2691 memory-region = <&pil_adsp_mem>; 2692 2693 qcom,smem-states = <&adsp_smp2p_out 0>; 2694 qcom,smem-state-names = "stop"; 2695 2696 status = "disabled"; 2697 2698 glink-edge { 2699 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; 2700 label = "lpass"; 2701 qcom,remote-pid = <2>; 2702 mboxes = <&apcs_glb 8>; 2703 2704 fastrpc { 2705 compatible = "qcom,fastrpc"; 2706 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2707 label = "adsp"; 2708 qcom,non-secure-domain; 2709 #address-cells = <1>; 2710 #size-cells = <0>; 2711 2712 compute-cb@3 { 2713 compatible = "qcom,fastrpc-compute-cb"; 2714 reg = <3>; 2715 iommus = <&apps_smmu 0x01c3 0x0>; 2716 }; 2717 2718 compute-cb@4 { 2719 compatible = "qcom,fastrpc-compute-cb"; 2720 reg = <4>; 2721 iommus = <&apps_smmu 0x01c4 0x0>; 2722 }; 2723 2724 compute-cb@5 { 2725 compatible = "qcom,fastrpc-compute-cb"; 2726 reg = <5>; 2727 iommus = <&apps_smmu 0x01c5 0x0>; 2728 }; 2729 2730 compute-cb@6 { 2731 compatible = "qcom,fastrpc-compute-cb"; 2732 reg = <6>; 2733 iommus = <&apps_smmu 0x01c6 0x0>; 2734 }; 2735 2736 compute-cb@7 { 2737 compatible = "qcom,fastrpc-compute-cb"; 2738 reg = <7>; 2739 iommus = <&apps_smmu 0x01c7 0x0>; 2740 }; 2741 }; 2742 }; 2743 }; 2744 2745 remoteproc_cdsp: remoteproc@b300000 { 2746 compatible = "qcom,sm6115-cdsp-pas"; 2747 reg = <0x0 0x0b300000 0x0 0x100000>; 2748 2749 interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 2750 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2751 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2752 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2753 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2754 interrupt-names = "wdog", "fatal", "ready", 2755 "handover", "stop-ack"; 2756 2757 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2758 clock-names = "xo"; 2759 2760 power-domains = <&rpmpd SM6115_VDDCX>; 2761 2762 memory-region = <&pil_cdsp_mem>; 2763 2764 qcom,smem-states = <&cdsp_smp2p_out 0>; 2765 qcom,smem-state-names = "stop"; 2766 2767 status = "disabled"; 2768 2769 glink-edge { 2770 interrupts = <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>; 2771 label = "cdsp"; 2772 qcom,remote-pid = <5>; 2773 mboxes = <&apcs_glb 28>; 2774 2775 fastrpc { 2776 compatible = "qcom,fastrpc"; 2777 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2778 label = "cdsp"; 2779 qcom,non-secure-domain; 2780 #address-cells = <1>; 2781 #size-cells = <0>; 2782 2783 compute-cb@1 { 2784 compatible = "qcom,fastrpc-compute-cb"; 2785 reg = <1>; 2786 iommus = <&apps_smmu 0x0c01 0x0>; 2787 }; 2788 2789 compute-cb@2 { 2790 compatible = "qcom,fastrpc-compute-cb"; 2791 reg = <2>; 2792 iommus = <&apps_smmu 0x0c02 0x0>; 2793 }; 2794 2795 compute-cb@3 { 2796 compatible = "qcom,fastrpc-compute-cb"; 2797 reg = <3>; 2798 iommus = <&apps_smmu 0x0c03 0x0>; 2799 }; 2800 2801 compute-cb@4 { 2802 compatible = "qcom,fastrpc-compute-cb"; 2803 reg = <4>; 2804 iommus = <&apps_smmu 0x0c04 0x0>; 2805 }; 2806 2807 compute-cb@5 { 2808 compatible = "qcom,fastrpc-compute-cb"; 2809 reg = <5>; 2810 iommus = <&apps_smmu 0x0c05 0x0>; 2811 }; 2812 2813 compute-cb@6 { 2814 compatible = "qcom,fastrpc-compute-cb"; 2815 reg = <6>; 2816 iommus = <&apps_smmu 0x0c06 0x0>; 2817 }; 2818 2819 /* note: secure cb9 in downstream */ 2820 }; 2821 }; 2822 }; 2823 2824 apps_smmu: iommu@c600000 { 2825 compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 2826 reg = <0x0 0x0c600000 0x0 0x80000>; 2827 #iommu-cells = <2>; 2828 #global-interrupts = <1>; 2829 2830 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 2831 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 2832 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 2833 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 2834 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 2835 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 2836 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 2837 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 2838 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 2839 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 2840 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2841 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2842 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2843 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2844 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2845 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2846 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2847 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2848 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2849 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2850 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2851 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2852 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2853 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2854 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2855 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2856 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2857 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2858 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2859 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2860 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2861 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2862 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 2863 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 2864 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 2865 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 2866 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 2867 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 2868 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2869 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 2870 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 2871 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 2872 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 2873 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2874 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2875 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 2876 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 2877 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 2878 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 2879 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2880 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 2881 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 2882 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 2883 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 2884 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2885 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2886 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2887 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2888 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2889 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2890 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2891 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2892 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2893 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 2894 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 2895 }; 2896 2897 wifi: wifi@c800000 { 2898 compatible = "qcom,wcn3990-wifi"; 2899 reg = <0x0 0x0c800000 0x0 0x800000>; 2900 reg-names = "membase"; 2901 memory-region = <&wlan_msa_mem>; 2902 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 2903 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 2904 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 2905 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 2906 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 2907 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 2908 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 2909 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 2910 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 2911 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 2912 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 2913 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2914 iommus = <&apps_smmu 0x1a0 0x1>; 2915 qcom,msa-fixed-perm; 2916 status = "disabled"; 2917 }; 2918 2919 watchdog@f017000 { 2920 compatible = "qcom,apss-wdt-sm6115", "qcom,kpss-wdt"; 2921 reg = <0x0 0x0f017000 0x0 0x1000>; 2922 clocks = <&sleep_clk>; 2923 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 2924 }; 2925 2926 apcs_glb: mailbox@f111000 { 2927 compatible = "qcom,sm6115-apcs-hmss-global", 2928 "qcom,msm8994-apcs-kpss-global"; 2929 reg = <0x0 0x0f111000 0x0 0x1000>; 2930 2931 #mbox-cells = <1>; 2932 }; 2933 2934 timer@f120000 { 2935 compatible = "arm,armv7-timer-mem"; 2936 reg = <0x0 0x0f120000 0x0 0x1000>; 2937 #address-cells = <2>; 2938 #size-cells = <1>; 2939 ranges = <0x0 0x0 0x0 0x0 0x20000000>; 2940 clock-frequency = <19200000>; 2941 2942 frame@f121000 { 2943 reg = <0x0 0x0f121000 0x1000>, <0x0 0x0f122000 0x1000>; 2944 frame-number = <0>; 2945 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2946 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2947 }; 2948 2949 frame@f123000 { 2950 reg = <0x0 0x0f123000 0x1000>; 2951 frame-number = <1>; 2952 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2953 status = "disabled"; 2954 }; 2955 2956 frame@f124000 { 2957 reg = <0x0 0x0f124000 0x1000>; 2958 frame-number = <2>; 2959 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2960 status = "disabled"; 2961 }; 2962 2963 frame@f125000 { 2964 reg = <0x0 0x0f125000 0x1000>; 2965 frame-number = <3>; 2966 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2967 status = "disabled"; 2968 }; 2969 2970 frame@f126000 { 2971 reg = <0x0 0x0f126000 0x1000>; 2972 frame-number = <4>; 2973 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2974 status = "disabled"; 2975 }; 2976 2977 frame@f127000 { 2978 reg = <0x0 0x0f127000 0x1000>; 2979 frame-number = <5>; 2980 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2981 status = "disabled"; 2982 }; 2983 2984 frame@f128000 { 2985 reg = <0x0 0x0f128000 0x1000>; 2986 frame-number = <6>; 2987 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2988 status = "disabled"; 2989 }; 2990 }; 2991 2992 intc: interrupt-controller@f200000 { 2993 compatible = "arm,gic-v3"; 2994 reg = <0x0 0x0f200000 0x0 0x10000>, 2995 <0x0 0x0f300000 0x0 0x100000>; 2996 #interrupt-cells = <3>; 2997 interrupt-controller; 2998 interrupt-parent = <&intc>; 2999 #redistributor-regions = <1>; 3000 redistributor-stride = <0x0 0x20000>; 3001 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3002 }; 3003 3004 cpufreq_hw: cpufreq@f521000 { 3005 compatible = "qcom,sm6115-cpufreq-hw", "qcom,cpufreq-hw"; 3006 reg = <0x0 0x0f521000 0x0 0x1000>, 3007 <0x0 0x0f523000 0x0 0x1000>; 3008 3009 reg-names = "freq-domain0", "freq-domain1"; 3010 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 3011 clock-names = "xo", "alternate"; 3012 3013 #freq-domain-cells = <1>; 3014 #clock-cells = <1>; 3015 }; 3016 }; 3017 3018 thermal-zones { 3019 mapss-thermal { 3020 thermal-sensors = <&tsens0 0>; 3021 3022 trips { 3023 trip-point0 { 3024 temperature = <115000>; 3025 hysteresis = <5000>; 3026 type = "passive"; 3027 }; 3028 3029 trip-point1 { 3030 temperature = <125000>; 3031 hysteresis = <1000>; 3032 type = "passive"; 3033 }; 3034 }; 3035 }; 3036 3037 cdsp-hvx-thermal { 3038 thermal-sensors = <&tsens0 1>; 3039 3040 trips { 3041 trip-point0 { 3042 temperature = <115000>; 3043 hysteresis = <5000>; 3044 type = "passive"; 3045 }; 3046 3047 trip-point1 { 3048 temperature = <125000>; 3049 hysteresis = <1000>; 3050 type = "passive"; 3051 }; 3052 }; 3053 }; 3054 3055 wlan-thermal { 3056 thermal-sensors = <&tsens0 2>; 3057 3058 trips { 3059 trip-point0 { 3060 temperature = <115000>; 3061 hysteresis = <5000>; 3062 type = "passive"; 3063 }; 3064 3065 trip-point1 { 3066 temperature = <125000>; 3067 hysteresis = <1000>; 3068 type = "passive"; 3069 }; 3070 }; 3071 }; 3072 3073 camera-thermal { 3074 thermal-sensors = <&tsens0 3>; 3075 3076 trips { 3077 trip-point0 { 3078 temperature = <115000>; 3079 hysteresis = <5000>; 3080 type = "passive"; 3081 }; 3082 3083 trip-point1 { 3084 temperature = <125000>; 3085 hysteresis = <1000>; 3086 type = "passive"; 3087 }; 3088 }; 3089 }; 3090 3091 video-thermal { 3092 thermal-sensors = <&tsens0 4>; 3093 3094 trips { 3095 trip-point0 { 3096 temperature = <115000>; 3097 hysteresis = <5000>; 3098 type = "passive"; 3099 }; 3100 3101 trip-point1 { 3102 temperature = <125000>; 3103 hysteresis = <1000>; 3104 type = "passive"; 3105 }; 3106 }; 3107 }; 3108 3109 modem1-thermal { 3110 thermal-sensors = <&tsens0 5>; 3111 3112 trips { 3113 trip-point0 { 3114 temperature = <115000>; 3115 hysteresis = <5000>; 3116 type = "passive"; 3117 }; 3118 3119 trip-point1 { 3120 temperature = <125000>; 3121 hysteresis = <1000>; 3122 type = "passive"; 3123 }; 3124 }; 3125 }; 3126 3127 cpu4-thermal { 3128 thermal-sensors = <&tsens0 6>; 3129 3130 trips { 3131 cpu4_alert0: trip-point0 { 3132 temperature = <90000>; 3133 hysteresis = <2000>; 3134 type = "passive"; 3135 }; 3136 3137 cpu4_alert1: trip-point1 { 3138 temperature = <95000>; 3139 hysteresis = <2000>; 3140 type = "passive"; 3141 }; 3142 3143 cpu4_crit: cpu-crit { 3144 temperature = <110000>; 3145 hysteresis = <1000>; 3146 type = "critical"; 3147 }; 3148 }; 3149 }; 3150 3151 cpu5-thermal { 3152 thermal-sensors = <&tsens0 7>; 3153 3154 trips { 3155 cpu5_alert0: trip-point0 { 3156 temperature = <90000>; 3157 hysteresis = <2000>; 3158 type = "passive"; 3159 }; 3160 3161 cpu5_alert1: trip-point1 { 3162 temperature = <95000>; 3163 hysteresis = <2000>; 3164 type = "passive"; 3165 }; 3166 3167 cpu5_crit: cpu-crit { 3168 temperature = <110000>; 3169 hysteresis = <1000>; 3170 type = "critical"; 3171 }; 3172 }; 3173 }; 3174 3175 cpu6-thermal { 3176 thermal-sensors = <&tsens0 8>; 3177 3178 trips { 3179 cpu6_alert0: trip-point0 { 3180 temperature = <90000>; 3181 hysteresis = <2000>; 3182 type = "passive"; 3183 }; 3184 3185 cpu6_alert1: trip-point1 { 3186 temperature = <95000>; 3187 hysteresis = <2000>; 3188 type = "passive"; 3189 }; 3190 3191 cpu6_crit: cpu-crit { 3192 temperature = <110000>; 3193 hysteresis = <1000>; 3194 type = "critical"; 3195 }; 3196 }; 3197 }; 3198 3199 cpu7-thermal { 3200 thermal-sensors = <&tsens0 9>; 3201 3202 trips { 3203 cpu7_alert0: trip-point0 { 3204 temperature = <90000>; 3205 hysteresis = <2000>; 3206 type = "passive"; 3207 }; 3208 3209 cpu7_alert1: trip-point1 { 3210 temperature = <95000>; 3211 hysteresis = <2000>; 3212 type = "passive"; 3213 }; 3214 3215 cpu7_crit: cpu-crit { 3216 temperature = <110000>; 3217 hysteresis = <1000>; 3218 type = "critical"; 3219 }; 3220 }; 3221 }; 3222 3223 cpu45-thermal { 3224 thermal-sensors = <&tsens0 10>; 3225 3226 trips { 3227 cpu45_alert0: trip-point0 { 3228 temperature = <90000>; 3229 hysteresis = <2000>; 3230 type = "passive"; 3231 }; 3232 3233 cpu45_alert1: trip-point1 { 3234 temperature = <95000>; 3235 hysteresis = <2000>; 3236 type = "passive"; 3237 }; 3238 3239 cpu45_crit: cpu-crit { 3240 temperature = <110000>; 3241 hysteresis = <1000>; 3242 type = "critical"; 3243 }; 3244 }; 3245 }; 3246 3247 cpu67-thermal { 3248 thermal-sensors = <&tsens0 11>; 3249 3250 trips { 3251 cpu67_alert0: trip-point0 { 3252 temperature = <90000>; 3253 hysteresis = <2000>; 3254 type = "passive"; 3255 }; 3256 3257 cpu67_alert1: trip-point1 { 3258 temperature = <95000>; 3259 hysteresis = <2000>; 3260 type = "passive"; 3261 }; 3262 3263 cpu67_crit: cpu-crit { 3264 temperature = <110000>; 3265 hysteresis = <1000>; 3266 type = "critical"; 3267 }; 3268 }; 3269 }; 3270 3271 cpu0123-thermal { 3272 thermal-sensors = <&tsens0 12>; 3273 3274 trips { 3275 cpu0123_alert0: trip-point0 { 3276 temperature = <90000>; 3277 hysteresis = <2000>; 3278 type = "passive"; 3279 }; 3280 3281 cpu0123_alert1: trip-point1 { 3282 temperature = <95000>; 3283 hysteresis = <2000>; 3284 type = "passive"; 3285 }; 3286 3287 cpu0123_crit: cpu-crit { 3288 temperature = <110000>; 3289 hysteresis = <1000>; 3290 type = "critical"; 3291 }; 3292 }; 3293 }; 3294 3295 modem0-thermal { 3296 thermal-sensors = <&tsens0 13>; 3297 3298 trips { 3299 trip-point0 { 3300 temperature = <115000>; 3301 hysteresis = <5000>; 3302 type = "passive"; 3303 }; 3304 3305 trip-point1 { 3306 temperature = <125000>; 3307 hysteresis = <1000>; 3308 type = "passive"; 3309 }; 3310 }; 3311 }; 3312 3313 display-thermal { 3314 thermal-sensors = <&tsens0 14>; 3315 3316 trips { 3317 trip-point0 { 3318 temperature = <115000>; 3319 hysteresis = <5000>; 3320 type = "passive"; 3321 }; 3322 3323 trip-point1 { 3324 temperature = <125000>; 3325 hysteresis = <1000>; 3326 type = "passive"; 3327 }; 3328 }; 3329 }; 3330 3331 gpu-thermal { 3332 polling-delay-passive = <250>; 3333 3334 thermal-sensors = <&tsens0 15>; 3335 3336 cooling-maps { 3337 map0 { 3338 trip = <&gpu_alert0>; 3339 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3340 }; 3341 }; 3342 3343 trips { 3344 gpu_alert0: trip-point0 { 3345 temperature = <85000>; 3346 hysteresis = <1000>; 3347 type = "passive"; 3348 }; 3349 3350 trip-point1 { 3351 temperature = <110000>; 3352 hysteresis = <1000>; 3353 type = "critical"; 3354 }; 3355 }; 3356 }; 3357 }; 3358 3359 timer { 3360 compatible = "arm,armv8-timer"; 3361 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3362 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3363 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3364 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3365 }; 3366}; 3367