1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com> 4 */ 5 6#include <dt-bindings/clock/qcom,gcc-sm6115.h> 7#include <dt-bindings/clock/qcom,sm6115-dispcc.h> 8#include <dt-bindings/clock/qcom,sm6115-gpucc.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/dma/qcom-gpi.h> 11#include <dt-bindings/firmware/qcom,scm.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interconnect/qcom,rpm-icc.h> 14#include <dt-bindings/interconnect/qcom,sm6115.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/power/qcom-rpmpd.h> 17#include <dt-bindings/thermal/thermal.h> 18 19/ { 20 interrupt-parent = <&intc>; 21 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 chosen { }; 26 27 clocks { 28 xo_board: xo-board { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 }; 32 33 sleep_clk: sleep-clk { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 }; 37 }; 38 39 cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 CPU0: cpu@0 { 44 device_type = "cpu"; 45 compatible = "qcom,kryo260"; 46 reg = <0x0 0x0>; 47 clocks = <&cpufreq_hw 0>; 48 capacity-dmips-mhz = <1024>; 49 dynamic-power-coefficient = <100>; 50 enable-method = "psci"; 51 next-level-cache = <&L2_0>; 52 qcom,freq-domain = <&cpufreq_hw 0>; 53 power-domains = <&CPU_PD0>; 54 power-domain-names = "psci"; 55 L2_0: l2-cache { 56 compatible = "cache"; 57 cache-level = <2>; 58 cache-unified; 59 }; 60 }; 61 62 CPU1: cpu@1 { 63 device_type = "cpu"; 64 compatible = "qcom,kryo260"; 65 reg = <0x0 0x1>; 66 clocks = <&cpufreq_hw 0>; 67 capacity-dmips-mhz = <1024>; 68 dynamic-power-coefficient = <100>; 69 enable-method = "psci"; 70 next-level-cache = <&L2_0>; 71 qcom,freq-domain = <&cpufreq_hw 0>; 72 power-domains = <&CPU_PD1>; 73 power-domain-names = "psci"; 74 }; 75 76 CPU2: cpu@2 { 77 device_type = "cpu"; 78 compatible = "qcom,kryo260"; 79 reg = <0x0 0x2>; 80 clocks = <&cpufreq_hw 0>; 81 capacity-dmips-mhz = <1024>; 82 dynamic-power-coefficient = <100>; 83 enable-method = "psci"; 84 next-level-cache = <&L2_0>; 85 qcom,freq-domain = <&cpufreq_hw 0>; 86 power-domains = <&CPU_PD2>; 87 power-domain-names = "psci"; 88 }; 89 90 CPU3: cpu@3 { 91 device_type = "cpu"; 92 compatible = "qcom,kryo260"; 93 reg = <0x0 0x3>; 94 clocks = <&cpufreq_hw 0>; 95 capacity-dmips-mhz = <1024>; 96 dynamic-power-coefficient = <100>; 97 enable-method = "psci"; 98 next-level-cache = <&L2_0>; 99 qcom,freq-domain = <&cpufreq_hw 0>; 100 power-domains = <&CPU_PD3>; 101 power-domain-names = "psci"; 102 }; 103 104 CPU4: cpu@100 { 105 device_type = "cpu"; 106 compatible = "qcom,kryo260"; 107 reg = <0x0 0x100>; 108 clocks = <&cpufreq_hw 1>; 109 enable-method = "psci"; 110 capacity-dmips-mhz = <1638>; 111 dynamic-power-coefficient = <282>; 112 next-level-cache = <&L2_1>; 113 qcom,freq-domain = <&cpufreq_hw 1>; 114 power-domains = <&CPU_PD4>; 115 power-domain-names = "psci"; 116 L2_1: l2-cache { 117 compatible = "cache"; 118 cache-level = <2>; 119 cache-unified; 120 }; 121 }; 122 123 CPU5: cpu@101 { 124 device_type = "cpu"; 125 compatible = "qcom,kryo260"; 126 reg = <0x0 0x101>; 127 clocks = <&cpufreq_hw 1>; 128 capacity-dmips-mhz = <1638>; 129 dynamic-power-coefficient = <282>; 130 enable-method = "psci"; 131 next-level-cache = <&L2_1>; 132 qcom,freq-domain = <&cpufreq_hw 1>; 133 power-domains = <&CPU_PD5>; 134 power-domain-names = "psci"; 135 }; 136 137 CPU6: cpu@102 { 138 device_type = "cpu"; 139 compatible = "qcom,kryo260"; 140 reg = <0x0 0x102>; 141 clocks = <&cpufreq_hw 1>; 142 capacity-dmips-mhz = <1638>; 143 dynamic-power-coefficient = <282>; 144 enable-method = "psci"; 145 next-level-cache = <&L2_1>; 146 qcom,freq-domain = <&cpufreq_hw 1>; 147 power-domains = <&CPU_PD6>; 148 power-domain-names = "psci"; 149 }; 150 151 CPU7: cpu@103 { 152 device_type = "cpu"; 153 compatible = "qcom,kryo260"; 154 reg = <0x0 0x103>; 155 clocks = <&cpufreq_hw 1>; 156 capacity-dmips-mhz = <1638>; 157 dynamic-power-coefficient = <282>; 158 enable-method = "psci"; 159 next-level-cache = <&L2_1>; 160 qcom,freq-domain = <&cpufreq_hw 1>; 161 power-domains = <&CPU_PD7>; 162 power-domain-names = "psci"; 163 }; 164 165 cpu-map { 166 cluster0 { 167 core0 { 168 cpu = <&CPU0>; 169 }; 170 171 core1 { 172 cpu = <&CPU1>; 173 }; 174 175 core2 { 176 cpu = <&CPU2>; 177 }; 178 179 core3 { 180 cpu = <&CPU3>; 181 }; 182 }; 183 184 cluster1 { 185 core0 { 186 cpu = <&CPU4>; 187 }; 188 189 core1 { 190 cpu = <&CPU5>; 191 }; 192 193 core2 { 194 cpu = <&CPU6>; 195 }; 196 197 core3 { 198 cpu = <&CPU7>; 199 }; 200 }; 201 }; 202 203 idle-states { 204 entry-method = "psci"; 205 206 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 207 compatible = "arm,idle-state"; 208 idle-state-name = "silver-rail-power-collapse"; 209 arm,psci-suspend-param = <0x40000003>; 210 entry-latency-us = <290>; 211 exit-latency-us = <376>; 212 min-residency-us = <1182>; 213 local-timer-stop; 214 }; 215 216 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 217 compatible = "arm,idle-state"; 218 idle-state-name = "gold-rail-power-collapse"; 219 arm,psci-suspend-param = <0x40000003>; 220 entry-latency-us = <297>; 221 exit-latency-us = <324>; 222 min-residency-us = <1110>; 223 local-timer-stop; 224 }; 225 }; 226 227 domain-idle-states { 228 CLUSTER_0_SLEEP_0: cluster-sleep-0-0 { 229 /* GDHS */ 230 compatible = "domain-idle-state"; 231 arm,psci-suspend-param = <0x40000022>; 232 entry-latency-us = <360>; 233 exit-latency-us = <421>; 234 min-residency-us = <782>; 235 }; 236 237 CLUSTER_0_SLEEP_1: cluster-sleep-0-1 { 238 /* Power Collapse */ 239 compatible = "domain-idle-state"; 240 arm,psci-suspend-param = <0x41000044>; 241 entry-latency-us = <800>; 242 exit-latency-us = <2118>; 243 min-residency-us = <7376>; 244 }; 245 246 CLUSTER_1_SLEEP_0: cluster-sleep-1-0 { 247 /* GDHS */ 248 compatible = "domain-idle-state"; 249 arm,psci-suspend-param = <0x40000042>; 250 entry-latency-us = <314>; 251 exit-latency-us = <345>; 252 min-residency-us = <660>; 253 }; 254 255 CLUSTER_1_SLEEP_1: cluster-sleep-1-1 { 256 /* Power Collapse */ 257 compatible = "domain-idle-state"; 258 arm,psci-suspend-param = <0x41000044>; 259 entry-latency-us = <640>; 260 exit-latency-us = <1654>; 261 min-residency-us = <8094>; 262 }; 263 }; 264 }; 265 266 firmware { 267 scm: scm { 268 compatible = "qcom,scm-sm6115", "qcom,scm"; 269 #reset-cells = <1>; 270 interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG 271 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 272 }; 273 }; 274 275 memory@80000000 { 276 device_type = "memory"; 277 /* We expect the bootloader to fill in the size */ 278 reg = <0 0x80000000 0 0>; 279 }; 280 281 qup_opp_table: opp-table-qup { 282 compatible = "operating-points-v2"; 283 284 opp-75000000 { 285 opp-hz = /bits/ 64 <75000000>; 286 required-opps = <&rpmpd_opp_low_svs>; 287 }; 288 289 opp-100000000 { 290 opp-hz = /bits/ 64 <100000000>; 291 required-opps = <&rpmpd_opp_svs>; 292 }; 293 294 opp-128000000 { 295 opp-hz = /bits/ 64 <128000000>; 296 required-opps = <&rpmpd_opp_nom>; 297 }; 298 }; 299 300 pmu { 301 compatible = "arm,armv8-pmuv3"; 302 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 303 }; 304 305 psci { 306 compatible = "arm,psci-1.0"; 307 method = "smc"; 308 309 CPU_PD0: power-domain-cpu0 { 310 #power-domain-cells = <0>; 311 power-domains = <&CLUSTER_0_PD>; 312 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 313 }; 314 315 CPU_PD1: power-domain-cpu1 { 316 #power-domain-cells = <0>; 317 power-domains = <&CLUSTER_0_PD>; 318 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 319 }; 320 321 CPU_PD2: power-domain-cpu2 { 322 #power-domain-cells = <0>; 323 power-domains = <&CLUSTER_0_PD>; 324 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 325 }; 326 327 CPU_PD3: power-domain-cpu3 { 328 #power-domain-cells = <0>; 329 power-domains = <&CLUSTER_0_PD>; 330 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 331 }; 332 333 CPU_PD4: power-domain-cpu4 { 334 #power-domain-cells = <0>; 335 power-domains = <&CLUSTER_1_PD>; 336 domain-idle-states = <&BIG_CPU_SLEEP_0>; 337 }; 338 339 CPU_PD5: power-domain-cpu5 { 340 #power-domain-cells = <0>; 341 power-domains = <&CLUSTER_1_PD>; 342 domain-idle-states = <&BIG_CPU_SLEEP_0>; 343 }; 344 345 CPU_PD6: power-domain-cpu6 { 346 #power-domain-cells = <0>; 347 power-domains = <&CLUSTER_1_PD>; 348 domain-idle-states = <&BIG_CPU_SLEEP_0>; 349 }; 350 351 CPU_PD7: power-domain-cpu7 { 352 #power-domain-cells = <0>; 353 power-domains = <&CLUSTER_1_PD>; 354 domain-idle-states = <&BIG_CPU_SLEEP_0>; 355 }; 356 357 CLUSTER_0_PD: power-domain-cpu-cluster0 { 358 #power-domain-cells = <0>; 359 domain-idle-states = <&CLUSTER_0_SLEEP_0>, <&CLUSTER_0_SLEEP_1>; 360 }; 361 362 CLUSTER_1_PD: power-domain-cpu-cluster1 { 363 #power-domain-cells = <0>; 364 domain-idle-states = <&CLUSTER_1_SLEEP_0>, <&CLUSTER_1_SLEEP_1>; 365 }; 366 }; 367 368 rpm: remoteproc { 369 compatible = "qcom,sm6115-rpm-proc", "qcom,rpm-proc"; 370 371 glink-edge { 372 compatible = "qcom,glink-rpm"; 373 374 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 375 qcom,rpm-msg-ram = <&rpm_msg_ram>; 376 mboxes = <&apcs_glb 0>; 377 378 rpm_requests: rpm-requests { 379 compatible = "qcom,rpm-sm6115"; 380 qcom,glink-channels = "rpm_requests"; 381 382 rpmcc: clock-controller { 383 compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc"; 384 clocks = <&xo_board>; 385 clock-names = "xo"; 386 #clock-cells = <1>; 387 }; 388 389 rpmpd: power-controller { 390 compatible = "qcom,sm6115-rpmpd"; 391 #power-domain-cells = <1>; 392 operating-points-v2 = <&rpmpd_opp_table>; 393 394 rpmpd_opp_table: opp-table { 395 compatible = "operating-points-v2"; 396 397 rpmpd_opp_min_svs: opp1 { 398 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 399 }; 400 401 rpmpd_opp_low_svs: opp2 { 402 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 403 }; 404 405 rpmpd_opp_svs: opp3 { 406 opp-level = <RPM_SMD_LEVEL_SVS>; 407 }; 408 409 rpmpd_opp_svs_plus: opp4 { 410 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 411 }; 412 413 rpmpd_opp_nom: opp5 { 414 opp-level = <RPM_SMD_LEVEL_NOM>; 415 }; 416 417 rpmpd_opp_nom_plus: opp6 { 418 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 419 }; 420 421 rpmpd_opp_turbo: opp7 { 422 opp-level = <RPM_SMD_LEVEL_TURBO>; 423 }; 424 425 rpmpd_opp_turbo_plus: opp8 { 426 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 427 }; 428 }; 429 }; 430 }; 431 }; 432 }; 433 434 reserved_memory: reserved-memory { 435 #address-cells = <2>; 436 #size-cells = <2>; 437 ranges; 438 439 hyp_mem: memory@45700000 { 440 reg = <0x0 0x45700000 0x0 0x600000>; 441 no-map; 442 }; 443 444 xbl_aop_mem: memory@45e00000 { 445 reg = <0x0 0x45e00000 0x0 0x140000>; 446 no-map; 447 }; 448 449 sec_apps_mem: memory@45fff000 { 450 reg = <0x0 0x45fff000 0x0 0x1000>; 451 no-map; 452 }; 453 454 smem_mem: memory@46000000 { 455 compatible = "qcom,smem"; 456 reg = <0x0 0x46000000 0x0 0x200000>; 457 no-map; 458 459 hwlocks = <&tcsr_mutex 3>; 460 qcom,rpm-msg-ram = <&rpm_msg_ram>; 461 }; 462 463 cdsp_sec_mem: memory@46200000 { 464 reg = <0x0 0x46200000 0x0 0x1e00000>; 465 no-map; 466 }; 467 468 pil_modem_mem: memory@4ab00000 { 469 reg = <0x0 0x4ab00000 0x0 0x6900000>; 470 no-map; 471 }; 472 473 pil_video_mem: memory@51400000 { 474 reg = <0x0 0x51400000 0x0 0x500000>; 475 no-map; 476 }; 477 478 wlan_msa_mem: memory@51900000 { 479 reg = <0x0 0x51900000 0x0 0x100000>; 480 no-map; 481 }; 482 483 pil_cdsp_mem: memory@51a00000 { 484 reg = <0x0 0x51a00000 0x0 0x1e00000>; 485 no-map; 486 }; 487 488 pil_adsp_mem: memory@53800000 { 489 reg = <0x0 0x53800000 0x0 0x2800000>; 490 no-map; 491 }; 492 493 pil_ipa_fw_mem: memory@56100000 { 494 reg = <0x0 0x56100000 0x0 0x10000>; 495 no-map; 496 }; 497 498 pil_ipa_gsi_mem: memory@56110000 { 499 reg = <0x0 0x56110000 0x0 0x5000>; 500 no-map; 501 }; 502 503 pil_gpu_mem: memory@56115000 { 504 reg = <0x0 0x56115000 0x0 0x2000>; 505 no-map; 506 }; 507 508 cont_splash_memory: memory@5c000000 { 509 reg = <0x0 0x5c000000 0x0 0x00f00000>; 510 no-map; 511 }; 512 513 dfps_data_memory: memory@5cf00000 { 514 reg = <0x0 0x5cf00000 0x0 0x0100000>; 515 no-map; 516 }; 517 518 removed_mem: memory@60000000 { 519 reg = <0x0 0x60000000 0x0 0x3900000>; 520 no-map; 521 }; 522 523 rmtfs_mem: memory@89b01000 { 524 compatible = "qcom,rmtfs-mem"; 525 reg = <0x0 0x89b01000 0x0 0x200000>; 526 no-map; 527 528 qcom,client-id = <1>; 529 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; 530 }; 531 }; 532 533 smp2p-adsp { 534 compatible = "qcom,smp2p"; 535 qcom,smem = <443>, <429>; 536 537 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>; 538 539 mboxes = <&apcs_glb 10>; 540 541 qcom,local-pid = <0>; 542 qcom,remote-pid = <2>; 543 544 adsp_smp2p_out: master-kernel { 545 qcom,entry-name = "master-kernel"; 546 #qcom,smem-state-cells = <1>; 547 }; 548 549 adsp_smp2p_in: slave-kernel { 550 qcom,entry-name = "slave-kernel"; 551 552 interrupt-controller; 553 #interrupt-cells = <2>; 554 }; 555 }; 556 557 smp2p-cdsp { 558 compatible = "qcom,smp2p"; 559 qcom,smem = <94>, <432>; 560 561 interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>; 562 563 mboxes = <&apcs_glb 30>; 564 565 qcom,local-pid = <0>; 566 qcom,remote-pid = <5>; 567 568 cdsp_smp2p_out: master-kernel { 569 qcom,entry-name = "master-kernel"; 570 #qcom,smem-state-cells = <1>; 571 }; 572 573 cdsp_smp2p_in: slave-kernel { 574 qcom,entry-name = "slave-kernel"; 575 576 interrupt-controller; 577 #interrupt-cells = <2>; 578 }; 579 }; 580 581 smp2p-mpss { 582 compatible = "qcom,smp2p"; 583 qcom,smem = <435>, <428>; 584 585 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; 586 587 mboxes = <&apcs_glb 14>; 588 589 qcom,local-pid = <0>; 590 qcom,remote-pid = <1>; 591 592 modem_smp2p_out: master-kernel { 593 qcom,entry-name = "master-kernel"; 594 #qcom,smem-state-cells = <1>; 595 }; 596 597 modem_smp2p_in: slave-kernel { 598 qcom,entry-name = "slave-kernel"; 599 600 interrupt-controller; 601 #interrupt-cells = <2>; 602 }; 603 }; 604 605 soc: soc@0 { 606 compatible = "simple-bus"; 607 #address-cells = <2>; 608 #size-cells = <2>; 609 ranges = <0 0 0 0 0x10 0>; 610 dma-ranges = <0 0 0 0 0x10 0>; 611 612 tcsr_mutex: hwlock@340000 { 613 compatible = "qcom,tcsr-mutex"; 614 reg = <0x0 0x00340000 0x0 0x20000>; 615 #hwlock-cells = <1>; 616 }; 617 618 tcsr_regs: syscon@3c0000 { 619 compatible = "qcom,sm6115-tcsr", "syscon"; 620 reg = <0x0 0x003c0000 0x0 0x40000>; 621 }; 622 623 tlmm: pinctrl@500000 { 624 compatible = "qcom,sm6115-tlmm"; 625 reg = <0x0 0x00500000 0x0 0x400000>, 626 <0x0 0x00900000 0x0 0x400000>, 627 <0x0 0x00d00000 0x0 0x400000>; 628 reg-names = "west", "south", "east"; 629 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 630 gpio-controller; 631 gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */ 632 #gpio-cells = <2>; 633 interrupt-controller; 634 #interrupt-cells = <2>; 635 636 qup_i2c0_default: qup-i2c0-default-state { 637 pins = "gpio0", "gpio1"; 638 function = "qup0"; 639 drive-strength = <2>; 640 bias-pull-up; 641 }; 642 643 qup_i2c1_default: qup-i2c1-default-state { 644 pins = "gpio4", "gpio5"; 645 function = "qup1"; 646 drive-strength = <2>; 647 bias-pull-up; 648 }; 649 650 qup_i2c2_default: qup-i2c2-default-state { 651 pins = "gpio6", "gpio7"; 652 function = "qup2"; 653 drive-strength = <2>; 654 bias-pull-up; 655 }; 656 657 qup_i2c3_default: qup-i2c3-default-state { 658 pins = "gpio8", "gpio9"; 659 function = "qup3"; 660 drive-strength = <2>; 661 bias-pull-up; 662 }; 663 664 qup_i2c4_default: qup-i2c4-default-state { 665 pins = "gpio12", "gpio13"; 666 function = "qup4"; 667 drive-strength = <2>; 668 bias-pull-up; 669 }; 670 671 qup_i2c5_default: qup-i2c5-default-state { 672 pins = "gpio14", "gpio15"; 673 function = "qup5"; 674 drive-strength = <2>; 675 bias-pull-up; 676 }; 677 678 qup_spi0_default: qup-spi0-default-state { 679 pins = "gpio0", "gpio1","gpio2", "gpio3"; 680 function = "qup0"; 681 drive-strength = <2>; 682 bias-pull-up; 683 }; 684 685 qup_spi1_default: qup-spi1-default-state { 686 pins = "gpio4", "gpio5", "gpio69", "gpio70"; 687 function = "qup1"; 688 drive-strength = <2>; 689 bias-pull-up; 690 }; 691 692 qup_spi2_default: qup-spi2-default-state { 693 pins = "gpio6", "gpio7", "gpio71", "gpio80"; 694 function = "qup2"; 695 drive-strength = <2>; 696 bias-pull-up; 697 }; 698 699 qup_spi3_default: qup-spi3-default-state { 700 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 701 function = "qup3"; 702 drive-strength = <2>; 703 bias-pull-up; 704 }; 705 706 qup_spi4_default: qup-spi4-default-state { 707 pins = "gpio12", "gpio13", "gpio96", "gpio97"; 708 function = "qup4"; 709 drive-strength = <2>; 710 bias-pull-up; 711 }; 712 713 qup_spi5_default: qup-spi5-default-state { 714 pins = "gpio14", "gpio15", "gpio16", "gpio17"; 715 function = "qup5"; 716 drive-strength = <2>; 717 bias-pull-up; 718 }; 719 720 sdc1_state_on: sdc1-on-state { 721 clk-pins { 722 pins = "sdc1_clk"; 723 bias-disable; 724 drive-strength = <16>; 725 }; 726 727 cmd-pins { 728 pins = "sdc1_cmd"; 729 bias-pull-up; 730 drive-strength = <10>; 731 }; 732 733 data-pins { 734 pins = "sdc1_data"; 735 bias-pull-up; 736 drive-strength = <10>; 737 }; 738 739 rclk-pins { 740 pins = "sdc1_rclk"; 741 bias-pull-down; 742 }; 743 }; 744 745 sdc1_state_off: sdc1-off-state { 746 clk-pins { 747 pins = "sdc1_clk"; 748 bias-disable; 749 drive-strength = <2>; 750 }; 751 752 cmd-pins { 753 pins = "sdc1_cmd"; 754 bias-pull-up; 755 drive-strength = <2>; 756 }; 757 758 data-pins { 759 pins = "sdc1_data"; 760 bias-pull-up; 761 drive-strength = <2>; 762 }; 763 764 rclk-pins { 765 pins = "sdc1_rclk"; 766 bias-pull-down; 767 }; 768 }; 769 770 sdc2_state_on: sdc2-on-state { 771 clk-pins { 772 pins = "sdc2_clk"; 773 bias-disable; 774 drive-strength = <16>; 775 }; 776 777 cmd-pins { 778 pins = "sdc2_cmd"; 779 bias-pull-up; 780 drive-strength = <10>; 781 }; 782 783 data-pins { 784 pins = "sdc2_data"; 785 bias-pull-up; 786 drive-strength = <10>; 787 }; 788 }; 789 790 sdc2_state_off: sdc2-off-state { 791 clk-pins { 792 pins = "sdc2_clk"; 793 bias-disable; 794 drive-strength = <2>; 795 }; 796 797 cmd-pins { 798 pins = "sdc2_cmd"; 799 bias-pull-up; 800 drive-strength = <2>; 801 }; 802 803 data-pins { 804 pins = "sdc2_data"; 805 bias-pull-up; 806 drive-strength = <2>; 807 }; 808 }; 809 }; 810 811 gcc: clock-controller@1400000 { 812 compatible = "qcom,gcc-sm6115"; 813 reg = <0x0 0x01400000 0x0 0x1f0000>; 814 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 815 clock-names = "bi_tcxo", "sleep_clk"; 816 #clock-cells = <1>; 817 #reset-cells = <1>; 818 #power-domain-cells = <1>; 819 }; 820 821 usb_hsphy: phy@1613000 { 822 compatible = "qcom,sm6115-qusb2-phy"; 823 reg = <0x0 0x01613000 0x0 0x180>; 824 #phy-cells = <0>; 825 826 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 827 clock-names = "cfg_ahb", "ref"; 828 829 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 830 nvmem-cells = <&qusb2_hstx_trim>; 831 832 status = "disabled"; 833 }; 834 835 cryptobam: dma-controller@1b04000 { 836 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 837 reg = <0x0 0x01b04000 0x0 0x24000>; 838 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 839 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 840 clock-names = "bam_clk"; 841 #dma-cells = <1>; 842 qcom,ee = <0>; 843 qcom,controlled-remotely; 844 iommus = <&apps_smmu 0x92 0>, 845 <&apps_smmu 0x94 0x11>, 846 <&apps_smmu 0x96 0x11>, 847 <&apps_smmu 0x98 0x1>, 848 <&apps_smmu 0x9F 0>; 849 }; 850 851 crypto: crypto@1b3a000 { 852 compatible = "qcom,sm6115-qce", "qcom,ipq4019-qce", "qcom,qce"; 853 reg = <0x0 0x01b3a000 0x0 0x6000>; 854 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 855 clock-names = "core"; 856 857 dmas = <&cryptobam 6>, <&cryptobam 7>; 858 dma-names = "rx", "tx"; 859 iommus = <&apps_smmu 0x92 0>, 860 <&apps_smmu 0x94 0x11>, 861 <&apps_smmu 0x96 0x11>, 862 <&apps_smmu 0x98 0x1>, 863 <&apps_smmu 0x9F 0>; 864 }; 865 866 usb_qmpphy: phy@1615000 { 867 compatible = "qcom,sm6115-qmp-usb3-phy"; 868 reg = <0x0 0x01615000 0x0 0x1000>; 869 870 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 871 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 872 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 873 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 874 clock-names = "cfg_ahb", 875 "ref", 876 "com_aux", 877 "pipe"; 878 879 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, 880 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; 881 reset-names = "phy", "phy_phy"; 882 883 #clock-cells = <0>; 884 clock-output-names = "usb3_phy_pipe_clk_src"; 885 886 #phy-cells = <0>; 887 orientation-switch; 888 889 qcom,tcsr-reg = <&tcsr_regs 0xb244>; 890 891 status = "disabled"; 892 893 ports { 894 #address-cells = <1>; 895 #size-cells = <0>; 896 897 port@0 { 898 reg = <0>; 899 900 usb_qmpphy_out: endpoint { 901 }; 902 }; 903 904 port@1 { 905 reg = <1>; 906 907 usb_qmpphy_usb_ss_in: endpoint { 908 remote-endpoint = <&usb_dwc3_ss>; 909 }; 910 }; 911 }; 912 }; 913 914 system_noc: interconnect@1880000 { 915 compatible = "qcom,sm6115-snoc"; 916 reg = <0x0 0x01880000 0x0 0x5f080>; 917 clocks = <&gcc GCC_SYS_NOC_CPUSS_AHB_CLK>, 918 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, 919 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 920 <&rpmcc RPM_SMD_IPA_CLK>; 921 clock-names = "cpu_axi", 922 "ufs_axi", 923 "usb_axi", 924 "ipa"; 925 #interconnect-cells = <2>; 926 927 clk_virt: interconnect-clk { 928 compatible = "qcom,sm6115-clk-virt"; 929 #interconnect-cells = <2>; 930 }; 931 932 mmrt_virt: interconnect-mmrt { 933 compatible = "qcom,sm6115-mmrt-virt"; 934 #interconnect-cells = <2>; 935 }; 936 937 mmnrt_virt: interconnect-mmnrt { 938 compatible = "qcom,sm6115-mmnrt-virt"; 939 #interconnect-cells = <2>; 940 }; 941 }; 942 943 config_noc: interconnect@1900000 { 944 compatible = "qcom,sm6115-cnoc"; 945 reg = <0x0 0x01900000 0x0 0x6200>; 946 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>; 947 clock-names = "usb_axi"; 948 #interconnect-cells = <2>; 949 }; 950 951 qfprom@1b40000 { 952 compatible = "qcom,sm6115-qfprom", "qcom,qfprom"; 953 reg = <0x0 0x01b40000 0x0 0x7000>; 954 #address-cells = <1>; 955 #size-cells = <1>; 956 957 qusb2_hstx_trim: hstx-trim@25b { 958 reg = <0x25b 0x1>; 959 bits = <1 4>; 960 }; 961 962 gpu_speed_bin: gpu-speed-bin@6006 { 963 reg = <0x6006 0x2>; 964 bits = <5 8>; 965 }; 966 }; 967 968 rng: rng@1b53000 { 969 compatible = "qcom,prng-ee"; 970 reg = <0x0 0x01b53000 0x0 0x1000>; 971 clocks = <&gcc GCC_PRNG_AHB_CLK>; 972 clock-names = "core"; 973 }; 974 975 pmu@1b8e300 { 976 compatible = "qcom,sm6115-cpu-bwmon", "qcom,sdm845-bwmon"; 977 reg = <0x0 0x01b8e300 0x0 0x600>; 978 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 979 980 operating-points-v2 = <&cpu_bwmon_opp_table>; 981 interconnects = <&bimc MASTER_AMPSS_M0 RPM_ACTIVE_TAG 982 &bimc SLAVE_EBI_CH0 RPM_ACTIVE_TAG>; 983 984 cpu_bwmon_opp_table: opp-table { 985 compatible = "operating-points-v2"; 986 987 opp-0 { 988 opp-peak-kBps = <(200 * 4 * 1000)>; 989 }; 990 991 opp-1 { 992 opp-peak-kBps = <(300 * 4 * 1000)>; 993 }; 994 995 opp-2 { 996 opp-peak-kBps = <(451 * 4 * 1000)>; 997 }; 998 999 opp-3 { 1000 opp-peak-kBps = <(547 * 4 * 1000)>; 1001 }; 1002 1003 opp-4 { 1004 opp-peak-kBps = <(681 * 4 * 1000)>; 1005 }; 1006 1007 opp-5 { 1008 opp-peak-kBps = <(768 * 4 * 1000)>; 1009 }; 1010 1011 opp-6 { 1012 opp-peak-kBps = <(1017 * 4 * 1000)>; 1013 }; 1014 1015 opp-7 { 1016 opp-peak-kBps = <(1353 * 4 * 1000)>; 1017 }; 1018 1019 opp-8 { 1020 opp-peak-kBps = <(1555 * 4 * 1000)>; 1021 }; 1022 1023 opp-9 { 1024 opp-peak-kBps = <(1804 * 4 * 1000)>; 1025 }; 1026 }; 1027 }; 1028 1029 spmi_bus: spmi@1c40000 { 1030 compatible = "qcom,spmi-pmic-arb"; 1031 reg = <0x0 0x01c40000 0x0 0x1100>, 1032 <0x0 0x01e00000 0x0 0x2000000>, 1033 <0x0 0x03e00000 0x0 0x100000>, 1034 <0x0 0x03f00000 0x0 0xa0000>, 1035 <0x0 0x01c0a000 0x0 0x26000>; 1036 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1037 interrupt-names = "periph_irq"; 1038 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 1039 qcom,ee = <0>; 1040 qcom,channel = <0>; 1041 #address-cells = <2>; 1042 #size-cells = <0>; 1043 interrupt-controller; 1044 #interrupt-cells = <4>; 1045 }; 1046 1047 tsens0: thermal-sensor@4411000 { 1048 compatible = "qcom,sm6115-tsens", "qcom,tsens-v2"; 1049 reg = <0x0 0x04411000 0x0 0x1ff>, /* TM */ 1050 <0x0 0x04410000 0x0 0x8>; /* SROT */ 1051 #qcom,sensors = <16>; 1052 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 1053 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1054 interrupt-names = "uplow", "critical"; 1055 #thermal-sensor-cells = <1>; 1056 }; 1057 1058 bimc: interconnect@4480000 { 1059 compatible = "qcom,sm6115-bimc"; 1060 reg = <0x0 0x04480000 0x0 0x80000>; 1061 #interconnect-cells = <2>; 1062 }; 1063 1064 rpm_msg_ram: sram@45f0000 { 1065 compatible = "qcom,rpm-msg-ram"; 1066 reg = <0x0 0x045f0000 0x0 0x7000>; 1067 }; 1068 1069 sram@4690000 { 1070 compatible = "qcom,rpm-stats"; 1071 reg = <0x0 0x04690000 0x0 0x10000>; 1072 }; 1073 1074 sdhc_1: mmc@4744000 { 1075 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; 1076 reg = <0x0 0x04744000 0x0 0x1000>, 1077 <0x0 0x04745000 0x0 0x1000>, 1078 <0x0 0x04748000 0x0 0x8000>; 1079 reg-names = "hc", "cqhci", "ice"; 1080 1081 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 1082 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1083 interrupt-names = "hc_irq", "pwr_irq"; 1084 1085 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1086 <&gcc GCC_SDCC1_APPS_CLK>, 1087 <&rpmcc RPM_SMD_XO_CLK_SRC>, 1088 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 1089 clock-names = "iface", "core", "xo", "ice"; 1090 1091 power-domains = <&rpmpd SM6115_VDDCX>; 1092 operating-points-v2 = <&sdhc1_opp_table>; 1093 iommus = <&apps_smmu 0x00c0 0x0>; 1094 interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG 1095 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, 1096 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1097 &config_noc SLAVE_SDCC_1 RPM_ALWAYS_TAG>; 1098 interconnect-names = "sdhc-ddr", 1099 "cpu-sdhc"; 1100 1101 bus-width = <8>; 1102 status = "disabled"; 1103 1104 sdhc1_opp_table: opp-table { 1105 compatible = "operating-points-v2"; 1106 1107 opp-100000000 { 1108 opp-hz = /bits/ 64 <100000000>; 1109 required-opps = <&rpmpd_opp_low_svs>; 1110 opp-peak-kBps = <250000 133320>; 1111 opp-avg-kBps = <102400 65000>; 1112 }; 1113 1114 opp-192000000 { 1115 opp-hz = /bits/ 64 <192000000>; 1116 required-opps = <&rpmpd_opp_low_svs>; 1117 opp-peak-kBps = <800000 300000>; 1118 opp-avg-kBps = <204800 200000>; 1119 }; 1120 1121 opp-384000000 { 1122 opp-hz = /bits/ 64 <384000000>; 1123 required-opps = <&rpmpd_opp_svs_plus>; 1124 opp-peak-kBps = <800000 300000>; 1125 opp-avg-kBps = <204800 200000>; 1126 }; 1127 }; 1128 }; 1129 1130 sdhc_2: mmc@4784000 { 1131 compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5"; 1132 reg = <0x0 0x04784000 0x0 0x1000>; 1133 reg-names = "hc"; 1134 1135 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 1136 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1137 interrupt-names = "hc_irq", "pwr_irq"; 1138 1139 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1140 <&gcc GCC_SDCC2_APPS_CLK>, 1141 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1142 clock-names = "iface", "core", "xo"; 1143 1144 power-domains = <&rpmpd SM6115_VDDCX>; 1145 operating-points-v2 = <&sdhc2_opp_table>; 1146 iommus = <&apps_smmu 0x00a0 0x0>; 1147 resets = <&gcc GCC_SDCC2_BCR>; 1148 interconnects = <&system_noc MASTER_SDCC_2 RPM_ALWAYS_TAG 1149 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, 1150 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1151 &config_noc SLAVE_SDCC_2 RPM_ALWAYS_TAG>; 1152 interconnect-names = "sdhc-ddr", 1153 "cpu-sdhc"; 1154 1155 bus-width = <4>; 1156 qcom,dll-config = <0x0007642c>; 1157 qcom,ddr-config = <0x80040868>; 1158 status = "disabled"; 1159 1160 sdhc2_opp_table: opp-table { 1161 compatible = "operating-points-v2"; 1162 1163 opp-100000000 { 1164 opp-hz = /bits/ 64 <100000000>; 1165 required-opps = <&rpmpd_opp_low_svs>; 1166 opp-peak-kBps = <250000 133320>; 1167 opp-avg-kBps = <261438 150000>; 1168 }; 1169 1170 opp-202000000 { 1171 opp-hz = /bits/ 64 <202000000>; 1172 required-opps = <&rpmpd_opp_nom>; 1173 opp-peak-kBps = <800000 300000>; 1174 opp-avg-kBps = <261438 300000>; 1175 }; 1176 }; 1177 }; 1178 1179 ufs_mem_hc: ufs@4804000 { 1180 compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 1181 reg = <0x0 0x04804000 0x0 0x3000>, <0x0 0x04810000 0x0 0x8000>; 1182 reg-names = "std", "ice"; 1183 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1184 phys = <&ufs_mem_phy>; 1185 phy-names = "ufsphy"; 1186 lanes-per-direction = <1>; 1187 #reset-cells = <1>; 1188 resets = <&gcc GCC_UFS_PHY_BCR>; 1189 reset-names = "rst"; 1190 1191 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 1192 iommus = <&apps_smmu 0x100 0>; 1193 1194 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1195 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, 1196 <&gcc GCC_UFS_PHY_AHB_CLK>, 1197 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1198 <&rpmcc RPM_SMD_XO_CLK_SRC>, 1199 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1200 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1201 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1202 clock-names = "core_clk", 1203 "bus_aggr_clk", 1204 "iface_clk", 1205 "core_clk_unipro", 1206 "ref_clk", 1207 "tx_lane0_sync_clk", 1208 "rx_lane0_sync_clk", 1209 "ice_core_clk"; 1210 1211 freq-table-hz = <50000000 200000000>, 1212 <0 0>, 1213 <0 0>, 1214 <37500000 150000000>, 1215 <0 0>, 1216 <0 0>, 1217 <0 0>, 1218 <75000000 300000000>; 1219 1220 status = "disabled"; 1221 }; 1222 1223 ufs_mem_phy: phy@4807000 { 1224 compatible = "qcom,sm6115-qmp-ufs-phy"; 1225 reg = <0x0 0x04807000 0x0 0x1000>; 1226 1227 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1228 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1229 <&gcc GCC_UFS_CLKREF_CLK>; 1230 clock-names = "ref", 1231 "ref_aux", 1232 "qref"; 1233 1234 resets = <&ufs_mem_hc 0>; 1235 reset-names = "ufsphy"; 1236 1237 #phy-cells = <0>; 1238 1239 status = "disabled"; 1240 }; 1241 1242 gpi_dma0: dma-controller@4a00000 { 1243 compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma"; 1244 reg = <0x0 0x04a00000 0x0 0x60000>; 1245 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1254 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1255 dma-channels = <10>; 1256 dma-channel-mask = <0xf>; 1257 iommus = <&apps_smmu 0xf6 0x0>; 1258 #dma-cells = <3>; 1259 status = "disabled"; 1260 }; 1261 1262 qupv3_id_0: geniqup@4ac0000 { 1263 compatible = "qcom,geni-se-qup"; 1264 reg = <0x0 0x04ac0000 0x0 0x2000>; 1265 clock-names = "m-ahb", "s-ahb"; 1266 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1267 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1268 #address-cells = <2>; 1269 #size-cells = <2>; 1270 iommus = <&apps_smmu 0xe3 0x0>; 1271 ranges; 1272 status = "disabled"; 1273 1274 i2c0: i2c@4a80000 { 1275 compatible = "qcom,geni-i2c"; 1276 reg = <0x0 0x04a80000 0x0 0x4000>; 1277 clock-names = "se"; 1278 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1279 pinctrl-names = "default"; 1280 pinctrl-0 = <&qup_i2c0_default>; 1281 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1282 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1283 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1284 dma-names = "tx", "rx"; 1285 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1286 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1287 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1288 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1289 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1290 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1291 interconnect-names = "qup-core", 1292 "qup-config", 1293 "qup-memory"; 1294 #address-cells = <1>; 1295 #size-cells = <0>; 1296 status = "disabled"; 1297 }; 1298 1299 spi0: spi@4a80000 { 1300 compatible = "qcom,geni-spi"; 1301 reg = <0x0 0x04a80000 0x0 0x4000>; 1302 clock-names = "se"; 1303 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1304 pinctrl-names = "default"; 1305 pinctrl-0 = <&qup_spi0_default>; 1306 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1307 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1308 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1309 dma-names = "tx", "rx"; 1310 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1311 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1312 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1313 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1314 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1315 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1316 interconnect-names = "qup-core", 1317 "qup-config", 1318 "qup-memory"; 1319 #address-cells = <1>; 1320 #size-cells = <0>; 1321 status = "disabled"; 1322 }; 1323 1324 i2c1: i2c@4a84000 { 1325 compatible = "qcom,geni-i2c"; 1326 reg = <0x0 0x04a84000 0x0 0x4000>; 1327 clock-names = "se"; 1328 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1329 pinctrl-names = "default"; 1330 pinctrl-0 = <&qup_i2c1_default>; 1331 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1332 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1333 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1334 dma-names = "tx", "rx"; 1335 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1336 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1337 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1338 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1339 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1340 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1341 interconnect-names = "qup-core", 1342 "qup-config", 1343 "qup-memory"; 1344 #address-cells = <1>; 1345 #size-cells = <0>; 1346 status = "disabled"; 1347 }; 1348 1349 spi1: spi@4a84000 { 1350 compatible = "qcom,geni-spi"; 1351 reg = <0x0 0x04a84000 0x0 0x4000>; 1352 clock-names = "se"; 1353 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1354 pinctrl-names = "default"; 1355 pinctrl-0 = <&qup_spi1_default>; 1356 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1357 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1358 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1359 dma-names = "tx", "rx"; 1360 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1361 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1362 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1363 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1364 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1365 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1366 interconnect-names = "qup-core", 1367 "qup-config", 1368 "qup-memory"; 1369 #address-cells = <1>; 1370 #size-cells = <0>; 1371 status = "disabled"; 1372 }; 1373 1374 i2c2: i2c@4a88000 { 1375 compatible = "qcom,geni-i2c"; 1376 reg = <0x0 0x04a88000 0x0 0x4000>; 1377 clock-names = "se"; 1378 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1379 pinctrl-names = "default"; 1380 pinctrl-0 = <&qup_i2c2_default>; 1381 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1382 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1383 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1384 dma-names = "tx", "rx"; 1385 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1386 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1387 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1388 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1389 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1390 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1391 interconnect-names = "qup-core", 1392 "qup-config", 1393 "qup-memory"; 1394 #address-cells = <1>; 1395 #size-cells = <0>; 1396 status = "disabled"; 1397 }; 1398 1399 spi2: spi@4a88000 { 1400 compatible = "qcom,geni-spi"; 1401 reg = <0x0 0x04a88000 0x0 0x4000>; 1402 clock-names = "se"; 1403 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1404 pinctrl-names = "default"; 1405 pinctrl-0 = <&qup_spi2_default>; 1406 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1407 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1408 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1409 dma-names = "tx", "rx"; 1410 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1411 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1412 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1413 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1414 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1415 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1416 interconnect-names = "qup-core", 1417 "qup-config", 1418 "qup-memory"; 1419 #address-cells = <1>; 1420 #size-cells = <0>; 1421 status = "disabled"; 1422 }; 1423 1424 i2c3: i2c@4a8c000 { 1425 compatible = "qcom,geni-i2c"; 1426 reg = <0x0 0x04a8c000 0x0 0x4000>; 1427 clock-names = "se"; 1428 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1429 pinctrl-names = "default"; 1430 pinctrl-0 = <&qup_i2c3_default>; 1431 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1432 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1433 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1434 dma-names = "tx", "rx"; 1435 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1436 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1437 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1438 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1439 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1440 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1441 interconnect-names = "qup-core", 1442 "qup-config", 1443 "qup-memory"; 1444 #address-cells = <1>; 1445 #size-cells = <0>; 1446 status = "disabled"; 1447 }; 1448 1449 spi3: spi@4a8c000 { 1450 compatible = "qcom,geni-spi"; 1451 reg = <0x0 0x04a8c000 0x0 0x4000>; 1452 clock-names = "se"; 1453 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1454 pinctrl-names = "default"; 1455 pinctrl-0 = <&qup_spi3_default>; 1456 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1457 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1458 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1459 dma-names = "tx", "rx"; 1460 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1461 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1462 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1463 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1464 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1465 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1466 interconnect-names = "qup-core", 1467 "qup-config", 1468 "qup-memory"; 1469 #address-cells = <1>; 1470 #size-cells = <0>; 1471 status = "disabled"; 1472 }; 1473 1474 uart3: serial@4a8c000 { 1475 compatible = "qcom,geni-uart"; 1476 reg = <0x0 0x04a8c000 0x0 0x4000>; 1477 interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1478 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1479 clock-names = "se"; 1480 power-domains = <&rpmpd SM6115_VDDCX>; 1481 operating-points-v2 = <&qup_opp_table>; 1482 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1483 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1484 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1485 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1486 interconnect-names = "qup-core", 1487 "qup-config"; 1488 status = "disabled"; 1489 }; 1490 1491 i2c4: i2c@4a90000 { 1492 compatible = "qcom,geni-i2c"; 1493 reg = <0x0 0x04a90000 0x0 0x4000>; 1494 clock-names = "se"; 1495 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1496 pinctrl-names = "default"; 1497 pinctrl-0 = <&qup_i2c4_default>; 1498 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1499 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1500 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1501 dma-names = "tx", "rx"; 1502 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1503 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1504 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1505 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1506 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1507 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1508 interconnect-names = "qup-core", 1509 "qup-config", 1510 "qup-memory"; 1511 #address-cells = <1>; 1512 #size-cells = <0>; 1513 status = "disabled"; 1514 }; 1515 1516 spi4: spi@4a90000 { 1517 compatible = "qcom,geni-spi"; 1518 reg = <0x0 0x04a90000 0x0 0x4000>; 1519 clock-names = "se"; 1520 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1521 pinctrl-names = "default"; 1522 pinctrl-0 = <&qup_spi4_default>; 1523 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1524 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1525 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1526 dma-names = "tx", "rx"; 1527 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1528 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1529 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1530 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1531 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1532 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1533 interconnect-names = "qup-core", 1534 "qup-config", 1535 "qup-memory"; 1536 #address-cells = <1>; 1537 #size-cells = <0>; 1538 status = "disabled"; 1539 }; 1540 1541 uart4: serial@4a90000 { 1542 compatible = "qcom,geni-debug-uart"; 1543 reg = <0x0 0x04a90000 0x0 0x4000>; 1544 clock-names = "se"; 1545 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1546 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1547 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1548 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1549 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1550 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1551 interconnect-names = "qup-core", 1552 "qup-config"; 1553 status = "disabled"; 1554 }; 1555 1556 i2c5: i2c@4a94000 { 1557 compatible = "qcom,geni-i2c"; 1558 reg = <0x0 0x04a94000 0x0 0x4000>; 1559 clock-names = "se"; 1560 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1561 pinctrl-names = "default"; 1562 pinctrl-0 = <&qup_i2c5_default>; 1563 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1564 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1565 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1566 dma-names = "tx", "rx"; 1567 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1568 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1569 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1570 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1571 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1572 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1573 interconnect-names = "qup-core", 1574 "qup-config", 1575 "qup-memory"; 1576 #address-cells = <1>; 1577 #size-cells = <0>; 1578 status = "disabled"; 1579 }; 1580 1581 spi5: spi@4a94000 { 1582 compatible = "qcom,geni-spi"; 1583 reg = <0x0 0x04a94000 0x0 0x4000>; 1584 clock-names = "se"; 1585 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1586 pinctrl-names = "default"; 1587 pinctrl-0 = <&qup_spi5_default>; 1588 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1589 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1590 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1591 dma-names = "tx", "rx"; 1592 interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1593 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1594 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1595 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1596 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1597 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; 1598 interconnect-names = "qup-core", 1599 "qup-config", 1600 "qup-memory"; 1601 #address-cells = <1>; 1602 #size-cells = <0>; 1603 status = "disabled"; 1604 }; 1605 }; 1606 1607 usb: usb@4ef8800 { 1608 compatible = "qcom,sm6115-dwc3", "qcom,dwc3"; 1609 reg = <0x0 0x04ef8800 0x0 0x400>; 1610 #address-cells = <2>; 1611 #size-cells = <2>; 1612 ranges; 1613 1614 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1615 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1616 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1617 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1618 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1619 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1620 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo"; 1621 1622 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1623 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1624 assigned-clock-rates = <19200000>, <66666667>; 1625 1626 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 1627 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1628 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1629 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 1630 interrupt-names = "pwr_event", 1631 "qusb2_phy", 1632 "hs_phy_irq", 1633 "ss_phy_irq"; 1634 1635 resets = <&gcc GCC_USB30_PRIM_BCR>; 1636 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1637 /* TODO: USB<->IPA path */ 1638 interconnects = <&system_noc MASTER_USB3 RPM_ALWAYS_TAG 1639 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, 1640 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1641 &config_noc SLAVE_USB3 RPM_ALWAYS_TAG>; 1642 interconnect-names = "usb-ddr", 1643 "apps-usb"; 1644 1645 status = "disabled"; 1646 1647 usb_dwc3: usb@4e00000 { 1648 compatible = "snps,dwc3"; 1649 reg = <0x0 0x04e00000 0x0 0xcd00>; 1650 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1651 phys = <&usb_hsphy>, <&usb_qmpphy>; 1652 phy-names = "usb2-phy", "usb3-phy"; 1653 iommus = <&apps_smmu 0x120 0x0>; 1654 snps,dis_u2_susphy_quirk; 1655 snps,dis_enblslpm_quirk; 1656 snps,has-lpm-erratum; 1657 snps,hird-threshold = /bits/ 8 <0x10>; 1658 snps,usb3_lpm_capable; 1659 1660 usb-role-switch; 1661 1662 ports { 1663 #address-cells = <1>; 1664 #size-cells = <0>; 1665 1666 port@0 { 1667 reg = <0>; 1668 1669 usb_dwc3_hs: endpoint { 1670 }; 1671 }; 1672 1673 port@1 { 1674 reg = <1>; 1675 1676 usb_dwc3_ss: endpoint { 1677 remote-endpoint = <&usb_qmpphy_usb_ss_in>; 1678 }; 1679 }; 1680 }; 1681 }; 1682 }; 1683 1684 gpu: gpu@5900000 { 1685 compatible = "qcom,adreno-610.0", "qcom,adreno"; 1686 reg = <0x0 0x05900000 0x0 0x40000>; 1687 reg-names = "kgsl_3d0_reg_memory"; 1688 1689 /* There's no (real) GMU, so we have to handle quite a bunch of clocks! */ 1690 clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, 1691 <&gpucc GPU_CC_AHB_CLK>, 1692 <&gcc GCC_BIMC_GPU_AXI_CLK>, 1693 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1694 <&gpucc GPU_CC_CX_GMU_CLK>, 1695 <&gpucc GPU_CC_CXO_CLK>; 1696 clock-names = "core", 1697 "iface", 1698 "mem_iface", 1699 "alt_mem_iface", 1700 "gmu", 1701 "xo"; 1702 1703 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 1704 1705 iommus = <&adreno_smmu 0 1>; 1706 operating-points-v2 = <&gpu_opp_table>; 1707 power-domains = <&rpmpd SM6115_VDDCX>; 1708 qcom,gmu = <&gmu_wrapper>; 1709 1710 nvmem-cells = <&gpu_speed_bin>; 1711 nvmem-cell-names = "speed_bin"; 1712 #cooling-cells = <2>; 1713 1714 status = "disabled"; 1715 1716 zap-shader { 1717 memory-region = <&pil_gpu_mem>; 1718 }; 1719 1720 gpu_opp_table: opp-table { 1721 compatible = "operating-points-v2"; 1722 1723 opp-320000000 { 1724 opp-hz = /bits/ 64 <320000000>; 1725 required-opps = <&rpmpd_opp_low_svs>; 1726 opp-supported-hw = <0x1f>; 1727 }; 1728 1729 opp-465000000 { 1730 opp-hz = /bits/ 64 <465000000>; 1731 required-opps = <&rpmpd_opp_svs>; 1732 opp-supported-hw = <0x1f>; 1733 }; 1734 1735 opp-600000000 { 1736 opp-hz = /bits/ 64 <600000000>; 1737 required-opps = <&rpmpd_opp_svs_plus>; 1738 opp-supported-hw = <0x1f>; 1739 }; 1740 1741 opp-745000000 { 1742 opp-hz = /bits/ 64 <745000000>; 1743 required-opps = <&rpmpd_opp_nom>; 1744 opp-supported-hw = <0xf>; 1745 }; 1746 1747 opp-820000000 { 1748 opp-hz = /bits/ 64 <820000000>; 1749 required-opps = <&rpmpd_opp_nom_plus>; 1750 opp-supported-hw = <0x7>; 1751 }; 1752 1753 opp-900000000 { 1754 opp-hz = /bits/ 64 <900000000>; 1755 required-opps = <&rpmpd_opp_turbo>; 1756 opp-supported-hw = <0x7>; 1757 }; 1758 1759 /* Speed bin 2 can reach 950 Mhz instead of 980 like the rest. */ 1760 opp-950000000 { 1761 opp-hz = /bits/ 64 <950000000>; 1762 required-opps = <&rpmpd_opp_turbo_plus>; 1763 opp-supported-hw = <0x4>; 1764 }; 1765 1766 opp-980000000 { 1767 opp-hz = /bits/ 64 <980000000>; 1768 required-opps = <&rpmpd_opp_turbo_plus>; 1769 opp-supported-hw = <0x3>; 1770 }; 1771 }; 1772 }; 1773 1774 gmu_wrapper: gmu@596a000 { 1775 compatible = "qcom,adreno-gmu-wrapper"; 1776 reg = <0x0 0x0596a000 0x0 0x30000>; 1777 reg-names = "gmu"; 1778 power-domains = <&gpucc GPU_CX_GDSC>, 1779 <&gpucc GPU_GX_GDSC>; 1780 power-domain-names = "cx", "gx"; 1781 }; 1782 1783 gpucc: clock-controller@5990000 { 1784 compatible = "qcom,sm6115-gpucc"; 1785 reg = <0x0 0x05990000 0x0 0x9000>; 1786 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1787 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1788 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1789 #clock-cells = <1>; 1790 #reset-cells = <1>; 1791 #power-domain-cells = <1>; 1792 }; 1793 1794 adreno_smmu: iommu@59a0000 { 1795 compatible = "qcom,sm6115-smmu-500", "qcom,adreno-smmu", 1796 "qcom,smmu-500", "arm,mmu-500"; 1797 reg = <0x0 0x059a0000 0x0 0x10000>; 1798 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1799 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 1800 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1801 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1802 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1803 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1804 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 1805 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1806 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1807 1808 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1809 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1810 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1811 clock-names = "mem", 1812 "hlos", 1813 "iface"; 1814 power-domains = <&gpucc GPU_CX_GDSC>; 1815 1816 #global-interrupts = <1>; 1817 #iommu-cells = <2>; 1818 }; 1819 1820 mdss: display-subsystem@5e00000 { 1821 compatible = "qcom,sm6115-mdss"; 1822 reg = <0x0 0x05e00000 0x0 0x1000>; 1823 reg-names = "mdss"; 1824 1825 power-domains = <&dispcc MDSS_GDSC>; 1826 1827 clocks = <&gcc GCC_DISP_AHB_CLK>, 1828 <&gcc GCC_DISP_HF_AXI_CLK>, 1829 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1830 1831 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1832 interrupt-controller; 1833 #interrupt-cells = <1>; 1834 1835 iommus = <&apps_smmu 0x420 0x2>, 1836 <&apps_smmu 0x421 0x0>; 1837 1838 interconnects = <&mmrt_virt MASTER_MDP_PORT0 RPM_ALWAYS_TAG 1839 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, 1840 <&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG 1841 &config_noc SLAVE_DISPLAY_CFG RPM_ALWAYS_TAG>; 1842 interconnect-names = "mdp0-mem", 1843 "cpu-cfg"; 1844 1845 #address-cells = <2>; 1846 #size-cells = <2>; 1847 ranges; 1848 1849 status = "disabled"; 1850 1851 mdp: display-controller@5e01000 { 1852 compatible = "qcom,sm6115-dpu"; 1853 reg = <0x0 0x05e01000 0x0 0x8f000>, 1854 <0x0 0x05eb0000 0x0 0x2008>; 1855 reg-names = "mdp", "vbif"; 1856 1857 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 1858 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1859 <&dispcc DISP_CC_MDSS_MDP_CLK>, 1860 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 1861 <&dispcc DISP_CC_MDSS_ROT_CLK>, 1862 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1863 clock-names = "bus", 1864 "iface", 1865 "core", 1866 "lut", 1867 "rot", 1868 "vsync"; 1869 1870 operating-points-v2 = <&mdp_opp_table>; 1871 power-domains = <&rpmpd SM6115_VDDCX>; 1872 1873 interrupt-parent = <&mdss>; 1874 interrupts = <0>; 1875 1876 ports { 1877 #address-cells = <1>; 1878 #size-cells = <0>; 1879 1880 port@0 { 1881 reg = <0>; 1882 dpu_intf1_out: endpoint { 1883 remote-endpoint = <&mdss_dsi0_in>; 1884 }; 1885 }; 1886 }; 1887 1888 mdp_opp_table: opp-table { 1889 compatible = "operating-points-v2"; 1890 1891 opp-19200000 { 1892 opp-hz = /bits/ 64 <19200000>; 1893 required-opps = <&rpmpd_opp_min_svs>; 1894 }; 1895 1896 opp-192000000 { 1897 opp-hz = /bits/ 64 <192000000>; 1898 required-opps = <&rpmpd_opp_low_svs>; 1899 }; 1900 1901 opp-256000000 { 1902 opp-hz = /bits/ 64 <256000000>; 1903 required-opps = <&rpmpd_opp_svs>; 1904 }; 1905 1906 opp-307200000 { 1907 opp-hz = /bits/ 64 <307200000>; 1908 required-opps = <&rpmpd_opp_svs_plus>; 1909 }; 1910 1911 opp-384000000 { 1912 opp-hz = /bits/ 64 <384000000>; 1913 required-opps = <&rpmpd_opp_nom>; 1914 }; 1915 }; 1916 }; 1917 1918 mdss_dsi0: dsi@5e94000 { 1919 compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 1920 reg = <0x0 0x05e94000 0x0 0x400>; 1921 reg-names = "dsi_ctrl"; 1922 1923 interrupt-parent = <&mdss>; 1924 interrupts = <4>; 1925 1926 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 1927 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 1928 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 1929 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 1930 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1931 <&gcc GCC_DISP_HF_AXI_CLK>; 1932 clock-names = "byte", 1933 "byte_intf", 1934 "pixel", 1935 "core", 1936 "iface", 1937 "bus"; 1938 1939 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 1940 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 1941 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 1942 1943 operating-points-v2 = <&dsi_opp_table>; 1944 power-domains = <&rpmpd SM6115_VDDCX>; 1945 phys = <&mdss_dsi0_phy>; 1946 1947 #address-cells = <1>; 1948 #size-cells = <0>; 1949 1950 status = "disabled"; 1951 1952 ports { 1953 #address-cells = <1>; 1954 #size-cells = <0>; 1955 1956 port@0 { 1957 reg = <0>; 1958 mdss_dsi0_in: endpoint { 1959 remote-endpoint = <&dpu_intf1_out>; 1960 }; 1961 }; 1962 1963 port@1 { 1964 reg = <1>; 1965 mdss_dsi0_out: endpoint { 1966 }; 1967 }; 1968 }; 1969 1970 dsi_opp_table: opp-table { 1971 compatible = "operating-points-v2"; 1972 1973 opp-19200000 { 1974 opp-hz = /bits/ 64 <19200000>; 1975 required-opps = <&rpmpd_opp_min_svs>; 1976 }; 1977 1978 opp-164000000 { 1979 opp-hz = /bits/ 64 <164000000>; 1980 required-opps = <&rpmpd_opp_low_svs>; 1981 }; 1982 1983 opp-187500000 { 1984 opp-hz = /bits/ 64 <187500000>; 1985 required-opps = <&rpmpd_opp_svs>; 1986 }; 1987 }; 1988 }; 1989 1990 mdss_dsi0_phy: phy@5e94400 { 1991 compatible = "qcom,dsi-phy-14nm-2290"; 1992 reg = <0x0 0x05e94400 0x0 0x100>, 1993 <0x0 0x05e94500 0x0 0x300>, 1994 <0x0 0x05e94800 0x0 0x188>; 1995 reg-names = "dsi_phy", 1996 "dsi_phy_lane", 1997 "dsi_pll"; 1998 1999 #clock-cells = <1>; 2000 #phy-cells = <0>; 2001 2002 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2003 <&rpmcc RPM_SMD_XO_CLK_SRC>; 2004 clock-names = "iface", "ref"; 2005 2006 status = "disabled"; 2007 }; 2008 }; 2009 2010 dispcc: clock-controller@5f00000 { 2011 compatible = "qcom,sm6115-dispcc"; 2012 reg = <0x0 0x05f00000 0 0x20000>; 2013 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 2014 <&sleep_clk>, 2015 <&mdss_dsi0_phy 0>, 2016 <&mdss_dsi0_phy 1>, 2017 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; 2018 #clock-cells = <1>; 2019 #reset-cells = <1>; 2020 #power-domain-cells = <1>; 2021 }; 2022 2023 remoteproc_mpss: remoteproc@6080000 { 2024 compatible = "qcom,sm6115-mpss-pas"; 2025 reg = <0x0 0x06080000 0x0 0x100>; 2026 2027 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, 2028 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2029 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2030 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2031 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2032 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2033 interrupt-names = "wdog", "fatal", "ready", "handover", 2034 "stop-ack", "shutdown-ack"; 2035 2036 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2037 clock-names = "xo"; 2038 2039 power-domains = <&rpmpd SM6115_VDDCX>; 2040 2041 memory-region = <&pil_modem_mem>; 2042 2043 qcom,smem-states = <&modem_smp2p_out 0>; 2044 qcom,smem-state-names = "stop"; 2045 2046 status = "disabled"; 2047 2048 glink-edge { 2049 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; 2050 label = "mpss"; 2051 qcom,remote-pid = <1>; 2052 mboxes = <&apcs_glb 12>; 2053 }; 2054 }; 2055 2056 stm@8002000 { 2057 compatible = "arm,coresight-stm", "arm,primecell"; 2058 reg = <0x0 0x08002000 0x0 0x1000>, 2059 <0x0 0x0e280000 0x0 0x180000>; 2060 reg-names = "stm-base", "stm-stimulus-base"; 2061 2062 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2063 clock-names = "apb_pclk"; 2064 2065 status = "disabled"; 2066 2067 out-ports { 2068 port { 2069 stm_out: endpoint { 2070 remote-endpoint = <&funnel_in0_in>; 2071 }; 2072 }; 2073 }; 2074 }; 2075 2076 cti0: cti@8010000 { 2077 compatible = "arm,coresight-cti", "arm,primecell"; 2078 reg = <0x0 0x08010000 0x0 0x1000>; 2079 2080 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2081 clock-names = "apb_pclk"; 2082 2083 status = "disabled"; 2084 }; 2085 2086 cti1: cti@8011000 { 2087 compatible = "arm,coresight-cti", "arm,primecell"; 2088 reg = <0x0 0x08011000 0x0 0x1000>; 2089 2090 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2091 clock-names = "apb_pclk"; 2092 2093 status = "disabled"; 2094 }; 2095 2096 cti2: cti@8012000 { 2097 compatible = "arm,coresight-cti", "arm,primecell"; 2098 reg = <0x0 0x08012000 0x0 0x1000>; 2099 2100 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2101 clock-names = "apb_pclk"; 2102 2103 status = "disabled"; 2104 }; 2105 2106 cti3: cti@8013000 { 2107 compatible = "arm,coresight-cti", "arm,primecell"; 2108 reg = <0x0 0x08013000 0x0 0x1000>; 2109 2110 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2111 clock-names = "apb_pclk"; 2112 2113 status = "disabled"; 2114 }; 2115 2116 cti4: cti@8014000 { 2117 compatible = "arm,coresight-cti", "arm,primecell"; 2118 reg = <0x0 0x08014000 0x0 0x1000>; 2119 2120 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2121 clock-names = "apb_pclk"; 2122 2123 status = "disabled"; 2124 }; 2125 2126 cti5: cti@8015000 { 2127 compatible = "arm,coresight-cti", "arm,primecell"; 2128 reg = <0x0 0x08015000 0x0 0x1000>; 2129 2130 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2131 clock-names = "apb_pclk"; 2132 2133 status = "disabled"; 2134 }; 2135 2136 cti6: cti@8016000 { 2137 compatible = "arm,coresight-cti", "arm,primecell"; 2138 reg = <0x0 0x08016000 0x0 0x1000>; 2139 2140 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2141 clock-names = "apb_pclk"; 2142 2143 status = "disabled"; 2144 }; 2145 2146 cti7: cti@8017000 { 2147 compatible = "arm,coresight-cti", "arm,primecell"; 2148 reg = <0x0 0x08017000 0x0 0x1000>; 2149 2150 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2151 clock-names = "apb_pclk"; 2152 2153 status = "disabled"; 2154 }; 2155 2156 cti8: cti@8018000 { 2157 compatible = "arm,coresight-cti", "arm,primecell"; 2158 reg = <0x0 0x08018000 0x0 0x1000>; 2159 2160 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2161 clock-names = "apb_pclk"; 2162 2163 status = "disabled"; 2164 }; 2165 2166 cti9: cti@8019000 { 2167 compatible = "arm,coresight-cti", "arm,primecell"; 2168 reg = <0x0 0x08019000 0x0 0x1000>; 2169 2170 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2171 clock-names = "apb_pclk"; 2172 2173 status = "disabled"; 2174 }; 2175 2176 cti10: cti@801a000 { 2177 compatible = "arm,coresight-cti", "arm,primecell"; 2178 reg = <0x0 0x0801a000 0x0 0x1000>; 2179 2180 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2181 clock-names = "apb_pclk"; 2182 2183 status = "disabled"; 2184 }; 2185 2186 cti11: cti@801b000 { 2187 compatible = "arm,coresight-cti", "arm,primecell"; 2188 reg = <0x0 0x0801b000 0x0 0x1000>; 2189 2190 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2191 clock-names = "apb_pclk"; 2192 2193 status = "disabled"; 2194 }; 2195 2196 cti12: cti@801c000 { 2197 compatible = "arm,coresight-cti", "arm,primecell"; 2198 reg = <0x0 0x0801c000 0x0 0x1000>; 2199 2200 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2201 clock-names = "apb_pclk"; 2202 2203 status = "disabled"; 2204 }; 2205 2206 cti13: cti@801d000 { 2207 compatible = "arm,coresight-cti", "arm,primecell"; 2208 reg = <0x0 0x0801d000 0x0 0x1000>; 2209 2210 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2211 clock-names = "apb_pclk"; 2212 2213 status = "disabled"; 2214 }; 2215 2216 cti14: cti@801e000 { 2217 compatible = "arm,coresight-cti", "arm,primecell"; 2218 reg = <0x0 0x0801e000 0x0 0x1000>; 2219 2220 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2221 clock-names = "apb_pclk"; 2222 2223 status = "disabled"; 2224 }; 2225 2226 cti15: cti@801f000 { 2227 compatible = "arm,coresight-cti", "arm,primecell"; 2228 reg = <0x0 0x0801f000 0x0 0x1000>; 2229 2230 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2231 clock-names = "apb_pclk"; 2232 2233 status = "disabled"; 2234 }; 2235 2236 replicator@8046000 { 2237 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2238 reg = <0x0 0x08046000 0x0 0x1000>; 2239 2240 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2241 clock-names = "apb_pclk"; 2242 2243 status = "disabled"; 2244 2245 out-ports { 2246 port { 2247 replicator_out: endpoint { 2248 remote-endpoint = <&etr_in>; 2249 }; 2250 }; 2251 }; 2252 2253 in-ports { 2254 port { 2255 replicator_in: endpoint { 2256 remote-endpoint = <&etf_out>; 2257 }; 2258 }; 2259 }; 2260 }; 2261 2262 etf@8047000 { 2263 compatible = "arm,coresight-tmc", "arm,primecell"; 2264 reg = <0x0 0x08047000 0x0 0x1000>; 2265 2266 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2267 clock-names = "apb_pclk"; 2268 2269 status = "disabled"; 2270 2271 in-ports { 2272 port { 2273 etf_in: endpoint { 2274 remote-endpoint = <&merge_funnel_out>; 2275 }; 2276 }; 2277 }; 2278 2279 out-ports { 2280 port { 2281 etf_out: endpoint { 2282 remote-endpoint = <&replicator_in>; 2283 }; 2284 }; 2285 }; 2286 }; 2287 2288 etr@8048000 { 2289 compatible = "arm,coresight-tmc", "arm,primecell"; 2290 reg = <0x0 0x08048000 0x0 0x1000>; 2291 2292 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2293 clock-names = "apb_pclk"; 2294 2295 status = "disabled"; 2296 2297 in-ports { 2298 port { 2299 etr_in: endpoint { 2300 remote-endpoint = <&replicator_out>; 2301 }; 2302 }; 2303 }; 2304 }; 2305 2306 funnel@8041000 { 2307 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2308 reg = <0x0 0x08041000 0x0 0x1000>; 2309 2310 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2311 clock-names = "apb_pclk"; 2312 2313 status = "disabled"; 2314 2315 out-ports { 2316 port { 2317 funnel_in0_out: endpoint { 2318 remote-endpoint = <&merge_funnel_in0>; 2319 }; 2320 }; 2321 }; 2322 2323 in-ports { 2324 port { 2325 funnel_in0_in: endpoint { 2326 remote-endpoint = <&stm_out>; 2327 }; 2328 }; 2329 }; 2330 }; 2331 2332 funnel@8042000 { 2333 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2334 reg = <0x0 0x08042000 0x0 0x1000>; 2335 2336 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2337 clock-names = "apb_pclk"; 2338 2339 status = "disabled"; 2340 2341 out-ports { 2342 port { 2343 funnel_in1_out: endpoint { 2344 remote-endpoint = <&merge_funnel_in1>; 2345 }; 2346 }; 2347 }; 2348 2349 in-ports { 2350 port { 2351 funnel_in1_in: endpoint { 2352 remote-endpoint = <&funnel_apss1_out>; 2353 }; 2354 }; 2355 }; 2356 }; 2357 2358 funnel@8045000 { 2359 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2360 reg = <0x0 0x08045000 0x0 0x1000>; 2361 2362 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2363 clock-names = "apb_pclk"; 2364 2365 status = "disabled"; 2366 2367 out-ports { 2368 port { 2369 merge_funnel_out: endpoint { 2370 remote-endpoint = <&etf_in>; 2371 }; 2372 }; 2373 }; 2374 2375 in-ports { 2376 #address-cells = <1>; 2377 #size-cells = <0>; 2378 2379 port@0 { 2380 reg = <0>; 2381 merge_funnel_in0: endpoint { 2382 remote-endpoint = <&funnel_in0_out>; 2383 }; 2384 }; 2385 2386 port@1 { 2387 reg = <1>; 2388 merge_funnel_in1: endpoint { 2389 remote-endpoint = <&funnel_in1_out>; 2390 }; 2391 }; 2392 }; 2393 }; 2394 2395 etm@9040000 { 2396 compatible = "arm,coresight-etm4x", "arm,primecell"; 2397 reg = <0x0 0x09040000 0x0 0x1000>; 2398 2399 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2400 clock-names = "apb_pclk"; 2401 arm,coresight-loses-context-with-cpu; 2402 2403 cpu = <&CPU0>; 2404 2405 status = "disabled"; 2406 2407 out-ports { 2408 port { 2409 etm0_out: endpoint { 2410 remote-endpoint = <&funnel_apss0_in0>; 2411 }; 2412 }; 2413 }; 2414 }; 2415 2416 etm@9140000 { 2417 compatible = "arm,coresight-etm4x", "arm,primecell"; 2418 reg = <0x0 0x09140000 0x0 0x1000>; 2419 2420 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2421 clock-names = "apb_pclk"; 2422 arm,coresight-loses-context-with-cpu; 2423 2424 cpu = <&CPU1>; 2425 2426 status = "disabled"; 2427 2428 out-ports { 2429 port { 2430 etm1_out: endpoint { 2431 remote-endpoint = <&funnel_apss0_in1>; 2432 }; 2433 }; 2434 }; 2435 }; 2436 2437 etm@9240000 { 2438 compatible = "arm,coresight-etm4x", "arm,primecell"; 2439 reg = <0x0 0x09240000 0x0 0x1000>; 2440 2441 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2442 clock-names = "apb_pclk"; 2443 arm,coresight-loses-context-with-cpu; 2444 2445 cpu = <&CPU2>; 2446 2447 status = "disabled"; 2448 2449 out-ports { 2450 port { 2451 etm2_out: endpoint { 2452 remote-endpoint = <&funnel_apss0_in2>; 2453 }; 2454 }; 2455 }; 2456 }; 2457 2458 etm@9340000 { 2459 compatible = "arm,coresight-etm4x", "arm,primecell"; 2460 reg = <0x0 0x09340000 0x0 0x1000>; 2461 2462 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2463 clock-names = "apb_pclk"; 2464 arm,coresight-loses-context-with-cpu; 2465 2466 cpu = <&CPU3>; 2467 2468 status = "disabled"; 2469 2470 out-ports { 2471 port { 2472 etm3_out: endpoint { 2473 remote-endpoint = <&funnel_apss0_in3>; 2474 }; 2475 }; 2476 }; 2477 }; 2478 2479 etm@9440000 { 2480 compatible = "arm,coresight-etm4x", "arm,primecell"; 2481 reg = <0x0 0x09440000 0x0 0x1000>; 2482 2483 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2484 clock-names = "apb_pclk"; 2485 arm,coresight-loses-context-with-cpu; 2486 2487 cpu = <&CPU4>; 2488 2489 status = "disabled"; 2490 2491 out-ports { 2492 port { 2493 etm4_out: endpoint { 2494 remote-endpoint = <&funnel_apss0_in4>; 2495 }; 2496 }; 2497 }; 2498 }; 2499 2500 etm@9540000 { 2501 compatible = "arm,coresight-etm4x", "arm,primecell"; 2502 reg = <0x0 0x09540000 0x0 0x1000>; 2503 2504 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2505 clock-names = "apb_pclk"; 2506 arm,coresight-loses-context-with-cpu; 2507 2508 cpu = <&CPU5>; 2509 2510 status = "disabled"; 2511 2512 out-ports { 2513 port { 2514 etm5_out: endpoint { 2515 remote-endpoint = <&funnel_apss0_in5>; 2516 }; 2517 }; 2518 }; 2519 }; 2520 2521 etm@9640000 { 2522 compatible = "arm,coresight-etm4x", "arm,primecell"; 2523 reg = <0x0 0x09640000 0x0 0x1000>; 2524 2525 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2526 clock-names = "apb_pclk"; 2527 arm,coresight-loses-context-with-cpu; 2528 2529 cpu = <&CPU6>; 2530 2531 status = "disabled"; 2532 2533 out-ports { 2534 port { 2535 etm6_out: endpoint { 2536 remote-endpoint = <&funnel_apss0_in6>; 2537 }; 2538 }; 2539 }; 2540 }; 2541 2542 etm@9740000 { 2543 compatible = "arm,coresight-etm4x", "arm,primecell"; 2544 reg = <0x0 0x09740000 0x0 0x1000>; 2545 2546 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2547 clock-names = "apb_pclk"; 2548 arm,coresight-loses-context-with-cpu; 2549 2550 cpu = <&CPU7>; 2551 2552 status = "disabled"; 2553 2554 out-ports { 2555 port { 2556 etm7_out: endpoint { 2557 remote-endpoint = <&funnel_apss0_in7>; 2558 }; 2559 }; 2560 }; 2561 }; 2562 2563 funnel@9800000 { 2564 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2565 reg = <0x0 0x09800000 0x0 0x1000>; 2566 2567 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2568 clock-names = "apb_pclk"; 2569 2570 status = "disabled"; 2571 2572 out-ports { 2573 port { 2574 funnel_apss0_out: endpoint { 2575 remote-endpoint = <&funnel_apss1_in>; 2576 }; 2577 }; 2578 }; 2579 2580 in-ports { 2581 #address-cells = <1>; 2582 #size-cells = <0>; 2583 2584 port@0 { 2585 reg = <0>; 2586 funnel_apss0_in0: endpoint { 2587 remote-endpoint = <&etm0_out>; 2588 }; 2589 }; 2590 2591 port@1 { 2592 reg = <1>; 2593 funnel_apss0_in1: endpoint { 2594 remote-endpoint = <&etm1_out>; 2595 }; 2596 }; 2597 2598 port@2 { 2599 reg = <2>; 2600 funnel_apss0_in2: endpoint { 2601 remote-endpoint = <&etm2_out>; 2602 }; 2603 }; 2604 2605 port@3 { 2606 reg = <3>; 2607 funnel_apss0_in3: endpoint { 2608 remote-endpoint = <&etm3_out>; 2609 }; 2610 }; 2611 2612 port@4 { 2613 reg = <4>; 2614 funnel_apss0_in4: endpoint { 2615 remote-endpoint = <&etm4_out>; 2616 }; 2617 }; 2618 2619 port@5 { 2620 reg = <5>; 2621 funnel_apss0_in5: endpoint { 2622 remote-endpoint = <&etm5_out>; 2623 }; 2624 }; 2625 2626 port@6 { 2627 reg = <6>; 2628 funnel_apss0_in6: endpoint { 2629 remote-endpoint = <&etm6_out>; 2630 }; 2631 }; 2632 2633 port@7 { 2634 reg = <7>; 2635 funnel_apss0_in7: endpoint { 2636 remote-endpoint = <&etm7_out>; 2637 }; 2638 }; 2639 }; 2640 }; 2641 2642 funnel@9810000 { 2643 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2644 reg = <0x0 0x09810000 0x0 0x1000>; 2645 2646 clocks = <&rpmcc RPM_SMD_QDSS_CLK>; 2647 clock-names = "apb_pclk"; 2648 2649 status = "disabled"; 2650 2651 out-ports { 2652 port { 2653 funnel_apss1_out: endpoint { 2654 remote-endpoint = <&funnel_in1_in>; 2655 }; 2656 }; 2657 }; 2658 2659 in-ports { 2660 port { 2661 funnel_apss1_in: endpoint { 2662 remote-endpoint = <&funnel_apss0_out>; 2663 }; 2664 }; 2665 }; 2666 }; 2667 2668 remoteproc_adsp: remoteproc@ab00000 { 2669 compatible = "qcom,sm6115-adsp-pas"; 2670 reg = <0x0 0x0ab00000 0x0 0x100>; 2671 2672 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, 2673 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2674 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2675 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2676 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2677 interrupt-names = "wdog", "fatal", "ready", 2678 "handover", "stop-ack"; 2679 2680 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2681 clock-names = "xo"; 2682 2683 power-domains = <&rpmpd SM6115_VDD_LPI_CX>, 2684 <&rpmpd SM6115_VDD_LPI_MX>; 2685 2686 memory-region = <&pil_adsp_mem>; 2687 2688 qcom,smem-states = <&adsp_smp2p_out 0>; 2689 qcom,smem-state-names = "stop"; 2690 2691 status = "disabled"; 2692 2693 glink-edge { 2694 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; 2695 label = "lpass"; 2696 qcom,remote-pid = <2>; 2697 mboxes = <&apcs_glb 8>; 2698 2699 fastrpc { 2700 compatible = "qcom,fastrpc"; 2701 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2702 label = "adsp"; 2703 qcom,non-secure-domain; 2704 #address-cells = <1>; 2705 #size-cells = <0>; 2706 2707 compute-cb@3 { 2708 compatible = "qcom,fastrpc-compute-cb"; 2709 reg = <3>; 2710 iommus = <&apps_smmu 0x01c3 0x0>; 2711 }; 2712 2713 compute-cb@4 { 2714 compatible = "qcom,fastrpc-compute-cb"; 2715 reg = <4>; 2716 iommus = <&apps_smmu 0x01c4 0x0>; 2717 }; 2718 2719 compute-cb@5 { 2720 compatible = "qcom,fastrpc-compute-cb"; 2721 reg = <5>; 2722 iommus = <&apps_smmu 0x01c5 0x0>; 2723 }; 2724 2725 compute-cb@6 { 2726 compatible = "qcom,fastrpc-compute-cb"; 2727 reg = <6>; 2728 iommus = <&apps_smmu 0x01c6 0x0>; 2729 }; 2730 2731 compute-cb@7 { 2732 compatible = "qcom,fastrpc-compute-cb"; 2733 reg = <7>; 2734 iommus = <&apps_smmu 0x01c7 0x0>; 2735 }; 2736 }; 2737 }; 2738 }; 2739 2740 remoteproc_cdsp: remoteproc@b300000 { 2741 compatible = "qcom,sm6115-cdsp-pas"; 2742 reg = <0x0 0x0b300000 0x0 0x100000>; 2743 2744 interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 2745 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2746 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2747 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2748 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2749 interrupt-names = "wdog", "fatal", "ready", 2750 "handover", "stop-ack"; 2751 2752 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2753 clock-names = "xo"; 2754 2755 power-domains = <&rpmpd SM6115_VDDCX>; 2756 2757 memory-region = <&pil_cdsp_mem>; 2758 2759 qcom,smem-states = <&cdsp_smp2p_out 0>; 2760 qcom,smem-state-names = "stop"; 2761 2762 status = "disabled"; 2763 2764 glink-edge { 2765 interrupts = <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>; 2766 label = "cdsp"; 2767 qcom,remote-pid = <5>; 2768 mboxes = <&apcs_glb 28>; 2769 2770 fastrpc { 2771 compatible = "qcom,fastrpc"; 2772 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2773 label = "cdsp"; 2774 qcom,non-secure-domain; 2775 #address-cells = <1>; 2776 #size-cells = <0>; 2777 2778 compute-cb@1 { 2779 compatible = "qcom,fastrpc-compute-cb"; 2780 reg = <1>; 2781 iommus = <&apps_smmu 0x0c01 0x0>; 2782 }; 2783 2784 compute-cb@2 { 2785 compatible = "qcom,fastrpc-compute-cb"; 2786 reg = <2>; 2787 iommus = <&apps_smmu 0x0c02 0x0>; 2788 }; 2789 2790 compute-cb@3 { 2791 compatible = "qcom,fastrpc-compute-cb"; 2792 reg = <3>; 2793 iommus = <&apps_smmu 0x0c03 0x0>; 2794 }; 2795 2796 compute-cb@4 { 2797 compatible = "qcom,fastrpc-compute-cb"; 2798 reg = <4>; 2799 iommus = <&apps_smmu 0x0c04 0x0>; 2800 }; 2801 2802 compute-cb@5 { 2803 compatible = "qcom,fastrpc-compute-cb"; 2804 reg = <5>; 2805 iommus = <&apps_smmu 0x0c05 0x0>; 2806 }; 2807 2808 compute-cb@6 { 2809 compatible = "qcom,fastrpc-compute-cb"; 2810 reg = <6>; 2811 iommus = <&apps_smmu 0x0c06 0x0>; 2812 }; 2813 2814 /* note: secure cb9 in downstream */ 2815 }; 2816 }; 2817 }; 2818 2819 apps_smmu: iommu@c600000 { 2820 compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 2821 reg = <0x0 0x0c600000 0x0 0x80000>; 2822 #iommu-cells = <2>; 2823 #global-interrupts = <1>; 2824 2825 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 2826 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 2827 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 2828 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 2829 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 2830 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 2831 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 2832 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 2833 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 2834 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 2835 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2836 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2837 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2838 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2839 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2840 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2841 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2842 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2843 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2844 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2845 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2846 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2847 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2848 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2849 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2850 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2851 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2852 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2853 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2854 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2855 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2856 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2857 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 2858 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 2859 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 2860 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 2861 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 2862 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 2863 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2864 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 2865 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 2866 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 2867 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 2868 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2869 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2870 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 2871 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 2872 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 2873 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 2874 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2875 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 2876 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 2877 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 2878 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 2879 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2880 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2881 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2882 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2883 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2884 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2885 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2886 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2887 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2888 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 2889 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 2890 }; 2891 2892 wifi: wifi@c800000 { 2893 compatible = "qcom,wcn3990-wifi"; 2894 reg = <0x0 0x0c800000 0x0 0x800000>; 2895 reg-names = "membase"; 2896 memory-region = <&wlan_msa_mem>; 2897 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 2898 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 2899 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 2900 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 2901 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 2902 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 2903 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 2904 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 2905 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 2906 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 2907 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 2908 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2909 iommus = <&apps_smmu 0x1a0 0x1>; 2910 qcom,msa-fixed-perm; 2911 status = "disabled"; 2912 }; 2913 2914 watchdog@f017000 { 2915 compatible = "qcom,apss-wdt-sm6115", "qcom,kpss-wdt"; 2916 reg = <0x0 0x0f017000 0x0 0x1000>; 2917 clocks = <&sleep_clk>; 2918 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 2919 }; 2920 2921 apcs_glb: mailbox@f111000 { 2922 compatible = "qcom,sm6115-apcs-hmss-global", 2923 "qcom,msm8994-apcs-kpss-global"; 2924 reg = <0x0 0x0f111000 0x0 0x1000>; 2925 2926 #mbox-cells = <1>; 2927 }; 2928 2929 timer@f120000 { 2930 compatible = "arm,armv7-timer-mem"; 2931 reg = <0x0 0x0f120000 0x0 0x1000>; 2932 #address-cells = <2>; 2933 #size-cells = <1>; 2934 ranges = <0x0 0x0 0x0 0x0 0x20000000>; 2935 clock-frequency = <19200000>; 2936 2937 frame@f121000 { 2938 reg = <0x0 0x0f121000 0x1000>, <0x0 0x0f122000 0x1000>; 2939 frame-number = <0>; 2940 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2941 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2942 }; 2943 2944 frame@f123000 { 2945 reg = <0x0 0x0f123000 0x1000>; 2946 frame-number = <1>; 2947 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2948 status = "disabled"; 2949 }; 2950 2951 frame@f124000 { 2952 reg = <0x0 0x0f124000 0x1000>; 2953 frame-number = <2>; 2954 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2955 status = "disabled"; 2956 }; 2957 2958 frame@f125000 { 2959 reg = <0x0 0x0f125000 0x1000>; 2960 frame-number = <3>; 2961 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2962 status = "disabled"; 2963 }; 2964 2965 frame@f126000 { 2966 reg = <0x0 0x0f126000 0x1000>; 2967 frame-number = <4>; 2968 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2969 status = "disabled"; 2970 }; 2971 2972 frame@f127000 { 2973 reg = <0x0 0x0f127000 0x1000>; 2974 frame-number = <5>; 2975 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2976 status = "disabled"; 2977 }; 2978 2979 frame@f128000 { 2980 reg = <0x0 0x0f128000 0x1000>; 2981 frame-number = <6>; 2982 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2983 status = "disabled"; 2984 }; 2985 }; 2986 2987 intc: interrupt-controller@f200000 { 2988 compatible = "arm,gic-v3"; 2989 reg = <0x0 0x0f200000 0x0 0x10000>, 2990 <0x0 0x0f300000 0x0 0x100000>; 2991 #interrupt-cells = <3>; 2992 interrupt-controller; 2993 interrupt-parent = <&intc>; 2994 #redistributor-regions = <1>; 2995 redistributor-stride = <0x0 0x20000>; 2996 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2997 }; 2998 2999 cpufreq_hw: cpufreq@f521000 { 3000 compatible = "qcom,sm6115-cpufreq-hw", "qcom,cpufreq-hw"; 3001 reg = <0x0 0x0f521000 0x0 0x1000>, 3002 <0x0 0x0f523000 0x0 0x1000>; 3003 3004 reg-names = "freq-domain0", "freq-domain1"; 3005 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 3006 clock-names = "xo", "alternate"; 3007 3008 #freq-domain-cells = <1>; 3009 #clock-cells = <1>; 3010 }; 3011 }; 3012 3013 thermal-zones { 3014 mapss-thermal { 3015 polling-delay-passive = <0>; 3016 polling-delay = <0>; 3017 thermal-sensors = <&tsens0 0>; 3018 3019 trips { 3020 trip-point0 { 3021 temperature = <115000>; 3022 hysteresis = <5000>; 3023 type = "passive"; 3024 }; 3025 3026 trip-point1 { 3027 temperature = <125000>; 3028 hysteresis = <1000>; 3029 type = "passive"; 3030 }; 3031 }; 3032 }; 3033 3034 cdsp-hvx-thermal { 3035 polling-delay-passive = <0>; 3036 polling-delay = <0>; 3037 thermal-sensors = <&tsens0 1>; 3038 3039 trips { 3040 trip-point0 { 3041 temperature = <115000>; 3042 hysteresis = <5000>; 3043 type = "passive"; 3044 }; 3045 3046 trip-point1 { 3047 temperature = <125000>; 3048 hysteresis = <1000>; 3049 type = "passive"; 3050 }; 3051 }; 3052 }; 3053 3054 wlan-thermal { 3055 polling-delay-passive = <0>; 3056 polling-delay = <0>; 3057 thermal-sensors = <&tsens0 2>; 3058 3059 trips { 3060 trip-point0 { 3061 temperature = <115000>; 3062 hysteresis = <5000>; 3063 type = "passive"; 3064 }; 3065 3066 trip-point1 { 3067 temperature = <125000>; 3068 hysteresis = <1000>; 3069 type = "passive"; 3070 }; 3071 }; 3072 }; 3073 3074 camera-thermal { 3075 polling-delay-passive = <0>; 3076 polling-delay = <0>; 3077 thermal-sensors = <&tsens0 3>; 3078 3079 trips { 3080 trip-point0 { 3081 temperature = <115000>; 3082 hysteresis = <5000>; 3083 type = "passive"; 3084 }; 3085 3086 trip-point1 { 3087 temperature = <125000>; 3088 hysteresis = <1000>; 3089 type = "passive"; 3090 }; 3091 }; 3092 }; 3093 3094 video-thermal { 3095 polling-delay-passive = <0>; 3096 polling-delay = <0>; 3097 thermal-sensors = <&tsens0 4>; 3098 3099 trips { 3100 trip-point0 { 3101 temperature = <115000>; 3102 hysteresis = <5000>; 3103 type = "passive"; 3104 }; 3105 3106 trip-point1 { 3107 temperature = <125000>; 3108 hysteresis = <1000>; 3109 type = "passive"; 3110 }; 3111 }; 3112 }; 3113 3114 modem1-thermal { 3115 polling-delay-passive = <0>; 3116 polling-delay = <0>; 3117 thermal-sensors = <&tsens0 5>; 3118 3119 trips { 3120 trip-point0 { 3121 temperature = <115000>; 3122 hysteresis = <5000>; 3123 type = "passive"; 3124 }; 3125 3126 trip-point1 { 3127 temperature = <125000>; 3128 hysteresis = <1000>; 3129 type = "passive"; 3130 }; 3131 }; 3132 }; 3133 3134 cpu4-thermal { 3135 polling-delay-passive = <0>; 3136 polling-delay = <0>; 3137 thermal-sensors = <&tsens0 6>; 3138 3139 trips { 3140 cpu4_alert0: trip-point0 { 3141 temperature = <90000>; 3142 hysteresis = <2000>; 3143 type = "passive"; 3144 }; 3145 3146 cpu4_alert1: trip-point1 { 3147 temperature = <95000>; 3148 hysteresis = <2000>; 3149 type = "passive"; 3150 }; 3151 3152 cpu4_crit: cpu-crit { 3153 temperature = <110000>; 3154 hysteresis = <1000>; 3155 type = "critical"; 3156 }; 3157 }; 3158 }; 3159 3160 cpu5-thermal { 3161 polling-delay-passive = <0>; 3162 polling-delay = <0>; 3163 thermal-sensors = <&tsens0 7>; 3164 3165 trips { 3166 cpu5_alert0: trip-point0 { 3167 temperature = <90000>; 3168 hysteresis = <2000>; 3169 type = "passive"; 3170 }; 3171 3172 cpu5_alert1: trip-point1 { 3173 temperature = <95000>; 3174 hysteresis = <2000>; 3175 type = "passive"; 3176 }; 3177 3178 cpu5_crit: cpu-crit { 3179 temperature = <110000>; 3180 hysteresis = <1000>; 3181 type = "critical"; 3182 }; 3183 }; 3184 }; 3185 3186 cpu6-thermal { 3187 polling-delay-passive = <0>; 3188 polling-delay = <0>; 3189 thermal-sensors = <&tsens0 8>; 3190 3191 trips { 3192 cpu6_alert0: trip-point0 { 3193 temperature = <90000>; 3194 hysteresis = <2000>; 3195 type = "passive"; 3196 }; 3197 3198 cpu6_alert1: trip-point1 { 3199 temperature = <95000>; 3200 hysteresis = <2000>; 3201 type = "passive"; 3202 }; 3203 3204 cpu6_crit: cpu-crit { 3205 temperature = <110000>; 3206 hysteresis = <1000>; 3207 type = "critical"; 3208 }; 3209 }; 3210 }; 3211 3212 cpu7-thermal { 3213 polling-delay-passive = <0>; 3214 polling-delay = <0>; 3215 thermal-sensors = <&tsens0 9>; 3216 3217 trips { 3218 cpu7_alert0: trip-point0 { 3219 temperature = <90000>; 3220 hysteresis = <2000>; 3221 type = "passive"; 3222 }; 3223 3224 cpu7_alert1: trip-point1 { 3225 temperature = <95000>; 3226 hysteresis = <2000>; 3227 type = "passive"; 3228 }; 3229 3230 cpu7_crit: cpu-crit { 3231 temperature = <110000>; 3232 hysteresis = <1000>; 3233 type = "critical"; 3234 }; 3235 }; 3236 }; 3237 3238 cpu45-thermal { 3239 polling-delay-passive = <0>; 3240 polling-delay = <0>; 3241 thermal-sensors = <&tsens0 10>; 3242 3243 trips { 3244 cpu45_alert0: trip-point0 { 3245 temperature = <90000>; 3246 hysteresis = <2000>; 3247 type = "passive"; 3248 }; 3249 3250 cpu45_alert1: trip-point1 { 3251 temperature = <95000>; 3252 hysteresis = <2000>; 3253 type = "passive"; 3254 }; 3255 3256 cpu45_crit: cpu-crit { 3257 temperature = <110000>; 3258 hysteresis = <1000>; 3259 type = "critical"; 3260 }; 3261 }; 3262 }; 3263 3264 cpu67-thermal { 3265 polling-delay-passive = <0>; 3266 polling-delay = <0>; 3267 thermal-sensors = <&tsens0 11>; 3268 3269 trips { 3270 cpu67_alert0: trip-point0 { 3271 temperature = <90000>; 3272 hysteresis = <2000>; 3273 type = "passive"; 3274 }; 3275 3276 cpu67_alert1: trip-point1 { 3277 temperature = <95000>; 3278 hysteresis = <2000>; 3279 type = "passive"; 3280 }; 3281 3282 cpu67_crit: cpu-crit { 3283 temperature = <110000>; 3284 hysteresis = <1000>; 3285 type = "critical"; 3286 }; 3287 }; 3288 }; 3289 3290 cpu0123-thermal { 3291 polling-delay-passive = <0>; 3292 polling-delay = <0>; 3293 thermal-sensors = <&tsens0 12>; 3294 3295 trips { 3296 cpu0123_alert0: trip-point0 { 3297 temperature = <90000>; 3298 hysteresis = <2000>; 3299 type = "passive"; 3300 }; 3301 3302 cpu0123_alert1: trip-point1 { 3303 temperature = <95000>; 3304 hysteresis = <2000>; 3305 type = "passive"; 3306 }; 3307 3308 cpu0123_crit: cpu-crit { 3309 temperature = <110000>; 3310 hysteresis = <1000>; 3311 type = "critical"; 3312 }; 3313 }; 3314 }; 3315 3316 modem0-thermal { 3317 polling-delay-passive = <0>; 3318 polling-delay = <0>; 3319 thermal-sensors = <&tsens0 13>; 3320 3321 trips { 3322 trip-point0 { 3323 temperature = <115000>; 3324 hysteresis = <5000>; 3325 type = "passive"; 3326 }; 3327 3328 trip-point1 { 3329 temperature = <125000>; 3330 hysteresis = <1000>; 3331 type = "passive"; 3332 }; 3333 }; 3334 }; 3335 3336 display-thermal { 3337 polling-delay-passive = <0>; 3338 polling-delay = <0>; 3339 thermal-sensors = <&tsens0 14>; 3340 3341 trips { 3342 trip-point0 { 3343 temperature = <115000>; 3344 hysteresis = <5000>; 3345 type = "passive"; 3346 }; 3347 3348 trip-point1 { 3349 temperature = <125000>; 3350 hysteresis = <1000>; 3351 type = "passive"; 3352 }; 3353 }; 3354 }; 3355 3356 gpu-thermal { 3357 polling-delay-passive = <0>; 3358 polling-delay = <0>; 3359 thermal-sensors = <&tsens0 15>; 3360 3361 cooling-maps { 3362 map0 { 3363 trip = <&gpu_alert0>; 3364 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3365 }; 3366 }; 3367 3368 trips { 3369 gpu_alert0: trip-point0 { 3370 temperature = <115000>; 3371 hysteresis = <5000>; 3372 type = "passive"; 3373 }; 3374 3375 trip-point1 { 3376 temperature = <125000>; 3377 hysteresis = <1000>; 3378 type = "critical"; 3379 }; 3380 }; 3381 }; 3382 }; 3383 3384 timer { 3385 compatible = "arm,armv8-timer"; 3386 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3387 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3388 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 3389 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 3390 }; 3391}; 3392