1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sm4450-gcc.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/soc/qcom,rpmh-rsc.h> 11 12/ { 13 interrupt-parent = <&intc>; 14 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 chosen { }; 19 20 clocks { 21 xo_board: xo-board { 22 compatible = "fixed-clock"; 23 clock-frequency = <76800000>; 24 #clock-cells = <0>; 25 }; 26 27 sleep_clk: sleep-clk { 28 compatible = "fixed-clock"; 29 clock-frequency = <32000>; 30 #clock-cells = <0>; 31 }; 32 33 bi_tcxo_div2: bi-tcxo-div2-clk { 34 #clock-cells = <0>; 35 compatible = "fixed-factor-clock"; 36 clocks = <&rpmhcc RPMH_CXO_CLK>; 37 clock-mult = <1>; 38 clock-div = <2>; 39 }; 40 }; 41 42 cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 CPU0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a55"; 49 reg = <0x0 0x0>; 50 clocks = <&cpufreq_hw 0>; 51 enable-method = "psci"; 52 next-level-cache = <&L2_0>; 53 power-domains = <&CPU_PD0>; 54 power-domain-names = "psci"; 55 qcom,freq-domain = <&cpufreq_hw 0>; 56 #cooling-cells = <2>; 57 58 L2_0: l2-cache { 59 compatible = "cache"; 60 cache-level = <2>; 61 cache-unified; 62 next-level-cache = <&L3_0>; 63 64 L3_0: l3-cache { 65 compatible = "cache"; 66 cache-level = <3>; 67 cache-unified; 68 }; 69 }; 70 }; 71 72 CPU1: cpu@100 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a55"; 75 reg = <0x0 0x100>; 76 clocks = <&cpufreq_hw 0>; 77 enable-method = "psci"; 78 next-level-cache = <&L2_100>; 79 power-domains = <&CPU_PD0>; 80 power-domain-names = "psci"; 81 qcom,freq-domain = <&cpufreq_hw 0>; 82 #cooling-cells = <2>; 83 84 L2_100: l2-cache { 85 compatible = "cache"; 86 cache-level = <2>; 87 cache-unified; 88 next-level-cache = <&L3_0>; 89 }; 90 }; 91 92 CPU2: cpu@200 { 93 device_type = "cpu"; 94 compatible = "arm,cortex-a55"; 95 reg = <0x0 0x200>; 96 clocks = <&cpufreq_hw 0>; 97 enable-method = "psci"; 98 next-level-cache = <&L2_200>; 99 power-domains = <&CPU_PD0>; 100 power-domain-names = "psci"; 101 qcom,freq-domain = <&cpufreq_hw 0>; 102 #cooling-cells = <2>; 103 104 L2_200: l2-cache { 105 compatible = "cache"; 106 cache-level = <2>; 107 cache-unified; 108 next-level-cache = <&L3_0>; 109 }; 110 }; 111 112 CPU3: cpu@300 { 113 device_type = "cpu"; 114 compatible = "arm,cortex-a55"; 115 reg = <0x0 0x300>; 116 clocks = <&cpufreq_hw 0>; 117 enable-method = "psci"; 118 next-level-cache = <&L2_300>; 119 power-domains = <&CPU_PD0>; 120 power-domain-names = "psci"; 121 qcom,freq-domain = <&cpufreq_hw 0>; 122 #cooling-cells = <2>; 123 124 L2_300: l2-cache { 125 compatible = "cache"; 126 cache-level = <2>; 127 cache-unified; 128 next-level-cache = <&L3_0>; 129 }; 130 }; 131 132 CPU4: cpu@400 { 133 device_type = "cpu"; 134 compatible = "arm,cortex-a55"; 135 reg = <0x0 0x400>; 136 clocks = <&cpufreq_hw 0>; 137 enable-method = "psci"; 138 next-level-cache = <&L2_400>; 139 power-domains = <&CPU_PD0>; 140 power-domain-names = "psci"; 141 qcom,freq-domain = <&cpufreq_hw 0>; 142 #cooling-cells = <2>; 143 144 L2_400: l2-cache { 145 compatible = "cache"; 146 cache-level = <2>; 147 cache-unified; 148 next-level-cache = <&L3_0>; 149 }; 150 }; 151 152 CPU5: cpu@500 { 153 device_type = "cpu"; 154 compatible = "arm,cortex-a55"; 155 reg = <0x0 0x500>; 156 clocks = <&cpufreq_hw 0>; 157 enable-method = "psci"; 158 next-level-cache = <&L2_500>; 159 power-domains = <&CPU_PD0>; 160 power-domain-names = "psci"; 161 qcom,freq-domain = <&cpufreq_hw 0>; 162 #cooling-cells = <2>; 163 164 L2_500: l2-cache { 165 compatible = "cache"; 166 cache-level = <2>; 167 cache-unified; 168 next-level-cache = <&L3_0>; 169 }; 170 }; 171 172 CPU6: cpu@600 { 173 device_type = "cpu"; 174 compatible = "arm,cortex-a78"; 175 reg = <0x0 0x600>; 176 clocks = <&cpufreq_hw 1>; 177 enable-method = "psci"; 178 next-level-cache = <&L2_600>; 179 power-domains = <&CPU_PD0>; 180 power-domain-names = "psci"; 181 qcom,freq-domain = <&cpufreq_hw 1>; 182 #cooling-cells = <2>; 183 184 L2_600: l2-cache { 185 compatible = "cache"; 186 cache-level = <2>; 187 cache-unified; 188 next-level-cache = <&L3_0>; 189 }; 190 }; 191 192 CPU7: cpu@700 { 193 device_type = "cpu"; 194 compatible = "arm,cortex-a78"; 195 reg = <0x0 0x700>; 196 clocks = <&cpufreq_hw 1>; 197 enable-method = "psci"; 198 next-level-cache = <&L2_700>; 199 power-domains = <&CPU_PD0>; 200 power-domain-names = "psci"; 201 qcom,freq-domain = <&cpufreq_hw 1>; 202 #cooling-cells = <2>; 203 204 L2_700: l2-cache { 205 compatible = "cache"; 206 cache-level = <2>; 207 cache-unified; 208 next-level-cache = <&L3_0>; 209 }; 210 }; 211 212 cpu-map { 213 cluster0 { 214 core0 { 215 cpu = <&CPU0>; 216 }; 217 218 core1 { 219 cpu = <&CPU1>; 220 }; 221 222 core2 { 223 cpu = <&CPU2>; 224 }; 225 226 core3 { 227 cpu = <&CPU3>; 228 }; 229 230 core4 { 231 cpu = <&CPU4>; 232 }; 233 234 core5 { 235 cpu = <&CPU5>; 236 }; 237 238 core6 { 239 cpu = <&CPU6>; 240 }; 241 242 core7 { 243 cpu = <&CPU7>; 244 }; 245 }; 246 }; 247 248 idle-states { 249 entry-method = "psci"; 250 251 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 252 compatible = "arm,idle-state"; 253 arm,psci-suspend-param = <0x40000004>; 254 entry-latency-us = <800>; 255 exit-latency-us = <750>; 256 min-residency-us = <4090>; 257 local-timer-stop; 258 }; 259 260 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 261 compatible = "arm,idle-state"; 262 arm,psci-suspend-param = <0x40000004>; 263 entry-latency-us = <600>; 264 exit-latency-us = <1550>; 265 min-residency-us = <4791>; 266 local-timer-stop; 267 }; 268 }; 269 270 domain-idle-states { 271 CLUSTER_SLEEP_0: cluster-sleep-0 { 272 compatible = "domain-idle-state"; 273 arm,psci-suspend-param = <0x41000044>; 274 entry-latency-us = <1050>; 275 exit-latency-us = <2500>; 276 min-residency-us = <5309>; 277 }; 278 279 CLUSTER_SLEEP_1: cluster-sleep-1 { 280 compatible = "domain-idle-state"; 281 arm,psci-suspend-param = <0x41003344>; 282 entry-latency-us = <1561>; 283 exit-latency-us = <2801>; 284 min-residency-us = <8550>; 285 }; 286 }; 287 }; 288 289 memory@a0000000 { 290 device_type = "memory"; 291 /* We expect the bootloader to fill in the size */ 292 reg = <0x0 0xa0000000 0x0 0x0>; 293 }; 294 295 pmu-a55 { 296 compatible = "arm,cortex-a55-pmu"; 297 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 298 }; 299 300 pmu-a78 { 301 compatible = "arm,cortex-a78-pmu"; 302 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 303 }; 304 305 psci { 306 compatible = "arm,psci-1.0"; 307 method = "smc"; 308 309 CPU_PD0: power-domain-cpu0 { 310 #power-domain-cells = <0>; 311 power-domains = <&CLUSTER_PD>; 312 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 313 }; 314 315 CPU_PD1: power-domain-cpu1 { 316 #power-domain-cells = <0>; 317 power-domains = <&CLUSTER_PD>; 318 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 319 }; 320 321 CPU_PD2: power-domain-cpu2 { 322 #power-domain-cells = <0>; 323 power-domains = <&CLUSTER_PD>; 324 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 325 }; 326 327 CPU_PD3: power-domain-cpu3 { 328 #power-domain-cells = <0>; 329 power-domains = <&CLUSTER_PD>; 330 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 331 }; 332 333 CPU_PD4: power-domain-cpu4 { 334 #power-domain-cells = <0>; 335 power-domains = <&CLUSTER_PD>; 336 domain-idle-states = <&BIG_CPU_SLEEP_0>; 337 }; 338 339 CPU_PD5: power-domain-cpu5 { 340 #power-domain-cells = <0>; 341 power-domains = <&CLUSTER_PD>; 342 domain-idle-states = <&BIG_CPU_SLEEP_0>; 343 }; 344 345 CPU_PD6: power-domain-cpu6 { 346 #power-domain-cells = <0>; 347 power-domains = <&CLUSTER_PD>; 348 domain-idle-states = <&BIG_CPU_SLEEP_0>; 349 }; 350 351 CPU_PD7: power-domain-cpu7 { 352 #power-domain-cells = <0>; 353 power-domains = <&CLUSTER_PD>; 354 domain-idle-states = <&BIG_CPU_SLEEP_0>; 355 }; 356 357 CLUSTER_PD: power-domain-cpu-cluster0 { 358 #power-domain-cells = <0>; 359 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>; 360 }; 361 }; 362 363 reserved_memory: reserved-memory { 364 #address-cells = <2>; 365 #size-cells = <2>; 366 ranges; 367 368 aop_cmd_db_mem: cmd-db@80860000 { 369 compatible = "qcom,cmd-db"; 370 reg = <0x0 0x80860000 0x0 0x20000>; 371 no-map; 372 }; 373 }; 374 375 soc: soc@0 { 376 #address-cells = <2>; 377 #size-cells = <2>; 378 ranges = <0 0 0 0 0x10 0>; 379 dma-ranges = <0 0 0 0 0x10 0>; 380 compatible = "simple-bus"; 381 382 gcc: clock-controller@100000 { 383 compatible = "qcom,sm4450-gcc"; 384 reg = <0x0 0x00100000 0x0 0x1f4200>; 385 #clock-cells = <1>; 386 #reset-cells = <1>; 387 #power-domain-cells = <1>; 388 clocks = <&rpmhcc RPMH_CXO_CLK>, 389 <&sleep_clk>, 390 <0>, 391 <0>, 392 <0>, 393 <0>; 394 }; 395 396 qupv3_id_0: geniqup@ac0000 { 397 compatible = "qcom,geni-se-qup"; 398 reg = <0x0 0x00ac0000 0x0 0x2000>; 399 ranges; 400 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 401 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 402 clock-names = "m-ahb", "s-ahb"; 403 #address-cells = <2>; 404 #size-cells = <2>; 405 status = "disabled"; 406 407 uart7: serial@a88000 { 408 compatible = "qcom,geni-debug-uart"; 409 reg = <0x0 0x00a88000 0x0 0x4000>; 410 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 411 clock-names = "se"; 412 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 413 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 414 pinctrl-names = "default"; 415 status = "disabled"; 416 }; 417 }; 418 419 tcsr_mutex: hwlock@1f40000 { 420 compatible = "qcom,tcsr-mutex"; 421 reg = <0x0 0x01f40000 0x0 0x40000>; 422 #hwlock-cells = <1>; 423 }; 424 425 pdc: interrupt-controller@b220000 { 426 compatible = "qcom,sm4450-pdc", "qcom,pdc"; 427 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 428 qcom,pdc-ranges = <0 480 94>, <94 494 31>, 429 <125 63 1>; 430 #interrupt-cells = <2>; 431 interrupt-parent = <&intc>; 432 interrupt-controller; 433 }; 434 435 tlmm: pinctrl@f100000 { 436 compatible = "qcom,sm4450-tlmm"; 437 reg = <0x0 0x0f100000 0x0 0x300000>; 438 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 439 gpio-controller; 440 #gpio-cells = <2>; 441 interrupt-controller; 442 #interrupt-cells = <2>; 443 gpio-ranges = <&tlmm 0 0 137>; 444 wakeup-parent = <&pdc>; 445 446 qup_uart7_rx: qup-uart7-rx-state { 447 pins = "gpio23"; 448 function = "qup1_se2_l2"; 449 drive-strength = <2>; 450 bias-disable; 451 }; 452 453 qup_uart7_tx: qup-uart7-tx-state { 454 pins = "gpio22"; 455 function = "qup1_se2_l2"; 456 drive-strength = <2>; 457 bias-disable; 458 }; 459 }; 460 461 intc: interrupt-controller@17200000 { 462 compatible = "arm,gic-v3"; 463 reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */ 464 <0x0 0x17260000 0x0 0x100000>; /* GICR * 8 */ 465 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 466 #interrupt-cells = <3>; 467 interrupt-controller; 468 #redistributor-regions = <1>; 469 redistributor-stride = <0x0 0x20000>; 470 }; 471 472 timer@17420000 { 473 compatible = "arm,armv7-timer-mem"; 474 reg = <0x0 0x17420000 0x0 0x1000>; 475 ranges = <0 0 0 0x20000000>; 476 #address-cells = <1>; 477 #size-cells = <1>; 478 479 frame@17421000 { 480 reg = <0x17421000 0x1000>, 481 <0x17422000 0x1000>; 482 frame-number = <0>; 483 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 485 }; 486 487 frame@17423000 { 488 reg = <0x17423000 0x1000>; 489 frame-number = <1>; 490 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 491 status = "disabled"; 492 }; 493 494 frame@17425000 { 495 reg = <0x17425000 0x1000>; 496 frame-number = <2>; 497 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 498 status = "disabled"; 499 }; 500 501 frame@17427000 { 502 reg = <0x17427000 0x1000>; 503 frame-number = <3>; 504 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 505 status = "disabled"; 506 }; 507 508 frame@17429000 { 509 reg = <0x17429000 0x1000>; 510 frame-number = <4>; 511 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 512 status = "disabled"; 513 }; 514 515 frame@1742b000 { 516 reg = <0x1742b000 0x1000>; 517 frame-number = <5>; 518 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 519 status = "disabled"; 520 }; 521 522 frame@1742d000 { 523 reg = <0x1742d000 0x1000>; 524 frame-number = <6>; 525 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 526 status = "disabled"; 527 }; 528 }; 529 530 apps_rsc: rsc@17a00000 { 531 compatible = "qcom,rpmh-rsc"; 532 reg = <0x0 0x17a00000 0x0 0x10000>, 533 <0x0 0x17a10000 0x0 0x10000>, 534 <0x0 0x17a20000 0x0 0x10000>; 535 reg-names = "drv-0", "drv-1", "drv-2"; 536 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 539 label = "apps_rsc"; 540 qcom,tcs-offset = <0xd00>; 541 qcom,drv-id = <2>; 542 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 543 <WAKE_TCS 3>, <CONTROL_TCS 0>; 544 power-domains = <&CLUSTER_PD>; 545 546 apps_bcm_voter: bcm-voter { 547 compatible = "qcom,bcm-voter"; 548 }; 549 550 rpmhcc: clock-controller { 551 compatible = "qcom,sm4450-rpmh-clk"; 552 #clock-cells = <1>; 553 clocks = <&xo_board>; 554 clock-names = "xo"; 555 }; 556 }; 557 558 cpufreq_hw: cpufreq@17d91000 { 559 compatible = "qcom,sm4450-cpufreq-epss", "qcom,cpufreq-epss"; 560 reg = <0 0x17d91000 0 0x1000>, 561 <0 0x17d92000 0 0x1000>; 562 reg-names = "freq-domain0", "freq-domain1"; 563 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 564 clock-names = "xo", "alternate"; 565 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 567 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; 568 #freq-domain-cells = <1>; 569 #clock-cells = <1>; 570 }; 571 }; 572 573 timer { 574 compatible = "arm,armv8-timer"; 575 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 576 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 577 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 578 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 579 }; 580}; 581