1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2018, Craig Tatlor. 4 * Copyright (c) 2020, Alexey Minnekhanov <alexey.min@gmail.com> 5 * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com> 6 * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com> 7 * Copyright (c) 2020, Martin Botka <martin.botka1@gmail.com> 8 */ 9 10#include "sdm630.dtsi" 11 12/delete-node/ &buffer_mem; 13 14/ { 15 smp2p-cdsp { 16 compatible = "qcom,smp2p"; 17 qcom,smem = <94>, <432>; 18 interrupts = <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>; 19 mboxes = <&apcs_glb 30>; 20 qcom,local-pid = <0>; 21 qcom,remote-pid = <5>; 22 23 cdsp_smp2p_out: master-kernel { 24 qcom,entry-name = "master-kernel"; 25 #qcom,smem-state-cells = <1>; 26 }; 27 28 cdsp_smp2p_in: slave-kernel { 29 qcom,entry-name = "slave-kernel"; 30 interrupt-controller; 31 #interrupt-cells = <2>; 32 }; 33 }; 34 35 reserved-memory { 36 cdsp_region: cdsp@94a00000 { 37 reg = <0x0 0x94a00000 0x00 0x600000>; 38 no-map; 39 }; 40 }; 41}; 42 43&adreno_gpu { 44 compatible = "qcom,adreno-512.0", "qcom,adreno"; 45 operating-points-v2 = <&gpu_sdm660_opp_table>; 46 47 gpu_sdm660_opp_table: opp-table { 48 compatible = "operating-points-v2"; 49 50 /* 51 * 775MHz is only available on the highest speed bin 52 * Though it cannot be used for now due to interconnect 53 * framework not supporting multiple frequencies 54 * at the same opp-level 55 56 opp-750000000 { 57 opp-hz = /bits/ 64 <750000000>; 58 opp-level = <RPM_SMD_LEVEL_TURBO>; 59 opp-peak-kBps = <5412000>; 60 opp-supported-hw = <0xCHECKME>; 61 }; 62 63 * These OPPs are correct, but we are lacking support for the 64 * GPU regulator. Hence, disable them for now to prevent the 65 * platform from hanging on high graphics loads. 66 67 opp-700000000 { 68 opp-hz = /bits/ 64 <700000000>; 69 opp-level = <RPM_SMD_LEVEL_TURBO>; 70 opp-peak-kBps = <5184000>; 71 opp-supported-hw = <0xff>; 72 }; 73 74 opp-647000000 { 75 opp-hz = /bits/ 64 <647000000>; 76 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 77 opp-peak-kBps = <4068000>; 78 opp-supported-hw = <0xff>; 79 }; 80 81 opp-588000000 { 82 opp-hz = /bits/ 64 <588000000>; 83 opp-level = <RPM_SMD_LEVEL_NOM>; 84 opp-peak-kBps = <3072000>; 85 opp-supported-hw = <0xff>; 86 }; 87 88 opp-465000000 { 89 opp-hz = /bits/ 64 <465000000>; 90 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 91 opp-peak-kBps = <2724000>; 92 opp-supported-hw = <0xff>; 93 }; 94 95 opp-370000000 { 96 opp-hz = /bits/ 64 <370000000>; 97 opp-level = <RPM_SMD_LEVEL_SVS>; 98 opp-peak-kBps = <2188000>; 99 opp-supported-hw = <0xff>; 100 }; 101 */ 102 103 opp-266000000 { 104 opp-hz = /bits/ 64 <266000000>; 105 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 106 opp-peak-kBps = <1648000>; 107 opp-supported-hw = <0xff>; 108 }; 109 110 opp-160000000 { 111 opp-hz = /bits/ 64 <160000000>; 112 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 113 opp-peak-kBps = <1200000>; 114 opp-supported-hw = <0xff>; 115 }; 116 }; 117}; 118 119&cpu0 { 120 compatible = "qcom,kryo260"; 121 capacity-dmips-mhz = <1024>; 122 /delete-property/ operating-points-v2; 123}; 124 125&cpu1 { 126 compatible = "qcom,kryo260"; 127 capacity-dmips-mhz = <1024>; 128 /delete-property/ operating-points-v2; 129}; 130 131&cpu2 { 132 compatible = "qcom,kryo260"; 133 capacity-dmips-mhz = <1024>; 134 /delete-property/ operating-points-v2; 135}; 136 137&cpu3 { 138 compatible = "qcom,kryo260"; 139 capacity-dmips-mhz = <1024>; 140 /delete-property/ operating-points-v2; 141}; 142 143&cpu4 { 144 compatible = "qcom,kryo260"; 145 capacity-dmips-mhz = <640>; 146 /delete-property/ operating-points-v2; 147}; 148 149&cpu5 { 150 compatible = "qcom,kryo260"; 151 capacity-dmips-mhz = <640>; 152 /delete-property/ operating-points-v2; 153}; 154 155&cpu6 { 156 compatible = "qcom,kryo260"; 157 capacity-dmips-mhz = <640>; 158 /delete-property/ operating-points-v2; 159}; 160 161&cpu7 { 162 compatible = "qcom,kryo260"; 163 capacity-dmips-mhz = <640>; 164 /delete-property/ operating-points-v2; 165}; 166 167&gcc { 168 compatible = "qcom,gcc-sdm660"; 169}; 170 171&gpucc { 172 compatible = "qcom,gpucc-sdm660"; 173}; 174 175&mdp { 176 compatible = "qcom,sdm660-mdp5", "qcom,mdp5"; 177 178 ports { 179 port@1 { 180 reg = <1>; 181 mdp5_intf2_out: endpoint { 182 remote-endpoint = <&mdss_dsi1_in>; 183 }; 184 }; 185 }; 186}; 187 188&mdss { 189 mdss_dsi1: dsi@c996000 { 190 compatible = "qcom,sdm660-dsi-ctrl", 191 "qcom,mdss-dsi-ctrl"; 192 reg = <0x0c996000 0x400>; 193 reg-names = "dsi_ctrl"; 194 195 /* DSI1 shares the OPP table with DSI0 */ 196 operating-points-v2 = <&dsi_opp_table>; 197 power-domains = <&rpmpd RPMPD_VDDCX>; 198 199 interrupt-parent = <&mdss>; 200 interrupts = <5>; 201 202 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, 203 <&mmcc PCLK1_CLK_SRC>; 204 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 205 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 206 207 clocks = <&mmcc MDSS_MDP_CLK>, 208 <&mmcc MDSS_BYTE1_CLK>, 209 <&mmcc MDSS_BYTE1_INTF_CLK>, 210 <&mmcc MNOC_AHB_CLK>, 211 <&mmcc MDSS_AHB_CLK>, 212 <&mmcc MDSS_AXI_CLK>, 213 <&mmcc MISC_AHB_CLK>, 214 <&mmcc MDSS_PCLK1_CLK>, 215 <&mmcc MDSS_ESC1_CLK>; 216 clock-names = "mdp_core", 217 "byte", 218 "byte_intf", 219 "mnoc", 220 "iface", 221 "bus", 222 "core_mmss", 223 "pixel", 224 "core"; 225 226 phys = <&mdss_dsi1_phy>; 227 228 status = "disabled"; 229 230 ports { 231 #address-cells = <1>; 232 #size-cells = <0>; 233 234 port@0 { 235 reg = <0>; 236 mdss_dsi1_in: endpoint { 237 remote-endpoint = <&mdp5_intf2_out>; 238 }; 239 }; 240 241 port@1 { 242 reg = <1>; 243 mdss_dsi1_out: endpoint { 244 }; 245 }; 246 }; 247 }; 248 249 mdss_dsi1_phy: phy@c996400 { 250 compatible = "qcom,dsi-phy-14nm-660"; 251 reg = <0x0c996400 0x100>, 252 <0x0c996500 0x300>, 253 <0x0c996800 0x188>; 254 reg-names = "dsi_phy", 255 "dsi_phy_lane", 256 "dsi_pll"; 257 258 #clock-cells = <1>; 259 #phy-cells = <0>; 260 261 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 262 clock-names = "iface", "ref"; 263 status = "disabled"; 264 }; 265}; 266 267&mmcc { 268 compatible = "qcom,mmcc-sdm660"; 269 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 270 <&sleep_clk>, 271 <&gcc GCC_MMSS_GPLL0_CLK>, 272 <&gcc GCC_MMSS_GPLL0_DIV_CLK>, 273 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 274 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 275 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 276 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 277 <0>, 278 <0>; 279}; 280 281&soc { 282 cdsp_smmu: iommu@5180000 { 283 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 284 reg = <0x5180000 0x40000>; 285 #iommu-cells = <1>; 286 287 #global-interrupts = <2>; 288 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 537 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>; 307 308 clocks = <&gcc GCC_HLOS1_VOTE_TURING_ADSP_SMMU_CLK>; 309 clock-names = "bus"; 310 311 power-domains = <&gcc HLOS1_VOTE_TURING_ADSP_GDSC>; 312 313 }; 314 315 remoteproc_cdsp: remoteproc@1a300000 { 316 compatible = "qcom,sdm660-cdsp-pas"; 317 reg = <0x1a300000 0x00100>; 318 interrupts-extended = <&intc GIC_SPI 518 IRQ_TYPE_EDGE_RISING>, 319 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 320 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 321 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 322 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 323 interrupt-names = "wdog", 324 "fatal", 325 "ready", 326 "handover", 327 "stop-ack"; 328 329 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 330 clock-names = "xo"; 331 332 memory-region = <&cdsp_region>; 333 power-domains = <&rpmpd SDM660_VDDCX>; 334 power-domain-names = "cx"; 335 336 qcom,smem-states = <&cdsp_smp2p_out 0>; 337 qcom,smem-state-names = "stop"; 338 339 glink-edge { 340 interrupts = <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>; 341 342 label = "cdsp"; 343 mboxes = <&apcs_glb 29>; 344 qcom,remote-pid = <5>; 345 346 fastrpc { 347 compatible = "qcom,fastrpc"; 348 qcom,glink-channels = "fastrpcglink-apps-dsp"; 349 label = "cdsp"; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 353 compute-cb@5 { 354 compatible = "qcom,fastrpc-compute-cb"; 355 reg = <5>; 356 iommus = <&cdsp_smmu 3>; 357 }; 358 359 compute-cb@6 { 360 compatible = "qcom,fastrpc-compute-cb"; 361 reg = <6>; 362 iommus = <&cdsp_smmu 4>; 363 }; 364 365 compute-cb@7 { 366 compatible = "qcom,fastrpc-compute-cb"; 367 reg = <7>; 368 iommus = <&cdsp_smmu 5>; 369 }; 370 371 compute-cb@8 { 372 compatible = "qcom,fastrpc-compute-cb"; 373 reg = <8>; 374 iommus = <&cdsp_smmu 6>; 375 }; 376 377 compute-cb@9 { 378 compatible = "qcom,fastrpc-compute-cb"; 379 reg = <9>; 380 iommus = <&cdsp_smmu 7>; 381 }; 382 383 compute-cb@10 { 384 compatible = "qcom,fastrpc-compute-cb"; 385 reg = <10>; 386 iommus = <&cdsp_smmu 8>; 387 }; 388 389 compute-cb@11 { 390 compatible = "qcom,fastrpc-compute-cb"; 391 reg = <11>; 392 iommus = <&cdsp_smmu 9>; 393 }; 394 395 compute-cb@12 { 396 compatible = "qcom,fastrpc-compute-cb"; 397 reg = <12>; 398 iommus = <&cdsp_smmu 10>; 399 }; 400 401 compute-cb@13 { 402 compatible = "qcom,fastrpc-compute-cb"; 403 reg = <13>; 404 iommus = <&cdsp_smmu 11>; 405 }; 406 }; 407 }; 408 }; 409}; 410 411&tlmm { 412 compatible = "qcom,sdm660-pinctrl"; 413}; 414 415&tsens { 416 #qcom,sensors = <14>; 417}; 418