1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com> 4 * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com> 5 */ 6 7#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 8#include <dt-bindings/clock/qcom,gcc-sdm660.h> 9#include <dt-bindings/clock/qcom,gpucc-sdm660.h> 10#include <dt-bindings/clock/qcom,mmcc-sdm660.h> 11#include <dt-bindings/clock/qcom,rpmcc.h> 12#include <dt-bindings/firmware/qcom,scm.h> 13#include <dt-bindings/interconnect/qcom,sdm660.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/thermal/thermal.h> 18#include <dt-bindings/soc/qcom,apr.h> 19 20/ { 21 interrupt-parent = <&intc>; 22 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 aliases { 27 mmc1 = &sdhc_1; 28 mmc2 = &sdhc_2; 29 }; 30 31 chosen { }; 32 33 clocks { 34 xo_board: xo-board { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <19200000>; 38 clock-output-names = "xo_board"; 39 }; 40 41 sleep_clk: sleep-clk { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-frequency = <32764>; 45 clock-output-names = "sleep_clk"; 46 }; 47 }; 48 49 cpus { 50 #address-cells = <2>; 51 #size-cells = <0>; 52 53 cpu0: cpu@100 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a53"; 56 reg = <0x0 0x100>; 57 enable-method = "psci"; 58 cpu-idle-states = <&perf_cpu_sleep_0 59 &perf_cpu_sleep_1 60 &perf_cluster_sleep_0 61 &perf_cluster_sleep_1 62 &perf_cluster_sleep_2>; 63 capacity-dmips-mhz = <1126>; 64 #cooling-cells = <2>; 65 next-level-cache = <&l2_1>; 66 l2_1: l2-cache { 67 compatible = "cache"; 68 cache-level = <2>; 69 cache-unified; 70 }; 71 }; 72 73 cpu1: cpu@101 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a53"; 76 reg = <0x0 0x101>; 77 enable-method = "psci"; 78 cpu-idle-states = <&perf_cpu_sleep_0 79 &perf_cpu_sleep_1 80 &perf_cluster_sleep_0 81 &perf_cluster_sleep_1 82 &perf_cluster_sleep_2>; 83 capacity-dmips-mhz = <1126>; 84 #cooling-cells = <2>; 85 next-level-cache = <&l2_1>; 86 }; 87 88 cpu2: cpu@102 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a53"; 91 reg = <0x0 0x102>; 92 enable-method = "psci"; 93 cpu-idle-states = <&perf_cpu_sleep_0 94 &perf_cpu_sleep_1 95 &perf_cluster_sleep_0 96 &perf_cluster_sleep_1 97 &perf_cluster_sleep_2>; 98 capacity-dmips-mhz = <1126>; 99 #cooling-cells = <2>; 100 next-level-cache = <&l2_1>; 101 }; 102 103 cpu3: cpu@103 { 104 device_type = "cpu"; 105 compatible = "arm,cortex-a53"; 106 reg = <0x0 0x103>; 107 enable-method = "psci"; 108 cpu-idle-states = <&perf_cpu_sleep_0 109 &perf_cpu_sleep_1 110 &perf_cluster_sleep_0 111 &perf_cluster_sleep_1 112 &perf_cluster_sleep_2>; 113 capacity-dmips-mhz = <1126>; 114 #cooling-cells = <2>; 115 next-level-cache = <&l2_1>; 116 }; 117 118 cpu4: cpu@0 { 119 device_type = "cpu"; 120 compatible = "arm,cortex-a53"; 121 reg = <0x0 0x0>; 122 enable-method = "psci"; 123 cpu-idle-states = <&pwr_cpu_sleep_0 124 &pwr_cpu_sleep_1 125 &pwr_cluster_sleep_0 126 &pwr_cluster_sleep_1 127 &pwr_cluster_sleep_2>; 128 capacity-dmips-mhz = <1024>; 129 #cooling-cells = <2>; 130 next-level-cache = <&l2_0>; 131 l2_0: l2-cache { 132 compatible = "cache"; 133 cache-level = <2>; 134 cache-unified; 135 }; 136 }; 137 138 cpu5: cpu@1 { 139 device_type = "cpu"; 140 compatible = "arm,cortex-a53"; 141 reg = <0x0 0x1>; 142 enable-method = "psci"; 143 cpu-idle-states = <&pwr_cpu_sleep_0 144 &pwr_cpu_sleep_1 145 &pwr_cluster_sleep_0 146 &pwr_cluster_sleep_1 147 &pwr_cluster_sleep_2>; 148 capacity-dmips-mhz = <1024>; 149 #cooling-cells = <2>; 150 next-level-cache = <&l2_0>; 151 }; 152 153 cpu6: cpu@2 { 154 device_type = "cpu"; 155 compatible = "arm,cortex-a53"; 156 reg = <0x0 0x2>; 157 enable-method = "psci"; 158 cpu-idle-states = <&pwr_cpu_sleep_0 159 &pwr_cpu_sleep_1 160 &pwr_cluster_sleep_0 161 &pwr_cluster_sleep_1 162 &pwr_cluster_sleep_2>; 163 capacity-dmips-mhz = <1024>; 164 #cooling-cells = <2>; 165 next-level-cache = <&l2_0>; 166 }; 167 168 cpu7: cpu@3 { 169 device_type = "cpu"; 170 compatible = "arm,cortex-a53"; 171 reg = <0x0 0x3>; 172 enable-method = "psci"; 173 cpu-idle-states = <&pwr_cpu_sleep_0 174 &pwr_cpu_sleep_1 175 &pwr_cluster_sleep_0 176 &pwr_cluster_sleep_1 177 &pwr_cluster_sleep_2>; 178 capacity-dmips-mhz = <1024>; 179 #cooling-cells = <2>; 180 next-level-cache = <&l2_0>; 181 }; 182 183 cpu-map { 184 cluster0 { 185 core0 { 186 cpu = <&cpu4>; 187 }; 188 189 core1 { 190 cpu = <&cpu5>; 191 }; 192 193 core2 { 194 cpu = <&cpu6>; 195 }; 196 197 core3 { 198 cpu = <&cpu7>; 199 }; 200 }; 201 202 cluster1 { 203 core0 { 204 cpu = <&cpu0>; 205 }; 206 207 core1 { 208 cpu = <&cpu1>; 209 }; 210 211 core2 { 212 cpu = <&cpu2>; 213 }; 214 215 core3 { 216 cpu = <&cpu3>; 217 }; 218 }; 219 }; 220 221 idle-states { 222 entry-method = "psci"; 223 224 pwr_cpu_sleep_0: cpu-sleep-0-0 { 225 compatible = "arm,idle-state"; 226 idle-state-name = "pwr-retention"; 227 arm,psci-suspend-param = <0x40000002>; 228 entry-latency-us = <338>; 229 exit-latency-us = <423>; 230 min-residency-us = <200>; 231 }; 232 233 pwr_cpu_sleep_1: cpu-sleep-0-1 { 234 compatible = "arm,idle-state"; 235 idle-state-name = "pwr-power-collapse"; 236 arm,psci-suspend-param = <0x40000003>; 237 entry-latency-us = <515>; 238 exit-latency-us = <1821>; 239 min-residency-us = <1000>; 240 local-timer-stop; 241 }; 242 243 perf_cpu_sleep_0: cpu-sleep-1-0 { 244 compatible = "arm,idle-state"; 245 idle-state-name = "perf-retention"; 246 arm,psci-suspend-param = <0x40000002>; 247 entry-latency-us = <154>; 248 exit-latency-us = <87>; 249 min-residency-us = <200>; 250 }; 251 252 perf_cpu_sleep_1: cpu-sleep-1-1 { 253 compatible = "arm,idle-state"; 254 idle-state-name = "perf-power-collapse"; 255 arm,psci-suspend-param = <0x40000003>; 256 entry-latency-us = <262>; 257 exit-latency-us = <301>; 258 min-residency-us = <1000>; 259 local-timer-stop; 260 }; 261 262 pwr_cluster_sleep_0: cluster-sleep-0-0 { 263 compatible = "arm,idle-state"; 264 idle-state-name = "pwr-cluster-dynamic-retention"; 265 arm,psci-suspend-param = <0x400000f2>; 266 entry-latency-us = <284>; 267 exit-latency-us = <384>; 268 min-residency-us = <9987>; 269 local-timer-stop; 270 }; 271 272 pwr_cluster_sleep_1: cluster-sleep-0-1 { 273 compatible = "arm,idle-state"; 274 idle-state-name = "pwr-cluster-retention"; 275 arm,psci-suspend-param = <0x400000f3>; 276 entry-latency-us = <338>; 277 exit-latency-us = <423>; 278 min-residency-us = <9987>; 279 local-timer-stop; 280 }; 281 282 pwr_cluster_sleep_2: cluster-sleep-0-2 { 283 compatible = "arm,idle-state"; 284 idle-state-name = "pwr-cluster-retention"; 285 arm,psci-suspend-param = <0x400000f4>; 286 entry-latency-us = <515>; 287 exit-latency-us = <1821>; 288 min-residency-us = <9987>; 289 local-timer-stop; 290 }; 291 292 perf_cluster_sleep_0: cluster-sleep-1-0 { 293 compatible = "arm,idle-state"; 294 idle-state-name = "perf-cluster-dynamic-retention"; 295 arm,psci-suspend-param = <0x400000f2>; 296 entry-latency-us = <272>; 297 exit-latency-us = <329>; 298 min-residency-us = <9987>; 299 local-timer-stop; 300 }; 301 302 perf_cluster_sleep_1: cluster-sleep-1-1 { 303 compatible = "arm,idle-state"; 304 idle-state-name = "perf-cluster-retention"; 305 arm,psci-suspend-param = <0x400000f3>; 306 entry-latency-us = <332>; 307 exit-latency-us = <368>; 308 min-residency-us = <9987>; 309 local-timer-stop; 310 }; 311 312 perf_cluster_sleep_2: cluster-sleep-1-2 { 313 compatible = "arm,idle-state"; 314 idle-state-name = "perf-cluster-retention"; 315 arm,psci-suspend-param = <0x400000f4>; 316 entry-latency-us = <545>; 317 exit-latency-us = <1609>; 318 min-residency-us = <9987>; 319 local-timer-stop; 320 }; 321 }; 322 }; 323 324 firmware { 325 scm { 326 compatible = "qcom,scm-msm8998", "qcom,scm"; 327 }; 328 }; 329 330 memory@80000000 { 331 device_type = "memory"; 332 /* We expect the bootloader to fill in the reg */ 333 reg = <0x0 0x80000000 0x0 0x0>; 334 }; 335 336 dsi_opp_table: opp-table-dsi { 337 compatible = "operating-points-v2"; 338 339 opp-131250000 { 340 opp-hz = /bits/ 64 <131250000>; 341 required-opps = <&rpmpd_opp_svs>; 342 }; 343 344 opp-210000000 { 345 opp-hz = /bits/ 64 <210000000>; 346 required-opps = <&rpmpd_opp_svs_plus>; 347 }; 348 349 opp-262500000 { 350 opp-hz = /bits/ 64 <262500000>; 351 required-opps = <&rpmpd_opp_nom>; 352 }; 353 }; 354 355 pmu { 356 compatible = "arm,armv8-pmuv3"; 357 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 358 }; 359 360 psci { 361 compatible = "arm,psci-1.0"; 362 method = "smc"; 363 }; 364 365 rpm: remoteproc { 366 compatible = "qcom,sdm660-rpm-proc", "qcom,rpm-proc"; 367 368 glink-edge { 369 compatible = "qcom,glink-rpm"; 370 371 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 372 qcom,rpm-msg-ram = <&rpm_msg_ram>; 373 mboxes = <&apcs_glb 0>; 374 375 rpm_requests: rpm-requests { 376 compatible = "qcom,rpm-sdm660", "qcom,glink-smd-rpm"; 377 qcom,glink-channels = "rpm_requests"; 378 379 rpmcc: clock-controller { 380 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc"; 381 #clock-cells = <1>; 382 }; 383 384 rpmpd: power-controller { 385 compatible = "qcom,sdm660-rpmpd"; 386 #power-domain-cells = <1>; 387 operating-points-v2 = <&rpmpd_opp_table>; 388 389 rpmpd_opp_table: opp-table { 390 compatible = "operating-points-v2"; 391 392 rpmpd_opp_ret: opp1 { 393 opp-level = <RPM_SMD_LEVEL_RETENTION>; 394 }; 395 396 rpmpd_opp_ret_plus: opp2 { 397 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 398 }; 399 400 rpmpd_opp_min_svs: opp3 { 401 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 402 }; 403 404 rpmpd_opp_low_svs: opp4 { 405 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 406 }; 407 408 rpmpd_opp_svs: opp5 { 409 opp-level = <RPM_SMD_LEVEL_SVS>; 410 }; 411 412 rpmpd_opp_svs_plus: opp6 { 413 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 414 }; 415 416 rpmpd_opp_nom: opp7 { 417 opp-level = <RPM_SMD_LEVEL_NOM>; 418 }; 419 420 rpmpd_opp_nom_plus: opp8 { 421 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 422 }; 423 424 rpmpd_opp_turbo: opp9 { 425 opp-level = <RPM_SMD_LEVEL_TURBO>; 426 }; 427 }; 428 }; 429 }; 430 }; 431 }; 432 433 reserved-memory { 434 #address-cells = <2>; 435 #size-cells = <2>; 436 ranges; 437 438 wlan_msa_guard: wlan-msa-guard@85600000 { 439 reg = <0x0 0x85600000 0x0 0x100000>; 440 no-map; 441 }; 442 443 wlan_msa_mem: wlan-msa-mem@85700000 { 444 reg = <0x0 0x85700000 0x0 0x100000>; 445 no-map; 446 }; 447 448 qhee_code: qhee-code@85800000 { 449 reg = <0x0 0x85800000 0x0 0x600000>; 450 no-map; 451 }; 452 453 rmtfs_mem: memory@85e00000 { 454 compatible = "qcom,rmtfs-mem"; 455 reg = <0x0 0x85e00000 0x0 0x200000>; 456 no-map; 457 458 qcom,client-id = <1>; 459 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 460 }; 461 462 smem_region: smem-mem@86000000 { 463 reg = <0 0x86000000 0 0x200000>; 464 no-map; 465 }; 466 467 tz_mem: memory@86200000 { 468 reg = <0x0 0x86200000 0x0 0x3300000>; 469 no-map; 470 }; 471 472 mpss_region: mpss@8ac00000 { 473 reg = <0x0 0x8ac00000 0x0 0x7e00000>; 474 no-map; 475 }; 476 477 adsp_region: adsp@92a00000 { 478 reg = <0x0 0x92a00000 0x0 0x1e00000>; 479 no-map; 480 }; 481 482 mba_region: mba@94800000 { 483 reg = <0x0 0x94800000 0x0 0x200000>; 484 no-map; 485 }; 486 487 buffer_mem: tzbuffer@94a00000 { 488 reg = <0x0 0x94a00000 0x0 0x100000>; 489 no-map; 490 }; 491 492 venus_region: venus@9f800000 { 493 reg = <0x0 0x9f800000 0x0 0x800000>; 494 no-map; 495 }; 496 497 adsp_mem: adsp-region@f6000000 { 498 reg = <0x0 0xf6000000 0x0 0x800000>; 499 no-map; 500 }; 501 502 qseecom_mem: qseecom-region@f6800000 { 503 reg = <0x0 0xf6800000 0x0 0x1400000>; 504 no-map; 505 }; 506 507 zap_shader_region: gpu@fed00000 { 508 compatible = "shared-dma-pool"; 509 reg = <0x0 0xfed00000 0x0 0xa00000>; 510 no-map; 511 }; 512 513 mdata_mem: mpss-metadata { 514 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; 515 size = <0x0 0x4000>; 516 no-map; 517 }; 518 }; 519 520 smem: smem { 521 compatible = "qcom,smem"; 522 memory-region = <&smem_region>; 523 hwlocks = <&tcsr_mutex 3>; 524 }; 525 526 smp2p-adsp { 527 compatible = "qcom,smp2p"; 528 qcom,smem = <443>, <429>; 529 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 530 mboxes = <&apcs_glb 10>; 531 qcom,local-pid = <0>; 532 qcom,remote-pid = <2>; 533 534 adsp_smp2p_out: master-kernel { 535 qcom,entry-name = "master-kernel"; 536 #qcom,smem-state-cells = <1>; 537 }; 538 539 adsp_smp2p_in: slave-kernel { 540 qcom,entry-name = "slave-kernel"; 541 interrupt-controller; 542 #interrupt-cells = <2>; 543 }; 544 }; 545 546 smp2p-mpss { 547 compatible = "qcom,smp2p"; 548 qcom,smem = <435>, <428>; 549 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 550 mboxes = <&apcs_glb 14>; 551 qcom,local-pid = <0>; 552 qcom,remote-pid = <1>; 553 554 modem_smp2p_out: master-kernel { 555 qcom,entry-name = "master-kernel"; 556 #qcom,smem-state-cells = <1>; 557 }; 558 559 modem_smp2p_in: slave-kernel { 560 qcom,entry-name = "slave-kernel"; 561 interrupt-controller; 562 #interrupt-cells = <2>; 563 }; 564 }; 565 566 soc: soc@0 { 567 #address-cells = <1>; 568 #size-cells = <1>; 569 ranges = <0 0 0 0xffffffff>; 570 compatible = "simple-bus"; 571 572 gcc: clock-controller@100000 { 573 compatible = "qcom,gcc-sdm630"; 574 #clock-cells = <1>; 575 #reset-cells = <1>; 576 #power-domain-cells = <1>; 577 reg = <0x00100000 0x94000>; 578 579 clock-names = "xo", "sleep_clk"; 580 clocks = <&xo_board>, 581 <&sleep_clk>; 582 }; 583 584 rpm_msg_ram: sram@778000 { 585 compatible = "qcom,rpm-msg-ram"; 586 reg = <0x00778000 0x7000>; 587 }; 588 589 qfprom: qfprom@780000 { 590 compatible = "qcom,sdm630-qfprom", "qcom,qfprom"; 591 reg = <0x00780000 0x621c>; 592 #address-cells = <1>; 593 #size-cells = <1>; 594 595 qusb2_hstx_trim: hstx-trim@240 { 596 reg = <0x243 0x1>; 597 bits = <1 3>; 598 }; 599 600 gpu_speed_bin: gpu-speed-bin@41a0 { 601 reg = <0x41a2 0x2>; 602 bits = <5 8>; 603 }; 604 }; 605 606 rng: rng@793000 { 607 compatible = "qcom,prng-ee"; 608 reg = <0x00793000 0x1000>; 609 clocks = <&gcc GCC_PRNG_AHB_CLK>; 610 clock-names = "core"; 611 }; 612 613 bimc: interconnect@1008000 { 614 compatible = "qcom,sdm660-bimc"; 615 reg = <0x01008000 0x78000>; 616 #interconnect-cells = <1>; 617 }; 618 619 restart@10ac000 { 620 compatible = "qcom,pshold"; 621 reg = <0x010ac000 0x4>; 622 }; 623 624 cnoc: interconnect@1500000 { 625 compatible = "qcom,sdm660-cnoc"; 626 reg = <0x01500000 0x10000>; 627 #interconnect-cells = <1>; 628 }; 629 630 snoc: interconnect@1626000 { 631 compatible = "qcom,sdm660-snoc"; 632 reg = <0x01626000 0x7090>; 633 #interconnect-cells = <1>; 634 }; 635 636 anoc2_smmu: iommu@16c0000 { 637 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 638 reg = <0x016c0000 0x40000>; 639 #global-interrupts = <2>; 640 #iommu-cells = <1>; 641 642 interrupts = 643 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 645 646 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 374 IRQ_TYPE_LEVEL_LOW>, 648 <GIC_SPI 375 IRQ_TYPE_LEVEL_LOW>, 649 <GIC_SPI 376 IRQ_TYPE_LEVEL_LOW>, 650 <GIC_SPI 377 IRQ_TYPE_LEVEL_LOW>, 651 <GIC_SPI 378 IRQ_TYPE_LEVEL_LOW>, 652 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 657 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 664 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 672 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 674 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 675 }; 676 677 a2noc: interconnect@1704000 { 678 compatible = "qcom,sdm660-a2noc"; 679 reg = <0x01704000 0xc100>; 680 #interconnect-cells = <1>; 681 clock-names = "ipa", 682 "ufs_axi", 683 "aggre2_ufs_axi", 684 "aggre2_usb3_axi", 685 "cfg_noc_usb2_axi"; 686 clocks = <&rpmcc RPM_SMD_IPA_CLK>, 687 <&gcc GCC_UFS_AXI_CLK>, 688 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 689 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 690 <&gcc GCC_CFG_NOC_USB2_AXI_CLK>; 691 }; 692 693 mnoc: interconnect@1745000 { 694 compatible = "qcom,sdm660-mnoc"; 695 reg = <0x01745000 0xa010>; 696 #interconnect-cells = <1>; 697 clock-names = "iface"; 698 clocks = <&mmcc AHB_CLK_SRC>; 699 }; 700 701 tsens: thermal-sensor@10ae000 { 702 compatible = "qcom,sdm630-tsens", "qcom,tsens-v2"; 703 reg = <0x010ae000 0x1000>, /* TM */ 704 <0x010ad000 0x1000>; /* SROT */ 705 #qcom,sensors = <12>; 706 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 708 interrupt-names = "uplow", "critical"; 709 #thermal-sensor-cells = <1>; 710 }; 711 712 tcsr_mutex: hwlock@1f40000 { 713 compatible = "qcom,tcsr-mutex"; 714 reg = <0x01f40000 0x20000>; 715 #hwlock-cells = <1>; 716 }; 717 718 tcsr_regs_1: syscon@1f60000 { 719 compatible = "qcom,sdm630-tcsr", "syscon"; 720 reg = <0x01f60000 0x20000>; 721 }; 722 723 tlmm: pinctrl@3100000 { 724 compatible = "qcom,sdm630-pinctrl"; 725 reg = <0x03100000 0x400000>, 726 <0x03500000 0x400000>, 727 <0x03900000 0x400000>; 728 reg-names = "south", "center", "north"; 729 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 730 gpio-controller; 731 gpio-ranges = <&tlmm 0 0 114>; 732 #gpio-cells = <2>; 733 interrupt-controller; 734 #interrupt-cells = <2>; 735 736 blsp1_uart1_default: blsp1-uart1-default-state { 737 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 738 function = "blsp_uart1"; 739 drive-strength = <2>; 740 bias-disable; 741 }; 742 743 blsp1_uart1_sleep: blsp1-uart1-sleep-state { 744 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 745 function = "gpio"; 746 drive-strength = <2>; 747 bias-disable; 748 }; 749 750 blsp1_uart2_default: blsp1-uart2-default-state { 751 pins = "gpio4", "gpio5"; 752 function = "blsp_uart2"; 753 drive-strength = <2>; 754 bias-disable; 755 }; 756 757 blsp2_uart1_default: blsp2-uart1-active-state { 758 tx-rts-pins { 759 pins = "gpio16", "gpio19"; 760 function = "blsp_uart5"; 761 drive-strength = <2>; 762 bias-disable; 763 }; 764 765 rx-pins { 766 /* 767 * Avoid garbage data while BT module 768 * is powered off or not driving signal 769 */ 770 pins = "gpio17"; 771 function = "blsp_uart5"; 772 drive-strength = <2>; 773 bias-pull-up; 774 }; 775 776 cts-pins { 777 /* Match the pull of the BT module */ 778 pins = "gpio18"; 779 function = "blsp_uart5"; 780 drive-strength = <2>; 781 bias-pull-down; 782 }; 783 }; 784 785 blsp2_uart1_sleep: blsp2-uart1-sleep-state { 786 tx-pins { 787 pins = "gpio16"; 788 function = "gpio"; 789 drive-strength = <2>; 790 bias-pull-up; 791 }; 792 793 rx-cts-rts-pins { 794 pins = "gpio17", "gpio18", "gpio19"; 795 function = "gpio"; 796 drive-strength = <2>; 797 bias-disable; 798 }; 799 }; 800 801 i2c1_default: i2c1-default-state { 802 pins = "gpio2", "gpio3"; 803 function = "blsp_i2c1"; 804 drive-strength = <2>; 805 bias-disable; 806 }; 807 808 i2c1_sleep: i2c1-sleep-state { 809 pins = "gpio2", "gpio3"; 810 function = "blsp_i2c1"; 811 drive-strength = <2>; 812 bias-pull-up; 813 }; 814 815 i2c2_default: i2c2-default-state { 816 pins = "gpio6", "gpio7"; 817 function = "blsp_i2c2"; 818 drive-strength = <2>; 819 bias-disable; 820 }; 821 822 i2c2_sleep: i2c2-sleep-state { 823 pins = "gpio6", "gpio7"; 824 function = "blsp_i2c2"; 825 drive-strength = <2>; 826 bias-pull-up; 827 }; 828 829 i2c3_default: i2c3-default-state { 830 pins = "gpio10", "gpio11"; 831 function = "blsp_i2c3"; 832 drive-strength = <2>; 833 bias-disable; 834 }; 835 836 i2c3_sleep: i2c3-sleep-state { 837 pins = "gpio10", "gpio11"; 838 function = "blsp_i2c3"; 839 drive-strength = <2>; 840 bias-pull-up; 841 }; 842 843 i2c4_default: i2c4-default-state { 844 pins = "gpio14", "gpio15"; 845 function = "blsp_i2c4"; 846 drive-strength = <2>; 847 bias-disable; 848 }; 849 850 i2c4_sleep: i2c4-sleep-state { 851 pins = "gpio14", "gpio15"; 852 function = "blsp_i2c4"; 853 drive-strength = <2>; 854 bias-pull-up; 855 }; 856 857 i2c5_default: i2c5-default-state { 858 pins = "gpio18", "gpio19"; 859 function = "blsp_i2c5"; 860 drive-strength = <2>; 861 bias-disable; 862 }; 863 864 i2c5_sleep: i2c5-sleep-state { 865 pins = "gpio18", "gpio19"; 866 function = "blsp_i2c5"; 867 drive-strength = <2>; 868 bias-pull-up; 869 }; 870 871 i2c6_default: i2c6-default-state { 872 pins = "gpio22", "gpio23"; 873 function = "blsp_i2c6"; 874 drive-strength = <2>; 875 bias-disable; 876 }; 877 878 i2c6_sleep: i2c6-sleep-state { 879 pins = "gpio22", "gpio23"; 880 function = "blsp_i2c6"; 881 drive-strength = <2>; 882 bias-pull-up; 883 }; 884 885 i2c7_default: i2c7-default-state { 886 pins = "gpio26", "gpio27"; 887 function = "blsp_i2c7"; 888 drive-strength = <2>; 889 bias-disable; 890 }; 891 892 i2c7_sleep: i2c7-sleep-state { 893 pins = "gpio26", "gpio27"; 894 function = "blsp_i2c7"; 895 drive-strength = <2>; 896 bias-pull-up; 897 }; 898 899 i2c8_default: i2c8-default-state { 900 pins = "gpio30", "gpio31"; 901 function = "blsp_i2c8_a"; 902 drive-strength = <2>; 903 bias-disable; 904 }; 905 906 i2c8_sleep: i2c8-sleep-state { 907 pins = "gpio30", "gpio31"; 908 function = "blsp_i2c8_a"; 909 drive-strength = <2>; 910 bias-pull-up; 911 }; 912 913 cci0_default: cci0-default-state { 914 pins = "gpio36","gpio37"; 915 function = "cci_i2c"; 916 bias-pull-up; 917 drive-strength = <2>; 918 }; 919 920 cci1_default: cci1-default-state { 921 pins = "gpio38","gpio39"; 922 function = "cci_i2c"; 923 bias-pull-up; 924 drive-strength = <2>; 925 }; 926 927 sdc1_state_on: sdc1-on-state { 928 clk-pins { 929 pins = "sdc1_clk"; 930 bias-disable; 931 drive-strength = <16>; 932 }; 933 934 cmd-pins { 935 pins = "sdc1_cmd"; 936 bias-pull-up; 937 drive-strength = <10>; 938 }; 939 940 data-pins { 941 pins = "sdc1_data"; 942 bias-pull-up; 943 drive-strength = <10>; 944 }; 945 946 rclk-pins { 947 pins = "sdc1_rclk"; 948 bias-pull-down; 949 }; 950 }; 951 952 sdc1_state_off: sdc1-off-state { 953 clk-pins { 954 pins = "sdc1_clk"; 955 bias-disable; 956 drive-strength = <2>; 957 }; 958 959 cmd-pins { 960 pins = "sdc1_cmd"; 961 bias-pull-up; 962 drive-strength = <2>; 963 }; 964 965 data-pins { 966 pins = "sdc1_data"; 967 bias-pull-up; 968 drive-strength = <2>; 969 }; 970 971 rclk-pins { 972 pins = "sdc1_rclk"; 973 bias-pull-down; 974 }; 975 }; 976 977 sdc2_state_on: sdc2-on-state { 978 clk-pins { 979 pins = "sdc2_clk"; 980 bias-disable; 981 drive-strength = <16>; 982 }; 983 984 cmd-pins { 985 pins = "sdc2_cmd"; 986 bias-pull-up; 987 drive-strength = <10>; 988 }; 989 990 data-pins { 991 pins = "sdc2_data"; 992 bias-pull-up; 993 drive-strength = <10>; 994 }; 995 }; 996 997 sdc2_state_off: sdc2-off-state { 998 clk-pins { 999 pins = "sdc2_clk"; 1000 bias-disable; 1001 drive-strength = <2>; 1002 }; 1003 1004 cmd-pins { 1005 pins = "sdc2_cmd"; 1006 bias-pull-up; 1007 drive-strength = <2>; 1008 }; 1009 1010 data-pins { 1011 pins = "sdc2_data"; 1012 bias-pull-up; 1013 drive-strength = <2>; 1014 }; 1015 }; 1016 1017 spi7_default: spi7-default-state { 1018 pins = "gpio24", "gpio25", "gpio26", "gpio27"; 1019 function = "blsp_spi7"; 1020 drive-strength = <6>; 1021 bias-disable; 1022 }; 1023 1024 spi7_sleep: spi7-sleep-state { 1025 pins = "gpio24", "gpio25", "gpio26", "gpio27"; 1026 function = "blsp_spi7"; 1027 drive-strength = <6>; 1028 bias-disable; 1029 }; 1030 }; 1031 1032 remoteproc_mss: remoteproc@4080000 { 1033 compatible = "qcom,sdm660-mss-pil"; 1034 reg = <0x04080000 0x100>, <0x04180000 0x40>; 1035 reg-names = "qdsp6", "rmb"; 1036 1037 interrupts-extended = <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 1038 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1039 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1040 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1041 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1042 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1043 interrupt-names = "wdog", 1044 "fatal", 1045 "ready", 1046 "handover", 1047 "stop-ack", 1048 "shutdown-ack"; 1049 1050 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1051 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>, 1052 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1053 <&gcc GPLL0_OUT_MSSCC>, 1054 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1055 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 1056 <&rpmcc RPM_SMD_QDSS_CLK>, 1057 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1058 clock-names = "iface", 1059 "bus", 1060 "mem", 1061 "gpll0_mss", 1062 "snoc_axi", 1063 "mnoc_axi", 1064 "qdss", 1065 "xo"; 1066 1067 qcom,smem-states = <&modem_smp2p_out 0>; 1068 qcom,smem-state-names = "stop"; 1069 1070 resets = <&gcc GCC_MSS_RESTART>; 1071 reset-names = "mss_restart"; 1072 1073 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; 1074 1075 power-domains = <&rpmpd RPMPD_VDDCX>, 1076 <&rpmpd RPMPD_VDDMX>; 1077 power-domain-names = "cx", "mx"; 1078 1079 memory-region = <&mba_region>, <&mpss_region>, <&mdata_mem>; 1080 1081 status = "disabled"; 1082 1083 glink-edge { 1084 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>; 1085 label = "modem"; 1086 qcom,remote-pid = <1>; 1087 mboxes = <&apcs_glb 15>; 1088 }; 1089 }; 1090 1091 adreno_gpu: gpu@5000000 { 1092 compatible = "qcom,adreno-508.0", "qcom,adreno"; 1093 1094 reg = <0x05000000 0x40000>; 1095 reg-names = "kgsl_3d0_reg_memory"; 1096 1097 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1098 1099 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1100 <&gpucc GPUCC_RBBMTIMER_CLK>, 1101 <&gcc GCC_BIMC_GFX_CLK>, 1102 <&gcc GCC_GPU_BIMC_GFX_CLK>, 1103 <&gpucc GPUCC_RBCPR_CLK>, 1104 <&gpucc GPUCC_GFX3D_CLK>; 1105 1106 clock-names = "iface", 1107 "rbbmtimer", 1108 "mem", 1109 "mem_iface", 1110 "rbcpr", 1111 "core"; 1112 1113 power-domains = <&rpmpd RPMPD_VDDMX>; 1114 iommus = <&kgsl_smmu 0>; 1115 1116 nvmem-cells = <&gpu_speed_bin>; 1117 nvmem-cell-names = "speed_bin"; 1118 1119 interconnects = <&bimc MASTER_OXILI &bimc SLAVE_EBI>; 1120 interconnect-names = "gfx-mem"; 1121 1122 operating-points-v2 = <&gpu_sdm630_opp_table>; 1123 #cooling-cells = <2>; 1124 1125 status = "disabled"; 1126 1127 gpu_sdm630_opp_table: opp-table { 1128 compatible = "operating-points-v2"; 1129 opp-775000000 { 1130 opp-hz = /bits/ 64 <775000000>; 1131 opp-level = <RPM_SMD_LEVEL_TURBO>; 1132 opp-peak-kBps = <5412000>; 1133 opp-supported-hw = <0xa2>; 1134 }; 1135 opp-647000000 { 1136 opp-hz = /bits/ 64 <647000000>; 1137 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 1138 opp-peak-kBps = <4068000>; 1139 opp-supported-hw = <0xff>; 1140 }; 1141 opp-588000000 { 1142 opp-hz = /bits/ 64 <588000000>; 1143 opp-level = <RPM_SMD_LEVEL_NOM>; 1144 opp-peak-kBps = <3072000>; 1145 opp-supported-hw = <0xff>; 1146 }; 1147 opp-465000000 { 1148 opp-hz = /bits/ 64 <465000000>; 1149 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 1150 opp-peak-kBps = <2724000>; 1151 opp-supported-hw = <0xff>; 1152 }; 1153 opp-370000000 { 1154 opp-hz = /bits/ 64 <370000000>; 1155 opp-level = <RPM_SMD_LEVEL_SVS>; 1156 opp-peak-kBps = <2188000>; 1157 opp-supported-hw = <0xff>; 1158 }; 1159 opp-240000000 { 1160 opp-hz = /bits/ 64 <240000000>; 1161 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 1162 opp-peak-kBps = <1648000>; 1163 opp-supported-hw = <0xff>; 1164 }; 1165 opp-160000000 { 1166 opp-hz = /bits/ 64 <160000000>; 1167 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 1168 opp-peak-kBps = <1200000>; 1169 opp-supported-hw = <0xff>; 1170 }; 1171 }; 1172 1173 adreno_gpu_zap: zap-shader { 1174 memory-region = <&zap_shader_region>; 1175 }; 1176 }; 1177 1178 kgsl_smmu: iommu@5040000 { 1179 compatible = "qcom,sdm630-smmu-v2", 1180 "qcom,adreno-smmu", "qcom,smmu-v2"; 1181 reg = <0x05040000 0x10000>; 1182 1183 /* 1184 * GX GDSC parent is CX. We need to bring up CX for SMMU 1185 * but we need both up for Adreno. On the other hand, we 1186 * need to manage the GX rpmpd domain in the adreno driver. 1187 * Enable CX/GX GDSCs here so that we can manage just the GX 1188 * RPM Power Domain in the Adreno driver. 1189 */ 1190 power-domains = <&gpucc GPU_GX_GDSC>; 1191 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1192 <&gcc GCC_BIMC_GFX_CLK>, 1193 <&gcc GCC_GPU_BIMC_GFX_CLK>; 1194 clock-names = "iface", 1195 "mem", 1196 "mem_iface"; 1197 #global-interrupts = <2>; 1198 #iommu-cells = <1>; 1199 1200 interrupts = 1201 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1203 1204 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>; 1212 }; 1213 1214 gpucc: clock-controller@5065000 { 1215 compatible = "qcom,gpucc-sdm630"; 1216 #clock-cells = <1>; 1217 #reset-cells = <1>; 1218 #power-domain-cells = <1>; 1219 reg = <0x05065000 0x9038>; 1220 1221 clocks = <&xo_board>, 1222 <&gcc GCC_GPU_GPLL0_CLK>, 1223 <&gcc GCC_GPU_GPLL0_DIV_CLK>; 1224 clock-names = "xo", 1225 "gcc_gpu_gpll0_clk", 1226 "gcc_gpu_gpll0_div_clk"; 1227 }; 1228 1229 lpass_smmu: iommu@5100000 { 1230 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 1231 reg = <0x05100000 0x40000>; 1232 #iommu-cells = <1>; 1233 1234 clocks = <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>; 1235 clock-names = "bus"; 1236 1237 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; 1238 1239 #global-interrupts = <2>; 1240 interrupts = 1241 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1243 1244 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1254 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1255 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1256 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1257 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 1258 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 1259 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 1260 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 1261 }; 1262 1263 sram@290000 { 1264 compatible = "qcom,rpm-stats"; 1265 reg = <0x00290000 0x10000>; 1266 }; 1267 1268 spmi_bus: spmi@800f000 { 1269 compatible = "qcom,spmi-pmic-arb"; 1270 reg = <0x0800f000 0x1000>, 1271 <0x08400000 0x1000000>, 1272 <0x09400000 0x1000000>, 1273 <0x0a400000 0x220000>, 1274 <0x0800a000 0x3000>; 1275 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1276 interrupt-names = "periph_irq"; 1277 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1278 qcom,ee = <0>; 1279 qcom,channel = <0>; 1280 #address-cells = <2>; 1281 #size-cells = <0>; 1282 interrupt-controller; 1283 #interrupt-cells = <4>; 1284 }; 1285 1286 usb3: usb@a8f8800 { 1287 compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; 1288 reg = <0x0a8f8800 0x400>; 1289 status = "disabled"; 1290 #address-cells = <1>; 1291 #size-cells = <1>; 1292 ranges; 1293 1294 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 1295 <&gcc GCC_USB30_MASTER_CLK>, 1296 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 1297 <&gcc GCC_USB30_SLEEP_CLK>, 1298 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 1299 clock-names = "cfg_noc", 1300 "core", 1301 "iface", 1302 "sleep", 1303 "mock_utmi"; 1304 1305 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1306 <&gcc GCC_USB30_MASTER_CLK>; 1307 assigned-clock-rates = <19200000>, <120000000>; 1308 1309 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 1310 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1311 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1312 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1313 interrupt-names = "pwr_event", 1314 "qusb2_phy", 1315 "hs_phy_irq", 1316 "ss_phy_irq"; 1317 1318 power-domains = <&gcc USB_30_GDSC>; 1319 1320 resets = <&gcc GCC_USB_30_BCR>; 1321 1322 usb3_dwc3: usb@a800000 { 1323 compatible = "snps,dwc3"; 1324 reg = <0x0a800000 0xc8d0>; 1325 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1326 snps,dis_u2_susphy_quirk; 1327 snps,dis_enblslpm_quirk; 1328 snps,parkmode-disable-ss-quirk; 1329 snps,dis-u1-entry-quirk; 1330 snps,dis-u2-entry-quirk; 1331 1332 phys = <&qusb2phy0>, <&usb3_qmpphy>; 1333 phy-names = "usb2-phy", "usb3-phy"; 1334 snps,hird-threshold = /bits/ 8 <0>; 1335 }; 1336 }; 1337 1338 usb3_qmpphy: phy@c010000 { 1339 compatible = "qcom,sdm660-qmp-usb3-phy"; 1340 reg = <0x0c010000 0x1000>; 1341 1342 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 1343 <&gcc GCC_USB3_CLKREF_CLK>, 1344 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1345 <&gcc GCC_USB3_PHY_PIPE_CLK>; 1346 clock-names = "aux", 1347 "ref", 1348 "cfg_ahb", 1349 "pipe"; 1350 clock-output-names = "usb3_phy_pipe_clk_src"; 1351 #clock-cells = <0>; 1352 #phy-cells = <0>; 1353 1354 resets = <&gcc GCC_USB3_PHY_BCR>, 1355 <&gcc GCC_USB3PHY_PHY_BCR>; 1356 reset-names = "phy", 1357 "phy_phy"; 1358 1359 qcom,tcsr-reg = <&tcsr_regs_1 0x6b244>; 1360 1361 status = "disabled"; 1362 }; 1363 1364 qusb2phy0: phy@c012000 { 1365 compatible = "qcom,sdm660-qusb2-phy"; 1366 reg = <0x0c012000 0x180>; 1367 #phy-cells = <0>; 1368 1369 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1370 <&gcc GCC_RX0_USB2_CLKREF_CLK>; 1371 clock-names = "cfg_ahb", "ref"; 1372 1373 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1374 nvmem-cells = <&qusb2_hstx_trim>; 1375 status = "disabled"; 1376 }; 1377 1378 qusb2phy1: phy@c014000 { 1379 compatible = "qcom,sdm660-qusb2-phy"; 1380 reg = <0x0c014000 0x180>; 1381 #phy-cells = <0>; 1382 1383 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1384 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 1385 clock-names = "cfg_ahb", "ref"; 1386 1387 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1388 nvmem-cells = <&qusb2_hstx_trim>; 1389 status = "disabled"; 1390 }; 1391 1392 sdhc_2: mmc@c084000 { 1393 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 1394 reg = <0x0c084000 0x1000>; 1395 reg-names = "hc"; 1396 1397 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1398 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1399 interrupt-names = "hc_irq", "pwr_irq"; 1400 1401 bus-width = <4>; 1402 1403 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1404 <&gcc GCC_SDCC2_APPS_CLK>, 1405 <&xo_board>; 1406 clock-names = "iface", "core", "xo"; 1407 1408 resets = <&gcc GCC_SDCC2_BCR>; 1409 1410 interconnects = <&a2noc 3 &a2noc 10>, 1411 <&gnoc 0 &cnoc 28>; 1412 interconnect-names = "sdhc-ddr","cpu-sdhc"; 1413 operating-points-v2 = <&sdhc2_opp_table>; 1414 1415 pinctrl-names = "default", "sleep"; 1416 pinctrl-0 = <&sdc2_state_on>; 1417 pinctrl-1 = <&sdc2_state_off>; 1418 power-domains = <&rpmpd RPMPD_VDDCX>; 1419 1420 status = "disabled"; 1421 1422 sdhc2_opp_table: opp-table { 1423 compatible = "operating-points-v2"; 1424 1425 opp-50000000 { 1426 opp-hz = /bits/ 64 <50000000>; 1427 required-opps = <&rpmpd_opp_low_svs>; 1428 opp-peak-kBps = <200000 140000>; 1429 opp-avg-kBps = <130718 133320>; 1430 }; 1431 opp-100000000 { 1432 opp-hz = /bits/ 64 <100000000>; 1433 required-opps = <&rpmpd_opp_svs>; 1434 opp-peak-kBps = <250000 160000>; 1435 opp-avg-kBps = <196078 150000>; 1436 }; 1437 opp-200000000 { 1438 opp-hz = /bits/ 64 <200000000>; 1439 required-opps = <&rpmpd_opp_nom>; 1440 opp-peak-kBps = <4096000 4096000>; 1441 opp-avg-kBps = <1338562 1338562>; 1442 }; 1443 }; 1444 }; 1445 1446 sdhc_1: mmc@c0c4000 { 1447 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 1448 reg = <0x0c0c4000 0x1000>, 1449 <0x0c0c5000 0x1000>, 1450 <0x0c0c8000 0x8000>; 1451 reg-names = "hc", "cqhci", "ice"; 1452 1453 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1455 interrupt-names = "hc_irq", "pwr_irq"; 1456 1457 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1458 <&gcc GCC_SDCC1_APPS_CLK>, 1459 <&xo_board>, 1460 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 1461 clock-names = "iface", "core", "xo", "ice"; 1462 1463 resets = <&gcc GCC_SDCC1_BCR>; 1464 1465 interconnects = <&a2noc 2 &a2noc 10>, 1466 <&gnoc 0 &cnoc 27>; 1467 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 1468 operating-points-v2 = <&sdhc1_opp_table>; 1469 pinctrl-names = "default", "sleep"; 1470 pinctrl-0 = <&sdc1_state_on>; 1471 pinctrl-1 = <&sdc1_state_off>; 1472 power-domains = <&rpmpd RPMPD_VDDCX>; 1473 1474 bus-width = <8>; 1475 non-removable; 1476 1477 status = "disabled"; 1478 1479 sdhc1_opp_table: opp-table { 1480 compatible = "operating-points-v2"; 1481 1482 opp-50000000 { 1483 opp-hz = /bits/ 64 <50000000>; 1484 required-opps = <&rpmpd_opp_low_svs>; 1485 opp-peak-kBps = <200000 140000>; 1486 opp-avg-kBps = <130718 133320>; 1487 }; 1488 opp-100000000 { 1489 opp-hz = /bits/ 64 <100000000>; 1490 required-opps = <&rpmpd_opp_svs>; 1491 opp-peak-kBps = <250000 160000>; 1492 opp-avg-kBps = <196078 150000>; 1493 }; 1494 opp-384000000 { 1495 opp-hz = /bits/ 64 <384000000>; 1496 required-opps = <&rpmpd_opp_nom>; 1497 opp-peak-kBps = <4096000 4096000>; 1498 opp-avg-kBps = <1338562 1338562>; 1499 }; 1500 }; 1501 }; 1502 1503 usb2: usb@c2f8800 { 1504 compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; 1505 reg = <0x0c2f8800 0x400>; 1506 status = "disabled"; 1507 #address-cells = <1>; 1508 #size-cells = <1>; 1509 ranges; 1510 1511 clocks = <&gcc GCC_CFG_NOC_USB2_AXI_CLK>, 1512 <&gcc GCC_USB20_MASTER_CLK>, 1513 <&gcc GCC_USB20_SLEEP_CLK>, 1514 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 1515 clock-names = "cfg_noc", "core", 1516 "sleep", "mock_utmi"; 1517 1518 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 1519 <&gcc GCC_USB20_MASTER_CLK>; 1520 assigned-clock-rates = <19200000>, <60000000>; 1521 1522 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 1525 interrupt-names = "pwr_event", 1526 "qusb2_phy", 1527 "hs_phy_irq"; 1528 1529 qcom,select-utmi-as-pipe-clk; 1530 1531 resets = <&gcc GCC_USB_20_BCR>; 1532 1533 usb2_dwc3: usb@c200000 { 1534 compatible = "snps,dwc3"; 1535 reg = <0x0c200000 0xc8d0>; 1536 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1537 snps,dis_u2_susphy_quirk; 1538 snps,dis_enblslpm_quirk; 1539 snps,dis-u1-entry-quirk; 1540 snps,dis-u2-entry-quirk; 1541 1542 /* This is the HS-only host */ 1543 maximum-speed = "high-speed"; 1544 phys = <&qusb2phy1>; 1545 phy-names = "usb2-phy"; 1546 snps,hird-threshold = /bits/ 8 <0>; 1547 }; 1548 }; 1549 1550 mmcc: clock-controller@c8c0000 { 1551 compatible = "qcom,mmcc-sdm630"; 1552 reg = <0x0c8c0000 0x40000>; 1553 #clock-cells = <1>; 1554 #reset-cells = <1>; 1555 #power-domain-cells = <1>; 1556 clock-names = "xo", 1557 "sleep_clk", 1558 "gpll0", 1559 "gpll0_div", 1560 "dsi0pll", 1561 "dsi0pllbyte", 1562 "dsi1pll", 1563 "dsi1pllbyte", 1564 "dp_link_2x_clk_divsel_five", 1565 "dp_vco_divided_clk_src_mux"; 1566 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1567 <&sleep_clk>, 1568 <&gcc GCC_MMSS_GPLL0_CLK>, 1569 <&gcc GCC_MMSS_GPLL0_DIV_CLK>, 1570 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 1571 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1572 <0>, 1573 <0>, 1574 <0>, 1575 <0>; 1576 }; 1577 1578 mdss: display-subsystem@c900000 { 1579 compatible = "qcom,mdss"; 1580 reg = <0x0c900000 0x1000>, 1581 <0x0c9b0000 0x1040>; 1582 reg-names = "mdss_phys", "vbif_phys"; 1583 1584 power-domains = <&mmcc MDSS_GDSC>; 1585 resets = <&mmcc MDSS_BCR>; 1586 1587 clocks = <&mmcc MDSS_AHB_CLK>, 1588 <&mmcc MDSS_AXI_CLK>, 1589 <&mmcc MDSS_VSYNC_CLK>, 1590 <&mmcc MDSS_MDP_CLK>; 1591 clock-names = "iface", 1592 "bus", 1593 "vsync", 1594 "core"; 1595 1596 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1597 1598 interrupt-controller; 1599 #interrupt-cells = <1>; 1600 1601 #address-cells = <1>; 1602 #size-cells = <1>; 1603 ranges; 1604 status = "disabled"; 1605 1606 mdp: display-controller@c901000 { 1607 compatible = "qcom,sdm630-mdp5", "qcom,mdp5"; 1608 reg = <0x0c901000 0x89000>; 1609 reg-names = "mdp_phys"; 1610 1611 interrupt-parent = <&mdss>; 1612 interrupts = <0>; 1613 1614 assigned-clocks = <&mmcc MDSS_MDP_CLK>, 1615 <&mmcc MDSS_VSYNC_CLK>; 1616 assigned-clock-rates = <300000000>, 1617 <19200000>; 1618 clocks = <&mmcc MDSS_AHB_CLK>, 1619 <&mmcc MDSS_AXI_CLK>, 1620 <&mmcc MDSS_MDP_CLK>, 1621 <&mmcc MDSS_VSYNC_CLK>; 1622 clock-names = "iface", 1623 "bus", 1624 "core", 1625 "vsync"; 1626 1627 interconnects = <&mnoc 2 &bimc 5>, 1628 <&mnoc 3 &bimc 5>, 1629 <&gnoc 0 &mnoc 17>; 1630 interconnect-names = "mdp0-mem", 1631 "mdp1-mem", 1632 "rotator-mem"; 1633 iommus = <&mmss_smmu 0>; 1634 operating-points-v2 = <&mdp_opp_table>; 1635 power-domains = <&rpmpd RPMPD_VDDCX>; 1636 1637 ports { 1638 #address-cells = <1>; 1639 #size-cells = <0>; 1640 1641 port@0 { 1642 reg = <0>; 1643 mdp5_intf1_out: endpoint { 1644 remote-endpoint = <&mdss_dsi0_in>; 1645 }; 1646 }; 1647 }; 1648 1649 mdp_opp_table: opp-table { 1650 compatible = "operating-points-v2"; 1651 1652 opp-150000000 { 1653 opp-hz = /bits/ 64 <150000000>; 1654 opp-peak-kBps = <320000 320000 76800>; 1655 required-opps = <&rpmpd_opp_low_svs>; 1656 }; 1657 opp-275000000 { 1658 opp-hz = /bits/ 64 <275000000>; 1659 opp-peak-kBps = <6400000 6400000 160000>; 1660 required-opps = <&rpmpd_opp_svs>; 1661 }; 1662 opp-300000000 { 1663 opp-hz = /bits/ 64 <300000000>; 1664 opp-peak-kBps = <6400000 6400000 190000>; 1665 required-opps = <&rpmpd_opp_svs_plus>; 1666 }; 1667 opp-330000000 { 1668 opp-hz = /bits/ 64 <330000000>; 1669 opp-peak-kBps = <6400000 6400000 240000>; 1670 required-opps = <&rpmpd_opp_nom>; 1671 }; 1672 opp-412500000 { 1673 opp-hz = /bits/ 64 <412500000>; 1674 opp-peak-kBps = <6400000 6400000 320000>; 1675 required-opps = <&rpmpd_opp_turbo>; 1676 }; 1677 }; 1678 }; 1679 1680 mdss_dsi0: dsi@c994000 { 1681 compatible = "qcom,sdm660-dsi-ctrl", 1682 "qcom,mdss-dsi-ctrl"; 1683 reg = <0x0c994000 0x400>; 1684 reg-names = "dsi_ctrl"; 1685 1686 operating-points-v2 = <&dsi_opp_table>; 1687 power-domains = <&rpmpd RPMPD_VDDCX>; 1688 1689 interrupt-parent = <&mdss>; 1690 interrupts = <4>; 1691 1692 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 1693 <&mmcc PCLK0_CLK_SRC>; 1694 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1695 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 1696 1697 clocks = <&mmcc MDSS_MDP_CLK>, 1698 <&mmcc MDSS_BYTE0_CLK>, 1699 <&mmcc MDSS_BYTE0_INTF_CLK>, 1700 <&mmcc MNOC_AHB_CLK>, 1701 <&mmcc MDSS_AHB_CLK>, 1702 <&mmcc MDSS_AXI_CLK>, 1703 <&mmcc MISC_AHB_CLK>, 1704 <&mmcc MDSS_PCLK0_CLK>, 1705 <&mmcc MDSS_ESC0_CLK>; 1706 clock-names = "mdp_core", 1707 "byte", 1708 "byte_intf", 1709 "mnoc", 1710 "iface", 1711 "bus", 1712 "core_mmss", 1713 "pixel", 1714 "core"; 1715 1716 phys = <&mdss_dsi0_phy>; 1717 1718 status = "disabled"; 1719 1720 ports { 1721 #address-cells = <1>; 1722 #size-cells = <0>; 1723 1724 port@0 { 1725 reg = <0>; 1726 mdss_dsi0_in: endpoint { 1727 remote-endpoint = <&mdp5_intf1_out>; 1728 }; 1729 }; 1730 1731 port@1 { 1732 reg = <1>; 1733 mdss_dsi0_out: endpoint { 1734 }; 1735 }; 1736 }; 1737 }; 1738 1739 mdss_dsi0_phy: phy@c994400 { 1740 compatible = "qcom,dsi-phy-14nm-660"; 1741 reg = <0x0c994400 0x100>, 1742 <0x0c994500 0x300>, 1743 <0x0c994800 0x188>; 1744 reg-names = "dsi_phy", 1745 "dsi_phy_lane", 1746 "dsi_pll"; 1747 1748 #clock-cells = <1>; 1749 #phy-cells = <0>; 1750 1751 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; 1752 clock-names = "iface", "ref"; 1753 status = "disabled"; 1754 }; 1755 }; 1756 1757 blsp1_dma: dma-controller@c144000 { 1758 compatible = "qcom,bam-v1.7.0"; 1759 reg = <0x0c144000 0x1f000>; 1760 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1761 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1762 clock-names = "bam_clk"; 1763 #dma-cells = <1>; 1764 qcom,ee = <0>; 1765 qcom,controlled-remotely; 1766 num-channels = <18>; 1767 qcom,num-ees = <4>; 1768 }; 1769 1770 blsp1_uart1: serial@c16f000 { 1771 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1772 reg = <0x0c16f000 0x200>; 1773 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1774 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 1775 <&gcc GCC_BLSP1_AHB_CLK>; 1776 clock-names = "core", "iface"; 1777 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 1778 dma-names = "tx", "rx"; 1779 pinctrl-names = "default", "sleep"; 1780 pinctrl-0 = <&blsp1_uart1_default>; 1781 pinctrl-1 = <&blsp1_uart1_sleep>; 1782 status = "disabled"; 1783 }; 1784 1785 blsp1_uart2: serial@c170000 { 1786 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1787 reg = <0x0c170000 0x1000>; 1788 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1789 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 1790 <&gcc GCC_BLSP1_AHB_CLK>; 1791 clock-names = "core", "iface"; 1792 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 1793 dma-names = "tx", "rx"; 1794 pinctrl-names = "default"; 1795 pinctrl-0 = <&blsp1_uart2_default>; 1796 status = "disabled"; 1797 }; 1798 1799 blsp_i2c1: i2c@c175000 { 1800 compatible = "qcom,i2c-qup-v2.2.1"; 1801 reg = <0x0c175000 0x600>; 1802 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1803 1804 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1805 <&gcc GCC_BLSP1_AHB_CLK>; 1806 clock-names = "core", "iface"; 1807 clock-frequency = <400000>; 1808 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 1809 dma-names = "tx", "rx"; 1810 1811 pinctrl-names = "default", "sleep"; 1812 pinctrl-0 = <&i2c1_default>; 1813 pinctrl-1 = <&i2c1_sleep>; 1814 #address-cells = <1>; 1815 #size-cells = <0>; 1816 status = "disabled"; 1817 }; 1818 1819 blsp_i2c2: i2c@c176000 { 1820 compatible = "qcom,i2c-qup-v2.2.1"; 1821 reg = <0x0c176000 0x600>; 1822 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1823 1824 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1825 <&gcc GCC_BLSP1_AHB_CLK>; 1826 clock-names = "core", "iface"; 1827 clock-frequency = <400000>; 1828 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 1829 dma-names = "tx", "rx"; 1830 1831 pinctrl-names = "default", "sleep"; 1832 pinctrl-0 = <&i2c2_default>; 1833 pinctrl-1 = <&i2c2_sleep>; 1834 #address-cells = <1>; 1835 #size-cells = <0>; 1836 status = "disabled"; 1837 }; 1838 1839 blsp_i2c3: i2c@c177000 { 1840 compatible = "qcom,i2c-qup-v2.2.1"; 1841 reg = <0x0c177000 0x600>; 1842 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1843 1844 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1845 <&gcc GCC_BLSP1_AHB_CLK>; 1846 clock-names = "core", "iface"; 1847 clock-frequency = <400000>; 1848 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 1849 dma-names = "tx", "rx"; 1850 1851 pinctrl-names = "default", "sleep"; 1852 pinctrl-0 = <&i2c3_default>; 1853 pinctrl-1 = <&i2c3_sleep>; 1854 #address-cells = <1>; 1855 #size-cells = <0>; 1856 status = "disabled"; 1857 }; 1858 1859 blsp_i2c4: i2c@c178000 { 1860 compatible = "qcom,i2c-qup-v2.2.1"; 1861 reg = <0x0c178000 0x600>; 1862 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1863 1864 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1865 <&gcc GCC_BLSP1_AHB_CLK>; 1866 clock-names = "core", "iface"; 1867 clock-frequency = <400000>; 1868 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 1869 dma-names = "tx", "rx"; 1870 1871 pinctrl-names = "default", "sleep"; 1872 pinctrl-0 = <&i2c4_default>; 1873 pinctrl-1 = <&i2c4_sleep>; 1874 #address-cells = <1>; 1875 #size-cells = <0>; 1876 status = "disabled"; 1877 }; 1878 1879 blsp2_dma: dma-controller@c184000 { 1880 compatible = "qcom,bam-v1.7.0"; 1881 reg = <0x0c184000 0x1f000>; 1882 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1883 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1884 clock-names = "bam_clk"; 1885 #dma-cells = <1>; 1886 qcom,ee = <0>; 1887 qcom,controlled-remotely; 1888 num-channels = <18>; 1889 qcom,num-ees = <4>; 1890 }; 1891 1892 blsp2_uart1: serial@c1af000 { 1893 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1894 reg = <0x0c1af000 0x200>; 1895 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1896 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, 1897 <&gcc GCC_BLSP2_AHB_CLK>; 1898 clock-names = "core", "iface"; 1899 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 1900 dma-names = "tx", "rx"; 1901 pinctrl-names = "default", "sleep"; 1902 pinctrl-0 = <&blsp2_uart1_default>; 1903 pinctrl-1 = <&blsp2_uart1_sleep>; 1904 status = "disabled"; 1905 }; 1906 1907 blsp_i2c5: i2c@c1b5000 { 1908 compatible = "qcom,i2c-qup-v2.2.1"; 1909 reg = <0x0c1b5000 0x600>; 1910 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1911 1912 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1913 <&gcc GCC_BLSP2_AHB_CLK>; 1914 clock-names = "core", "iface"; 1915 clock-frequency = <400000>; 1916 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; 1917 dma-names = "tx", "rx"; 1918 1919 pinctrl-names = "default", "sleep"; 1920 pinctrl-0 = <&i2c5_default>; 1921 pinctrl-1 = <&i2c5_sleep>; 1922 #address-cells = <1>; 1923 #size-cells = <0>; 1924 status = "disabled"; 1925 }; 1926 1927 blsp_i2c6: i2c@c1b6000 { 1928 compatible = "qcom,i2c-qup-v2.2.1"; 1929 reg = <0x0c1b6000 0x600>; 1930 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1931 1932 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 1933 <&gcc GCC_BLSP2_AHB_CLK>; 1934 clock-names = "core", "iface"; 1935 clock-frequency = <400000>; 1936 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 1937 dma-names = "tx", "rx"; 1938 1939 pinctrl-names = "default", "sleep"; 1940 pinctrl-0 = <&i2c6_default>; 1941 pinctrl-1 = <&i2c6_sleep>; 1942 #address-cells = <1>; 1943 #size-cells = <0>; 1944 status = "disabled"; 1945 }; 1946 1947 blsp_i2c7: i2c@c1b7000 { 1948 compatible = "qcom,i2c-qup-v2.2.1"; 1949 reg = <0x0c1b7000 0x600>; 1950 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1951 1952 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 1953 <&gcc GCC_BLSP2_AHB_CLK>; 1954 clock-names = "core", "iface"; 1955 clock-frequency = <400000>; 1956 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 1957 dma-names = "tx", "rx"; 1958 1959 pinctrl-names = "default", "sleep"; 1960 pinctrl-0 = <&i2c7_default>; 1961 pinctrl-1 = <&i2c7_sleep>; 1962 #address-cells = <1>; 1963 #size-cells = <0>; 1964 status = "disabled"; 1965 }; 1966 1967 blsp_spi7: spi@c1b7000 { 1968 compatible = "qcom,spi-qup-v2.2.1"; 1969 reg = <0x0c1b7000 0x600>; 1970 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1971 1972 clocks = <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>, 1973 <&gcc GCC_BLSP2_AHB_CLK>; 1974 clock-names = "core", "iface"; 1975 1976 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 1977 dma-names = "tx", "rx"; 1978 1979 pinctrl-names = "default", "sleep"; 1980 pinctrl-0 = <&spi7_default>; 1981 pinctrl-1 = <&spi7_sleep>; 1982 #address-cells = <1>; 1983 #size-cells = <0>; 1984 status = "disabled"; 1985 }; 1986 1987 blsp_i2c8: i2c@c1b8000 { 1988 compatible = "qcom,i2c-qup-v2.2.1"; 1989 reg = <0x0c1b8000 0x600>; 1990 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1991 1992 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 1993 <&gcc GCC_BLSP2_AHB_CLK>; 1994 clock-names = "core", "iface"; 1995 clock-frequency = <400000>; 1996 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 1997 dma-names = "tx", "rx"; 1998 1999 pinctrl-names = "default", "sleep"; 2000 pinctrl-0 = <&i2c8_default>; 2001 pinctrl-1 = <&i2c8_sleep>; 2002 #address-cells = <1>; 2003 #size-cells = <0>; 2004 status = "disabled"; 2005 }; 2006 2007 sram@146bf000 { 2008 compatible = "qcom,sdm630-imem", "syscon", "simple-mfd"; 2009 reg = <0x146bf000 0x1000>; 2010 2011 #address-cells = <1>; 2012 #size-cells = <1>; 2013 2014 ranges = <0 0x146bf000 0x1000>; 2015 2016 pil-reloc@94c { 2017 compatible = "qcom,pil-reloc-info"; 2018 reg = <0x94c 0xc8>; 2019 }; 2020 }; 2021 2022 camss: camss@ca00020 { 2023 compatible = "qcom,sdm660-camss"; 2024 reg = <0x0ca00020 0x10>, 2025 <0x0ca30000 0x100>, 2026 <0x0ca30400 0x100>, 2027 <0x0ca30800 0x100>, 2028 <0x0ca30c00 0x100>, 2029 <0x0c824000 0x1000>, 2030 <0x0ca00120 0x4>, 2031 <0x0c825000 0x1000>, 2032 <0x0ca00124 0x4>, 2033 <0x0c826000 0x1000>, 2034 <0x0ca00128 0x4>, 2035 <0x0ca31000 0x500>, 2036 <0x0ca10000 0x1000>, 2037 <0x0ca14000 0x1000>; 2038 reg-names = "csi_clk_mux", 2039 "csid0", 2040 "csid1", 2041 "csid2", 2042 "csid3", 2043 "csiphy0", 2044 "csiphy0_clk_mux", 2045 "csiphy1", 2046 "csiphy1_clk_mux", 2047 "csiphy2", 2048 "csiphy2_clk_mux", 2049 "ispif", 2050 "vfe0", 2051 "vfe1"; 2052 interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 2053 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 2054 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 2055 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 2056 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 2057 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 2058 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 2059 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 2060 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 2061 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 2062 interrupt-names = "csid0", 2063 "csid1", 2064 "csid2", 2065 "csid3", 2066 "csiphy0", 2067 "csiphy1", 2068 "csiphy2", 2069 "ispif", 2070 "vfe0", 2071 "vfe1"; 2072 clocks = <&mmcc CAMSS_AHB_CLK>, 2073 <&mmcc CAMSS_CPHY_CSID0_CLK>, 2074 <&mmcc CAMSS_CPHY_CSID1_CLK>, 2075 <&mmcc CAMSS_CPHY_CSID2_CLK>, 2076 <&mmcc CAMSS_CPHY_CSID3_CLK>, 2077 <&mmcc CAMSS_CSI0_AHB_CLK>, 2078 <&mmcc CAMSS_CSI0_CLK>, 2079 <&mmcc CAMSS_CPHY_CSID0_CLK>, 2080 <&mmcc CAMSS_CSI0PIX_CLK>, 2081 <&mmcc CAMSS_CSI0RDI_CLK>, 2082 <&mmcc CAMSS_CSI1_AHB_CLK>, 2083 <&mmcc CAMSS_CSI1_CLK>, 2084 <&mmcc CAMSS_CPHY_CSID1_CLK>, 2085 <&mmcc CAMSS_CSI1PIX_CLK>, 2086 <&mmcc CAMSS_CSI1RDI_CLK>, 2087 <&mmcc CAMSS_CSI2_AHB_CLK>, 2088 <&mmcc CAMSS_CSI2_CLK>, 2089 <&mmcc CAMSS_CPHY_CSID2_CLK>, 2090 <&mmcc CAMSS_CSI2PIX_CLK>, 2091 <&mmcc CAMSS_CSI2RDI_CLK>, 2092 <&mmcc CAMSS_CSI3_AHB_CLK>, 2093 <&mmcc CAMSS_CSI3_CLK>, 2094 <&mmcc CAMSS_CPHY_CSID3_CLK>, 2095 <&mmcc CAMSS_CSI3PIX_CLK>, 2096 <&mmcc CAMSS_CSI3RDI_CLK>, 2097 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 2098 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 2099 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 2100 <&mmcc CSIPHY_AHB2CRIF_CLK>, 2101 <&mmcc CAMSS_CSI_VFE0_CLK>, 2102 <&mmcc CAMSS_CSI_VFE1_CLK>, 2103 <&mmcc CAMSS_ISPIF_AHB_CLK>, 2104 <&mmcc THROTTLE_CAMSS_AXI_CLK>, 2105 <&mmcc CAMSS_TOP_AHB_CLK>, 2106 <&mmcc CAMSS_VFE0_AHB_CLK>, 2107 <&mmcc CAMSS_VFE0_CLK>, 2108 <&mmcc CAMSS_VFE0_STREAM_CLK>, 2109 <&mmcc CAMSS_VFE1_AHB_CLK>, 2110 <&mmcc CAMSS_VFE1_CLK>, 2111 <&mmcc CAMSS_VFE1_STREAM_CLK>, 2112 <&mmcc CAMSS_VFE_VBIF_AHB_CLK>, 2113 <&mmcc CAMSS_VFE_VBIF_AXI_CLK>; 2114 clock-names = "ahb", 2115 "cphy_csid0", 2116 "cphy_csid1", 2117 "cphy_csid2", 2118 "cphy_csid3", 2119 "csi0_ahb", 2120 "csi0", 2121 "csi0_phy", 2122 "csi0_pix", 2123 "csi0_rdi", 2124 "csi1_ahb", 2125 "csi1", 2126 "csi1_phy", 2127 "csi1_pix", 2128 "csi1_rdi", 2129 "csi2_ahb", 2130 "csi2", 2131 "csi2_phy", 2132 "csi2_pix", 2133 "csi2_rdi", 2134 "csi3_ahb", 2135 "csi3", 2136 "csi3_phy", 2137 "csi3_pix", 2138 "csi3_rdi", 2139 "csiphy0_timer", 2140 "csiphy1_timer", 2141 "csiphy2_timer", 2142 "csiphy_ahb2crif", 2143 "csi_vfe0", 2144 "csi_vfe1", 2145 "ispif_ahb", 2146 "throttle_axi", 2147 "top_ahb", 2148 "vfe0_ahb", 2149 "vfe0", 2150 "vfe0_stream", 2151 "vfe1_ahb", 2152 "vfe1", 2153 "vfe1_stream", 2154 "vfe_ahb", 2155 "vfe_axi"; 2156 interconnects = <&mnoc 5 &bimc 5>; 2157 interconnect-names = "vfe-mem"; 2158 iommus = <&mmss_smmu 0xc00>, 2159 <&mmss_smmu 0xc01>, 2160 <&mmss_smmu 0xc02>, 2161 <&mmss_smmu 0xc03>; 2162 power-domains = <&mmcc CAMSS_VFE0_GDSC>, 2163 <&mmcc CAMSS_VFE1_GDSC>; 2164 status = "disabled"; 2165 2166 ports { 2167 #address-cells = <1>; 2168 #size-cells = <0>; 2169 }; 2170 }; 2171 2172 cci: cci@ca0c000 { 2173 compatible = "qcom,msm8996-cci"; 2174 #address-cells = <1>; 2175 #size-cells = <0>; 2176 reg = <0x0ca0c000 0x1000>; 2177 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 2178 2179 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 2180 <&mmcc CAMSS_CCI_CLK>; 2181 assigned-clock-rates = <80800000>, <37500000>; 2182 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2183 <&mmcc CAMSS_CCI_AHB_CLK>, 2184 <&mmcc CAMSS_CCI_CLK>, 2185 <&mmcc CAMSS_AHB_CLK>; 2186 clock-names = "camss_top_ahb", 2187 "cci_ahb", 2188 "cci", 2189 "camss_ahb"; 2190 2191 pinctrl-names = "default"; 2192 pinctrl-0 = <&cci0_default &cci1_default>; 2193 power-domains = <&mmcc CAMSS_TOP_GDSC>; 2194 status = "disabled"; 2195 2196 cci_i2c0: i2c-bus@0 { 2197 reg = <0>; 2198 clock-frequency = <400000>; 2199 #address-cells = <1>; 2200 #size-cells = <0>; 2201 }; 2202 2203 cci_i2c1: i2c-bus@1 { 2204 reg = <1>; 2205 clock-frequency = <400000>; 2206 #address-cells = <1>; 2207 #size-cells = <0>; 2208 }; 2209 }; 2210 2211 venus: video-codec@cc00000 { 2212 compatible = "qcom,sdm660-venus"; 2213 reg = <0x0cc00000 0xff000>; 2214 clocks = <&mmcc VIDEO_CORE_CLK>, 2215 <&mmcc VIDEO_AHB_CLK>, 2216 <&mmcc VIDEO_AXI_CLK>, 2217 <&mmcc THROTTLE_VIDEO_AXI_CLK>; 2218 clock-names = "core", "iface", "bus", "bus_throttle"; 2219 interconnects = <&gnoc 0 &mnoc 13>, 2220 <&mnoc 4 &bimc 5>; 2221 interconnect-names = "cpu-cfg", "video-mem"; 2222 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 2223 iommus = <&mmss_smmu 0x400>, 2224 <&mmss_smmu 0x401>, 2225 <&mmss_smmu 0x40a>, 2226 <&mmss_smmu 0x407>, 2227 <&mmss_smmu 0x40e>, 2228 <&mmss_smmu 0x40f>, 2229 <&mmss_smmu 0x408>, 2230 <&mmss_smmu 0x409>, 2231 <&mmss_smmu 0x40b>, 2232 <&mmss_smmu 0x40c>, 2233 <&mmss_smmu 0x40d>, 2234 <&mmss_smmu 0x410>, 2235 <&mmss_smmu 0x421>, 2236 <&mmss_smmu 0x428>, 2237 <&mmss_smmu 0x429>, 2238 <&mmss_smmu 0x42b>, 2239 <&mmss_smmu 0x42c>, 2240 <&mmss_smmu 0x42d>, 2241 <&mmss_smmu 0x411>, 2242 <&mmss_smmu 0x431>; 2243 memory-region = <&venus_region>; 2244 power-domains = <&mmcc VENUS_GDSC>; 2245 status = "disabled"; 2246 2247 video-decoder { 2248 compatible = "venus-decoder"; 2249 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2250 clock-names = "vcodec0_core"; 2251 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2252 }; 2253 2254 video-encoder { 2255 compatible = "venus-encoder"; 2256 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2257 clock-names = "vcodec0_core"; 2258 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2259 }; 2260 }; 2261 2262 mmss_smmu: iommu@cd00000 { 2263 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 2264 reg = <0x0cd00000 0x40000>; 2265 2266 clocks = <&mmcc MNOC_AHB_CLK>, 2267 <&mmcc BIMC_SMMU_AHB_CLK>, 2268 <&mmcc BIMC_SMMU_AXI_CLK>; 2269 clock-names = "iface-mm", "iface-smmu", 2270 "bus-smmu"; 2271 #global-interrupts = <2>; 2272 #iommu-cells = <1>; 2273 2274 interrupts = 2275 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2276 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2277 2278 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2279 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 2280 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 2281 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2282 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 2283 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 2284 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 2285 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 2286 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 2287 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 2288 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 2289 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 2290 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 2291 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 2292 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 2293 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2294 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 2295 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2296 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2297 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 2298 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 2299 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 2300 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 2301 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 2302 2303 status = "disabled"; 2304 }; 2305 2306 lpi_tlmm: pinctrl@15070000 { 2307 compatible = "qcom,sdm660-lpass-lpi-pinctrl"; 2308 reg = <0x15070000 0x20000>; 2309 gpio-controller; 2310 #gpio-cells = <2>; 2311 gpio-ranges = <&lpi_tlmm 0 0 32>; 2312 2313 cdc_pdm_default: cdc-pdm-default-state { 2314 clk-pins { 2315 pins = "gpio18"; 2316 function = "pdm_clk"; 2317 drive-strength = <8>; 2318 output-high; 2319 }; 2320 2321 sync-pins { 2322 pins = "gpio19"; 2323 function = "pdm_sync"; 2324 drive-strength = <4>; 2325 output-high; 2326 }; 2327 2328 tx-pins { 2329 pins = "gpio20"; 2330 function = "pdm_tx"; 2331 drive-strength = <8>; 2332 }; 2333 2334 rx-pins { 2335 pins = "gpio21", "gpio23", "gpio25"; 2336 function = "pdm_rx"; 2337 drive-strength = <4>; 2338 output-high; 2339 }; 2340 }; 2341 2342 cdc_comp_default: cdc-comp-default-state { 2343 pins = "gpio22", "gpio24"; 2344 function = "comp_rx"; 2345 drive-strength = <8>; 2346 }; 2347 2348 cdc_dmic_default: cdc-dmic-default-state { 2349 dmic1-clk-pins { 2350 pins = "gpio26"; 2351 function = "dmic1_clk"; 2352 drive-strength = <8>; 2353 output-high; 2354 }; 2355 2356 dmic1-data-pins { 2357 pins = "gpio27"; 2358 function = "dmic1_data"; 2359 drive-strength = <8>; 2360 output-high; 2361 }; 2362 2363 dmic2-clk-pins { 2364 pins = "gpio28"; 2365 function = "dmic2_clk"; 2366 drive-strength = <8>; 2367 input-enable; 2368 }; 2369 2370 dmic2-data-pins { 2371 pins = "gpio29"; 2372 function = "dmic2_data"; 2373 drive-strength = <8>; 2374 input-enable; 2375 }; 2376 }; 2377 }; 2378 2379 adsp_pil: remoteproc@15700000 { 2380 compatible = "qcom,sdm660-adsp-pas"; 2381 reg = <0x15700000 0x4040>; 2382 2383 interrupts-extended = 2384 <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2385 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2386 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2387 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2388 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2389 interrupt-names = "wdog", "fatal", "ready", 2390 "handover", "stop-ack"; 2391 2392 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2393 clock-names = "xo"; 2394 2395 memory-region = <&adsp_region>; 2396 power-domains = <&rpmpd RPMPD_VDDCX>; 2397 power-domain-names = "cx"; 2398 2399 qcom,smem-states = <&adsp_smp2p_out 0>; 2400 qcom,smem-state-names = "stop"; 2401 2402 glink-edge { 2403 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 2404 2405 label = "lpass"; 2406 mboxes = <&apcs_glb 9>; 2407 qcom,remote-pid = <2>; 2408 2409 apr { 2410 compatible = "qcom,apr-v2"; 2411 qcom,glink-channels = "apr_audio_svc"; 2412 qcom,domain = <APR_DOMAIN_ADSP>; 2413 #address-cells = <1>; 2414 #size-cells = <0>; 2415 2416 service@3 { 2417 reg = <APR_SVC_ADSP_CORE>; 2418 compatible = "qcom,q6core"; 2419 }; 2420 2421 q6afe: service@4 { 2422 compatible = "qcom,q6afe"; 2423 reg = <APR_SVC_AFE>; 2424 q6afedai: dais { 2425 compatible = "qcom,q6afe-dais"; 2426 #address-cells = <1>; 2427 #size-cells = <0>; 2428 #sound-dai-cells = <1>; 2429 }; 2430 }; 2431 2432 q6asm: service@7 { 2433 compatible = "qcom,q6asm"; 2434 reg = <APR_SVC_ASM>; 2435 q6asmdai: dais { 2436 compatible = "qcom,q6asm-dais"; 2437 #address-cells = <1>; 2438 #size-cells = <0>; 2439 #sound-dai-cells = <1>; 2440 iommus = <&lpass_smmu 1>; 2441 }; 2442 }; 2443 2444 q6adm: service@8 { 2445 compatible = "qcom,q6adm"; 2446 reg = <APR_SVC_ADM>; 2447 q6routing: routing { 2448 compatible = "qcom,q6adm-routing"; 2449 #sound-dai-cells = <0>; 2450 }; 2451 }; 2452 }; 2453 2454 fastrpc { 2455 compatible = "qcom,fastrpc"; 2456 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2457 label = "adsp"; 2458 qcom,non-secure-domain; 2459 #address-cells = <1>; 2460 #size-cells = <0>; 2461 2462 compute-cb@1 { 2463 compatible = "qcom,fastrpc-compute-cb"; 2464 reg = <1>; 2465 iommus = <&lpass_smmu 3>; 2466 }; 2467 2468 compute-cb@2 { 2469 compatible = "qcom,fastrpc-compute-cb"; 2470 reg = <2>; 2471 iommus = <&lpass_smmu 7>; 2472 }; 2473 2474 compute-cb@3 { 2475 compatible = "qcom,fastrpc-compute-cb"; 2476 reg = <3>; 2477 iommus = <&lpass_smmu 8>; 2478 }; 2479 2480 compute-cb@4 { 2481 compatible = "qcom,fastrpc-compute-cb"; 2482 reg = <4>; 2483 iommus = <&lpass_smmu 9>; 2484 }; 2485 }; 2486 }; 2487 }; 2488 2489 gnoc: interconnect@17900000 { 2490 compatible = "qcom,sdm660-gnoc"; 2491 reg = <0x17900000 0xe000>; 2492 #interconnect-cells = <1>; 2493 }; 2494 2495 apcs_glb: mailbox@17911000 { 2496 compatible = "qcom,sdm660-apcs-hmss-global", 2497 "qcom,msm8994-apcs-kpss-global"; 2498 reg = <0x17911000 0x1000>; 2499 2500 #mbox-cells = <1>; 2501 }; 2502 2503 timer@17920000 { 2504 #address-cells = <1>; 2505 #size-cells = <1>; 2506 ranges; 2507 compatible = "arm,armv7-timer-mem"; 2508 reg = <0x17920000 0x1000>; 2509 clock-frequency = <19200000>; 2510 2511 frame@17921000 { 2512 frame-number = <0>; 2513 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2514 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2515 reg = <0x17921000 0x1000>, 2516 <0x17922000 0x1000>; 2517 }; 2518 2519 frame@17923000 { 2520 frame-number = <1>; 2521 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2522 reg = <0x17923000 0x1000>; 2523 status = "disabled"; 2524 }; 2525 2526 frame@17924000 { 2527 frame-number = <2>; 2528 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2529 reg = <0x17924000 0x1000>; 2530 status = "disabled"; 2531 }; 2532 2533 frame@17925000 { 2534 frame-number = <3>; 2535 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2536 reg = <0x17925000 0x1000>; 2537 status = "disabled"; 2538 }; 2539 2540 frame@17926000 { 2541 frame-number = <4>; 2542 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2543 reg = <0x17926000 0x1000>; 2544 status = "disabled"; 2545 }; 2546 2547 frame@17927000 { 2548 frame-number = <5>; 2549 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2550 reg = <0x17927000 0x1000>; 2551 status = "disabled"; 2552 }; 2553 2554 frame@17928000 { 2555 frame-number = <6>; 2556 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2557 reg = <0x17928000 0x1000>; 2558 status = "disabled"; 2559 }; 2560 }; 2561 2562 intc: interrupt-controller@17a00000 { 2563 compatible = "arm,gic-v3"; 2564 reg = <0x17a00000 0x10000>, /* GICD */ 2565 <0x17b00000 0x100000>; /* GICR * 8 */ 2566 #interrupt-cells = <3>; 2567 #address-cells = <1>; 2568 #size-cells = <1>; 2569 ranges; 2570 interrupt-controller; 2571 #redistributor-regions = <1>; 2572 redistributor-stride = <0x0 0x20000>; 2573 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2574 }; 2575 2576 wifi: wifi@18800000 { 2577 compatible = "qcom,wcn3990-wifi"; 2578 reg = <0x18800000 0x800000>; 2579 reg-names = "membase"; 2580 memory-region = <&wlan_msa_mem>; 2581 clocks = <&rpmcc RPM_SMD_RF_CLK1_PIN>; 2582 clock-names = "cxo_ref_clk_pin"; 2583 interrupts = 2584 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 2585 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 2586 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 2587 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 2588 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 2589 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2590 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 2591 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2592 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2593 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2594 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2595 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 2596 iommus = <&anoc2_smmu 0x1a00>, 2597 <&anoc2_smmu 0x1a01>; 2598 qcom,snoc-host-cap-8bit-quirk; 2599 qcom,no-msa-ready-indicator; 2600 status = "disabled"; 2601 }; 2602 }; 2603 2604 sound: sound { 2605 }; 2606 2607 thermal-zones { 2608 aoss-thermal { 2609 polling-delay-passive = <250>; 2610 2611 thermal-sensors = <&tsens 0>; 2612 2613 trips { 2614 aoss_alert0: trip-point0 { 2615 temperature = <105000>; 2616 hysteresis = <1000>; 2617 type = "hot"; 2618 }; 2619 }; 2620 }; 2621 2622 cpuss0-thermal { 2623 polling-delay-passive = <250>; 2624 2625 thermal-sensors = <&tsens 1>; 2626 2627 trips { 2628 cpuss0_alert0: trip-point0 { 2629 temperature = <125000>; 2630 hysteresis = <1000>; 2631 type = "hot"; 2632 }; 2633 }; 2634 }; 2635 2636 cpuss1-thermal { 2637 polling-delay-passive = <250>; 2638 2639 thermal-sensors = <&tsens 2>; 2640 2641 trips { 2642 cpuss1_alert0: trip-point0 { 2643 temperature = <125000>; 2644 hysteresis = <1000>; 2645 type = "hot"; 2646 }; 2647 }; 2648 }; 2649 2650 cpu0-thermal { 2651 polling-delay-passive = <250>; 2652 2653 thermal-sensors = <&tsens 3>; 2654 2655 trips { 2656 cpu0_alert0: trip-point0 { 2657 temperature = <70000>; 2658 hysteresis = <1000>; 2659 type = "passive"; 2660 }; 2661 2662 cpu0_crit: cpu-crit { 2663 temperature = <110000>; 2664 hysteresis = <1000>; 2665 type = "critical"; 2666 }; 2667 }; 2668 }; 2669 2670 cpu1-thermal { 2671 polling-delay-passive = <250>; 2672 2673 thermal-sensors = <&tsens 4>; 2674 2675 trips { 2676 cpu1_alert0: trip-point0 { 2677 temperature = <70000>; 2678 hysteresis = <1000>; 2679 type = "passive"; 2680 }; 2681 2682 cpu1_crit: cpu-crit { 2683 temperature = <110000>; 2684 hysteresis = <1000>; 2685 type = "critical"; 2686 }; 2687 }; 2688 }; 2689 2690 cpu2-thermal { 2691 polling-delay-passive = <250>; 2692 2693 thermal-sensors = <&tsens 5>; 2694 2695 trips { 2696 cpu2_alert0: trip-point0 { 2697 temperature = <70000>; 2698 hysteresis = <1000>; 2699 type = "passive"; 2700 }; 2701 2702 cpu2_crit: cpu-crit { 2703 temperature = <110000>; 2704 hysteresis = <1000>; 2705 type = "critical"; 2706 }; 2707 }; 2708 }; 2709 2710 cpu3-thermal { 2711 polling-delay-passive = <250>; 2712 2713 thermal-sensors = <&tsens 6>; 2714 2715 trips { 2716 cpu3_alert0: trip-point0 { 2717 temperature = <70000>; 2718 hysteresis = <1000>; 2719 type = "passive"; 2720 }; 2721 2722 cpu3_crit: cpu-crit { 2723 temperature = <110000>; 2724 hysteresis = <1000>; 2725 type = "critical"; 2726 }; 2727 }; 2728 }; 2729 2730 /* 2731 * According to what downstream DTS says, 2732 * the entire power efficient cluster has 2733 * only a single thermal sensor. 2734 */ 2735 2736 pwr-cluster-thermal { 2737 polling-delay-passive = <250>; 2738 2739 thermal-sensors = <&tsens 7>; 2740 2741 trips { 2742 pwr_cluster_alert0: trip-point0 { 2743 temperature = <70000>; 2744 hysteresis = <1000>; 2745 type = "passive"; 2746 }; 2747 2748 pwr_cluster_crit: cpu-crit { 2749 temperature = <110000>; 2750 hysteresis = <1000>; 2751 type = "critical"; 2752 }; 2753 }; 2754 }; 2755 2756 gpu-thermal { 2757 polling-delay-passive = <250>; 2758 2759 thermal-sensors = <&tsens 8>; 2760 2761 cooling-maps { 2762 map0 { 2763 trip = <&gpu_alert0>; 2764 cooling-device = <&adreno_gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2765 }; 2766 }; 2767 2768 trips { 2769 gpu_alert0: trip-point0 { 2770 temperature = <85000>; 2771 hysteresis = <1000>; 2772 type = "passive"; 2773 }; 2774 2775 trip-point1 { 2776 temperature = <90000>; 2777 hysteresis = <1000>; 2778 type = "hot"; 2779 }; 2780 2781 trip-point2 { 2782 temperature = <110000>; 2783 hysteresis = <1000>; 2784 type = "critical"; 2785 }; 2786 }; 2787 }; 2788 }; 2789 2790 timer { 2791 compatible = "arm,armv8-timer"; 2792 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 2793 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 2794 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 2795 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 2796 }; 2797}; 2798 2799