1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Konrad Dybcio <konradybcio@gmail.com> 4 * Copyright (c) 2020, AngeloGioacchino Del Regno <kholk11@gmail.com> 5 */ 6 7#include <dt-bindings/clock/qcom,gcc-sdm660.h> 8#include <dt-bindings/clock/qcom,gpucc-sdm660.h> 9#include <dt-bindings/clock/qcom,mmcc-sdm660.h> 10#include <dt-bindings/clock/qcom,rpmcc.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/soc/qcom,apr.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 clocks { 25 xo_board: xo-board { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <19200000>; 29 clock-output-names = "xo_board"; 30 }; 31 32 sleep_clk: sleep-clk { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <32764>; 36 clock-output-names = "sleep_clk"; 37 }; 38 }; 39 40 cpus { 41 #address-cells = <2>; 42 #size-cells = <0>; 43 44 CPU0: cpu@100 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a53"; 47 reg = <0x0 0x100>; 48 enable-method = "psci"; 49 cpu-idle-states = <&PERF_CPU_SLEEP_0 50 &PERF_CPU_SLEEP_1 51 &PERF_CLUSTER_SLEEP_0 52 &PERF_CLUSTER_SLEEP_1 53 &PERF_CLUSTER_SLEEP_2>; 54 capacity-dmips-mhz = <1126>; 55 #cooling-cells = <2>; 56 next-level-cache = <&L2_1>; 57 L2_1: l2-cache { 58 compatible = "cache"; 59 cache-level = <2>; 60 }; 61 }; 62 63 CPU1: cpu@101 { 64 device_type = "cpu"; 65 compatible = "arm,cortex-a53"; 66 reg = <0x0 0x101>; 67 enable-method = "psci"; 68 cpu-idle-states = <&PERF_CPU_SLEEP_0 69 &PERF_CPU_SLEEP_1 70 &PERF_CLUSTER_SLEEP_0 71 &PERF_CLUSTER_SLEEP_1 72 &PERF_CLUSTER_SLEEP_2>; 73 capacity-dmips-mhz = <1126>; 74 #cooling-cells = <2>; 75 next-level-cache = <&L2_1>; 76 }; 77 78 CPU2: cpu@102 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a53"; 81 reg = <0x0 0x102>; 82 enable-method = "psci"; 83 cpu-idle-states = <&PERF_CPU_SLEEP_0 84 &PERF_CPU_SLEEP_1 85 &PERF_CLUSTER_SLEEP_0 86 &PERF_CLUSTER_SLEEP_1 87 &PERF_CLUSTER_SLEEP_2>; 88 capacity-dmips-mhz = <1126>; 89 #cooling-cells = <2>; 90 next-level-cache = <&L2_1>; 91 }; 92 93 CPU3: cpu@103 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a53"; 96 reg = <0x0 0x103>; 97 enable-method = "psci"; 98 cpu-idle-states = <&PERF_CPU_SLEEP_0 99 &PERF_CPU_SLEEP_1 100 &PERF_CLUSTER_SLEEP_0 101 &PERF_CLUSTER_SLEEP_1 102 &PERF_CLUSTER_SLEEP_2>; 103 capacity-dmips-mhz = <1126>; 104 #cooling-cells = <2>; 105 next-level-cache = <&L2_1>; 106 }; 107 108 CPU4: cpu@0 { 109 device_type = "cpu"; 110 compatible = "arm,cortex-a53"; 111 reg = <0x0 0x0>; 112 enable-method = "psci"; 113 cpu-idle-states = <&PWR_CPU_SLEEP_0 114 &PWR_CPU_SLEEP_1 115 &PWR_CLUSTER_SLEEP_0 116 &PWR_CLUSTER_SLEEP_1 117 &PWR_CLUSTER_SLEEP_2>; 118 capacity-dmips-mhz = <1024>; 119 #cooling-cells = <2>; 120 next-level-cache = <&L2_0>; 121 L2_0: l2-cache { 122 compatible = "cache"; 123 cache-level = <2>; 124 }; 125 }; 126 127 CPU5: cpu@1 { 128 device_type = "cpu"; 129 compatible = "arm,cortex-a53"; 130 reg = <0x0 0x1>; 131 enable-method = "psci"; 132 cpu-idle-states = <&PWR_CPU_SLEEP_0 133 &PWR_CPU_SLEEP_1 134 &PWR_CLUSTER_SLEEP_0 135 &PWR_CLUSTER_SLEEP_1 136 &PWR_CLUSTER_SLEEP_2>; 137 capacity-dmips-mhz = <1024>; 138 #cooling-cells = <2>; 139 next-level-cache = <&L2_0>; 140 }; 141 142 CPU6: cpu@2 { 143 device_type = "cpu"; 144 compatible = "arm,cortex-a53"; 145 reg = <0x0 0x2>; 146 enable-method = "psci"; 147 cpu-idle-states = <&PWR_CPU_SLEEP_0 148 &PWR_CPU_SLEEP_1 149 &PWR_CLUSTER_SLEEP_0 150 &PWR_CLUSTER_SLEEP_1 151 &PWR_CLUSTER_SLEEP_2>; 152 capacity-dmips-mhz = <1024>; 153 #cooling-cells = <2>; 154 next-level-cache = <&L2_0>; 155 }; 156 157 CPU7: cpu@3 { 158 device_type = "cpu"; 159 compatible = "arm,cortex-a53"; 160 reg = <0x0 0x3>; 161 enable-method = "psci"; 162 cpu-idle-states = <&PWR_CPU_SLEEP_0 163 &PWR_CPU_SLEEP_1 164 &PWR_CLUSTER_SLEEP_0 165 &PWR_CLUSTER_SLEEP_1 166 &PWR_CLUSTER_SLEEP_2>; 167 capacity-dmips-mhz = <1024>; 168 #cooling-cells = <2>; 169 next-level-cache = <&L2_0>; 170 }; 171 172 cpu-map { 173 cluster0 { 174 core0 { 175 cpu = <&CPU4>; 176 }; 177 178 core1 { 179 cpu = <&CPU5>; 180 }; 181 182 core2 { 183 cpu = <&CPU6>; 184 }; 185 186 core3 { 187 cpu = <&CPU7>; 188 }; 189 }; 190 191 cluster1 { 192 core0 { 193 cpu = <&CPU0>; 194 }; 195 196 core1 { 197 cpu = <&CPU1>; 198 }; 199 200 core2 { 201 cpu = <&CPU2>; 202 }; 203 204 core3 { 205 cpu = <&CPU3>; 206 }; 207 }; 208 }; 209 210 idle-states { 211 entry-method = "psci"; 212 213 PWR_CPU_SLEEP_0: cpu-sleep-0-0 { 214 compatible = "arm,idle-state"; 215 idle-state-name = "pwr-retention"; 216 arm,psci-suspend-param = <0x40000002>; 217 entry-latency-us = <338>; 218 exit-latency-us = <423>; 219 min-residency-us = <200>; 220 }; 221 222 PWR_CPU_SLEEP_1: cpu-sleep-0-1 { 223 compatible = "arm,idle-state"; 224 idle-state-name = "pwr-power-collapse"; 225 arm,psci-suspend-param = <0x40000003>; 226 entry-latency-us = <515>; 227 exit-latency-us = <1821>; 228 min-residency-us = <1000>; 229 local-timer-stop; 230 }; 231 232 PERF_CPU_SLEEP_0: cpu-sleep-1-0 { 233 compatible = "arm,idle-state"; 234 idle-state-name = "perf-retention"; 235 arm,psci-suspend-param = <0x40000002>; 236 entry-latency-us = <154>; 237 exit-latency-us = <87>; 238 min-residency-us = <200>; 239 }; 240 241 PERF_CPU_SLEEP_1: cpu-sleep-1-1 { 242 compatible = "arm,idle-state"; 243 idle-state-name = "perf-power-collapse"; 244 arm,psci-suspend-param = <0x40000003>; 245 entry-latency-us = <262>; 246 exit-latency-us = <301>; 247 min-residency-us = <1000>; 248 local-timer-stop; 249 }; 250 251 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 { 252 compatible = "arm,idle-state"; 253 idle-state-name = "pwr-cluster-dynamic-retention"; 254 arm,psci-suspend-param = <0x400000F2>; 255 entry-latency-us = <284>; 256 exit-latency-us = <384>; 257 min-residency-us = <9987>; 258 local-timer-stop; 259 }; 260 261 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 { 262 compatible = "arm,idle-state"; 263 idle-state-name = "pwr-cluster-retention"; 264 arm,psci-suspend-param = <0x400000F3>; 265 entry-latency-us = <338>; 266 exit-latency-us = <423>; 267 min-residency-us = <9987>; 268 local-timer-stop; 269 }; 270 271 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 { 272 compatible = "arm,idle-state"; 273 idle-state-name = "pwr-cluster-retention"; 274 arm,psci-suspend-param = <0x400000F4>; 275 entry-latency-us = <515>; 276 exit-latency-us = <1821>; 277 min-residency-us = <9987>; 278 local-timer-stop; 279 }; 280 281 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 { 282 compatible = "arm,idle-state"; 283 idle-state-name = "perf-cluster-dynamic-retention"; 284 arm,psci-suspend-param = <0x400000F2>; 285 entry-latency-us = <272>; 286 exit-latency-us = <329>; 287 min-residency-us = <9987>; 288 local-timer-stop; 289 }; 290 291 PERF_CLUSTER_SLEEP_1: cluster-sleep-1-1 { 292 compatible = "arm,idle-state"; 293 idle-state-name = "perf-cluster-retention"; 294 arm,psci-suspend-param = <0x400000F3>; 295 entry-latency-us = <332>; 296 exit-latency-us = <368>; 297 min-residency-us = <9987>; 298 local-timer-stop; 299 }; 300 301 PERF_CLUSTER_SLEEP_2: cluster-sleep-1-2 { 302 compatible = "arm,idle-state"; 303 idle-state-name = "perf-cluster-retention"; 304 arm,psci-suspend-param = <0x400000F4>; 305 entry-latency-us = <545>; 306 exit-latency-us = <1609>; 307 min-residency-us = <9987>; 308 local-timer-stop; 309 }; 310 }; 311 }; 312 313 firmware { 314 scm { 315 compatible = "qcom,scm-msm8998", "qcom,scm"; 316 }; 317 }; 318 319 memory@80000000 { 320 device_type = "memory"; 321 /* We expect the bootloader to fill in the reg */ 322 reg = <0x0 0x80000000 0x0 0x0>; 323 }; 324 325 pmu { 326 compatible = "arm,armv8-pmuv3"; 327 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 328 }; 329 330 psci { 331 compatible = "arm,psci-1.0"; 332 method = "smc"; 333 }; 334 335 reserved-memory { 336 #address-cells = <2>; 337 #size-cells = <2>; 338 ranges; 339 340 wlan_msa_guard: wlan-msa-guard@85600000 { 341 reg = <0x0 0x85600000 0x0 0x100000>; 342 no-map; 343 }; 344 345 wlan_msa_mem: wlan-msa-mem@85700000 { 346 reg = <0x0 0x85700000 0x0 0x100000>; 347 no-map; 348 }; 349 350 qhee_code: qhee-code@85800000 { 351 reg = <0x0 0x85800000 0x0 0x600000>; 352 no-map; 353 }; 354 355 rmtfs_mem: memory@85e00000 { 356 compatible = "qcom,rmtfs-mem"; 357 reg = <0x0 0x85e00000 0x0 0x200000>; 358 no-map; 359 360 qcom,client-id = <1>; 361 qcom,vmid = <15>; 362 }; 363 364 smem_region: smem-mem@86000000 { 365 reg = <0 0x86000000 0 0x200000>; 366 no-map; 367 }; 368 369 tz_mem: memory@86200000 { 370 reg = <0x0 0x86200000 0x0 0x3300000>; 371 no-map; 372 }; 373 374 mpss_region: mpss@8ac00000 { 375 reg = <0x0 0x8ac00000 0x0 0x7e00000>; 376 no-map; 377 }; 378 379 adsp_region: adsp@92a00000 { 380 reg = <0x0 0x92a00000 0x0 0x1e00000>; 381 no-map; 382 }; 383 384 mba_region: mba@94800000 { 385 reg = <0x0 0x94800000 0x0 0x200000>; 386 no-map; 387 }; 388 389 buffer_mem: tzbuffer@94a00000 { 390 reg = <0x0 0x94a00000 0x0 0x100000>; 391 no-map; 392 }; 393 394 venus_region: venus@9f800000 { 395 reg = <0x0 0x9f800000 0x0 0x800000>; 396 no-map; 397 }; 398 399 adsp_mem: adsp-region@f6000000 { 400 reg = <0x0 0xf6000000 0x0 0x800000>; 401 no-map; 402 }; 403 404 qseecom_mem: qseecom-region@f6800000 { 405 reg = <0x0 0xf6800000 0x0 0x1400000>; 406 no-map; 407 }; 408 409 zap_shader_region: gpu@fed00000 { 410 compatible = "shared-dma-pool"; 411 reg = <0x0 0xfed00000 0x0 0xa00000>; 412 no-map; 413 }; 414 }; 415 416 rpm-glink { 417 compatible = "qcom,glink-rpm"; 418 419 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 420 qcom,rpm-msg-ram = <&rpm_msg_ram>; 421 mboxes = <&apcs_glb 0>; 422 423 rpm_requests: rpm-requests { 424 compatible = "qcom,rpm-sdm660"; 425 qcom,glink-channels = "rpm_requests"; 426 427 rpmcc: clock-controller { 428 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc"; 429 #clock-cells = <1>; 430 }; 431 432 rpmpd: power-controller { 433 compatible = "qcom,sdm660-rpmpd"; 434 #power-domain-cells = <1>; 435 operating-points-v2 = <&rpmpd_opp_table>; 436 437 rpmpd_opp_table: opp-table { 438 compatible = "operating-points-v2"; 439 440 rpmpd_opp_ret: opp1 { 441 opp-level = <RPM_SMD_LEVEL_RETENTION>; 442 }; 443 444 rpmpd_opp_ret_plus: opp2 { 445 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 446 }; 447 448 rpmpd_opp_min_svs: opp3 { 449 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 450 }; 451 452 rpmpd_opp_low_svs: opp4 { 453 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 454 }; 455 456 rpmpd_opp_svs: opp5 { 457 opp-level = <RPM_SMD_LEVEL_SVS>; 458 }; 459 460 rpmpd_opp_svs_plus: opp6 { 461 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 462 }; 463 464 rpmpd_opp_nom: opp7 { 465 opp-level = <RPM_SMD_LEVEL_NOM>; 466 }; 467 468 rpmpd_opp_nom_plus: opp8 { 469 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 470 }; 471 472 rpmpd_opp_turbo: opp9 { 473 opp-level = <RPM_SMD_LEVEL_TURBO>; 474 }; 475 }; 476 }; 477 }; 478 }; 479 480 smem: smem { 481 compatible = "qcom,smem"; 482 memory-region = <&smem_region>; 483 hwlocks = <&tcsr_mutex 3>; 484 }; 485 486 smp2p-adsp { 487 compatible = "qcom,smp2p"; 488 qcom,smem = <443>, <429>; 489 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 490 mboxes = <&apcs_glb 10>; 491 qcom,local-pid = <0>; 492 qcom,remote-pid = <2>; 493 494 adsp_smp2p_out: master-kernel { 495 qcom,entry-name = "master-kernel"; 496 #qcom,smem-state-cells = <1>; 497 }; 498 499 adsp_smp2p_in: slave-kernel { 500 qcom,entry-name = "slave-kernel"; 501 interrupt-controller; 502 #interrupt-cells = <2>; 503 }; 504 }; 505 506 smp2p-mpss { 507 compatible = "qcom,smp2p"; 508 qcom,smem = <435>, <428>; 509 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 510 mboxes = <&apcs_glb 14>; 511 qcom,local-pid = <0>; 512 qcom,remote-pid = <1>; 513 514 modem_smp2p_out: master-kernel { 515 qcom,entry-name = "master-kernel"; 516 #qcom,smem-state-cells = <1>; 517 }; 518 519 modem_smp2p_in: slave-kernel { 520 qcom,entry-name = "slave-kernel"; 521 interrupt-controller; 522 #interrupt-cells = <2>; 523 }; 524 }; 525 526 soc { 527 #address-cells = <1>; 528 #size-cells = <1>; 529 ranges = <0 0 0 0xffffffff>; 530 compatible = "simple-bus"; 531 532 gcc: clock-controller@100000 { 533 compatible = "qcom,gcc-sdm630"; 534 #clock-cells = <1>; 535 #reset-cells = <1>; 536 #power-domain-cells = <1>; 537 reg = <0x00100000 0x94000>; 538 539 clock-names = "xo", "sleep_clk"; 540 clocks = <&xo_board>, 541 <&sleep_clk>; 542 }; 543 544 rpm_msg_ram: sram@778000 { 545 compatible = "qcom,rpm-msg-ram"; 546 reg = <0x00778000 0x7000>; 547 }; 548 549 qfprom: qfprom@780000 { 550 compatible = "qcom,qfprom"; 551 reg = <0x00780000 0x621c>; 552 #address-cells = <1>; 553 #size-cells = <1>; 554 555 qusb2_hstx_trim: hstx-trim@240 { 556 reg = <0x240 0x1>; 557 bits = <25 3>; 558 }; 559 560 gpu_speed_bin: gpu-speed-bin@41a0 { 561 reg = <0x41a0 0x1>; 562 bits = <21 7>; 563 }; 564 }; 565 566 rng: rng@793000 { 567 compatible = "qcom,prng-ee"; 568 reg = <0x00793000 0x1000>; 569 clocks = <&gcc GCC_PRNG_AHB_CLK>; 570 clock-names = "core"; 571 }; 572 573 bimc: interconnect@1008000 { 574 compatible = "qcom,sdm660-bimc"; 575 reg = <0x01008000 0x78000>; 576 #interconnect-cells = <1>; 577 clock-names = "bus", "bus_a"; 578 clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 579 <&rpmcc RPM_SMD_BIMC_A_CLK>; 580 }; 581 582 restart@10ac000 { 583 compatible = "qcom,pshold"; 584 reg = <0x010ac000 0x4>; 585 }; 586 587 cnoc: interconnect@1500000 { 588 compatible = "qcom,sdm660-cnoc"; 589 reg = <0x01500000 0x10000>; 590 #interconnect-cells = <1>; 591 clock-names = "bus", "bus_a"; 592 clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 593 <&rpmcc RPM_SMD_CNOC_A_CLK>; 594 }; 595 596 snoc: interconnect@1626000 { 597 compatible = "qcom,sdm660-snoc"; 598 reg = <0x01626000 0x7090>; 599 #interconnect-cells = <1>; 600 clock-names = "bus", "bus_a"; 601 clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 602 <&rpmcc RPM_SMD_SNOC_A_CLK>; 603 }; 604 605 anoc2_smmu: iommu@16c0000 { 606 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 607 reg = <0x016c0000 0x40000>; 608 609 assigned-clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 610 assigned-clock-rates = <1000>; 611 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 612 clock-names = "bus"; 613 #global-interrupts = <2>; 614 #iommu-cells = <1>; 615 616 interrupts = 617 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 619 620 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 374 IRQ_TYPE_LEVEL_LOW>, 622 <GIC_SPI 375 IRQ_TYPE_LEVEL_LOW>, 623 <GIC_SPI 376 IRQ_TYPE_LEVEL_LOW>, 624 <GIC_SPI 377 IRQ_TYPE_LEVEL_LOW>, 625 <GIC_SPI 378 IRQ_TYPE_LEVEL_LOW>, 626 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 628 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 631 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 632 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 649 650 status = "disabled"; 651 }; 652 653 a2noc: interconnect@1704000 { 654 compatible = "qcom,sdm660-a2noc"; 655 reg = <0x01704000 0xc100>; 656 #interconnect-cells = <1>; 657 clock-names = "bus", 658 "bus_a", 659 "ipa", 660 "ufs_axi", 661 "aggre2_ufs_axi", 662 "aggre2_usb3_axi", 663 "cfg_noc_usb2_axi"; 664 clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, 665 <&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>, 666 <&rpmcc RPM_SMD_IPA_CLK>, 667 <&gcc GCC_UFS_AXI_CLK>, 668 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 669 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 670 <&gcc GCC_CFG_NOC_USB2_AXI_CLK>; 671 }; 672 673 mnoc: interconnect@1745000 { 674 compatible = "qcom,sdm660-mnoc"; 675 reg = <0x01745000 0xA010>; 676 #interconnect-cells = <1>; 677 clock-names = "bus", "bus_a", "iface"; 678 clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>, 679 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>, 680 <&mmcc AHB_CLK_SRC>; 681 }; 682 683 tsens: thermal-sensor@10ae000 { 684 compatible = "qcom,sdm630-tsens", "qcom,tsens-v2"; 685 reg = <0x010ae000 0x1000>, /* TM */ 686 <0x010ad000 0x1000>; /* SROT */ 687 #qcom,sensors = <12>; 688 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 690 interrupt-names = "uplow", "critical"; 691 #thermal-sensor-cells = <1>; 692 }; 693 694 tcsr_mutex_regs: syscon@1f40000 { 695 compatible = "syscon"; 696 reg = <0x01f40000 0x40000>; 697 }; 698 699 tlmm: pinctrl@3100000 { 700 compatible = "qcom,sdm630-pinctrl"; 701 reg = <0x03100000 0x400000>, 702 <0x03500000 0x400000>, 703 <0x03900000 0x400000>; 704 reg-names = "south", "center", "north"; 705 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 706 gpio-controller; 707 gpio-ranges = <&tlmm 0 0 114>; 708 #gpio-cells = <2>; 709 interrupt-controller; 710 #interrupt-cells = <2>; 711 712 blsp1_uart1_default: blsp1-uart1-default { 713 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 714 drive-strength = <2>; 715 bias-disable; 716 }; 717 718 blsp1_uart1_sleep: blsp1-uart1-sleep { 719 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 720 drive-strength = <2>; 721 bias-disable; 722 }; 723 724 blsp1_uart2_default: blsp1-uart2-default { 725 pins = "gpio4", "gpio5"; 726 drive-strength = <2>; 727 bias-disable; 728 }; 729 730 blsp2_uart1_default: blsp2-uart1-active { 731 tx-rts { 732 pins = "gpio16", "gpio19"; 733 function = "blsp_uart5"; 734 drive-strength = <2>; 735 bias-disable; 736 }; 737 738 rx { 739 /* 740 * Avoid garbage data while BT module 741 * is powered off or not driving signal 742 */ 743 pins = "gpio17"; 744 function = "blsp_uart5"; 745 drive-strength = <2>; 746 bias-pull-up; 747 }; 748 749 cts { 750 /* Match the pull of the BT module */ 751 pins = "gpio18"; 752 function = "blsp_uart5"; 753 drive-strength = <2>; 754 bias-pull-down; 755 }; 756 }; 757 758 blsp2_uart1_sleep: blsp2-uart1-sleep { 759 tx { 760 pins = "gpio16"; 761 function = "gpio"; 762 drive-strength = <2>; 763 bias-pull-up; 764 }; 765 766 rx-cts-rts { 767 pins = "gpio17", "gpio18", "gpio19"; 768 function = "gpio"; 769 drive-strength = <2>; 770 bias-no-pull; 771 }; 772 }; 773 774 i2c1_default: i2c1-default { 775 pins = "gpio2", "gpio3"; 776 function = "blsp_i2c1"; 777 drive-strength = <2>; 778 bias-disable; 779 }; 780 781 i2c1_sleep: i2c1-sleep { 782 pins = "gpio2", "gpio3"; 783 function = "blsp_i2c1"; 784 drive-strength = <2>; 785 bias-pull-up; 786 }; 787 788 i2c2_default: i2c2-default { 789 pins = "gpio6", "gpio7"; 790 function = "blsp_i2c2"; 791 drive-strength = <2>; 792 bias-disable; 793 }; 794 795 i2c2_sleep: i2c2-sleep { 796 pins = "gpio6", "gpio7"; 797 function = "blsp_i2c2"; 798 drive-strength = <2>; 799 bias-pull-up; 800 }; 801 802 i2c3_default: i2c3-default { 803 pins = "gpio10", "gpio11"; 804 function = "blsp_i2c3"; 805 drive-strength = <2>; 806 bias-disable; 807 }; 808 809 i2c3_sleep: i2c3-sleep { 810 pins = "gpio10", "gpio11"; 811 function = "blsp_i2c3"; 812 drive-strength = <2>; 813 bias-pull-up; 814 }; 815 816 i2c4_default: i2c4-default { 817 pins = "gpio14", "gpio15"; 818 function = "blsp_i2c4"; 819 drive-strength = <2>; 820 bias-disable; 821 }; 822 823 i2c4_sleep: i2c4-sleep { 824 pins = "gpio14", "gpio15"; 825 function = "blsp_i2c4"; 826 drive-strength = <2>; 827 bias-pull-up; 828 }; 829 830 i2c5_default: i2c5-default { 831 pins = "gpio18", "gpio19"; 832 function = "blsp_i2c5"; 833 drive-strength = <2>; 834 bias-disable; 835 }; 836 837 i2c5_sleep: i2c5-sleep { 838 pins = "gpio18", "gpio19"; 839 function = "blsp_i2c5"; 840 drive-strength = <2>; 841 bias-pull-up; 842 }; 843 844 i2c6_default: i2c6-default { 845 pins = "gpio22", "gpio23"; 846 function = "blsp_i2c6"; 847 drive-strength = <2>; 848 bias-disable; 849 }; 850 851 i2c6_sleep: i2c6-sleep { 852 pins = "gpio22", "gpio23"; 853 function = "blsp_i2c6"; 854 drive-strength = <2>; 855 bias-pull-up; 856 }; 857 858 i2c7_default: i2c7-default { 859 pins = "gpio26", "gpio27"; 860 function = "blsp_i2c7"; 861 drive-strength = <2>; 862 bias-disable; 863 }; 864 865 i2c7_sleep: i2c7-sleep { 866 pins = "gpio26", "gpio27"; 867 function = "blsp_i2c7"; 868 drive-strength = <2>; 869 bias-pull-up; 870 }; 871 872 i2c8_default: i2c8-default { 873 pins = "gpio30", "gpio31"; 874 function = "blsp_i2c8"; 875 drive-strength = <2>; 876 bias-disable; 877 }; 878 879 i2c8_sleep: i2c8-sleep { 880 pins = "gpio30", "gpio31"; 881 function = "blsp_i2c8"; 882 drive-strength = <2>; 883 bias-pull-up; 884 }; 885 886 cci0_default: cci0_default { 887 pinmux { 888 pins = "gpio36","gpio37"; 889 function = "cci_i2c"; 890 }; 891 892 pinconf { 893 pins = "gpio36","gpio37"; 894 bias-pull-up; 895 drive-strength = <2>; 896 }; 897 }; 898 899 cci1_default: cci1_default { 900 pinmux { 901 pins = "gpio38","gpio39"; 902 function = "cci_i2c"; 903 }; 904 905 pinconf { 906 pins = "gpio38","gpio39"; 907 bias-pull-up; 908 drive-strength = <2>; 909 }; 910 }; 911 912 sdc1_state_on: sdc1-on { 913 clk { 914 pins = "sdc1_clk"; 915 bias-disable; 916 drive-strength = <16>; 917 }; 918 919 cmd { 920 pins = "sdc1_cmd"; 921 bias-pull-up; 922 drive-strength = <10>; 923 }; 924 925 data { 926 pins = "sdc1_data"; 927 bias-pull-up; 928 drive-strength = <10>; 929 }; 930 931 rclk { 932 pins = "sdc1_rclk"; 933 bias-pull-down; 934 }; 935 }; 936 937 sdc1_state_off: sdc1-off { 938 clk { 939 pins = "sdc1_clk"; 940 bias-disable; 941 drive-strength = <2>; 942 }; 943 944 cmd { 945 pins = "sdc1_cmd"; 946 bias-pull-up; 947 drive-strength = <2>; 948 }; 949 950 data { 951 pins = "sdc1_data"; 952 bias-pull-up; 953 drive-strength = <2>; 954 }; 955 956 rclk { 957 pins = "sdc1_rclk"; 958 bias-pull-down; 959 }; 960 }; 961 962 sdc2_state_on: sdc2-on { 963 clk { 964 pins = "sdc2_clk"; 965 bias-disable; 966 drive-strength = <16>; 967 }; 968 969 cmd { 970 pins = "sdc2_cmd"; 971 bias-pull-up; 972 drive-strength = <10>; 973 }; 974 975 data { 976 pins = "sdc2_data"; 977 bias-pull-up; 978 drive-strength = <10>; 979 }; 980 981 sd-cd { 982 pins = "gpio54"; 983 bias-pull-up; 984 drive-strength = <2>; 985 }; 986 }; 987 988 sdc2_state_off: sdc2-off { 989 clk { 990 pins = "sdc2_clk"; 991 bias-disable; 992 drive-strength = <2>; 993 }; 994 995 cmd { 996 pins = "sdc2_cmd"; 997 bias-pull-up; 998 drive-strength = <2>; 999 }; 1000 1001 data { 1002 pins = "sdc2_data"; 1003 bias-pull-up; 1004 drive-strength = <2>; 1005 }; 1006 1007 sd-cd { 1008 pins = "gpio54"; 1009 bias-disable; 1010 drive-strength = <2>; 1011 }; 1012 }; 1013 }; 1014 1015 adreno_gpu: gpu@5000000 { 1016 compatible = "qcom,adreno-508.0", "qcom,adreno"; 1017 #stream-id-cells = <16>; 1018 1019 reg = <0x05000000 0x40000>; 1020 reg-names = "kgsl_3d0_reg_memory"; 1021 1022 interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; 1023 1024 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1025 <&gpucc GPUCC_RBBMTIMER_CLK>, 1026 <&gcc GCC_BIMC_GFX_CLK>, 1027 <&gcc GCC_GPU_BIMC_GFX_CLK>, 1028 <&gpucc GPUCC_RBCPR_CLK>, 1029 <&gpucc GPUCC_GFX3D_CLK>; 1030 1031 clock-names = "iface", 1032 "rbbmtimer", 1033 "mem", 1034 "mem_iface", 1035 "rbcpr", 1036 "core"; 1037 1038 power-domains = <&rpmpd SDM660_VDDMX>; 1039 iommus = <&kgsl_smmu 0>; 1040 1041 nvmem-cells = <&gpu_speed_bin>; 1042 nvmem-cell-names = "speed_bin"; 1043 1044 interconnects = <&gnoc 1 &bimc 5>; 1045 interconnect-names = "gfx-mem"; 1046 1047 operating-points-v2 = <&gpu_sdm630_opp_table>; 1048 1049 gpu_sdm630_opp_table: opp-table { 1050 compatible = "operating-points-v2"; 1051 opp-775000000 { 1052 opp-hz = /bits/ 64 <775000000>; 1053 opp-level = <RPM_SMD_LEVEL_TURBO>; 1054 opp-peak-kBps = <5412000>; 1055 opp-supported-hw = <0xA2>; 1056 }; 1057 opp-647000000 { 1058 opp-hz = /bits/ 64 <647000000>; 1059 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 1060 opp-peak-kBps = <4068000>; 1061 opp-supported-hw = <0xFF>; 1062 }; 1063 opp-588000000 { 1064 opp-hz = /bits/ 64 <588000000>; 1065 opp-level = <RPM_SMD_LEVEL_NOM>; 1066 opp-peak-kBps = <3072000>; 1067 opp-supported-hw = <0xFF>; 1068 }; 1069 opp-465000000 { 1070 opp-hz = /bits/ 64 <465000000>; 1071 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 1072 opp-peak-kBps = <2724000>; 1073 opp-supported-hw = <0xFF>; 1074 }; 1075 opp-370000000 { 1076 opp-hz = /bits/ 64 <370000000>; 1077 opp-level = <RPM_SMD_LEVEL_SVS>; 1078 opp-peak-kBps = <2188000>; 1079 opp-supported-hw = <0xFF>; 1080 }; 1081 opp-240000000 { 1082 opp-hz = /bits/ 64 <240000000>; 1083 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 1084 opp-peak-kBps = <1648000>; 1085 opp-supported-hw = <0xFF>; 1086 }; 1087 opp-160000000 { 1088 opp-hz = /bits/ 64 <160000000>; 1089 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 1090 opp-peak-kBps = <1200000>; 1091 opp-supported-hw = <0xFF>; 1092 }; 1093 }; 1094 }; 1095 1096 kgsl_smmu: iommu@5040000 { 1097 compatible = "qcom,sdm630-smmu-v2", 1098 "qcom,adreno-smmu", "qcom,smmu-v2"; 1099 reg = <0x05040000 0x10000>; 1100 1101 /* 1102 * GX GDSC parent is CX. We need to bring up CX for SMMU 1103 * but we need both up for Adreno. On the other hand, we 1104 * need to manage the GX rpmpd domain in the adreno driver. 1105 * Enable CX/GX GDSCs here so that we can manage just the GX 1106 * RPM Power Domain in the Adreno driver. 1107 */ 1108 power-domains = <&gpucc GPU_GX_GDSC>; 1109 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1110 <&gcc GCC_BIMC_GFX_CLK>, 1111 <&gcc GCC_GPU_BIMC_GFX_CLK>; 1112 clock-names = "iface", "mem", "mem_iface"; 1113 #global-interrupts = <2>; 1114 #iommu-cells = <1>; 1115 1116 interrupts = 1117 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1119 1120 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1125 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>; 1128 1129 status = "disabled"; 1130 }; 1131 1132 gpucc: clock-controller@5065000 { 1133 compatible = "qcom,gpucc-sdm630"; 1134 #clock-cells = <1>; 1135 #reset-cells = <1>; 1136 #power-domain-cells = <1>; 1137 reg = <0x05065000 0x9038>; 1138 1139 clocks = <&xo_board>, 1140 <&gcc GCC_GPU_GPLL0_CLK>, 1141 <&gcc GCC_GPU_GPLL0_DIV_CLK>; 1142 clock-names = "xo", 1143 "gcc_gpu_gpll0_clk", 1144 "gcc_gpu_gpll0_div_clk"; 1145 status = "disabled"; 1146 }; 1147 1148 lpass_smmu: iommu@5100000 { 1149 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 1150 reg = <0x05100000 0x40000>; 1151 #iommu-cells = <1>; 1152 1153 #global-interrupts = <2>; 1154 interrupts = 1155 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1156 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1157 1158 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1169 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 1174 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 1175 1176 status = "disabled"; 1177 }; 1178 1179 sram@290000 { 1180 compatible = "qcom,rpm-stats"; 1181 reg = <0x00290000 0x10000>; 1182 }; 1183 1184 spmi_bus: spmi@800f000 { 1185 compatible = "qcom,spmi-pmic-arb"; 1186 reg = <0x0800f000 0x1000>, 1187 <0x08400000 0x1000000>, 1188 <0x09400000 0x1000000>, 1189 <0x0a400000 0x220000>, 1190 <0x0800a000 0x3000>; 1191 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1192 interrupt-names = "periph_irq"; 1193 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1194 qcom,ee = <0>; 1195 qcom,channel = <0>; 1196 #address-cells = <2>; 1197 #size-cells = <0>; 1198 interrupt-controller; 1199 #interrupt-cells = <4>; 1200 cell-index = <0>; 1201 }; 1202 1203 usb3: usb@a8f8800 { 1204 compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; 1205 reg = <0x0a8f8800 0x400>; 1206 status = "disabled"; 1207 #address-cells = <1>; 1208 #size-cells = <1>; 1209 ranges; 1210 1211 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 1212 <&gcc GCC_USB30_MASTER_CLK>, 1213 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 1214 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>, 1215 <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1216 <&gcc GCC_USB30_SLEEP_CLK>; 1217 clock-names = "cfg_noc", "core", "iface", "bus", 1218 "mock_utmi", "sleep"; 1219 1220 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1221 <&gcc GCC_USB30_MASTER_CLK>, 1222 <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; 1223 assigned-clock-rates = <19200000>, <120000000>, 1224 <19200000>; 1225 1226 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1228 interrupt-names = "hs_phy_irq", "ss_phy_irq"; 1229 1230 power-domains = <&gcc USB_30_GDSC>; 1231 qcom,select-utmi-as-pipe-clk; 1232 1233 resets = <&gcc GCC_USB_30_BCR>; 1234 1235 usb3_dwc3: usb@a800000 { 1236 compatible = "snps,dwc3"; 1237 reg = <0x0a800000 0xc8d0>; 1238 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1239 snps,dis_u2_susphy_quirk; 1240 snps,dis_enblslpm_quirk; 1241 1242 /* 1243 * SDM630 technically supports USB3 but I 1244 * haven't seen any devices making use of it. 1245 */ 1246 maximum-speed = "high-speed"; 1247 phys = <&qusb2phy>; 1248 phy-names = "usb2-phy"; 1249 snps,hird-threshold = /bits/ 8 <0>; 1250 }; 1251 }; 1252 1253 qusb2phy: phy@c012000 { 1254 compatible = "qcom,sdm660-qusb2-phy"; 1255 reg = <0x0c012000 0x180>; 1256 #phy-cells = <0>; 1257 1258 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1259 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 1260 clock-names = "cfg_ahb", "ref"; 1261 1262 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1263 nvmem-cells = <&qusb2_hstx_trim>; 1264 status = "disabled"; 1265 }; 1266 1267 sdhc_2: sdhci@c084000 { 1268 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 1269 reg = <0x0c084000 0x1000>; 1270 reg-names = "hc"; 1271 1272 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1274 interrupt-names = "hc_irq", "pwr_irq"; 1275 1276 bus-width = <4>; 1277 clocks = <&gcc GCC_SDCC2_APPS_CLK>, 1278 <&gcc GCC_SDCC2_AHB_CLK>, 1279 <&xo_board>; 1280 clock-names = "core", "iface", "xo"; 1281 1282 interconnects = <&a2noc 3 &a2noc 10>, 1283 <&gnoc 0 &cnoc 28>; 1284 operating-points-v2 = <&sdhc2_opp_table>; 1285 1286 pinctrl-names = "default", "sleep"; 1287 pinctrl-0 = <&sdc2_state_on>; 1288 pinctrl-1 = <&sdc2_state_off>; 1289 power-domains = <&rpmpd SDM660_VDDCX>; 1290 1291 status = "disabled"; 1292 1293 sdhc2_opp_table: opp-table { 1294 compatible = "operating-points-v2"; 1295 1296 opp-50000000 { 1297 opp-hz = /bits/ 64 <50000000>; 1298 required-opps = <&rpmpd_opp_low_svs>; 1299 opp-peak-kBps = <200000 140000>; 1300 opp-avg-kBps = <130718 133320>; 1301 }; 1302 opp-100000000 { 1303 opp-hz = /bits/ 64 <100000000>; 1304 required-opps = <&rpmpd_opp_svs>; 1305 opp-peak-kBps = <250000 160000>; 1306 opp-avg-kBps = <196078 150000>; 1307 }; 1308 opp-200000000 { 1309 opp-hz = /bits/ 64 <200000000>; 1310 required-opps = <&rpmpd_opp_nom>; 1311 opp-peak-kBps = <4096000 4096000>; 1312 opp-avg-kBps = <1338562 1338562>; 1313 }; 1314 }; 1315 }; 1316 1317 sdhc_1: sdhci@c0c4000 { 1318 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 1319 reg = <0x0c0c4000 0x1000>, 1320 <0x0c0c5000 0x1000>, 1321 <0x0c0c8000 0x8000>; 1322 reg-names = "hc", "cqhci", "ice"; 1323 1324 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1325 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1326 interrupt-names = "hc_irq", "pwr_irq"; 1327 1328 clocks = <&gcc GCC_SDCC1_APPS_CLK>, 1329 <&gcc GCC_SDCC1_AHB_CLK>, 1330 <&xo_board>, 1331 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 1332 clock-names = "core", "iface", "xo", "ice"; 1333 1334 interconnects = <&a2noc 2 &a2noc 10>, 1335 <&gnoc 0 &cnoc 27>; 1336 interconnect-names = "sdhc1-ddr", "cpu-sdhc1"; 1337 operating-points-v2 = <&sdhc1_opp_table>; 1338 pinctrl-names = "default", "sleep"; 1339 pinctrl-0 = <&sdc1_state_on>; 1340 pinctrl-1 = <&sdc1_state_off>; 1341 power-domains = <&rpmpd SDM660_VDDCX>; 1342 1343 bus-width = <8>; 1344 non-removable; 1345 1346 status = "disabled"; 1347 1348 sdhc1_opp_table: opp-table { 1349 compatible = "operating-points-v2"; 1350 1351 opp-50000000 { 1352 opp-hz = /bits/ 64 <50000000>; 1353 required-opps = <&rpmpd_opp_low_svs>; 1354 opp-peak-kBps = <200000 140000>; 1355 opp-avg-kBps = <130718 133320>; 1356 }; 1357 opp-100000000 { 1358 opp-hz = /bits/ 64 <100000000>; 1359 required-opps = <&rpmpd_opp_svs>; 1360 opp-peak-kBps = <250000 160000>; 1361 opp-avg-kBps = <196078 150000>; 1362 }; 1363 opp-384000000 { 1364 opp-hz = /bits/ 64 <384000000>; 1365 required-opps = <&rpmpd_opp_nom>; 1366 opp-peak-kBps = <4096000 4096000>; 1367 opp-avg-kBps = <1338562 1338562>; 1368 }; 1369 }; 1370 }; 1371 1372 mmcc: clock-controller@c8c0000 { 1373 compatible = "qcom,mmcc-sdm630"; 1374 reg = <0x0c8c0000 0x40000>; 1375 #clock-cells = <1>; 1376 #reset-cells = <1>; 1377 #power-domain-cells = <1>; 1378 clock-names = "xo", 1379 "sleep_clk", 1380 "gpll0", 1381 "gpll0_div", 1382 "dsi0pll", 1383 "dsi0pllbyte", 1384 "dsi1pll", 1385 "dsi1pllbyte", 1386 "dp_link_2x_clk_divsel_five", 1387 "dp_vco_divided_clk_src_mux"; 1388 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1389 <&sleep_clk>, 1390 <&gcc GCC_MMSS_GPLL0_CLK>, 1391 <&gcc GCC_MMSS_GPLL0_DIV_CLK>, 1392 <&dsi0_phy 1>, 1393 <&dsi0_phy 0>, 1394 <0>, 1395 <0>, 1396 <0>, 1397 <0>; 1398 }; 1399 1400 dsi_opp_table: dsi-opp-table { 1401 compatible = "operating-points-v2"; 1402 1403 opp-131250000 { 1404 opp-hz = /bits/ 64 <131250000>; 1405 required-opps = <&rpmpd_opp_svs>; 1406 }; 1407 1408 opp-210000000 { 1409 opp-hz = /bits/ 64 <210000000>; 1410 required-opps = <&rpmpd_opp_svs_plus>; 1411 }; 1412 1413 opp-262500000 { 1414 opp-hz = /bits/ 64 <262500000>; 1415 required-opps = <&rpmpd_opp_nom>; 1416 }; 1417 }; 1418 1419 mdss: mdss@c900000 { 1420 compatible = "qcom,mdss"; 1421 reg = <0x0c900000 0x1000>, 1422 <0x0c9b0000 0x1040>; 1423 reg-names = "mdss_phys", "vbif_phys"; 1424 1425 power-domains = <&mmcc MDSS_GDSC>; 1426 1427 clocks = <&mmcc MDSS_AHB_CLK>, 1428 <&mmcc MDSS_AXI_CLK>, 1429 <&mmcc MDSS_VSYNC_CLK>, 1430 <&mmcc MDSS_MDP_CLK>; 1431 clock-names = "iface", 1432 "bus", 1433 "vsync", 1434 "core"; 1435 1436 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1437 1438 interrupt-controller; 1439 #interrupt-cells = <1>; 1440 1441 #address-cells = <1>; 1442 #size-cells = <1>; 1443 ranges; 1444 status = "disabled"; 1445 1446 mdp: mdp@c901000 { 1447 compatible = "qcom,mdp5"; 1448 reg = <0x0c901000 0x89000>; 1449 reg-names = "mdp_phys"; 1450 1451 interrupt-parent = <&mdss>; 1452 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 1453 1454 assigned-clocks = <&mmcc MDSS_MDP_CLK>, 1455 <&mmcc MDSS_VSYNC_CLK>; 1456 assigned-clock-rates = <300000000>, 1457 <19200000>; 1458 clocks = <&mmcc MDSS_AHB_CLK>, 1459 <&mmcc MDSS_AXI_CLK>, 1460 <&mmcc MDSS_MDP_CLK>, 1461 <&mmcc MDSS_VSYNC_CLK>; 1462 clock-names = "iface", 1463 "bus", 1464 "core", 1465 "vsync"; 1466 1467 interconnects = <&mnoc 2 &bimc 5>, 1468 <&mnoc 3 &bimc 5>, 1469 <&gnoc 0 &mnoc 17>; 1470 interconnect-names = "mdp0-mem", 1471 "mdp1-mem", 1472 "rotator-mem"; 1473 iommus = <&mmss_smmu 0>; 1474 operating-points-v2 = <&mdp_opp_table>; 1475 power-domains = <&rpmpd SDM660_VDDCX>; 1476 1477 ports { 1478 #address-cells = <1>; 1479 #size-cells = <0>; 1480 1481 port@0 { 1482 reg = <0>; 1483 mdp5_intf1_out: endpoint { 1484 remote-endpoint = <&dsi0_in>; 1485 }; 1486 }; 1487 }; 1488 1489 mdp_opp_table: mdp-opp { 1490 compatible = "operating-points-v2"; 1491 1492 opp-150000000 { 1493 opp-hz = /bits/ 64 <150000000>; 1494 opp-peak-kBps = <320000 320000 76800>; 1495 required-opps = <&rpmpd_opp_low_svs>; 1496 }; 1497 opp-275000000 { 1498 opp-hz = /bits/ 64 <275000000>; 1499 opp-peak-kBps = <6400000 6400000 160000>; 1500 required-opps = <&rpmpd_opp_svs>; 1501 }; 1502 opp-300000000 { 1503 opp-hz = /bits/ 64 <300000000>; 1504 opp-peak-kBps = <6400000 6400000 190000>; 1505 required-opps = <&rpmpd_opp_svs_plus>; 1506 }; 1507 opp-330000000 { 1508 opp-hz = /bits/ 64 <330000000>; 1509 opp-peak-kBps = <6400000 6400000 240000>; 1510 required-opps = <&rpmpd_opp_nom>; 1511 }; 1512 opp-412500000 { 1513 opp-hz = /bits/ 64 <412500000>; 1514 opp-peak-kBps = <6400000 6400000 320000>; 1515 required-opps = <&rpmpd_opp_turbo>; 1516 }; 1517 }; 1518 }; 1519 1520 dsi0: dsi@c994000 { 1521 compatible = "qcom,mdss-dsi-ctrl"; 1522 reg = <0x0c994000 0x400>; 1523 reg-names = "dsi_ctrl"; 1524 1525 operating-points-v2 = <&dsi_opp_table>; 1526 power-domains = <&rpmpd SDM660_VDDCX>; 1527 1528 interrupt-parent = <&mdss>; 1529 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 1530 1531 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 1532 <&mmcc PCLK0_CLK_SRC>; 1533 assigned-clock-parents = <&dsi0_phy 0>, 1534 <&dsi0_phy 1>; 1535 1536 clocks = <&mmcc MDSS_MDP_CLK>, 1537 <&mmcc MDSS_BYTE0_CLK>, 1538 <&mmcc MDSS_BYTE0_INTF_CLK>, 1539 <&mmcc MNOC_AHB_CLK>, 1540 <&mmcc MDSS_AHB_CLK>, 1541 <&mmcc MDSS_AXI_CLK>, 1542 <&mmcc MISC_AHB_CLK>, 1543 <&mmcc MDSS_PCLK0_CLK>, 1544 <&mmcc MDSS_ESC0_CLK>; 1545 clock-names = "mdp_core", 1546 "byte", 1547 "byte_intf", 1548 "mnoc", 1549 "iface", 1550 "bus", 1551 "core_mmss", 1552 "pixel", 1553 "core"; 1554 1555 phys = <&dsi0_phy>; 1556 phy-names = "dsi"; 1557 1558 ports { 1559 #address-cells = <1>; 1560 #size-cells = <0>; 1561 1562 port@0 { 1563 reg = <0>; 1564 dsi0_in: endpoint { 1565 remote-endpoint = <&mdp5_intf1_out>; 1566 }; 1567 }; 1568 1569 port@1 { 1570 reg = <1>; 1571 dsi0_out: endpoint { 1572 }; 1573 }; 1574 }; 1575 }; 1576 1577 dsi0_phy: dsi-phy@c994400 { 1578 compatible = "qcom,dsi-phy-14nm-660"; 1579 reg = <0x0c994400 0x100>, 1580 <0x0c994500 0x300>, 1581 <0x0c994800 0x188>; 1582 reg-names = "dsi_phy", 1583 "dsi_phy_lane", 1584 "dsi_pll"; 1585 1586 #clock-cells = <1>; 1587 #phy-cells = <0>; 1588 1589 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; 1590 clock-names = "iface", "ref"; 1591 }; 1592 }; 1593 1594 blsp1_dma: dma-controller@c144000 { 1595 compatible = "qcom,bam-v1.7.0"; 1596 reg = <0x0c144000 0x1f000>; 1597 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1598 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1599 clock-names = "bam_clk"; 1600 #dma-cells = <1>; 1601 qcom,ee = <0>; 1602 qcom,controlled-remotely; 1603 num-channels = <18>; 1604 qcom,num-ees = <4>; 1605 }; 1606 1607 blsp1_uart1: serial@c16f000 { 1608 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1609 reg = <0x0c16f000 0x200>; 1610 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1611 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 1612 <&gcc GCC_BLSP1_AHB_CLK>; 1613 clock-names = "core", "iface"; 1614 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 1615 dma-names = "tx", "rx"; 1616 pinctrl-names = "default", "sleep"; 1617 pinctrl-0 = <&blsp1_uart1_default>; 1618 pinctrl-1 = <&blsp1_uart1_sleep>; 1619 status = "disabled"; 1620 }; 1621 1622 blsp1_uart2: serial@c170000 { 1623 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1624 reg = <0x0c170000 0x1000>; 1625 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1626 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 1627 <&gcc GCC_BLSP1_AHB_CLK>; 1628 clock-names = "core", "iface"; 1629 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 1630 dma-names = "tx", "rx"; 1631 pinctrl-names = "default"; 1632 pinctrl-0 = <&blsp1_uart2_default>; 1633 status = "disabled"; 1634 }; 1635 1636 blsp_i2c1: i2c@c175000 { 1637 compatible = "qcom,i2c-qup-v2.2.1"; 1638 reg = <0x0c175000 0x600>; 1639 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1640 1641 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1642 <&gcc GCC_BLSP1_AHB_CLK>; 1643 clock-names = "core", "iface"; 1644 clock-frequency = <400000>; 1645 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 1646 dma-names = "tx", "rx"; 1647 1648 pinctrl-names = "default", "sleep"; 1649 pinctrl-0 = <&i2c1_default>; 1650 pinctrl-1 = <&i2c1_sleep>; 1651 #address-cells = <1>; 1652 #size-cells = <0>; 1653 status = "disabled"; 1654 }; 1655 1656 blsp_i2c2: i2c@c176000 { 1657 compatible = "qcom,i2c-qup-v2.2.1"; 1658 reg = <0x0c176000 0x600>; 1659 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1660 1661 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1662 <&gcc GCC_BLSP1_AHB_CLK>; 1663 clock-names = "core", "iface"; 1664 clock-frequency = <400000>; 1665 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 1666 dma-names = "tx", "rx"; 1667 1668 pinctrl-names = "default", "sleep"; 1669 pinctrl-0 = <&i2c2_default>; 1670 pinctrl-1 = <&i2c2_sleep>; 1671 #address-cells = <1>; 1672 #size-cells = <0>; 1673 status = "disabled"; 1674 }; 1675 1676 blsp_i2c3: i2c@c177000 { 1677 compatible = "qcom,i2c-qup-v2.2.1"; 1678 reg = <0x0c177000 0x600>; 1679 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1680 1681 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1682 <&gcc GCC_BLSP1_AHB_CLK>; 1683 clock-names = "core", "iface"; 1684 clock-frequency = <400000>; 1685 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 1686 dma-names = "tx", "rx"; 1687 1688 pinctrl-names = "default", "sleep"; 1689 pinctrl-0 = <&i2c3_default>; 1690 pinctrl-1 = <&i2c3_sleep>; 1691 #address-cells = <1>; 1692 #size-cells = <0>; 1693 status = "disabled"; 1694 }; 1695 1696 blsp_i2c4: i2c@c178000 { 1697 compatible = "qcom,i2c-qup-v2.2.1"; 1698 reg = <0x0c178000 0x600>; 1699 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1700 1701 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1702 <&gcc GCC_BLSP1_AHB_CLK>; 1703 clock-names = "core", "iface"; 1704 clock-frequency = <400000>; 1705 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 1706 dma-names = "tx", "rx"; 1707 1708 pinctrl-names = "default", "sleep"; 1709 pinctrl-0 = <&i2c4_default>; 1710 pinctrl-1 = <&i2c4_sleep>; 1711 #address-cells = <1>; 1712 #size-cells = <0>; 1713 status = "disabled"; 1714 }; 1715 1716 blsp2_dma: dma-controller@c184000 { 1717 compatible = "qcom,bam-v1.7.0"; 1718 reg = <0x0c184000 0x1f000>; 1719 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1720 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1721 clock-names = "bam_clk"; 1722 #dma-cells = <1>; 1723 qcom,ee = <0>; 1724 qcom,controlled-remotely; 1725 num-channels = <18>; 1726 qcom,num-ees = <4>; 1727 }; 1728 1729 blsp2_uart1: serial@c1af000 { 1730 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1731 reg = <0x0c1af000 0x200>; 1732 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1733 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, 1734 <&gcc GCC_BLSP2_AHB_CLK>; 1735 clock-names = "core", "iface"; 1736 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 1737 dma-names = "tx", "rx"; 1738 pinctrl-names = "default", "sleep"; 1739 pinctrl-0 = <&blsp2_uart1_default>; 1740 pinctrl-1 = <&blsp2_uart1_sleep>; 1741 status = "disabled"; 1742 }; 1743 1744 blsp_i2c5: i2c@c1b5000 { 1745 compatible = "qcom,i2c-qup-v2.2.1"; 1746 reg = <0x0c1b5000 0x600>; 1747 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1748 1749 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1750 <&gcc GCC_BLSP2_AHB_CLK>; 1751 clock-names = "core", "iface"; 1752 clock-frequency = <400000>; 1753 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; 1754 dma-names = "tx", "rx"; 1755 1756 pinctrl-names = "default", "sleep"; 1757 pinctrl-0 = <&i2c5_default>; 1758 pinctrl-1 = <&i2c5_sleep>; 1759 #address-cells = <1>; 1760 #size-cells = <0>; 1761 status = "disabled"; 1762 }; 1763 1764 blsp_i2c6: i2c@c1b6000 { 1765 compatible = "qcom,i2c-qup-v2.2.1"; 1766 reg = <0x0c1b6000 0x600>; 1767 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1768 1769 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 1770 <&gcc GCC_BLSP2_AHB_CLK>; 1771 clock-names = "core", "iface"; 1772 clock-frequency = <400000>; 1773 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 1774 dma-names = "tx", "rx"; 1775 1776 pinctrl-names = "default", "sleep"; 1777 pinctrl-0 = <&i2c6_default>; 1778 pinctrl-1 = <&i2c6_sleep>; 1779 #address-cells = <1>; 1780 #size-cells = <0>; 1781 status = "disabled"; 1782 }; 1783 1784 blsp_i2c7: i2c@c1b7000 { 1785 compatible = "qcom,i2c-qup-v2.2.1"; 1786 reg = <0x0c1b7000 0x600>; 1787 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1788 1789 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 1790 <&gcc GCC_BLSP2_AHB_CLK>; 1791 clock-names = "core", "iface"; 1792 clock-frequency = <400000>; 1793 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 1794 dma-names = "tx", "rx"; 1795 1796 pinctrl-names = "default", "sleep"; 1797 pinctrl-0 = <&i2c7_default>; 1798 pinctrl-1 = <&i2c7_sleep>; 1799 #address-cells = <1>; 1800 #size-cells = <0>; 1801 status = "disabled"; 1802 }; 1803 1804 blsp_i2c8: i2c@c1b8000 { 1805 compatible = "qcom,i2c-qup-v2.2.1"; 1806 reg = <0x0c1b8000 0x600>; 1807 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1808 1809 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 1810 <&gcc GCC_BLSP2_AHB_CLK>; 1811 clock-names = "core", "iface"; 1812 clock-frequency = <400000>; 1813 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 1814 dma-names = "tx", "rx"; 1815 1816 pinctrl-names = "default", "sleep"; 1817 pinctrl-0 = <&i2c8_default>; 1818 pinctrl-1 = <&i2c8_sleep>; 1819 #address-cells = <1>; 1820 #size-cells = <0>; 1821 status = "disabled"; 1822 }; 1823 1824 imem@146bf000 { 1825 compatible = "simple-mfd"; 1826 reg = <0x146bf000 0x1000>; 1827 1828 #address-cells = <1>; 1829 #size-cells = <1>; 1830 1831 ranges = <0 0x146bf000 0x1000>; 1832 1833 pil-reloc@94c { 1834 compatible = "qcom,pil-reloc-info"; 1835 reg = <0x94c 0xc8>; 1836 }; 1837 }; 1838 1839 camss: camss@ca00000 { 1840 compatible = "qcom,sdm660-camss"; 1841 reg = <0x0c824000 0x1000>, 1842 <0x0ca00120 0x4>, 1843 <0x0c825000 0x1000>, 1844 <0x0ca00124 0x4>, 1845 <0x0c826000 0x1000>, 1846 <0x0ca00128 0x4>, 1847 <0x0ca30000 0x100>, 1848 <0x0ca30400 0x100>, 1849 <0x0ca30800 0x100>, 1850 <0x0ca30c00 0x100>, 1851 <0x0ca31000 0x500>, 1852 <0x0ca00020 0x10>, 1853 <0x0ca10000 0x1000>, 1854 <0x0ca14000 0x1000>; 1855 reg-names = "csiphy0", 1856 "csiphy0_clk_mux", 1857 "csiphy1", 1858 "csiphy1_clk_mux", 1859 "csiphy2", 1860 "csiphy2_clk_mux", 1861 "csid0", 1862 "csid1", 1863 "csid2", 1864 "csid3", 1865 "ispif", 1866 "csi_clk_mux", 1867 "vfe0", 1868 "vfe1"; 1869 interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 1870 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 1871 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 1872 <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 1873 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 1874 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 1875 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 1876 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 1877 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 1878 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 1879 interrupt-names = "csiphy0", 1880 "csiphy1", 1881 "csiphy2", 1882 "csid0", 1883 "csid1", 1884 "csid2", 1885 "csid3", 1886 "ispif", 1887 "vfe0", 1888 "vfe1"; 1889 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 1890 <&mmcc THROTTLE_CAMSS_AXI_CLK>, 1891 <&mmcc CAMSS_ISPIF_AHB_CLK>, 1892 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 1893 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 1894 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 1895 <&mmcc CAMSS_CSI0_AHB_CLK>, 1896 <&mmcc CAMSS_CSI0_CLK>, 1897 <&mmcc CAMSS_CPHY_CSID0_CLK>, 1898 <&mmcc CAMSS_CSI0PIX_CLK>, 1899 <&mmcc CAMSS_CSI0RDI_CLK>, 1900 <&mmcc CAMSS_CSI1_AHB_CLK>, 1901 <&mmcc CAMSS_CSI1_CLK>, 1902 <&mmcc CAMSS_CPHY_CSID1_CLK>, 1903 <&mmcc CAMSS_CSI1PIX_CLK>, 1904 <&mmcc CAMSS_CSI1RDI_CLK>, 1905 <&mmcc CAMSS_CSI2_AHB_CLK>, 1906 <&mmcc CAMSS_CSI2_CLK>, 1907 <&mmcc CAMSS_CPHY_CSID2_CLK>, 1908 <&mmcc CAMSS_CSI2PIX_CLK>, 1909 <&mmcc CAMSS_CSI2RDI_CLK>, 1910 <&mmcc CAMSS_CSI3_AHB_CLK>, 1911 <&mmcc CAMSS_CSI3_CLK>, 1912 <&mmcc CAMSS_CPHY_CSID3_CLK>, 1913 <&mmcc CAMSS_CSI3PIX_CLK>, 1914 <&mmcc CAMSS_CSI3RDI_CLK>, 1915 <&mmcc CAMSS_AHB_CLK>, 1916 <&mmcc CAMSS_VFE0_CLK>, 1917 <&mmcc CAMSS_CSI_VFE0_CLK>, 1918 <&mmcc CAMSS_VFE0_AHB_CLK>, 1919 <&mmcc CAMSS_VFE0_STREAM_CLK>, 1920 <&mmcc CAMSS_VFE1_CLK>, 1921 <&mmcc CAMSS_CSI_VFE1_CLK>, 1922 <&mmcc CAMSS_VFE1_AHB_CLK>, 1923 <&mmcc CAMSS_VFE1_STREAM_CLK>, 1924 <&mmcc CAMSS_VFE_VBIF_AHB_CLK>, 1925 <&mmcc CAMSS_VFE_VBIF_AXI_CLK>, 1926 <&mmcc CSIPHY_AHB2CRIF_CLK>, 1927 <&mmcc CAMSS_CPHY_CSID0_CLK>, 1928 <&mmcc CAMSS_CPHY_CSID1_CLK>, 1929 <&mmcc CAMSS_CPHY_CSID2_CLK>, 1930 <&mmcc CAMSS_CPHY_CSID3_CLK>; 1931 clock-names = "top_ahb", 1932 "throttle_axi", 1933 "ispif_ahb", 1934 "csiphy0_timer", 1935 "csiphy1_timer", 1936 "csiphy2_timer", 1937 "csi0_ahb", 1938 "csi0", 1939 "csi0_phy", 1940 "csi0_pix", 1941 "csi0_rdi", 1942 "csi1_ahb", 1943 "csi1", 1944 "csi1_phy", 1945 "csi1_pix", 1946 "csi1_rdi", 1947 "csi2_ahb", 1948 "csi2", 1949 "csi2_phy", 1950 "csi2_pix", 1951 "csi2_rdi", 1952 "csi3_ahb", 1953 "csi3", 1954 "csi3_phy", 1955 "csi3_pix", 1956 "csi3_rdi", 1957 "ahb", 1958 "vfe0", 1959 "csi_vfe0", 1960 "vfe0_ahb", 1961 "vfe0_stream", 1962 "vfe1", 1963 "csi_vfe1", 1964 "vfe1_ahb", 1965 "vfe1_stream", 1966 "vfe_ahb", 1967 "vfe_axi", 1968 "csiphy_ahb2crif", 1969 "cphy_csid0", 1970 "cphy_csid1", 1971 "cphy_csid2", 1972 "cphy_csid3"; 1973 interconnects = <&mnoc 5 &bimc 5>; 1974 interconnect-names = "vfe-mem"; 1975 iommus = <&mmss_smmu 0xc00>, 1976 <&mmss_smmu 0xc01>, 1977 <&mmss_smmu 0xc02>, 1978 <&mmss_smmu 0xc03>; 1979 power-domains = <&mmcc CAMSS_VFE0_GDSC>, 1980 <&mmcc CAMSS_VFE1_GDSC>; 1981 status = "disabled"; 1982 1983 ports { 1984 #address-cells = <1>; 1985 #size-cells = <0>; 1986 }; 1987 }; 1988 1989 cci: cci@ca0c000 { 1990 compatible = "qcom,msm8996-cci"; 1991 #address-cells = <1>; 1992 #size-cells = <0>; 1993 reg = <0x0ca0c000 0x1000>; 1994 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 1995 1996 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 1997 <&mmcc CAMSS_CCI_CLK>; 1998 assigned-clock-rates = <80800000>, <37500000>; 1999 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2000 <&mmcc CAMSS_CCI_AHB_CLK>, 2001 <&mmcc CAMSS_CCI_CLK>, 2002 <&mmcc CAMSS_AHB_CLK>; 2003 clock-names = "camss_top_ahb", 2004 "cci_ahb", 2005 "cci", 2006 "camss_ahb"; 2007 2008 pinctrl-names = "default"; 2009 pinctrl-0 = <&cci0_default &cci1_default>; 2010 power-domains = <&mmcc CAMSS_TOP_GDSC>; 2011 status = "disabled"; 2012 2013 cci_i2c0: i2c-bus@0 { 2014 reg = <0>; 2015 clock-frequency = <400000>; 2016 #address-cells = <1>; 2017 #size-cells = <0>; 2018 }; 2019 2020 cci_i2c1: i2c-bus@1 { 2021 reg = <1>; 2022 clock-frequency = <400000>; 2023 #address-cells = <1>; 2024 #size-cells = <0>; 2025 }; 2026 }; 2027 2028 venus: video-codec@cc00000 { 2029 compatible = "qcom,sdm660-venus"; 2030 reg = <0x0cc00000 0xff000>; 2031 clocks = <&mmcc VIDEO_CORE_CLK>, 2032 <&mmcc VIDEO_AHB_CLK>, 2033 <&mmcc VIDEO_AXI_CLK>, 2034 <&mmcc THROTTLE_VIDEO_AXI_CLK>; 2035 clock-names = "core", "iface", "bus", "bus_throttle"; 2036 interconnects = <&gnoc 0 &mnoc 13>, 2037 <&mnoc 4 &bimc 5>; 2038 interconnect-names = "cpu-cfg", "video-mem"; 2039 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 2040 iommus = <&mmss_smmu 0x400>, 2041 <&mmss_smmu 0x401>, 2042 <&mmss_smmu 0x40a>, 2043 <&mmss_smmu 0x407>, 2044 <&mmss_smmu 0x40e>, 2045 <&mmss_smmu 0x40f>, 2046 <&mmss_smmu 0x408>, 2047 <&mmss_smmu 0x409>, 2048 <&mmss_smmu 0x40b>, 2049 <&mmss_smmu 0x40c>, 2050 <&mmss_smmu 0x40d>, 2051 <&mmss_smmu 0x410>, 2052 <&mmss_smmu 0x421>, 2053 <&mmss_smmu 0x428>, 2054 <&mmss_smmu 0x429>, 2055 <&mmss_smmu 0x42b>, 2056 <&mmss_smmu 0x42c>, 2057 <&mmss_smmu 0x42d>, 2058 <&mmss_smmu 0x411>, 2059 <&mmss_smmu 0x431>; 2060 memory-region = <&venus_region>; 2061 power-domains = <&mmcc VENUS_GDSC>; 2062 status = "disabled"; 2063 2064 video-decoder { 2065 compatible = "venus-decoder"; 2066 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2067 clock-names = "vcodec0_core"; 2068 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2069 }; 2070 2071 video-encoder { 2072 compatible = "venus-encoder"; 2073 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2074 clock-names = "vcodec0_core"; 2075 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2076 }; 2077 }; 2078 2079 mmss_smmu: iommu@cd00000 { 2080 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 2081 reg = <0x0cd00000 0x40000>; 2082 2083 clocks = <&mmcc MNOC_AHB_CLK>, 2084 <&mmcc BIMC_SMMU_AHB_CLK>, 2085 <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>, 2086 <&mmcc BIMC_SMMU_AXI_CLK>; 2087 clock-names = "iface-mm", "iface-smmu", 2088 "bus-mm", "bus-smmu"; 2089 #global-interrupts = <2>; 2090 #iommu-cells = <1>; 2091 2092 interrupts = 2093 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2094 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2095 2096 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2097 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 2098 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 2099 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2100 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 2101 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 2102 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 2103 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 2104 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 2105 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 2106 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 2107 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 2108 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 2109 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 2110 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 2111 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2112 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 2113 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2114 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2115 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 2116 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 2117 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 2118 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 2119 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 2120 2121 status = "disabled"; 2122 }; 2123 2124 adsp_pil: remoteproc@15700000 { 2125 compatible = "qcom,sdm660-adsp-pas"; 2126 reg = <0x15700000 0x4040>; 2127 2128 interrupts-extended = 2129 <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2130 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2131 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2132 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2133 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2134 interrupt-names = "wdog", "fatal", "ready", 2135 "handover", "stop-ack"; 2136 2137 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2138 clock-names = "xo"; 2139 2140 memory-region = <&adsp_region>; 2141 power-domains = <&rpmpd SDM660_VDDCX>; 2142 power-domain-names = "cx"; 2143 2144 qcom,smem-states = <&adsp_smp2p_out 0>; 2145 qcom,smem-state-names = "stop"; 2146 2147 glink-edge { 2148 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 2149 2150 label = "lpass"; 2151 mboxes = <&apcs_glb 9>; 2152 qcom,remote-pid = <2>; 2153 #address-cells = <1>; 2154 #size-cells = <0>; 2155 2156 apr { 2157 compatible = "qcom,apr-v2"; 2158 qcom,glink-channels = "apr_audio_svc"; 2159 qcom,apr-domain = <APR_DOMAIN_ADSP>; 2160 #address-cells = <1>; 2161 #size-cells = <0>; 2162 2163 q6core { 2164 reg = <APR_SVC_ADSP_CORE>; 2165 compatible = "qcom,q6core"; 2166 }; 2167 2168 q6afe: apr-service@4 { 2169 compatible = "qcom,q6afe"; 2170 reg = <APR_SVC_AFE>; 2171 q6afedai: dais { 2172 compatible = "qcom,q6afe-dais"; 2173 #address-cells = <1>; 2174 #size-cells = <0>; 2175 #sound-dai-cells = <1>; 2176 }; 2177 }; 2178 2179 q6asm: apr-service@7 { 2180 compatible = "qcom,q6asm"; 2181 reg = <APR_SVC_ASM>; 2182 q6asmdai: dais { 2183 compatible = "qcom,q6asm-dais"; 2184 #address-cells = <1>; 2185 #size-cells = <0>; 2186 #sound-dai-cells = <1>; 2187 iommus = <&lpass_smmu 1>; 2188 }; 2189 }; 2190 2191 q6adm: apr-service@8 { 2192 compatible = "qcom,q6adm"; 2193 reg = <APR_SVC_ADM>; 2194 q6routing: routing { 2195 compatible = "qcom,q6adm-routing"; 2196 #sound-dai-cells = <0>; 2197 }; 2198 }; 2199 }; 2200 }; 2201 }; 2202 2203 gnoc: interconnect@17900000 { 2204 compatible = "qcom,sdm660-gnoc"; 2205 reg = <0x17900000 0xe000>; 2206 #interconnect-cells = <1>; 2207 /* 2208 * This one apparently features no clocks, 2209 * so let's not mess with the driver needlessly 2210 */ 2211 clock-names = "bus", "bus_a"; 2212 clocks = <&xo_board>, <&xo_board>; 2213 }; 2214 2215 apcs_glb: mailbox@17911000 { 2216 compatible = "qcom,sdm660-apcs-hmss-global"; 2217 reg = <0x17911000 0x1000>; 2218 2219 #mbox-cells = <1>; 2220 }; 2221 2222 timer@17920000 { 2223 #address-cells = <1>; 2224 #size-cells = <1>; 2225 ranges; 2226 compatible = "arm,armv7-timer-mem"; 2227 reg = <0x17920000 0x1000>; 2228 clock-frequency = <19200000>; 2229 2230 frame@17921000 { 2231 frame-number = <0>; 2232 interrupts = <0 8 0x4>, 2233 <0 7 0x4>; 2234 reg = <0x17921000 0x1000>, 2235 <0x17922000 0x1000>; 2236 }; 2237 2238 frame@17923000 { 2239 frame-number = <1>; 2240 interrupts = <0 9 0x4>; 2241 reg = <0x17923000 0x1000>; 2242 status = "disabled"; 2243 }; 2244 2245 frame@17924000 { 2246 frame-number = <2>; 2247 interrupts = <0 10 0x4>; 2248 reg = <0x17924000 0x1000>; 2249 status = "disabled"; 2250 }; 2251 2252 frame@17925000 { 2253 frame-number = <3>; 2254 interrupts = <0 11 0x4>; 2255 reg = <0x17925000 0x1000>; 2256 status = "disabled"; 2257 }; 2258 2259 frame@17926000 { 2260 frame-number = <4>; 2261 interrupts = <0 12 0x4>; 2262 reg = <0x17926000 0x1000>; 2263 status = "disabled"; 2264 }; 2265 2266 frame@17927000 { 2267 frame-number = <5>; 2268 interrupts = <0 13 0x4>; 2269 reg = <0x17927000 0x1000>; 2270 status = "disabled"; 2271 }; 2272 2273 frame@17928000 { 2274 frame-number = <6>; 2275 interrupts = <0 14 0x4>; 2276 reg = <0x17928000 0x1000>; 2277 status = "disabled"; 2278 }; 2279 }; 2280 2281 intc: interrupt-controller@17a00000 { 2282 compatible = "arm,gic-v3"; 2283 reg = <0x17a00000 0x10000>, /* GICD */ 2284 <0x17b00000 0x100000>; /* GICR * 8 */ 2285 #interrupt-cells = <3>; 2286 #address-cells = <1>; 2287 #size-cells = <1>; 2288 ranges; 2289 interrupt-controller; 2290 #redistributor-regions = <1>; 2291 redistributor-stride = <0x0 0x20000>; 2292 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2293 }; 2294 }; 2295 2296 tcsr_mutex: hwlock { 2297 compatible = "qcom,tcsr-mutex"; 2298 syscon = <&tcsr_mutex_regs 0 0x1000>; 2299 #hwlock-cells = <1>; 2300 }; 2301 2302 sound: sound { 2303 }; 2304 2305 thermal-zones { 2306 aoss-thermal { 2307 polling-delay-passive = <250>; 2308 polling-delay = <1000>; 2309 2310 thermal-sensors = <&tsens 0>; 2311 2312 trips { 2313 aoss_alert0: trip-point0 { 2314 temperature = <105000>; 2315 hysteresis = <1000>; 2316 type = "hot"; 2317 }; 2318 }; 2319 }; 2320 2321 cpuss0-thermal { 2322 polling-delay-passive = <250>; 2323 polling-delay = <1000>; 2324 2325 thermal-sensors = <&tsens 1>; 2326 2327 trips { 2328 cpuss0_alert0: trip-point0 { 2329 temperature = <125000>; 2330 hysteresis = <1000>; 2331 type = "hot"; 2332 }; 2333 }; 2334 }; 2335 2336 cpuss1-thermal { 2337 polling-delay-passive = <250>; 2338 polling-delay = <1000>; 2339 2340 thermal-sensors = <&tsens 2>; 2341 2342 trips { 2343 cpuss1_alert0: trip-point0 { 2344 temperature = <125000>; 2345 hysteresis = <1000>; 2346 type = "hot"; 2347 }; 2348 }; 2349 }; 2350 2351 cpu0-thermal { 2352 polling-delay-passive = <250>; 2353 polling-delay = <1000>; 2354 2355 thermal-sensors = <&tsens 3>; 2356 2357 trips { 2358 cpu0_alert0: trip-point0 { 2359 temperature = <70000>; 2360 hysteresis = <1000>; 2361 type = "passive"; 2362 }; 2363 2364 cpu0_crit: cpu_crit { 2365 temperature = <110000>; 2366 hysteresis = <1000>; 2367 type = "critical"; 2368 }; 2369 }; 2370 }; 2371 2372 cpu1-thermal { 2373 polling-delay-passive = <250>; 2374 polling-delay = <1000>; 2375 2376 thermal-sensors = <&tsens 4>; 2377 2378 trips { 2379 cpu1_alert0: trip-point0 { 2380 temperature = <70000>; 2381 hysteresis = <1000>; 2382 type = "passive"; 2383 }; 2384 2385 cpu1_crit: cpu_crit { 2386 temperature = <110000>; 2387 hysteresis = <1000>; 2388 type = "critical"; 2389 }; 2390 }; 2391 }; 2392 2393 cpu2-thermal { 2394 polling-delay-passive = <250>; 2395 polling-delay = <1000>; 2396 2397 thermal-sensors = <&tsens 5>; 2398 2399 trips { 2400 cpu2_alert0: trip-point0 { 2401 temperature = <70000>; 2402 hysteresis = <1000>; 2403 type = "passive"; 2404 }; 2405 2406 cpu2_crit: cpu_crit { 2407 temperature = <110000>; 2408 hysteresis = <1000>; 2409 type = "critical"; 2410 }; 2411 }; 2412 }; 2413 2414 cpu3-thermal { 2415 polling-delay-passive = <250>; 2416 polling-delay = <1000>; 2417 2418 thermal-sensors = <&tsens 6>; 2419 2420 trips { 2421 cpu3_alert0: trip-point0 { 2422 temperature = <70000>; 2423 hysteresis = <1000>; 2424 type = "passive"; 2425 }; 2426 2427 cpu3_crit: cpu_crit { 2428 temperature = <110000>; 2429 hysteresis = <1000>; 2430 type = "critical"; 2431 }; 2432 }; 2433 }; 2434 2435 /* 2436 * According to what downstream DTS says, 2437 * the entire power efficient cluster has 2438 * only a single thermal sensor. 2439 */ 2440 2441 pwr-cluster-thermal { 2442 polling-delay-passive = <250>; 2443 polling-delay = <1000>; 2444 2445 thermal-sensors = <&tsens 7>; 2446 2447 trips { 2448 pwr_cluster_alert0: trip-point0 { 2449 temperature = <70000>; 2450 hysteresis = <1000>; 2451 type = "passive"; 2452 }; 2453 2454 pwr_cluster_crit: cpu_crit { 2455 temperature = <110000>; 2456 hysteresis = <1000>; 2457 type = "critical"; 2458 }; 2459 }; 2460 }; 2461 2462 gpu-thermal { 2463 polling-delay-passive = <250>; 2464 polling-delay = <1000>; 2465 2466 thermal-sensors = <&tsens 8>; 2467 2468 trips { 2469 gpu_alert0: trip-point0 { 2470 temperature = <90000>; 2471 hysteresis = <1000>; 2472 type = "hot"; 2473 }; 2474 }; 2475 }; 2476 }; 2477 2478 timer { 2479 compatible = "arm,armv8-timer"; 2480 interrupts = <GIC_PPI 1 0xf08>, 2481 <GIC_PPI 2 0xf08>, 2482 <GIC_PPI 3 0xf08>, 2483 <GIC_PPI 0 0xf08>; 2484 }; 2485}; 2486 2487