1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Linaro Limited 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> 8#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 9#include <dt-bindings/clock/qcom,gcc-sc8280xp.h> 10#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,sc8280xp-camcc.h> 13#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> 14#include <dt-bindings/dma/qcom-gpi.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,sc8280xp.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/mailbox/qcom-ipcc.h> 19#include <dt-bindings/phy/phy-qcom-qmp.h> 20#include <dt-bindings/power/qcom-rpmpd.h> 21#include <dt-bindings/soc/qcom,gpr.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23#include <dt-bindings/sound/qcom,q6afe.h> 24#include <dt-bindings/thermal/thermal.h> 25 26/ { 27 interrupt-parent = <&intc>; 28 29 #address-cells = <2>; 30 #size-cells = <2>; 31 32 clocks { 33 xo_board_clk: xo-board-clk { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 }; 37 38 sleep_clk: sleep-clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <32764>; 42 }; 43 }; 44 45 cpus { 46 #address-cells = <2>; 47 #size-cells = <0>; 48 49 cpu0: cpu@0 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a78c"; 52 reg = <0x0 0x0>; 53 clocks = <&cpufreq_hw 0>; 54 enable-method = "psci"; 55 capacity-dmips-mhz = <981>; 56 dynamic-power-coefficient = <549>; 57 next-level-cache = <&l2_0>; 58 power-domains = <&cpu_pd0>; 59 power-domain-names = "psci"; 60 qcom,freq-domain = <&cpufreq_hw 0>; 61 operating-points-v2 = <&cpu0_opp_table>; 62 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 63 #cooling-cells = <2>; 64 l2_0: l2-cache { 65 compatible = "cache"; 66 cache-level = <2>; 67 cache-unified; 68 next-level-cache = <&l3_0>; 69 l3_0: l3-cache { 70 compatible = "cache"; 71 cache-level = <3>; 72 cache-unified; 73 }; 74 }; 75 }; 76 77 cpu1: cpu@100 { 78 device_type = "cpu"; 79 compatible = "arm,cortex-a78c"; 80 reg = <0x0 0x100>; 81 clocks = <&cpufreq_hw 0>; 82 enable-method = "psci"; 83 capacity-dmips-mhz = <981>; 84 dynamic-power-coefficient = <549>; 85 next-level-cache = <&l2_100>; 86 power-domains = <&cpu_pd1>; 87 power-domain-names = "psci"; 88 qcom,freq-domain = <&cpufreq_hw 0>; 89 operating-points-v2 = <&cpu0_opp_table>; 90 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 91 #cooling-cells = <2>; 92 l2_100: l2-cache { 93 compatible = "cache"; 94 cache-level = <2>; 95 cache-unified; 96 next-level-cache = <&l3_0>; 97 }; 98 }; 99 100 cpu2: cpu@200 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a78c"; 103 reg = <0x0 0x200>; 104 clocks = <&cpufreq_hw 0>; 105 enable-method = "psci"; 106 capacity-dmips-mhz = <981>; 107 dynamic-power-coefficient = <549>; 108 next-level-cache = <&l2_200>; 109 power-domains = <&cpu_pd2>; 110 power-domain-names = "psci"; 111 qcom,freq-domain = <&cpufreq_hw 0>; 112 operating-points-v2 = <&cpu0_opp_table>; 113 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 114 #cooling-cells = <2>; 115 l2_200: l2-cache { 116 compatible = "cache"; 117 cache-level = <2>; 118 cache-unified; 119 next-level-cache = <&l3_0>; 120 }; 121 }; 122 123 cpu3: cpu@300 { 124 device_type = "cpu"; 125 compatible = "arm,cortex-a78c"; 126 reg = <0x0 0x300>; 127 clocks = <&cpufreq_hw 0>; 128 enable-method = "psci"; 129 capacity-dmips-mhz = <981>; 130 dynamic-power-coefficient = <549>; 131 next-level-cache = <&l2_300>; 132 power-domains = <&cpu_pd3>; 133 power-domain-names = "psci"; 134 qcom,freq-domain = <&cpufreq_hw 0>; 135 operating-points-v2 = <&cpu0_opp_table>; 136 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 137 #cooling-cells = <2>; 138 l2_300: l2-cache { 139 compatible = "cache"; 140 cache-level = <2>; 141 cache-unified; 142 next-level-cache = <&l3_0>; 143 }; 144 }; 145 146 cpu4: cpu@400 { 147 device_type = "cpu"; 148 compatible = "arm,cortex-x1c"; 149 reg = <0x0 0x400>; 150 clocks = <&cpufreq_hw 1>; 151 enable-method = "psci"; 152 capacity-dmips-mhz = <1024>; 153 dynamic-power-coefficient = <590>; 154 next-level-cache = <&l2_400>; 155 power-domains = <&cpu_pd4>; 156 power-domain-names = "psci"; 157 qcom,freq-domain = <&cpufreq_hw 1>; 158 operating-points-v2 = <&cpu4_opp_table>; 159 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 160 #cooling-cells = <2>; 161 l2_400: l2-cache { 162 compatible = "cache"; 163 cache-level = <2>; 164 cache-unified; 165 next-level-cache = <&l3_0>; 166 }; 167 }; 168 169 cpu5: cpu@500 { 170 device_type = "cpu"; 171 compatible = "arm,cortex-x1c"; 172 reg = <0x0 0x500>; 173 clocks = <&cpufreq_hw 1>; 174 enable-method = "psci"; 175 capacity-dmips-mhz = <1024>; 176 dynamic-power-coefficient = <590>; 177 next-level-cache = <&l2_500>; 178 power-domains = <&cpu_pd5>; 179 power-domain-names = "psci"; 180 qcom,freq-domain = <&cpufreq_hw 1>; 181 operating-points-v2 = <&cpu4_opp_table>; 182 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 183 #cooling-cells = <2>; 184 l2_500: l2-cache { 185 compatible = "cache"; 186 cache-level = <2>; 187 cache-unified; 188 next-level-cache = <&l3_0>; 189 }; 190 }; 191 192 cpu6: cpu@600 { 193 device_type = "cpu"; 194 compatible = "arm,cortex-x1c"; 195 reg = <0x0 0x600>; 196 clocks = <&cpufreq_hw 1>; 197 enable-method = "psci"; 198 capacity-dmips-mhz = <1024>; 199 dynamic-power-coefficient = <590>; 200 next-level-cache = <&l2_600>; 201 power-domains = <&cpu_pd6>; 202 power-domain-names = "psci"; 203 qcom,freq-domain = <&cpufreq_hw 1>; 204 operating-points-v2 = <&cpu4_opp_table>; 205 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 206 #cooling-cells = <2>; 207 l2_600: l2-cache { 208 compatible = "cache"; 209 cache-level = <2>; 210 cache-unified; 211 next-level-cache = <&l3_0>; 212 }; 213 }; 214 215 cpu7: cpu@700 { 216 device_type = "cpu"; 217 compatible = "arm,cortex-x1c"; 218 reg = <0x0 0x700>; 219 clocks = <&cpufreq_hw 1>; 220 enable-method = "psci"; 221 capacity-dmips-mhz = <1024>; 222 dynamic-power-coefficient = <590>; 223 next-level-cache = <&l2_700>; 224 power-domains = <&cpu_pd7>; 225 power-domain-names = "psci"; 226 qcom,freq-domain = <&cpufreq_hw 1>; 227 operating-points-v2 = <&cpu4_opp_table>; 228 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 229 #cooling-cells = <2>; 230 l2_700: l2-cache { 231 compatible = "cache"; 232 cache-level = <2>; 233 cache-unified; 234 next-level-cache = <&l3_0>; 235 }; 236 }; 237 238 cpu-map { 239 cluster0 { 240 core0 { 241 cpu = <&cpu0>; 242 }; 243 244 core1 { 245 cpu = <&cpu1>; 246 }; 247 248 core2 { 249 cpu = <&cpu2>; 250 }; 251 252 core3 { 253 cpu = <&cpu3>; 254 }; 255 256 core4 { 257 cpu = <&cpu4>; 258 }; 259 260 core5 { 261 cpu = <&cpu5>; 262 }; 263 264 core6 { 265 cpu = <&cpu6>; 266 }; 267 268 core7 { 269 cpu = <&cpu7>; 270 }; 271 }; 272 }; 273 274 idle-states { 275 entry-method = "psci"; 276 277 little_cpu_sleep_0: cpu-sleep-0-0 { 278 compatible = "arm,idle-state"; 279 idle-state-name = "little-rail-power-collapse"; 280 arm,psci-suspend-param = <0x40000004>; 281 entry-latency-us = <355>; 282 exit-latency-us = <909>; 283 min-residency-us = <3934>; 284 local-timer-stop; 285 }; 286 287 big_cpu_sleep_0: cpu-sleep-1-0 { 288 compatible = "arm,idle-state"; 289 idle-state-name = "big-rail-power-collapse"; 290 arm,psci-suspend-param = <0x40000004>; 291 entry-latency-us = <241>; 292 exit-latency-us = <1461>; 293 min-residency-us = <4488>; 294 local-timer-stop; 295 }; 296 }; 297 298 domain-idle-states { 299 cluster_sleep_0: cluster-sleep-0 { 300 compatible = "domain-idle-state"; 301 arm,psci-suspend-param = <0x4100c344>; 302 entry-latency-us = <3263>; 303 exit-latency-us = <6562>; 304 min-residency-us = <9987>; 305 }; 306 }; 307 }; 308 309 firmware { 310 scm: scm { 311 compatible = "qcom,scm-sc8280xp", "qcom,scm"; 312 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 313 qcom,dload-mode = <&tcsr 0x13000>; 314 }; 315 }; 316 317 aggre1_noc: interconnect-aggre1-noc { 318 compatible = "qcom,sc8280xp-aggre1-noc"; 319 #interconnect-cells = <2>; 320 qcom,bcm-voters = <&apps_bcm_voter>; 321 }; 322 323 aggre2_noc: interconnect-aggre2-noc { 324 compatible = "qcom,sc8280xp-aggre2-noc"; 325 #interconnect-cells = <2>; 326 qcom,bcm-voters = <&apps_bcm_voter>; 327 }; 328 329 clk_virt: interconnect-clk-virt { 330 compatible = "qcom,sc8280xp-clk-virt"; 331 #interconnect-cells = <2>; 332 qcom,bcm-voters = <&apps_bcm_voter>; 333 }; 334 335 config_noc: interconnect-config-noc { 336 compatible = "qcom,sc8280xp-config-noc"; 337 #interconnect-cells = <2>; 338 qcom,bcm-voters = <&apps_bcm_voter>; 339 }; 340 341 dc_noc: interconnect-dc-noc { 342 compatible = "qcom,sc8280xp-dc-noc"; 343 #interconnect-cells = <2>; 344 qcom,bcm-voters = <&apps_bcm_voter>; 345 }; 346 347 gem_noc: interconnect-gem-noc { 348 compatible = "qcom,sc8280xp-gem-noc"; 349 #interconnect-cells = <2>; 350 qcom,bcm-voters = <&apps_bcm_voter>; 351 }; 352 353 lpass_noc: interconnect-lpass-ag-noc { 354 compatible = "qcom,sc8280xp-lpass-ag-noc"; 355 #interconnect-cells = <2>; 356 qcom,bcm-voters = <&apps_bcm_voter>; 357 }; 358 359 mc_virt: interconnect-mc-virt { 360 compatible = "qcom,sc8280xp-mc-virt"; 361 #interconnect-cells = <2>; 362 qcom,bcm-voters = <&apps_bcm_voter>; 363 }; 364 365 mmss_noc: interconnect-mmss-noc { 366 compatible = "qcom,sc8280xp-mmss-noc"; 367 #interconnect-cells = <2>; 368 qcom,bcm-voters = <&apps_bcm_voter>; 369 }; 370 371 nspa_noc: interconnect-nspa-noc { 372 compatible = "qcom,sc8280xp-nspa-noc"; 373 #interconnect-cells = <2>; 374 qcom,bcm-voters = <&apps_bcm_voter>; 375 }; 376 377 nspb_noc: interconnect-nspb-noc { 378 compatible = "qcom,sc8280xp-nspb-noc"; 379 #interconnect-cells = <2>; 380 qcom,bcm-voters = <&apps_bcm_voter>; 381 }; 382 383 system_noc: interconnect-system-noc { 384 compatible = "qcom,sc8280xp-system-noc"; 385 #interconnect-cells = <2>; 386 qcom,bcm-voters = <&apps_bcm_voter>; 387 }; 388 389 memory@80000000 { 390 device_type = "memory"; 391 /* We expect the bootloader to fill in the size */ 392 reg = <0x0 0x80000000 0x0 0x0>; 393 }; 394 395 cpu0_opp_table: opp-table-cpu0 { 396 compatible = "operating-points-v2"; 397 opp-shared; 398 399 opp-300000000 { 400 opp-hz = /bits/ 64 <300000000>; 401 opp-peak-kBps = <(300000 * 32)>; 402 }; 403 opp-403200000 { 404 opp-hz = /bits/ 64 <403200000>; 405 opp-peak-kBps = <(384000 * 32)>; 406 }; 407 opp-499200000 { 408 opp-hz = /bits/ 64 <499200000>; 409 opp-peak-kBps = <(480000 * 32)>; 410 }; 411 opp-595200000 { 412 opp-hz = /bits/ 64 <595200000>; 413 opp-peak-kBps = <(576000 * 32)>; 414 }; 415 opp-691200000 { 416 opp-hz = /bits/ 64 <691200000>; 417 opp-peak-kBps = <(672000 * 32)>; 418 }; 419 opp-806400000 { 420 opp-hz = /bits/ 64 <806400000>; 421 opp-peak-kBps = <(768000 * 32)>; 422 }; 423 opp-902400000 { 424 opp-hz = /bits/ 64 <902400000>; 425 opp-peak-kBps = <(864000 * 32)>; 426 }; 427 opp-1017600000 { 428 opp-hz = /bits/ 64 <1017600000>; 429 opp-peak-kBps = <(960000 * 32)>; 430 }; 431 opp-1113600000 { 432 opp-hz = /bits/ 64 <1113600000>; 433 opp-peak-kBps = <(1075200 * 32)>; 434 }; 435 opp-1209600000 { 436 opp-hz = /bits/ 64 <1209600000>; 437 opp-peak-kBps = <(1171200 * 32)>; 438 }; 439 opp-1324800000 { 440 opp-hz = /bits/ 64 <1324800000>; 441 opp-peak-kBps = <(1267200 * 32)>; 442 }; 443 opp-1440000000 { 444 opp-hz = /bits/ 64 <1440000000>; 445 opp-peak-kBps = <(1363200 * 32)>; 446 }; 447 opp-1555200000 { 448 opp-hz = /bits/ 64 <1555200000>; 449 opp-peak-kBps = <(1536000 * 32)>; 450 }; 451 opp-1670400000 { 452 opp-hz = /bits/ 64 <1670400000>; 453 opp-peak-kBps = <(1612800 * 32)>; 454 }; 455 opp-1785600000 { 456 opp-hz = /bits/ 64 <1785600000>; 457 opp-peak-kBps = <(1689600 * 32)>; 458 }; 459 opp-1881600000 { 460 opp-hz = /bits/ 64 <1881600000>; 461 opp-peak-kBps = <(1689600 * 32)>; 462 }; 463 opp-1996800000 { 464 opp-hz = /bits/ 64 <1996800000>; 465 opp-peak-kBps = <(1689600 * 32)>; 466 }; 467 opp-2112000000 { 468 opp-hz = /bits/ 64 <2112000000>; 469 opp-peak-kBps = <(1689600 * 32)>; 470 }; 471 opp-2227200000 { 472 opp-hz = /bits/ 64 <2227200000>; 473 opp-peak-kBps = <(1689600 * 32)>; 474 }; 475 opp-2342400000 { 476 opp-hz = /bits/ 64 <2342400000>; 477 opp-peak-kBps = <(1689600 * 32)>; 478 }; 479 opp-2438400000 { 480 opp-hz = /bits/ 64 <2438400000>; 481 opp-peak-kBps = <(1689600 * 32)>; 482 }; 483 }; 484 485 cpu4_opp_table: opp-table-cpu4 { 486 compatible = "operating-points-v2"; 487 opp-shared; 488 489 opp-825600000 { 490 opp-hz = /bits/ 64 <825600000>; 491 opp-peak-kBps = <(768000 * 32)>; 492 }; 493 opp-940800000 { 494 opp-hz = /bits/ 64 <940800000>; 495 opp-peak-kBps = <(864000 * 32)>; 496 }; 497 opp-1056000000 { 498 opp-hz = /bits/ 64 <1056000000>; 499 opp-peak-kBps = <(960000 * 32)>; 500 }; 501 opp-1171200000 { 502 opp-hz = /bits/ 64 <1171200000>; 503 opp-peak-kBps = <(1171200 * 32)>; 504 }; 505 opp-1286400000 { 506 opp-hz = /bits/ 64 <1286400000>; 507 opp-peak-kBps = <(1267200 * 32)>; 508 }; 509 opp-1401600000 { 510 opp-hz = /bits/ 64 <1401600000>; 511 opp-peak-kBps = <(1363200 * 32)>; 512 }; 513 opp-1516800000 { 514 opp-hz = /bits/ 64 <1516800000>; 515 opp-peak-kBps = <(1459200 * 32)>; 516 }; 517 opp-1632000000 { 518 opp-hz = /bits/ 64 <1632000000>; 519 opp-peak-kBps = <(1612800 * 32)>; 520 }; 521 opp-1747200000 { 522 opp-hz = /bits/ 64 <1747200000>; 523 opp-peak-kBps = <(1689600 * 32)>; 524 }; 525 opp-1862400000 { 526 opp-hz = /bits/ 64 <1862400000>; 527 opp-peak-kBps = <(1689600 * 32)>; 528 }; 529 opp-1977600000 { 530 opp-hz = /bits/ 64 <1977600000>; 531 opp-peak-kBps = <(1689600 * 32)>; 532 }; 533 opp-2073600000 { 534 opp-hz = /bits/ 64 <2073600000>; 535 opp-peak-kBps = <(1689600 * 32)>; 536 }; 537 opp-2169600000 { 538 opp-hz = /bits/ 64 <2169600000>; 539 opp-peak-kBps = <(1689600 * 32)>; 540 }; 541 opp-2284800000 { 542 opp-hz = /bits/ 64 <2284800000>; 543 opp-peak-kBps = <(1689600 * 32)>; 544 }; 545 opp-2400000000 { 546 opp-hz = /bits/ 64 <2400000000>; 547 opp-peak-kBps = <(1689600 * 32)>; 548 }; 549 opp-2496000000 { 550 opp-hz = /bits/ 64 <2496000000>; 551 opp-peak-kBps = <(1689600 * 32)>; 552 }; 553 opp-2592000000 { 554 opp-hz = /bits/ 64 <2592000000>; 555 opp-peak-kBps = <(1689600 * 32)>; 556 }; 557 opp-2688000000 { 558 opp-hz = /bits/ 64 <2688000000>; 559 opp-peak-kBps = <(1689600 * 32)>; 560 }; 561 opp-2803200000 { 562 opp-hz = /bits/ 64 <2803200000>; 563 opp-peak-kBps = <(1689600 * 32)>; 564 }; 565 opp-2899200000 { 566 opp-hz = /bits/ 64 <2899200000>; 567 opp-peak-kBps = <(1689600 * 32)>; 568 }; 569 opp-2995200000 { 570 opp-hz = /bits/ 64 <2995200000>; 571 opp-peak-kBps = <(1689600 * 32)>; 572 }; 573 }; 574 575 qup_opp_table_100mhz: opp-table-qup100mhz { 576 compatible = "operating-points-v2"; 577 578 opp-75000000 { 579 opp-hz = /bits/ 64 <75000000>; 580 required-opps = <&rpmhpd_opp_low_svs>; 581 }; 582 583 opp-100000000 { 584 opp-hz = /bits/ 64 <100000000>; 585 required-opps = <&rpmhpd_opp_svs>; 586 }; 587 }; 588 589 pmu { 590 compatible = "arm,armv8-pmuv3"; 591 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 592 }; 593 594 psci { 595 compatible = "arm,psci-1.0"; 596 method = "smc"; 597 598 cpu_pd0: power-domain-cpu0 { 599 #power-domain-cells = <0>; 600 power-domains = <&cluster_pd>; 601 domain-idle-states = <&little_cpu_sleep_0>; 602 }; 603 604 cpu_pd1: power-domain-cpu1 { 605 #power-domain-cells = <0>; 606 power-domains = <&cluster_pd>; 607 domain-idle-states = <&little_cpu_sleep_0>; 608 }; 609 610 cpu_pd2: power-domain-cpu2 { 611 #power-domain-cells = <0>; 612 power-domains = <&cluster_pd>; 613 domain-idle-states = <&little_cpu_sleep_0>; 614 }; 615 616 cpu_pd3: power-domain-cpu3 { 617 #power-domain-cells = <0>; 618 power-domains = <&cluster_pd>; 619 domain-idle-states = <&little_cpu_sleep_0>; 620 }; 621 622 cpu_pd4: power-domain-cpu4 { 623 #power-domain-cells = <0>; 624 power-domains = <&cluster_pd>; 625 domain-idle-states = <&big_cpu_sleep_0>; 626 }; 627 628 cpu_pd5: power-domain-cpu5 { 629 #power-domain-cells = <0>; 630 power-domains = <&cluster_pd>; 631 domain-idle-states = <&big_cpu_sleep_0>; 632 }; 633 634 cpu_pd6: power-domain-cpu6 { 635 #power-domain-cells = <0>; 636 power-domains = <&cluster_pd>; 637 domain-idle-states = <&big_cpu_sleep_0>; 638 }; 639 640 cpu_pd7: power-domain-cpu7 { 641 #power-domain-cells = <0>; 642 power-domains = <&cluster_pd>; 643 domain-idle-states = <&big_cpu_sleep_0>; 644 }; 645 646 cluster_pd: power-domain-cpu-cluster0 { 647 #power-domain-cells = <0>; 648 domain-idle-states = <&cluster_sleep_0>; 649 }; 650 }; 651 652 reserved-memory { 653 #address-cells = <2>; 654 #size-cells = <2>; 655 ranges; 656 657 reserved-region@80000000 { 658 reg = <0 0x80000000 0 0x860000>; 659 no-map; 660 }; 661 662 cmd_db: cmd-db-region@80860000 { 663 compatible = "qcom,cmd-db"; 664 reg = <0 0x80860000 0 0x20000>; 665 no-map; 666 }; 667 668 reserved-region@80880000 { 669 reg = <0 0x80880000 0 0x80000>; 670 no-map; 671 }; 672 673 smem_mem: smem-region@80900000 { 674 compatible = "qcom,smem"; 675 reg = <0 0x80900000 0 0x200000>; 676 no-map; 677 hwlocks = <&tcsr_mutex 3>; 678 }; 679 680 reserved-region@80b00000 { 681 reg = <0 0x80b00000 0 0x100000>; 682 no-map; 683 }; 684 685 reserved-region@83b00000 { 686 reg = <0 0x83b00000 0 0x1700000>; 687 no-map; 688 }; 689 690 reserved-region@85b00000 { 691 reg = <0 0x85b00000 0 0xc00000>; 692 no-map; 693 }; 694 695 pil_gpu_mem: gpu-mem@8bf00000 { 696 reg = <0 0x8bf00000 0 0x2000>; 697 no-map; 698 }; 699 700 pil_adsp_mem: adsp-region@86c00000 { 701 reg = <0 0x86c00000 0 0x2000000>; 702 no-map; 703 }; 704 705 pil_slpi_mem: slpi-region@88c00000 { 706 reg = <0 0x88c00000 0 0x1500000>; 707 no-map; 708 }; 709 710 pil_nsp0_mem: cdsp0-region@8a100000 { 711 reg = <0 0x8a100000 0 0x1e00000>; 712 no-map; 713 }; 714 715 pil_nsp1_mem: cdsp1-region@8c600000 { 716 reg = <0 0x8c600000 0 0x1e00000>; 717 no-map; 718 }; 719 720 reserved-region@aeb00000 { 721 reg = <0 0xaeb00000 0 0x16600000>; 722 no-map; 723 }; 724 }; 725 726 smp2p-adsp { 727 compatible = "qcom,smp2p"; 728 qcom,smem = <443>, <429>; 729 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 730 IPCC_MPROC_SIGNAL_SMP2P 731 IRQ_TYPE_EDGE_RISING>; 732 mboxes = <&ipcc IPCC_CLIENT_LPASS 733 IPCC_MPROC_SIGNAL_SMP2P>; 734 735 qcom,local-pid = <0>; 736 qcom,remote-pid = <2>; 737 738 smp2p_adsp_out: master-kernel { 739 qcom,entry-name = "master-kernel"; 740 #qcom,smem-state-cells = <1>; 741 }; 742 743 smp2p_adsp_in: slave-kernel { 744 qcom,entry-name = "slave-kernel"; 745 interrupt-controller; 746 #interrupt-cells = <2>; 747 }; 748 }; 749 750 smp2p-nsp0 { 751 compatible = "qcom,smp2p"; 752 qcom,smem = <94>, <432>; 753 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 754 IPCC_MPROC_SIGNAL_SMP2P 755 IRQ_TYPE_EDGE_RISING>; 756 mboxes = <&ipcc IPCC_CLIENT_CDSP 757 IPCC_MPROC_SIGNAL_SMP2P>; 758 759 qcom,local-pid = <0>; 760 qcom,remote-pid = <5>; 761 762 smp2p_nsp0_out: master-kernel { 763 qcom,entry-name = "master-kernel"; 764 #qcom,smem-state-cells = <1>; 765 }; 766 767 smp2p_nsp0_in: slave-kernel { 768 qcom,entry-name = "slave-kernel"; 769 interrupt-controller; 770 #interrupt-cells = <2>; 771 }; 772 }; 773 774 smp2p-nsp1 { 775 compatible = "qcom,smp2p"; 776 qcom,smem = <617>, <616>; 777 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 778 IPCC_MPROC_SIGNAL_SMP2P 779 IRQ_TYPE_EDGE_RISING>; 780 mboxes = <&ipcc IPCC_CLIENT_NSP1 781 IPCC_MPROC_SIGNAL_SMP2P>; 782 783 qcom,local-pid = <0>; 784 qcom,remote-pid = <12>; 785 786 smp2p_nsp1_out: master-kernel { 787 qcom,entry-name = "master-kernel"; 788 #qcom,smem-state-cells = <1>; 789 }; 790 791 smp2p_nsp1_in: slave-kernel { 792 qcom,entry-name = "slave-kernel"; 793 interrupt-controller; 794 #interrupt-cells = <2>; 795 }; 796 }; 797 798 smp2p-slpi { 799 compatible = "qcom,smp2p"; 800 qcom,smem = <481>, <430>; 801 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 802 IPCC_MPROC_SIGNAL_SMP2P 803 IRQ_TYPE_EDGE_RISING>; 804 mboxes = <&ipcc IPCC_CLIENT_SLPI 805 IPCC_MPROC_SIGNAL_SMP2P>; 806 807 qcom,local-pid = <0>; 808 qcom,remote-pid = <3>; 809 810 smp2p_slpi_out: master-kernel { 811 qcom,entry-name = "master-kernel"; 812 #qcom,smem-state-cells = <1>; 813 }; 814 815 smp2p_slpi_in: slave-kernel { 816 qcom,entry-name = "slave-kernel"; 817 interrupt-controller; 818 #interrupt-cells = <2>; 819 }; 820 }; 821 822 soc: soc@0 { 823 compatible = "simple-bus"; 824 #address-cells = <2>; 825 #size-cells = <2>; 826 ranges = <0 0 0 0 0x10 0>; 827 dma-ranges = <0 0 0 0 0x10 0>; 828 829 ethernet0: ethernet@20000 { 830 compatible = "qcom,sc8280xp-ethqos"; 831 reg = <0x0 0x00020000 0x0 0x10000>, 832 <0x0 0x00036000 0x0 0x100>; 833 reg-names = "stmmaceth", "rgmii"; 834 835 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 836 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 837 <&gcc GCC_EMAC0_PTP_CLK>, 838 <&gcc GCC_EMAC0_RGMII_CLK>; 839 clock-names = "stmmaceth", 840 "pclk", 841 "ptp_ref", 842 "rgmii"; 843 844 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 845 <GIC_SPI 936 IRQ_TYPE_LEVEL_HIGH>; 846 interrupt-names = "macirq", "eth_lpi"; 847 848 iommus = <&apps_smmu 0x4c0 0xf>; 849 power-domains = <&gcc EMAC_0_GDSC>; 850 851 snps,tso; 852 snps,pbl = <32>; 853 rx-fifo-depth = <4096>; 854 tx-fifo-depth = <4096>; 855 856 status = "disabled"; 857 }; 858 859 gcc: clock-controller@100000 { 860 compatible = "qcom,gcc-sc8280xp"; 861 reg = <0x0 0x00100000 0x0 0x1f0000>; 862 #clock-cells = <1>; 863 #reset-cells = <1>; 864 #power-domain-cells = <1>; 865 clocks = <&rpmhcc RPMH_CXO_CLK>, 866 <&sleep_clk>, 867 <0>, 868 <0>, 869 <0>, 870 <0>, 871 <0>, 872 <0>, 873 <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 874 <0>, 875 <0>, 876 <0>, 877 <0>, 878 <0>, 879 <0>, 880 <0>, 881 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 882 <0>, 883 <0>, 884 <0>, 885 <0>, 886 <0>, 887 <0>, 888 <0>, 889 <0>, 890 <0>, 891 <&pcie2a_phy>, 892 <&pcie2b_phy>, 893 <&pcie3a_phy>, 894 <&pcie3b_phy>, 895 <&pcie4_phy>, 896 <0>, 897 <0>; 898 power-domains = <&rpmhpd SC8280XP_CX>; 899 }; 900 901 ipcc: mailbox@408000 { 902 compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc"; 903 reg = <0 0x00408000 0 0x1000>; 904 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 905 interrupt-controller; 906 #interrupt-cells = <3>; 907 #mbox-cells = <2>; 908 }; 909 910 qfprom: efuse@784000 { 911 compatible = "qcom,sc8280xp-qfprom", "qcom,qfprom"; 912 reg = <0 0x00784000 0 0x3000>; 913 #address-cells = <1>; 914 #size-cells = <1>; 915 916 gpu_speed_bin: gpu-speed-bin@18b { 917 reg = <0x18b 0x1>; 918 bits = <5 3>; 919 }; 920 }; 921 922 gpi_dma2: dma-controller@800000 { 923 compatible = "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma"; 924 reg = <0 0x00800000 0 0x60000>; 925 926 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 938 939 dma-channels = <12>; 940 dma-channel-mask = <0xfff>; 941 #dma-cells = <3>; 942 943 iommus = <&apps_smmu 0xb6 0x0>; 944 945 status = "disabled"; 946 }; 947 948 qup2: geniqup@8c0000 { 949 compatible = "qcom,geni-se-qup"; 950 reg = <0 0x008c0000 0 0x2000>; 951 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 952 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 953 clock-names = "m-ahb", "s-ahb"; 954 iommus = <&apps_smmu 0xa3 0>; 955 956 #address-cells = <2>; 957 #size-cells = <2>; 958 ranges; 959 960 status = "disabled"; 961 962 i2c16: i2c@880000 { 963 compatible = "qcom,geni-i2c"; 964 reg = <0 0x00880000 0 0x4000>; 965 #address-cells = <1>; 966 #size-cells = <0>; 967 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 968 clock-names = "se"; 969 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 970 power-domains = <&rpmhpd SC8280XP_CX>; 971 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 972 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 973 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 974 interconnect-names = "qup-core", "qup-config", "qup-memory"; 975 976 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 977 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 978 dma-names = "tx", 979 "rx"; 980 981 status = "disabled"; 982 }; 983 984 spi16: spi@880000 { 985 compatible = "qcom,geni-spi"; 986 reg = <0 0x00880000 0 0x4000>; 987 #address-cells = <1>; 988 #size-cells = <0>; 989 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 990 clock-names = "se"; 991 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 992 power-domains = <&rpmhpd SC8280XP_CX>; 993 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 994 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 995 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 996 interconnect-names = "qup-core", "qup-config", "qup-memory"; 997 998 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 999 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1000 dma-names = "tx", 1001 "rx"; 1002 1003 status = "disabled"; 1004 }; 1005 1006 i2c17: i2c@884000 { 1007 compatible = "qcom,geni-i2c"; 1008 reg = <0 0x00884000 0 0x4000>; 1009 #address-cells = <1>; 1010 #size-cells = <0>; 1011 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1012 clock-names = "se"; 1013 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1014 power-domains = <&rpmhpd SC8280XP_CX>; 1015 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1016 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1017 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1018 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1019 1020 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1021 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1022 dma-names = "tx", 1023 "rx"; 1024 1025 status = "disabled"; 1026 }; 1027 1028 spi17: spi@884000 { 1029 compatible = "qcom,geni-spi"; 1030 reg = <0 0x00884000 0 0x4000>; 1031 #address-cells = <1>; 1032 #size-cells = <0>; 1033 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1034 clock-names = "se"; 1035 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1036 power-domains = <&rpmhpd SC8280XP_CX>; 1037 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1038 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1039 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1040 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1041 1042 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1043 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1044 dma-names = "tx", 1045 "rx"; 1046 1047 status = "disabled"; 1048 }; 1049 1050 uart17: serial@884000 { 1051 compatible = "qcom,geni-uart"; 1052 reg = <0 0x00884000 0 0x4000>; 1053 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1054 clock-names = "se"; 1055 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1056 operating-points-v2 = <&qup_opp_table_100mhz>; 1057 power-domains = <&rpmhpd SC8280XP_CX>; 1058 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1059 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; 1060 interconnect-names = "qup-core", "qup-config"; 1061 status = "disabled"; 1062 }; 1063 1064 i2c18: i2c@888000 { 1065 compatible = "qcom,geni-i2c"; 1066 reg = <0 0x00888000 0 0x4000>; 1067 #address-cells = <1>; 1068 #size-cells = <0>; 1069 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1070 clock-names = "se"; 1071 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1072 power-domains = <&rpmhpd SC8280XP_CX>; 1073 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1074 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1075 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1076 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1077 1078 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1079 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1080 dma-names = "tx", 1081 "rx"; 1082 1083 status = "disabled"; 1084 }; 1085 1086 spi18: spi@888000 { 1087 compatible = "qcom,geni-spi"; 1088 reg = <0 0x00888000 0 0x4000>; 1089 #address-cells = <1>; 1090 #size-cells = <0>; 1091 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1092 clock-names = "se"; 1093 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1094 power-domains = <&rpmhpd SC8280XP_CX>; 1095 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1096 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1097 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1098 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1099 1100 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1101 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1102 dma-names = "tx", 1103 "rx"; 1104 1105 status = "disabled"; 1106 }; 1107 1108 uart18: serial@888000 { 1109 compatible = "qcom,geni-uart"; 1110 reg = <0 0x00888000 0 0x4000>; 1111 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1112 clock-names = "se"; 1113 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1114 operating-points-v2 = <&qup_opp_table_100mhz>; 1115 power-domains = <&rpmhpd SC8280XP_CX>; 1116 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1117 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; 1118 interconnect-names = "qup-core", "qup-config"; 1119 1120 pinctrl-0 = <&qup_uart18_default>; 1121 pinctrl-names = "default"; 1122 1123 status = "disabled"; 1124 }; 1125 1126 i2c19: i2c@88c000 { 1127 compatible = "qcom,geni-i2c"; 1128 reg = <0 0x0088c000 0 0x4000>; 1129 #address-cells = <1>; 1130 #size-cells = <0>; 1131 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1132 clock-names = "se"; 1133 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1134 power-domains = <&rpmhpd SC8280XP_CX>; 1135 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1136 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1137 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1138 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1139 1140 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1141 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1142 dma-names = "tx", 1143 "rx"; 1144 1145 status = "disabled"; 1146 }; 1147 1148 spi19: spi@88c000 { 1149 compatible = "qcom,geni-spi"; 1150 reg = <0 0x0088c000 0 0x4000>; 1151 #address-cells = <1>; 1152 #size-cells = <0>; 1153 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1154 clock-names = "se"; 1155 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1156 power-domains = <&rpmhpd SC8280XP_CX>; 1157 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1158 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1159 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1160 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1161 1162 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1163 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1164 dma-names = "tx", 1165 "rx"; 1166 1167 status = "disabled"; 1168 }; 1169 1170 i2c20: i2c@890000 { 1171 compatible = "qcom,geni-i2c"; 1172 reg = <0 0x00890000 0 0x4000>; 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1176 clock-names = "se"; 1177 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1178 power-domains = <&rpmhpd SC8280XP_CX>; 1179 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1180 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1181 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1182 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1183 1184 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1185 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1186 dma-names = "tx", 1187 "rx"; 1188 1189 status = "disabled"; 1190 }; 1191 1192 spi20: spi@890000 { 1193 compatible = "qcom,geni-spi"; 1194 reg = <0 0x00890000 0 0x4000>; 1195 #address-cells = <1>; 1196 #size-cells = <0>; 1197 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1198 clock-names = "se"; 1199 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1200 power-domains = <&rpmhpd SC8280XP_CX>; 1201 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1202 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1203 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1204 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1205 1206 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1207 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1208 dma-names = "tx", 1209 "rx"; 1210 1211 status = "disabled"; 1212 }; 1213 1214 i2c21: i2c@894000 { 1215 compatible = "qcom,geni-i2c"; 1216 reg = <0 0x00894000 0 0x4000>; 1217 clock-names = "se"; 1218 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1219 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1220 #address-cells = <1>; 1221 #size-cells = <0>; 1222 power-domains = <&rpmhpd SC8280XP_CX>; 1223 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1224 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1225 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1226 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1227 1228 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1229 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1230 dma-names = "tx", 1231 "rx"; 1232 1233 status = "disabled"; 1234 }; 1235 1236 spi21: spi@894000 { 1237 compatible = "qcom,geni-spi"; 1238 reg = <0 0x00894000 0 0x4000>; 1239 #address-cells = <1>; 1240 #size-cells = <0>; 1241 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1242 clock-names = "se"; 1243 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1244 power-domains = <&rpmhpd SC8280XP_CX>; 1245 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1246 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1247 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1248 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1249 1250 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1251 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1252 dma-names = "tx", 1253 "rx"; 1254 1255 status = "disabled"; 1256 }; 1257 1258 i2c22: i2c@898000 { 1259 compatible = "qcom,geni-i2c"; 1260 reg = <0 0x00898000 0 0x4000>; 1261 #address-cells = <1>; 1262 #size-cells = <0>; 1263 clock-names = "se"; 1264 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1265 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1266 power-domains = <&rpmhpd SC8280XP_CX>; 1267 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1268 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1269 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1270 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1271 1272 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1273 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1274 dma-names = "tx", 1275 "rx"; 1276 1277 status = "disabled"; 1278 }; 1279 1280 spi22: spi@898000 { 1281 compatible = "qcom,geni-spi"; 1282 reg = <0 0x00898000 0 0x4000>; 1283 #address-cells = <1>; 1284 #size-cells = <0>; 1285 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1286 clock-names = "se"; 1287 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1288 power-domains = <&rpmhpd SC8280XP_CX>; 1289 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1290 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1291 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1292 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1293 1294 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1295 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1296 dma-names = "tx", 1297 "rx"; 1298 1299 status = "disabled"; 1300 }; 1301 1302 i2c23: i2c@89c000 { 1303 compatible = "qcom,geni-i2c"; 1304 reg = <0 0x0089c000 0 0x4000>; 1305 #address-cells = <1>; 1306 #size-cells = <0>; 1307 clock-names = "se"; 1308 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1309 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1310 power-domains = <&rpmhpd SC8280XP_CX>; 1311 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1312 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1313 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1314 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1315 1316 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1317 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1318 dma-names = "tx", 1319 "rx"; 1320 1321 status = "disabled"; 1322 }; 1323 1324 spi23: spi@89c000 { 1325 compatible = "qcom,geni-spi"; 1326 reg = <0 0x0089c000 0 0x4000>; 1327 #address-cells = <1>; 1328 #size-cells = <0>; 1329 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1330 clock-names = "se"; 1331 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1332 power-domains = <&rpmhpd SC8280XP_CX>; 1333 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1334 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1335 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1336 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1337 1338 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1339 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1340 dma-names = "tx", 1341 "rx"; 1342 1343 status = "disabled"; 1344 }; 1345 }; 1346 1347 gpi_dma0: dma-controller@900000 { 1348 compatible = "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma"; 1349 reg = <0 0x00900000 0 0x60000>; 1350 1351 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1352 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1353 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1354 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1355 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1356 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1357 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1358 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1359 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1360 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1361 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1362 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1363 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1364 1365 dma-channels = <13>; 1366 dma-channel-mask = <0x1fff>; 1367 #dma-cells = <3>; 1368 1369 iommus = <&apps_smmu 0x576 0x0>; 1370 1371 status = "disabled"; 1372 }; 1373 1374 qup0: geniqup@9c0000 { 1375 compatible = "qcom,geni-se-qup"; 1376 reg = <0 0x009c0000 0 0x6000>; 1377 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1378 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1379 clock-names = "m-ahb", "s-ahb"; 1380 iommus = <&apps_smmu 0x563 0>; 1381 1382 #address-cells = <2>; 1383 #size-cells = <2>; 1384 ranges; 1385 1386 status = "disabled"; 1387 1388 i2c0: i2c@980000 { 1389 compatible = "qcom,geni-i2c"; 1390 reg = <0 0x00980000 0 0x4000>; 1391 #address-cells = <1>; 1392 #size-cells = <0>; 1393 clock-names = "se"; 1394 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1395 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1396 power-domains = <&rpmhpd SC8280XP_CX>; 1397 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1398 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1399 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1400 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1401 1402 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1403 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1404 dma-names = "tx", 1405 "rx"; 1406 1407 status = "disabled"; 1408 }; 1409 1410 spi0: spi@980000 { 1411 compatible = "qcom,geni-spi"; 1412 reg = <0 0x00980000 0 0x4000>; 1413 #address-cells = <1>; 1414 #size-cells = <0>; 1415 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1416 clock-names = "se"; 1417 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1418 power-domains = <&rpmhpd SC8280XP_CX>; 1419 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1420 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1421 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1422 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1423 1424 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1425 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1426 dma-names = "tx", 1427 "rx"; 1428 1429 status = "disabled"; 1430 }; 1431 1432 i2c1: i2c@984000 { 1433 compatible = "qcom,geni-i2c"; 1434 reg = <0 0x00984000 0 0x4000>; 1435 #address-cells = <1>; 1436 #size-cells = <0>; 1437 clock-names = "se"; 1438 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1439 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1440 power-domains = <&rpmhpd SC8280XP_CX>; 1441 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1442 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1443 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1444 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1445 1446 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1447 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1448 dma-names = "tx", 1449 "rx"; 1450 1451 status = "disabled"; 1452 }; 1453 1454 spi1: spi@984000 { 1455 compatible = "qcom,geni-spi"; 1456 reg = <0 0x00984000 0 0x4000>; 1457 #address-cells = <1>; 1458 #size-cells = <0>; 1459 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1460 clock-names = "se"; 1461 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1462 power-domains = <&rpmhpd SC8280XP_CX>; 1463 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1464 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1465 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1466 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1467 1468 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1469 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1470 dma-names = "tx", 1471 "rx"; 1472 1473 status = "disabled"; 1474 }; 1475 1476 i2c2: i2c@988000 { 1477 compatible = "qcom,geni-i2c"; 1478 reg = <0 0x00988000 0 0x4000>; 1479 #address-cells = <1>; 1480 #size-cells = <0>; 1481 clock-names = "se"; 1482 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1483 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1484 power-domains = <&rpmhpd SC8280XP_CX>; 1485 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1486 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1487 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1488 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1489 1490 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1491 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1492 dma-names = "tx", 1493 "rx"; 1494 1495 status = "disabled"; 1496 }; 1497 1498 spi2: spi@988000 { 1499 compatible = "qcom,geni-spi"; 1500 reg = <0 0x00988000 0 0x4000>; 1501 #address-cells = <1>; 1502 #size-cells = <0>; 1503 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1504 clock-names = "se"; 1505 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1506 power-domains = <&rpmhpd SC8280XP_CX>; 1507 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1508 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1509 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1510 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1511 1512 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1513 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1514 dma-names = "tx", 1515 "rx"; 1516 1517 status = "disabled"; 1518 }; 1519 1520 uart2: serial@988000 { 1521 compatible = "qcom,geni-uart"; 1522 reg = <0 0x00988000 0 0x4000>; 1523 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1524 clock-names = "se"; 1525 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1526 operating-points-v2 = <&qup_opp_table_100mhz>; 1527 power-domains = <&rpmhpd SC8280XP_CX>; 1528 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1529 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1530 interconnect-names = "qup-core", "qup-config"; 1531 status = "disabled"; 1532 }; 1533 1534 i2c3: i2c@98c000 { 1535 compatible = "qcom,geni-i2c"; 1536 reg = <0 0x0098c000 0 0x4000>; 1537 #address-cells = <1>; 1538 #size-cells = <0>; 1539 clock-names = "se"; 1540 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1541 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1542 power-domains = <&rpmhpd SC8280XP_CX>; 1543 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1544 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1545 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1546 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1547 1548 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1549 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1550 dma-names = "tx", 1551 "rx"; 1552 1553 status = "disabled"; 1554 }; 1555 1556 spi3: spi@98c000 { 1557 compatible = "qcom,geni-spi"; 1558 reg = <0 0x0098c000 0 0x4000>; 1559 #address-cells = <1>; 1560 #size-cells = <0>; 1561 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1562 clock-names = "se"; 1563 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1564 power-domains = <&rpmhpd SC8280XP_CX>; 1565 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1566 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1567 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1568 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1569 1570 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1571 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1572 dma-names = "tx", 1573 "rx"; 1574 1575 status = "disabled"; 1576 }; 1577 1578 i2c4: i2c@990000 { 1579 compatible = "qcom,geni-i2c"; 1580 reg = <0 0x00990000 0 0x4000>; 1581 clock-names = "se"; 1582 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1583 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1584 #address-cells = <1>; 1585 #size-cells = <0>; 1586 power-domains = <&rpmhpd SC8280XP_CX>; 1587 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1588 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1589 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1590 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1591 1592 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1593 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1594 dma-names = "tx", 1595 "rx"; 1596 1597 status = "disabled"; 1598 }; 1599 1600 spi4: spi@990000 { 1601 compatible = "qcom,geni-spi"; 1602 reg = <0 0x00990000 0 0x4000>; 1603 #address-cells = <1>; 1604 #size-cells = <0>; 1605 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1606 clock-names = "se"; 1607 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1608 power-domains = <&rpmhpd SC8280XP_CX>; 1609 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1610 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1611 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1612 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1613 1614 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1615 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1616 dma-names = "tx", 1617 "rx"; 1618 1619 status = "disabled"; 1620 }; 1621 1622 i2c5: i2c@994000 { 1623 compatible = "qcom,geni-i2c"; 1624 reg = <0 0x00994000 0 0x4000>; 1625 #address-cells = <1>; 1626 #size-cells = <0>; 1627 clock-names = "se"; 1628 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1629 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1630 power-domains = <&rpmhpd SC8280XP_CX>; 1631 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1632 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1633 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1634 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1635 1636 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1637 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1638 dma-names = "tx", 1639 "rx"; 1640 1641 status = "disabled"; 1642 }; 1643 1644 spi5: spi@994000 { 1645 compatible = "qcom,geni-spi"; 1646 reg = <0 0x00994000 0 0x4000>; 1647 #address-cells = <1>; 1648 #size-cells = <0>; 1649 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1650 clock-names = "se"; 1651 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1652 power-domains = <&rpmhpd SC8280XP_CX>; 1653 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1654 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1655 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1656 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1657 1658 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1659 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1660 dma-names = "tx", 1661 "rx"; 1662 1663 status = "disabled"; 1664 }; 1665 1666 i2c6: i2c@998000 { 1667 compatible = "qcom,geni-i2c"; 1668 reg = <0 0x00998000 0 0x4000>; 1669 #address-cells = <1>; 1670 #size-cells = <0>; 1671 clock-names = "se"; 1672 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1673 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1674 power-domains = <&rpmhpd SC8280XP_CX>; 1675 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1676 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1677 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1678 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1679 1680 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1681 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1682 dma-names = "tx", 1683 "rx"; 1684 1685 status = "disabled"; 1686 }; 1687 1688 spi6: spi@998000 { 1689 compatible = "qcom,geni-spi"; 1690 reg = <0 0x00998000 0 0x4000>; 1691 #address-cells = <1>; 1692 #size-cells = <0>; 1693 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1694 clock-names = "se"; 1695 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1696 power-domains = <&rpmhpd SC8280XP_CX>; 1697 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1698 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1699 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1700 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1701 1702 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1703 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1704 dma-names = "tx", 1705 "rx"; 1706 1707 status = "disabled"; 1708 }; 1709 1710 i2c7: i2c@99c000 { 1711 compatible = "qcom,geni-i2c"; 1712 reg = <0 0x0099c000 0 0x4000>; 1713 #address-cells = <1>; 1714 #size-cells = <0>; 1715 clock-names = "se"; 1716 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1717 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1718 power-domains = <&rpmhpd SC8280XP_CX>; 1719 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1720 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1721 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1722 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1723 1724 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1725 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1726 dma-names = "tx", 1727 "rx"; 1728 1729 status = "disabled"; 1730 }; 1731 1732 spi7: spi@99c000 { 1733 compatible = "qcom,geni-spi"; 1734 reg = <0 0x0099c000 0 0x4000>; 1735 #address-cells = <1>; 1736 #size-cells = <0>; 1737 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1738 clock-names = "se"; 1739 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1740 power-domains = <&rpmhpd SC8280XP_CX>; 1741 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1742 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1743 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1744 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1745 1746 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1747 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1748 dma-names = "tx", 1749 "rx"; 1750 1751 status = "disabled"; 1752 }; 1753 }; 1754 1755 gpi_dma1: dma-controller@a00000 { 1756 compatible = "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma"; 1757 reg = <0 0x00a00000 0 0x60000>; 1758 1759 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1769 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1770 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1771 1772 dma-channels = <12>; 1773 dma-channel-mask = <0xfff>; 1774 #dma-cells = <3>; 1775 1776 iommus = <&apps_smmu 0x96 0x0>; 1777 1778 status = "disabled"; 1779 }; 1780 1781 qup1: geniqup@ac0000 { 1782 compatible = "qcom,geni-se-qup"; 1783 reg = <0 0x00ac0000 0 0x6000>; 1784 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1785 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1786 clock-names = "m-ahb", "s-ahb"; 1787 iommus = <&apps_smmu 0x83 0>; 1788 1789 #address-cells = <2>; 1790 #size-cells = <2>; 1791 ranges; 1792 1793 status = "disabled"; 1794 1795 i2c8: i2c@a80000 { 1796 compatible = "qcom,geni-i2c"; 1797 reg = <0 0x00a80000 0 0x4000>; 1798 #address-cells = <1>; 1799 #size-cells = <0>; 1800 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1801 clock-names = "se"; 1802 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1803 power-domains = <&rpmhpd SC8280XP_CX>; 1804 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1805 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1806 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1807 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1808 1809 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1810 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1811 dma-names = "tx", 1812 "rx"; 1813 1814 status = "disabled"; 1815 }; 1816 1817 spi8: spi@a80000 { 1818 compatible = "qcom,geni-spi"; 1819 reg = <0 0x00a80000 0 0x4000>; 1820 #address-cells = <1>; 1821 #size-cells = <0>; 1822 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1823 clock-names = "se"; 1824 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1825 power-domains = <&rpmhpd SC8280XP_CX>; 1826 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1827 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1828 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1829 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1830 1831 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1832 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1833 dma-names = "tx", 1834 "rx"; 1835 1836 status = "disabled"; 1837 }; 1838 1839 i2c9: i2c@a84000 { 1840 compatible = "qcom,geni-i2c"; 1841 reg = <0 0x00a84000 0 0x4000>; 1842 #address-cells = <1>; 1843 #size-cells = <0>; 1844 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1845 clock-names = "se"; 1846 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1847 power-domains = <&rpmhpd SC8280XP_CX>; 1848 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1849 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1850 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1851 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1852 1853 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1854 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1855 dma-names = "tx", 1856 "rx"; 1857 1858 status = "disabled"; 1859 }; 1860 1861 spi9: spi@a84000 { 1862 compatible = "qcom,geni-spi"; 1863 reg = <0 0x00a84000 0 0x4000>; 1864 #address-cells = <1>; 1865 #size-cells = <0>; 1866 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1867 clock-names = "se"; 1868 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1869 power-domains = <&rpmhpd SC8280XP_CX>; 1870 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1871 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1872 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1873 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1874 1875 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1876 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1877 dma-names = "tx", 1878 "rx"; 1879 1880 status = "disabled"; 1881 }; 1882 1883 i2c10: i2c@a88000 { 1884 compatible = "qcom,geni-i2c"; 1885 reg = <0 0x00a88000 0 0x4000>; 1886 #address-cells = <1>; 1887 #size-cells = <0>; 1888 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1889 clock-names = "se"; 1890 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1891 power-domains = <&rpmhpd SC8280XP_CX>; 1892 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1893 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1894 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1895 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1896 1897 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1898 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1899 dma-names = "tx", 1900 "rx"; 1901 1902 status = "disabled"; 1903 }; 1904 1905 spi10: spi@a88000 { 1906 compatible = "qcom,geni-spi"; 1907 reg = <0 0x00a88000 0 0x4000>; 1908 #address-cells = <1>; 1909 #size-cells = <0>; 1910 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1911 clock-names = "se"; 1912 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1913 power-domains = <&rpmhpd SC8280XP_CX>; 1914 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1915 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1916 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1917 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1918 1919 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1920 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1921 dma-names = "tx", 1922 "rx"; 1923 1924 status = "disabled"; 1925 }; 1926 1927 i2c11: i2c@a8c000 { 1928 compatible = "qcom,geni-i2c"; 1929 reg = <0 0x00a8c000 0 0x4000>; 1930 #address-cells = <1>; 1931 #size-cells = <0>; 1932 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1933 clock-names = "se"; 1934 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1935 power-domains = <&rpmhpd SC8280XP_CX>; 1936 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1937 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1938 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1939 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1940 1941 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1942 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1943 dma-names = "tx", 1944 "rx"; 1945 1946 status = "disabled"; 1947 }; 1948 1949 spi11: spi@a8c000 { 1950 compatible = "qcom,geni-spi"; 1951 reg = <0 0x00a8c000 0 0x4000>; 1952 #address-cells = <1>; 1953 #size-cells = <0>; 1954 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1955 clock-names = "se"; 1956 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1957 power-domains = <&rpmhpd SC8280XP_CX>; 1958 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1959 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1960 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1961 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1962 1963 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1964 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1965 dma-names = "tx", 1966 "rx"; 1967 1968 status = "disabled"; 1969 }; 1970 1971 i2c12: i2c@a90000 { 1972 compatible = "qcom,geni-i2c"; 1973 reg = <0 0x00a90000 0 0x4000>; 1974 #address-cells = <1>; 1975 #size-cells = <0>; 1976 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1977 clock-names = "se"; 1978 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1979 power-domains = <&rpmhpd SC8280XP_CX>; 1980 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1981 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1982 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1983 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1984 1985 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1986 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1987 dma-names = "tx", 1988 "rx"; 1989 1990 status = "disabled"; 1991 }; 1992 1993 spi12: spi@a90000 { 1994 compatible = "qcom,geni-spi"; 1995 reg = <0 0x00a90000 0 0x4000>; 1996 #address-cells = <1>; 1997 #size-cells = <0>; 1998 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1999 clock-names = "se"; 2000 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2001 power-domains = <&rpmhpd SC8280XP_CX>; 2002 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2003 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 2004 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2005 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2006 2007 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 2008 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 2009 dma-names = "tx", 2010 "rx"; 2011 2012 status = "disabled"; 2013 }; 2014 2015 i2c13: i2c@a94000 { 2016 compatible = "qcom,geni-i2c"; 2017 reg = <0 0x00a94000 0 0x4000>; 2018 #address-cells = <1>; 2019 #size-cells = <0>; 2020 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2021 clock-names = "se"; 2022 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2023 power-domains = <&rpmhpd SC8280XP_CX>; 2024 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2025 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 2026 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2027 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2028 2029 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 2030 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 2031 dma-names = "tx", 2032 "rx"; 2033 2034 status = "disabled"; 2035 }; 2036 2037 spi13: spi@a94000 { 2038 compatible = "qcom,geni-spi"; 2039 reg = <0 0x00a94000 0 0x4000>; 2040 #address-cells = <1>; 2041 #size-cells = <0>; 2042 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2043 clock-names = "se"; 2044 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2045 power-domains = <&rpmhpd SC8280XP_CX>; 2046 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2047 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 2048 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2049 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2050 2051 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 2052 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 2053 dma-names = "tx", 2054 "rx"; 2055 2056 status = "disabled"; 2057 }; 2058 2059 i2c14: i2c@a98000 { 2060 compatible = "qcom,geni-i2c"; 2061 reg = <0 0x00a98000 0 0x4000>; 2062 #address-cells = <1>; 2063 #size-cells = <0>; 2064 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2065 clock-names = "se"; 2066 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 2067 power-domains = <&rpmhpd SC8280XP_CX>; 2068 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2069 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 2070 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2071 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2072 2073 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2074 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2075 dma-names = "tx", 2076 "rx"; 2077 2078 status = "disabled"; 2079 }; 2080 2081 spi14: spi@a98000 { 2082 compatible = "qcom,geni-spi"; 2083 reg = <0 0x00a98000 0 0x4000>; 2084 #address-cells = <1>; 2085 #size-cells = <0>; 2086 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2087 clock-names = "se"; 2088 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 2089 power-domains = <&rpmhpd SC8280XP_CX>; 2090 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2091 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 2092 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2093 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2094 2095 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2096 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2097 dma-names = "tx", 2098 "rx"; 2099 2100 status = "disabled"; 2101 }; 2102 2103 i2c15: i2c@a9c000 { 2104 compatible = "qcom,geni-i2c"; 2105 reg = <0 0x00a9c000 0 0x4000>; 2106 #address-cells = <1>; 2107 #size-cells = <0>; 2108 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2109 clock-names = "se"; 2110 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 2111 power-domains = <&rpmhpd SC8280XP_CX>; 2112 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2113 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 2114 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2115 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2116 2117 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2118 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2119 dma-names = "tx", 2120 "rx"; 2121 2122 status = "disabled"; 2123 }; 2124 2125 spi15: spi@a9c000 { 2126 compatible = "qcom,geni-spi"; 2127 reg = <0 0x00a9c000 0 0x4000>; 2128 #address-cells = <1>; 2129 #size-cells = <0>; 2130 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2131 clock-names = "se"; 2132 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 2133 power-domains = <&rpmhpd SC8280XP_CX>; 2134 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2135 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 2136 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2137 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2138 2139 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2140 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2141 dma-names = "tx", 2142 "rx"; 2143 2144 status = "disabled"; 2145 }; 2146 }; 2147 2148 rng: rng@10d3000 { 2149 compatible = "qcom,prng-ee"; 2150 reg = <0 0x010d3000 0 0x1000>; 2151 clocks = <&rpmhcc RPMH_HWKM_CLK>; 2152 clock-names = "core"; 2153 }; 2154 2155 pcie4: pcie@1c00000 { 2156 device_type = "pci"; 2157 compatible = "qcom,pcie-sc8280xp"; 2158 reg = <0x0 0x01c00000 0x0 0x3000>, 2159 <0x0 0x30000000 0x0 0xf1d>, 2160 <0x0 0x30000f20 0x0 0xa8>, 2161 <0x0 0x30001000 0x0 0x1000>, 2162 <0x0 0x30100000 0x0 0x100000>, 2163 <0x0 0x01c03000 0x0 0x1000>; 2164 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2165 #address-cells = <3>; 2166 #size-cells = <2>; 2167 ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>, 2168 <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>; 2169 bus-range = <0x00 0xff>; 2170 2171 dma-coherent; 2172 2173 linux,pci-domain = <6>; 2174 num-lanes = <1>; 2175 2176 msi-map = <0x0 &its 0xe0000 0x10000>; 2177 2178 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2179 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2180 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2181 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 2182 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2183 2184 #interrupt-cells = <1>; 2185 interrupt-map-mask = <0 0 0 0x7>; 2186 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2187 <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 2188 <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 2189 <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 2190 2191 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 2192 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 2193 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 2194 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 2195 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 2196 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2197 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2198 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>, 2199 <&gcc GCC_CNOC_PCIE4_QX_CLK>; 2200 clock-names = "aux", 2201 "cfg", 2202 "bus_master", 2203 "bus_slave", 2204 "slave_q2a", 2205 "ddrss_sf_tbu", 2206 "noc_aggr_4", 2207 "noc_aggr_south_sf", 2208 "cnoc_qx"; 2209 2210 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 2211 assigned-clock-rates = <19200000>; 2212 2213 interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>, 2214 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>; 2215 interconnect-names = "pcie-mem", "cpu-pcie"; 2216 2217 resets = <&gcc GCC_PCIE_4_BCR>; 2218 reset-names = "pci"; 2219 2220 power-domains = <&gcc PCIE_4_GDSC>; 2221 required-opps = <&rpmhpd_opp_nom>; 2222 2223 phys = <&pcie4_phy>; 2224 phy-names = "pciephy"; 2225 2226 status = "disabled"; 2227 2228 pcie4_port0: pcie@0 { 2229 device_type = "pci"; 2230 reg = <0x0 0x0 0x0 0x0 0x0>; 2231 bus-range = <0x01 0xff>; 2232 2233 #address-cells = <3>; 2234 #size-cells = <2>; 2235 ranges; 2236 }; 2237 }; 2238 2239 pcie4_phy: phy@1c06000 { 2240 compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy"; 2241 reg = <0x0 0x01c06000 0x0 0x2000>; 2242 2243 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 2244 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 2245 <&gcc GCC_PCIE_4_CLKREF_CLK>, 2246 <&gcc GCC_PCIE4_PHY_RCHNG_CLK>, 2247 <&gcc GCC_PCIE_4_PIPE_CLK>, 2248 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; 2249 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2250 "pipe", "pipediv2"; 2251 2252 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>; 2253 assigned-clock-rates = <100000000>; 2254 2255 power-domains = <&gcc PCIE_4_GDSC>; 2256 2257 resets = <&gcc GCC_PCIE_4_PHY_BCR>; 2258 reset-names = "phy"; 2259 2260 #clock-cells = <0>; 2261 clock-output-names = "pcie_4_pipe_clk"; 2262 2263 #phy-cells = <0>; 2264 2265 status = "disabled"; 2266 }; 2267 2268 pcie3b: pcie@1c08000 { 2269 device_type = "pci"; 2270 compatible = "qcom,pcie-sc8280xp"; 2271 reg = <0x0 0x01c08000 0x0 0x3000>, 2272 <0x0 0x32000000 0x0 0xf1d>, 2273 <0x0 0x32000f20 0x0 0xa8>, 2274 <0x0 0x32001000 0x0 0x1000>, 2275 <0x0 0x32100000 0x0 0x100000>, 2276 <0x0 0x01c0b000 0x0 0x1000>; 2277 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2278 #address-cells = <3>; 2279 #size-cells = <2>; 2280 ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>, 2281 <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>; 2282 bus-range = <0x00 0xff>; 2283 2284 dma-coherent; 2285 2286 linux,pci-domain = <5>; 2287 num-lanes = <2>; 2288 2289 msi-map = <0x0 &its 0xd0000 0x10000>; 2290 2291 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2292 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2293 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2294 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2295 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2296 2297 #interrupt-cells = <1>; 2298 interrupt-map-mask = <0 0 0 0x7>; 2299 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, 2300 <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 2301 <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>, 2302 <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 2303 2304 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 2305 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 2306 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, 2307 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, 2308 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, 2309 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2310 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2311 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2312 clock-names = "aux", 2313 "cfg", 2314 "bus_master", 2315 "bus_slave", 2316 "slave_q2a", 2317 "ddrss_sf_tbu", 2318 "noc_aggr_4", 2319 "noc_aggr_south_sf"; 2320 2321 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>; 2322 assigned-clock-rates = <19200000>; 2323 2324 interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>, 2325 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>; 2326 interconnect-names = "pcie-mem", "cpu-pcie"; 2327 2328 resets = <&gcc GCC_PCIE_3B_BCR>; 2329 reset-names = "pci"; 2330 2331 power-domains = <&gcc PCIE_3B_GDSC>; 2332 required-opps = <&rpmhpd_opp_nom>; 2333 2334 phys = <&pcie3b_phy>; 2335 phy-names = "pciephy"; 2336 2337 status = "disabled"; 2338 2339 pcie3b_port0: pcie@0 { 2340 device_type = "pci"; 2341 reg = <0x0 0x0 0x0 0x0 0x0>; 2342 bus-range = <0x01 0xff>; 2343 2344 #address-cells = <3>; 2345 #size-cells = <2>; 2346 ranges; 2347 }; 2348 }; 2349 2350 pcie3b_phy: phy@1c0e000 { 2351 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 2352 reg = <0x0 0x01c0e000 0x0 0x2000>; 2353 2354 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 2355 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 2356 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 2357 <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>, 2358 <&gcc GCC_PCIE_3B_PIPE_CLK>, 2359 <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>; 2360 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2361 "pipe", "pipediv2"; 2362 2363 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>; 2364 assigned-clock-rates = <100000000>; 2365 2366 power-domains = <&gcc PCIE_3B_GDSC>; 2367 2368 resets = <&gcc GCC_PCIE_3B_PHY_BCR>; 2369 reset-names = "phy"; 2370 2371 #clock-cells = <0>; 2372 clock-output-names = "pcie_3b_pipe_clk"; 2373 2374 #phy-cells = <0>; 2375 2376 status = "disabled"; 2377 }; 2378 2379 pcie3a: pcie@1c10000 { 2380 device_type = "pci"; 2381 compatible = "qcom,pcie-sc8280xp"; 2382 reg = <0x0 0x01c10000 0x0 0x3000>, 2383 <0x0 0x34000000 0x0 0xf1d>, 2384 <0x0 0x34000f20 0x0 0xa8>, 2385 <0x0 0x34001000 0x0 0x1000>, 2386 <0x0 0x34100000 0x0 0x100000>, 2387 <0x0 0x01c13000 0x0 0x1000>; 2388 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2389 #address-cells = <3>; 2390 #size-cells = <2>; 2391 ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>, 2392 <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>; 2393 bus-range = <0x00 0xff>; 2394 2395 dma-coherent; 2396 2397 linux,pci-domain = <4>; 2398 num-lanes = <4>; 2399 2400 msi-map = <0x0 &its 0xc0000 0x10000>; 2401 2402 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2403 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2404 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2405 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 2406 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2407 2408 #interrupt-cells = <1>; 2409 interrupt-map-mask = <0 0 0 0x7>; 2410 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 2411 <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>, 2412 <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, 2413 <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>; 2414 2415 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 2416 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 2417 <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>, 2418 <&gcc GCC_PCIE_3A_SLV_AXI_CLK>, 2419 <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>, 2420 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2421 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2422 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2423 clock-names = "aux", 2424 "cfg", 2425 "bus_master", 2426 "bus_slave", 2427 "slave_q2a", 2428 "ddrss_sf_tbu", 2429 "noc_aggr_4", 2430 "noc_aggr_south_sf"; 2431 2432 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>; 2433 assigned-clock-rates = <19200000>; 2434 2435 interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>, 2436 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>; 2437 interconnect-names = "pcie-mem", "cpu-pcie"; 2438 2439 resets = <&gcc GCC_PCIE_3A_BCR>; 2440 reset-names = "pci"; 2441 2442 power-domains = <&gcc PCIE_3A_GDSC>; 2443 required-opps = <&rpmhpd_opp_nom>; 2444 2445 phys = <&pcie3a_phy>; 2446 phy-names = "pciephy"; 2447 2448 status = "disabled"; 2449 2450 pcie3a_port0: pcie@0 { 2451 device_type = "pci"; 2452 reg = <0x0 0x0 0x0 0x0 0x0>; 2453 bus-range = <0x01 0xff>; 2454 2455 #address-cells = <3>; 2456 #size-cells = <2>; 2457 ranges; 2458 }; 2459 }; 2460 2461 pcie3a_phy: phy@1c14000 { 2462 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 2463 reg = <0x0 0x01c14000 0x0 0x2000>, 2464 <0x0 0x01c16000 0x0 0x2000>; 2465 2466 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 2467 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 2468 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 2469 <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>, 2470 <&gcc GCC_PCIE_3A_PIPE_CLK>, 2471 <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>; 2472 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2473 "pipe", "pipediv2"; 2474 2475 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>; 2476 assigned-clock-rates = <100000000>; 2477 2478 power-domains = <&gcc PCIE_3A_GDSC>; 2479 2480 resets = <&gcc GCC_PCIE_3A_PHY_BCR>; 2481 reset-names = "phy"; 2482 2483 qcom,4ln-config-sel = <&tcsr 0xa044 1>; 2484 2485 #clock-cells = <0>; 2486 clock-output-names = "pcie_3a_pipe_clk"; 2487 2488 #phy-cells = <0>; 2489 2490 status = "disabled"; 2491 }; 2492 2493 pcie2b: pcie@1c18000 { 2494 device_type = "pci"; 2495 compatible = "qcom,pcie-sc8280xp"; 2496 reg = <0x0 0x01c18000 0x0 0x3000>, 2497 <0x0 0x38000000 0x0 0xf1d>, 2498 <0x0 0x38000f20 0x0 0xa8>, 2499 <0x0 0x38001000 0x0 0x1000>, 2500 <0x0 0x38100000 0x0 0x100000>, 2501 <0x0 0x01c1b000 0x0 0x1000>; 2502 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2503 #address-cells = <3>; 2504 #size-cells = <2>; 2505 ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>, 2506 <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>; 2507 bus-range = <0x00 0xff>; 2508 2509 dma-coherent; 2510 2511 linux,pci-domain = <3>; 2512 num-lanes = <2>; 2513 2514 msi-map = <0x0 &its 0xb0000 0x10000>; 2515 2516 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 2517 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2518 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2519 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 2520 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2521 2522 #interrupt-cells = <1>; 2523 interrupt-map-mask = <0 0 0 0x7>; 2524 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2525 <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 2526 <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 2527 <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; 2528 2529 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2530 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2531 <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>, 2532 <&gcc GCC_PCIE_2B_SLV_AXI_CLK>, 2533 <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>, 2534 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2535 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2536 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2537 clock-names = "aux", 2538 "cfg", 2539 "bus_master", 2540 "bus_slave", 2541 "slave_q2a", 2542 "ddrss_sf_tbu", 2543 "noc_aggr_4", 2544 "noc_aggr_south_sf"; 2545 2546 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>; 2547 assigned-clock-rates = <19200000>; 2548 2549 interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>, 2550 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>; 2551 interconnect-names = "pcie-mem", "cpu-pcie"; 2552 2553 resets = <&gcc GCC_PCIE_2B_BCR>; 2554 reset-names = "pci"; 2555 2556 power-domains = <&gcc PCIE_2B_GDSC>; 2557 required-opps = <&rpmhpd_opp_nom>; 2558 2559 phys = <&pcie2b_phy>; 2560 phy-names = "pciephy"; 2561 2562 status = "disabled"; 2563 2564 pcie2b_port0: pcie@0 { 2565 device_type = "pci"; 2566 reg = <0x0 0x0 0x0 0x0 0x0>; 2567 bus-range = <0x01 0xff>; 2568 2569 #address-cells = <3>; 2570 #size-cells = <2>; 2571 ranges; 2572 }; 2573 }; 2574 2575 pcie2b_phy: phy@1c1e000 { 2576 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 2577 reg = <0x0 0x01c1e000 0x0 0x2000>; 2578 2579 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2580 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2581 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2582 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>, 2583 <&gcc GCC_PCIE_2B_PIPE_CLK>, 2584 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>; 2585 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2586 "pipe", "pipediv2"; 2587 2588 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>; 2589 assigned-clock-rates = <100000000>; 2590 2591 power-domains = <&gcc PCIE_2B_GDSC>; 2592 2593 resets = <&gcc GCC_PCIE_2B_PHY_BCR>; 2594 reset-names = "phy"; 2595 2596 #clock-cells = <0>; 2597 clock-output-names = "pcie_2b_pipe_clk"; 2598 2599 #phy-cells = <0>; 2600 2601 status = "disabled"; 2602 }; 2603 2604 pcie2a: pcie@1c20000 { 2605 device_type = "pci"; 2606 compatible = "qcom,pcie-sc8280xp"; 2607 reg = <0x0 0x01c20000 0x0 0x3000>, 2608 <0x0 0x3c000000 0x0 0xf1d>, 2609 <0x0 0x3c000f20 0x0 0xa8>, 2610 <0x0 0x3c001000 0x0 0x1000>, 2611 <0x0 0x3c100000 0x0 0x100000>, 2612 <0x0 0x01c23000 0x0 0x1000>; 2613 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2614 #address-cells = <3>; 2615 #size-cells = <2>; 2616 ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>, 2617 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>; 2618 bus-range = <0x00 0xff>; 2619 2620 dma-coherent; 2621 2622 linux,pci-domain = <2>; 2623 num-lanes = <4>; 2624 2625 msi-map = <0x0 &its 0xa0000 0x10000>; 2626 2627 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 2628 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, 2629 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, 2630 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>; 2631 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2632 2633 #interrupt-cells = <1>; 2634 interrupt-map-mask = <0 0 0 0x7>; 2635 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 2636 <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 2637 <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 2638 <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; 2639 2640 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2641 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2642 <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>, 2643 <&gcc GCC_PCIE_2A_SLV_AXI_CLK>, 2644 <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>, 2645 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2646 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2647 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2648 clock-names = "aux", 2649 "cfg", 2650 "bus_master", 2651 "bus_slave", 2652 "slave_q2a", 2653 "ddrss_sf_tbu", 2654 "noc_aggr_4", 2655 "noc_aggr_south_sf"; 2656 2657 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>; 2658 assigned-clock-rates = <19200000>; 2659 2660 interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>, 2661 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>; 2662 interconnect-names = "pcie-mem", "cpu-pcie"; 2663 2664 resets = <&gcc GCC_PCIE_2A_BCR>; 2665 reset-names = "pci"; 2666 2667 power-domains = <&gcc PCIE_2A_GDSC>; 2668 required-opps = <&rpmhpd_opp_nom>; 2669 2670 phys = <&pcie2a_phy>; 2671 phy-names = "pciephy"; 2672 2673 status = "disabled"; 2674 2675 pcie2a_port0: pcie@0 { 2676 device_type = "pci"; 2677 reg = <0x0 0x0 0x0 0x0 0x0>; 2678 bus-range = <0x01 0xff>; 2679 2680 #address-cells = <3>; 2681 #size-cells = <2>; 2682 ranges; 2683 }; 2684 }; 2685 2686 pcie2a_phy: phy@1c24000 { 2687 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 2688 reg = <0x0 0x01c24000 0x0 0x2000>, 2689 <0x0 0x01c26000 0x0 0x2000>; 2690 2691 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2692 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2693 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2694 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>, 2695 <&gcc GCC_PCIE_2A_PIPE_CLK>, 2696 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>; 2697 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2698 "pipe", "pipediv2"; 2699 2700 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>; 2701 assigned-clock-rates = <100000000>; 2702 2703 power-domains = <&gcc PCIE_2A_GDSC>; 2704 2705 resets = <&gcc GCC_PCIE_2A_PHY_BCR>; 2706 reset-names = "phy"; 2707 2708 qcom,4ln-config-sel = <&tcsr 0xa044 0>; 2709 2710 #clock-cells = <0>; 2711 clock-output-names = "pcie_2a_pipe_clk"; 2712 2713 #phy-cells = <0>; 2714 2715 status = "disabled"; 2716 }; 2717 2718 ufs_mem_hc: ufshc@1d84000 { 2719 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2720 "jedec,ufs-2.0"; 2721 reg = <0 0x01d84000 0 0x3000>; 2722 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2723 phys = <&ufs_mem_phy>; 2724 phy-names = "ufsphy"; 2725 lanes-per-direction = <2>; 2726 #reset-cells = <1>; 2727 resets = <&gcc GCC_UFS_PHY_BCR>; 2728 reset-names = "rst"; 2729 2730 power-domains = <&gcc UFS_PHY_GDSC>; 2731 required-opps = <&rpmhpd_opp_nom>; 2732 2733 iommus = <&apps_smmu 0xe0 0x0>; 2734 dma-coherent; 2735 2736 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2737 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2738 <&gcc GCC_UFS_PHY_AHB_CLK>, 2739 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2740 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2741 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2742 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2743 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2744 clock-names = "core_clk", 2745 "bus_aggr_clk", 2746 "iface_clk", 2747 "core_clk_unipro", 2748 "ref_clk", 2749 "tx_lane0_sync_clk", 2750 "rx_lane0_sync_clk", 2751 "rx_lane1_sync_clk"; 2752 freq-table-hz = <75000000 300000000>, 2753 <0 0>, 2754 <0 0>, 2755 <75000000 300000000>, 2756 <0 0>, 2757 <0 0>, 2758 <0 0>, 2759 <0 0>; 2760 status = "disabled"; 2761 }; 2762 2763 ufs_mem_phy: phy@1d87000 { 2764 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2765 reg = <0 0x01d87000 0 0x1000>; 2766 2767 clocks = <&rpmhcc RPMH_CXO_CLK>, 2768 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2769 <&gcc GCC_UFS_CARD_CLKREF_CLK>; 2770 clock-names = "ref", 2771 "ref_aux", 2772 "qref"; 2773 2774 power-domains = <&gcc UFS_PHY_GDSC>; 2775 2776 resets = <&ufs_mem_hc 0>; 2777 reset-names = "ufsphy"; 2778 2779 #phy-cells = <0>; 2780 2781 status = "disabled"; 2782 }; 2783 2784 ufs_card_hc: ufshc@1da4000 { 2785 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2786 "jedec,ufs-2.0"; 2787 reg = <0 0x01da4000 0 0x3000>; 2788 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2789 phys = <&ufs_card_phy>; 2790 phy-names = "ufsphy"; 2791 lanes-per-direction = <2>; 2792 #reset-cells = <1>; 2793 resets = <&gcc GCC_UFS_CARD_BCR>; 2794 reset-names = "rst"; 2795 2796 power-domains = <&gcc UFS_CARD_GDSC>; 2797 2798 iommus = <&apps_smmu 0x4a0 0x0>; 2799 dma-coherent; 2800 2801 clocks = <&gcc GCC_UFS_CARD_AXI_CLK>, 2802 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, 2803 <&gcc GCC_UFS_CARD_AHB_CLK>, 2804 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>, 2805 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2806 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>, 2807 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>, 2808 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>; 2809 clock-names = "core_clk", 2810 "bus_aggr_clk", 2811 "iface_clk", 2812 "core_clk_unipro", 2813 "ref_clk", 2814 "tx_lane0_sync_clk", 2815 "rx_lane0_sync_clk", 2816 "rx_lane1_sync_clk"; 2817 freq-table-hz = <75000000 300000000>, 2818 <0 0>, 2819 <0 0>, 2820 <75000000 300000000>, 2821 <0 0>, 2822 <0 0>, 2823 <0 0>, 2824 <0 0>; 2825 status = "disabled"; 2826 }; 2827 2828 ufs_card_phy: phy@1da7000 { 2829 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2830 reg = <0 0x01da7000 0 0x1000>; 2831 2832 clocks = <&rpmhcc RPMH_CXO_CLK>, 2833 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>, 2834 <&gcc GCC_UFS_1_CARD_CLKREF_CLK>; 2835 clock-names = "ref", 2836 "ref_aux", 2837 "qref"; 2838 2839 power-domains = <&gcc UFS_CARD_GDSC>; 2840 2841 resets = <&ufs_card_hc 0>; 2842 reset-names = "ufsphy"; 2843 2844 #phy-cells = <0>; 2845 2846 status = "disabled"; 2847 }; 2848 2849 tcsr_mutex: hwlock@1f40000 { 2850 compatible = "qcom,tcsr-mutex"; 2851 reg = <0x0 0x01f40000 0x0 0x20000>; 2852 #hwlock-cells = <1>; 2853 }; 2854 2855 tcsr: syscon@1fc0000 { 2856 compatible = "qcom,sc8280xp-tcsr", "syscon"; 2857 reg = <0x0 0x01fc0000 0x0 0x30000>; 2858 }; 2859 2860 remoteproc_slpi: remoteproc@2400000 { 2861 compatible = "qcom,sc8280xp-slpi-pas", "qcom,sm8350-slpi-pas"; 2862 reg = <0 0x02400000 0 0x10000>; 2863 2864 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2865 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2866 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2867 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2868 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2869 interrupt-names = "wdog", 2870 "fatal", 2871 "ready", 2872 "handover", 2873 "stop-ack"; 2874 2875 clocks = <&rpmhcc RPMH_CXO_CLK>; 2876 clock-names = "xo"; 2877 2878 power-domains = <&rpmhpd SC8280XP_LCX>, 2879 <&rpmhpd SC8280XP_LMX>; 2880 power-domain-names = "lcx", "lmx"; 2881 2882 memory-region = <&pil_slpi_mem>; 2883 2884 qcom,qmp = <&aoss_qmp>; 2885 2886 qcom,smem-states = <&smp2p_slpi_out 0>; 2887 qcom,smem-state-names = "stop"; 2888 2889 status = "disabled"; 2890 2891 glink-edge { 2892 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2893 IPCC_MPROC_SIGNAL_GLINK_QMP 2894 IRQ_TYPE_EDGE_RISING>; 2895 mboxes = <&ipcc IPCC_CLIENT_SLPI 2896 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2897 2898 label = "slpi"; 2899 qcom,remote-pid = <3>; 2900 2901 fastrpc { 2902 compatible = "qcom,fastrpc"; 2903 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2904 label = "sdsp"; 2905 qcom,non-secure-domain; 2906 #address-cells = <1>; 2907 #size-cells = <0>; 2908 2909 compute-cb@1 { 2910 compatible = "qcom,fastrpc-compute-cb"; 2911 reg = <1>; 2912 iommus = <&apps_smmu 0x0521 0x0>; 2913 }; 2914 2915 compute-cb@2 { 2916 compatible = "qcom,fastrpc-compute-cb"; 2917 reg = <2>; 2918 iommus = <&apps_smmu 0x0522 0x0>; 2919 }; 2920 2921 compute-cb@3 { 2922 compatible = "qcom,fastrpc-compute-cb"; 2923 reg = <3>; 2924 iommus = <&apps_smmu 0x0523 0x0>; 2925 }; 2926 }; 2927 }; 2928 }; 2929 2930 remoteproc_adsp: remoteproc@3000000 { 2931 compatible = "qcom,sc8280xp-adsp-pas"; 2932 reg = <0 0x03000000 0 0x10000>; 2933 2934 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2935 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2936 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2937 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2938 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, 2939 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; 2940 interrupt-names = "wdog", "fatal", "ready", 2941 "handover", "stop-ack", "shutdown-ack"; 2942 2943 clocks = <&rpmhcc RPMH_CXO_CLK>; 2944 clock-names = "xo"; 2945 2946 power-domains = <&rpmhpd SC8280XP_LCX>, 2947 <&rpmhpd SC8280XP_LMX>; 2948 power-domain-names = "lcx", "lmx"; 2949 2950 memory-region = <&pil_adsp_mem>; 2951 2952 qcom,qmp = <&aoss_qmp>; 2953 2954 qcom,smem-states = <&smp2p_adsp_out 0>; 2955 qcom,smem-state-names = "stop"; 2956 2957 status = "disabled"; 2958 2959 remoteproc_adsp_glink: glink-edge { 2960 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2961 IPCC_MPROC_SIGNAL_GLINK_QMP 2962 IRQ_TYPE_EDGE_RISING>; 2963 mboxes = <&ipcc IPCC_CLIENT_LPASS 2964 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2965 2966 label = "lpass"; 2967 qcom,remote-pid = <2>; 2968 2969 gpr { 2970 compatible = "qcom,gpr"; 2971 qcom,glink-channels = "adsp_apps"; 2972 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2973 qcom,intents = <512 20>; 2974 #address-cells = <1>; 2975 #size-cells = <0>; 2976 2977 q6apm: service@1 { 2978 compatible = "qcom,q6apm"; 2979 reg = <GPR_APM_MODULE_IID>; 2980 #sound-dai-cells = <0>; 2981 qcom,protection-domain = "avs/audio", 2982 "msm/adsp/audio_pd"; 2983 q6apmdai: dais { 2984 compatible = "qcom,q6apm-dais"; 2985 iommus = <&apps_smmu 0x0c01 0x0>; 2986 }; 2987 2988 q6apmbedai: bedais { 2989 compatible = "qcom,q6apm-lpass-dais"; 2990 #sound-dai-cells = <1>; 2991 }; 2992 }; 2993 2994 q6prm: service@2 { 2995 compatible = "qcom,q6prm"; 2996 reg = <GPR_PRM_MODULE_IID>; 2997 qcom,protection-domain = "avs/audio", 2998 "msm/adsp/audio_pd"; 2999 q6prmcc: clock-controller { 3000 compatible = "qcom,q6prm-lpass-clocks"; 3001 #clock-cells = <2>; 3002 }; 3003 }; 3004 }; 3005 }; 3006 }; 3007 3008 rxmacro: rxmacro@3200000 { 3009 compatible = "qcom,sc8280xp-lpass-rx-macro"; 3010 reg = <0 0x03200000 0 0x1000>; 3011 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3012 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3013 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3014 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3015 <&vamacro>; 3016 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 3017 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3018 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3019 assigned-clock-rates = <19200000>, <19200000>; 3020 3021 clock-output-names = "mclk"; 3022 #clock-cells = <0>; 3023 #sound-dai-cells = <1>; 3024 3025 pinctrl-names = "default"; 3026 pinctrl-0 = <&rx_swr_default>; 3027 3028 status = "disabled"; 3029 }; 3030 3031 swr1: soundwire@3210000 { 3032 compatible = "qcom,soundwire-v1.6.0"; 3033 reg = <0 0x03210000 0 0x2000>; 3034 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 3035 clocks = <&rxmacro>; 3036 clock-names = "iface"; 3037 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 3038 reset-names = "swr_audio_cgcr"; 3039 label = "RX"; 3040 3041 qcom,din-ports = <0>; 3042 qcom,dout-ports = <5>; 3043 3044 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 3045 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; 3046 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 3047 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>; 3048 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>; 3049 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 3050 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>; 3051 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 3052 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 3053 3054 #sound-dai-cells = <1>; 3055 #address-cells = <2>; 3056 #size-cells = <0>; 3057 3058 status = "disabled"; 3059 }; 3060 3061 txmacro: txmacro@3220000 { 3062 compatible = "qcom,sc8280xp-lpass-tx-macro"; 3063 reg = <0 0x03220000 0 0x1000>; 3064 pinctrl-names = "default"; 3065 pinctrl-0 = <&tx_swr_default>; 3066 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3067 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3068 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3069 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3070 <&vamacro>; 3071 3072 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 3073 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3074 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3075 assigned-clock-rates = <19200000>, <19200000>; 3076 clock-output-names = "mclk"; 3077 3078 #clock-cells = <0>; 3079 #sound-dai-cells = <1>; 3080 3081 status = "disabled"; 3082 }; 3083 3084 wsamacro: codec@3240000 { 3085 compatible = "qcom,sc8280xp-lpass-wsa-macro"; 3086 reg = <0 0x03240000 0 0x1000>; 3087 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3088 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3089 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3090 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3091 <&vamacro>; 3092 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 3093 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3094 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3095 assigned-clock-rates = <19200000>, <19200000>; 3096 3097 #clock-cells = <0>; 3098 clock-output-names = "mclk"; 3099 #sound-dai-cells = <1>; 3100 3101 pinctrl-names = "default"; 3102 pinctrl-0 = <&wsa_swr_default>; 3103 3104 status = "disabled"; 3105 }; 3106 3107 swr0: soundwire@3250000 { 3108 reg = <0 0x03250000 0 0x2000>; 3109 compatible = "qcom,soundwire-v1.6.0"; 3110 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 3111 clocks = <&wsamacro>; 3112 clock-names = "iface"; 3113 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; 3114 reset-names = "swr_audio_cgcr"; 3115 label = "WSA"; 3116 3117 qcom,din-ports = <2>; 3118 qcom,dout-ports = <6>; 3119 3120 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 3121 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 3122 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 3123 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3124 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3125 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3126 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 3127 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3128 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3129 3130 #sound-dai-cells = <1>; 3131 #address-cells = <2>; 3132 #size-cells = <0>; 3133 3134 status = "disabled"; 3135 }; 3136 3137 lpass_audiocc: clock-controller@32a9000 { 3138 compatible = "qcom,sc8280xp-lpassaudiocc"; 3139 reg = <0 0x032a9000 0 0x1000>; 3140 #clock-cells = <1>; 3141 #reset-cells = <1>; 3142 }; 3143 3144 swr2: soundwire@3330000 { 3145 compatible = "qcom,soundwire-v1.6.0"; 3146 reg = <0 0x03330000 0 0x2000>; 3147 interrupts = <GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>, 3148 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 3149 interrupt-names = "core", "wakeup"; 3150 3151 clocks = <&txmacro>; 3152 clock-names = "iface"; 3153 resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; 3154 reset-names = "swr_audio_cgcr"; 3155 label = "TX"; 3156 #sound-dai-cells = <1>; 3157 #address-cells = <2>; 3158 #size-cells = <0>; 3159 3160 qcom,din-ports = <4>; 3161 qcom,dout-ports = <0>; 3162 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 3163 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>; 3164 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 3165 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 3166 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 3167 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 3168 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 3169 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 3170 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>; 3171 3172 status = "disabled"; 3173 }; 3174 3175 vamacro: codec@3370000 { 3176 compatible = "qcom,sc8280xp-lpass-va-macro"; 3177 reg = <0 0x03370000 0 0x1000>; 3178 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3179 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3180 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3181 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3182 clock-names = "mclk", "macro", "dcodec", "npl"; 3183 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3184 assigned-clock-rates = <19200000>; 3185 3186 #clock-cells = <0>; 3187 clock-output-names = "fsgen"; 3188 #sound-dai-cells = <1>; 3189 3190 status = "disabled"; 3191 }; 3192 3193 lpass_tlmm: pinctrl@33c0000 { 3194 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl"; 3195 reg = <0 0x33c0000 0x0 0x20000>, 3196 <0 0x3550000 0x0 0x10000>; 3197 gpio-controller; 3198 #gpio-cells = <2>; 3199 gpio-ranges = <&lpass_tlmm 0 0 19>; 3200 3201 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3202 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3203 clock-names = "core", "audio"; 3204 3205 status = "disabled"; 3206 3207 tx_swr_default: tx-swr-default-state { 3208 clk-pins { 3209 pins = "gpio0"; 3210 function = "swr_tx_clk"; 3211 drive-strength = <2>; 3212 slew-rate = <1>; 3213 bias-disable; 3214 }; 3215 3216 data-pins { 3217 pins = "gpio1", "gpio2"; 3218 function = "swr_tx_data"; 3219 drive-strength = <2>; 3220 slew-rate = <1>; 3221 bias-bus-hold; 3222 }; 3223 }; 3224 3225 rx_swr_default: rx-swr-default-state { 3226 clk-pins { 3227 pins = "gpio3"; 3228 function = "swr_rx_clk"; 3229 drive-strength = <2>; 3230 slew-rate = <1>; 3231 bias-disable; 3232 }; 3233 3234 data-pins { 3235 pins = "gpio4", "gpio5"; 3236 function = "swr_rx_data"; 3237 drive-strength = <2>; 3238 slew-rate = <1>; 3239 bias-bus-hold; 3240 }; 3241 }; 3242 3243 dmic01_default: dmic01-default-state { 3244 clk-pins { 3245 pins = "gpio6"; 3246 function = "dmic1_clk"; 3247 drive-strength = <8>; 3248 output-high; 3249 }; 3250 3251 data-pins { 3252 pins = "gpio7"; 3253 function = "dmic1_data"; 3254 drive-strength = <8>; 3255 input-enable; 3256 }; 3257 }; 3258 3259 dmic01_sleep: dmic01-sleep-state { 3260 clk-pins { 3261 pins = "gpio6"; 3262 function = "dmic1_clk"; 3263 drive-strength = <2>; 3264 bias-disable; 3265 output-low; 3266 }; 3267 3268 data-pins { 3269 pins = "gpio7"; 3270 function = "dmic1_data"; 3271 drive-strength = <2>; 3272 bias-pull-down; 3273 input-enable; 3274 }; 3275 }; 3276 3277 dmic23_default: dmic23-default-state { 3278 clk-pins { 3279 pins = "gpio8"; 3280 function = "dmic2_clk"; 3281 drive-strength = <8>; 3282 output-high; 3283 }; 3284 3285 data-pins { 3286 pins = "gpio9"; 3287 function = "dmic2_data"; 3288 drive-strength = <8>; 3289 input-enable; 3290 }; 3291 }; 3292 3293 dmic23_sleep: dmic23-sleep-state { 3294 clk-pins { 3295 pins = "gpio8"; 3296 function = "dmic2_clk"; 3297 drive-strength = <2>; 3298 bias-disable; 3299 output-low; 3300 }; 3301 3302 data-pins { 3303 pins = "gpio9"; 3304 function = "dmic2_data"; 3305 drive-strength = <2>; 3306 bias-pull-down; 3307 input-enable; 3308 }; 3309 }; 3310 3311 wsa_swr_default: wsa-swr-default-state { 3312 clk-pins { 3313 pins = "gpio10"; 3314 function = "wsa_swr_clk"; 3315 drive-strength = <2>; 3316 slew-rate = <1>; 3317 bias-disable; 3318 }; 3319 3320 data-pins { 3321 pins = "gpio11"; 3322 function = "wsa_swr_data"; 3323 drive-strength = <2>; 3324 slew-rate = <1>; 3325 bias-bus-hold; 3326 }; 3327 }; 3328 3329 wsa2_swr_default: wsa2-swr-default-state { 3330 clk-pins { 3331 pins = "gpio15"; 3332 function = "wsa2_swr_clk"; 3333 drive-strength = <2>; 3334 slew-rate = <1>; 3335 bias-disable; 3336 }; 3337 3338 data-pins { 3339 pins = "gpio16"; 3340 function = "wsa2_swr_data"; 3341 drive-strength = <2>; 3342 slew-rate = <1>; 3343 bias-bus-hold; 3344 }; 3345 }; 3346 }; 3347 3348 lpasscc: clock-controller@33e0000 { 3349 compatible = "qcom,sc8280xp-lpasscc"; 3350 reg = <0 0x033e0000 0 0x12000>; 3351 #clock-cells = <1>; 3352 #reset-cells = <1>; 3353 }; 3354 3355 gpu: gpu@3d00000 { 3356 compatible = "qcom,adreno-690.0", "qcom,adreno"; 3357 3358 reg = <0 0x03d00000 0 0x40000>, 3359 <0 0x03d9e000 0 0x1000>, 3360 <0 0x03d61000 0 0x800>; 3361 reg-names = "kgsl_3d0_reg_memory", 3362 "cx_mem", 3363 "cx_dbgc"; 3364 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 3365 iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>; 3366 operating-points-v2 = <&gpu_opp_table>; 3367 3368 qcom,gmu = <&gmu>; 3369 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 3370 interconnect-names = "gfx-mem"; 3371 #cooling-cells = <2>; 3372 3373 status = "disabled"; 3374 3375 gpu_zap_shader: zap-shader { 3376 memory-region = <&pil_gpu_mem>; 3377 }; 3378 3379 gpu_opp_table: opp-table { 3380 compatible = "operating-points-v2"; 3381 3382 opp-270000000 { 3383 opp-hz = /bits/ 64 <270000000>; 3384 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3385 opp-peak-kBps = <451000>; 3386 }; 3387 3388 opp-410000000 { 3389 opp-hz = /bits/ 64 <410000000>; 3390 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3391 opp-peak-kBps = <1555000>; 3392 }; 3393 3394 opp-500000000 { 3395 opp-hz = /bits/ 64 <500000000>; 3396 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3397 opp-peak-kBps = <1555000>; 3398 }; 3399 3400 opp-547000000 { 3401 opp-hz = /bits/ 64 <547000000>; 3402 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 3403 opp-peak-kBps = <1555000>; 3404 }; 3405 3406 opp-606000000 { 3407 opp-hz = /bits/ 64 <606000000>; 3408 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3409 opp-peak-kBps = <2736000>; 3410 }; 3411 3412 opp-640000000 { 3413 opp-hz = /bits/ 64 <640000000>; 3414 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3415 opp-peak-kBps = <2736000>; 3416 }; 3417 3418 opp-655000000 { 3419 opp-hz = /bits/ 64 <655000000>; 3420 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3421 opp-peak-kBps = <2736000>; 3422 }; 3423 3424 opp-690000000 { 3425 opp-hz = /bits/ 64 <690000000>; 3426 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3427 opp-peak-kBps = <2736000>; 3428 }; 3429 }; 3430 }; 3431 3432 gmu: gmu@3d6a000 { 3433 compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu"; 3434 reg = <0 0x03d6a000 0 0x34000>, 3435 <0 0x03de0000 0 0x10000>, 3436 <0 0x0b290000 0 0x10000>; 3437 reg-names = "gmu", "rscc", "gmu_pdc"; 3438 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 3439 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 3440 interrupt-names = "hfi", "gmu"; 3441 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 3442 <&gpucc GPU_CC_CXO_CLK>, 3443 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 3444 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3445 <&gpucc GPU_CC_AHB_CLK>, 3446 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3447 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 3448 clock-names = "gmu", 3449 "cxo", 3450 "axi", 3451 "memnoc", 3452 "ahb", 3453 "hub", 3454 "smmu_vote"; 3455 power-domains = <&gpucc GPU_CC_CX_GDSC>, 3456 <&gpucc GPU_CC_GX_GDSC>; 3457 power-domain-names = "cx", 3458 "gx"; 3459 iommus = <&gpu_smmu 5 0xc00>; 3460 operating-points-v2 = <&gmu_opp_table>; 3461 3462 gmu_opp_table: opp-table { 3463 compatible = "operating-points-v2"; 3464 3465 opp-200000000 { 3466 opp-hz = /bits/ 64 <200000000>; 3467 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3468 }; 3469 3470 opp-500000000 { 3471 opp-hz = /bits/ 64 <500000000>; 3472 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3473 }; 3474 }; 3475 }; 3476 3477 gpucc: clock-controller@3d90000 { 3478 compatible = "qcom,sc8280xp-gpucc"; 3479 reg = <0 0x03d90000 0 0x9000>; 3480 clocks = <&rpmhcc RPMH_CXO_CLK>, 3481 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3482 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3483 clock-names = "bi_tcxo", 3484 "gcc_gpu_gpll0_clk_src", 3485 "gcc_gpu_gpll0_div_clk_src"; 3486 3487 power-domains = <&rpmhpd SC8280XP_GFX>; 3488 #clock-cells = <1>; 3489 #reset-cells = <1>; 3490 #power-domain-cells = <1>; 3491 }; 3492 3493 gpu_smmu: iommu@3da0000 { 3494 compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu", 3495 "qcom,smmu-500", "arm,mmu-500"; 3496 reg = <0 0x03da0000 0 0x20000>; 3497 #iommu-cells = <2>; 3498 #global-interrupts = <2>; 3499 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 3500 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 3501 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 3502 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 3503 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 3504 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 3505 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 3506 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 3507 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 3508 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 3509 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 3510 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 3511 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, 3512 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>; 3513 3514 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3515 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 3516 <&gpucc GPU_CC_AHB_CLK>, 3517 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 3518 <&gpucc GPU_CC_CX_GMU_CLK>, 3519 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3520 <&gpucc GPU_CC_HUB_AON_CLK>; 3521 clock-names = "gcc_gpu_memnoc_gfx_clk", 3522 "gcc_gpu_snoc_dvm_gfx_clk", 3523 "gpu_cc_ahb_clk", 3524 "gpu_cc_hlos1_vote_gpu_smmu_clk", 3525 "gpu_cc_cx_gmu_clk", 3526 "gpu_cc_hub_cx_int_clk", 3527 "gpu_cc_hub_aon_clk"; 3528 3529 power-domains = <&gpucc GPU_CC_CX_GDSC>; 3530 dma-coherent; 3531 }; 3532 3533 sdc2: mmc@8804000 { 3534 compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5"; 3535 reg = <0 0x08804000 0 0x1000>; 3536 3537 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3538 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3539 interrupt-names = "hc_irq", "pwr_irq"; 3540 3541 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3542 <&gcc GCC_SDCC2_APPS_CLK>, 3543 <&rpmhcc RPMH_CXO_CLK>; 3544 clock-names = "iface", "core", "xo"; 3545 resets = <&gcc GCC_SDCC2_BCR>; 3546 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3547 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 3548 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3549 iommus = <&apps_smmu 0x4e0 0x0>; 3550 power-domains = <&rpmhpd SC8280XP_CX>; 3551 operating-points-v2 = <&sdc2_opp_table>; 3552 bus-width = <4>; 3553 dma-coherent; 3554 3555 status = "disabled"; 3556 3557 sdc2_opp_table: opp-table { 3558 compatible = "operating-points-v2"; 3559 3560 opp-100000000 { 3561 opp-hz = /bits/ 64 <100000000>; 3562 required-opps = <&rpmhpd_opp_low_svs>; 3563 opp-peak-kBps = <1800000 400000>; 3564 opp-avg-kBps = <100000 0>; 3565 }; 3566 3567 opp-202000000 { 3568 opp-hz = /bits/ 64 <202000000>; 3569 required-opps = <&rpmhpd_opp_svs_l1>; 3570 opp-peak-kBps = <5400000 1600000>; 3571 opp-avg-kBps = <200000 0>; 3572 }; 3573 }; 3574 }; 3575 3576 usb_0_hsphy: phy@88e5000 { 3577 compatible = "qcom,sc8280xp-usb-hs-phy", 3578 "qcom,usb-snps-hs-5nm-phy"; 3579 reg = <0 0x088e5000 0 0x400>; 3580 clocks = <&rpmhcc RPMH_CXO_CLK>; 3581 clock-names = "ref"; 3582 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3583 3584 #phy-cells = <0>; 3585 3586 status = "disabled"; 3587 }; 3588 3589 usb_2_hsphy0: phy@88e7000 { 3590 compatible = "qcom,sc8280xp-usb-hs-phy", 3591 "qcom,usb-snps-hs-5nm-phy"; 3592 reg = <0 0x088e7000 0 0x400>; 3593 clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>; 3594 clock-names = "ref"; 3595 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 3596 3597 #phy-cells = <0>; 3598 3599 status = "disabled"; 3600 }; 3601 3602 usb_2_hsphy1: phy@88e8000 { 3603 compatible = "qcom,sc8280xp-usb-hs-phy", 3604 "qcom,usb-snps-hs-5nm-phy"; 3605 reg = <0 0x088e8000 0 0x400>; 3606 clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>; 3607 clock-names = "ref"; 3608 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 3609 3610 #phy-cells = <0>; 3611 3612 status = "disabled"; 3613 }; 3614 3615 usb_2_hsphy2: phy@88e9000 { 3616 compatible = "qcom,sc8280xp-usb-hs-phy", 3617 "qcom,usb-snps-hs-5nm-phy"; 3618 reg = <0 0x088e9000 0 0x400>; 3619 clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>; 3620 clock-names = "ref"; 3621 resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>; 3622 3623 #phy-cells = <0>; 3624 3625 status = "disabled"; 3626 }; 3627 3628 usb_2_hsphy3: phy@88ea000 { 3629 compatible = "qcom,sc8280xp-usb-hs-phy", 3630 "qcom,usb-snps-hs-5nm-phy"; 3631 reg = <0 0x088ea000 0 0x400>; 3632 clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>; 3633 clock-names = "ref"; 3634 resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>; 3635 3636 #phy-cells = <0>; 3637 3638 status = "disabled"; 3639 }; 3640 3641 usb_0_qmpphy: phy@88eb000 { 3642 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 3643 reg = <0 0x088eb000 0 0x4000>; 3644 3645 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3646 <&gcc GCC_USB4_EUD_CLKREF_CLK>, 3647 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3648 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3649 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3650 3651 power-domains = <&gcc USB30_PRIM_GDSC>; 3652 3653 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3654 <&gcc GCC_USB4_DP_PHY_PRIM_BCR>; 3655 reset-names = "phy", "common"; 3656 3657 #clock-cells = <1>; 3658 #phy-cells = <1>; 3659 3660 status = "disabled"; 3661 3662 ports { 3663 #address-cells = <1>; 3664 #size-cells = <0>; 3665 3666 port@0 { 3667 reg = <0>; 3668 3669 usb_0_qmpphy_out: endpoint {}; 3670 }; 3671 3672 port@1 { 3673 reg = <1>; 3674 3675 usb_0_qmpphy_usb_ss_in: endpoint { 3676 remote-endpoint = <&usb_0_dwc3_ss>; 3677 }; 3678 }; 3679 3680 port@2 { 3681 reg = <2>; 3682 3683 usb_0_qmpphy_dp_in: endpoint {}; 3684 }; 3685 }; 3686 }; 3687 3688 usb_2_qmpphy0: phy@88ef000 { 3689 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 3690 reg = <0 0x088ef000 0 0x2000>; 3691 3692 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 3693 <&gcc GCC_USB3_MP0_CLKREF_CLK>, 3694 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 3695 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 3696 clock-names = "aux", "ref", "com_aux", "pipe"; 3697 3698 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 3699 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 3700 reset-names = "phy", "phy_phy"; 3701 3702 power-domains = <&gcc USB30_MP_GDSC>; 3703 3704 #clock-cells = <0>; 3705 clock-output-names = "usb2_phy0_pipe_clk"; 3706 3707 #phy-cells = <0>; 3708 3709 status = "disabled"; 3710 }; 3711 3712 usb_2_qmpphy1: phy@88f1000 { 3713 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 3714 reg = <0 0x088f1000 0 0x2000>; 3715 3716 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 3717 <&gcc GCC_USB3_MP1_CLKREF_CLK>, 3718 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 3719 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 3720 clock-names = "aux", "ref", "com_aux", "pipe"; 3721 3722 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, 3723 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 3724 reset-names = "phy", "phy_phy"; 3725 3726 power-domains = <&gcc USB30_MP_GDSC>; 3727 3728 #clock-cells = <0>; 3729 clock-output-names = "usb2_phy1_pipe_clk"; 3730 3731 #phy-cells = <0>; 3732 3733 status = "disabled"; 3734 }; 3735 3736 refgen: regulator@8900000 { 3737 compatible = "qcom,sc8280xp-refgen-regulator", 3738 "qcom,sm8250-refgen-regulator"; 3739 reg = <0x0 0x08900000 0x0 0x96>; 3740 }; 3741 3742 usb_1_hsphy: phy@8902000 { 3743 compatible = "qcom,sc8280xp-usb-hs-phy", 3744 "qcom,usb-snps-hs-5nm-phy"; 3745 reg = <0 0x08902000 0 0x400>; 3746 #phy-cells = <0>; 3747 3748 clocks = <&rpmhcc RPMH_CXO_CLK>; 3749 clock-names = "ref"; 3750 3751 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3752 3753 status = "disabled"; 3754 }; 3755 3756 usb_1_qmpphy: phy@8903000 { 3757 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 3758 reg = <0 0x08903000 0 0x4000>; 3759 3760 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3761 <&gcc GCC_USB4_CLKREF_CLK>, 3762 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 3763 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3764 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3765 3766 power-domains = <&gcc USB30_SEC_GDSC>; 3767 3768 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 3769 <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>; 3770 reset-names = "phy", "common"; 3771 3772 #clock-cells = <1>; 3773 #phy-cells = <1>; 3774 3775 status = "disabled"; 3776 3777 ports { 3778 #address-cells = <1>; 3779 #size-cells = <0>; 3780 3781 port@0 { 3782 reg = <0>; 3783 3784 usb_1_qmpphy_out: endpoint {}; 3785 }; 3786 3787 port@1 { 3788 reg = <1>; 3789 3790 usb_1_qmpphy_usb_ss_in: endpoint { 3791 remote-endpoint = <&usb_1_dwc3_ss>; 3792 }; 3793 }; 3794 3795 port@2 { 3796 reg = <2>; 3797 3798 usb_1_qmpphy_dp_in: endpoint {}; 3799 }; 3800 }; 3801 }; 3802 3803 mdss1_dp0_phy: phy@8909a00 { 3804 compatible = "qcom,sc8280xp-dp-phy"; 3805 reg = <0 0x08909a00 0 0x19c>, 3806 <0 0x08909200 0 0xec>, 3807 <0 0x08909600 0 0xec>, 3808 <0 0x08909000 0 0x1c8>; 3809 3810 clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 3811 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 3812 clock-names = "aux", "cfg_ahb"; 3813 power-domains = <&rpmhpd SC8280XP_MX>; 3814 3815 #clock-cells = <1>; 3816 #phy-cells = <0>; 3817 3818 status = "disabled"; 3819 }; 3820 3821 mdss1_dp1_phy: phy@890ca00 { 3822 compatible = "qcom,sc8280xp-dp-phy"; 3823 reg = <0 0x0890ca00 0 0x19c>, 3824 <0 0x0890c200 0 0xec>, 3825 <0 0x0890c600 0 0xec>, 3826 <0 0x0890c000 0 0x1c8>; 3827 3828 clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 3829 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 3830 clock-names = "aux", "cfg_ahb"; 3831 power-domains = <&rpmhpd SC8280XP_MX>; 3832 3833 #clock-cells = <1>; 3834 #phy-cells = <0>; 3835 3836 status = "disabled"; 3837 }; 3838 3839 pmu@9091000 { 3840 compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3841 reg = <0 0x09091000 0 0x1000>; 3842 3843 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3844 3845 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3846 3847 operating-points-v2 = <&llcc_bwmon_opp_table>; 3848 3849 llcc_bwmon_opp_table: opp-table { 3850 compatible = "operating-points-v2"; 3851 3852 opp-0 { 3853 opp-peak-kBps = <762000>; 3854 }; 3855 opp-1 { 3856 opp-peak-kBps = <1720000>; 3857 }; 3858 opp-2 { 3859 opp-peak-kBps = <2086000>; 3860 }; 3861 opp-3 { 3862 opp-peak-kBps = <2597000>; 3863 }; 3864 opp-4 { 3865 opp-peak-kBps = <2929000>; 3866 }; 3867 opp-5 { 3868 opp-peak-kBps = <3879000>; 3869 }; 3870 opp-6 { 3871 opp-peak-kBps = <5161000>; 3872 }; 3873 opp-7 { 3874 opp-peak-kBps = <5931000>; 3875 }; 3876 opp-8 { 3877 opp-peak-kBps = <6515000>; 3878 }; 3879 opp-9 { 3880 opp-peak-kBps = <7980000>; 3881 }; 3882 opp-10 { 3883 opp-peak-kBps = <8136000>; 3884 }; 3885 opp-11 { 3886 opp-peak-kBps = <10437000>; 3887 }; 3888 opp-12 { 3889 opp-peak-kBps = <12191000>; 3890 }; 3891 }; 3892 }; 3893 3894 pmu@90b6400 { 3895 compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon"; 3896 reg = <0 0x090b6400 0 0x600>; 3897 3898 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3899 3900 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3901 operating-points-v2 = <&cpu_bwmon_opp_table>; 3902 3903 cpu_bwmon_opp_table: opp-table { 3904 compatible = "operating-points-v2"; 3905 3906 opp-0 { 3907 opp-peak-kBps = <2288000>; 3908 }; 3909 opp-1 { 3910 opp-peak-kBps = <4577000>; 3911 }; 3912 opp-2 { 3913 opp-peak-kBps = <7110000>; 3914 }; 3915 opp-3 { 3916 opp-peak-kBps = <9155000>; 3917 }; 3918 opp-4 { 3919 opp-peak-kBps = <12298000>; 3920 }; 3921 opp-5 { 3922 opp-peak-kBps = <14236000>; 3923 }; 3924 opp-6 { 3925 opp-peak-kBps = <15258001>; 3926 }; 3927 }; 3928 }; 3929 3930 system-cache-controller@9200000 { 3931 compatible = "qcom,sc8280xp-llcc"; 3932 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 3933 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 3934 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, 3935 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, 3936 <0 0x09600000 0 0x58000>; 3937 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 3938 "llcc3_base", "llcc4_base", "llcc5_base", 3939 "llcc6_base", "llcc7_base", "llcc_broadcast_base"; 3940 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3941 }; 3942 3943 usb_2: usb@a4f8800 { 3944 compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3"; 3945 reg = <0 0x0a4f8800 0 0x400>; 3946 #address-cells = <2>; 3947 #size-cells = <2>; 3948 ranges; 3949 3950 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, 3951 <&gcc GCC_USB30_MP_MASTER_CLK>, 3952 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, 3953 <&gcc GCC_USB30_MP_SLEEP_CLK>, 3954 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 3955 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3956 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 3957 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 3958 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3959 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 3960 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 3961 3962 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 3963 <&gcc GCC_USB30_MP_MASTER_CLK>; 3964 assigned-clock-rates = <19200000>, <200000000>; 3965 3966 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 3967 <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 3968 <&intc GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>, 3969 <&intc GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, 3970 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3971 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3972 <&intc GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>, 3973 <&intc GIC_SPI 859 IRQ_TYPE_LEVEL_HIGH>, 3974 <&pdc 127 IRQ_TYPE_EDGE_BOTH>, 3975 <&pdc 126 IRQ_TYPE_EDGE_BOTH>, 3976 <&pdc 129 IRQ_TYPE_EDGE_BOTH>, 3977 <&pdc 128 IRQ_TYPE_EDGE_BOTH>, 3978 <&pdc 131 IRQ_TYPE_EDGE_BOTH>, 3979 <&pdc 130 IRQ_TYPE_EDGE_BOTH>, 3980 <&pdc 133 IRQ_TYPE_EDGE_BOTH>, 3981 <&pdc 132 IRQ_TYPE_EDGE_BOTH>, 3982 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, 3983 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 3984 3985 interrupt-names = "pwr_event_1", "pwr_event_2", 3986 "pwr_event_3", "pwr_event_4", 3987 "hs_phy_1", "hs_phy_2", 3988 "hs_phy_3", "hs_phy_4", 3989 "dp_hs_phy_1", "dm_hs_phy_1", 3990 "dp_hs_phy_2", "dm_hs_phy_2", 3991 "dp_hs_phy_3", "dm_hs_phy_3", 3992 "dp_hs_phy_4", "dm_hs_phy_4", 3993 "ss_phy_1", "ss_phy_2"; 3994 3995 power-domains = <&gcc USB30_MP_GDSC>; 3996 required-opps = <&rpmhpd_opp_nom>; 3997 3998 resets = <&gcc GCC_USB30_MP_BCR>; 3999 4000 interconnects = <&aggre1_noc MASTER_USB3_MP 0 &mc_virt SLAVE_EBI1 0>, 4001 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_MP 0>; 4002 interconnect-names = "usb-ddr", "apps-usb"; 4003 4004 wakeup-source; 4005 4006 status = "disabled"; 4007 4008 usb_2_dwc3: usb@a400000 { 4009 compatible = "snps,dwc3"; 4010 reg = <0 0x0a400000 0 0xcd00>; 4011 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4012 iommus = <&apps_smmu 0x800 0x0>; 4013 phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>, 4014 <&usb_2_hsphy1>, <&usb_2_qmpphy1>, 4015 <&usb_2_hsphy2>, 4016 <&usb_2_hsphy3>; 4017 phy-names = "usb2-0", "usb3-0", 4018 "usb2-1", "usb3-1", 4019 "usb2-2", 4020 "usb2-3"; 4021 dr_mode = "host"; 4022 snps,dis-u1-entry-quirk; 4023 snps,dis-u2-entry-quirk; 4024 }; 4025 }; 4026 4027 usb_0: usb@a6f8800 { 4028 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 4029 reg = <0 0x0a6f8800 0 0x400>; 4030 #address-cells = <2>; 4031 #size-cells = <2>; 4032 ranges; 4033 4034 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4035 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4036 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4037 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4038 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4039 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4040 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 4041 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 4042 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4043 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 4044 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 4045 4046 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4047 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4048 assigned-clock-rates = <19200000>, <200000000>; 4049 4050 interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 4051 <&intc GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, 4052 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4053 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4054 <&pdc 138 IRQ_TYPE_LEVEL_HIGH>; 4055 interrupt-names = "pwr_event", 4056 "hs_phy_irq", 4057 "dp_hs_phy_irq", 4058 "dm_hs_phy_irq", 4059 "ss_phy_irq"; 4060 4061 power-domains = <&gcc USB30_PRIM_GDSC>; 4062 required-opps = <&rpmhpd_opp_nom>; 4063 4064 resets = <&gcc GCC_USB30_PRIM_BCR>; 4065 4066 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 4067 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 4068 interconnect-names = "usb-ddr", "apps-usb"; 4069 4070 wakeup-source; 4071 4072 status = "disabled"; 4073 4074 usb_0_dwc3: usb@a600000 { 4075 compatible = "snps,dwc3"; 4076 reg = <0 0x0a600000 0 0xcd00>; 4077 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 4078 iommus = <&apps_smmu 0x820 0x0>; 4079 phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; 4080 phy-names = "usb2-phy", "usb3-phy"; 4081 snps,dis-u1-entry-quirk; 4082 snps,dis-u2-entry-quirk; 4083 4084 ports { 4085 #address-cells = <1>; 4086 #size-cells = <0>; 4087 4088 port@0 { 4089 reg = <0>; 4090 4091 usb_0_dwc3_hs: endpoint { 4092 }; 4093 }; 4094 4095 port@1 { 4096 reg = <1>; 4097 4098 usb_0_dwc3_ss: endpoint { 4099 remote-endpoint = <&usb_0_qmpphy_usb_ss_in>; 4100 }; 4101 }; 4102 }; 4103 }; 4104 }; 4105 4106 usb_1: usb@a8f8800 { 4107 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 4108 reg = <0 0x0a8f8800 0 0x400>; 4109 #address-cells = <2>; 4110 #size-cells = <2>; 4111 ranges; 4112 4113 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4114 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4115 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4116 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4117 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4118 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4119 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 4120 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 4121 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4122 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 4123 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 4124 4125 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4126 <&gcc GCC_USB30_SEC_MASTER_CLK>; 4127 assigned-clock-rates = <19200000>, <200000000>; 4128 4129 interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 4130 <&intc GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 4131 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 4132 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 4133 <&pdc 136 IRQ_TYPE_LEVEL_HIGH>; 4134 interrupt-names = "pwr_event", 4135 "hs_phy_irq", 4136 "dp_hs_phy_irq", 4137 "dm_hs_phy_irq", 4138 "ss_phy_irq"; 4139 4140 power-domains = <&gcc USB30_SEC_GDSC>; 4141 required-opps = <&rpmhpd_opp_nom>; 4142 4143 resets = <&gcc GCC_USB30_SEC_BCR>; 4144 4145 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 4146 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 4147 interconnect-names = "usb-ddr", "apps-usb"; 4148 4149 wakeup-source; 4150 4151 status = "disabled"; 4152 4153 usb_1_dwc3: usb@a800000 { 4154 compatible = "snps,dwc3"; 4155 reg = <0 0x0a800000 0 0xcd00>; 4156 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 4157 iommus = <&apps_smmu 0x860 0x0>; 4158 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4159 phy-names = "usb2-phy", "usb3-phy"; 4160 snps,dis-u1-entry-quirk; 4161 snps,dis-u2-entry-quirk; 4162 4163 ports { 4164 #address-cells = <1>; 4165 #size-cells = <0>; 4166 4167 port@0 { 4168 reg = <0>; 4169 4170 usb_1_dwc3_hs: endpoint { 4171 }; 4172 }; 4173 4174 port@1 { 4175 reg = <1>; 4176 4177 usb_1_dwc3_ss: endpoint { 4178 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 4179 }; 4180 }; 4181 }; 4182 }; 4183 }; 4184 4185 cci0: cci@ac4a000 { 4186 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 4187 reg = <0 0x0ac4a000 0 0x1000>; 4188 4189 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4190 4191 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 4192 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 4193 <&camcc CAMCC_CPAS_AHB_CLK>, 4194 <&camcc CAMCC_CCI_0_CLK>; 4195 clock-names = "camnoc_axi", 4196 "slow_ahb_src", 4197 "cpas_ahb", 4198 "cci"; 4199 4200 power-domains = <&camcc TITAN_TOP_GDSC>; 4201 4202 pinctrl-0 = <&cci0_default>; 4203 pinctrl-1 = <&cci0_sleep>; 4204 pinctrl-names = "default", "sleep"; 4205 4206 #address-cells = <1>; 4207 #size-cells = <0>; 4208 4209 status = "disabled"; 4210 4211 cci0_i2c0: i2c-bus@0 { 4212 reg = <0>; 4213 clock-frequency = <1000000>; 4214 #address-cells = <1>; 4215 #size-cells = <0>; 4216 }; 4217 4218 cci0_i2c1: i2c-bus@1 { 4219 reg = <1>; 4220 clock-frequency = <1000000>; 4221 #address-cells = <1>; 4222 #size-cells = <0>; 4223 }; 4224 }; 4225 4226 cci1: cci@ac4b000 { 4227 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 4228 reg = <0 0x0ac4b000 0 0x1000>; 4229 4230 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 4231 4232 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 4233 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 4234 <&camcc CAMCC_CPAS_AHB_CLK>, 4235 <&camcc CAMCC_CCI_1_CLK>; 4236 clock-names = "camnoc_axi", 4237 "slow_ahb_src", 4238 "cpas_ahb", 4239 "cci"; 4240 4241 power-domains = <&camcc TITAN_TOP_GDSC>; 4242 4243 pinctrl-0 = <&cci1_default>; 4244 pinctrl-1 = <&cci1_sleep>; 4245 pinctrl-names = "default", "sleep"; 4246 4247 #address-cells = <1>; 4248 #size-cells = <0>; 4249 4250 status = "disabled"; 4251 4252 cci1_i2c0: i2c-bus@0 { 4253 reg = <0>; 4254 clock-frequency = <1000000>; 4255 #address-cells = <1>; 4256 #size-cells = <0>; 4257 }; 4258 4259 cci1_i2c1: i2c-bus@1 { 4260 reg = <1>; 4261 clock-frequency = <1000000>; 4262 #address-cells = <1>; 4263 #size-cells = <0>; 4264 }; 4265 }; 4266 4267 cci2: cci@ac4c000 { 4268 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 4269 reg = <0 0x0ac4c000 0 0x1000>; 4270 4271 interrupts = <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>; 4272 4273 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 4274 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 4275 <&camcc CAMCC_CPAS_AHB_CLK>, 4276 <&camcc CAMCC_CCI_2_CLK>; 4277 clock-names = "camnoc_axi", 4278 "slow_ahb_src", 4279 "cpas_ahb", 4280 "cci"; 4281 power-domains = <&camcc TITAN_TOP_GDSC>; 4282 4283 pinctrl-0 = <&cci2_default>; 4284 pinctrl-1 = <&cci2_sleep>; 4285 pinctrl-names = "default", "sleep"; 4286 4287 #address-cells = <1>; 4288 #size-cells = <0>; 4289 4290 status = "disabled"; 4291 4292 cci2_i2c0: i2c-bus@0 { 4293 reg = <0>; 4294 clock-frequency = <1000000>; 4295 #address-cells = <1>; 4296 #size-cells = <0>; 4297 }; 4298 4299 cci2_i2c1: i2c-bus@1 { 4300 reg = <1>; 4301 clock-frequency = <1000000>; 4302 #address-cells = <1>; 4303 #size-cells = <0>; 4304 }; 4305 }; 4306 4307 cci3: cci@ac4d000 { 4308 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 4309 reg = <0 0x0ac4d000 0 0x1000>; 4310 4311 interrupts = <GIC_SPI 650 IRQ_TYPE_EDGE_RISING>; 4312 4313 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 4314 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 4315 <&camcc CAMCC_CPAS_AHB_CLK>, 4316 <&camcc CAMCC_CCI_3_CLK>; 4317 clock-names = "camnoc_axi", 4318 "slow_ahb_src", 4319 "cpas_ahb", 4320 "cci"; 4321 4322 power-domains = <&camcc TITAN_TOP_GDSC>; 4323 4324 pinctrl-0 = <&cci3_default>; 4325 pinctrl-1 = <&cci3_sleep>; 4326 pinctrl-names = "default", "sleep"; 4327 4328 #address-cells = <1>; 4329 #size-cells = <0>; 4330 4331 status = "disabled"; 4332 4333 cci3_i2c0: i2c-bus@0 { 4334 reg = <0>; 4335 clock-frequency = <1000000>; 4336 #address-cells = <1>; 4337 #size-cells = <0>; 4338 }; 4339 4340 cci3_i2c1: i2c-bus@1 { 4341 reg = <1>; 4342 clock-frequency = <1000000>; 4343 #address-cells = <1>; 4344 #size-cells = <0>; 4345 }; 4346 }; 4347 4348 camss: camss@ac5a000 { 4349 compatible = "qcom,sc8280xp-camss"; 4350 4351 reg = <0 0x0ac5a000 0 0x2000>, 4352 <0 0x0ac5c000 0 0x2000>, 4353 <0 0x0ac65000 0 0x2000>, 4354 <0 0x0ac67000 0 0x2000>, 4355 <0 0x0acaf000 0 0x4000>, 4356 <0 0x0acb3000 0 0x1000>, 4357 <0 0x0acb6000 0 0x4000>, 4358 <0 0x0acba000 0 0x1000>, 4359 <0 0x0acbd000 0 0x4000>, 4360 <0 0x0acc1000 0 0x1000>, 4361 <0 0x0acc4000 0 0x4000>, 4362 <0 0x0acc8000 0 0x1000>, 4363 <0 0x0accb000 0 0x4000>, 4364 <0 0x0accf000 0 0x1000>, 4365 <0 0x0acd2000 0 0x4000>, 4366 <0 0x0acd6000 0 0x1000>, 4367 <0 0x0acd9000 0 0x4000>, 4368 <0 0x0acdd000 0 0x1000>, 4369 <0 0x0ace0000 0 0x4000>, 4370 <0 0x0ace4000 0 0x1000>; 4371 reg-names = "csiphy2", 4372 "csiphy3", 4373 "csiphy0", 4374 "csiphy1", 4375 "vfe0", 4376 "csid0", 4377 "vfe1", 4378 "csid1", 4379 "vfe2", 4380 "csid2", 4381 "vfe_lite0", 4382 "csid0_lite", 4383 "vfe_lite1", 4384 "csid1_lite", 4385 "vfe_lite2", 4386 "csid2_lite", 4387 "vfe_lite3", 4388 "csid3_lite", 4389 "vfe3", 4390 "csid3"; 4391 4392 interrupts = <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, 4393 <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>, 4394 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 4395 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 4396 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 4397 <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, 4398 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 4399 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 4400 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, 4401 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 4402 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 4403 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 4404 <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>, 4405 <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>, 4406 <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>, 4407 <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>, 4408 <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>, 4409 <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>, 4410 <GIC_SPI 762 IRQ_TYPE_EDGE_RISING>, 4411 <GIC_SPI 764 IRQ_TYPE_EDGE_RISING>; 4412 interrupt-names = "csid1_lite", 4413 "vfe_lite1", 4414 "csiphy3", 4415 "csid0", 4416 "vfe0", 4417 "csid1", 4418 "vfe1", 4419 "csid0_lite", 4420 "vfe_lite0", 4421 "csiphy0", 4422 "csiphy1", 4423 "csiphy2", 4424 "csid2", 4425 "vfe2", 4426 "csid3_lite", 4427 "csid2_lite", 4428 "vfe_lite3", 4429 "vfe_lite2", 4430 "csid3", 4431 "vfe3"; 4432 4433 power-domains = <&camcc IFE_0_GDSC>, 4434 <&camcc IFE_1_GDSC>, 4435 <&camcc IFE_2_GDSC>, 4436 <&camcc IFE_3_GDSC>, 4437 <&camcc TITAN_TOP_GDSC>; 4438 power-domain-names = "ife0", 4439 "ife1", 4440 "ife2", 4441 "ife3", 4442 "top"; 4443 4444 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 4445 <&camcc CAMCC_CPAS_AHB_CLK>, 4446 <&camcc CAMCC_CSIPHY0_CLK>, 4447 <&camcc CAMCC_CSI0PHYTIMER_CLK>, 4448 <&camcc CAMCC_CSIPHY1_CLK>, 4449 <&camcc CAMCC_CSI1PHYTIMER_CLK>, 4450 <&camcc CAMCC_CSIPHY2_CLK>, 4451 <&camcc CAMCC_CSI2PHYTIMER_CLK>, 4452 <&camcc CAMCC_CSIPHY3_CLK>, 4453 <&camcc CAMCC_CSI3PHYTIMER_CLK>, 4454 <&camcc CAMCC_IFE_0_AXI_CLK>, 4455 <&camcc CAMCC_IFE_0_CLK>, 4456 <&camcc CAMCC_IFE_0_CPHY_RX_CLK>, 4457 <&camcc CAMCC_IFE_0_CSID_CLK>, 4458 <&camcc CAMCC_IFE_1_AXI_CLK>, 4459 <&camcc CAMCC_IFE_1_CLK>, 4460 <&camcc CAMCC_IFE_1_CPHY_RX_CLK>, 4461 <&camcc CAMCC_IFE_1_CSID_CLK>, 4462 <&camcc CAMCC_IFE_2_AXI_CLK>, 4463 <&camcc CAMCC_IFE_2_CLK>, 4464 <&camcc CAMCC_IFE_2_CPHY_RX_CLK>, 4465 <&camcc CAMCC_IFE_2_CSID_CLK>, 4466 <&camcc CAMCC_IFE_3_AXI_CLK>, 4467 <&camcc CAMCC_IFE_3_CLK>, 4468 <&camcc CAMCC_IFE_3_CPHY_RX_CLK>, 4469 <&camcc CAMCC_IFE_3_CSID_CLK>, 4470 <&camcc CAMCC_IFE_LITE_0_CLK>, 4471 <&camcc CAMCC_IFE_LITE_0_CPHY_RX_CLK>, 4472 <&camcc CAMCC_IFE_LITE_0_CSID_CLK>, 4473 <&camcc CAMCC_IFE_LITE_1_CLK>, 4474 <&camcc CAMCC_IFE_LITE_1_CPHY_RX_CLK>, 4475 <&camcc CAMCC_IFE_LITE_1_CSID_CLK>, 4476 <&camcc CAMCC_IFE_LITE_2_CLK>, 4477 <&camcc CAMCC_IFE_LITE_2_CPHY_RX_CLK>, 4478 <&camcc CAMCC_IFE_LITE_2_CSID_CLK>, 4479 <&camcc CAMCC_IFE_LITE_3_CLK>, 4480 <&camcc CAMCC_IFE_LITE_3_CPHY_RX_CLK>, 4481 <&camcc CAMCC_IFE_LITE_3_CSID_CLK>, 4482 <&gcc GCC_CAMERA_HF_AXI_CLK>, 4483 <&gcc GCC_CAMERA_SF_AXI_CLK>; 4484 clock-names = "camnoc_axi", 4485 "cpas_ahb", 4486 "csiphy0", 4487 "csiphy0_timer", 4488 "csiphy1", 4489 "csiphy1_timer", 4490 "csiphy2", 4491 "csiphy2_timer", 4492 "csiphy3", 4493 "csiphy3_timer", 4494 "vfe0_axi", 4495 "vfe0", 4496 "vfe0_cphy_rx", 4497 "vfe0_csid", 4498 "vfe1_axi", 4499 "vfe1", 4500 "vfe1_cphy_rx", 4501 "vfe1_csid", 4502 "vfe2_axi", 4503 "vfe2", 4504 "vfe2_cphy_rx", 4505 "vfe2_csid", 4506 "vfe3_axi", 4507 "vfe3", 4508 "vfe3_cphy_rx", 4509 "vfe3_csid", 4510 "vfe_lite0", 4511 "vfe_lite0_cphy_rx", 4512 "vfe_lite0_csid", 4513 "vfe_lite1", 4514 "vfe_lite1_cphy_rx", 4515 "vfe_lite1_csid", 4516 "vfe_lite2", 4517 "vfe_lite2_cphy_rx", 4518 "vfe_lite2_csid", 4519 "vfe_lite3", 4520 "vfe_lite3_cphy_rx", 4521 "vfe_lite3_csid", 4522 "gcc_axi_hf", 4523 "gcc_axi_sf"; 4524 4525 iommus = <&apps_smmu 0x2000 0x4e0>, 4526 <&apps_smmu 0x2020 0x4e0>, 4527 <&apps_smmu 0x2040 0x4e0>, 4528 <&apps_smmu 0x2060 0x4e0>, 4529 <&apps_smmu 0x2080 0x4e0>, 4530 <&apps_smmu 0x20e0 0x4e0>, 4531 <&apps_smmu 0x20c0 0x4e0>, 4532 <&apps_smmu 0x20a0 0x4e0>, 4533 <&apps_smmu 0x2400 0x4e0>, 4534 <&apps_smmu 0x2420 0x4e0>, 4535 <&apps_smmu 0x2440 0x4e0>, 4536 <&apps_smmu 0x2460 0x4e0>, 4537 <&apps_smmu 0x2480 0x4e0>, 4538 <&apps_smmu 0x24e0 0x4e0>, 4539 <&apps_smmu 0x24c0 0x4e0>, 4540 <&apps_smmu 0x24a0 0x4e0>; 4541 4542 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>, 4543 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>, 4544 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>, 4545 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>; 4546 interconnect-names = "cam_ahb", 4547 "cam_hf_mnoc", 4548 "cam_sf_mnoc", 4549 "cam_sf_icp_mnoc"; 4550 4551 status = "disabled"; 4552 4553 ports { 4554 #address-cells = <1>; 4555 #size-cells = <0>; 4556 4557 port@0 { 4558 reg = <0>; 4559 #address-cells = <1>; 4560 #size-cells = <0>; 4561 }; 4562 4563 port@1 { 4564 reg = <1>; 4565 #address-cells = <1>; 4566 #size-cells = <0>; 4567 }; 4568 4569 port@2 { 4570 reg = <2>; 4571 #address-cells = <1>; 4572 #size-cells = <0>; 4573 }; 4574 4575 port@3 { 4576 reg = <3>; 4577 #address-cells = <1>; 4578 #size-cells = <0>; 4579 }; 4580 }; 4581 }; 4582 4583 camcc: clock-controller@ad00000 { 4584 compatible = "qcom,sc8280xp-camcc"; 4585 reg = <0 0x0ad00000 0 0x20000>; 4586 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4587 <&rpmhcc RPMH_CXO_CLK>, 4588 <&rpmhcc RPMH_CXO_CLK_A>, 4589 <&sleep_clk>; 4590 power-domains = <&rpmhpd SC8280XP_MMCX>; 4591 required-opps = <&rpmhpd_opp_low_svs>; 4592 #clock-cells = <1>; 4593 #reset-cells = <1>; 4594 #power-domain-cells = <1>; 4595 }; 4596 4597 mdss0: display-subsystem@ae00000 { 4598 compatible = "qcom,sc8280xp-mdss"; 4599 reg = <0 0x0ae00000 0 0x1000>; 4600 reg-names = "mdss"; 4601 4602 clocks = <&gcc GCC_DISP_AHB_CLK>, 4603 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4604 <&dispcc0 DISP_CC_MDSS_MDP_CLK>; 4605 clock-names = "iface", 4606 "ahb", 4607 "core"; 4608 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4609 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 4610 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 4611 interconnect-names = "mdp0-mem", "mdp1-mem"; 4612 iommus = <&apps_smmu 0x1000 0x402>; 4613 power-domains = <&dispcc0 MDSS_GDSC>; 4614 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>; 4615 4616 interrupt-controller; 4617 #interrupt-cells = <1>; 4618 #address-cells = <2>; 4619 #size-cells = <2>; 4620 ranges; 4621 4622 status = "disabled"; 4623 4624 mdss0_mdp: display-controller@ae01000 { 4625 compatible = "qcom,sc8280xp-dpu"; 4626 reg = <0 0x0ae01000 0 0x8f000>, 4627 <0 0x0aeb0000 0 0x3000>; 4628 reg-names = "mdp", "vbif"; 4629 4630 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4631 <&gcc GCC_DISP_SF_AXI_CLK>, 4632 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4633 <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>, 4634 <&dispcc0 DISP_CC_MDSS_MDP_CLK>, 4635 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 4636 clock-names = "bus", 4637 "nrt_bus", 4638 "iface", 4639 "lut", 4640 "core", 4641 "vsync"; 4642 interrupt-parent = <&mdss0>; 4643 interrupts = <0>; 4644 power-domains = <&rpmhpd SC8280XP_MMCX>; 4645 4646 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 4647 assigned-clock-rates = <19200000>; 4648 operating-points-v2 = <&mdss0_mdp_opp_table>; 4649 4650 ports { 4651 #address-cells = <1>; 4652 #size-cells = <0>; 4653 4654 port@0 { 4655 reg = <0>; 4656 4657 mdss0_intf0_out: endpoint { 4658 remote-endpoint = <&mdss0_dp0_in>; 4659 }; 4660 }; 4661 4662 port@1 { 4663 reg = <1>; 4664 4665 mdss0_intf1_out: endpoint { 4666 remote-endpoint = <&mdss0_dsi0_in>; 4667 }; 4668 }; 4669 4670 port@2 { 4671 reg = <2>; 4672 4673 mdss0_intf2_out: endpoint { 4674 remote-endpoint = <&mdss0_dsi1_in>; 4675 }; 4676 }; 4677 4678 port@4 { 4679 reg = <4>; 4680 4681 mdss0_intf4_out: endpoint { 4682 remote-endpoint = <&mdss0_dp1_in>; 4683 }; 4684 }; 4685 4686 port@5 { 4687 reg = <5>; 4688 4689 mdss0_intf5_out: endpoint { 4690 remote-endpoint = <&mdss0_dp3_in>; 4691 }; 4692 }; 4693 4694 port@6 { 4695 reg = <6>; 4696 4697 mdss0_intf6_out: endpoint { 4698 remote-endpoint = <&mdss0_dp2_in>; 4699 }; 4700 }; 4701 }; 4702 4703 mdss0_mdp_opp_table: opp-table { 4704 compatible = "operating-points-v2"; 4705 4706 opp-200000000 { 4707 opp-hz = /bits/ 64 <200000000>; 4708 required-opps = <&rpmhpd_opp_low_svs>; 4709 }; 4710 4711 opp-300000000 { 4712 opp-hz = /bits/ 64 <300000000>; 4713 required-opps = <&rpmhpd_opp_svs>; 4714 }; 4715 4716 opp-375000000 { 4717 opp-hz = /bits/ 64 <375000000>; 4718 required-opps = <&rpmhpd_opp_svs_l1>; 4719 }; 4720 4721 opp-500000000 { 4722 opp-hz = /bits/ 64 <500000000>; 4723 required-opps = <&rpmhpd_opp_nom>; 4724 }; 4725 opp-600000000 { 4726 opp-hz = /bits/ 64 <600000000>; 4727 required-opps = <&rpmhpd_opp_turbo_l1>; 4728 }; 4729 }; 4730 }; 4731 4732 mdss0_dp0: displayport-controller@ae90000 { 4733 compatible = "qcom,sc8280xp-dp"; 4734 reg = <0 0xae90000 0 0x200>, 4735 <0 0xae90200 0 0x200>, 4736 <0 0xae90400 0 0x600>, 4737 <0 0xae91000 0 0x400>, 4738 <0 0xae91400 0 0x400>; 4739 interrupt-parent = <&mdss0>; 4740 interrupts = <12>; 4741 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4742 <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>, 4743 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>, 4744 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 4745 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 4746 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; 4747 clock-names = "core_iface", "core_aux", 4748 "ctrl_link", 4749 "ctrl_link_iface", 4750 "stream_pixel", 4751 "stream_1_pixel"; 4752 4753 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 4754 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 4755 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; 4756 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4757 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4758 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4759 4760 phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; 4761 phy-names = "dp"; 4762 4763 #sound-dai-cells = <0>; 4764 4765 operating-points-v2 = <&mdss0_dp0_opp_table>; 4766 power-domains = <&rpmhpd SC8280XP_MMCX>; 4767 4768 status = "disabled"; 4769 4770 ports { 4771 #address-cells = <1>; 4772 #size-cells = <0>; 4773 4774 port@0 { 4775 reg = <0>; 4776 4777 mdss0_dp0_in: endpoint { 4778 remote-endpoint = <&mdss0_intf0_out>; 4779 }; 4780 }; 4781 4782 port@1 { 4783 reg = <1>; 4784 4785 mdss0_dp0_out: endpoint { 4786 }; 4787 }; 4788 }; 4789 4790 mdss0_dp0_opp_table: opp-table { 4791 compatible = "operating-points-v2"; 4792 4793 opp-162000000 { 4794 opp-hz = /bits/ 64 <162000000>; 4795 required-opps = <&rpmhpd_opp_low_svs>; 4796 }; 4797 4798 opp-270000000 { 4799 opp-hz = /bits/ 64 <270000000>; 4800 required-opps = <&rpmhpd_opp_svs>; 4801 }; 4802 4803 opp-540000000 { 4804 opp-hz = /bits/ 64 <540000000>; 4805 required-opps = <&rpmhpd_opp_svs_l1>; 4806 }; 4807 4808 opp-810000000 { 4809 opp-hz = /bits/ 64 <810000000>; 4810 required-opps = <&rpmhpd_opp_nom>; 4811 }; 4812 }; 4813 }; 4814 4815 mdss0_dsi0: dsi@ae94000 { 4816 compatible = "qcom,sc8280xp-dsi-ctrl", 4817 "qcom,sa8775p-dsi-ctrl", 4818 "qcom,mdss-dsi-ctrl"; 4819 reg = <0 0x0ae94000 0 0x400>; 4820 reg-names = "dsi_ctrl"; 4821 4822 interrupt-parent = <&mdss0>; 4823 interrupts = <4>; 4824 4825 clocks = <&dispcc0 DISP_CC_MDSS_BYTE0_CLK>, 4826 <&dispcc0 DISP_CC_MDSS_BYTE0_INTF_CLK>, 4827 <&dispcc0 DISP_CC_MDSS_PCLK0_CLK>, 4828 <&dispcc0 DISP_CC_MDSS_ESC0_CLK>, 4829 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4830 <&gcc GCC_DISP_HF_AXI_CLK>; 4831 clock-names = "byte", 4832 "byte_intf", 4833 "pixel", 4834 "core", 4835 "iface", 4836 "bus"; 4837 4838 assigned-clocks = <&dispcc0 DISP_CC_MDSS_BYTE0_CLK_SRC>, 4839 <&dispcc0 DISP_CC_MDSS_PCLK0_CLK_SRC>; 4840 assigned-clock-parents = <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>, 4841 <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>; 4842 4843 operating-points-v2 = <&dsi_opp_table>; 4844 power-domains = <&rpmhpd SC8280XP_MMCX>; 4845 4846 refgen-supply = <&refgen>; 4847 4848 phys = <&mdss0_dsi0_phy>; 4849 phy-names = "dsi"; 4850 4851 #address-cells = <1>; 4852 #size-cells = <0>; 4853 4854 status = "disabled"; 4855 4856 ports { 4857 #address-cells = <1>; 4858 #size-cells = <0>; 4859 4860 port@0 { 4861 reg = <0>; 4862 4863 mdss0_dsi0_in: endpoint { 4864 remote-endpoint = <&mdss0_intf1_out>; 4865 }; 4866 }; 4867 4868 port@1 { 4869 reg = <1>; 4870 4871 mdss0_dsi0_out: endpoint { 4872 }; 4873 }; 4874 }; 4875 4876 dsi_opp_table: opp-table { 4877 compatible = "operating-points-v2"; 4878 4879 opp-187500000 { 4880 opp-hz = /bits/ 64 <187500000>; 4881 required-opps = <&rpmhpd_opp_low_svs>; 4882 }; 4883 4884 opp-300000000 { 4885 opp-hz = /bits/ 64 <300000000>; 4886 required-opps = <&rpmhpd_opp_svs>; 4887 }; 4888 4889 opp-358000000 { 4890 opp-hz = /bits/ 64 <358000000>; 4891 required-opps = <&rpmhpd_opp_svs_l1>; 4892 }; 4893 }; 4894 }; 4895 4896 mdss0_dsi0_phy: phy@ae94400 { 4897 compatible = "qcom,sc8280xp-dsi-phy-5nm", 4898 "qcom,sa8775p-dsi-phy-5nm"; 4899 reg = <0 0x0ae94400 0 0x200>, 4900 <0 0x0ae94600 0 0x280>, 4901 <0 0x0ae94900 0 0x280>; 4902 reg-names = "dsi_phy", 4903 "dsi_phy_lane", 4904 "dsi_pll"; 4905 4906 #clock-cells = <1>; 4907 #phy-cells = <0>; 4908 4909 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4910 <&rpmhcc RPMH_CXO_CLK>; 4911 clock-names = "iface", "ref"; 4912 4913 status = "disabled"; 4914 }; 4915 4916 mdss0_dsi1: dsi@ae96000 { 4917 compatible = "qcom,sc8280xp-dsi-ctrl", 4918 "qcom,sa8775p-dsi-ctrl", 4919 "qcom,mdss-dsi-ctrl"; 4920 reg = <0 0x0ae96000 0 0x400>; 4921 reg-names = "dsi_ctrl"; 4922 4923 interrupt-parent = <&mdss0>; 4924 interrupts = <5>; 4925 4926 clocks = <&dispcc0 DISP_CC_MDSS_BYTE1_CLK>, 4927 <&dispcc0 DISP_CC_MDSS_BYTE1_INTF_CLK>, 4928 <&dispcc0 DISP_CC_MDSS_PCLK1_CLK>, 4929 <&dispcc0 DISP_CC_MDSS_ESC1_CLK>, 4930 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4931 <&gcc GCC_DISP_HF_AXI_CLK>; 4932 clock-names = "byte", 4933 "byte_intf", 4934 "pixel", 4935 "core", 4936 "iface", 4937 "bus"; 4938 4939 assigned-clocks = <&dispcc0 DISP_CC_MDSS_BYTE1_CLK_SRC>, 4940 <&dispcc0 DISP_CC_MDSS_PCLK1_CLK_SRC>; 4941 assigned-clock-parents = <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>, 4942 <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>; 4943 4944 operating-points-v2 = <&dsi_opp_table>; 4945 power-domains = <&rpmhpd SC8280XP_MMCX>; 4946 4947 refgen-supply = <&refgen>; 4948 4949 phys = <&mdss0_dsi1_phy>; 4950 phy-names = "dsi"; 4951 4952 #address-cells = <1>; 4953 #size-cells = <0>; 4954 4955 status = "disabled"; 4956 4957 ports { 4958 #address-cells = <1>; 4959 #size-cells = <0>; 4960 4961 port@0 { 4962 reg = <0>; 4963 4964 mdss0_dsi1_in: endpoint { 4965 remote-endpoint = <&mdss0_intf2_out>; 4966 }; 4967 }; 4968 4969 port@1 { 4970 reg = <1>; 4971 4972 mdss0_dsi1_out: endpoint { 4973 }; 4974 }; 4975 }; 4976 }; 4977 4978 mdss0_dsi1_phy: phy@ae96400 { 4979 compatible = "qcom,sc8280xp-dsi-phy-5nm", 4980 "qcom,sa8775p-dsi-phy-5nm"; 4981 reg = <0 0x0ae96400 0 0x200>, 4982 <0 0x0ae96600 0 0x280>, 4983 <0 0x0ae96900 0 0x280>; 4984 reg-names = "dsi_phy", 4985 "dsi_phy_lane", 4986 "dsi_pll"; 4987 4988 #clock-cells = <1>; 4989 #phy-cells = <0>; 4990 4991 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4992 <&rpmhcc RPMH_CXO_CLK>; 4993 clock-names = "iface", "ref"; 4994 4995 status = "disabled"; 4996 }; 4997 4998 mdss0_dp1: displayport-controller@ae98000 { 4999 compatible = "qcom,sc8280xp-dp"; 5000 reg = <0 0xae98000 0 0x200>, 5001 <0 0xae98200 0 0x200>, 5002 <0 0xae98400 0 0x600>, 5003 <0 0xae99000 0 0x400>, 5004 <0 0xae99400 0 0x400>; 5005 interrupt-parent = <&mdss0>; 5006 interrupts = <13>; 5007 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 5008 <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>, 5009 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>, 5010 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 5011 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, 5012 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; 5013 clock-names = "core_iface", "core_aux", 5014 "ctrl_link", 5015 "ctrl_link_iface", "stream_pixel", 5016 "stream_1_pixel"; 5017 5018 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 5019 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, 5020 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; 5021 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5022 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5023 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5024 5025 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 5026 phy-names = "dp"; 5027 5028 #sound-dai-cells = <0>; 5029 5030 operating-points-v2 = <&mdss0_dp1_opp_table>; 5031 power-domains = <&rpmhpd SC8280XP_MMCX>; 5032 5033 status = "disabled"; 5034 5035 ports { 5036 #address-cells = <1>; 5037 #size-cells = <0>; 5038 5039 port@0 { 5040 reg = <0>; 5041 5042 mdss0_dp1_in: endpoint { 5043 remote-endpoint = <&mdss0_intf4_out>; 5044 }; 5045 }; 5046 5047 port@1 { 5048 reg = <1>; 5049 5050 mdss0_dp1_out: endpoint { 5051 }; 5052 }; 5053 }; 5054 5055 mdss0_dp1_opp_table: opp-table { 5056 compatible = "operating-points-v2"; 5057 5058 opp-162000000 { 5059 opp-hz = /bits/ 64 <162000000>; 5060 required-opps = <&rpmhpd_opp_low_svs>; 5061 }; 5062 5063 opp-270000000 { 5064 opp-hz = /bits/ 64 <270000000>; 5065 required-opps = <&rpmhpd_opp_svs>; 5066 }; 5067 5068 opp-540000000 { 5069 opp-hz = /bits/ 64 <540000000>; 5070 required-opps = <&rpmhpd_opp_svs_l1>; 5071 }; 5072 5073 opp-810000000 { 5074 opp-hz = /bits/ 64 <810000000>; 5075 required-opps = <&rpmhpd_opp_nom>; 5076 }; 5077 }; 5078 }; 5079 5080 mdss0_dp2: displayport-controller@ae9a000 { 5081 compatible = "qcom,sc8280xp-dp"; 5082 reg = <0 0xae9a000 0 0x200>, 5083 <0 0xae9a200 0 0x200>, 5084 <0 0xae9a400 0 0x600>, 5085 <0 0xae9b000 0 0x400>, 5086 <0 0xae9b400 0 0x400>; 5087 5088 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 5089 <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 5090 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>, 5091 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 5092 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, 5093 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; 5094 clock-names = "core_iface", "core_aux", 5095 "ctrl_link", 5096 "ctrl_link_iface", "stream_pixel", 5097 "stream_1_pixel"; 5098 interrupt-parent = <&mdss0>; 5099 interrupts = <14>; 5100 phys = <&mdss0_dp2_phy>; 5101 phy-names = "dp"; 5102 power-domains = <&rpmhpd SC8280XP_MMCX>; 5103 5104 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 5105 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, 5106 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; 5107 assigned-clock-parents = <&mdss0_dp2_phy 0>, 5108 <&mdss0_dp2_phy 1>, 5109 <&mdss0_dp2_phy 1>; 5110 operating-points-v2 = <&mdss0_dp2_opp_table>; 5111 5112 #sound-dai-cells = <0>; 5113 5114 status = "disabled"; 5115 5116 ports { 5117 #address-cells = <1>; 5118 #size-cells = <0>; 5119 5120 port@0 { 5121 reg = <0>; 5122 mdss0_dp2_in: endpoint { 5123 remote-endpoint = <&mdss0_intf6_out>; 5124 }; 5125 }; 5126 5127 port@1 { 5128 reg = <1>; 5129 5130 mdss0_dp2_out: endpoint { 5131 }; 5132 }; 5133 }; 5134 5135 mdss0_dp2_opp_table: opp-table { 5136 compatible = "operating-points-v2"; 5137 5138 opp-162000000 { 5139 opp-hz = /bits/ 64 <162000000>; 5140 required-opps = <&rpmhpd_opp_low_svs>; 5141 }; 5142 5143 opp-270000000 { 5144 opp-hz = /bits/ 64 <270000000>; 5145 required-opps = <&rpmhpd_opp_svs>; 5146 }; 5147 5148 opp-540000000 { 5149 opp-hz = /bits/ 64 <540000000>; 5150 required-opps = <&rpmhpd_opp_svs_l1>; 5151 }; 5152 5153 opp-810000000 { 5154 opp-hz = /bits/ 64 <810000000>; 5155 required-opps = <&rpmhpd_opp_nom>; 5156 }; 5157 }; 5158 }; 5159 5160 mdss0_dp3: displayport-controller@aea0000 { 5161 compatible = "qcom,sc8280xp-dp"; 5162 reg = <0 0xaea0000 0 0x200>, 5163 <0 0xaea0200 0 0x200>, 5164 <0 0xaea0400 0 0x600>, 5165 <0 0xaea1000 0 0x400>, 5166 <0 0xaea1400 0 0x400>; 5167 5168 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 5169 <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 5170 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>, 5171 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 5172 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 5173 clock-names = "core_iface", "core_aux", 5174 "ctrl_link", 5175 "ctrl_link_iface", "stream_pixel"; 5176 interrupt-parent = <&mdss0>; 5177 interrupts = <15>; 5178 phys = <&mdss0_dp3_phy>; 5179 phy-names = "dp"; 5180 power-domains = <&rpmhpd SC8280XP_MMCX>; 5181 5182 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 5183 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 5184 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>; 5185 operating-points-v2 = <&mdss0_dp3_opp_table>; 5186 5187 #sound-dai-cells = <0>; 5188 5189 status = "disabled"; 5190 5191 ports { 5192 #address-cells = <1>; 5193 #size-cells = <0>; 5194 5195 port@0 { 5196 reg = <0>; 5197 mdss0_dp3_in: endpoint { 5198 remote-endpoint = <&mdss0_intf5_out>; 5199 }; 5200 }; 5201 5202 port@1 { 5203 reg = <1>; 5204 5205 mdss0_dp3_out: endpoint { 5206 }; 5207 }; 5208 }; 5209 5210 mdss0_dp3_opp_table: opp-table { 5211 compatible = "operating-points-v2"; 5212 5213 opp-162000000 { 5214 opp-hz = /bits/ 64 <162000000>; 5215 required-opps = <&rpmhpd_opp_low_svs>; 5216 }; 5217 5218 opp-270000000 { 5219 opp-hz = /bits/ 64 <270000000>; 5220 required-opps = <&rpmhpd_opp_svs>; 5221 }; 5222 5223 opp-540000000 { 5224 opp-hz = /bits/ 64 <540000000>; 5225 required-opps = <&rpmhpd_opp_svs_l1>; 5226 }; 5227 5228 opp-810000000 { 5229 opp-hz = /bits/ 64 <810000000>; 5230 required-opps = <&rpmhpd_opp_nom>; 5231 }; 5232 }; 5233 }; 5234 }; 5235 5236 mdss0_dp2_phy: phy@aec2a00 { 5237 compatible = "qcom,sc8280xp-dp-phy"; 5238 reg = <0 0x0aec2a00 0 0x19c>, 5239 <0 0x0aec2200 0 0xec>, 5240 <0 0x0aec2600 0 0xec>, 5241 <0 0x0aec2000 0 0x1c8>; 5242 5243 clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 5244 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 5245 clock-names = "aux", "cfg_ahb"; 5246 power-domains = <&rpmhpd SC8280XP_MX>; 5247 5248 #clock-cells = <1>; 5249 #phy-cells = <0>; 5250 5251 status = "disabled"; 5252 }; 5253 5254 mdss0_dp3_phy: phy@aec5a00 { 5255 compatible = "qcom,sc8280xp-dp-phy"; 5256 reg = <0 0x0aec5a00 0 0x19c>, 5257 <0 0x0aec5200 0 0xec>, 5258 <0 0x0aec5600 0 0xec>, 5259 <0 0x0aec5000 0 0x1c8>; 5260 5261 clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 5262 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 5263 clock-names = "aux", "cfg_ahb"; 5264 power-domains = <&rpmhpd SC8280XP_MX>; 5265 5266 #clock-cells = <1>; 5267 #phy-cells = <0>; 5268 5269 status = "disabled"; 5270 }; 5271 5272 dispcc0: clock-controller@af00000 { 5273 compatible = "qcom,sc8280xp-dispcc0"; 5274 reg = <0 0x0af00000 0 0x20000>; 5275 5276 clocks = <&gcc GCC_DISP_AHB_CLK>, 5277 <&rpmhcc RPMH_CXO_CLK>, 5278 <&sleep_clk>, 5279 <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5280 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5281 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5282 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5283 <&mdss0_dp2_phy 0>, 5284 <&mdss0_dp2_phy 1>, 5285 <&mdss0_dp3_phy 0>, 5286 <&mdss0_dp3_phy 1>, 5287 <&mdss0_dsi0_phy DSI_BYTE_PLL_CLK>, 5288 <&mdss0_dsi0_phy DSI_PIXEL_PLL_CLK>, 5289 <&mdss0_dsi1_phy DSI_BYTE_PLL_CLK>, 5290 <&mdss0_dsi1_phy DSI_PIXEL_PLL_CLK>; 5291 power-domains = <&rpmhpd SC8280XP_MMCX>; 5292 5293 #clock-cells = <1>; 5294 #power-domain-cells = <1>; 5295 #reset-cells = <1>; 5296 5297 status = "disabled"; 5298 }; 5299 5300 pdc: interrupt-controller@b220000 { 5301 compatible = "qcom,sc8280xp-pdc", "qcom,pdc"; 5302 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 5303 qcom,pdc-ranges = <0 480 40>, 5304 <40 140 14>, 5305 <54 263 1>, 5306 <55 306 4>, 5307 <59 312 3>, 5308 <62 374 2>, 5309 <64 434 2>, 5310 <66 438 3>, 5311 <69 86 1>, 5312 <70 520 54>, 5313 <124 609 28>, 5314 <159 638 1>, 5315 <160 720 8>, 5316 <168 801 1>, 5317 <169 728 30>, 5318 <199 416 2>, 5319 <201 449 1>, 5320 <202 89 1>, 5321 <203 451 1>, 5322 <204 462 1>, 5323 <205 264 1>, 5324 <206 579 1>, 5325 <207 653 1>, 5326 <208 656 1>, 5327 <209 659 1>, 5328 <210 122 1>, 5329 <211 699 1>, 5330 <212 705 1>, 5331 <213 450 1>, 5332 <214 643 1>, 5333 <216 646 5>, 5334 <221 390 5>, 5335 <226 700 3>, 5336 <229 240 3>, 5337 <232 269 1>, 5338 <233 377 1>, 5339 <234 372 1>, 5340 <235 138 1>, 5341 <236 857 1>, 5342 <237 860 1>, 5343 <238 137 1>, 5344 <239 668 1>, 5345 <240 366 1>, 5346 <241 949 1>, 5347 <242 815 5>, 5348 <247 769 1>, 5349 <248 768 1>, 5350 <249 663 1>, 5351 <250 799 2>, 5352 <252 798 1>, 5353 <253 765 1>, 5354 <254 763 1>, 5355 <255 454 1>, 5356 <258 139 1>, 5357 <259 786 2>, 5358 <261 370 2>, 5359 <263 158 2>; 5360 #interrupt-cells = <2>; 5361 interrupt-parent = <&intc>; 5362 interrupt-controller; 5363 }; 5364 5365 tsens2: thermal-sensor@c251000 { 5366 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 5367 reg = <0 0x0c251000 0 0x1ff>, 5368 <0 0x0c224000 0 0x8>; 5369 #qcom,sensors = <11>; 5370 interrupts-extended = <&pdc 122 IRQ_TYPE_LEVEL_HIGH>, 5371 <&pdc 124 IRQ_TYPE_LEVEL_HIGH>; 5372 interrupt-names = "uplow", "critical"; 5373 #thermal-sensor-cells = <1>; 5374 }; 5375 5376 tsens3: thermal-sensor@c252000 { 5377 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 5378 reg = <0 0x0c252000 0 0x1ff>, 5379 <0 0x0c225000 0 0x8>; 5380 #qcom,sensors = <5>; 5381 interrupts-extended = <&pdc 123 IRQ_TYPE_LEVEL_HIGH>, 5382 <&pdc 125 IRQ_TYPE_LEVEL_HIGH>; 5383 interrupt-names = "uplow", "critical"; 5384 #thermal-sensor-cells = <1>; 5385 }; 5386 5387 tsens0: thermal-sensor@c263000 { 5388 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 5389 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 5390 <0 0x0c222000 0 0x8>; /* SROT */ 5391 #qcom,sensors = <14>; 5392 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 5393 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 5394 interrupt-names = "uplow", "critical"; 5395 #thermal-sensor-cells = <1>; 5396 }; 5397 5398 restart@c264000 { 5399 compatible = "qcom,pshold"; 5400 reg = <0 0x0c264000 0 0x4>; 5401 /* TZ seems to block access */ 5402 status = "reserved"; 5403 }; 5404 5405 tsens1: thermal-sensor@c265000 { 5406 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 5407 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 5408 <0 0x0c223000 0 0x8>; /* SROT */ 5409 #qcom,sensors = <16>; 5410 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 5411 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 5412 interrupt-names = "uplow", "critical"; 5413 #thermal-sensor-cells = <1>; 5414 }; 5415 5416 aoss_qmp: power-management@c300000 { 5417 compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp"; 5418 reg = <0 0x0c300000 0 0x400>; 5419 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; 5420 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 5421 5422 #clock-cells = <0>; 5423 }; 5424 5425 sram@c3f0000 { 5426 compatible = "qcom,rpmh-stats"; 5427 reg = <0 0x0c3f0000 0 0x400>; 5428 qcom,qmp = <&aoss_qmp>; 5429 }; 5430 5431 spmi_bus: spmi@c440000 { 5432 compatible = "qcom,spmi-pmic-arb"; 5433 reg = <0 0x0c440000 0 0x1100>, 5434 <0 0x0c600000 0 0x2000000>, 5435 <0 0x0e600000 0 0x100000>, 5436 <0 0x0e700000 0 0xa0000>, 5437 <0 0x0c40a000 0 0x26000>; 5438 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 5439 interrupt-names = "periph_irq"; 5440 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5441 qcom,ee = <0>; 5442 qcom,channel = <0>; 5443 #address-cells = <2>; 5444 #size-cells = <0>; 5445 interrupt-controller; 5446 #interrupt-cells = <4>; 5447 }; 5448 5449 tlmm: pinctrl@f100000 { 5450 compatible = "qcom,sc8280xp-tlmm"; 5451 reg = <0 0x0f100000 0 0x300000>; 5452 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 5453 gpio-controller; 5454 #gpio-cells = <2>; 5455 interrupt-controller; 5456 #interrupt-cells = <2>; 5457 gpio-ranges = <&tlmm 0 0 230>; 5458 wakeup-parent = <&pdc>; 5459 5460 cci0_default: cci0-default-state { 5461 cci0_i2c0_default: cci0-i2c0-default-pins { 5462 /* cci_i2c_sda0, cci_i2c_scl0 */ 5463 pins = "gpio113", "gpio114"; 5464 function = "cci_i2c"; 5465 drive-strength = <2>; 5466 bias-pull-up; 5467 }; 5468 5469 cci0_i2c1_default: cci0-i2c1-default-pins { 5470 /* cci_i2c_sda1, cci_i2c_scl1 */ 5471 pins = "gpio115", "gpio116"; 5472 function = "cci_i2c"; 5473 drive-strength = <2>; 5474 bias-pull-up; 5475 }; 5476 }; 5477 5478 cci0_sleep: cci0-sleep-state { 5479 cci0_i2c0_sleep: cci0-i2c0-sleep-pins { 5480 /* cci_i2c_sda0, cci_i2c_scl0 */ 5481 pins = "gpio113", "gpio114"; 5482 function = "cci_i2c"; 5483 drive-strength = <2>; 5484 bias-pull-down; 5485 }; 5486 5487 cci0_i2c1_sleep: cci0-i2c1-sleep-pins { 5488 /* cci_i2c_sda1, cci_i2c_scl1 */ 5489 pins = "gpio115", "gpio116"; 5490 function = "cci_i2c"; 5491 drive-strength = <2>; 5492 bias-pull-down; 5493 }; 5494 }; 5495 5496 cci1_default: cci1-default-state { 5497 cci1_i2c0_default: cci1-i2c0-default-pins { 5498 /* cci_i2c_sda2, cci_i2c_scl2 */ 5499 pins = "gpio10","gpio11"; 5500 function = "cci_i2c"; 5501 drive-strength = <2>; 5502 bias-pull-up; 5503 }; 5504 5505 cci1_i2c1_default: cci1-i2c1-default-pins { 5506 /* cci_i2c_sda3, cci_i2c_scl3 */ 5507 pins = "gpio123","gpio124"; 5508 function = "cci_i2c"; 5509 drive-strength = <2>; 5510 bias-pull-up; 5511 }; 5512 }; 5513 5514 cci1_sleep: cci1-sleep-state { 5515 cci1_i2c0_sleep: cci1-i2c0-sleep-pins { 5516 /* cci_i2c_sda2, cci_i2c_scl2 */ 5517 pins = "gpio10","gpio11"; 5518 function = "cci_i2c"; 5519 drive-strength = <2>; 5520 bias-pull-down; 5521 }; 5522 5523 cci1_i2c1_sleep: cci1-i2c1-sleep-pins { 5524 /* cci_i2c_sda3, cci_i2c_scl3 */ 5525 pins = "gpio123","gpio124"; 5526 function = "cci_i2c"; 5527 drive-strength = <2>; 5528 bias-pull-down; 5529 }; 5530 }; 5531 5532 cci2_default: cci2-default-state { 5533 cci2_i2c0_default: cci2-i2c0-default-pins { 5534 /* cci_i2c_sda4, cci_i2c_scl4 */ 5535 pins = "gpio117","gpio118"; 5536 function = "cci_i2c"; 5537 drive-strength = <2>; 5538 bias-pull-up; 5539 }; 5540 5541 cci2_i2c1_default: cci2-i2c1-default-pins { 5542 /* cci_i2c_sda5, cci_i2c_scl5 */ 5543 pins = "gpio12","gpio13"; 5544 function = "cci_i2c"; 5545 drive-strength = <2>; 5546 bias-pull-up; 5547 }; 5548 }; 5549 5550 cci2_sleep: cci2-sleep-state { 5551 cci2_i2c0_sleep: cci2-i2c0-sleep-pins { 5552 /* cci_i2c_sda4, cci_i2c_scl4 */ 5553 pins = "gpio117","gpio118"; 5554 function = "cci_i2c"; 5555 drive-strength = <2>; 5556 bias-pull-down; 5557 }; 5558 5559 cci2_i2c1_sleep: cci2-i2c1-sleep-pins { 5560 /* cci_i2c_sda5, cci_i2c_scl5 */ 5561 pins = "gpio12","gpio13"; 5562 function = "cci_i2c"; 5563 drive-strength = <2>; 5564 bias-pull-down; 5565 }; 5566 }; 5567 5568 cci3_default: cci3-default-state { 5569 cci3_i2c0_default: cci3-i2c0-default-pins { 5570 /* cci_i2c_sda6, cci_i2c_scl6 */ 5571 pins = "gpio145","gpio146"; 5572 function = "cci_i2c"; 5573 drive-strength = <2>; 5574 bias-pull-up; 5575 }; 5576 5577 cci3_i2c1_default: cci3-i2c1-default-pins { 5578 /* cci_i2c_sda7, cci_i2c_scl7 */ 5579 pins = "gpio164","gpio165"; 5580 function = "cci_i2c"; 5581 drive-strength = <2>; 5582 bias-pull-up; 5583 }; 5584 }; 5585 5586 cci3_sleep: cci3-sleep-state { 5587 cci3_i2c0_sleep: cci3-i2c0-sleep-pins { 5588 /* cci_i2c_sda6, cci_i2c_scl6 */ 5589 pins = "gpio145","gpio146"; 5590 function = "cci_i2c"; 5591 drive-strength = <2>; 5592 bias-pull-down; 5593 }; 5594 5595 cci3_i2c1_sleep: cci3-i2c1-sleep-pins { 5596 /* cci_i2c_sda7, cci_i2c_scl7 */ 5597 pins = "gpio164","gpio165"; 5598 function = "cci_i2c"; 5599 drive-strength = <2>; 5600 bias-pull-down; 5601 }; 5602 }; 5603 5604 qup_uart18_default: qup-uart18-default-state { 5605 cts-pins { 5606 pins = "gpio66"; 5607 function = "qup18"; 5608 drive-strength = <2>; 5609 bias-disable; 5610 }; 5611 5612 rts-pins { 5613 pins = "gpio67"; 5614 function = "qup18"; 5615 drive-strength = <2>; 5616 bias-disable; 5617 }; 5618 5619 tx-pins { 5620 pins = "gpio68"; 5621 function = "qup18"; 5622 drive-strength = <2>; 5623 bias-disable; 5624 }; 5625 5626 rx-pins { 5627 pins = "gpio69"; 5628 function = "qup18"; 5629 drive-strength = <2>; 5630 bias-disable; 5631 }; 5632 }; 5633 }; 5634 5635 pcie_smmu: iommu@14f80000 { 5636 compatible = "arm,smmu-v3"; 5637 reg = <0 0x14f80000 0 0x80000>; 5638 #iommu-cells = <1>; 5639 interrupts = <GIC_SPI 951 IRQ_TYPE_EDGE_RISING>, 5640 <GIC_SPI 955 IRQ_TYPE_EDGE_RISING>, 5641 <GIC_SPI 953 IRQ_TYPE_EDGE_RISING>; 5642 interrupt-names = "eventq", 5643 "gerror", 5644 "cmdq-sync"; 5645 dma-coherent; 5646 status = "reserved"; /* Controlled by QHEE. */ 5647 }; 5648 5649 apps_smmu: iommu@15000000 { 5650 compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500"; 5651 reg = <0 0x15000000 0 0x100000>; 5652 #iommu-cells = <2>; 5653 #global-interrupts = <2>; 5654 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 5655 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5656 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5657 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5658 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5659 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5660 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5661 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5662 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5663 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5664 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5665 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5666 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5667 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5668 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5669 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5670 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5671 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5672 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5673 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5674 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5675 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5676 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5677 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5678 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5679 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5680 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5681 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5682 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5683 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5684 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5685 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5686 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5687 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5688 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5689 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5690 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5691 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5692 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5693 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5694 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5695 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5696 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5697 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5698 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5699 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5700 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5701 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5702 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5703 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5704 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5705 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5706 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5707 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5708 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5709 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5710 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5711 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5712 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5713 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5714 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5715 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5716 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5717 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5718 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5719 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5720 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5721 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5722 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5723 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5724 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5725 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5726 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5727 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5728 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5729 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5730 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5731 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5732 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5733 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5734 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 5735 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5736 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5737 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5738 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 5739 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5740 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5741 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5742 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5743 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5744 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5745 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5746 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 5747 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 5748 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 5749 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 5750 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 5751 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 5752 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 5753 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 5754 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 5755 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 5756 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 5757 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 5758 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 5759 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 5760 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 5761 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 5762 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 5763 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 5764 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 5765 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 5766 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 5767 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 5768 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 5769 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 5770 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 5771 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 5772 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 5773 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 5774 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 5775 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 5776 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 5777 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 5778 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 5779 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 5780 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 5781 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 5782 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>, 5783 <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>; 5784 dma-coherent; 5785 }; 5786 5787 intc: interrupt-controller@17a00000 { 5788 compatible = "arm,gic-v3"; 5789 interrupt-controller; 5790 #interrupt-cells = <3>; 5791 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 5792 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 5793 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5794 #redistributor-regions = <1>; 5795 redistributor-stride = <0 0x20000>; 5796 5797 #address-cells = <2>; 5798 #size-cells = <2>; 5799 ranges; 5800 5801 its: msi-controller@17a40000 { 5802 compatible = "arm,gic-v3-its"; 5803 reg = <0 0x17a40000 0 0x20000>; 5804 msi-controller; 5805 #msi-cells = <1>; 5806 }; 5807 }; 5808 5809 watchdog@17c10000 { 5810 compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt"; 5811 reg = <0 0x17c10000 0 0x1000>; 5812 clocks = <&sleep_clk>; 5813 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 5814 }; 5815 5816 timer@17c20000 { 5817 compatible = "arm,armv7-timer-mem"; 5818 reg = <0x0 0x17c20000 0x0 0x1000>; 5819 #address-cells = <1>; 5820 #size-cells = <1>; 5821 ranges = <0x0 0x0 0x0 0x20000000>; 5822 5823 frame@17c21000 { 5824 frame-number = <0>; 5825 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5826 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5827 reg = <0x17c21000 0x1000>, 5828 <0x17c22000 0x1000>; 5829 }; 5830 5831 frame@17c23000 { 5832 frame-number = <1>; 5833 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5834 reg = <0x17c23000 0x1000>; 5835 status = "disabled"; 5836 }; 5837 5838 frame@17c25000 { 5839 frame-number = <2>; 5840 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5841 reg = <0x17c25000 0x1000>; 5842 status = "disabled"; 5843 }; 5844 5845 frame@17c27000 { 5846 frame-number = <3>; 5847 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5848 reg = <0x17c26000 0x1000>; 5849 status = "disabled"; 5850 }; 5851 5852 frame@17c29000 { 5853 frame-number = <4>; 5854 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5855 reg = <0x17c29000 0x1000>; 5856 status = "disabled"; 5857 }; 5858 5859 frame@17c2b000 { 5860 frame-number = <5>; 5861 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5862 reg = <0x17c2b000 0x1000>; 5863 status = "disabled"; 5864 }; 5865 5866 frame@17c2d000 { 5867 frame-number = <6>; 5868 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5869 reg = <0x17c2d000 0x1000>; 5870 status = "disabled"; 5871 }; 5872 }; 5873 5874 apps_rsc: rsc@18200000 { 5875 compatible = "qcom,rpmh-rsc"; 5876 reg = <0x0 0x18200000 0x0 0x10000>, 5877 <0x0 0x18210000 0x0 0x10000>, 5878 <0x0 0x18220000 0x0 0x10000>; 5879 reg-names = "drv-0", "drv-1", "drv-2"; 5880 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5881 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5882 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5883 qcom,tcs-offset = <0xd00>; 5884 qcom,drv-id = <2>; 5885 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 5886 <WAKE_TCS 3>, <CONTROL_TCS 1>; 5887 label = "apps_rsc"; 5888 power-domains = <&cluster_pd>; 5889 5890 apps_bcm_voter: bcm-voter { 5891 compatible = "qcom,bcm-voter"; 5892 }; 5893 5894 rpmhcc: clock-controller { 5895 compatible = "qcom,sc8280xp-rpmh-clk"; 5896 #clock-cells = <1>; 5897 clock-names = "xo"; 5898 clocks = <&xo_board_clk>; 5899 }; 5900 5901 rpmhpd: power-controller { 5902 compatible = "qcom,sc8280xp-rpmhpd"; 5903 #power-domain-cells = <1>; 5904 operating-points-v2 = <&rpmhpd_opp_table>; 5905 5906 rpmhpd_opp_table: opp-table { 5907 compatible = "operating-points-v2"; 5908 5909 rpmhpd_opp_ret: opp1 { 5910 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5911 }; 5912 5913 rpmhpd_opp_min_svs: opp2 { 5914 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5915 }; 5916 5917 rpmhpd_opp_low_svs: opp3 { 5918 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5919 }; 5920 5921 rpmhpd_opp_svs: opp4 { 5922 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5923 }; 5924 5925 rpmhpd_opp_svs_l1: opp5 { 5926 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5927 }; 5928 5929 rpmhpd_opp_nom: opp6 { 5930 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5931 }; 5932 5933 rpmhpd_opp_nom_l1: opp7 { 5934 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5935 }; 5936 5937 rpmhpd_opp_nom_l2: opp8 { 5938 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5939 }; 5940 5941 rpmhpd_opp_turbo: opp9 { 5942 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5943 }; 5944 5945 rpmhpd_opp_turbo_l1: opp10 { 5946 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5947 }; 5948 }; 5949 }; 5950 }; 5951 5952 epss_l3: interconnect@18590000 { 5953 compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3"; 5954 reg = <0 0x18590000 0 0x1000>; 5955 5956 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5957 clock-names = "xo", "alternate"; 5958 5959 #interconnect-cells = <1>; 5960 }; 5961 5962 cpufreq_hw: cpufreq@18591000 { 5963 compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss"; 5964 reg = <0 0x18591000 0 0x1000>, 5965 <0 0x18592000 0 0x1000>; 5966 reg-names = "freq-domain0", "freq-domain1"; 5967 5968 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5969 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 5970 interrupt-names = "dcvsh-irq-0", 5971 "dcvsh-irq-1"; 5972 5973 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5974 clock-names = "xo", "alternate"; 5975 5976 #freq-domain-cells = <1>; 5977 #clock-cells = <1>; 5978 }; 5979 5980 remoteproc_nsp0: remoteproc@1b300000 { 5981 compatible = "qcom,sc8280xp-nsp0-pas"; 5982 reg = <0 0x1b300000 0 0x10000>; 5983 5984 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 5985 <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>, 5986 <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>, 5987 <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>, 5988 <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>; 5989 interrupt-names = "wdog", "fatal", "ready", 5990 "handover", "stop-ack"; 5991 5992 clocks = <&rpmhcc RPMH_CXO_CLK>; 5993 clock-names = "xo"; 5994 5995 power-domains = <&rpmhpd SC8280XP_NSP>, 5996 <&rpmhpd SC8280XP_CX>, 5997 <&rpmhpd SC8280XP_MXC>; 5998 power-domain-names = "nsp", 5999 "cx", 6000 "mxc"; 6001 6002 memory-region = <&pil_nsp0_mem>; 6003 6004 qcom,smem-states = <&smp2p_nsp0_out 0>; 6005 qcom,smem-state-names = "stop"; 6006 6007 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 6008 6009 status = "disabled"; 6010 6011 glink-edge { 6012 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 6013 IPCC_MPROC_SIGNAL_GLINK_QMP 6014 IRQ_TYPE_EDGE_RISING>; 6015 mboxes = <&ipcc IPCC_CLIENT_CDSP 6016 IPCC_MPROC_SIGNAL_GLINK_QMP>; 6017 6018 label = "nsp0"; 6019 qcom,remote-pid = <5>; 6020 6021 fastrpc { 6022 compatible = "qcom,fastrpc"; 6023 qcom,glink-channels = "fastrpcglink-apps-dsp"; 6024 label = "cdsp"; 6025 #address-cells = <1>; 6026 #size-cells = <0>; 6027 6028 compute-cb@1 { 6029 compatible = "qcom,fastrpc-compute-cb"; 6030 reg = <1>; 6031 iommus = <&apps_smmu 0x3181 0x0420>; 6032 }; 6033 6034 compute-cb@2 { 6035 compatible = "qcom,fastrpc-compute-cb"; 6036 reg = <2>; 6037 iommus = <&apps_smmu 0x3182 0x0420>; 6038 }; 6039 6040 compute-cb@3 { 6041 compatible = "qcom,fastrpc-compute-cb"; 6042 reg = <3>; 6043 iommus = <&apps_smmu 0x3183 0x0420>; 6044 }; 6045 6046 compute-cb@4 { 6047 compatible = "qcom,fastrpc-compute-cb"; 6048 reg = <4>; 6049 iommus = <&apps_smmu 0x3184 0x0420>; 6050 }; 6051 6052 compute-cb@5 { 6053 compatible = "qcom,fastrpc-compute-cb"; 6054 reg = <5>; 6055 iommus = <&apps_smmu 0x3185 0x0420>; 6056 }; 6057 6058 compute-cb@6 { 6059 compatible = "qcom,fastrpc-compute-cb"; 6060 reg = <6>; 6061 iommus = <&apps_smmu 0x3186 0x0420>; 6062 }; 6063 6064 compute-cb@7 { 6065 compatible = "qcom,fastrpc-compute-cb"; 6066 reg = <7>; 6067 iommus = <&apps_smmu 0x3187 0x0420>; 6068 }; 6069 6070 compute-cb@8 { 6071 compatible = "qcom,fastrpc-compute-cb"; 6072 reg = <8>; 6073 iommus = <&apps_smmu 0x3188 0x0420>; 6074 }; 6075 6076 compute-cb@9 { 6077 compatible = "qcom,fastrpc-compute-cb"; 6078 reg = <9>; 6079 iommus = <&apps_smmu 0x318b 0x0420>; 6080 }; 6081 6082 compute-cb@10 { 6083 compatible = "qcom,fastrpc-compute-cb"; 6084 reg = <10>; 6085 iommus = <&apps_smmu 0x318b 0x0420>; 6086 }; 6087 6088 compute-cb@11 { 6089 compatible = "qcom,fastrpc-compute-cb"; 6090 reg = <11>; 6091 iommus = <&apps_smmu 0x318c 0x0420>; 6092 }; 6093 6094 compute-cb@12 { 6095 compatible = "qcom,fastrpc-compute-cb"; 6096 reg = <12>; 6097 iommus = <&apps_smmu 0x318d 0x0420>; 6098 }; 6099 6100 compute-cb@13 { 6101 compatible = "qcom,fastrpc-compute-cb"; 6102 reg = <13>; 6103 iommus = <&apps_smmu 0x318e 0x0420>; 6104 }; 6105 6106 compute-cb@14 { 6107 compatible = "qcom,fastrpc-compute-cb"; 6108 reg = <14>; 6109 iommus = <&apps_smmu 0x318f 0x0420>; 6110 }; 6111 }; 6112 }; 6113 }; 6114 6115 remoteproc_nsp1: remoteproc@21300000 { 6116 compatible = "qcom,sc8280xp-nsp1-pas"; 6117 reg = <0 0x21300000 0 0x10000>; 6118 6119 interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_EDGE_RISING>, 6120 <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>, 6121 <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>, 6122 <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>, 6123 <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>; 6124 interrupt-names = "wdog", "fatal", "ready", 6125 "handover", "stop-ack"; 6126 6127 clocks = <&rpmhcc RPMH_CXO_CLK>; 6128 clock-names = "xo"; 6129 6130 power-domains = <&rpmhpd SC8280XP_NSP>, 6131 <&rpmhpd SC8280XP_CX>, 6132 <&rpmhpd SC8280XP_MXC>; 6133 power-domain-names = "nsp", 6134 "cx", 6135 "mxc"; 6136 6137 memory-region = <&pil_nsp1_mem>; 6138 6139 qcom,smem-states = <&smp2p_nsp1_out 0>; 6140 qcom,smem-state-names = "stop"; 6141 6142 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>; 6143 6144 status = "disabled"; 6145 6146 glink-edge { 6147 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 6148 IPCC_MPROC_SIGNAL_GLINK_QMP 6149 IRQ_TYPE_EDGE_RISING>; 6150 mboxes = <&ipcc IPCC_CLIENT_NSP1 6151 IPCC_MPROC_SIGNAL_GLINK_QMP>; 6152 6153 label = "nsp1"; 6154 qcom,remote-pid = <12>; 6155 }; 6156 }; 6157 6158 mdss1: display-subsystem@22000000 { 6159 compatible = "qcom,sc8280xp-mdss"; 6160 reg = <0 0x22000000 0 0x1000>; 6161 reg-names = "mdss"; 6162 6163 clocks = <&gcc GCC_DISP_AHB_CLK>, 6164 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6165 <&dispcc1 DISP_CC_MDSS_MDP_CLK>; 6166 clock-names = "iface", 6167 "ahb", 6168 "core"; 6169 interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>, 6170 <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>; 6171 interconnect-names = "mdp0-mem", "mdp1-mem"; 6172 interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; 6173 6174 iommus = <&apps_smmu 0x1800 0x402>; 6175 power-domains = <&dispcc1 MDSS_GDSC>; 6176 resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>; 6177 6178 interrupt-controller; 6179 #interrupt-cells = <1>; 6180 #address-cells = <2>; 6181 #size-cells = <2>; 6182 ranges; 6183 6184 status = "disabled"; 6185 6186 mdss1_mdp: display-controller@22001000 { 6187 compatible = "qcom,sc8280xp-dpu"; 6188 reg = <0 0x22001000 0 0x8f000>, 6189 <0 0x220b0000 0 0x3000>; 6190 reg-names = "mdp", "vbif"; 6191 6192 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 6193 <&gcc GCC_DISP_SF_AXI_CLK>, 6194 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6195 <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>, 6196 <&dispcc1 DISP_CC_MDSS_MDP_CLK>, 6197 <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 6198 clock-names = "bus", 6199 "nrt_bus", 6200 "iface", 6201 "lut", 6202 "core", 6203 "vsync"; 6204 interrupt-parent = <&mdss1>; 6205 interrupts = <0>; 6206 power-domains = <&rpmhpd SC8280XP_MMCX>; 6207 6208 assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 6209 assigned-clock-rates = <19200000>; 6210 operating-points-v2 = <&mdss1_mdp_opp_table>; 6211 6212 ports { 6213 #address-cells = <1>; 6214 #size-cells = <0>; 6215 6216 port@0 { 6217 reg = <0>; 6218 6219 mdss1_intf0_out: endpoint { 6220 remote-endpoint = <&mdss1_dp0_in>; 6221 }; 6222 }; 6223 6224 port@1 { 6225 reg = <1>; 6226 6227 mdss1_intf1_out: endpoint { 6228 remote-endpoint = <&mdss1_dsi0_in>; 6229 }; 6230 }; 6231 6232 port@2 { 6233 reg = <2>; 6234 6235 mdss1_intf2_out: endpoint { 6236 remote-endpoint = <&mdss1_dsi1_in>; 6237 }; 6238 }; 6239 6240 port@4 { 6241 reg = <4>; 6242 6243 mdss1_intf4_out: endpoint { 6244 remote-endpoint = <&mdss1_dp1_in>; 6245 }; 6246 }; 6247 6248 port@5 { 6249 reg = <5>; 6250 6251 mdss1_intf5_out: endpoint { 6252 remote-endpoint = <&mdss1_dp3_in>; 6253 }; 6254 }; 6255 6256 port@6 { 6257 reg = <6>; 6258 6259 mdss1_intf6_out: endpoint { 6260 remote-endpoint = <&mdss1_dp2_in>; 6261 }; 6262 }; 6263 }; 6264 6265 mdss1_mdp_opp_table: opp-table { 6266 compatible = "operating-points-v2"; 6267 6268 opp-200000000 { 6269 opp-hz = /bits/ 64 <200000000>; 6270 required-opps = <&rpmhpd_opp_low_svs>; 6271 }; 6272 6273 opp-300000000 { 6274 opp-hz = /bits/ 64 <300000000>; 6275 required-opps = <&rpmhpd_opp_svs>; 6276 }; 6277 6278 opp-375000000 { 6279 opp-hz = /bits/ 64 <375000000>; 6280 required-opps = <&rpmhpd_opp_svs_l1>; 6281 }; 6282 6283 opp-500000000 { 6284 opp-hz = /bits/ 64 <500000000>; 6285 required-opps = <&rpmhpd_opp_nom>; 6286 }; 6287 opp-600000000 { 6288 opp-hz = /bits/ 64 <600000000>; 6289 required-opps = <&rpmhpd_opp_turbo_l1>; 6290 }; 6291 }; 6292 }; 6293 6294 mdss1_dp0: displayport-controller@22090000 { 6295 compatible = "qcom,sc8280xp-dp"; 6296 reg = <0 0x22090000 0 0x200>, 6297 <0 0x22090200 0 0x200>, 6298 <0 0x22090400 0 0x600>, 6299 <0 0x22091000 0 0x400>, 6300 <0 0x22091400 0 0x400>; 6301 6302 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6303 <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 6304 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>, 6305 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 6306 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 6307 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; 6308 clock-names = "core_iface", "core_aux", 6309 "ctrl_link", 6310 "ctrl_link_iface", "stream_pixel", 6311 "stream_1_pixel"; 6312 interrupt-parent = <&mdss1>; 6313 interrupts = <12>; 6314 phys = <&mdss1_dp0_phy>; 6315 phy-names = "dp"; 6316 power-domains = <&rpmhpd SC8280XP_MMCX>; 6317 6318 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 6319 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 6320 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; 6321 assigned-clock-parents = <&mdss1_dp0_phy 0>, 6322 <&mdss1_dp0_phy 1>, 6323 <&mdss1_dp0_phy 1>; 6324 operating-points-v2 = <&mdss1_dp0_opp_table>; 6325 6326 #sound-dai-cells = <0>; 6327 6328 status = "disabled"; 6329 6330 ports { 6331 #address-cells = <1>; 6332 #size-cells = <0>; 6333 6334 port@0 { 6335 reg = <0>; 6336 mdss1_dp0_in: endpoint { 6337 remote-endpoint = <&mdss1_intf0_out>; 6338 }; 6339 }; 6340 6341 port@1 { 6342 reg = <1>; 6343 6344 mdss1_dp0_out: endpoint { 6345 }; 6346 }; 6347 }; 6348 6349 mdss1_dp0_opp_table: opp-table { 6350 compatible = "operating-points-v2"; 6351 6352 opp-162000000 { 6353 opp-hz = /bits/ 64 <162000000>; 6354 required-opps = <&rpmhpd_opp_low_svs>; 6355 }; 6356 6357 opp-270000000 { 6358 opp-hz = /bits/ 64 <270000000>; 6359 required-opps = <&rpmhpd_opp_svs>; 6360 }; 6361 6362 opp-540000000 { 6363 opp-hz = /bits/ 64 <540000000>; 6364 required-opps = <&rpmhpd_opp_svs_l1>; 6365 }; 6366 6367 opp-810000000 { 6368 opp-hz = /bits/ 64 <810000000>; 6369 required-opps = <&rpmhpd_opp_nom>; 6370 }; 6371 }; 6372 }; 6373 6374 mdss1_dsi0: dsi@22094000 { 6375 compatible = "qcom,sc8280xp-dsi-ctrl", 6376 "qcom,sa8775p-dsi-ctrl", 6377 "qcom,mdss-dsi-ctrl"; 6378 reg = <0 0x22094000 0 0x400>; 6379 reg-names = "dsi_ctrl"; 6380 6381 interrupt-parent = <&mdss1>; 6382 interrupts = <4>; 6383 6384 clocks = <&dispcc1 DISP_CC_MDSS_BYTE0_CLK>, 6385 <&dispcc1 DISP_CC_MDSS_BYTE0_INTF_CLK>, 6386 <&dispcc1 DISP_CC_MDSS_PCLK0_CLK>, 6387 <&dispcc1 DISP_CC_MDSS_ESC0_CLK>, 6388 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6389 <&gcc GCC_DISP_HF_AXI_CLK>; 6390 clock-names = "byte", 6391 "byte_intf", 6392 "pixel", 6393 "core", 6394 "iface", 6395 "bus"; 6396 6397 assigned-clocks = <&dispcc1 DISP_CC_MDSS_BYTE0_CLK_SRC>, 6398 <&dispcc1 DISP_CC_MDSS_PCLK0_CLK_SRC>; 6399 assigned-clock-parents = <&mdss1_dsi1_phy DSI_BYTE_PLL_CLK>, 6400 <&mdss1_dsi0_phy DSI_PIXEL_PLL_CLK>; 6401 6402 operating-points-v2 = <&dsi_opp_table>; 6403 power-domains = <&rpmhpd SC8280XP_MMCX>; 6404 6405 refgen-supply = <&refgen>; 6406 6407 phys = <&mdss1_dsi0_phy>; 6408 phy-names = "dsi"; 6409 6410 #address-cells = <1>; 6411 #size-cells = <0>; 6412 6413 status = "disabled"; 6414 6415 ports { 6416 #address-cells = <1>; 6417 #size-cells = <0>; 6418 6419 port@0 { 6420 reg = <0>; 6421 6422 mdss1_dsi0_in: endpoint { 6423 remote-endpoint = <&mdss1_intf1_out>; 6424 }; 6425 }; 6426 6427 port@1 { 6428 reg = <1>; 6429 6430 mdss1_dsi0_out: endpoint { 6431 }; 6432 }; 6433 }; 6434 }; 6435 6436 mdss1_dsi0_phy: phy@22094400 { 6437 compatible = "qcom,sc8280xp-dsi-phy-5nm", 6438 "qcom,sa8775p-dsi-phy-5nm"; 6439 reg = <0 0x22094400 0 0x200>, 6440 <0 0x22094600 0 0x280>, 6441 <0 0x22094900 0 0x280>; 6442 reg-names = "dsi_phy", 6443 "dsi_phy_lane", 6444 "dsi_pll"; 6445 6446 #clock-cells = <1>; 6447 #phy-cells = <0>; 6448 6449 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6450 <&rpmhcc RPMH_CXO_CLK>; 6451 clock-names = "iface", "ref"; 6452 6453 status = "disabled"; 6454 }; 6455 6456 mdss1_dsi1: dsi@22096000 { 6457 compatible = "qcom,sc8280xp-dsi-ctrl", 6458 "qcom,sa8775p-dsi-ctrl", 6459 "qcom,mdss-dsi-ctrl"; 6460 reg = <0 0x22096000 0 0x400>; 6461 reg-names = "dsi_ctrl"; 6462 6463 interrupt-parent = <&mdss1>; 6464 interrupts = <5>; 6465 6466 clocks = <&dispcc1 DISP_CC_MDSS_BYTE1_CLK>, 6467 <&dispcc1 DISP_CC_MDSS_BYTE1_INTF_CLK>, 6468 <&dispcc1 DISP_CC_MDSS_PCLK1_CLK>, 6469 <&dispcc1 DISP_CC_MDSS_ESC1_CLK>, 6470 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6471 <&gcc GCC_DISP_HF_AXI_CLK>; 6472 clock-names = "byte", 6473 "byte_intf", 6474 "pixel", 6475 "core", 6476 "iface", 6477 "bus"; 6478 6479 assigned-clocks = <&dispcc1 DISP_CC_MDSS_BYTE1_CLK_SRC>, 6480 <&dispcc1 DISP_CC_MDSS_PCLK1_CLK_SRC>; 6481 assigned-clock-parents = <&mdss1_dsi1_phy DSI_BYTE_PLL_CLK>, 6482 <&mdss1_dsi1_phy DSI_PIXEL_PLL_CLK>; 6483 6484 operating-points-v2 = <&dsi_opp_table>; 6485 power-domains = <&rpmhpd SC8280XP_MMCX>; 6486 6487 refgen-supply = <&refgen>; 6488 6489 phys = <&mdss1_dsi1_phy>; 6490 phy-names = "dsi"; 6491 6492 #address-cells = <1>; 6493 #size-cells = <0>; 6494 6495 status = "disabled"; 6496 6497 ports { 6498 #address-cells = <1>; 6499 #size-cells = <0>; 6500 6501 port@0 { 6502 reg = <0>; 6503 6504 mdss1_dsi1_in: endpoint { 6505 remote-endpoint = <&mdss1_intf2_out>; 6506 }; 6507 }; 6508 6509 port@1 { 6510 reg = <1>; 6511 6512 mdss1_dsi1_out: endpoint { 6513 }; 6514 }; 6515 }; 6516 }; 6517 6518 mdss1_dsi1_phy: phy@22096400 { 6519 compatible = "qcom,sc8280xp-dsi-phy-5nm", 6520 "qcom,sa8775p-dsi-phy-5nm"; 6521 reg = <0 0x22096400 0 0x200>, 6522 <0 0x22096600 0 0x280>, 6523 <0 0x22096900 0 0x280>; 6524 reg-names = "dsi_phy", 6525 "dsi_phy_lane", 6526 "dsi_pll"; 6527 6528 #clock-cells = <1>; 6529 #phy-cells = <0>; 6530 6531 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6532 <&rpmhcc RPMH_CXO_CLK>; 6533 clock-names = "iface", "ref"; 6534 6535 status = "disabled"; 6536 }; 6537 6538 mdss1_dp1: displayport-controller@22098000 { 6539 compatible = "qcom,sc8280xp-dp"; 6540 reg = <0 0x22098000 0 0x200>, 6541 <0 0x22098200 0 0x200>, 6542 <0 0x22098400 0 0x600>, 6543 <0 0x22099000 0 0x400>, 6544 <0 0x22099400 0 0x400>; 6545 6546 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6547 <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 6548 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>, 6549 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 6550 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, 6551 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; 6552 clock-names = "core_iface", "core_aux", 6553 "ctrl_link", 6554 "ctrl_link_iface", "stream_pixel", 6555 "stream_1_pixel"; 6556 interrupt-parent = <&mdss1>; 6557 interrupts = <13>; 6558 phys = <&mdss1_dp1_phy>; 6559 phy-names = "dp"; 6560 power-domains = <&rpmhpd SC8280XP_MMCX>; 6561 6562 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 6563 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, 6564 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; 6565 assigned-clock-parents = <&mdss1_dp1_phy 0>, 6566 <&mdss1_dp1_phy 1>, 6567 <&mdss1_dp1_phy 1>; 6568 operating-points-v2 = <&mdss1_dp1_opp_table>; 6569 6570 #sound-dai-cells = <0>; 6571 6572 status = "disabled"; 6573 6574 ports { 6575 #address-cells = <1>; 6576 #size-cells = <0>; 6577 6578 port@0 { 6579 reg = <0>; 6580 mdss1_dp1_in: endpoint { 6581 remote-endpoint = <&mdss1_intf4_out>; 6582 }; 6583 }; 6584 6585 port@1 { 6586 reg = <1>; 6587 6588 mdss1_dp1_out: endpoint { 6589 }; 6590 }; 6591 }; 6592 6593 mdss1_dp1_opp_table: opp-table { 6594 compatible = "operating-points-v2"; 6595 6596 opp-162000000 { 6597 opp-hz = /bits/ 64 <162000000>; 6598 required-opps = <&rpmhpd_opp_low_svs>; 6599 }; 6600 6601 opp-270000000 { 6602 opp-hz = /bits/ 64 <270000000>; 6603 required-opps = <&rpmhpd_opp_svs>; 6604 }; 6605 6606 opp-540000000 { 6607 opp-hz = /bits/ 64 <540000000>; 6608 required-opps = <&rpmhpd_opp_svs_l1>; 6609 }; 6610 6611 opp-810000000 { 6612 opp-hz = /bits/ 64 <810000000>; 6613 required-opps = <&rpmhpd_opp_nom>; 6614 }; 6615 }; 6616 }; 6617 6618 mdss1_dp2: displayport-controller@2209a000 { 6619 compatible = "qcom,sc8280xp-dp"; 6620 reg = <0 0x2209a000 0 0x200>, 6621 <0 0x2209a200 0 0x200>, 6622 <0 0x2209a400 0 0x600>, 6623 <0 0x2209b000 0 0x400>, 6624 <0 0x2209b400 0 0x400>; 6625 6626 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6627 <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 6628 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>, 6629 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 6630 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, 6631 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; 6632 clock-names = "core_iface", "core_aux", 6633 "ctrl_link", 6634 "ctrl_link_iface", "stream_pixel", 6635 "stream_1_pixel"; 6636 interrupt-parent = <&mdss1>; 6637 interrupts = <14>; 6638 phys = <&mdss1_dp2_phy>; 6639 phy-names = "dp"; 6640 power-domains = <&rpmhpd SC8280XP_MMCX>; 6641 6642 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 6643 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, 6644 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; 6645 assigned-clock-parents = <&mdss1_dp2_phy 0>, 6646 <&mdss1_dp2_phy 1>, 6647 <&mdss1_dp2_phy 1>; 6648 operating-points-v2 = <&mdss1_dp2_opp_table>; 6649 6650 #sound-dai-cells = <0>; 6651 6652 status = "disabled"; 6653 6654 ports { 6655 #address-cells = <1>; 6656 #size-cells = <0>; 6657 6658 port@0 { 6659 reg = <0>; 6660 mdss1_dp2_in: endpoint { 6661 remote-endpoint = <&mdss1_intf6_out>; 6662 }; 6663 }; 6664 6665 port@1 { 6666 reg = <1>; 6667 6668 mdss1_dp2_out: endpoint { 6669 }; 6670 }; 6671 }; 6672 6673 mdss1_dp2_opp_table: opp-table { 6674 compatible = "operating-points-v2"; 6675 6676 opp-162000000 { 6677 opp-hz = /bits/ 64 <162000000>; 6678 required-opps = <&rpmhpd_opp_low_svs>; 6679 }; 6680 6681 opp-270000000 { 6682 opp-hz = /bits/ 64 <270000000>; 6683 required-opps = <&rpmhpd_opp_svs>; 6684 }; 6685 6686 opp-540000000 { 6687 opp-hz = /bits/ 64 <540000000>; 6688 required-opps = <&rpmhpd_opp_svs_l1>; 6689 }; 6690 6691 opp-810000000 { 6692 opp-hz = /bits/ 64 <810000000>; 6693 required-opps = <&rpmhpd_opp_nom>; 6694 }; 6695 }; 6696 }; 6697 6698 mdss1_dp3: displayport-controller@220a0000 { 6699 compatible = "qcom,sc8280xp-dp"; 6700 reg = <0 0x220a0000 0 0x200>, 6701 <0 0x220a0200 0 0x200>, 6702 <0 0x220a0400 0 0x600>, 6703 <0 0x220a1000 0 0x400>, 6704 <0 0x220a1400 0 0x400>; 6705 6706 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6707 <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 6708 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK>, 6709 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 6710 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 6711 clock-names = "core_iface", "core_aux", 6712 "ctrl_link", 6713 "ctrl_link_iface", "stream_pixel"; 6714 interrupt-parent = <&mdss1>; 6715 interrupts = <15>; 6716 phys = <&mdss1_dp3_phy>; 6717 phy-names = "dp"; 6718 power-domains = <&rpmhpd SC8280XP_MMCX>; 6719 6720 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 6721 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 6722 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>; 6723 operating-points-v2 = <&mdss1_dp3_opp_table>; 6724 6725 #sound-dai-cells = <0>; 6726 6727 status = "disabled"; 6728 6729 ports { 6730 #address-cells = <1>; 6731 #size-cells = <0>; 6732 6733 port@0 { 6734 reg = <0>; 6735 mdss1_dp3_in: endpoint { 6736 remote-endpoint = <&mdss1_intf5_out>; 6737 }; 6738 }; 6739 6740 port@1 { 6741 reg = <1>; 6742 6743 mdss1_dp3_out: endpoint { 6744 }; 6745 }; 6746 }; 6747 6748 mdss1_dp3_opp_table: opp-table { 6749 compatible = "operating-points-v2"; 6750 6751 opp-162000000 { 6752 opp-hz = /bits/ 64 <162000000>; 6753 required-opps = <&rpmhpd_opp_low_svs>; 6754 }; 6755 6756 opp-270000000 { 6757 opp-hz = /bits/ 64 <270000000>; 6758 required-opps = <&rpmhpd_opp_svs>; 6759 }; 6760 6761 opp-540000000 { 6762 opp-hz = /bits/ 64 <540000000>; 6763 required-opps = <&rpmhpd_opp_svs_l1>; 6764 }; 6765 6766 opp-810000000 { 6767 opp-hz = /bits/ 64 <810000000>; 6768 required-opps = <&rpmhpd_opp_nom>; 6769 }; 6770 }; 6771 }; 6772 }; 6773 6774 mdss1_dp2_phy: phy@220c2a00 { 6775 compatible = "qcom,sc8280xp-dp-phy"; 6776 reg = <0 0x220c2a00 0 0x19c>, 6777 <0 0x220c2200 0 0xec>, 6778 <0 0x220c2600 0 0xec>, 6779 <0 0x220c2000 0 0x1c8>; 6780 6781 clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 6782 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 6783 clock-names = "aux", "cfg_ahb"; 6784 power-domains = <&rpmhpd SC8280XP_MX>; 6785 6786 #clock-cells = <1>; 6787 #phy-cells = <0>; 6788 6789 status = "disabled"; 6790 }; 6791 6792 mdss1_dp3_phy: phy@220c5a00 { 6793 compatible = "qcom,sc8280xp-dp-phy"; 6794 reg = <0 0x220c5a00 0 0x19c>, 6795 <0 0x220c5200 0 0xec>, 6796 <0 0x220c5600 0 0xec>, 6797 <0 0x220c5000 0 0x1c8>; 6798 6799 clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 6800 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 6801 clock-names = "aux", "cfg_ahb"; 6802 power-domains = <&rpmhpd SC8280XP_MX>; 6803 6804 #clock-cells = <1>; 6805 #phy-cells = <0>; 6806 6807 status = "disabled"; 6808 }; 6809 6810 dispcc1: clock-controller@22100000 { 6811 compatible = "qcom,sc8280xp-dispcc1"; 6812 reg = <0 0x22100000 0 0x20000>; 6813 6814 clocks = <&gcc GCC_DISP_AHB_CLK>, 6815 <&rpmhcc RPMH_CXO_CLK>, 6816 <0>, 6817 <&mdss1_dp0_phy 0>, 6818 <&mdss1_dp0_phy 1>, 6819 <&mdss1_dp1_phy 0>, 6820 <&mdss1_dp1_phy 1>, 6821 <&mdss1_dp2_phy 0>, 6822 <&mdss1_dp2_phy 1>, 6823 <&mdss1_dp3_phy 0>, 6824 <&mdss1_dp3_phy 1>, 6825 <&mdss1_dsi0_phy DSI_BYTE_PLL_CLK>, 6826 <&mdss1_dsi0_phy DSI_PIXEL_PLL_CLK>, 6827 <&mdss1_dsi1_phy DSI_BYTE_PLL_CLK>, 6828 <&mdss1_dsi1_phy DSI_PIXEL_PLL_CLK>; 6829 power-domains = <&rpmhpd SC8280XP_MMCX>; 6830 6831 #clock-cells = <1>; 6832 #power-domain-cells = <1>; 6833 #reset-cells = <1>; 6834 6835 status = "disabled"; 6836 }; 6837 6838 ethernet1: ethernet@23000000 { 6839 compatible = "qcom,sc8280xp-ethqos"; 6840 reg = <0x0 0x23000000 0x0 0x10000>, 6841 <0x0 0x23016000 0x0 0x100>; 6842 reg-names = "stmmaceth", "rgmii"; 6843 6844 clocks = <&gcc GCC_EMAC1_AXI_CLK>, 6845 <&gcc GCC_EMAC1_SLV_AHB_CLK>, 6846 <&gcc GCC_EMAC1_PTP_CLK>, 6847 <&gcc GCC_EMAC1_RGMII_CLK>; 6848 clock-names = "stmmaceth", 6849 "pclk", 6850 "ptp_ref", 6851 "rgmii"; 6852 6853 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, 6854 <GIC_SPI 919 IRQ_TYPE_LEVEL_HIGH>; 6855 interrupt-names = "macirq", "eth_lpi"; 6856 6857 iommus = <&apps_smmu 0x40 0xf>; 6858 power-domains = <&gcc EMAC_1_GDSC>; 6859 6860 snps,tso; 6861 snps,pbl = <32>; 6862 rx-fifo-depth = <4096>; 6863 tx-fifo-depth = <4096>; 6864 6865 status = "disabled"; 6866 }; 6867 }; 6868 6869 sound: sound { 6870 }; 6871 6872 thermal-zones { 6873 cpu0-thermal { 6874 polling-delay-passive = <250>; 6875 6876 thermal-sensors = <&tsens0 1>; 6877 6878 trips { 6879 cpu-crit { 6880 temperature = <110000>; 6881 hysteresis = <1000>; 6882 type = "critical"; 6883 }; 6884 }; 6885 }; 6886 6887 cpu1-thermal { 6888 polling-delay-passive = <250>; 6889 6890 thermal-sensors = <&tsens0 2>; 6891 6892 trips { 6893 cpu-crit { 6894 temperature = <110000>; 6895 hysteresis = <1000>; 6896 type = "critical"; 6897 }; 6898 }; 6899 }; 6900 6901 cpu2-thermal { 6902 polling-delay-passive = <250>; 6903 6904 thermal-sensors = <&tsens0 3>; 6905 6906 trips { 6907 cpu-crit { 6908 temperature = <110000>; 6909 hysteresis = <1000>; 6910 type = "critical"; 6911 }; 6912 }; 6913 }; 6914 6915 cpu3-thermal { 6916 polling-delay-passive = <250>; 6917 6918 thermal-sensors = <&tsens0 4>; 6919 6920 trips { 6921 cpu-crit { 6922 temperature = <110000>; 6923 hysteresis = <1000>; 6924 type = "critical"; 6925 }; 6926 }; 6927 }; 6928 6929 cpu4-thermal { 6930 polling-delay-passive = <250>; 6931 6932 thermal-sensors = <&tsens0 5>; 6933 6934 trips { 6935 cpu-crit { 6936 temperature = <110000>; 6937 hysteresis = <1000>; 6938 type = "critical"; 6939 }; 6940 }; 6941 }; 6942 6943 cpu5-thermal { 6944 polling-delay-passive = <250>; 6945 6946 thermal-sensors = <&tsens0 6>; 6947 6948 trips { 6949 cpu-crit { 6950 temperature = <110000>; 6951 hysteresis = <1000>; 6952 type = "critical"; 6953 }; 6954 }; 6955 }; 6956 6957 cpu6-thermal { 6958 polling-delay-passive = <250>; 6959 6960 thermal-sensors = <&tsens0 7>; 6961 6962 trips { 6963 cpu-crit { 6964 temperature = <110000>; 6965 hysteresis = <1000>; 6966 type = "critical"; 6967 }; 6968 }; 6969 }; 6970 6971 cpu7-thermal { 6972 polling-delay-passive = <250>; 6973 6974 thermal-sensors = <&tsens0 8>; 6975 6976 trips { 6977 cpu-crit { 6978 temperature = <110000>; 6979 hysteresis = <1000>; 6980 type = "critical"; 6981 }; 6982 }; 6983 }; 6984 6985 cluster0-thermal { 6986 polling-delay-passive = <250>; 6987 6988 thermal-sensors = <&tsens0 9>; 6989 6990 trips { 6991 cpu-crit { 6992 temperature = <110000>; 6993 hysteresis = <1000>; 6994 type = "critical"; 6995 }; 6996 }; 6997 }; 6998 6999 gpu-thermal { 7000 polling-delay-passive = <250>; 7001 7002 thermal-sensors = <&tsens2 2>; 7003 7004 cooling-maps { 7005 map0 { 7006 trip = <&gpu_alert0>; 7007 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7008 }; 7009 }; 7010 7011 trips { 7012 gpu_alert0: trip-point0 { 7013 temperature = <85000>; 7014 hysteresis = <1000>; 7015 type = "passive"; 7016 }; 7017 7018 trip-point1 { 7019 temperature = <110000>; 7020 hysteresis = <1000>; 7021 type = "critical"; 7022 }; 7023 }; 7024 }; 7025 7026 mem-thermal { 7027 polling-delay-passive = <250>; 7028 7029 thermal-sensors = <&tsens1 15>; 7030 7031 trips { 7032 trip-point0 { 7033 temperature = <90000>; 7034 hysteresis = <2000>; 7035 type = "hot"; 7036 }; 7037 }; 7038 }; 7039 }; 7040 7041 timer { 7042 compatible = "arm,armv8-timer"; 7043 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 7044 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 7045 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 7046 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 7047 }; 7048}; 7049