1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Linaro Limited 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> 8#include <dt-bindings/clock/qcom,gcc-sc8280xp.h> 9#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sc8280xp-camcc.h> 12#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> 13#include <dt-bindings/interconnect/qcom,osm-l3.h> 14#include <dt-bindings/interconnect/qcom,sc8280xp.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/phy/phy-qcom-qmp.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/soc/qcom,gpr.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/sound/qcom,q6afe.h> 22#include <dt-bindings/thermal/thermal.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 clocks { 31 xo_board_clk: xo-board-clk { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 }; 35 36 sleep_clk: sleep-clk { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <32764>; 40 }; 41 }; 42 43 cpus { 44 #address-cells = <2>; 45 #size-cells = <0>; 46 47 CPU0: cpu@0 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a78c"; 50 reg = <0x0 0x0>; 51 clocks = <&cpufreq_hw 0>; 52 enable-method = "psci"; 53 capacity-dmips-mhz = <602>; 54 next-level-cache = <&L2_0>; 55 power-domains = <&CPU_PD0>; 56 power-domain-names = "psci"; 57 qcom,freq-domain = <&cpufreq_hw 0>; 58 operating-points-v2 = <&cpu0_opp_table>; 59 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 60 #cooling-cells = <2>; 61 L2_0: l2-cache { 62 compatible = "cache"; 63 cache-level = <2>; 64 cache-unified; 65 next-level-cache = <&L3_0>; 66 L3_0: l3-cache { 67 compatible = "cache"; 68 cache-level = <3>; 69 cache-unified; 70 }; 71 }; 72 }; 73 74 CPU1: cpu@100 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a78c"; 77 reg = <0x0 0x100>; 78 clocks = <&cpufreq_hw 0>; 79 enable-method = "psci"; 80 capacity-dmips-mhz = <602>; 81 next-level-cache = <&L2_100>; 82 power-domains = <&CPU_PD1>; 83 power-domain-names = "psci"; 84 qcom,freq-domain = <&cpufreq_hw 0>; 85 operating-points-v2 = <&cpu0_opp_table>; 86 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 87 #cooling-cells = <2>; 88 L2_100: l2-cache { 89 compatible = "cache"; 90 cache-level = <2>; 91 cache-unified; 92 next-level-cache = <&L3_0>; 93 }; 94 }; 95 96 CPU2: cpu@200 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a78c"; 99 reg = <0x0 0x200>; 100 clocks = <&cpufreq_hw 0>; 101 enable-method = "psci"; 102 capacity-dmips-mhz = <602>; 103 next-level-cache = <&L2_200>; 104 power-domains = <&CPU_PD2>; 105 power-domain-names = "psci"; 106 qcom,freq-domain = <&cpufreq_hw 0>; 107 operating-points-v2 = <&cpu0_opp_table>; 108 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 109 #cooling-cells = <2>; 110 L2_200: l2-cache { 111 compatible = "cache"; 112 cache-level = <2>; 113 cache-unified; 114 next-level-cache = <&L3_0>; 115 }; 116 }; 117 118 CPU3: cpu@300 { 119 device_type = "cpu"; 120 compatible = "arm,cortex-a78c"; 121 reg = <0x0 0x300>; 122 clocks = <&cpufreq_hw 0>; 123 enable-method = "psci"; 124 capacity-dmips-mhz = <602>; 125 next-level-cache = <&L2_300>; 126 power-domains = <&CPU_PD3>; 127 power-domain-names = "psci"; 128 qcom,freq-domain = <&cpufreq_hw 0>; 129 operating-points-v2 = <&cpu0_opp_table>; 130 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 131 #cooling-cells = <2>; 132 L2_300: l2-cache { 133 compatible = "cache"; 134 cache-level = <2>; 135 cache-unified; 136 next-level-cache = <&L3_0>; 137 }; 138 }; 139 140 CPU4: cpu@400 { 141 device_type = "cpu"; 142 compatible = "arm,cortex-x1c"; 143 reg = <0x0 0x400>; 144 clocks = <&cpufreq_hw 1>; 145 enable-method = "psci"; 146 capacity-dmips-mhz = <1024>; 147 next-level-cache = <&L2_400>; 148 power-domains = <&CPU_PD4>; 149 power-domain-names = "psci"; 150 qcom,freq-domain = <&cpufreq_hw 1>; 151 operating-points-v2 = <&cpu4_opp_table>; 152 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 153 #cooling-cells = <2>; 154 L2_400: l2-cache { 155 compatible = "cache"; 156 cache-level = <2>; 157 cache-unified; 158 next-level-cache = <&L3_0>; 159 }; 160 }; 161 162 CPU5: cpu@500 { 163 device_type = "cpu"; 164 compatible = "arm,cortex-x1c"; 165 reg = <0x0 0x500>; 166 clocks = <&cpufreq_hw 1>; 167 enable-method = "psci"; 168 capacity-dmips-mhz = <1024>; 169 next-level-cache = <&L2_500>; 170 power-domains = <&CPU_PD5>; 171 power-domain-names = "psci"; 172 qcom,freq-domain = <&cpufreq_hw 1>; 173 operating-points-v2 = <&cpu4_opp_table>; 174 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 175 #cooling-cells = <2>; 176 L2_500: l2-cache { 177 compatible = "cache"; 178 cache-level = <2>; 179 cache-unified; 180 next-level-cache = <&L3_0>; 181 }; 182 }; 183 184 CPU6: cpu@600 { 185 device_type = "cpu"; 186 compatible = "arm,cortex-x1c"; 187 reg = <0x0 0x600>; 188 clocks = <&cpufreq_hw 1>; 189 enable-method = "psci"; 190 capacity-dmips-mhz = <1024>; 191 next-level-cache = <&L2_600>; 192 power-domains = <&CPU_PD6>; 193 power-domain-names = "psci"; 194 qcom,freq-domain = <&cpufreq_hw 1>; 195 operating-points-v2 = <&cpu4_opp_table>; 196 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 197 #cooling-cells = <2>; 198 L2_600: l2-cache { 199 compatible = "cache"; 200 cache-level = <2>; 201 cache-unified; 202 next-level-cache = <&L3_0>; 203 }; 204 }; 205 206 CPU7: cpu@700 { 207 device_type = "cpu"; 208 compatible = "arm,cortex-x1c"; 209 reg = <0x0 0x700>; 210 clocks = <&cpufreq_hw 1>; 211 enable-method = "psci"; 212 capacity-dmips-mhz = <1024>; 213 next-level-cache = <&L2_700>; 214 power-domains = <&CPU_PD7>; 215 power-domain-names = "psci"; 216 qcom,freq-domain = <&cpufreq_hw 1>; 217 operating-points-v2 = <&cpu4_opp_table>; 218 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 219 #cooling-cells = <2>; 220 L2_700: l2-cache { 221 compatible = "cache"; 222 cache-level = <2>; 223 cache-unified; 224 next-level-cache = <&L3_0>; 225 }; 226 }; 227 228 cpu-map { 229 cluster0 { 230 core0 { 231 cpu = <&CPU0>; 232 }; 233 234 core1 { 235 cpu = <&CPU1>; 236 }; 237 238 core2 { 239 cpu = <&CPU2>; 240 }; 241 242 core3 { 243 cpu = <&CPU3>; 244 }; 245 246 core4 { 247 cpu = <&CPU4>; 248 }; 249 250 core5 { 251 cpu = <&CPU5>; 252 }; 253 254 core6 { 255 cpu = <&CPU6>; 256 }; 257 258 core7 { 259 cpu = <&CPU7>; 260 }; 261 }; 262 }; 263 264 idle-states { 265 entry-method = "psci"; 266 267 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 268 compatible = "arm,idle-state"; 269 idle-state-name = "little-rail-power-collapse"; 270 arm,psci-suspend-param = <0x40000004>; 271 entry-latency-us = <355>; 272 exit-latency-us = <909>; 273 min-residency-us = <3934>; 274 local-timer-stop; 275 }; 276 277 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 278 compatible = "arm,idle-state"; 279 idle-state-name = "big-rail-power-collapse"; 280 arm,psci-suspend-param = <0x40000004>; 281 entry-latency-us = <241>; 282 exit-latency-us = <1461>; 283 min-residency-us = <4488>; 284 local-timer-stop; 285 }; 286 }; 287 288 domain-idle-states { 289 CLUSTER_SLEEP_0: cluster-sleep-0 { 290 compatible = "domain-idle-state"; 291 arm,psci-suspend-param = <0x4100c344>; 292 entry-latency-us = <3263>; 293 exit-latency-us = <6562>; 294 min-residency-us = <9987>; 295 }; 296 }; 297 }; 298 299 firmware { 300 scm: scm { 301 compatible = "qcom,scm-sc8280xp", "qcom,scm"; 302 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 303 }; 304 }; 305 306 aggre1_noc: interconnect-aggre1-noc { 307 compatible = "qcom,sc8280xp-aggre1-noc"; 308 #interconnect-cells = <2>; 309 qcom,bcm-voters = <&apps_bcm_voter>; 310 }; 311 312 aggre2_noc: interconnect-aggre2-noc { 313 compatible = "qcom,sc8280xp-aggre2-noc"; 314 #interconnect-cells = <2>; 315 qcom,bcm-voters = <&apps_bcm_voter>; 316 }; 317 318 clk_virt: interconnect-clk-virt { 319 compatible = "qcom,sc8280xp-clk-virt"; 320 #interconnect-cells = <2>; 321 qcom,bcm-voters = <&apps_bcm_voter>; 322 }; 323 324 config_noc: interconnect-config-noc { 325 compatible = "qcom,sc8280xp-config-noc"; 326 #interconnect-cells = <2>; 327 qcom,bcm-voters = <&apps_bcm_voter>; 328 }; 329 330 dc_noc: interconnect-dc-noc { 331 compatible = "qcom,sc8280xp-dc-noc"; 332 #interconnect-cells = <2>; 333 qcom,bcm-voters = <&apps_bcm_voter>; 334 }; 335 336 gem_noc: interconnect-gem-noc { 337 compatible = "qcom,sc8280xp-gem-noc"; 338 #interconnect-cells = <2>; 339 qcom,bcm-voters = <&apps_bcm_voter>; 340 }; 341 342 lpass_noc: interconnect-lpass-ag-noc { 343 compatible = "qcom,sc8280xp-lpass-ag-noc"; 344 #interconnect-cells = <2>; 345 qcom,bcm-voters = <&apps_bcm_voter>; 346 }; 347 348 mc_virt: interconnect-mc-virt { 349 compatible = "qcom,sc8280xp-mc-virt"; 350 #interconnect-cells = <2>; 351 qcom,bcm-voters = <&apps_bcm_voter>; 352 }; 353 354 mmss_noc: interconnect-mmss-noc { 355 compatible = "qcom,sc8280xp-mmss-noc"; 356 #interconnect-cells = <2>; 357 qcom,bcm-voters = <&apps_bcm_voter>; 358 }; 359 360 nspa_noc: interconnect-nspa-noc { 361 compatible = "qcom,sc8280xp-nspa-noc"; 362 #interconnect-cells = <2>; 363 qcom,bcm-voters = <&apps_bcm_voter>; 364 }; 365 366 nspb_noc: interconnect-nspb-noc { 367 compatible = "qcom,sc8280xp-nspb-noc"; 368 #interconnect-cells = <2>; 369 qcom,bcm-voters = <&apps_bcm_voter>; 370 }; 371 372 system_noc: interconnect-system-noc { 373 compatible = "qcom,sc8280xp-system-noc"; 374 #interconnect-cells = <2>; 375 qcom,bcm-voters = <&apps_bcm_voter>; 376 }; 377 378 memory@80000000 { 379 device_type = "memory"; 380 /* We expect the bootloader to fill in the size */ 381 reg = <0x0 0x80000000 0x0 0x0>; 382 }; 383 384 cpu0_opp_table: opp-table-cpu0 { 385 compatible = "operating-points-v2"; 386 opp-shared; 387 388 opp-300000000 { 389 opp-hz = /bits/ 64 <300000000>; 390 opp-peak-kBps = <(300000 * 32)>; 391 }; 392 opp-403200000 { 393 opp-hz = /bits/ 64 <403200000>; 394 opp-peak-kBps = <(384000 * 32)>; 395 }; 396 opp-499200000 { 397 opp-hz = /bits/ 64 <499200000>; 398 opp-peak-kBps = <(480000 * 32)>; 399 }; 400 opp-595200000 { 401 opp-hz = /bits/ 64 <595200000>; 402 opp-peak-kBps = <(576000 * 32)>; 403 }; 404 opp-691200000 { 405 opp-hz = /bits/ 64 <691200000>; 406 opp-peak-kBps = <(672000 * 32)>; 407 }; 408 opp-806400000 { 409 opp-hz = /bits/ 64 <806400000>; 410 opp-peak-kBps = <(768000 * 32)>; 411 }; 412 opp-902400000 { 413 opp-hz = /bits/ 64 <902400000>; 414 opp-peak-kBps = <(864000 * 32)>; 415 }; 416 opp-1017600000 { 417 opp-hz = /bits/ 64 <1017600000>; 418 opp-peak-kBps = <(960000 * 32)>; 419 }; 420 opp-1113600000 { 421 opp-hz = /bits/ 64 <1113600000>; 422 opp-peak-kBps = <(1075200 * 32)>; 423 }; 424 opp-1209600000 { 425 opp-hz = /bits/ 64 <1209600000>; 426 opp-peak-kBps = <(1171200 * 32)>; 427 }; 428 opp-1324800000 { 429 opp-hz = /bits/ 64 <1324800000>; 430 opp-peak-kBps = <(1267200 * 32)>; 431 }; 432 opp-1440000000 { 433 opp-hz = /bits/ 64 <1440000000>; 434 opp-peak-kBps = <(1363200 * 32)>; 435 }; 436 opp-1555200000 { 437 opp-hz = /bits/ 64 <1555200000>; 438 opp-peak-kBps = <(1536000 * 32)>; 439 }; 440 opp-1670400000 { 441 opp-hz = /bits/ 64 <1670400000>; 442 opp-peak-kBps = <(1612800 * 32)>; 443 }; 444 opp-1785600000 { 445 opp-hz = /bits/ 64 <1785600000>; 446 opp-peak-kBps = <(1689600 * 32)>; 447 }; 448 opp-1881600000 { 449 opp-hz = /bits/ 64 <1881600000>; 450 opp-peak-kBps = <(1689600 * 32)>; 451 }; 452 opp-1996800000 { 453 opp-hz = /bits/ 64 <1996800000>; 454 opp-peak-kBps = <(1689600 * 32)>; 455 }; 456 opp-2112000000 { 457 opp-hz = /bits/ 64 <2112000000>; 458 opp-peak-kBps = <(1689600 * 32)>; 459 }; 460 opp-2227200000 { 461 opp-hz = /bits/ 64 <2227200000>; 462 opp-peak-kBps = <(1689600 * 32)>; 463 }; 464 opp-2342400000 { 465 opp-hz = /bits/ 64 <2342400000>; 466 opp-peak-kBps = <(1689600 * 32)>; 467 }; 468 opp-2438400000 { 469 opp-hz = /bits/ 64 <2438400000>; 470 opp-peak-kBps = <(1689600 * 32)>; 471 }; 472 }; 473 474 cpu4_opp_table: opp-table-cpu4 { 475 compatible = "operating-points-v2"; 476 opp-shared; 477 478 opp-825600000 { 479 opp-hz = /bits/ 64 <825600000>; 480 opp-peak-kBps = <(768000 * 32)>; 481 }; 482 opp-940800000 { 483 opp-hz = /bits/ 64 <940800000>; 484 opp-peak-kBps = <(864000 * 32)>; 485 }; 486 opp-1056000000 { 487 opp-hz = /bits/ 64 <1056000000>; 488 opp-peak-kBps = <(960000 * 32)>; 489 }; 490 opp-1171200000 { 491 opp-hz = /bits/ 64 <1171200000>; 492 opp-peak-kBps = <(1171200 * 32)>; 493 }; 494 opp-1286400000 { 495 opp-hz = /bits/ 64 <1286400000>; 496 opp-peak-kBps = <(1267200 * 32)>; 497 }; 498 opp-1401600000 { 499 opp-hz = /bits/ 64 <1401600000>; 500 opp-peak-kBps = <(1363200 * 32)>; 501 }; 502 opp-1516800000 { 503 opp-hz = /bits/ 64 <1516800000>; 504 opp-peak-kBps = <(1459200 * 32)>; 505 }; 506 opp-1632000000 { 507 opp-hz = /bits/ 64 <1632000000>; 508 opp-peak-kBps = <(1612800 * 32)>; 509 }; 510 opp-1747200000 { 511 opp-hz = /bits/ 64 <1747200000>; 512 opp-peak-kBps = <(1689600 * 32)>; 513 }; 514 opp-1862400000 { 515 opp-hz = /bits/ 64 <1862400000>; 516 opp-peak-kBps = <(1689600 * 32)>; 517 }; 518 opp-1977600000 { 519 opp-hz = /bits/ 64 <1977600000>; 520 opp-peak-kBps = <(1689600 * 32)>; 521 }; 522 opp-2073600000 { 523 opp-hz = /bits/ 64 <2073600000>; 524 opp-peak-kBps = <(1689600 * 32)>; 525 }; 526 opp-2169600000 { 527 opp-hz = /bits/ 64 <2169600000>; 528 opp-peak-kBps = <(1689600 * 32)>; 529 }; 530 opp-2284800000 { 531 opp-hz = /bits/ 64 <2284800000>; 532 opp-peak-kBps = <(1689600 * 32)>; 533 }; 534 opp-2400000000 { 535 opp-hz = /bits/ 64 <2400000000>; 536 opp-peak-kBps = <(1689600 * 32)>; 537 }; 538 opp-2496000000 { 539 opp-hz = /bits/ 64 <2496000000>; 540 opp-peak-kBps = <(1689600 * 32)>; 541 }; 542 opp-2592000000 { 543 opp-hz = /bits/ 64 <2592000000>; 544 opp-peak-kBps = <(1689600 * 32)>; 545 }; 546 opp-2688000000 { 547 opp-hz = /bits/ 64 <2688000000>; 548 opp-peak-kBps = <(1689600 * 32)>; 549 }; 550 opp-2803200000 { 551 opp-hz = /bits/ 64 <2803200000>; 552 opp-peak-kBps = <(1689600 * 32)>; 553 }; 554 opp-2899200000 { 555 opp-hz = /bits/ 64 <2899200000>; 556 opp-peak-kBps = <(1689600 * 32)>; 557 }; 558 opp-2995200000 { 559 opp-hz = /bits/ 64 <2995200000>; 560 opp-peak-kBps = <(1689600 * 32)>; 561 }; 562 }; 563 564 qup_opp_table_100mhz: opp-table-qup100mhz { 565 compatible = "operating-points-v2"; 566 567 opp-75000000 { 568 opp-hz = /bits/ 64 <75000000>; 569 required-opps = <&rpmhpd_opp_low_svs>; 570 }; 571 572 opp-100000000 { 573 opp-hz = /bits/ 64 <100000000>; 574 required-opps = <&rpmhpd_opp_svs>; 575 }; 576 }; 577 578 pmu { 579 compatible = "arm,armv8-pmuv3"; 580 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 581 }; 582 583 psci { 584 compatible = "arm,psci-1.0"; 585 method = "smc"; 586 587 CPU_PD0: power-domain-cpu0 { 588 #power-domain-cells = <0>; 589 power-domains = <&CLUSTER_PD>; 590 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 591 }; 592 593 CPU_PD1: power-domain-cpu1 { 594 #power-domain-cells = <0>; 595 power-domains = <&CLUSTER_PD>; 596 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 597 }; 598 599 CPU_PD2: power-domain-cpu2 { 600 #power-domain-cells = <0>; 601 power-domains = <&CLUSTER_PD>; 602 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 603 }; 604 605 CPU_PD3: power-domain-cpu3 { 606 #power-domain-cells = <0>; 607 power-domains = <&CLUSTER_PD>; 608 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 609 }; 610 611 CPU_PD4: power-domain-cpu4 { 612 #power-domain-cells = <0>; 613 power-domains = <&CLUSTER_PD>; 614 domain-idle-states = <&BIG_CPU_SLEEP_0>; 615 }; 616 617 CPU_PD5: power-domain-cpu5 { 618 #power-domain-cells = <0>; 619 power-domains = <&CLUSTER_PD>; 620 domain-idle-states = <&BIG_CPU_SLEEP_0>; 621 }; 622 623 CPU_PD6: power-domain-cpu6 { 624 #power-domain-cells = <0>; 625 power-domains = <&CLUSTER_PD>; 626 domain-idle-states = <&BIG_CPU_SLEEP_0>; 627 }; 628 629 CPU_PD7: power-domain-cpu7 { 630 #power-domain-cells = <0>; 631 power-domains = <&CLUSTER_PD>; 632 domain-idle-states = <&BIG_CPU_SLEEP_0>; 633 }; 634 635 CLUSTER_PD: power-domain-cpu-cluster0 { 636 #power-domain-cells = <0>; 637 domain-idle-states = <&CLUSTER_SLEEP_0>; 638 }; 639 }; 640 641 reserved-memory { 642 #address-cells = <2>; 643 #size-cells = <2>; 644 ranges; 645 646 reserved-region@80000000 { 647 reg = <0 0x80000000 0 0x860000>; 648 no-map; 649 }; 650 651 cmd_db: cmd-db-region@80860000 { 652 compatible = "qcom,cmd-db"; 653 reg = <0 0x80860000 0 0x20000>; 654 no-map; 655 }; 656 657 reserved-region@80880000 { 658 reg = <0 0x80880000 0 0x80000>; 659 no-map; 660 }; 661 662 smem_mem: smem-region@80900000 { 663 compatible = "qcom,smem"; 664 reg = <0 0x80900000 0 0x200000>; 665 no-map; 666 hwlocks = <&tcsr_mutex 3>; 667 }; 668 669 reserved-region@80b00000 { 670 reg = <0 0x80b00000 0 0x100000>; 671 no-map; 672 }; 673 674 reserved-region@83b00000 { 675 reg = <0 0x83b00000 0 0x1700000>; 676 no-map; 677 }; 678 679 reserved-region@85b00000 { 680 reg = <0 0x85b00000 0 0xc00000>; 681 no-map; 682 }; 683 684 pil_adsp_mem: adsp-region@86c00000 { 685 reg = <0 0x86c00000 0 0x2000000>; 686 no-map; 687 }; 688 689 pil_nsp0_mem: cdsp0-region@8a100000 { 690 reg = <0 0x8a100000 0 0x1e00000>; 691 no-map; 692 }; 693 694 pil_nsp1_mem: cdsp1-region@8c600000 { 695 reg = <0 0x8c600000 0 0x1e00000>; 696 no-map; 697 }; 698 699 reserved-region@aeb00000 { 700 reg = <0 0xaeb00000 0 0x16600000>; 701 no-map; 702 }; 703 }; 704 705 smp2p-adsp { 706 compatible = "qcom,smp2p"; 707 qcom,smem = <443>, <429>; 708 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 709 IPCC_MPROC_SIGNAL_SMP2P 710 IRQ_TYPE_EDGE_RISING>; 711 mboxes = <&ipcc IPCC_CLIENT_LPASS 712 IPCC_MPROC_SIGNAL_SMP2P>; 713 714 qcom,local-pid = <0>; 715 qcom,remote-pid = <2>; 716 717 smp2p_adsp_out: master-kernel { 718 qcom,entry-name = "master-kernel"; 719 #qcom,smem-state-cells = <1>; 720 }; 721 722 smp2p_adsp_in: slave-kernel { 723 qcom,entry-name = "slave-kernel"; 724 interrupt-controller; 725 #interrupt-cells = <2>; 726 }; 727 }; 728 729 smp2p-nsp0 { 730 compatible = "qcom,smp2p"; 731 qcom,smem = <94>, <432>; 732 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 733 IPCC_MPROC_SIGNAL_SMP2P 734 IRQ_TYPE_EDGE_RISING>; 735 mboxes = <&ipcc IPCC_CLIENT_CDSP 736 IPCC_MPROC_SIGNAL_SMP2P>; 737 738 qcom,local-pid = <0>; 739 qcom,remote-pid = <5>; 740 741 smp2p_nsp0_out: master-kernel { 742 qcom,entry-name = "master-kernel"; 743 #qcom,smem-state-cells = <1>; 744 }; 745 746 smp2p_nsp0_in: slave-kernel { 747 qcom,entry-name = "slave-kernel"; 748 interrupt-controller; 749 #interrupt-cells = <2>; 750 }; 751 }; 752 753 smp2p-nsp1 { 754 compatible = "qcom,smp2p"; 755 qcom,smem = <617>, <616>; 756 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 757 IPCC_MPROC_SIGNAL_SMP2P 758 IRQ_TYPE_EDGE_RISING>; 759 mboxes = <&ipcc IPCC_CLIENT_NSP1 760 IPCC_MPROC_SIGNAL_SMP2P>; 761 762 qcom,local-pid = <0>; 763 qcom,remote-pid = <12>; 764 765 smp2p_nsp1_out: master-kernel { 766 qcom,entry-name = "master-kernel"; 767 #qcom,smem-state-cells = <1>; 768 }; 769 770 smp2p_nsp1_in: slave-kernel { 771 qcom,entry-name = "slave-kernel"; 772 interrupt-controller; 773 #interrupt-cells = <2>; 774 }; 775 }; 776 777 soc: soc@0 { 778 compatible = "simple-bus"; 779 #address-cells = <2>; 780 #size-cells = <2>; 781 ranges = <0 0 0 0 0x10 0>; 782 dma-ranges = <0 0 0 0 0x10 0>; 783 784 ethernet0: ethernet@20000 { 785 compatible = "qcom,sc8280xp-ethqos"; 786 reg = <0x0 0x00020000 0x0 0x10000>, 787 <0x0 0x00036000 0x0 0x100>; 788 reg-names = "stmmaceth", "rgmii"; 789 790 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 791 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 792 <&gcc GCC_EMAC0_PTP_CLK>, 793 <&gcc GCC_EMAC0_RGMII_CLK>; 794 clock-names = "stmmaceth", 795 "pclk", 796 "ptp_ref", 797 "rgmii"; 798 799 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 800 <GIC_SPI 936 IRQ_TYPE_LEVEL_HIGH>; 801 interrupt-names = "macirq", "eth_lpi"; 802 803 iommus = <&apps_smmu 0x4c0 0xf>; 804 power-domains = <&gcc EMAC_0_GDSC>; 805 806 snps,tso; 807 snps,pbl = <32>; 808 rx-fifo-depth = <4096>; 809 tx-fifo-depth = <4096>; 810 811 status = "disabled"; 812 }; 813 814 gcc: clock-controller@100000 { 815 compatible = "qcom,gcc-sc8280xp"; 816 reg = <0x0 0x00100000 0x0 0x1f0000>; 817 #clock-cells = <1>; 818 #reset-cells = <1>; 819 #power-domain-cells = <1>; 820 clocks = <&rpmhcc RPMH_CXO_CLK>, 821 <&sleep_clk>, 822 <0>, 823 <0>, 824 <0>, 825 <0>, 826 <0>, 827 <0>, 828 <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 829 <0>, 830 <0>, 831 <0>, 832 <0>, 833 <0>, 834 <0>, 835 <0>, 836 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 837 <0>, 838 <0>, 839 <0>, 840 <0>, 841 <0>, 842 <0>, 843 <0>, 844 <0>, 845 <0>, 846 <&pcie2a_phy>, 847 <&pcie2b_phy>, 848 <&pcie3a_phy>, 849 <&pcie3b_phy>, 850 <&pcie4_phy>, 851 <0>, 852 <0>; 853 power-domains = <&rpmhpd SC8280XP_CX>; 854 }; 855 856 ipcc: mailbox@408000 { 857 compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc"; 858 reg = <0 0x00408000 0 0x1000>; 859 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 860 interrupt-controller; 861 #interrupt-cells = <3>; 862 #mbox-cells = <2>; 863 }; 864 865 qup2: geniqup@8c0000 { 866 compatible = "qcom,geni-se-qup"; 867 reg = <0 0x008c0000 0 0x2000>; 868 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 869 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 870 clock-names = "m-ahb", "s-ahb"; 871 iommus = <&apps_smmu 0xa3 0>; 872 873 #address-cells = <2>; 874 #size-cells = <2>; 875 ranges; 876 877 status = "disabled"; 878 879 i2c16: i2c@880000 { 880 compatible = "qcom,geni-i2c"; 881 reg = <0 0x00880000 0 0x4000>; 882 #address-cells = <1>; 883 #size-cells = <0>; 884 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 885 clock-names = "se"; 886 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 887 power-domains = <&rpmhpd SC8280XP_CX>; 888 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 889 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 890 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 891 interconnect-names = "qup-core", "qup-config", "qup-memory"; 892 status = "disabled"; 893 }; 894 895 spi16: spi@880000 { 896 compatible = "qcom,geni-spi"; 897 reg = <0 0x00880000 0 0x4000>; 898 #address-cells = <1>; 899 #size-cells = <0>; 900 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 901 clock-names = "se"; 902 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 903 power-domains = <&rpmhpd SC8280XP_CX>; 904 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 905 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 906 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 907 interconnect-names = "qup-core", "qup-config", "qup-memory"; 908 status = "disabled"; 909 }; 910 911 i2c17: i2c@884000 { 912 compatible = "qcom,geni-i2c"; 913 reg = <0 0x00884000 0 0x4000>; 914 #address-cells = <1>; 915 #size-cells = <0>; 916 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 917 clock-names = "se"; 918 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 919 power-domains = <&rpmhpd SC8280XP_CX>; 920 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 921 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 922 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 923 interconnect-names = "qup-core", "qup-config", "qup-memory"; 924 status = "disabled"; 925 }; 926 927 spi17: spi@884000 { 928 compatible = "qcom,geni-spi"; 929 reg = <0 0x00884000 0 0x4000>; 930 #address-cells = <1>; 931 #size-cells = <0>; 932 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 933 clock-names = "se"; 934 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 935 power-domains = <&rpmhpd SC8280XP_CX>; 936 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 937 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 938 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 939 interconnect-names = "qup-core", "qup-config", "qup-memory"; 940 status = "disabled"; 941 }; 942 943 uart17: serial@884000 { 944 compatible = "qcom,geni-uart"; 945 reg = <0 0x00884000 0 0x4000>; 946 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 947 clock-names = "se"; 948 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 949 operating-points-v2 = <&qup_opp_table_100mhz>; 950 power-domains = <&rpmhpd SC8280XP_CX>; 951 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 952 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; 953 interconnect-names = "qup-core", "qup-config"; 954 status = "disabled"; 955 }; 956 957 i2c18: i2c@888000 { 958 compatible = "qcom,geni-i2c"; 959 reg = <0 0x00888000 0 0x4000>; 960 #address-cells = <1>; 961 #size-cells = <0>; 962 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 963 clock-names = "se"; 964 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 965 power-domains = <&rpmhpd SC8280XP_CX>; 966 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 967 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 968 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 969 interconnect-names = "qup-core", "qup-config", "qup-memory"; 970 status = "disabled"; 971 }; 972 973 spi18: spi@888000 { 974 compatible = "qcom,geni-spi"; 975 reg = <0 0x00888000 0 0x4000>; 976 #address-cells = <1>; 977 #size-cells = <0>; 978 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 979 clock-names = "se"; 980 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 981 power-domains = <&rpmhpd SC8280XP_CX>; 982 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 983 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 984 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 985 interconnect-names = "qup-core", "qup-config", "qup-memory"; 986 status = "disabled"; 987 }; 988 989 i2c19: i2c@88c000 { 990 compatible = "qcom,geni-i2c"; 991 reg = <0 0x0088c000 0 0x4000>; 992 #address-cells = <1>; 993 #size-cells = <0>; 994 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 995 clock-names = "se"; 996 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 997 power-domains = <&rpmhpd SC8280XP_CX>; 998 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 999 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1000 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1001 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1002 status = "disabled"; 1003 }; 1004 1005 spi19: spi@88c000 { 1006 compatible = "qcom,geni-spi"; 1007 reg = <0 0x0088c000 0 0x4000>; 1008 #address-cells = <1>; 1009 #size-cells = <0>; 1010 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1011 clock-names = "se"; 1012 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1013 power-domains = <&rpmhpd SC8280XP_CX>; 1014 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1015 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1016 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1017 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1018 status = "disabled"; 1019 }; 1020 1021 i2c20: i2c@890000 { 1022 compatible = "qcom,geni-i2c"; 1023 reg = <0 0x00890000 0 0x4000>; 1024 #address-cells = <1>; 1025 #size-cells = <0>; 1026 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1027 clock-names = "se"; 1028 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1029 power-domains = <&rpmhpd SC8280XP_CX>; 1030 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1031 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1032 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1033 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1034 status = "disabled"; 1035 }; 1036 1037 spi20: spi@890000 { 1038 compatible = "qcom,geni-spi"; 1039 reg = <0 0x00890000 0 0x4000>; 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1043 clock-names = "se"; 1044 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1045 power-domains = <&rpmhpd SC8280XP_CX>; 1046 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1047 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1048 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1049 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1050 status = "disabled"; 1051 }; 1052 1053 i2c21: i2c@894000 { 1054 compatible = "qcom,geni-i2c"; 1055 reg = <0 0x00894000 0 0x4000>; 1056 clock-names = "se"; 1057 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1058 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1059 #address-cells = <1>; 1060 #size-cells = <0>; 1061 power-domains = <&rpmhpd SC8280XP_CX>; 1062 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1063 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1064 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1065 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1066 status = "disabled"; 1067 }; 1068 1069 spi21: spi@894000 { 1070 compatible = "qcom,geni-spi"; 1071 reg = <0 0x00894000 0 0x4000>; 1072 #address-cells = <1>; 1073 #size-cells = <0>; 1074 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1075 clock-names = "se"; 1076 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1077 power-domains = <&rpmhpd SC8280XP_CX>; 1078 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1079 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1080 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1081 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1082 status = "disabled"; 1083 }; 1084 1085 i2c22: i2c@898000 { 1086 compatible = "qcom,geni-i2c"; 1087 reg = <0 0x00898000 0 0x4000>; 1088 #address-cells = <1>; 1089 #size-cells = <0>; 1090 clock-names = "se"; 1091 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1092 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1093 power-domains = <&rpmhpd SC8280XP_CX>; 1094 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1095 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1096 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1097 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1098 status = "disabled"; 1099 }; 1100 1101 spi22: spi@898000 { 1102 compatible = "qcom,geni-spi"; 1103 reg = <0 0x00898000 0 0x4000>; 1104 #address-cells = <1>; 1105 #size-cells = <0>; 1106 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1107 clock-names = "se"; 1108 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1109 power-domains = <&rpmhpd SC8280XP_CX>; 1110 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1111 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1112 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1113 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1114 status = "disabled"; 1115 }; 1116 1117 i2c23: i2c@89c000 { 1118 compatible = "qcom,geni-i2c"; 1119 reg = <0 0x0089c000 0 0x4000>; 1120 #address-cells = <1>; 1121 #size-cells = <0>; 1122 clock-names = "se"; 1123 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1124 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1125 power-domains = <&rpmhpd SC8280XP_CX>; 1126 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1127 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1128 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1129 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1130 status = "disabled"; 1131 }; 1132 1133 spi23: spi@89c000 { 1134 compatible = "qcom,geni-spi"; 1135 reg = <0 0x0089c000 0 0x4000>; 1136 #address-cells = <1>; 1137 #size-cells = <0>; 1138 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1139 clock-names = "se"; 1140 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1141 power-domains = <&rpmhpd SC8280XP_CX>; 1142 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1143 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1144 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1145 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1146 status = "disabled"; 1147 }; 1148 }; 1149 1150 qup0: geniqup@9c0000 { 1151 compatible = "qcom,geni-se-qup"; 1152 reg = <0 0x009c0000 0 0x6000>; 1153 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1154 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1155 clock-names = "m-ahb", "s-ahb"; 1156 iommus = <&apps_smmu 0x563 0>; 1157 1158 #address-cells = <2>; 1159 #size-cells = <2>; 1160 ranges; 1161 1162 status = "disabled"; 1163 1164 i2c0: i2c@980000 { 1165 compatible = "qcom,geni-i2c"; 1166 reg = <0 0x00980000 0 0x4000>; 1167 #address-cells = <1>; 1168 #size-cells = <0>; 1169 clock-names = "se"; 1170 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1171 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1172 power-domains = <&rpmhpd SC8280XP_CX>; 1173 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1174 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1175 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1176 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1177 status = "disabled"; 1178 }; 1179 1180 spi0: spi@980000 { 1181 compatible = "qcom,geni-spi"; 1182 reg = <0 0x00980000 0 0x4000>; 1183 #address-cells = <1>; 1184 #size-cells = <0>; 1185 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1186 clock-names = "se"; 1187 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1188 power-domains = <&rpmhpd SC8280XP_CX>; 1189 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1190 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1191 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1192 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1193 status = "disabled"; 1194 }; 1195 1196 i2c1: i2c@984000 { 1197 compatible = "qcom,geni-i2c"; 1198 reg = <0 0x00984000 0 0x4000>; 1199 #address-cells = <1>; 1200 #size-cells = <0>; 1201 clock-names = "se"; 1202 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1203 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1204 power-domains = <&rpmhpd SC8280XP_CX>; 1205 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1206 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1207 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1208 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1209 status = "disabled"; 1210 }; 1211 1212 spi1: spi@984000 { 1213 compatible = "qcom,geni-spi"; 1214 reg = <0 0x00984000 0 0x4000>; 1215 #address-cells = <1>; 1216 #size-cells = <0>; 1217 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1218 clock-names = "se"; 1219 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1220 power-domains = <&rpmhpd SC8280XP_CX>; 1221 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1222 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1223 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1224 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1225 status = "disabled"; 1226 }; 1227 1228 i2c2: i2c@988000 { 1229 compatible = "qcom,geni-i2c"; 1230 reg = <0 0x00988000 0 0x4000>; 1231 #address-cells = <1>; 1232 #size-cells = <0>; 1233 clock-names = "se"; 1234 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1235 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1236 power-domains = <&rpmhpd SC8280XP_CX>; 1237 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1238 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1239 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1240 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1241 status = "disabled"; 1242 }; 1243 1244 spi2: spi@988000 { 1245 compatible = "qcom,geni-spi"; 1246 reg = <0 0x00988000 0 0x4000>; 1247 #address-cells = <1>; 1248 #size-cells = <0>; 1249 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1250 clock-names = "se"; 1251 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1252 power-domains = <&rpmhpd SC8280XP_CX>; 1253 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1254 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1255 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1256 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1257 status = "disabled"; 1258 }; 1259 1260 uart2: serial@988000 { 1261 compatible = "qcom,geni-uart"; 1262 reg = <0 0x00988000 0 0x4000>; 1263 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1264 clock-names = "se"; 1265 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1266 operating-points-v2 = <&qup_opp_table_100mhz>; 1267 power-domains = <&rpmhpd SC8280XP_CX>; 1268 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1269 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1270 interconnect-names = "qup-core", "qup-config"; 1271 status = "disabled"; 1272 }; 1273 1274 i2c3: i2c@98c000 { 1275 compatible = "qcom,geni-i2c"; 1276 reg = <0 0x0098c000 0 0x4000>; 1277 #address-cells = <1>; 1278 #size-cells = <0>; 1279 clock-names = "se"; 1280 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1281 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1282 power-domains = <&rpmhpd SC8280XP_CX>; 1283 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1284 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1285 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1286 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1287 status = "disabled"; 1288 }; 1289 1290 spi3: spi@98c000 { 1291 compatible = "qcom,geni-spi"; 1292 reg = <0 0x0098c000 0 0x4000>; 1293 #address-cells = <1>; 1294 #size-cells = <0>; 1295 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1296 clock-names = "se"; 1297 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1298 power-domains = <&rpmhpd SC8280XP_CX>; 1299 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1300 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1301 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1302 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1303 status = "disabled"; 1304 }; 1305 1306 i2c4: i2c@990000 { 1307 compatible = "qcom,geni-i2c"; 1308 reg = <0 0x00990000 0 0x4000>; 1309 clock-names = "se"; 1310 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1311 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1312 #address-cells = <1>; 1313 #size-cells = <0>; 1314 power-domains = <&rpmhpd SC8280XP_CX>; 1315 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1316 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1317 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1318 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1319 status = "disabled"; 1320 }; 1321 1322 spi4: spi@990000 { 1323 compatible = "qcom,geni-spi"; 1324 reg = <0 0x00990000 0 0x4000>; 1325 #address-cells = <1>; 1326 #size-cells = <0>; 1327 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1328 clock-names = "se"; 1329 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1330 power-domains = <&rpmhpd SC8280XP_CX>; 1331 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1332 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1333 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1334 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1335 status = "disabled"; 1336 }; 1337 1338 i2c5: i2c@994000 { 1339 compatible = "qcom,geni-i2c"; 1340 reg = <0 0x00994000 0 0x4000>; 1341 #address-cells = <1>; 1342 #size-cells = <0>; 1343 clock-names = "se"; 1344 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1345 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1346 power-domains = <&rpmhpd SC8280XP_CX>; 1347 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1348 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1349 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1350 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1351 status = "disabled"; 1352 }; 1353 1354 spi5: spi@994000 { 1355 compatible = "qcom,geni-spi"; 1356 reg = <0 0x00994000 0 0x4000>; 1357 #address-cells = <1>; 1358 #size-cells = <0>; 1359 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1360 clock-names = "se"; 1361 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1362 power-domains = <&rpmhpd SC8280XP_CX>; 1363 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1364 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1365 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1366 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1367 status = "disabled"; 1368 }; 1369 1370 i2c6: i2c@998000 { 1371 compatible = "qcom,geni-i2c"; 1372 reg = <0 0x00998000 0 0x4000>; 1373 #address-cells = <1>; 1374 #size-cells = <0>; 1375 clock-names = "se"; 1376 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1377 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1378 power-domains = <&rpmhpd SC8280XP_CX>; 1379 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1380 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1381 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1382 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1383 status = "disabled"; 1384 }; 1385 1386 spi6: spi@998000 { 1387 compatible = "qcom,geni-spi"; 1388 reg = <0 0x00998000 0 0x4000>; 1389 #address-cells = <1>; 1390 #size-cells = <0>; 1391 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1392 clock-names = "se"; 1393 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1394 power-domains = <&rpmhpd SC8280XP_CX>; 1395 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1396 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1397 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1398 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1399 status = "disabled"; 1400 }; 1401 1402 i2c7: i2c@99c000 { 1403 compatible = "qcom,geni-i2c"; 1404 reg = <0 0x0099c000 0 0x4000>; 1405 #address-cells = <1>; 1406 #size-cells = <0>; 1407 clock-names = "se"; 1408 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1409 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1410 power-domains = <&rpmhpd SC8280XP_CX>; 1411 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1412 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1413 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1414 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1415 status = "disabled"; 1416 }; 1417 1418 spi7: spi@99c000 { 1419 compatible = "qcom,geni-spi"; 1420 reg = <0 0x0099c000 0 0x4000>; 1421 #address-cells = <1>; 1422 #size-cells = <0>; 1423 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1424 clock-names = "se"; 1425 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1426 power-domains = <&rpmhpd SC8280XP_CX>; 1427 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1428 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1429 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1430 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1431 status = "disabled"; 1432 }; 1433 }; 1434 1435 qup1: geniqup@ac0000 { 1436 compatible = "qcom,geni-se-qup"; 1437 reg = <0 0x00ac0000 0 0x6000>; 1438 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1439 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1440 clock-names = "m-ahb", "s-ahb"; 1441 iommus = <&apps_smmu 0x83 0>; 1442 1443 #address-cells = <2>; 1444 #size-cells = <2>; 1445 ranges; 1446 1447 status = "disabled"; 1448 1449 i2c8: i2c@a80000 { 1450 compatible = "qcom,geni-i2c"; 1451 reg = <0 0x00a80000 0 0x4000>; 1452 #address-cells = <1>; 1453 #size-cells = <0>; 1454 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1455 clock-names = "se"; 1456 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1457 power-domains = <&rpmhpd SC8280XP_CX>; 1458 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1459 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1460 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1461 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1462 status = "disabled"; 1463 }; 1464 1465 spi8: spi@a80000 { 1466 compatible = "qcom,geni-spi"; 1467 reg = <0 0x00a80000 0 0x4000>; 1468 #address-cells = <1>; 1469 #size-cells = <0>; 1470 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1471 clock-names = "se"; 1472 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1473 power-domains = <&rpmhpd SC8280XP_CX>; 1474 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1475 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1476 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1477 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1478 status = "disabled"; 1479 }; 1480 1481 i2c9: i2c@a84000 { 1482 compatible = "qcom,geni-i2c"; 1483 reg = <0 0x00a84000 0 0x4000>; 1484 #address-cells = <1>; 1485 #size-cells = <0>; 1486 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1487 clock-names = "se"; 1488 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1489 power-domains = <&rpmhpd SC8280XP_CX>; 1490 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1491 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1492 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1493 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1494 status = "disabled"; 1495 }; 1496 1497 spi9: spi@a84000 { 1498 compatible = "qcom,geni-spi"; 1499 reg = <0 0x00a84000 0 0x4000>; 1500 #address-cells = <1>; 1501 #size-cells = <0>; 1502 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1503 clock-names = "se"; 1504 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1505 power-domains = <&rpmhpd SC8280XP_CX>; 1506 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1507 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1508 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1509 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1510 status = "disabled"; 1511 }; 1512 1513 i2c10: i2c@a88000 { 1514 compatible = "qcom,geni-i2c"; 1515 reg = <0 0x00a88000 0 0x4000>; 1516 #address-cells = <1>; 1517 #size-cells = <0>; 1518 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1519 clock-names = "se"; 1520 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1521 power-domains = <&rpmhpd SC8280XP_CX>; 1522 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1523 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1524 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1525 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1526 status = "disabled"; 1527 }; 1528 1529 spi10: spi@a88000 { 1530 compatible = "qcom,geni-spi"; 1531 reg = <0 0x00a88000 0 0x4000>; 1532 #address-cells = <1>; 1533 #size-cells = <0>; 1534 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1535 clock-names = "se"; 1536 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1537 power-domains = <&rpmhpd SC8280XP_CX>; 1538 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1539 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1540 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1541 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1542 status = "disabled"; 1543 }; 1544 1545 i2c11: i2c@a8c000 { 1546 compatible = "qcom,geni-i2c"; 1547 reg = <0 0x00a8c000 0 0x4000>; 1548 #address-cells = <1>; 1549 #size-cells = <0>; 1550 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1551 clock-names = "se"; 1552 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1553 power-domains = <&rpmhpd SC8280XP_CX>; 1554 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1555 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1556 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1557 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1558 status = "disabled"; 1559 }; 1560 1561 spi11: spi@a8c000 { 1562 compatible = "qcom,geni-spi"; 1563 reg = <0 0x00a8c000 0 0x4000>; 1564 #address-cells = <1>; 1565 #size-cells = <0>; 1566 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1567 clock-names = "se"; 1568 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1569 power-domains = <&rpmhpd SC8280XP_CX>; 1570 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1571 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1572 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1573 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1574 status = "disabled"; 1575 }; 1576 1577 i2c12: i2c@a90000 { 1578 compatible = "qcom,geni-i2c"; 1579 reg = <0 0x00a90000 0 0x4000>; 1580 #address-cells = <1>; 1581 #size-cells = <0>; 1582 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1583 clock-names = "se"; 1584 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1585 power-domains = <&rpmhpd SC8280XP_CX>; 1586 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1587 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1588 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1589 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1590 status = "disabled"; 1591 }; 1592 1593 spi12: spi@a90000 { 1594 compatible = "qcom,geni-spi"; 1595 reg = <0 0x00a90000 0 0x4000>; 1596 #address-cells = <1>; 1597 #size-cells = <0>; 1598 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1599 clock-names = "se"; 1600 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1601 power-domains = <&rpmhpd SC8280XP_CX>; 1602 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1603 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1604 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1605 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1606 status = "disabled"; 1607 }; 1608 1609 i2c13: i2c@a94000 { 1610 compatible = "qcom,geni-i2c"; 1611 reg = <0 0x00a94000 0 0x4000>; 1612 #address-cells = <1>; 1613 #size-cells = <0>; 1614 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1615 clock-names = "se"; 1616 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1617 power-domains = <&rpmhpd SC8280XP_CX>; 1618 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1619 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1620 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1621 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1622 status = "disabled"; 1623 }; 1624 1625 spi13: spi@a94000 { 1626 compatible = "qcom,geni-spi"; 1627 reg = <0 0x00a94000 0 0x4000>; 1628 #address-cells = <1>; 1629 #size-cells = <0>; 1630 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1631 clock-names = "se"; 1632 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1633 power-domains = <&rpmhpd SC8280XP_CX>; 1634 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1635 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1636 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1637 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1638 status = "disabled"; 1639 }; 1640 1641 i2c14: i2c@a98000 { 1642 compatible = "qcom,geni-i2c"; 1643 reg = <0 0x00a98000 0 0x4000>; 1644 #address-cells = <1>; 1645 #size-cells = <0>; 1646 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1647 clock-names = "se"; 1648 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1649 power-domains = <&rpmhpd SC8280XP_CX>; 1650 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1651 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1652 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1653 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1654 status = "disabled"; 1655 }; 1656 1657 spi14: spi@a98000 { 1658 compatible = "qcom,geni-spi"; 1659 reg = <0 0x00a98000 0 0x4000>; 1660 #address-cells = <1>; 1661 #size-cells = <0>; 1662 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1663 clock-names = "se"; 1664 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1665 power-domains = <&rpmhpd SC8280XP_CX>; 1666 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1667 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1668 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1669 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1670 status = "disabled"; 1671 }; 1672 1673 i2c15: i2c@a9c000 { 1674 compatible = "qcom,geni-i2c"; 1675 reg = <0 0x00a9c000 0 0x4000>; 1676 #address-cells = <1>; 1677 #size-cells = <0>; 1678 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1679 clock-names = "se"; 1680 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 1681 power-domains = <&rpmhpd SC8280XP_CX>; 1682 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1683 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1684 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1685 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1686 status = "disabled"; 1687 }; 1688 1689 spi15: spi@a9c000 { 1690 compatible = "qcom,geni-spi"; 1691 reg = <0 0x00a9c000 0 0x4000>; 1692 #address-cells = <1>; 1693 #size-cells = <0>; 1694 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1695 clock-names = "se"; 1696 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 1697 power-domains = <&rpmhpd SC8280XP_CX>; 1698 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1699 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1700 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1701 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1702 status = "disabled"; 1703 }; 1704 }; 1705 1706 rng: rng@10d3000 { 1707 compatible = "qcom,prng-ee"; 1708 reg = <0 0x010d3000 0 0x1000>; 1709 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1710 clock-names = "core"; 1711 }; 1712 1713 pcie4: pcie@1c00000 { 1714 device_type = "pci"; 1715 compatible = "qcom,pcie-sc8280xp"; 1716 reg = <0x0 0x01c00000 0x0 0x3000>, 1717 <0x0 0x30000000 0x0 0xf1d>, 1718 <0x0 0x30000f20 0x0 0xa8>, 1719 <0x0 0x30001000 0x0 0x1000>, 1720 <0x0 0x30100000 0x0 0x100000>, 1721 <0x0 0x01c03000 0x0 0x1000>; 1722 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1723 #address-cells = <3>; 1724 #size-cells = <2>; 1725 ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>, 1726 <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>; 1727 bus-range = <0x00 0xff>; 1728 1729 dma-coherent; 1730 1731 linux,pci-domain = <6>; 1732 num-lanes = <1>; 1733 1734 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1737 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 1738 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1739 1740 #interrupt-cells = <1>; 1741 interrupt-map-mask = <0 0 0 0x7>; 1742 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1743 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1744 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1745 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1746 1747 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 1748 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 1749 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 1750 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 1751 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 1752 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1753 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1754 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>, 1755 <&gcc GCC_CNOC_PCIE4_QX_CLK>; 1756 clock-names = "aux", 1757 "cfg", 1758 "bus_master", 1759 "bus_slave", 1760 "slave_q2a", 1761 "ddrss_sf_tbu", 1762 "noc_aggr_4", 1763 "noc_aggr_south_sf", 1764 "cnoc_qx"; 1765 1766 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 1767 assigned-clock-rates = <19200000>; 1768 1769 interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>, 1770 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>; 1771 interconnect-names = "pcie-mem", "cpu-pcie"; 1772 1773 resets = <&gcc GCC_PCIE_4_BCR>; 1774 reset-names = "pci"; 1775 1776 power-domains = <&gcc PCIE_4_GDSC>; 1777 required-opps = <&rpmhpd_opp_nom>; 1778 1779 phys = <&pcie4_phy>; 1780 phy-names = "pciephy"; 1781 1782 status = "disabled"; 1783 }; 1784 1785 pcie4_phy: phy@1c06000 { 1786 compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy"; 1787 reg = <0x0 0x01c06000 0x0 0x2000>; 1788 1789 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 1790 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 1791 <&gcc GCC_PCIE_4_CLKREF_CLK>, 1792 <&gcc GCC_PCIE4_PHY_RCHNG_CLK>, 1793 <&gcc GCC_PCIE_4_PIPE_CLK>, 1794 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; 1795 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1796 "pipe", "pipediv2"; 1797 1798 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>; 1799 assigned-clock-rates = <100000000>; 1800 1801 power-domains = <&gcc PCIE_4_GDSC>; 1802 1803 resets = <&gcc GCC_PCIE_4_PHY_BCR>; 1804 reset-names = "phy"; 1805 1806 #clock-cells = <0>; 1807 clock-output-names = "pcie_4_pipe_clk"; 1808 1809 #phy-cells = <0>; 1810 1811 status = "disabled"; 1812 }; 1813 1814 pcie3b: pcie@1c08000 { 1815 device_type = "pci"; 1816 compatible = "qcom,pcie-sc8280xp"; 1817 reg = <0x0 0x01c08000 0x0 0x3000>, 1818 <0x0 0x32000000 0x0 0xf1d>, 1819 <0x0 0x32000f20 0x0 0xa8>, 1820 <0x0 0x32001000 0x0 0x1000>, 1821 <0x0 0x32100000 0x0 0x100000>, 1822 <0x0 0x01c0b000 0x0 0x1000>; 1823 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1824 #address-cells = <3>; 1825 #size-cells = <2>; 1826 ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>, 1827 <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>; 1828 bus-range = <0x00 0xff>; 1829 1830 dma-coherent; 1831 1832 linux,pci-domain = <5>; 1833 num-lanes = <2>; 1834 1835 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1836 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1839 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1840 1841 #interrupt-cells = <1>; 1842 interrupt-map-mask = <0 0 0 0x7>; 1843 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, 1844 <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 1845 <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>, 1846 <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1847 1848 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 1849 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 1850 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, 1851 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, 1852 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, 1853 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1854 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1855 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 1856 clock-names = "aux", 1857 "cfg", 1858 "bus_master", 1859 "bus_slave", 1860 "slave_q2a", 1861 "ddrss_sf_tbu", 1862 "noc_aggr_4", 1863 "noc_aggr_south_sf"; 1864 1865 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>; 1866 assigned-clock-rates = <19200000>; 1867 1868 interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>, 1869 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>; 1870 interconnect-names = "pcie-mem", "cpu-pcie"; 1871 1872 resets = <&gcc GCC_PCIE_3B_BCR>; 1873 reset-names = "pci"; 1874 1875 power-domains = <&gcc PCIE_3B_GDSC>; 1876 required-opps = <&rpmhpd_opp_nom>; 1877 1878 phys = <&pcie3b_phy>; 1879 phy-names = "pciephy"; 1880 1881 status = "disabled"; 1882 }; 1883 1884 pcie3b_phy: phy@1c0e000 { 1885 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 1886 reg = <0x0 0x01c0e000 0x0 0x2000>; 1887 1888 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 1889 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 1890 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 1891 <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>, 1892 <&gcc GCC_PCIE_3B_PIPE_CLK>, 1893 <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>; 1894 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1895 "pipe", "pipediv2"; 1896 1897 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>; 1898 assigned-clock-rates = <100000000>; 1899 1900 power-domains = <&gcc PCIE_3B_GDSC>; 1901 1902 resets = <&gcc GCC_PCIE_3B_PHY_BCR>; 1903 reset-names = "phy"; 1904 1905 #clock-cells = <0>; 1906 clock-output-names = "pcie_3b_pipe_clk"; 1907 1908 #phy-cells = <0>; 1909 1910 status = "disabled"; 1911 }; 1912 1913 pcie3a: pcie@1c10000 { 1914 device_type = "pci"; 1915 compatible = "qcom,pcie-sc8280xp"; 1916 reg = <0x0 0x01c10000 0x0 0x3000>, 1917 <0x0 0x34000000 0x0 0xf1d>, 1918 <0x0 0x34000f20 0x0 0xa8>, 1919 <0x0 0x34001000 0x0 0x1000>, 1920 <0x0 0x34100000 0x0 0x100000>, 1921 <0x0 0x01c13000 0x0 0x1000>; 1922 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1923 #address-cells = <3>; 1924 #size-cells = <2>; 1925 ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>, 1926 <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>; 1927 bus-range = <0x00 0xff>; 1928 1929 dma-coherent; 1930 1931 linux,pci-domain = <4>; 1932 num-lanes = <4>; 1933 1934 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1935 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1936 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1937 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1938 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1939 1940 #interrupt-cells = <1>; 1941 interrupt-map-mask = <0 0 0 0x7>; 1942 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 1943 <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>, 1944 <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, 1945 <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>; 1946 1947 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 1948 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 1949 <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>, 1950 <&gcc GCC_PCIE_3A_SLV_AXI_CLK>, 1951 <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>, 1952 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1953 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1954 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 1955 clock-names = "aux", 1956 "cfg", 1957 "bus_master", 1958 "bus_slave", 1959 "slave_q2a", 1960 "ddrss_sf_tbu", 1961 "noc_aggr_4", 1962 "noc_aggr_south_sf"; 1963 1964 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>; 1965 assigned-clock-rates = <19200000>; 1966 1967 interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>, 1968 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>; 1969 interconnect-names = "pcie-mem", "cpu-pcie"; 1970 1971 resets = <&gcc GCC_PCIE_3A_BCR>; 1972 reset-names = "pci"; 1973 1974 power-domains = <&gcc PCIE_3A_GDSC>; 1975 required-opps = <&rpmhpd_opp_nom>; 1976 1977 phys = <&pcie3a_phy>; 1978 phy-names = "pciephy"; 1979 1980 status = "disabled"; 1981 }; 1982 1983 pcie3a_phy: phy@1c14000 { 1984 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 1985 reg = <0x0 0x01c14000 0x0 0x2000>, 1986 <0x0 0x01c16000 0x0 0x2000>; 1987 1988 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 1989 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 1990 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 1991 <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>, 1992 <&gcc GCC_PCIE_3A_PIPE_CLK>, 1993 <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>; 1994 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1995 "pipe", "pipediv2"; 1996 1997 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>; 1998 assigned-clock-rates = <100000000>; 1999 2000 power-domains = <&gcc PCIE_3A_GDSC>; 2001 2002 resets = <&gcc GCC_PCIE_3A_PHY_BCR>; 2003 reset-names = "phy"; 2004 2005 qcom,4ln-config-sel = <&tcsr 0xa044 1>; 2006 2007 #clock-cells = <0>; 2008 clock-output-names = "pcie_3a_pipe_clk"; 2009 2010 #phy-cells = <0>; 2011 2012 status = "disabled"; 2013 }; 2014 2015 pcie2b: pcie@1c18000 { 2016 device_type = "pci"; 2017 compatible = "qcom,pcie-sc8280xp"; 2018 reg = <0x0 0x01c18000 0x0 0x3000>, 2019 <0x0 0x38000000 0x0 0xf1d>, 2020 <0x0 0x38000f20 0x0 0xa8>, 2021 <0x0 0x38001000 0x0 0x1000>, 2022 <0x0 0x38100000 0x0 0x100000>, 2023 <0x0 0x01c1b000 0x0 0x1000>; 2024 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2025 #address-cells = <3>; 2026 #size-cells = <2>; 2027 ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>, 2028 <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>; 2029 bus-range = <0x00 0xff>; 2030 2031 dma-coherent; 2032 2033 linux,pci-domain = <3>; 2034 num-lanes = <2>; 2035 2036 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 2037 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2038 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2039 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 2040 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2041 2042 #interrupt-cells = <1>; 2043 interrupt-map-mask = <0 0 0 0x7>; 2044 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2045 <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 2046 <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 2047 <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; 2048 2049 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2050 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2051 <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>, 2052 <&gcc GCC_PCIE_2B_SLV_AXI_CLK>, 2053 <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>, 2054 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2055 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2056 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2057 clock-names = "aux", 2058 "cfg", 2059 "bus_master", 2060 "bus_slave", 2061 "slave_q2a", 2062 "ddrss_sf_tbu", 2063 "noc_aggr_4", 2064 "noc_aggr_south_sf"; 2065 2066 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>; 2067 assigned-clock-rates = <19200000>; 2068 2069 interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>, 2070 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>; 2071 interconnect-names = "pcie-mem", "cpu-pcie"; 2072 2073 resets = <&gcc GCC_PCIE_2B_BCR>; 2074 reset-names = "pci"; 2075 2076 power-domains = <&gcc PCIE_2B_GDSC>; 2077 required-opps = <&rpmhpd_opp_nom>; 2078 2079 phys = <&pcie2b_phy>; 2080 phy-names = "pciephy"; 2081 2082 status = "disabled"; 2083 }; 2084 2085 pcie2b_phy: phy@1c1e000 { 2086 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 2087 reg = <0x0 0x01c1e000 0x0 0x2000>; 2088 2089 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2090 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2091 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2092 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>, 2093 <&gcc GCC_PCIE_2B_PIPE_CLK>, 2094 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>; 2095 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2096 "pipe", "pipediv2"; 2097 2098 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>; 2099 assigned-clock-rates = <100000000>; 2100 2101 power-domains = <&gcc PCIE_2B_GDSC>; 2102 2103 resets = <&gcc GCC_PCIE_2B_PHY_BCR>; 2104 reset-names = "phy"; 2105 2106 #clock-cells = <0>; 2107 clock-output-names = "pcie_2b_pipe_clk"; 2108 2109 #phy-cells = <0>; 2110 2111 status = "disabled"; 2112 }; 2113 2114 pcie2a: pcie@1c20000 { 2115 device_type = "pci"; 2116 compatible = "qcom,pcie-sc8280xp"; 2117 reg = <0x0 0x01c20000 0x0 0x3000>, 2118 <0x0 0x3c000000 0x0 0xf1d>, 2119 <0x0 0x3c000f20 0x0 0xa8>, 2120 <0x0 0x3c001000 0x0 0x1000>, 2121 <0x0 0x3c100000 0x0 0x100000>, 2122 <0x0 0x01c23000 0x0 0x1000>; 2123 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2124 #address-cells = <3>; 2125 #size-cells = <2>; 2126 ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>, 2127 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>; 2128 bus-range = <0x00 0xff>; 2129 2130 dma-coherent; 2131 2132 linux,pci-domain = <2>; 2133 num-lanes = <4>; 2134 2135 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 2136 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, 2137 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, 2138 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>; 2139 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2140 2141 #interrupt-cells = <1>; 2142 interrupt-map-mask = <0 0 0 0x7>; 2143 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 2144 <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 2145 <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 2146 <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; 2147 2148 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2149 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2150 <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>, 2151 <&gcc GCC_PCIE_2A_SLV_AXI_CLK>, 2152 <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>, 2153 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2154 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2155 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2156 clock-names = "aux", 2157 "cfg", 2158 "bus_master", 2159 "bus_slave", 2160 "slave_q2a", 2161 "ddrss_sf_tbu", 2162 "noc_aggr_4", 2163 "noc_aggr_south_sf"; 2164 2165 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>; 2166 assigned-clock-rates = <19200000>; 2167 2168 interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>, 2169 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>; 2170 interconnect-names = "pcie-mem", "cpu-pcie"; 2171 2172 resets = <&gcc GCC_PCIE_2A_BCR>; 2173 reset-names = "pci"; 2174 2175 power-domains = <&gcc PCIE_2A_GDSC>; 2176 required-opps = <&rpmhpd_opp_nom>; 2177 2178 phys = <&pcie2a_phy>; 2179 phy-names = "pciephy"; 2180 2181 status = "disabled"; 2182 }; 2183 2184 pcie2a_phy: phy@1c24000 { 2185 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 2186 reg = <0x0 0x01c24000 0x0 0x2000>, 2187 <0x0 0x01c26000 0x0 0x2000>; 2188 2189 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2190 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2191 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2192 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>, 2193 <&gcc GCC_PCIE_2A_PIPE_CLK>, 2194 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>; 2195 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2196 "pipe", "pipediv2"; 2197 2198 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>; 2199 assigned-clock-rates = <100000000>; 2200 2201 power-domains = <&gcc PCIE_2A_GDSC>; 2202 2203 resets = <&gcc GCC_PCIE_2A_PHY_BCR>; 2204 reset-names = "phy"; 2205 2206 qcom,4ln-config-sel = <&tcsr 0xa044 0>; 2207 2208 #clock-cells = <0>; 2209 clock-output-names = "pcie_2a_pipe_clk"; 2210 2211 #phy-cells = <0>; 2212 2213 status = "disabled"; 2214 }; 2215 2216 ufs_mem_hc: ufs@1d84000 { 2217 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2218 "jedec,ufs-2.0"; 2219 reg = <0 0x01d84000 0 0x3000>; 2220 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2221 phys = <&ufs_mem_phy>; 2222 phy-names = "ufsphy"; 2223 lanes-per-direction = <2>; 2224 #reset-cells = <1>; 2225 resets = <&gcc GCC_UFS_PHY_BCR>; 2226 reset-names = "rst"; 2227 2228 power-domains = <&gcc UFS_PHY_GDSC>; 2229 required-opps = <&rpmhpd_opp_nom>; 2230 2231 iommus = <&apps_smmu 0xe0 0x0>; 2232 dma-coherent; 2233 2234 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2235 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2236 <&gcc GCC_UFS_PHY_AHB_CLK>, 2237 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2238 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2239 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2240 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2241 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2242 clock-names = "core_clk", 2243 "bus_aggr_clk", 2244 "iface_clk", 2245 "core_clk_unipro", 2246 "ref_clk", 2247 "tx_lane0_sync_clk", 2248 "rx_lane0_sync_clk", 2249 "rx_lane1_sync_clk"; 2250 freq-table-hz = <75000000 300000000>, 2251 <0 0>, 2252 <0 0>, 2253 <75000000 300000000>, 2254 <0 0>, 2255 <0 0>, 2256 <0 0>, 2257 <0 0>; 2258 status = "disabled"; 2259 }; 2260 2261 ufs_mem_phy: phy@1d87000 { 2262 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2263 reg = <0 0x01d87000 0 0x1000>; 2264 2265 clocks = <&rpmhcc RPMH_CXO_CLK>, 2266 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2267 <&gcc GCC_UFS_CARD_CLKREF_CLK>; 2268 clock-names = "ref", 2269 "ref_aux", 2270 "qref"; 2271 2272 power-domains = <&gcc UFS_PHY_GDSC>; 2273 2274 resets = <&ufs_mem_hc 0>; 2275 reset-names = "ufsphy"; 2276 2277 #phy-cells = <0>; 2278 2279 status = "disabled"; 2280 }; 2281 2282 ufs_card_hc: ufs@1da4000 { 2283 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2284 "jedec,ufs-2.0"; 2285 reg = <0 0x01da4000 0 0x3000>; 2286 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2287 phys = <&ufs_card_phy>; 2288 phy-names = "ufsphy"; 2289 lanes-per-direction = <2>; 2290 #reset-cells = <1>; 2291 resets = <&gcc GCC_UFS_CARD_BCR>; 2292 reset-names = "rst"; 2293 2294 power-domains = <&gcc UFS_CARD_GDSC>; 2295 2296 iommus = <&apps_smmu 0x4a0 0x0>; 2297 dma-coherent; 2298 2299 clocks = <&gcc GCC_UFS_CARD_AXI_CLK>, 2300 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, 2301 <&gcc GCC_UFS_CARD_AHB_CLK>, 2302 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>, 2303 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2304 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>, 2305 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>, 2306 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>; 2307 clock-names = "core_clk", 2308 "bus_aggr_clk", 2309 "iface_clk", 2310 "core_clk_unipro", 2311 "ref_clk", 2312 "tx_lane0_sync_clk", 2313 "rx_lane0_sync_clk", 2314 "rx_lane1_sync_clk"; 2315 freq-table-hz = <75000000 300000000>, 2316 <0 0>, 2317 <0 0>, 2318 <75000000 300000000>, 2319 <0 0>, 2320 <0 0>, 2321 <0 0>, 2322 <0 0>; 2323 status = "disabled"; 2324 }; 2325 2326 ufs_card_phy: phy@1da7000 { 2327 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2328 reg = <0 0x01da7000 0 0x1000>; 2329 2330 clocks = <&rpmhcc RPMH_CXO_CLK>, 2331 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>, 2332 <&gcc GCC_UFS_1_CARD_CLKREF_CLK>; 2333 clock-names = "ref", 2334 "ref_aux", 2335 "qref"; 2336 2337 power-domains = <&gcc UFS_CARD_GDSC>; 2338 2339 resets = <&ufs_card_hc 0>; 2340 reset-names = "ufsphy"; 2341 2342 #phy-cells = <0>; 2343 2344 status = "disabled"; 2345 }; 2346 2347 tcsr_mutex: hwlock@1f40000 { 2348 compatible = "qcom,tcsr-mutex"; 2349 reg = <0x0 0x01f40000 0x0 0x20000>; 2350 #hwlock-cells = <1>; 2351 }; 2352 2353 tcsr: syscon@1fc0000 { 2354 compatible = "qcom,sc8280xp-tcsr", "syscon"; 2355 reg = <0x0 0x01fc0000 0x0 0x30000>; 2356 }; 2357 2358 gpu: gpu@3d00000 { 2359 compatible = "qcom,adreno-690.0", "qcom,adreno"; 2360 2361 reg = <0 0x03d00000 0 0x40000>, 2362 <0 0x03d9e000 0 0x1000>, 2363 <0 0x03d61000 0 0x800>; 2364 reg-names = "kgsl_3d0_reg_memory", 2365 "cx_mem", 2366 "cx_dbgc"; 2367 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2368 iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>; 2369 operating-points-v2 = <&gpu_opp_table>; 2370 2371 qcom,gmu = <&gmu>; 2372 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2373 interconnect-names = "gfx-mem"; 2374 #cooling-cells = <2>; 2375 2376 status = "disabled"; 2377 2378 gpu_opp_table: opp-table { 2379 compatible = "operating-points-v2"; 2380 2381 opp-270000000 { 2382 opp-hz = /bits/ 64 <270000000>; 2383 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2384 opp-peak-kBps = <451000>; 2385 }; 2386 2387 opp-410000000 { 2388 opp-hz = /bits/ 64 <410000000>; 2389 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2390 opp-peak-kBps = <1555000>; 2391 }; 2392 2393 opp-500000000 { 2394 opp-hz = /bits/ 64 <500000000>; 2395 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2396 opp-peak-kBps = <1555000>; 2397 }; 2398 2399 opp-547000000 { 2400 opp-hz = /bits/ 64 <547000000>; 2401 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2402 opp-peak-kBps = <1555000>; 2403 }; 2404 2405 opp-606000000 { 2406 opp-hz = /bits/ 64 <606000000>; 2407 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2408 opp-peak-kBps = <2736000>; 2409 }; 2410 2411 opp-640000000 { 2412 opp-hz = /bits/ 64 <640000000>; 2413 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2414 opp-peak-kBps = <2736000>; 2415 }; 2416 2417 opp-655000000 { 2418 opp-hz = /bits/ 64 <655000000>; 2419 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2420 opp-peak-kBps = <2736000>; 2421 }; 2422 2423 opp-690000000 { 2424 opp-hz = /bits/ 64 <690000000>; 2425 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2426 opp-peak-kBps = <2736000>; 2427 }; 2428 }; 2429 }; 2430 2431 gmu: gmu@3d6a000 { 2432 compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu"; 2433 reg = <0 0x03d6a000 0 0x34000>, 2434 <0 0x03de0000 0 0x10000>, 2435 <0 0x0b290000 0 0x10000>; 2436 reg-names = "gmu", "rscc", "gmu_pdc"; 2437 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2438 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2439 interrupt-names = "hfi", "gmu"; 2440 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2441 <&gpucc GPU_CC_CXO_CLK>, 2442 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2443 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2444 <&gpucc GPU_CC_AHB_CLK>, 2445 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2446 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2447 clock-names = "gmu", 2448 "cxo", 2449 "axi", 2450 "memnoc", 2451 "ahb", 2452 "hub", 2453 "smmu_vote"; 2454 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2455 <&gpucc GPU_CC_GX_GDSC>; 2456 power-domain-names = "cx", 2457 "gx"; 2458 iommus = <&gpu_smmu 5 0xc00>; 2459 operating-points-v2 = <&gmu_opp_table>; 2460 2461 gmu_opp_table: opp-table { 2462 compatible = "operating-points-v2"; 2463 2464 opp-200000000 { 2465 opp-hz = /bits/ 64 <200000000>; 2466 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2467 }; 2468 2469 opp-500000000 { 2470 opp-hz = /bits/ 64 <500000000>; 2471 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2472 }; 2473 }; 2474 }; 2475 2476 gpucc: clock-controller@3d90000 { 2477 compatible = "qcom,sc8280xp-gpucc"; 2478 reg = <0 0x03d90000 0 0x9000>; 2479 clocks = <&rpmhcc RPMH_CXO_CLK>, 2480 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2481 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2482 clock-names = "bi_tcxo", 2483 "gcc_gpu_gpll0_clk_src", 2484 "gcc_gpu_gpll0_div_clk_src"; 2485 2486 power-domains = <&rpmhpd SC8280XP_GFX>; 2487 #clock-cells = <1>; 2488 #reset-cells = <1>; 2489 #power-domain-cells = <1>; 2490 }; 2491 2492 gpu_smmu: iommu@3da0000 { 2493 compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu", 2494 "qcom,smmu-500", "arm,mmu-500"; 2495 reg = <0 0x03da0000 0 0x20000>; 2496 #iommu-cells = <2>; 2497 #global-interrupts = <2>; 2498 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2499 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2500 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2501 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2502 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2503 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2504 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2505 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2506 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2507 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2508 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2509 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2510 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, 2511 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>; 2512 2513 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2514 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2515 <&gpucc GPU_CC_AHB_CLK>, 2516 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2517 <&gpucc GPU_CC_CX_GMU_CLK>, 2518 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2519 <&gpucc GPU_CC_HUB_AON_CLK>; 2520 clock-names = "gcc_gpu_memnoc_gfx_clk", 2521 "gcc_gpu_snoc_dvm_gfx_clk", 2522 "gpu_cc_ahb_clk", 2523 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2524 "gpu_cc_cx_gmu_clk", 2525 "gpu_cc_hub_cx_int_clk", 2526 "gpu_cc_hub_aon_clk"; 2527 2528 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2529 dma-coherent; 2530 }; 2531 2532 usb_0_hsphy: phy@88e5000 { 2533 compatible = "qcom,sc8280xp-usb-hs-phy", 2534 "qcom,usb-snps-hs-5nm-phy"; 2535 reg = <0 0x088e5000 0 0x400>; 2536 clocks = <&rpmhcc RPMH_CXO_CLK>; 2537 clock-names = "ref"; 2538 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2539 2540 #phy-cells = <0>; 2541 2542 status = "disabled"; 2543 }; 2544 2545 usb_2_hsphy0: phy@88e7000 { 2546 compatible = "qcom,sc8280xp-usb-hs-phy", 2547 "qcom,usb-snps-hs-5nm-phy"; 2548 reg = <0 0x088e7000 0 0x400>; 2549 clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>; 2550 clock-names = "ref"; 2551 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 2552 2553 #phy-cells = <0>; 2554 2555 status = "disabled"; 2556 }; 2557 2558 usb_2_hsphy1: phy@88e8000 { 2559 compatible = "qcom,sc8280xp-usb-hs-phy", 2560 "qcom,usb-snps-hs-5nm-phy"; 2561 reg = <0 0x088e8000 0 0x400>; 2562 clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>; 2563 clock-names = "ref"; 2564 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 2565 2566 #phy-cells = <0>; 2567 2568 status = "disabled"; 2569 }; 2570 2571 usb_2_hsphy2: phy@88e9000 { 2572 compatible = "qcom,sc8280xp-usb-hs-phy", 2573 "qcom,usb-snps-hs-5nm-phy"; 2574 reg = <0 0x088e9000 0 0x400>; 2575 clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>; 2576 clock-names = "ref"; 2577 resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>; 2578 2579 #phy-cells = <0>; 2580 2581 status = "disabled"; 2582 }; 2583 2584 usb_2_hsphy3: phy@88ea000 { 2585 compatible = "qcom,sc8280xp-usb-hs-phy", 2586 "qcom,usb-snps-hs-5nm-phy"; 2587 reg = <0 0x088ea000 0 0x400>; 2588 clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>; 2589 clock-names = "ref"; 2590 resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>; 2591 2592 #phy-cells = <0>; 2593 2594 status = "disabled"; 2595 }; 2596 2597 usb_2_qmpphy0: phy@88ef000 { 2598 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 2599 reg = <0 0x088ef000 0 0x2000>; 2600 2601 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2602 <&gcc GCC_USB3_MP0_CLKREF_CLK>, 2603 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2604 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 2605 clock-names = "aux", "ref", "com_aux", "pipe"; 2606 2607 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 2608 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 2609 reset-names = "phy", "phy_phy"; 2610 2611 power-domains = <&gcc USB30_MP_GDSC>; 2612 2613 #clock-cells = <0>; 2614 clock-output-names = "usb2_phy0_pipe_clk"; 2615 2616 #phy-cells = <0>; 2617 2618 status = "disabled"; 2619 }; 2620 2621 usb_2_qmpphy1: phy@88f1000 { 2622 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 2623 reg = <0 0x088f1000 0 0x2000>; 2624 2625 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2626 <&gcc GCC_USB3_MP1_CLKREF_CLK>, 2627 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2628 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 2629 clock-names = "aux", "ref", "com_aux", "pipe"; 2630 2631 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, 2632 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 2633 reset-names = "phy", "phy_phy"; 2634 2635 power-domains = <&gcc USB30_MP_GDSC>; 2636 2637 #clock-cells = <0>; 2638 clock-output-names = "usb2_phy1_pipe_clk"; 2639 2640 #phy-cells = <0>; 2641 2642 status = "disabled"; 2643 }; 2644 2645 remoteproc_adsp: remoteproc@3000000 { 2646 compatible = "qcom,sc8280xp-adsp-pas"; 2647 reg = <0 0x03000000 0 0x100>; 2648 2649 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2650 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2651 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2652 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2653 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, 2654 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; 2655 interrupt-names = "wdog", "fatal", "ready", 2656 "handover", "stop-ack", "shutdown-ack"; 2657 2658 clocks = <&rpmhcc RPMH_CXO_CLK>; 2659 clock-names = "xo"; 2660 2661 power-domains = <&rpmhpd SC8280XP_LCX>, 2662 <&rpmhpd SC8280XP_LMX>; 2663 power-domain-names = "lcx", "lmx"; 2664 2665 memory-region = <&pil_adsp_mem>; 2666 2667 qcom,qmp = <&aoss_qmp>; 2668 2669 qcom,smem-states = <&smp2p_adsp_out 0>; 2670 qcom,smem-state-names = "stop"; 2671 2672 status = "disabled"; 2673 2674 remoteproc_adsp_glink: glink-edge { 2675 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2676 IPCC_MPROC_SIGNAL_GLINK_QMP 2677 IRQ_TYPE_EDGE_RISING>; 2678 mboxes = <&ipcc IPCC_CLIENT_LPASS 2679 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2680 2681 label = "lpass"; 2682 qcom,remote-pid = <2>; 2683 2684 gpr { 2685 compatible = "qcom,gpr"; 2686 qcom,glink-channels = "adsp_apps"; 2687 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2688 qcom,intents = <512 20>; 2689 #address-cells = <1>; 2690 #size-cells = <0>; 2691 2692 q6apm: service@1 { 2693 compatible = "qcom,q6apm"; 2694 reg = <GPR_APM_MODULE_IID>; 2695 #sound-dai-cells = <0>; 2696 qcom,protection-domain = "avs/audio", 2697 "msm/adsp/audio_pd"; 2698 q6apmdai: dais { 2699 compatible = "qcom,q6apm-dais"; 2700 iommus = <&apps_smmu 0x0c01 0x0>; 2701 }; 2702 2703 q6apmbedai: bedais { 2704 compatible = "qcom,q6apm-lpass-dais"; 2705 #sound-dai-cells = <1>; 2706 }; 2707 }; 2708 2709 q6prm: service@2 { 2710 compatible = "qcom,q6prm"; 2711 reg = <GPR_PRM_MODULE_IID>; 2712 qcom,protection-domain = "avs/audio", 2713 "msm/adsp/audio_pd"; 2714 q6prmcc: clock-controller { 2715 compatible = "qcom,q6prm-lpass-clocks"; 2716 #clock-cells = <2>; 2717 }; 2718 }; 2719 }; 2720 }; 2721 }; 2722 2723 rxmacro: rxmacro@3200000 { 2724 compatible = "qcom,sc8280xp-lpass-rx-macro"; 2725 reg = <0 0x03200000 0 0x1000>; 2726 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2727 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2728 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2729 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2730 <&vamacro>; 2731 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2732 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2733 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2734 assigned-clock-rates = <19200000>, <19200000>; 2735 2736 clock-output-names = "mclk"; 2737 #clock-cells = <0>; 2738 #sound-dai-cells = <1>; 2739 2740 pinctrl-names = "default"; 2741 pinctrl-0 = <&rx_swr_default>; 2742 2743 status = "disabled"; 2744 }; 2745 2746 swr1: soundwire@3210000 { 2747 compatible = "qcom,soundwire-v1.6.0"; 2748 reg = <0 0x03210000 0 0x2000>; 2749 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2750 clocks = <&rxmacro>; 2751 clock-names = "iface"; 2752 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2753 reset-names = "swr_audio_cgcr"; 2754 label = "RX"; 2755 2756 qcom,din-ports = <0>; 2757 qcom,dout-ports = <5>; 2758 2759 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2760 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; 2761 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; 2762 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>; 2763 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>; 2764 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2765 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>; 2766 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2767 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2768 2769 #sound-dai-cells = <1>; 2770 #address-cells = <2>; 2771 #size-cells = <0>; 2772 2773 status = "disabled"; 2774 }; 2775 2776 txmacro: txmacro@3220000 { 2777 compatible = "qcom,sc8280xp-lpass-tx-macro"; 2778 reg = <0 0x03220000 0 0x1000>; 2779 pinctrl-names = "default"; 2780 pinctrl-0 = <&tx_swr_default>; 2781 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2782 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2783 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2784 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2785 <&vamacro>; 2786 2787 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2788 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2789 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2790 assigned-clock-rates = <19200000>, <19200000>; 2791 clock-output-names = "mclk"; 2792 2793 #clock-cells = <0>; 2794 #sound-dai-cells = <1>; 2795 2796 status = "disabled"; 2797 }; 2798 2799 wsamacro: codec@3240000 { 2800 compatible = "qcom,sc8280xp-lpass-wsa-macro"; 2801 reg = <0 0x03240000 0 0x1000>; 2802 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2803 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2804 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2805 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2806 <&vamacro>; 2807 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2808 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2809 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2810 assigned-clock-rates = <19200000>, <19200000>; 2811 2812 #clock-cells = <0>; 2813 clock-output-names = "mclk"; 2814 #sound-dai-cells = <1>; 2815 2816 pinctrl-names = "default"; 2817 pinctrl-0 = <&wsa_swr_default>; 2818 2819 status = "disabled"; 2820 }; 2821 2822 swr0: soundwire@3250000 { 2823 reg = <0 0x03250000 0 0x2000>; 2824 compatible = "qcom,soundwire-v1.6.0"; 2825 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2826 clocks = <&wsamacro>; 2827 clock-names = "iface"; 2828 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; 2829 reset-names = "swr_audio_cgcr"; 2830 label = "WSA"; 2831 2832 qcom,din-ports = <2>; 2833 qcom,dout-ports = <6>; 2834 2835 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2836 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2837 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2838 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2839 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2840 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2841 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2842 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2843 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2844 2845 #sound-dai-cells = <1>; 2846 #address-cells = <2>; 2847 #size-cells = <0>; 2848 2849 status = "disabled"; 2850 }; 2851 2852 lpass_audiocc: clock-controller@32a9000 { 2853 compatible = "qcom,sc8280xp-lpassaudiocc"; 2854 reg = <0 0x032a9000 0 0x1000>; 2855 #clock-cells = <1>; 2856 #reset-cells = <1>; 2857 }; 2858 2859 swr2: soundwire@3330000 { 2860 compatible = "qcom,soundwire-v1.6.0"; 2861 reg = <0 0x03330000 0 0x2000>; 2862 interrupts = <GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>, 2863 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2864 interrupt-names = "core", "wakeup"; 2865 2866 clocks = <&txmacro>; 2867 clock-names = "iface"; 2868 resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; 2869 reset-names = "swr_audio_cgcr"; 2870 label = "TX"; 2871 #sound-dai-cells = <1>; 2872 #address-cells = <2>; 2873 #size-cells = <0>; 2874 2875 qcom,din-ports = <4>; 2876 qcom,dout-ports = <0>; 2877 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2878 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>; 2879 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2880 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2881 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2882 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2883 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2884 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2885 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>; 2886 2887 status = "disabled"; 2888 }; 2889 2890 vamacro: codec@3370000 { 2891 compatible = "qcom,sc8280xp-lpass-va-macro"; 2892 reg = <0 0x03370000 0 0x1000>; 2893 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2894 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2895 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2896 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2897 clock-names = "mclk", "macro", "dcodec", "npl"; 2898 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2899 assigned-clock-rates = <19200000>; 2900 2901 #clock-cells = <0>; 2902 clock-output-names = "fsgen"; 2903 #sound-dai-cells = <1>; 2904 2905 status = "disabled"; 2906 }; 2907 2908 lpass_tlmm: pinctrl@33c0000 { 2909 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl"; 2910 reg = <0 0x33c0000 0x0 0x20000>, 2911 <0 0x3550000 0x0 0x10000>; 2912 gpio-controller; 2913 #gpio-cells = <2>; 2914 gpio-ranges = <&lpass_tlmm 0 0 19>; 2915 2916 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2917 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2918 clock-names = "core", "audio"; 2919 2920 status = "disabled"; 2921 2922 tx_swr_default: tx-swr-default-state { 2923 clk-pins { 2924 pins = "gpio0"; 2925 function = "swr_tx_clk"; 2926 drive-strength = <2>; 2927 slew-rate = <1>; 2928 bias-disable; 2929 }; 2930 2931 data-pins { 2932 pins = "gpio1", "gpio2"; 2933 function = "swr_tx_data"; 2934 drive-strength = <2>; 2935 slew-rate = <1>; 2936 bias-bus-hold; 2937 }; 2938 }; 2939 2940 rx_swr_default: rx-swr-default-state { 2941 clk-pins { 2942 pins = "gpio3"; 2943 function = "swr_rx_clk"; 2944 drive-strength = <2>; 2945 slew-rate = <1>; 2946 bias-disable; 2947 }; 2948 2949 data-pins { 2950 pins = "gpio4", "gpio5"; 2951 function = "swr_rx_data"; 2952 drive-strength = <2>; 2953 slew-rate = <1>; 2954 bias-bus-hold; 2955 }; 2956 }; 2957 2958 dmic01_default: dmic01-default-state { 2959 clk-pins { 2960 pins = "gpio6"; 2961 function = "dmic1_clk"; 2962 drive-strength = <8>; 2963 output-high; 2964 }; 2965 2966 data-pins { 2967 pins = "gpio7"; 2968 function = "dmic1_data"; 2969 drive-strength = <8>; 2970 input-enable; 2971 }; 2972 }; 2973 2974 dmic01_sleep: dmic01-sleep-state { 2975 clk-pins { 2976 pins = "gpio6"; 2977 function = "dmic1_clk"; 2978 drive-strength = <2>; 2979 bias-disable; 2980 output-low; 2981 }; 2982 2983 data-pins { 2984 pins = "gpio7"; 2985 function = "dmic1_data"; 2986 drive-strength = <2>; 2987 bias-pull-down; 2988 input-enable; 2989 }; 2990 }; 2991 2992 dmic23_default: dmic23-default-state { 2993 clk-pins { 2994 pins = "gpio8"; 2995 function = "dmic2_clk"; 2996 drive-strength = <8>; 2997 output-high; 2998 }; 2999 3000 data-pins { 3001 pins = "gpio9"; 3002 function = "dmic2_data"; 3003 drive-strength = <8>; 3004 input-enable; 3005 }; 3006 }; 3007 3008 dmic23_sleep: dmic23-sleep-state { 3009 clk-pins { 3010 pins = "gpio8"; 3011 function = "dmic2_clk"; 3012 drive-strength = <2>; 3013 bias-disable; 3014 output-low; 3015 }; 3016 3017 data-pins { 3018 pins = "gpio9"; 3019 function = "dmic2_data"; 3020 drive-strength = <2>; 3021 bias-pull-down; 3022 input-enable; 3023 }; 3024 }; 3025 3026 wsa_swr_default: wsa-swr-default-state { 3027 clk-pins { 3028 pins = "gpio10"; 3029 function = "wsa_swr_clk"; 3030 drive-strength = <2>; 3031 slew-rate = <1>; 3032 bias-disable; 3033 }; 3034 3035 data-pins { 3036 pins = "gpio11"; 3037 function = "wsa_swr_data"; 3038 drive-strength = <2>; 3039 slew-rate = <1>; 3040 bias-bus-hold; 3041 }; 3042 }; 3043 3044 wsa2_swr_default: wsa2-swr-default-state { 3045 clk-pins { 3046 pins = "gpio15"; 3047 function = "wsa2_swr_clk"; 3048 drive-strength = <2>; 3049 slew-rate = <1>; 3050 bias-disable; 3051 }; 3052 3053 data-pins { 3054 pins = "gpio16"; 3055 function = "wsa2_swr_data"; 3056 drive-strength = <2>; 3057 slew-rate = <1>; 3058 bias-bus-hold; 3059 }; 3060 }; 3061 }; 3062 3063 lpasscc: clock-controller@33e0000 { 3064 compatible = "qcom,sc8280xp-lpasscc"; 3065 reg = <0 0x033e0000 0 0x12000>; 3066 #clock-cells = <1>; 3067 #reset-cells = <1>; 3068 }; 3069 3070 sdc2: mmc@8804000 { 3071 compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5"; 3072 reg = <0 0x08804000 0 0x1000>; 3073 3074 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3075 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3076 interrupt-names = "hc_irq", "pwr_irq"; 3077 3078 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3079 <&gcc GCC_SDCC2_APPS_CLK>, 3080 <&rpmhcc RPMH_CXO_CLK>; 3081 clock-names = "iface", "core", "xo"; 3082 resets = <&gcc GCC_SDCC2_BCR>; 3083 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3084 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 3085 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3086 iommus = <&apps_smmu 0x4e0 0x0>; 3087 power-domains = <&rpmhpd SC8280XP_CX>; 3088 operating-points-v2 = <&sdc2_opp_table>; 3089 bus-width = <4>; 3090 dma-coherent; 3091 3092 status = "disabled"; 3093 3094 sdc2_opp_table: opp-table { 3095 compatible = "operating-points-v2"; 3096 3097 opp-100000000 { 3098 opp-hz = /bits/ 64 <100000000>; 3099 required-opps = <&rpmhpd_opp_low_svs>; 3100 opp-peak-kBps = <1800000 400000>; 3101 opp-avg-kBps = <100000 0>; 3102 }; 3103 3104 opp-202000000 { 3105 opp-hz = /bits/ 64 <202000000>; 3106 required-opps = <&rpmhpd_opp_svs_l1>; 3107 opp-peak-kBps = <5400000 1600000>; 3108 opp-avg-kBps = <200000 0>; 3109 }; 3110 }; 3111 }; 3112 3113 usb_0_qmpphy: phy@88eb000 { 3114 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 3115 reg = <0 0x088eb000 0 0x4000>; 3116 3117 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3118 <&gcc GCC_USB4_EUD_CLKREF_CLK>, 3119 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3120 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3121 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3122 3123 power-domains = <&gcc USB30_PRIM_GDSC>; 3124 3125 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3126 <&gcc GCC_USB4_DP_PHY_PRIM_BCR>; 3127 reset-names = "phy", "common"; 3128 3129 #clock-cells = <1>; 3130 #phy-cells = <1>; 3131 3132 status = "disabled"; 3133 3134 ports { 3135 #address-cells = <1>; 3136 #size-cells = <0>; 3137 3138 port@0 { 3139 reg = <0>; 3140 3141 usb_0_qmpphy_out: endpoint {}; 3142 }; 3143 3144 port@2 { 3145 reg = <2>; 3146 3147 usb_0_qmpphy_dp_in: endpoint {}; 3148 }; 3149 }; 3150 }; 3151 3152 usb_1_hsphy: phy@8902000 { 3153 compatible = "qcom,sc8280xp-usb-hs-phy", 3154 "qcom,usb-snps-hs-5nm-phy"; 3155 reg = <0 0x08902000 0 0x400>; 3156 #phy-cells = <0>; 3157 3158 clocks = <&rpmhcc RPMH_CXO_CLK>; 3159 clock-names = "ref"; 3160 3161 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3162 3163 status = "disabled"; 3164 }; 3165 3166 usb_1_qmpphy: phy@8903000 { 3167 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 3168 reg = <0 0x08903000 0 0x4000>; 3169 3170 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3171 <&gcc GCC_USB4_CLKREF_CLK>, 3172 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 3173 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3174 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3175 3176 power-domains = <&gcc USB30_SEC_GDSC>; 3177 3178 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 3179 <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>; 3180 reset-names = "phy", "common"; 3181 3182 #clock-cells = <1>; 3183 #phy-cells = <1>; 3184 3185 status = "disabled"; 3186 3187 ports { 3188 #address-cells = <1>; 3189 #size-cells = <0>; 3190 3191 port@0 { 3192 reg = <0>; 3193 3194 usb_1_qmpphy_out: endpoint {}; 3195 }; 3196 3197 port@2 { 3198 reg = <2>; 3199 3200 usb_1_qmpphy_dp_in: endpoint {}; 3201 }; 3202 }; 3203 }; 3204 3205 mdss1_dp0_phy: phy@8909a00 { 3206 compatible = "qcom,sc8280xp-dp-phy"; 3207 reg = <0 0x08909a00 0 0x19c>, 3208 <0 0x08909200 0 0xec>, 3209 <0 0x08909600 0 0xec>, 3210 <0 0x08909000 0 0x1c8>; 3211 3212 clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 3213 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 3214 clock-names = "aux", "cfg_ahb"; 3215 power-domains = <&rpmhpd SC8280XP_MX>; 3216 3217 #clock-cells = <1>; 3218 #phy-cells = <0>; 3219 3220 status = "disabled"; 3221 }; 3222 3223 mdss1_dp1_phy: phy@890ca00 { 3224 compatible = "qcom,sc8280xp-dp-phy"; 3225 reg = <0 0x0890ca00 0 0x19c>, 3226 <0 0x0890c200 0 0xec>, 3227 <0 0x0890c600 0 0xec>, 3228 <0 0x0890c000 0 0x1c8>; 3229 3230 clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 3231 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 3232 clock-names = "aux", "cfg_ahb"; 3233 power-domains = <&rpmhpd SC8280XP_MX>; 3234 3235 #clock-cells = <1>; 3236 #phy-cells = <0>; 3237 3238 status = "disabled"; 3239 }; 3240 3241 pmu@9091000 { 3242 compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3243 reg = <0 0x09091000 0 0x1000>; 3244 3245 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3246 3247 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3248 3249 operating-points-v2 = <&llcc_bwmon_opp_table>; 3250 3251 llcc_bwmon_opp_table: opp-table { 3252 compatible = "operating-points-v2"; 3253 3254 opp-0 { 3255 opp-peak-kBps = <762000>; 3256 }; 3257 opp-1 { 3258 opp-peak-kBps = <1720000>; 3259 }; 3260 opp-2 { 3261 opp-peak-kBps = <2086000>; 3262 }; 3263 opp-3 { 3264 opp-peak-kBps = <2597000>; 3265 }; 3266 opp-4 { 3267 opp-peak-kBps = <2929000>; 3268 }; 3269 opp-5 { 3270 opp-peak-kBps = <3879000>; 3271 }; 3272 opp-6 { 3273 opp-peak-kBps = <5161000>; 3274 }; 3275 opp-7 { 3276 opp-peak-kBps = <5931000>; 3277 }; 3278 opp-8 { 3279 opp-peak-kBps = <6515000>; 3280 }; 3281 opp-9 { 3282 opp-peak-kBps = <7980000>; 3283 }; 3284 opp-10 { 3285 opp-peak-kBps = <8136000>; 3286 }; 3287 opp-11 { 3288 opp-peak-kBps = <10437000>; 3289 }; 3290 opp-12 { 3291 opp-peak-kBps = <12191000>; 3292 }; 3293 }; 3294 }; 3295 3296 pmu@90b6400 { 3297 compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon"; 3298 reg = <0 0x090b6400 0 0x600>; 3299 3300 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3301 3302 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3303 operating-points-v2 = <&cpu_bwmon_opp_table>; 3304 3305 cpu_bwmon_opp_table: opp-table { 3306 compatible = "operating-points-v2"; 3307 3308 opp-0 { 3309 opp-peak-kBps = <2288000>; 3310 }; 3311 opp-1 { 3312 opp-peak-kBps = <4577000>; 3313 }; 3314 opp-2 { 3315 opp-peak-kBps = <7110000>; 3316 }; 3317 opp-3 { 3318 opp-peak-kBps = <9155000>; 3319 }; 3320 opp-4 { 3321 opp-peak-kBps = <12298000>; 3322 }; 3323 opp-5 { 3324 opp-peak-kBps = <14236000>; 3325 }; 3326 opp-6 { 3327 opp-peak-kBps = <15258001>; 3328 }; 3329 }; 3330 }; 3331 3332 system-cache-controller@9200000 { 3333 compatible = "qcom,sc8280xp-llcc"; 3334 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 3335 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 3336 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, 3337 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, 3338 <0 0x09600000 0 0x58000>; 3339 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 3340 "llcc3_base", "llcc4_base", "llcc5_base", 3341 "llcc6_base", "llcc7_base", "llcc_broadcast_base"; 3342 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3343 }; 3344 3345 usb_0: usb@a6f8800 { 3346 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 3347 reg = <0 0x0a6f8800 0 0x400>; 3348 #address-cells = <2>; 3349 #size-cells = <2>; 3350 ranges; 3351 3352 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3353 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3354 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3355 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3356 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3357 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3358 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 3359 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 3360 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3361 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 3362 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 3363 3364 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3365 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3366 assigned-clock-rates = <19200000>, <200000000>; 3367 3368 interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 3369 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3370 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3371 <&pdc 138 IRQ_TYPE_LEVEL_HIGH>; 3372 interrupt-names = "pwr_event", 3373 "dp_hs_phy_irq", 3374 "dm_hs_phy_irq", 3375 "ss_phy_irq"; 3376 3377 power-domains = <&gcc USB30_PRIM_GDSC>; 3378 required-opps = <&rpmhpd_opp_nom>; 3379 3380 resets = <&gcc GCC_USB30_PRIM_BCR>; 3381 3382 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3383 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 3384 interconnect-names = "usb-ddr", "apps-usb"; 3385 3386 wakeup-source; 3387 3388 status = "disabled"; 3389 3390 usb_0_dwc3: usb@a600000 { 3391 compatible = "snps,dwc3"; 3392 reg = <0 0x0a600000 0 0xcd00>; 3393 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 3394 iommus = <&apps_smmu 0x820 0x0>; 3395 phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; 3396 phy-names = "usb2-phy", "usb3-phy"; 3397 3398 port { 3399 usb_0_role_switch: endpoint { 3400 }; 3401 }; 3402 }; 3403 }; 3404 3405 usb_1: usb@a8f8800 { 3406 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 3407 reg = <0 0x0a8f8800 0 0x400>; 3408 #address-cells = <2>; 3409 #size-cells = <2>; 3410 ranges; 3411 3412 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3413 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3414 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3415 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3416 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3417 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3418 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 3419 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 3420 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3421 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 3422 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 3423 3424 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3425 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3426 assigned-clock-rates = <19200000>, <200000000>; 3427 3428 interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 3429 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 3430 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 3431 <&pdc 136 IRQ_TYPE_LEVEL_HIGH>; 3432 interrupt-names = "pwr_event", 3433 "dp_hs_phy_irq", 3434 "dm_hs_phy_irq", 3435 "ss_phy_irq"; 3436 3437 power-domains = <&gcc USB30_SEC_GDSC>; 3438 required-opps = <&rpmhpd_opp_nom>; 3439 3440 resets = <&gcc GCC_USB30_SEC_BCR>; 3441 3442 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 3443 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 3444 interconnect-names = "usb-ddr", "apps-usb"; 3445 3446 wakeup-source; 3447 3448 status = "disabled"; 3449 3450 usb_1_dwc3: usb@a800000 { 3451 compatible = "snps,dwc3"; 3452 reg = <0 0x0a800000 0 0xcd00>; 3453 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 3454 iommus = <&apps_smmu 0x860 0x0>; 3455 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 3456 phy-names = "usb2-phy", "usb3-phy"; 3457 3458 port { 3459 usb_1_role_switch: endpoint { 3460 }; 3461 }; 3462 }; 3463 }; 3464 3465 cci0: cci@ac4a000 { 3466 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 3467 reg = <0 0x0ac4a000 0 0x1000>; 3468 3469 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 3470 3471 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 3472 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 3473 <&camcc CAMCC_CPAS_AHB_CLK>, 3474 <&camcc CAMCC_CCI_0_CLK>; 3475 clock-names = "camnoc_axi", 3476 "slow_ahb_src", 3477 "cpas_ahb", 3478 "cci"; 3479 3480 power-domains = <&camcc TITAN_TOP_GDSC>; 3481 3482 pinctrl-0 = <&cci0_default>; 3483 pinctrl-1 = <&cci0_sleep>; 3484 pinctrl-names = "default", "sleep"; 3485 3486 #address-cells = <1>; 3487 #size-cells = <0>; 3488 3489 status = "disabled"; 3490 3491 cci0_i2c0: i2c-bus@0 { 3492 reg = <0>; 3493 clock-frequency = <1000000>; 3494 #address-cells = <1>; 3495 #size-cells = <0>; 3496 }; 3497 3498 cci0_i2c1: i2c-bus@1 { 3499 reg = <1>; 3500 clock-frequency = <1000000>; 3501 #address-cells = <1>; 3502 #size-cells = <0>; 3503 }; 3504 }; 3505 3506 cci1: cci@ac4b000 { 3507 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 3508 reg = <0 0x0ac4b000 0 0x1000>; 3509 3510 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 3511 3512 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 3513 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 3514 <&camcc CAMCC_CPAS_AHB_CLK>, 3515 <&camcc CAMCC_CCI_1_CLK>; 3516 clock-names = "camnoc_axi", 3517 "slow_ahb_src", 3518 "cpas_ahb", 3519 "cci"; 3520 3521 power-domains = <&camcc TITAN_TOP_GDSC>; 3522 3523 pinctrl-0 = <&cci1_default>; 3524 pinctrl-1 = <&cci1_sleep>; 3525 pinctrl-names = "default", "sleep"; 3526 3527 #address-cells = <1>; 3528 #size-cells = <0>; 3529 3530 status = "disabled"; 3531 3532 cci1_i2c0: i2c-bus@0 { 3533 reg = <0>; 3534 clock-frequency = <1000000>; 3535 #address-cells = <1>; 3536 #size-cells = <0>; 3537 }; 3538 3539 cci1_i2c1: i2c-bus@1 { 3540 reg = <1>; 3541 clock-frequency = <1000000>; 3542 #address-cells = <1>; 3543 #size-cells = <0>; 3544 }; 3545 }; 3546 3547 cci2: cci@ac4c000 { 3548 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 3549 reg = <0 0x0ac4c000 0 0x1000>; 3550 3551 interrupts = <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>; 3552 3553 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 3554 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 3555 <&camcc CAMCC_CPAS_AHB_CLK>, 3556 <&camcc CAMCC_CCI_2_CLK>; 3557 clock-names = "camnoc_axi", 3558 "slow_ahb_src", 3559 "cpas_ahb", 3560 "cci"; 3561 power-domains = <&camcc TITAN_TOP_GDSC>; 3562 3563 pinctrl-0 = <&cci2_default>; 3564 pinctrl-1 = <&cci2_sleep>; 3565 pinctrl-names = "default", "sleep"; 3566 3567 #address-cells = <1>; 3568 #size-cells = <0>; 3569 3570 status = "disabled"; 3571 3572 cci2_i2c0: i2c-bus@0 { 3573 reg = <0>; 3574 clock-frequency = <1000000>; 3575 #address-cells = <1>; 3576 #size-cells = <0>; 3577 }; 3578 3579 cci2_i2c1: i2c-bus@1 { 3580 reg = <1>; 3581 clock-frequency = <1000000>; 3582 #address-cells = <1>; 3583 #size-cells = <0>; 3584 }; 3585 }; 3586 3587 cci3: cci@ac4d000 { 3588 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 3589 reg = <0 0x0ac4d000 0 0x1000>; 3590 3591 interrupts = <GIC_SPI 650 IRQ_TYPE_EDGE_RISING>; 3592 3593 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 3594 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 3595 <&camcc CAMCC_CPAS_AHB_CLK>, 3596 <&camcc CAMCC_CCI_3_CLK>; 3597 clock-names = "camnoc_axi", 3598 "slow_ahb_src", 3599 "cpas_ahb", 3600 "cci"; 3601 3602 power-domains = <&camcc TITAN_TOP_GDSC>; 3603 3604 pinctrl-0 = <&cci3_default>; 3605 pinctrl-1 = <&cci3_sleep>; 3606 pinctrl-names = "default", "sleep"; 3607 3608 #address-cells = <1>; 3609 #size-cells = <0>; 3610 3611 status = "disabled"; 3612 3613 cci3_i2c0: i2c-bus@0 { 3614 reg = <0>; 3615 clock-frequency = <1000000>; 3616 #address-cells = <1>; 3617 #size-cells = <0>; 3618 }; 3619 3620 cci3_i2c1: i2c-bus@1 { 3621 reg = <1>; 3622 clock-frequency = <1000000>; 3623 #address-cells = <1>; 3624 #size-cells = <0>; 3625 }; 3626 }; 3627 3628 camss: camss@ac5a000 { 3629 compatible = "qcom,sc8280xp-camss"; 3630 3631 reg = <0 0x0ac5a000 0 0x2000>, 3632 <0 0x0ac5c000 0 0x2000>, 3633 <0 0x0ac65000 0 0x2000>, 3634 <0 0x0ac67000 0 0x2000>, 3635 <0 0x0acaf000 0 0x4000>, 3636 <0 0x0acb3000 0 0x1000>, 3637 <0 0x0acb6000 0 0x4000>, 3638 <0 0x0acba000 0 0x1000>, 3639 <0 0x0acbd000 0 0x4000>, 3640 <0 0x0acc1000 0 0x1000>, 3641 <0 0x0acc4000 0 0x4000>, 3642 <0 0x0acc8000 0 0x1000>, 3643 <0 0x0accb000 0 0x4000>, 3644 <0 0x0accf000 0 0x1000>, 3645 <0 0x0acd2000 0 0x4000>, 3646 <0 0x0acd6000 0 0x1000>, 3647 <0 0x0acd9000 0 0x4000>, 3648 <0 0x0acdd000 0 0x1000>, 3649 <0 0x0ace0000 0 0x4000>, 3650 <0 0x0ace4000 0 0x1000>; 3651 reg-names = "csiphy2", 3652 "csiphy3", 3653 "csiphy0", 3654 "csiphy1", 3655 "vfe0", 3656 "csid0", 3657 "vfe1", 3658 "csid1", 3659 "vfe2", 3660 "csid2", 3661 "vfe_lite0", 3662 "csid0_lite", 3663 "vfe_lite1", 3664 "csid1_lite", 3665 "vfe_lite2", 3666 "csid2_lite", 3667 "vfe_lite3", 3668 "csid3_lite", 3669 "vfe3", 3670 "csid3"; 3671 3672 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 3673 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 3674 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 3675 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 3676 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 3677 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 3678 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 3679 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 3680 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 3681 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, 3682 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, 3683 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, 3684 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>, 3685 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 3686 <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>, 3687 <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>, 3688 <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>, 3689 <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>, 3690 <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>, 3691 <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>; 3692 interrupt-names = "csid1_lite", 3693 "vfe_lite1", 3694 "csiphy3", 3695 "csid0", 3696 "vfe0", 3697 "csid1", 3698 "vfe1", 3699 "csid0_lite", 3700 "vfe_lite0", 3701 "csiphy0", 3702 "csiphy1", 3703 "csiphy2", 3704 "csid2", 3705 "vfe2", 3706 "csid3_lite", 3707 "csid2_lite", 3708 "vfe_lite3", 3709 "vfe_lite2", 3710 "csid3", 3711 "vfe3"; 3712 3713 power-domains = <&camcc IFE_0_GDSC>, 3714 <&camcc IFE_1_GDSC>, 3715 <&camcc IFE_2_GDSC>, 3716 <&camcc IFE_3_GDSC>, 3717 <&camcc TITAN_TOP_GDSC>; 3718 power-domain-names = "ife0", 3719 "ife1", 3720 "ife2", 3721 "ife3", 3722 "top"; 3723 3724 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 3725 <&camcc CAMCC_CPAS_AHB_CLK>, 3726 <&camcc CAMCC_CSIPHY0_CLK>, 3727 <&camcc CAMCC_CSI0PHYTIMER_CLK>, 3728 <&camcc CAMCC_CSIPHY1_CLK>, 3729 <&camcc CAMCC_CSI1PHYTIMER_CLK>, 3730 <&camcc CAMCC_CSIPHY2_CLK>, 3731 <&camcc CAMCC_CSI2PHYTIMER_CLK>, 3732 <&camcc CAMCC_CSIPHY3_CLK>, 3733 <&camcc CAMCC_CSI3PHYTIMER_CLK>, 3734 <&camcc CAMCC_IFE_0_AXI_CLK>, 3735 <&camcc CAMCC_IFE_0_CLK>, 3736 <&camcc CAMCC_IFE_0_CPHY_RX_CLK>, 3737 <&camcc CAMCC_IFE_0_CSID_CLK>, 3738 <&camcc CAMCC_IFE_1_AXI_CLK>, 3739 <&camcc CAMCC_IFE_1_CLK>, 3740 <&camcc CAMCC_IFE_1_CPHY_RX_CLK>, 3741 <&camcc CAMCC_IFE_1_CSID_CLK>, 3742 <&camcc CAMCC_IFE_2_AXI_CLK>, 3743 <&camcc CAMCC_IFE_2_CLK>, 3744 <&camcc CAMCC_IFE_2_CPHY_RX_CLK>, 3745 <&camcc CAMCC_IFE_2_CSID_CLK>, 3746 <&camcc CAMCC_IFE_3_AXI_CLK>, 3747 <&camcc CAMCC_IFE_3_CLK>, 3748 <&camcc CAMCC_IFE_3_CPHY_RX_CLK>, 3749 <&camcc CAMCC_IFE_3_CSID_CLK>, 3750 <&camcc CAMCC_IFE_LITE_0_CLK>, 3751 <&camcc CAMCC_IFE_LITE_0_CPHY_RX_CLK>, 3752 <&camcc CAMCC_IFE_LITE_0_CSID_CLK>, 3753 <&camcc CAMCC_IFE_LITE_1_CLK>, 3754 <&camcc CAMCC_IFE_LITE_1_CPHY_RX_CLK>, 3755 <&camcc CAMCC_IFE_LITE_1_CSID_CLK>, 3756 <&camcc CAMCC_IFE_LITE_2_CLK>, 3757 <&camcc CAMCC_IFE_LITE_2_CPHY_RX_CLK>, 3758 <&camcc CAMCC_IFE_LITE_2_CSID_CLK>, 3759 <&camcc CAMCC_IFE_LITE_3_CLK>, 3760 <&camcc CAMCC_IFE_LITE_3_CPHY_RX_CLK>, 3761 <&camcc CAMCC_IFE_LITE_3_CSID_CLK>, 3762 <&gcc GCC_CAMERA_HF_AXI_CLK>, 3763 <&gcc GCC_CAMERA_SF_AXI_CLK>; 3764 clock-names = "camnoc_axi", 3765 "cpas_ahb", 3766 "csiphy0", 3767 "csiphy0_timer", 3768 "csiphy1", 3769 "csiphy1_timer", 3770 "csiphy2", 3771 "csiphy2_timer", 3772 "csiphy3", 3773 "csiphy3_timer", 3774 "vfe0_axi", 3775 "vfe0", 3776 "vfe0_cphy_rx", 3777 "vfe0_csid", 3778 "vfe1_axi", 3779 "vfe1", 3780 "vfe1_cphy_rx", 3781 "vfe1_csid", 3782 "vfe2_axi", 3783 "vfe2", 3784 "vfe2_cphy_rx", 3785 "vfe2_csid", 3786 "vfe3_axi", 3787 "vfe3", 3788 "vfe3_cphy_rx", 3789 "vfe3_csid", 3790 "vfe_lite0", 3791 "vfe_lite0_cphy_rx", 3792 "vfe_lite0_csid", 3793 "vfe_lite1", 3794 "vfe_lite1_cphy_rx", 3795 "vfe_lite1_csid", 3796 "vfe_lite2", 3797 "vfe_lite2_cphy_rx", 3798 "vfe_lite2_csid", 3799 "vfe_lite3", 3800 "vfe_lite3_cphy_rx", 3801 "vfe_lite3_csid", 3802 "gcc_axi_hf", 3803 "gcc_axi_sf"; 3804 3805 iommus = <&apps_smmu 0x2000 0x4e0>, 3806 <&apps_smmu 0x2020 0x4e0>, 3807 <&apps_smmu 0x2040 0x4e0>, 3808 <&apps_smmu 0x2060 0x4e0>, 3809 <&apps_smmu 0x2080 0x4e0>, 3810 <&apps_smmu 0x20e0 0x4e0>, 3811 <&apps_smmu 0x20c0 0x4e0>, 3812 <&apps_smmu 0x20a0 0x4e0>, 3813 <&apps_smmu 0x2400 0x4e0>, 3814 <&apps_smmu 0x2420 0x4e0>, 3815 <&apps_smmu 0x2440 0x4e0>, 3816 <&apps_smmu 0x2460 0x4e0>, 3817 <&apps_smmu 0x2480 0x4e0>, 3818 <&apps_smmu 0x24e0 0x4e0>, 3819 <&apps_smmu 0x24c0 0x4e0>, 3820 <&apps_smmu 0x24a0 0x4e0>; 3821 3822 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>, 3823 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>, 3824 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>, 3825 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>; 3826 interconnect-names = "cam_ahb", 3827 "cam_hf_mnoc", 3828 "cam_sf_mnoc", 3829 "cam_sf_icp_mnoc"; 3830 3831 status = "disabled"; 3832 3833 ports { 3834 #address-cells = <1>; 3835 #size-cells = <0>; 3836 3837 port@0 { 3838 reg = <0>; 3839 #address-cells = <1>; 3840 #size-cells = <0>; 3841 }; 3842 3843 port@1 { 3844 reg = <1>; 3845 #address-cells = <1>; 3846 #size-cells = <0>; 3847 }; 3848 3849 port@2 { 3850 reg = <2>; 3851 #address-cells = <1>; 3852 #size-cells = <0>; 3853 }; 3854 3855 port@3 { 3856 reg = <3>; 3857 #address-cells = <1>; 3858 #size-cells = <0>; 3859 }; 3860 }; 3861 }; 3862 3863 camcc: clock-controller@ad00000 { 3864 compatible = "qcom,sc8280xp-camcc"; 3865 reg = <0 0x0ad00000 0 0x20000>; 3866 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 3867 <&rpmhcc RPMH_CXO_CLK>, 3868 <&rpmhcc RPMH_CXO_CLK_A>, 3869 <&sleep_clk>; 3870 power-domains = <&rpmhpd SC8280XP_MMCX>; 3871 required-opps = <&rpmhpd_opp_low_svs>; 3872 #clock-cells = <1>; 3873 #reset-cells = <1>; 3874 #power-domain-cells = <1>; 3875 }; 3876 3877 mdss0: display-subsystem@ae00000 { 3878 compatible = "qcom,sc8280xp-mdss"; 3879 reg = <0 0x0ae00000 0 0x1000>; 3880 reg-names = "mdss"; 3881 3882 clocks = <&gcc GCC_DISP_AHB_CLK>, 3883 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3884 <&dispcc0 DISP_CC_MDSS_MDP_CLK>; 3885 clock-names = "iface", 3886 "ahb", 3887 "core"; 3888 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3889 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 3890 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 3891 interconnect-names = "mdp0-mem", "mdp1-mem"; 3892 iommus = <&apps_smmu 0x1000 0x402>; 3893 power-domains = <&dispcc0 MDSS_GDSC>; 3894 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>; 3895 3896 interrupt-controller; 3897 #interrupt-cells = <1>; 3898 #address-cells = <2>; 3899 #size-cells = <2>; 3900 ranges; 3901 3902 status = "disabled"; 3903 3904 mdss0_mdp: display-controller@ae01000 { 3905 compatible = "qcom,sc8280xp-dpu"; 3906 reg = <0 0x0ae01000 0 0x8f000>, 3907 <0 0x0aeb0000 0 0x2008>; 3908 reg-names = "mdp", "vbif"; 3909 3910 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3911 <&gcc GCC_DISP_SF_AXI_CLK>, 3912 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 3913 <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>, 3914 <&dispcc0 DISP_CC_MDSS_MDP_CLK>, 3915 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 3916 clock-names = "bus", 3917 "nrt_bus", 3918 "iface", 3919 "lut", 3920 "core", 3921 "vsync"; 3922 interrupt-parent = <&mdss0>; 3923 interrupts = <0>; 3924 power-domains = <&rpmhpd SC8280XP_MMCX>; 3925 3926 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 3927 assigned-clock-rates = <19200000>; 3928 operating-points-v2 = <&mdss0_mdp_opp_table>; 3929 3930 ports { 3931 #address-cells = <1>; 3932 #size-cells = <0>; 3933 3934 port@0 { 3935 reg = <0>; 3936 mdss0_intf0_out: endpoint { 3937 remote-endpoint = <&mdss0_dp0_in>; 3938 }; 3939 }; 3940 3941 port@4 { 3942 reg = <4>; 3943 mdss0_intf4_out: endpoint { 3944 remote-endpoint = <&mdss0_dp1_in>; 3945 }; 3946 }; 3947 3948 port@5 { 3949 reg = <5>; 3950 mdss0_intf5_out: endpoint { 3951 remote-endpoint = <&mdss0_dp3_in>; 3952 }; 3953 }; 3954 3955 port@6 { 3956 reg = <6>; 3957 mdss0_intf6_out: endpoint { 3958 remote-endpoint = <&mdss0_dp2_in>; 3959 }; 3960 }; 3961 }; 3962 3963 mdss0_mdp_opp_table: opp-table { 3964 compatible = "operating-points-v2"; 3965 3966 opp-200000000 { 3967 opp-hz = /bits/ 64 <200000000>; 3968 required-opps = <&rpmhpd_opp_low_svs>; 3969 }; 3970 3971 opp-300000000 { 3972 opp-hz = /bits/ 64 <300000000>; 3973 required-opps = <&rpmhpd_opp_svs>; 3974 }; 3975 3976 opp-375000000 { 3977 opp-hz = /bits/ 64 <375000000>; 3978 required-opps = <&rpmhpd_opp_svs_l1>; 3979 }; 3980 3981 opp-500000000 { 3982 opp-hz = /bits/ 64 <500000000>; 3983 required-opps = <&rpmhpd_opp_nom>; 3984 }; 3985 opp-600000000 { 3986 opp-hz = /bits/ 64 <600000000>; 3987 required-opps = <&rpmhpd_opp_turbo_l1>; 3988 }; 3989 }; 3990 }; 3991 3992 mdss0_dp0: displayport-controller@ae90000 { 3993 compatible = "qcom,sc8280xp-dp"; 3994 reg = <0 0xae90000 0 0x200>, 3995 <0 0xae90200 0 0x200>, 3996 <0 0xae90400 0 0x600>, 3997 <0 0xae91000 0 0x400>, 3998 <0 0xae91400 0 0x400>; 3999 interrupt-parent = <&mdss0>; 4000 interrupts = <12>; 4001 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4002 <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>, 4003 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>, 4004 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 4005 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 4006 clock-names = "core_iface", "core_aux", 4007 "ctrl_link", 4008 "ctrl_link_iface", 4009 "stream_pixel"; 4010 4011 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 4012 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 4013 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4014 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4015 4016 phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; 4017 phy-names = "dp"; 4018 4019 #sound-dai-cells = <0>; 4020 4021 operating-points-v2 = <&mdss0_dp0_opp_table>; 4022 power-domains = <&rpmhpd SC8280XP_MMCX>; 4023 4024 status = "disabled"; 4025 4026 ports { 4027 #address-cells = <1>; 4028 #size-cells = <0>; 4029 4030 port@0 { 4031 reg = <0>; 4032 4033 mdss0_dp0_in: endpoint { 4034 remote-endpoint = <&mdss0_intf0_out>; 4035 }; 4036 }; 4037 4038 port@1 { 4039 reg = <1>; 4040 4041 mdss0_dp0_out: endpoint { 4042 }; 4043 }; 4044 }; 4045 4046 mdss0_dp0_opp_table: opp-table { 4047 compatible = "operating-points-v2"; 4048 4049 opp-160000000 { 4050 opp-hz = /bits/ 64 <160000000>; 4051 required-opps = <&rpmhpd_opp_low_svs>; 4052 }; 4053 4054 opp-270000000 { 4055 opp-hz = /bits/ 64 <270000000>; 4056 required-opps = <&rpmhpd_opp_svs>; 4057 }; 4058 4059 opp-540000000 { 4060 opp-hz = /bits/ 64 <540000000>; 4061 required-opps = <&rpmhpd_opp_svs_l1>; 4062 }; 4063 4064 opp-810000000 { 4065 opp-hz = /bits/ 64 <810000000>; 4066 required-opps = <&rpmhpd_opp_nom>; 4067 }; 4068 }; 4069 }; 4070 4071 mdss0_dp1: displayport-controller@ae98000 { 4072 compatible = "qcom,sc8280xp-dp"; 4073 reg = <0 0xae98000 0 0x200>, 4074 <0 0xae98200 0 0x200>, 4075 <0 0xae98400 0 0x600>, 4076 <0 0xae99000 0 0x400>, 4077 <0 0xae99400 0 0x400>; 4078 interrupt-parent = <&mdss0>; 4079 interrupts = <13>; 4080 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4081 <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>, 4082 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>, 4083 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 4084 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 4085 clock-names = "core_iface", "core_aux", 4086 "ctrl_link", 4087 "ctrl_link_iface", "stream_pixel"; 4088 4089 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 4090 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 4091 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4092 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4093 4094 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 4095 phy-names = "dp"; 4096 4097 #sound-dai-cells = <0>; 4098 4099 operating-points-v2 = <&mdss0_dp1_opp_table>; 4100 power-domains = <&rpmhpd SC8280XP_MMCX>; 4101 4102 status = "disabled"; 4103 4104 ports { 4105 #address-cells = <1>; 4106 #size-cells = <0>; 4107 4108 port@0 { 4109 reg = <0>; 4110 4111 mdss0_dp1_in: endpoint { 4112 remote-endpoint = <&mdss0_intf4_out>; 4113 }; 4114 }; 4115 4116 port@1 { 4117 reg = <1>; 4118 4119 mdss0_dp1_out: endpoint { 4120 }; 4121 }; 4122 }; 4123 4124 mdss0_dp1_opp_table: opp-table { 4125 compatible = "operating-points-v2"; 4126 4127 opp-160000000 { 4128 opp-hz = /bits/ 64 <160000000>; 4129 required-opps = <&rpmhpd_opp_low_svs>; 4130 }; 4131 4132 opp-270000000 { 4133 opp-hz = /bits/ 64 <270000000>; 4134 required-opps = <&rpmhpd_opp_svs>; 4135 }; 4136 4137 opp-540000000 { 4138 opp-hz = /bits/ 64 <540000000>; 4139 required-opps = <&rpmhpd_opp_svs_l1>; 4140 }; 4141 4142 opp-810000000 { 4143 opp-hz = /bits/ 64 <810000000>; 4144 required-opps = <&rpmhpd_opp_nom>; 4145 }; 4146 }; 4147 }; 4148 4149 mdss0_dp2: displayport-controller@ae9a000 { 4150 compatible = "qcom,sc8280xp-dp"; 4151 reg = <0 0xae9a000 0 0x200>, 4152 <0 0xae9a200 0 0x200>, 4153 <0 0xae9a400 0 0x600>, 4154 <0 0xae9b000 0 0x400>, 4155 <0 0xae9b400 0 0x400>; 4156 4157 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4158 <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 4159 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>, 4160 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 4161 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; 4162 clock-names = "core_iface", "core_aux", 4163 "ctrl_link", 4164 "ctrl_link_iface", "stream_pixel"; 4165 interrupt-parent = <&mdss0>; 4166 interrupts = <14>; 4167 phys = <&mdss0_dp2_phy>; 4168 phy-names = "dp"; 4169 power-domains = <&rpmhpd SC8280XP_MMCX>; 4170 4171 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 4172 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 4173 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>; 4174 operating-points-v2 = <&mdss0_dp2_opp_table>; 4175 4176 #sound-dai-cells = <0>; 4177 4178 status = "disabled"; 4179 4180 ports { 4181 #address-cells = <1>; 4182 #size-cells = <0>; 4183 4184 port@0 { 4185 reg = <0>; 4186 mdss0_dp2_in: endpoint { 4187 remote-endpoint = <&mdss0_intf6_out>; 4188 }; 4189 }; 4190 4191 port@1 { 4192 reg = <1>; 4193 }; 4194 }; 4195 4196 mdss0_dp2_opp_table: opp-table { 4197 compatible = "operating-points-v2"; 4198 4199 opp-160000000 { 4200 opp-hz = /bits/ 64 <160000000>; 4201 required-opps = <&rpmhpd_opp_low_svs>; 4202 }; 4203 4204 opp-270000000 { 4205 opp-hz = /bits/ 64 <270000000>; 4206 required-opps = <&rpmhpd_opp_svs>; 4207 }; 4208 4209 opp-540000000 { 4210 opp-hz = /bits/ 64 <540000000>; 4211 required-opps = <&rpmhpd_opp_svs_l1>; 4212 }; 4213 4214 opp-810000000 { 4215 opp-hz = /bits/ 64 <810000000>; 4216 required-opps = <&rpmhpd_opp_nom>; 4217 }; 4218 }; 4219 }; 4220 4221 mdss0_dp3: displayport-controller@aea0000 { 4222 compatible = "qcom,sc8280xp-dp"; 4223 reg = <0 0xaea0000 0 0x200>, 4224 <0 0xaea0200 0 0x200>, 4225 <0 0xaea0400 0 0x600>, 4226 <0 0xaea1000 0 0x400>, 4227 <0 0xaea1400 0 0x400>; 4228 4229 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4230 <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 4231 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>, 4232 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 4233 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 4234 clock-names = "core_iface", "core_aux", 4235 "ctrl_link", 4236 "ctrl_link_iface", "stream_pixel"; 4237 interrupt-parent = <&mdss0>; 4238 interrupts = <15>; 4239 phys = <&mdss0_dp3_phy>; 4240 phy-names = "dp"; 4241 power-domains = <&rpmhpd SC8280XP_MMCX>; 4242 4243 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 4244 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 4245 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>; 4246 operating-points-v2 = <&mdss0_dp3_opp_table>; 4247 4248 #sound-dai-cells = <0>; 4249 4250 status = "disabled"; 4251 4252 ports { 4253 #address-cells = <1>; 4254 #size-cells = <0>; 4255 4256 port@0 { 4257 reg = <0>; 4258 mdss0_dp3_in: endpoint { 4259 remote-endpoint = <&mdss0_intf5_out>; 4260 }; 4261 }; 4262 4263 port@1 { 4264 reg = <1>; 4265 }; 4266 }; 4267 4268 mdss0_dp3_opp_table: opp-table { 4269 compatible = "operating-points-v2"; 4270 4271 opp-160000000 { 4272 opp-hz = /bits/ 64 <160000000>; 4273 required-opps = <&rpmhpd_opp_low_svs>; 4274 }; 4275 4276 opp-270000000 { 4277 opp-hz = /bits/ 64 <270000000>; 4278 required-opps = <&rpmhpd_opp_svs>; 4279 }; 4280 4281 opp-540000000 { 4282 opp-hz = /bits/ 64 <540000000>; 4283 required-opps = <&rpmhpd_opp_svs_l1>; 4284 }; 4285 4286 opp-810000000 { 4287 opp-hz = /bits/ 64 <810000000>; 4288 required-opps = <&rpmhpd_opp_nom>; 4289 }; 4290 }; 4291 }; 4292 }; 4293 4294 mdss0_dp2_phy: phy@aec2a00 { 4295 compatible = "qcom,sc8280xp-dp-phy"; 4296 reg = <0 0x0aec2a00 0 0x19c>, 4297 <0 0x0aec2200 0 0xec>, 4298 <0 0x0aec2600 0 0xec>, 4299 <0 0x0aec2000 0 0x1c8>; 4300 4301 clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 4302 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 4303 clock-names = "aux", "cfg_ahb"; 4304 power-domains = <&rpmhpd SC8280XP_MX>; 4305 4306 #clock-cells = <1>; 4307 #phy-cells = <0>; 4308 4309 status = "disabled"; 4310 }; 4311 4312 mdss0_dp3_phy: phy@aec5a00 { 4313 compatible = "qcom,sc8280xp-dp-phy"; 4314 reg = <0 0x0aec5a00 0 0x19c>, 4315 <0 0x0aec5200 0 0xec>, 4316 <0 0x0aec5600 0 0xec>, 4317 <0 0x0aec5000 0 0x1c8>; 4318 4319 clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 4320 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 4321 clock-names = "aux", "cfg_ahb"; 4322 power-domains = <&rpmhpd SC8280XP_MX>; 4323 4324 #clock-cells = <1>; 4325 #phy-cells = <0>; 4326 4327 status = "disabled"; 4328 }; 4329 4330 dispcc0: clock-controller@af00000 { 4331 compatible = "qcom,sc8280xp-dispcc0"; 4332 reg = <0 0x0af00000 0 0x20000>; 4333 4334 clocks = <&gcc GCC_DISP_AHB_CLK>, 4335 <&rpmhcc RPMH_CXO_CLK>, 4336 <&sleep_clk>, 4337 <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4338 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4339 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4340 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4341 <&mdss0_dp2_phy 0>, 4342 <&mdss0_dp2_phy 1>, 4343 <&mdss0_dp3_phy 0>, 4344 <&mdss0_dp3_phy 1>, 4345 <0>, 4346 <0>, 4347 <0>, 4348 <0>; 4349 power-domains = <&rpmhpd SC8280XP_MMCX>; 4350 4351 #clock-cells = <1>; 4352 #power-domain-cells = <1>; 4353 #reset-cells = <1>; 4354 4355 status = "disabled"; 4356 }; 4357 4358 pdc: interrupt-controller@b220000 { 4359 compatible = "qcom,sc8280xp-pdc", "qcom,pdc"; 4360 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 4361 qcom,pdc-ranges = <0 480 40>, 4362 <40 140 14>, 4363 <54 263 1>, 4364 <55 306 4>, 4365 <59 312 3>, 4366 <62 374 2>, 4367 <64 434 2>, 4368 <66 438 3>, 4369 <69 86 1>, 4370 <70 520 54>, 4371 <124 609 28>, 4372 <159 638 1>, 4373 <160 720 8>, 4374 <168 801 1>, 4375 <169 728 30>, 4376 <199 416 2>, 4377 <201 449 1>, 4378 <202 89 1>, 4379 <203 451 1>, 4380 <204 462 1>, 4381 <205 264 1>, 4382 <206 579 1>, 4383 <207 653 1>, 4384 <208 656 1>, 4385 <209 659 1>, 4386 <210 122 1>, 4387 <211 699 1>, 4388 <212 705 1>, 4389 <213 450 1>, 4390 <214 643 1>, 4391 <216 646 5>, 4392 <221 390 5>, 4393 <226 700 3>, 4394 <229 240 3>, 4395 <232 269 1>, 4396 <233 377 1>, 4397 <234 372 1>, 4398 <235 138 1>, 4399 <236 857 1>, 4400 <237 860 1>, 4401 <238 137 1>, 4402 <239 668 1>, 4403 <240 366 1>, 4404 <241 949 1>, 4405 <242 815 5>, 4406 <247 769 1>, 4407 <248 768 1>, 4408 <249 663 1>, 4409 <250 799 2>, 4410 <252 798 1>, 4411 <253 765 1>, 4412 <254 763 1>, 4413 <255 454 1>, 4414 <258 139 1>, 4415 <259 786 2>, 4416 <261 370 2>, 4417 <263 158 2>; 4418 #interrupt-cells = <2>; 4419 interrupt-parent = <&intc>; 4420 interrupt-controller; 4421 }; 4422 4423 tsens2: thermal-sensor@c251000 { 4424 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 4425 reg = <0 0x0c251000 0 0x1ff>, 4426 <0 0x0c224000 0 0x8>; 4427 #qcom,sensors = <11>; 4428 interrupts-extended = <&pdc 122 IRQ_TYPE_LEVEL_HIGH>, 4429 <&pdc 124 IRQ_TYPE_LEVEL_HIGH>; 4430 interrupt-names = "uplow", "critical"; 4431 #thermal-sensor-cells = <1>; 4432 }; 4433 4434 tsens3: thermal-sensor@c252000 { 4435 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 4436 reg = <0 0x0c252000 0 0x1ff>, 4437 <0 0x0c225000 0 0x8>; 4438 #qcom,sensors = <5>; 4439 interrupts-extended = <&pdc 123 IRQ_TYPE_LEVEL_HIGH>, 4440 <&pdc 125 IRQ_TYPE_LEVEL_HIGH>; 4441 interrupt-names = "uplow", "critical"; 4442 #thermal-sensor-cells = <1>; 4443 }; 4444 4445 tsens0: thermal-sensor@c263000 { 4446 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 4447 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4448 <0 0x0c222000 0 0x8>; /* SROT */ 4449 #qcom,sensors = <14>; 4450 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 4451 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 4452 interrupt-names = "uplow", "critical"; 4453 #thermal-sensor-cells = <1>; 4454 }; 4455 4456 tsens1: thermal-sensor@c265000 { 4457 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 4458 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4459 <0 0x0c223000 0 0x8>; /* SROT */ 4460 #qcom,sensors = <16>; 4461 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 4462 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 4463 interrupt-names = "uplow", "critical"; 4464 #thermal-sensor-cells = <1>; 4465 }; 4466 4467 aoss_qmp: power-management@c300000 { 4468 compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp"; 4469 reg = <0 0x0c300000 0 0x400>; 4470 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; 4471 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 4472 4473 #clock-cells = <0>; 4474 }; 4475 4476 sram@c3f0000 { 4477 compatible = "qcom,rpmh-stats"; 4478 reg = <0 0x0c3f0000 0 0x400>; 4479 qcom,qmp = <&aoss_qmp>; 4480 }; 4481 4482 spmi_bus: spmi@c440000 { 4483 compatible = "qcom,spmi-pmic-arb"; 4484 reg = <0 0x0c440000 0 0x1100>, 4485 <0 0x0c600000 0 0x2000000>, 4486 <0 0x0e600000 0 0x100000>, 4487 <0 0x0e700000 0 0xa0000>, 4488 <0 0x0c40a000 0 0x26000>; 4489 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4490 interrupt-names = "periph_irq"; 4491 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4492 qcom,ee = <0>; 4493 qcom,channel = <0>; 4494 #address-cells = <2>; 4495 #size-cells = <0>; 4496 interrupt-controller; 4497 #interrupt-cells = <4>; 4498 }; 4499 4500 tlmm: pinctrl@f100000 { 4501 compatible = "qcom,sc8280xp-tlmm"; 4502 reg = <0 0x0f100000 0 0x300000>; 4503 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4504 gpio-controller; 4505 #gpio-cells = <2>; 4506 interrupt-controller; 4507 #interrupt-cells = <2>; 4508 gpio-ranges = <&tlmm 0 0 230>; 4509 wakeup-parent = <&pdc>; 4510 4511 cci0_default: cci0-default-state { 4512 cci0_i2c0_default: cci0-i2c0-default-pins { 4513 /* cci_i2c_sda0, cci_i2c_scl0 */ 4514 pins = "gpio113", "gpio114"; 4515 function = "cci_i2c"; 4516 drive-strength = <2>; 4517 bias-pull-up; 4518 }; 4519 4520 cci0_i2c1_default: cci0-i2c1-default-pins { 4521 /* cci_i2c_sda1, cci_i2c_scl1 */ 4522 pins = "gpio115", "gpio116"; 4523 function = "cci_i2c"; 4524 drive-strength = <2>; 4525 bias-pull-up; 4526 }; 4527 }; 4528 4529 cci0_sleep: cci0-sleep-state { 4530 cci0_i2c0_sleep: cci0-i2c0-sleep-pins { 4531 /* cci_i2c_sda0, cci_i2c_scl0 */ 4532 pins = "gpio113", "gpio114"; 4533 function = "cci_i2c"; 4534 drive-strength = <2>; 4535 bias-pull-down; 4536 }; 4537 4538 cci0_i2c1_sleep: cci0-i2c1-sleep-pins { 4539 /* cci_i2c_sda1, cci_i2c_scl1 */ 4540 pins = "gpio115", "gpio116"; 4541 function = "cci_i2c"; 4542 drive-strength = <2>; 4543 bias-pull-down; 4544 }; 4545 }; 4546 4547 cci1_default: cci1-default-state { 4548 cci1_i2c0_default: cci1-i2c0-default-pins { 4549 /* cci_i2c_sda2, cci_i2c_scl2 */ 4550 pins = "gpio10","gpio11"; 4551 function = "cci_i2c"; 4552 drive-strength = <2>; 4553 bias-pull-up; 4554 }; 4555 4556 cci1_i2c1_default: cci1-i2c1-default-pins { 4557 /* cci_i2c_sda3, cci_i2c_scl3 */ 4558 pins = "gpio123","gpio124"; 4559 function = "cci_i2c"; 4560 drive-strength = <2>; 4561 bias-pull-up; 4562 }; 4563 }; 4564 4565 cci1_sleep: cci1-sleep-state { 4566 cci1_i2c0_sleep: cci1-i2c0-sleep-pins { 4567 /* cci_i2c_sda2, cci_i2c_scl2 */ 4568 pins = "gpio10","gpio11"; 4569 function = "cci_i2c"; 4570 drive-strength = <2>; 4571 bias-pull-down; 4572 }; 4573 4574 cci1_i2c1_sleep: cci1-i2c1-sleep-pins { 4575 /* cci_i2c_sda3, cci_i2c_scl3 */ 4576 pins = "gpio123","gpio124"; 4577 function = "cci_i2c"; 4578 drive-strength = <2>; 4579 bias-pull-down; 4580 }; 4581 }; 4582 4583 cci2_default: cci2-default-state { 4584 cci2_i2c0_default: cci2-i2c0-default-pins { 4585 /* cci_i2c_sda4, cci_i2c_scl4 */ 4586 pins = "gpio117","gpio118"; 4587 function = "cci_i2c"; 4588 drive-strength = <2>; 4589 bias-pull-up; 4590 }; 4591 4592 cci2_i2c1_default: cci2-i2c1-default-pins { 4593 /* cci_i2c_sda5, cci_i2c_scl5 */ 4594 pins = "gpio12","gpio13"; 4595 function = "cci_i2c"; 4596 drive-strength = <2>; 4597 bias-pull-up; 4598 }; 4599 }; 4600 4601 cci2_sleep: cci2-sleep-state { 4602 cci2_i2c0_sleep: cci2-i2c0-sleep-pins { 4603 /* cci_i2c_sda4, cci_i2c_scl4 */ 4604 pins = "gpio117","gpio118"; 4605 function = "cci_i2c"; 4606 drive-strength = <2>; 4607 bias-pull-down; 4608 }; 4609 4610 cci2_i2c1_sleep: cci2-i2c1-sleep-pins { 4611 /* cci_i2c_sda5, cci_i2c_scl5 */ 4612 pins = "gpio12","gpio13"; 4613 function = "cci_i2c"; 4614 drive-strength = <2>; 4615 bias-pull-down; 4616 }; 4617 }; 4618 4619 cci3_default: cci3-default-state { 4620 cci3_i2c0_default: cci3-i2c0-default-pins { 4621 /* cci_i2c_sda6, cci_i2c_scl6 */ 4622 pins = "gpio145","gpio146"; 4623 function = "cci_i2c"; 4624 drive-strength = <2>; 4625 bias-pull-up; 4626 }; 4627 4628 cci3_i2c1_default: cci3-i2c1-default-pins { 4629 /* cci_i2c_sda7, cci_i2c_scl7 */ 4630 pins = "gpio164","gpio165"; 4631 function = "cci_i2c"; 4632 drive-strength = <2>; 4633 bias-pull-up; 4634 }; 4635 }; 4636 4637 cci3_sleep: cci3-sleep-state { 4638 cci3_i2c0_sleep: cci3-i2c0-sleep-pins { 4639 /* cci_i2c_sda6, cci_i2c_scl6 */ 4640 pins = "gpio145","gpio146"; 4641 function = "cci_i2c"; 4642 drive-strength = <2>; 4643 bias-pull-down; 4644 }; 4645 4646 cci3_i2c1_sleep: cci3-i2c1-sleep-pins { 4647 /* cci_i2c_sda7, cci_i2c_scl7 */ 4648 pins = "gpio164","gpio165"; 4649 function = "cci_i2c"; 4650 drive-strength = <2>; 4651 bias-pull-down; 4652 }; 4653 }; 4654 }; 4655 4656 apps_smmu: iommu@15000000 { 4657 compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500"; 4658 reg = <0 0x15000000 0 0x100000>; 4659 #iommu-cells = <2>; 4660 #global-interrupts = <2>; 4661 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 4662 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4663 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4664 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4665 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4666 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4667 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4668 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4669 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4670 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4671 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4672 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4673 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4674 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4675 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4676 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4677 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4678 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4679 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4680 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4681 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4682 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4683 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4684 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4685 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4686 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4687 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4688 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4689 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4690 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4691 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4692 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4693 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4694 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4695 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4696 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4697 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4698 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4699 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4700 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4701 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4702 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4703 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4704 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4705 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4706 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4707 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4708 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4709 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4710 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4711 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4712 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4713 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4714 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4715 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4716 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4717 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4718 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4719 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4720 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4721 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4722 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4723 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4724 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4725 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4726 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4727 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4728 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4729 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4730 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4731 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4732 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4733 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4734 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4735 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4736 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 4737 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4738 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4739 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 4740 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4741 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 4742 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4743 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4744 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 4745 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 4746 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 4747 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 4748 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 4749 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 4750 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 4751 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 4752 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 4753 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 4754 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 4755 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 4756 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 4757 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4758 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 4759 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 4760 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 4761 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 4762 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 4763 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 4764 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 4765 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 4766 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 4767 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 4768 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 4769 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 4770 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 4771 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 4772 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 4773 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 4774 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 4775 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 4776 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 4777 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 4778 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 4779 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 4780 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 4781 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 4782 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 4783 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 4784 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 4785 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 4786 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 4787 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 4788 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 4789 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>, 4790 <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>; 4791 }; 4792 4793 intc: interrupt-controller@17a00000 { 4794 compatible = "arm,gic-v3"; 4795 interrupt-controller; 4796 #interrupt-cells = <3>; 4797 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4798 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4799 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4800 #redistributor-regions = <1>; 4801 redistributor-stride = <0 0x20000>; 4802 4803 #address-cells = <2>; 4804 #size-cells = <2>; 4805 ranges; 4806 4807 msi-controller@17a40000 { 4808 compatible = "arm,gic-v3-its"; 4809 reg = <0 0x17a40000 0 0x20000>; 4810 msi-controller; 4811 #msi-cells = <1>; 4812 }; 4813 }; 4814 4815 watchdog@17c10000 { 4816 compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt"; 4817 reg = <0 0x17c10000 0 0x1000>; 4818 clocks = <&sleep_clk>; 4819 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 4820 }; 4821 4822 timer@17c20000 { 4823 compatible = "arm,armv7-timer-mem"; 4824 reg = <0x0 0x17c20000 0x0 0x1000>; 4825 #address-cells = <1>; 4826 #size-cells = <1>; 4827 ranges = <0x0 0x0 0x0 0x20000000>; 4828 4829 frame@17c21000 { 4830 frame-number = <0>; 4831 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4832 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4833 reg = <0x17c21000 0x1000>, 4834 <0x17c22000 0x1000>; 4835 }; 4836 4837 frame@17c23000 { 4838 frame-number = <1>; 4839 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4840 reg = <0x17c23000 0x1000>; 4841 status = "disabled"; 4842 }; 4843 4844 frame@17c25000 { 4845 frame-number = <2>; 4846 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4847 reg = <0x17c25000 0x1000>; 4848 status = "disabled"; 4849 }; 4850 4851 frame@17c27000 { 4852 frame-number = <3>; 4853 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4854 reg = <0x17c26000 0x1000>; 4855 status = "disabled"; 4856 }; 4857 4858 frame@17c29000 { 4859 frame-number = <4>; 4860 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4861 reg = <0x17c29000 0x1000>; 4862 status = "disabled"; 4863 }; 4864 4865 frame@17c2b000 { 4866 frame-number = <5>; 4867 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4868 reg = <0x17c2b000 0x1000>; 4869 status = "disabled"; 4870 }; 4871 4872 frame@17c2d000 { 4873 frame-number = <6>; 4874 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4875 reg = <0x17c2d000 0x1000>; 4876 status = "disabled"; 4877 }; 4878 }; 4879 4880 apps_rsc: rsc@18200000 { 4881 compatible = "qcom,rpmh-rsc"; 4882 reg = <0x0 0x18200000 0x0 0x10000>, 4883 <0x0 0x18210000 0x0 0x10000>, 4884 <0x0 0x18220000 0x0 0x10000>; 4885 reg-names = "drv-0", "drv-1", "drv-2"; 4886 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4887 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4888 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4889 qcom,tcs-offset = <0xd00>; 4890 qcom,drv-id = <2>; 4891 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 4892 <WAKE_TCS 3>, <CONTROL_TCS 1>; 4893 label = "apps_rsc"; 4894 power-domains = <&CLUSTER_PD>; 4895 4896 apps_bcm_voter: bcm-voter { 4897 compatible = "qcom,bcm-voter"; 4898 }; 4899 4900 rpmhcc: clock-controller { 4901 compatible = "qcom,sc8280xp-rpmh-clk"; 4902 #clock-cells = <1>; 4903 clock-names = "xo"; 4904 clocks = <&xo_board_clk>; 4905 }; 4906 4907 rpmhpd: power-controller { 4908 compatible = "qcom,sc8280xp-rpmhpd"; 4909 #power-domain-cells = <1>; 4910 operating-points-v2 = <&rpmhpd_opp_table>; 4911 4912 rpmhpd_opp_table: opp-table { 4913 compatible = "operating-points-v2"; 4914 4915 rpmhpd_opp_ret: opp1 { 4916 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4917 }; 4918 4919 rpmhpd_opp_min_svs: opp2 { 4920 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4921 }; 4922 4923 rpmhpd_opp_low_svs: opp3 { 4924 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4925 }; 4926 4927 rpmhpd_opp_svs: opp4 { 4928 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4929 }; 4930 4931 rpmhpd_opp_svs_l1: opp5 { 4932 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4933 }; 4934 4935 rpmhpd_opp_nom: opp6 { 4936 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4937 }; 4938 4939 rpmhpd_opp_nom_l1: opp7 { 4940 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4941 }; 4942 4943 rpmhpd_opp_nom_l2: opp8 { 4944 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4945 }; 4946 4947 rpmhpd_opp_turbo: opp9 { 4948 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4949 }; 4950 4951 rpmhpd_opp_turbo_l1: opp10 { 4952 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4953 }; 4954 }; 4955 }; 4956 }; 4957 4958 epss_l3: interconnect@18590000 { 4959 compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3"; 4960 reg = <0 0x18590000 0 0x1000>; 4961 4962 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4963 clock-names = "xo", "alternate"; 4964 4965 #interconnect-cells = <1>; 4966 }; 4967 4968 cpufreq_hw: cpufreq@18591000 { 4969 compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss"; 4970 reg = <0 0x18591000 0 0x1000>, 4971 <0 0x18592000 0 0x1000>; 4972 reg-names = "freq-domain0", "freq-domain1"; 4973 4974 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 4975 clock-names = "xo", "alternate"; 4976 4977 #freq-domain-cells = <1>; 4978 #clock-cells = <1>; 4979 }; 4980 4981 remoteproc_nsp0: remoteproc@1b300000 { 4982 compatible = "qcom,sc8280xp-nsp0-pas"; 4983 reg = <0 0x1b300000 0 0x100>; 4984 4985 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 4986 <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>, 4987 <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>, 4988 <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>, 4989 <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>; 4990 interrupt-names = "wdog", "fatal", "ready", 4991 "handover", "stop-ack"; 4992 4993 clocks = <&rpmhcc RPMH_CXO_CLK>; 4994 clock-names = "xo"; 4995 4996 power-domains = <&rpmhpd SC8280XP_NSP>; 4997 power-domain-names = "nsp"; 4998 4999 memory-region = <&pil_nsp0_mem>; 5000 5001 qcom,smem-states = <&smp2p_nsp0_out 0>; 5002 qcom,smem-state-names = "stop"; 5003 5004 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 5005 5006 status = "disabled"; 5007 5008 glink-edge { 5009 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 5010 IPCC_MPROC_SIGNAL_GLINK_QMP 5011 IRQ_TYPE_EDGE_RISING>; 5012 mboxes = <&ipcc IPCC_CLIENT_CDSP 5013 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5014 5015 label = "nsp0"; 5016 qcom,remote-pid = <5>; 5017 5018 fastrpc { 5019 compatible = "qcom,fastrpc"; 5020 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5021 label = "cdsp"; 5022 #address-cells = <1>; 5023 #size-cells = <0>; 5024 5025 compute-cb@1 { 5026 compatible = "qcom,fastrpc-compute-cb"; 5027 reg = <1>; 5028 iommus = <&apps_smmu 0x3181 0x0420>; 5029 }; 5030 5031 compute-cb@2 { 5032 compatible = "qcom,fastrpc-compute-cb"; 5033 reg = <2>; 5034 iommus = <&apps_smmu 0x3182 0x0420>; 5035 }; 5036 5037 compute-cb@3 { 5038 compatible = "qcom,fastrpc-compute-cb"; 5039 reg = <3>; 5040 iommus = <&apps_smmu 0x3183 0x0420>; 5041 }; 5042 5043 compute-cb@4 { 5044 compatible = "qcom,fastrpc-compute-cb"; 5045 reg = <4>; 5046 iommus = <&apps_smmu 0x3184 0x0420>; 5047 }; 5048 5049 compute-cb@5 { 5050 compatible = "qcom,fastrpc-compute-cb"; 5051 reg = <5>; 5052 iommus = <&apps_smmu 0x3185 0x0420>; 5053 }; 5054 5055 compute-cb@6 { 5056 compatible = "qcom,fastrpc-compute-cb"; 5057 reg = <6>; 5058 iommus = <&apps_smmu 0x3186 0x0420>; 5059 }; 5060 5061 compute-cb@7 { 5062 compatible = "qcom,fastrpc-compute-cb"; 5063 reg = <7>; 5064 iommus = <&apps_smmu 0x3187 0x0420>; 5065 }; 5066 5067 compute-cb@8 { 5068 compatible = "qcom,fastrpc-compute-cb"; 5069 reg = <8>; 5070 iommus = <&apps_smmu 0x3188 0x0420>; 5071 }; 5072 5073 compute-cb@9 { 5074 compatible = "qcom,fastrpc-compute-cb"; 5075 reg = <9>; 5076 iommus = <&apps_smmu 0x318b 0x0420>; 5077 }; 5078 5079 compute-cb@10 { 5080 compatible = "qcom,fastrpc-compute-cb"; 5081 reg = <10>; 5082 iommus = <&apps_smmu 0x318b 0x0420>; 5083 }; 5084 5085 compute-cb@11 { 5086 compatible = "qcom,fastrpc-compute-cb"; 5087 reg = <11>; 5088 iommus = <&apps_smmu 0x318c 0x0420>; 5089 }; 5090 5091 compute-cb@12 { 5092 compatible = "qcom,fastrpc-compute-cb"; 5093 reg = <12>; 5094 iommus = <&apps_smmu 0x318d 0x0420>; 5095 }; 5096 5097 compute-cb@13 { 5098 compatible = "qcom,fastrpc-compute-cb"; 5099 reg = <13>; 5100 iommus = <&apps_smmu 0x318e 0x0420>; 5101 }; 5102 5103 compute-cb@14 { 5104 compatible = "qcom,fastrpc-compute-cb"; 5105 reg = <14>; 5106 iommus = <&apps_smmu 0x318f 0x0420>; 5107 }; 5108 }; 5109 }; 5110 }; 5111 5112 remoteproc_nsp1: remoteproc@21300000 { 5113 compatible = "qcom,sc8280xp-nsp1-pas"; 5114 reg = <0 0x21300000 0 0x100>; 5115 5116 interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_EDGE_RISING>, 5117 <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>, 5118 <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>, 5119 <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>, 5120 <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>; 5121 interrupt-names = "wdog", "fatal", "ready", 5122 "handover", "stop-ack"; 5123 5124 clocks = <&rpmhcc RPMH_CXO_CLK>; 5125 clock-names = "xo"; 5126 5127 power-domains = <&rpmhpd SC8280XP_NSP>; 5128 power-domain-names = "nsp"; 5129 5130 memory-region = <&pil_nsp1_mem>; 5131 5132 qcom,smem-states = <&smp2p_nsp1_out 0>; 5133 qcom,smem-state-names = "stop"; 5134 5135 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>; 5136 5137 status = "disabled"; 5138 5139 glink-edge { 5140 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 5141 IPCC_MPROC_SIGNAL_GLINK_QMP 5142 IRQ_TYPE_EDGE_RISING>; 5143 mboxes = <&ipcc IPCC_CLIENT_NSP1 5144 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5145 5146 label = "nsp1"; 5147 qcom,remote-pid = <12>; 5148 }; 5149 }; 5150 5151 mdss1: display-subsystem@22000000 { 5152 compatible = "qcom,sc8280xp-mdss"; 5153 reg = <0 0x22000000 0 0x1000>; 5154 reg-names = "mdss"; 5155 5156 clocks = <&gcc GCC_DISP_AHB_CLK>, 5157 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 5158 <&dispcc1 DISP_CC_MDSS_MDP_CLK>; 5159 clock-names = "iface", 5160 "ahb", 5161 "core"; 5162 interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>, 5163 <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>; 5164 interconnect-names = "mdp0-mem", "mdp1-mem"; 5165 interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; 5166 5167 iommus = <&apps_smmu 0x1800 0x402>; 5168 power-domains = <&dispcc1 MDSS_GDSC>; 5169 resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>; 5170 5171 interrupt-controller; 5172 #interrupt-cells = <1>; 5173 #address-cells = <2>; 5174 #size-cells = <2>; 5175 ranges; 5176 5177 status = "disabled"; 5178 5179 mdss1_mdp: display-controller@22001000 { 5180 compatible = "qcom,sc8280xp-dpu"; 5181 reg = <0 0x22001000 0 0x8f000>, 5182 <0 0x220b0000 0 0x2008>; 5183 reg-names = "mdp", "vbif"; 5184 5185 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 5186 <&gcc GCC_DISP_SF_AXI_CLK>, 5187 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 5188 <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>, 5189 <&dispcc1 DISP_CC_MDSS_MDP_CLK>, 5190 <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 5191 clock-names = "bus", 5192 "nrt_bus", 5193 "iface", 5194 "lut", 5195 "core", 5196 "vsync"; 5197 interrupt-parent = <&mdss1>; 5198 interrupts = <0>; 5199 power-domains = <&rpmhpd SC8280XP_MMCX>; 5200 5201 assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 5202 assigned-clock-rates = <19200000>; 5203 operating-points-v2 = <&mdss1_mdp_opp_table>; 5204 5205 ports { 5206 #address-cells = <1>; 5207 #size-cells = <0>; 5208 5209 port@0 { 5210 reg = <0>; 5211 mdss1_intf0_out: endpoint { 5212 remote-endpoint = <&mdss1_dp0_in>; 5213 }; 5214 }; 5215 5216 port@4 { 5217 reg = <4>; 5218 mdss1_intf4_out: endpoint { 5219 remote-endpoint = <&mdss1_dp1_in>; 5220 }; 5221 }; 5222 5223 port@5 { 5224 reg = <5>; 5225 mdss1_intf5_out: endpoint { 5226 remote-endpoint = <&mdss1_dp3_in>; 5227 }; 5228 }; 5229 5230 port@6 { 5231 reg = <6>; 5232 mdss1_intf6_out: endpoint { 5233 remote-endpoint = <&mdss1_dp2_in>; 5234 }; 5235 }; 5236 }; 5237 5238 mdss1_mdp_opp_table: opp-table { 5239 compatible = "operating-points-v2"; 5240 5241 opp-200000000 { 5242 opp-hz = /bits/ 64 <200000000>; 5243 required-opps = <&rpmhpd_opp_low_svs>; 5244 }; 5245 5246 opp-300000000 { 5247 opp-hz = /bits/ 64 <300000000>; 5248 required-opps = <&rpmhpd_opp_svs>; 5249 }; 5250 5251 opp-375000000 { 5252 opp-hz = /bits/ 64 <375000000>; 5253 required-opps = <&rpmhpd_opp_svs_l1>; 5254 }; 5255 5256 opp-500000000 { 5257 opp-hz = /bits/ 64 <500000000>; 5258 required-opps = <&rpmhpd_opp_nom>; 5259 }; 5260 opp-600000000 { 5261 opp-hz = /bits/ 64 <600000000>; 5262 required-opps = <&rpmhpd_opp_turbo_l1>; 5263 }; 5264 }; 5265 }; 5266 5267 mdss1_dp0: displayport-controller@22090000 { 5268 compatible = "qcom,sc8280xp-dp"; 5269 reg = <0 0x22090000 0 0x200>, 5270 <0 0x22090200 0 0x200>, 5271 <0 0x22090400 0 0x600>, 5272 <0 0x22091000 0 0x400>, 5273 <0 0x22091400 0 0x400>; 5274 5275 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 5276 <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 5277 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>, 5278 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 5279 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 5280 clock-names = "core_iface", "core_aux", 5281 "ctrl_link", 5282 "ctrl_link_iface", "stream_pixel"; 5283 interrupt-parent = <&mdss1>; 5284 interrupts = <12>; 5285 phys = <&mdss1_dp0_phy>; 5286 phy-names = "dp"; 5287 power-domains = <&rpmhpd SC8280XP_MMCX>; 5288 5289 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 5290 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 5291 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>; 5292 operating-points-v2 = <&mdss1_dp0_opp_table>; 5293 5294 #sound-dai-cells = <0>; 5295 5296 status = "disabled"; 5297 5298 ports { 5299 #address-cells = <1>; 5300 #size-cells = <0>; 5301 5302 port@0 { 5303 reg = <0>; 5304 mdss1_dp0_in: endpoint { 5305 remote-endpoint = <&mdss1_intf0_out>; 5306 }; 5307 }; 5308 5309 port@1 { 5310 reg = <1>; 5311 }; 5312 }; 5313 5314 mdss1_dp0_opp_table: opp-table { 5315 compatible = "operating-points-v2"; 5316 5317 opp-160000000 { 5318 opp-hz = /bits/ 64 <160000000>; 5319 required-opps = <&rpmhpd_opp_low_svs>; 5320 }; 5321 5322 opp-270000000 { 5323 opp-hz = /bits/ 64 <270000000>; 5324 required-opps = <&rpmhpd_opp_svs>; 5325 }; 5326 5327 opp-540000000 { 5328 opp-hz = /bits/ 64 <540000000>; 5329 required-opps = <&rpmhpd_opp_svs_l1>; 5330 }; 5331 5332 opp-810000000 { 5333 opp-hz = /bits/ 64 <810000000>; 5334 required-opps = <&rpmhpd_opp_nom>; 5335 }; 5336 }; 5337 }; 5338 5339 mdss1_dp1: displayport-controller@22098000 { 5340 compatible = "qcom,sc8280xp-dp"; 5341 reg = <0 0x22098000 0 0x200>, 5342 <0 0x22098200 0 0x200>, 5343 <0 0x22098400 0 0x600>, 5344 <0 0x22099000 0 0x400>, 5345 <0 0x22099400 0 0x400>; 5346 5347 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 5348 <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 5349 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>, 5350 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 5351 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 5352 clock-names = "core_iface", "core_aux", 5353 "ctrl_link", 5354 "ctrl_link_iface", "stream_pixel"; 5355 interrupt-parent = <&mdss1>; 5356 interrupts = <13>; 5357 phys = <&mdss1_dp1_phy>; 5358 phy-names = "dp"; 5359 power-domains = <&rpmhpd SC8280XP_MMCX>; 5360 5361 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 5362 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 5363 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>; 5364 operating-points-v2 = <&mdss1_dp1_opp_table>; 5365 5366 #sound-dai-cells = <0>; 5367 5368 status = "disabled"; 5369 5370 ports { 5371 #address-cells = <1>; 5372 #size-cells = <0>; 5373 5374 port@0 { 5375 reg = <0>; 5376 mdss1_dp1_in: endpoint { 5377 remote-endpoint = <&mdss1_intf4_out>; 5378 }; 5379 }; 5380 5381 port@1 { 5382 reg = <1>; 5383 }; 5384 }; 5385 5386 mdss1_dp1_opp_table: opp-table { 5387 compatible = "operating-points-v2"; 5388 5389 opp-160000000 { 5390 opp-hz = /bits/ 64 <160000000>; 5391 required-opps = <&rpmhpd_opp_low_svs>; 5392 }; 5393 5394 opp-270000000 { 5395 opp-hz = /bits/ 64 <270000000>; 5396 required-opps = <&rpmhpd_opp_svs>; 5397 }; 5398 5399 opp-540000000 { 5400 opp-hz = /bits/ 64 <540000000>; 5401 required-opps = <&rpmhpd_opp_svs_l1>; 5402 }; 5403 5404 opp-810000000 { 5405 opp-hz = /bits/ 64 <810000000>; 5406 required-opps = <&rpmhpd_opp_nom>; 5407 }; 5408 }; 5409 }; 5410 5411 mdss1_dp2: displayport-controller@2209a000 { 5412 compatible = "qcom,sc8280xp-dp"; 5413 reg = <0 0x2209a000 0 0x200>, 5414 <0 0x2209a200 0 0x200>, 5415 <0 0x2209a400 0 0x600>, 5416 <0 0x2209b000 0 0x400>, 5417 <0 0x2209b400 0 0x400>; 5418 5419 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 5420 <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 5421 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>, 5422 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 5423 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; 5424 clock-names = "core_iface", "core_aux", 5425 "ctrl_link", 5426 "ctrl_link_iface", "stream_pixel"; 5427 interrupt-parent = <&mdss1>; 5428 interrupts = <14>; 5429 phys = <&mdss1_dp2_phy>; 5430 phy-names = "dp"; 5431 power-domains = <&rpmhpd SC8280XP_MMCX>; 5432 5433 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 5434 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 5435 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>; 5436 operating-points-v2 = <&mdss1_dp2_opp_table>; 5437 5438 #sound-dai-cells = <0>; 5439 5440 status = "disabled"; 5441 5442 ports { 5443 #address-cells = <1>; 5444 #size-cells = <0>; 5445 5446 port@0 { 5447 reg = <0>; 5448 mdss1_dp2_in: endpoint { 5449 remote-endpoint = <&mdss1_intf6_out>; 5450 }; 5451 }; 5452 5453 port@1 { 5454 reg = <1>; 5455 }; 5456 }; 5457 5458 mdss1_dp2_opp_table: opp-table { 5459 compatible = "operating-points-v2"; 5460 5461 opp-160000000 { 5462 opp-hz = /bits/ 64 <160000000>; 5463 required-opps = <&rpmhpd_opp_low_svs>; 5464 }; 5465 5466 opp-270000000 { 5467 opp-hz = /bits/ 64 <270000000>; 5468 required-opps = <&rpmhpd_opp_svs>; 5469 }; 5470 5471 opp-540000000 { 5472 opp-hz = /bits/ 64 <540000000>; 5473 required-opps = <&rpmhpd_opp_svs_l1>; 5474 }; 5475 5476 opp-810000000 { 5477 opp-hz = /bits/ 64 <810000000>; 5478 required-opps = <&rpmhpd_opp_nom>; 5479 }; 5480 }; 5481 }; 5482 5483 mdss1_dp3: displayport-controller@220a0000 { 5484 compatible = "qcom,sc8280xp-dp"; 5485 reg = <0 0x220a0000 0 0x200>, 5486 <0 0x220a0200 0 0x200>, 5487 <0 0x220a0400 0 0x600>, 5488 <0 0x220a1000 0 0x400>, 5489 <0 0x220a1400 0 0x400>; 5490 5491 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 5492 <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 5493 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK>, 5494 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 5495 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 5496 clock-names = "core_iface", "core_aux", 5497 "ctrl_link", 5498 "ctrl_link_iface", "stream_pixel"; 5499 interrupt-parent = <&mdss1>; 5500 interrupts = <15>; 5501 phys = <&mdss1_dp3_phy>; 5502 phy-names = "dp"; 5503 power-domains = <&rpmhpd SC8280XP_MMCX>; 5504 5505 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 5506 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 5507 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>; 5508 operating-points-v2 = <&mdss1_dp3_opp_table>; 5509 5510 #sound-dai-cells = <0>; 5511 5512 status = "disabled"; 5513 5514 ports { 5515 #address-cells = <1>; 5516 #size-cells = <0>; 5517 5518 port@0 { 5519 reg = <0>; 5520 mdss1_dp3_in: endpoint { 5521 remote-endpoint = <&mdss1_intf5_out>; 5522 }; 5523 }; 5524 5525 port@1 { 5526 reg = <1>; 5527 }; 5528 }; 5529 5530 mdss1_dp3_opp_table: opp-table { 5531 compatible = "operating-points-v2"; 5532 5533 opp-160000000 { 5534 opp-hz = /bits/ 64 <160000000>; 5535 required-opps = <&rpmhpd_opp_low_svs>; 5536 }; 5537 5538 opp-270000000 { 5539 opp-hz = /bits/ 64 <270000000>; 5540 required-opps = <&rpmhpd_opp_svs>; 5541 }; 5542 5543 opp-540000000 { 5544 opp-hz = /bits/ 64 <540000000>; 5545 required-opps = <&rpmhpd_opp_svs_l1>; 5546 }; 5547 5548 opp-810000000 { 5549 opp-hz = /bits/ 64 <810000000>; 5550 required-opps = <&rpmhpd_opp_nom>; 5551 }; 5552 }; 5553 }; 5554 }; 5555 5556 mdss1_dp2_phy: phy@220c2a00 { 5557 compatible = "qcom,sc8280xp-dp-phy"; 5558 reg = <0 0x220c2a00 0 0x19c>, 5559 <0 0x220c2200 0 0xec>, 5560 <0 0x220c2600 0 0xec>, 5561 <0 0x220c2000 0 0x1c8>; 5562 5563 clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 5564 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 5565 clock-names = "aux", "cfg_ahb"; 5566 power-domains = <&rpmhpd SC8280XP_MX>; 5567 5568 #clock-cells = <1>; 5569 #phy-cells = <0>; 5570 5571 status = "disabled"; 5572 }; 5573 5574 mdss1_dp3_phy: phy@220c5a00 { 5575 compatible = "qcom,sc8280xp-dp-phy"; 5576 reg = <0 0x220c5a00 0 0x19c>, 5577 <0 0x220c5200 0 0xec>, 5578 <0 0x220c5600 0 0xec>, 5579 <0 0x220c5000 0 0x1c8>; 5580 5581 clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 5582 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 5583 clock-names = "aux", "cfg_ahb"; 5584 power-domains = <&rpmhpd SC8280XP_MX>; 5585 5586 #clock-cells = <1>; 5587 #phy-cells = <0>; 5588 5589 status = "disabled"; 5590 }; 5591 5592 dispcc1: clock-controller@22100000 { 5593 compatible = "qcom,sc8280xp-dispcc1"; 5594 reg = <0 0x22100000 0 0x20000>; 5595 5596 clocks = <&gcc GCC_DISP_AHB_CLK>, 5597 <&rpmhcc RPMH_CXO_CLK>, 5598 <0>, 5599 <&mdss1_dp0_phy 0>, 5600 <&mdss1_dp0_phy 1>, 5601 <&mdss1_dp1_phy 0>, 5602 <&mdss1_dp1_phy 1>, 5603 <&mdss1_dp2_phy 0>, 5604 <&mdss1_dp2_phy 1>, 5605 <&mdss1_dp3_phy 0>, 5606 <&mdss1_dp3_phy 1>, 5607 <0>, 5608 <0>, 5609 <0>, 5610 <0>; 5611 power-domains = <&rpmhpd SC8280XP_MMCX>; 5612 5613 #clock-cells = <1>; 5614 #power-domain-cells = <1>; 5615 #reset-cells = <1>; 5616 5617 status = "disabled"; 5618 }; 5619 5620 ethernet1: ethernet@23000000 { 5621 compatible = "qcom,sc8280xp-ethqos"; 5622 reg = <0x0 0x23000000 0x0 0x10000>, 5623 <0x0 0x23016000 0x0 0x100>; 5624 reg-names = "stmmaceth", "rgmii"; 5625 5626 clocks = <&gcc GCC_EMAC1_AXI_CLK>, 5627 <&gcc GCC_EMAC1_SLV_AHB_CLK>, 5628 <&gcc GCC_EMAC1_PTP_CLK>, 5629 <&gcc GCC_EMAC1_RGMII_CLK>; 5630 clock-names = "stmmaceth", 5631 "pclk", 5632 "ptp_ref", 5633 "rgmii"; 5634 5635 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, 5636 <GIC_SPI 919 IRQ_TYPE_LEVEL_HIGH>; 5637 interrupt-names = "macirq", "eth_lpi"; 5638 5639 iommus = <&apps_smmu 0x40 0xf>; 5640 power-domains = <&gcc EMAC_1_GDSC>; 5641 5642 snps,tso; 5643 snps,pbl = <32>; 5644 rx-fifo-depth = <4096>; 5645 tx-fifo-depth = <4096>; 5646 5647 status = "disabled"; 5648 }; 5649 }; 5650 5651 sound: sound { 5652 }; 5653 5654 thermal-zones { 5655 cpu0-thermal { 5656 polling-delay-passive = <250>; 5657 polling-delay = <1000>; 5658 5659 thermal-sensors = <&tsens0 1>; 5660 5661 trips { 5662 cpu-crit { 5663 temperature = <110000>; 5664 hysteresis = <1000>; 5665 type = "critical"; 5666 }; 5667 }; 5668 }; 5669 5670 cpu1-thermal { 5671 polling-delay-passive = <250>; 5672 polling-delay = <1000>; 5673 5674 thermal-sensors = <&tsens0 2>; 5675 5676 trips { 5677 cpu-crit { 5678 temperature = <110000>; 5679 hysteresis = <1000>; 5680 type = "critical"; 5681 }; 5682 }; 5683 }; 5684 5685 cpu2-thermal { 5686 polling-delay-passive = <250>; 5687 polling-delay = <1000>; 5688 5689 thermal-sensors = <&tsens0 3>; 5690 5691 trips { 5692 cpu-crit { 5693 temperature = <110000>; 5694 hysteresis = <1000>; 5695 type = "critical"; 5696 }; 5697 }; 5698 }; 5699 5700 cpu3-thermal { 5701 polling-delay-passive = <250>; 5702 polling-delay = <1000>; 5703 5704 thermal-sensors = <&tsens0 4>; 5705 5706 trips { 5707 cpu-crit { 5708 temperature = <110000>; 5709 hysteresis = <1000>; 5710 type = "critical"; 5711 }; 5712 }; 5713 }; 5714 5715 cpu4-thermal { 5716 polling-delay-passive = <250>; 5717 polling-delay = <1000>; 5718 5719 thermal-sensors = <&tsens0 5>; 5720 5721 trips { 5722 cpu-crit { 5723 temperature = <110000>; 5724 hysteresis = <1000>; 5725 type = "critical"; 5726 }; 5727 }; 5728 }; 5729 5730 cpu5-thermal { 5731 polling-delay-passive = <250>; 5732 polling-delay = <1000>; 5733 5734 thermal-sensors = <&tsens0 6>; 5735 5736 trips { 5737 cpu-crit { 5738 temperature = <110000>; 5739 hysteresis = <1000>; 5740 type = "critical"; 5741 }; 5742 }; 5743 }; 5744 5745 cpu6-thermal { 5746 polling-delay-passive = <250>; 5747 polling-delay = <1000>; 5748 5749 thermal-sensors = <&tsens0 7>; 5750 5751 trips { 5752 cpu-crit { 5753 temperature = <110000>; 5754 hysteresis = <1000>; 5755 type = "critical"; 5756 }; 5757 }; 5758 }; 5759 5760 cpu7-thermal { 5761 polling-delay-passive = <250>; 5762 polling-delay = <1000>; 5763 5764 thermal-sensors = <&tsens0 8>; 5765 5766 trips { 5767 cpu-crit { 5768 temperature = <110000>; 5769 hysteresis = <1000>; 5770 type = "critical"; 5771 }; 5772 }; 5773 }; 5774 5775 cluster0-thermal { 5776 polling-delay-passive = <250>; 5777 polling-delay = <1000>; 5778 5779 thermal-sensors = <&tsens0 9>; 5780 5781 trips { 5782 cpu-crit { 5783 temperature = <110000>; 5784 hysteresis = <1000>; 5785 type = "critical"; 5786 }; 5787 }; 5788 }; 5789 5790 gpu-thermal { 5791 polling-delay-passive = <0>; 5792 polling-delay = <0>; 5793 5794 thermal-sensors = <&tsens2 2>; 5795 5796 trips { 5797 gpu-crit { 5798 temperature = <110000>; 5799 hysteresis = <1000>; 5800 type = "critical"; 5801 }; 5802 }; 5803 }; 5804 5805 mem-thermal { 5806 polling-delay-passive = <250>; 5807 polling-delay = <1000>; 5808 5809 thermal-sensors = <&tsens1 15>; 5810 5811 trips { 5812 trip-point0 { 5813 temperature = <90000>; 5814 hysteresis = <2000>; 5815 type = "hot"; 5816 }; 5817 }; 5818 }; 5819 }; 5820 5821 timer { 5822 compatible = "arm,armv8-timer"; 5823 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5824 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5825 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 5826 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 5827 }; 5828}; 5829