1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Linaro Limited 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> 8#include <dt-bindings/clock/qcom,gcc-sc8280xp.h> 9#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sc8280xp-camcc.h> 12#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/interconnect/qcom,osm-l3.h> 15#include <dt-bindings/interconnect/qcom,sc8280xp.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/mailbox/qcom-ipcc.h> 18#include <dt-bindings/phy/phy-qcom-qmp.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/soc/qcom,gpr.h> 21#include <dt-bindings/soc/qcom,rpmh-rsc.h> 22#include <dt-bindings/sound/qcom,q6afe.h> 23#include <dt-bindings/thermal/thermal.h> 24 25/ { 26 interrupt-parent = <&intc>; 27 28 #address-cells = <2>; 29 #size-cells = <2>; 30 31 clocks { 32 xo_board_clk: xo-board-clk { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 }; 36 37 sleep_clk: sleep-clk { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <32764>; 41 }; 42 }; 43 44 cpus { 45 #address-cells = <2>; 46 #size-cells = <0>; 47 48 cpu0: cpu@0 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a78c"; 51 reg = <0x0 0x0>; 52 clocks = <&cpufreq_hw 0>; 53 enable-method = "psci"; 54 capacity-dmips-mhz = <981>; 55 dynamic-power-coefficient = <549>; 56 next-level-cache = <&l2_0>; 57 power-domains = <&cpu_pd0>; 58 power-domain-names = "psci"; 59 qcom,freq-domain = <&cpufreq_hw 0>; 60 operating-points-v2 = <&cpu0_opp_table>; 61 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 62 #cooling-cells = <2>; 63 l2_0: l2-cache { 64 compatible = "cache"; 65 cache-level = <2>; 66 cache-unified; 67 next-level-cache = <&l3_0>; 68 l3_0: l3-cache { 69 compatible = "cache"; 70 cache-level = <3>; 71 cache-unified; 72 }; 73 }; 74 }; 75 76 cpu1: cpu@100 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a78c"; 79 reg = <0x0 0x100>; 80 clocks = <&cpufreq_hw 0>; 81 enable-method = "psci"; 82 capacity-dmips-mhz = <981>; 83 dynamic-power-coefficient = <549>; 84 next-level-cache = <&l2_100>; 85 power-domains = <&cpu_pd1>; 86 power-domain-names = "psci"; 87 qcom,freq-domain = <&cpufreq_hw 0>; 88 operating-points-v2 = <&cpu0_opp_table>; 89 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 90 #cooling-cells = <2>; 91 l2_100: l2-cache { 92 compatible = "cache"; 93 cache-level = <2>; 94 cache-unified; 95 next-level-cache = <&l3_0>; 96 }; 97 }; 98 99 cpu2: cpu@200 { 100 device_type = "cpu"; 101 compatible = "arm,cortex-a78c"; 102 reg = <0x0 0x200>; 103 clocks = <&cpufreq_hw 0>; 104 enable-method = "psci"; 105 capacity-dmips-mhz = <981>; 106 dynamic-power-coefficient = <549>; 107 next-level-cache = <&l2_200>; 108 power-domains = <&cpu_pd2>; 109 power-domain-names = "psci"; 110 qcom,freq-domain = <&cpufreq_hw 0>; 111 operating-points-v2 = <&cpu0_opp_table>; 112 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 113 #cooling-cells = <2>; 114 l2_200: l2-cache { 115 compatible = "cache"; 116 cache-level = <2>; 117 cache-unified; 118 next-level-cache = <&l3_0>; 119 }; 120 }; 121 122 cpu3: cpu@300 { 123 device_type = "cpu"; 124 compatible = "arm,cortex-a78c"; 125 reg = <0x0 0x300>; 126 clocks = <&cpufreq_hw 0>; 127 enable-method = "psci"; 128 capacity-dmips-mhz = <981>; 129 dynamic-power-coefficient = <549>; 130 next-level-cache = <&l2_300>; 131 power-domains = <&cpu_pd3>; 132 power-domain-names = "psci"; 133 qcom,freq-domain = <&cpufreq_hw 0>; 134 operating-points-v2 = <&cpu0_opp_table>; 135 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 136 #cooling-cells = <2>; 137 l2_300: l2-cache { 138 compatible = "cache"; 139 cache-level = <2>; 140 cache-unified; 141 next-level-cache = <&l3_0>; 142 }; 143 }; 144 145 cpu4: cpu@400 { 146 device_type = "cpu"; 147 compatible = "arm,cortex-x1c"; 148 reg = <0x0 0x400>; 149 clocks = <&cpufreq_hw 1>; 150 enable-method = "psci"; 151 capacity-dmips-mhz = <1024>; 152 dynamic-power-coefficient = <590>; 153 next-level-cache = <&l2_400>; 154 power-domains = <&cpu_pd4>; 155 power-domain-names = "psci"; 156 qcom,freq-domain = <&cpufreq_hw 1>; 157 operating-points-v2 = <&cpu4_opp_table>; 158 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 159 #cooling-cells = <2>; 160 l2_400: l2-cache { 161 compatible = "cache"; 162 cache-level = <2>; 163 cache-unified; 164 next-level-cache = <&l3_0>; 165 }; 166 }; 167 168 cpu5: cpu@500 { 169 device_type = "cpu"; 170 compatible = "arm,cortex-x1c"; 171 reg = <0x0 0x500>; 172 clocks = <&cpufreq_hw 1>; 173 enable-method = "psci"; 174 capacity-dmips-mhz = <1024>; 175 dynamic-power-coefficient = <590>; 176 next-level-cache = <&l2_500>; 177 power-domains = <&cpu_pd5>; 178 power-domain-names = "psci"; 179 qcom,freq-domain = <&cpufreq_hw 1>; 180 operating-points-v2 = <&cpu4_opp_table>; 181 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 182 #cooling-cells = <2>; 183 l2_500: l2-cache { 184 compatible = "cache"; 185 cache-level = <2>; 186 cache-unified; 187 next-level-cache = <&l3_0>; 188 }; 189 }; 190 191 cpu6: cpu@600 { 192 device_type = "cpu"; 193 compatible = "arm,cortex-x1c"; 194 reg = <0x0 0x600>; 195 clocks = <&cpufreq_hw 1>; 196 enable-method = "psci"; 197 capacity-dmips-mhz = <1024>; 198 dynamic-power-coefficient = <590>; 199 next-level-cache = <&l2_600>; 200 power-domains = <&cpu_pd6>; 201 power-domain-names = "psci"; 202 qcom,freq-domain = <&cpufreq_hw 1>; 203 operating-points-v2 = <&cpu4_opp_table>; 204 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 205 #cooling-cells = <2>; 206 l2_600: l2-cache { 207 compatible = "cache"; 208 cache-level = <2>; 209 cache-unified; 210 next-level-cache = <&l3_0>; 211 }; 212 }; 213 214 cpu7: cpu@700 { 215 device_type = "cpu"; 216 compatible = "arm,cortex-x1c"; 217 reg = <0x0 0x700>; 218 clocks = <&cpufreq_hw 1>; 219 enable-method = "psci"; 220 capacity-dmips-mhz = <1024>; 221 dynamic-power-coefficient = <590>; 222 next-level-cache = <&l2_700>; 223 power-domains = <&cpu_pd7>; 224 power-domain-names = "psci"; 225 qcom,freq-domain = <&cpufreq_hw 1>; 226 operating-points-v2 = <&cpu4_opp_table>; 227 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 228 #cooling-cells = <2>; 229 l2_700: l2-cache { 230 compatible = "cache"; 231 cache-level = <2>; 232 cache-unified; 233 next-level-cache = <&l3_0>; 234 }; 235 }; 236 237 cpu-map { 238 cluster0 { 239 core0 { 240 cpu = <&cpu0>; 241 }; 242 243 core1 { 244 cpu = <&cpu1>; 245 }; 246 247 core2 { 248 cpu = <&cpu2>; 249 }; 250 251 core3 { 252 cpu = <&cpu3>; 253 }; 254 255 core4 { 256 cpu = <&cpu4>; 257 }; 258 259 core5 { 260 cpu = <&cpu5>; 261 }; 262 263 core6 { 264 cpu = <&cpu6>; 265 }; 266 267 core7 { 268 cpu = <&cpu7>; 269 }; 270 }; 271 }; 272 273 idle-states { 274 entry-method = "psci"; 275 276 little_cpu_sleep_0: cpu-sleep-0-0 { 277 compatible = "arm,idle-state"; 278 idle-state-name = "little-rail-power-collapse"; 279 arm,psci-suspend-param = <0x40000004>; 280 entry-latency-us = <355>; 281 exit-latency-us = <909>; 282 min-residency-us = <3934>; 283 local-timer-stop; 284 }; 285 286 big_cpu_sleep_0: cpu-sleep-1-0 { 287 compatible = "arm,idle-state"; 288 idle-state-name = "big-rail-power-collapse"; 289 arm,psci-suspend-param = <0x40000004>; 290 entry-latency-us = <241>; 291 exit-latency-us = <1461>; 292 min-residency-us = <4488>; 293 local-timer-stop; 294 }; 295 }; 296 297 domain-idle-states { 298 cluster_sleep_0: cluster-sleep-0 { 299 compatible = "domain-idle-state"; 300 arm,psci-suspend-param = <0x4100c344>; 301 entry-latency-us = <3263>; 302 exit-latency-us = <6562>; 303 min-residency-us = <9987>; 304 }; 305 }; 306 }; 307 308 firmware { 309 scm: scm { 310 compatible = "qcom,scm-sc8280xp", "qcom,scm"; 311 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 312 qcom,dload-mode = <&tcsr 0x13000>; 313 }; 314 }; 315 316 aggre1_noc: interconnect-aggre1-noc { 317 compatible = "qcom,sc8280xp-aggre1-noc"; 318 #interconnect-cells = <2>; 319 qcom,bcm-voters = <&apps_bcm_voter>; 320 }; 321 322 aggre2_noc: interconnect-aggre2-noc { 323 compatible = "qcom,sc8280xp-aggre2-noc"; 324 #interconnect-cells = <2>; 325 qcom,bcm-voters = <&apps_bcm_voter>; 326 }; 327 328 clk_virt: interconnect-clk-virt { 329 compatible = "qcom,sc8280xp-clk-virt"; 330 #interconnect-cells = <2>; 331 qcom,bcm-voters = <&apps_bcm_voter>; 332 }; 333 334 config_noc: interconnect-config-noc { 335 compatible = "qcom,sc8280xp-config-noc"; 336 #interconnect-cells = <2>; 337 qcom,bcm-voters = <&apps_bcm_voter>; 338 }; 339 340 dc_noc: interconnect-dc-noc { 341 compatible = "qcom,sc8280xp-dc-noc"; 342 #interconnect-cells = <2>; 343 qcom,bcm-voters = <&apps_bcm_voter>; 344 }; 345 346 gem_noc: interconnect-gem-noc { 347 compatible = "qcom,sc8280xp-gem-noc"; 348 #interconnect-cells = <2>; 349 qcom,bcm-voters = <&apps_bcm_voter>; 350 }; 351 352 lpass_noc: interconnect-lpass-ag-noc { 353 compatible = "qcom,sc8280xp-lpass-ag-noc"; 354 #interconnect-cells = <2>; 355 qcom,bcm-voters = <&apps_bcm_voter>; 356 }; 357 358 mc_virt: interconnect-mc-virt { 359 compatible = "qcom,sc8280xp-mc-virt"; 360 #interconnect-cells = <2>; 361 qcom,bcm-voters = <&apps_bcm_voter>; 362 }; 363 364 mmss_noc: interconnect-mmss-noc { 365 compatible = "qcom,sc8280xp-mmss-noc"; 366 #interconnect-cells = <2>; 367 qcom,bcm-voters = <&apps_bcm_voter>; 368 }; 369 370 nspa_noc: interconnect-nspa-noc { 371 compatible = "qcom,sc8280xp-nspa-noc"; 372 #interconnect-cells = <2>; 373 qcom,bcm-voters = <&apps_bcm_voter>; 374 }; 375 376 nspb_noc: interconnect-nspb-noc { 377 compatible = "qcom,sc8280xp-nspb-noc"; 378 #interconnect-cells = <2>; 379 qcom,bcm-voters = <&apps_bcm_voter>; 380 }; 381 382 system_noc: interconnect-system-noc { 383 compatible = "qcom,sc8280xp-system-noc"; 384 #interconnect-cells = <2>; 385 qcom,bcm-voters = <&apps_bcm_voter>; 386 }; 387 388 memory@80000000 { 389 device_type = "memory"; 390 /* We expect the bootloader to fill in the size */ 391 reg = <0x0 0x80000000 0x0 0x0>; 392 }; 393 394 cpu0_opp_table: opp-table-cpu0 { 395 compatible = "operating-points-v2"; 396 opp-shared; 397 398 opp-300000000 { 399 opp-hz = /bits/ 64 <300000000>; 400 opp-peak-kBps = <(300000 * 32)>; 401 }; 402 opp-403200000 { 403 opp-hz = /bits/ 64 <403200000>; 404 opp-peak-kBps = <(384000 * 32)>; 405 }; 406 opp-499200000 { 407 opp-hz = /bits/ 64 <499200000>; 408 opp-peak-kBps = <(480000 * 32)>; 409 }; 410 opp-595200000 { 411 opp-hz = /bits/ 64 <595200000>; 412 opp-peak-kBps = <(576000 * 32)>; 413 }; 414 opp-691200000 { 415 opp-hz = /bits/ 64 <691200000>; 416 opp-peak-kBps = <(672000 * 32)>; 417 }; 418 opp-806400000 { 419 opp-hz = /bits/ 64 <806400000>; 420 opp-peak-kBps = <(768000 * 32)>; 421 }; 422 opp-902400000 { 423 opp-hz = /bits/ 64 <902400000>; 424 opp-peak-kBps = <(864000 * 32)>; 425 }; 426 opp-1017600000 { 427 opp-hz = /bits/ 64 <1017600000>; 428 opp-peak-kBps = <(960000 * 32)>; 429 }; 430 opp-1113600000 { 431 opp-hz = /bits/ 64 <1113600000>; 432 opp-peak-kBps = <(1075200 * 32)>; 433 }; 434 opp-1209600000 { 435 opp-hz = /bits/ 64 <1209600000>; 436 opp-peak-kBps = <(1171200 * 32)>; 437 }; 438 opp-1324800000 { 439 opp-hz = /bits/ 64 <1324800000>; 440 opp-peak-kBps = <(1267200 * 32)>; 441 }; 442 opp-1440000000 { 443 opp-hz = /bits/ 64 <1440000000>; 444 opp-peak-kBps = <(1363200 * 32)>; 445 }; 446 opp-1555200000 { 447 opp-hz = /bits/ 64 <1555200000>; 448 opp-peak-kBps = <(1536000 * 32)>; 449 }; 450 opp-1670400000 { 451 opp-hz = /bits/ 64 <1670400000>; 452 opp-peak-kBps = <(1612800 * 32)>; 453 }; 454 opp-1785600000 { 455 opp-hz = /bits/ 64 <1785600000>; 456 opp-peak-kBps = <(1689600 * 32)>; 457 }; 458 opp-1881600000 { 459 opp-hz = /bits/ 64 <1881600000>; 460 opp-peak-kBps = <(1689600 * 32)>; 461 }; 462 opp-1996800000 { 463 opp-hz = /bits/ 64 <1996800000>; 464 opp-peak-kBps = <(1689600 * 32)>; 465 }; 466 opp-2112000000 { 467 opp-hz = /bits/ 64 <2112000000>; 468 opp-peak-kBps = <(1689600 * 32)>; 469 }; 470 opp-2227200000 { 471 opp-hz = /bits/ 64 <2227200000>; 472 opp-peak-kBps = <(1689600 * 32)>; 473 }; 474 opp-2342400000 { 475 opp-hz = /bits/ 64 <2342400000>; 476 opp-peak-kBps = <(1689600 * 32)>; 477 }; 478 opp-2438400000 { 479 opp-hz = /bits/ 64 <2438400000>; 480 opp-peak-kBps = <(1689600 * 32)>; 481 }; 482 }; 483 484 cpu4_opp_table: opp-table-cpu4 { 485 compatible = "operating-points-v2"; 486 opp-shared; 487 488 opp-825600000 { 489 opp-hz = /bits/ 64 <825600000>; 490 opp-peak-kBps = <(768000 * 32)>; 491 }; 492 opp-940800000 { 493 opp-hz = /bits/ 64 <940800000>; 494 opp-peak-kBps = <(864000 * 32)>; 495 }; 496 opp-1056000000 { 497 opp-hz = /bits/ 64 <1056000000>; 498 opp-peak-kBps = <(960000 * 32)>; 499 }; 500 opp-1171200000 { 501 opp-hz = /bits/ 64 <1171200000>; 502 opp-peak-kBps = <(1171200 * 32)>; 503 }; 504 opp-1286400000 { 505 opp-hz = /bits/ 64 <1286400000>; 506 opp-peak-kBps = <(1267200 * 32)>; 507 }; 508 opp-1401600000 { 509 opp-hz = /bits/ 64 <1401600000>; 510 opp-peak-kBps = <(1363200 * 32)>; 511 }; 512 opp-1516800000 { 513 opp-hz = /bits/ 64 <1516800000>; 514 opp-peak-kBps = <(1459200 * 32)>; 515 }; 516 opp-1632000000 { 517 opp-hz = /bits/ 64 <1632000000>; 518 opp-peak-kBps = <(1612800 * 32)>; 519 }; 520 opp-1747200000 { 521 opp-hz = /bits/ 64 <1747200000>; 522 opp-peak-kBps = <(1689600 * 32)>; 523 }; 524 opp-1862400000 { 525 opp-hz = /bits/ 64 <1862400000>; 526 opp-peak-kBps = <(1689600 * 32)>; 527 }; 528 opp-1977600000 { 529 opp-hz = /bits/ 64 <1977600000>; 530 opp-peak-kBps = <(1689600 * 32)>; 531 }; 532 opp-2073600000 { 533 opp-hz = /bits/ 64 <2073600000>; 534 opp-peak-kBps = <(1689600 * 32)>; 535 }; 536 opp-2169600000 { 537 opp-hz = /bits/ 64 <2169600000>; 538 opp-peak-kBps = <(1689600 * 32)>; 539 }; 540 opp-2284800000 { 541 opp-hz = /bits/ 64 <2284800000>; 542 opp-peak-kBps = <(1689600 * 32)>; 543 }; 544 opp-2400000000 { 545 opp-hz = /bits/ 64 <2400000000>; 546 opp-peak-kBps = <(1689600 * 32)>; 547 }; 548 opp-2496000000 { 549 opp-hz = /bits/ 64 <2496000000>; 550 opp-peak-kBps = <(1689600 * 32)>; 551 }; 552 opp-2592000000 { 553 opp-hz = /bits/ 64 <2592000000>; 554 opp-peak-kBps = <(1689600 * 32)>; 555 }; 556 opp-2688000000 { 557 opp-hz = /bits/ 64 <2688000000>; 558 opp-peak-kBps = <(1689600 * 32)>; 559 }; 560 opp-2803200000 { 561 opp-hz = /bits/ 64 <2803200000>; 562 opp-peak-kBps = <(1689600 * 32)>; 563 }; 564 opp-2899200000 { 565 opp-hz = /bits/ 64 <2899200000>; 566 opp-peak-kBps = <(1689600 * 32)>; 567 }; 568 opp-2995200000 { 569 opp-hz = /bits/ 64 <2995200000>; 570 opp-peak-kBps = <(1689600 * 32)>; 571 }; 572 }; 573 574 qup_opp_table_100mhz: opp-table-qup100mhz { 575 compatible = "operating-points-v2"; 576 577 opp-75000000 { 578 opp-hz = /bits/ 64 <75000000>; 579 required-opps = <&rpmhpd_opp_low_svs>; 580 }; 581 582 opp-100000000 { 583 opp-hz = /bits/ 64 <100000000>; 584 required-opps = <&rpmhpd_opp_svs>; 585 }; 586 }; 587 588 pmu { 589 compatible = "arm,armv8-pmuv3"; 590 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 591 }; 592 593 psci { 594 compatible = "arm,psci-1.0"; 595 method = "smc"; 596 597 cpu_pd0: power-domain-cpu0 { 598 #power-domain-cells = <0>; 599 power-domains = <&cluster_pd>; 600 domain-idle-states = <&little_cpu_sleep_0>; 601 }; 602 603 cpu_pd1: power-domain-cpu1 { 604 #power-domain-cells = <0>; 605 power-domains = <&cluster_pd>; 606 domain-idle-states = <&little_cpu_sleep_0>; 607 }; 608 609 cpu_pd2: power-domain-cpu2 { 610 #power-domain-cells = <0>; 611 power-domains = <&cluster_pd>; 612 domain-idle-states = <&little_cpu_sleep_0>; 613 }; 614 615 cpu_pd3: power-domain-cpu3 { 616 #power-domain-cells = <0>; 617 power-domains = <&cluster_pd>; 618 domain-idle-states = <&little_cpu_sleep_0>; 619 }; 620 621 cpu_pd4: power-domain-cpu4 { 622 #power-domain-cells = <0>; 623 power-domains = <&cluster_pd>; 624 domain-idle-states = <&big_cpu_sleep_0>; 625 }; 626 627 cpu_pd5: power-domain-cpu5 { 628 #power-domain-cells = <0>; 629 power-domains = <&cluster_pd>; 630 domain-idle-states = <&big_cpu_sleep_0>; 631 }; 632 633 cpu_pd6: power-domain-cpu6 { 634 #power-domain-cells = <0>; 635 power-domains = <&cluster_pd>; 636 domain-idle-states = <&big_cpu_sleep_0>; 637 }; 638 639 cpu_pd7: power-domain-cpu7 { 640 #power-domain-cells = <0>; 641 power-domains = <&cluster_pd>; 642 domain-idle-states = <&big_cpu_sleep_0>; 643 }; 644 645 cluster_pd: power-domain-cpu-cluster0 { 646 #power-domain-cells = <0>; 647 domain-idle-states = <&cluster_sleep_0>; 648 }; 649 }; 650 651 reserved-memory { 652 #address-cells = <2>; 653 #size-cells = <2>; 654 ranges; 655 656 reserved-region@80000000 { 657 reg = <0 0x80000000 0 0x860000>; 658 no-map; 659 }; 660 661 cmd_db: cmd-db-region@80860000 { 662 compatible = "qcom,cmd-db"; 663 reg = <0 0x80860000 0 0x20000>; 664 no-map; 665 }; 666 667 reserved-region@80880000 { 668 reg = <0 0x80880000 0 0x80000>; 669 no-map; 670 }; 671 672 smem_mem: smem-region@80900000 { 673 compatible = "qcom,smem"; 674 reg = <0 0x80900000 0 0x200000>; 675 no-map; 676 hwlocks = <&tcsr_mutex 3>; 677 }; 678 679 reserved-region@80b00000 { 680 reg = <0 0x80b00000 0 0x100000>; 681 no-map; 682 }; 683 684 reserved-region@83b00000 { 685 reg = <0 0x83b00000 0 0x1700000>; 686 no-map; 687 }; 688 689 reserved-region@85b00000 { 690 reg = <0 0x85b00000 0 0xc00000>; 691 no-map; 692 }; 693 694 pil_adsp_mem: adsp-region@86c00000 { 695 reg = <0 0x86c00000 0 0x2000000>; 696 no-map; 697 }; 698 699 pil_slpi_mem: slpi-region@88c00000 { 700 reg = <0 0x88c00000 0 0x1500000>; 701 no-map; 702 }; 703 704 pil_nsp0_mem: cdsp0-region@8a100000 { 705 reg = <0 0x8a100000 0 0x1e00000>; 706 no-map; 707 }; 708 709 pil_nsp1_mem: cdsp1-region@8c600000 { 710 reg = <0 0x8c600000 0 0x1e00000>; 711 no-map; 712 }; 713 714 reserved-region@aeb00000 { 715 reg = <0 0xaeb00000 0 0x16600000>; 716 no-map; 717 }; 718 }; 719 720 smp2p-adsp { 721 compatible = "qcom,smp2p"; 722 qcom,smem = <443>, <429>; 723 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 724 IPCC_MPROC_SIGNAL_SMP2P 725 IRQ_TYPE_EDGE_RISING>; 726 mboxes = <&ipcc IPCC_CLIENT_LPASS 727 IPCC_MPROC_SIGNAL_SMP2P>; 728 729 qcom,local-pid = <0>; 730 qcom,remote-pid = <2>; 731 732 smp2p_adsp_out: master-kernel { 733 qcom,entry-name = "master-kernel"; 734 #qcom,smem-state-cells = <1>; 735 }; 736 737 smp2p_adsp_in: slave-kernel { 738 qcom,entry-name = "slave-kernel"; 739 interrupt-controller; 740 #interrupt-cells = <2>; 741 }; 742 }; 743 744 smp2p-nsp0 { 745 compatible = "qcom,smp2p"; 746 qcom,smem = <94>, <432>; 747 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 748 IPCC_MPROC_SIGNAL_SMP2P 749 IRQ_TYPE_EDGE_RISING>; 750 mboxes = <&ipcc IPCC_CLIENT_CDSP 751 IPCC_MPROC_SIGNAL_SMP2P>; 752 753 qcom,local-pid = <0>; 754 qcom,remote-pid = <5>; 755 756 smp2p_nsp0_out: master-kernel { 757 qcom,entry-name = "master-kernel"; 758 #qcom,smem-state-cells = <1>; 759 }; 760 761 smp2p_nsp0_in: slave-kernel { 762 qcom,entry-name = "slave-kernel"; 763 interrupt-controller; 764 #interrupt-cells = <2>; 765 }; 766 }; 767 768 smp2p-nsp1 { 769 compatible = "qcom,smp2p"; 770 qcom,smem = <617>, <616>; 771 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 772 IPCC_MPROC_SIGNAL_SMP2P 773 IRQ_TYPE_EDGE_RISING>; 774 mboxes = <&ipcc IPCC_CLIENT_NSP1 775 IPCC_MPROC_SIGNAL_SMP2P>; 776 777 qcom,local-pid = <0>; 778 qcom,remote-pid = <12>; 779 780 smp2p_nsp1_out: master-kernel { 781 qcom,entry-name = "master-kernel"; 782 #qcom,smem-state-cells = <1>; 783 }; 784 785 smp2p_nsp1_in: slave-kernel { 786 qcom,entry-name = "slave-kernel"; 787 interrupt-controller; 788 #interrupt-cells = <2>; 789 }; 790 }; 791 792 smp2p-slpi { 793 compatible = "qcom,smp2p"; 794 qcom,smem = <481>, <430>; 795 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 796 IPCC_MPROC_SIGNAL_SMP2P 797 IRQ_TYPE_EDGE_RISING>; 798 mboxes = <&ipcc IPCC_CLIENT_SLPI 799 IPCC_MPROC_SIGNAL_SMP2P>; 800 801 qcom,local-pid = <0>; 802 qcom,remote-pid = <3>; 803 804 smp2p_slpi_out: master-kernel { 805 qcom,entry-name = "master-kernel"; 806 #qcom,smem-state-cells = <1>; 807 }; 808 809 smp2p_slpi_in: slave-kernel { 810 qcom,entry-name = "slave-kernel"; 811 interrupt-controller; 812 #interrupt-cells = <2>; 813 }; 814 }; 815 816 soc: soc@0 { 817 compatible = "simple-bus"; 818 #address-cells = <2>; 819 #size-cells = <2>; 820 ranges = <0 0 0 0 0x10 0>; 821 dma-ranges = <0 0 0 0 0x10 0>; 822 823 ethernet0: ethernet@20000 { 824 compatible = "qcom,sc8280xp-ethqos"; 825 reg = <0x0 0x00020000 0x0 0x10000>, 826 <0x0 0x00036000 0x0 0x100>; 827 reg-names = "stmmaceth", "rgmii"; 828 829 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 830 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 831 <&gcc GCC_EMAC0_PTP_CLK>, 832 <&gcc GCC_EMAC0_RGMII_CLK>; 833 clock-names = "stmmaceth", 834 "pclk", 835 "ptp_ref", 836 "rgmii"; 837 838 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 839 <GIC_SPI 936 IRQ_TYPE_LEVEL_HIGH>; 840 interrupt-names = "macirq", "eth_lpi"; 841 842 iommus = <&apps_smmu 0x4c0 0xf>; 843 power-domains = <&gcc EMAC_0_GDSC>; 844 845 snps,tso; 846 snps,pbl = <32>; 847 rx-fifo-depth = <4096>; 848 tx-fifo-depth = <4096>; 849 850 status = "disabled"; 851 }; 852 853 gcc: clock-controller@100000 { 854 compatible = "qcom,gcc-sc8280xp"; 855 reg = <0x0 0x00100000 0x0 0x1f0000>; 856 #clock-cells = <1>; 857 #reset-cells = <1>; 858 #power-domain-cells = <1>; 859 clocks = <&rpmhcc RPMH_CXO_CLK>, 860 <&sleep_clk>, 861 <0>, 862 <0>, 863 <0>, 864 <0>, 865 <0>, 866 <0>, 867 <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 868 <0>, 869 <0>, 870 <0>, 871 <0>, 872 <0>, 873 <0>, 874 <0>, 875 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 876 <0>, 877 <0>, 878 <0>, 879 <0>, 880 <0>, 881 <0>, 882 <0>, 883 <0>, 884 <0>, 885 <&pcie2a_phy>, 886 <&pcie2b_phy>, 887 <&pcie3a_phy>, 888 <&pcie3b_phy>, 889 <&pcie4_phy>, 890 <0>, 891 <0>; 892 power-domains = <&rpmhpd SC8280XP_CX>; 893 }; 894 895 ipcc: mailbox@408000 { 896 compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc"; 897 reg = <0 0x00408000 0 0x1000>; 898 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 899 interrupt-controller; 900 #interrupt-cells = <3>; 901 #mbox-cells = <2>; 902 }; 903 904 qfprom: efuse@784000 { 905 compatible = "qcom,sc8280xp-qfprom", "qcom,qfprom"; 906 reg = <0 0x00784000 0 0x3000>; 907 #address-cells = <1>; 908 #size-cells = <1>; 909 910 gpu_speed_bin: gpu-speed-bin@18b { 911 reg = <0x18b 0x1>; 912 bits = <5 3>; 913 }; 914 }; 915 916 gpi_dma2: dma-controller@800000 { 917 compatible = "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma"; 918 reg = <0 0x00800000 0 0x60000>; 919 920 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 921 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 922 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 923 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 932 933 dma-channels = <12>; 934 dma-channel-mask = <0xfff>; 935 #dma-cells = <3>; 936 937 iommus = <&apps_smmu 0xb6 0x0>; 938 939 status = "disabled"; 940 }; 941 942 qup2: geniqup@8c0000 { 943 compatible = "qcom,geni-se-qup"; 944 reg = <0 0x008c0000 0 0x2000>; 945 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 946 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 947 clock-names = "m-ahb", "s-ahb"; 948 iommus = <&apps_smmu 0xa3 0>; 949 950 #address-cells = <2>; 951 #size-cells = <2>; 952 ranges; 953 954 status = "disabled"; 955 956 i2c16: i2c@880000 { 957 compatible = "qcom,geni-i2c"; 958 reg = <0 0x00880000 0 0x4000>; 959 #address-cells = <1>; 960 #size-cells = <0>; 961 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 962 clock-names = "se"; 963 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 964 power-domains = <&rpmhpd SC8280XP_CX>; 965 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 966 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 967 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 968 interconnect-names = "qup-core", "qup-config", "qup-memory"; 969 970 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 971 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 972 dma-names = "tx", 973 "rx"; 974 975 status = "disabled"; 976 }; 977 978 spi16: spi@880000 { 979 compatible = "qcom,geni-spi"; 980 reg = <0 0x00880000 0 0x4000>; 981 #address-cells = <1>; 982 #size-cells = <0>; 983 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 984 clock-names = "se"; 985 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 986 power-domains = <&rpmhpd SC8280XP_CX>; 987 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 988 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 989 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 990 interconnect-names = "qup-core", "qup-config", "qup-memory"; 991 992 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 993 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 994 dma-names = "tx", 995 "rx"; 996 997 status = "disabled"; 998 }; 999 1000 i2c17: i2c@884000 { 1001 compatible = "qcom,geni-i2c"; 1002 reg = <0 0x00884000 0 0x4000>; 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1006 clock-names = "se"; 1007 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1008 power-domains = <&rpmhpd SC8280XP_CX>; 1009 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1010 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1011 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1012 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1013 1014 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1015 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1016 dma-names = "tx", 1017 "rx"; 1018 1019 status = "disabled"; 1020 }; 1021 1022 spi17: spi@884000 { 1023 compatible = "qcom,geni-spi"; 1024 reg = <0 0x00884000 0 0x4000>; 1025 #address-cells = <1>; 1026 #size-cells = <0>; 1027 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1028 clock-names = "se"; 1029 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1030 power-domains = <&rpmhpd SC8280XP_CX>; 1031 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1032 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1033 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1034 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1035 1036 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1037 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1038 dma-names = "tx", 1039 "rx"; 1040 1041 status = "disabled"; 1042 }; 1043 1044 uart17: serial@884000 { 1045 compatible = "qcom,geni-uart"; 1046 reg = <0 0x00884000 0 0x4000>; 1047 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1048 clock-names = "se"; 1049 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1050 operating-points-v2 = <&qup_opp_table_100mhz>; 1051 power-domains = <&rpmhpd SC8280XP_CX>; 1052 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1053 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; 1054 interconnect-names = "qup-core", "qup-config"; 1055 status = "disabled"; 1056 }; 1057 1058 i2c18: i2c@888000 { 1059 compatible = "qcom,geni-i2c"; 1060 reg = <0 0x00888000 0 0x4000>; 1061 #address-cells = <1>; 1062 #size-cells = <0>; 1063 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1064 clock-names = "se"; 1065 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1066 power-domains = <&rpmhpd SC8280XP_CX>; 1067 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1068 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1069 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1070 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1071 1072 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1073 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1074 dma-names = "tx", 1075 "rx"; 1076 1077 status = "disabled"; 1078 }; 1079 1080 spi18: spi@888000 { 1081 compatible = "qcom,geni-spi"; 1082 reg = <0 0x00888000 0 0x4000>; 1083 #address-cells = <1>; 1084 #size-cells = <0>; 1085 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1086 clock-names = "se"; 1087 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1088 power-domains = <&rpmhpd SC8280XP_CX>; 1089 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1090 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1091 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1092 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1093 1094 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1095 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1096 dma-names = "tx", 1097 "rx"; 1098 1099 status = "disabled"; 1100 }; 1101 1102 uart18: serial@888000 { 1103 compatible = "qcom,geni-uart"; 1104 reg = <0 0x00888000 0 0x4000>; 1105 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1106 clock-names = "se"; 1107 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1108 operating-points-v2 = <&qup_opp_table_100mhz>; 1109 power-domains = <&rpmhpd SC8280XP_CX>; 1110 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1111 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; 1112 interconnect-names = "qup-core", "qup-config"; 1113 1114 pinctrl-0 = <&qup_uart18_default>; 1115 pinctrl-names = "default"; 1116 1117 status = "disabled"; 1118 }; 1119 1120 i2c19: i2c@88c000 { 1121 compatible = "qcom,geni-i2c"; 1122 reg = <0 0x0088c000 0 0x4000>; 1123 #address-cells = <1>; 1124 #size-cells = <0>; 1125 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1126 clock-names = "se"; 1127 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1128 power-domains = <&rpmhpd SC8280XP_CX>; 1129 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1130 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1131 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1132 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1133 1134 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1135 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1136 dma-names = "tx", 1137 "rx"; 1138 1139 status = "disabled"; 1140 }; 1141 1142 spi19: spi@88c000 { 1143 compatible = "qcom,geni-spi"; 1144 reg = <0 0x0088c000 0 0x4000>; 1145 #address-cells = <1>; 1146 #size-cells = <0>; 1147 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1148 clock-names = "se"; 1149 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1150 power-domains = <&rpmhpd SC8280XP_CX>; 1151 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1152 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1153 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1154 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1155 1156 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1157 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1158 dma-names = "tx", 1159 "rx"; 1160 1161 status = "disabled"; 1162 }; 1163 1164 i2c20: i2c@890000 { 1165 compatible = "qcom,geni-i2c"; 1166 reg = <0 0x00890000 0 0x4000>; 1167 #address-cells = <1>; 1168 #size-cells = <0>; 1169 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1170 clock-names = "se"; 1171 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1172 power-domains = <&rpmhpd SC8280XP_CX>; 1173 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1174 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1175 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1176 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1177 1178 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1179 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1180 dma-names = "tx", 1181 "rx"; 1182 1183 status = "disabled"; 1184 }; 1185 1186 spi20: spi@890000 { 1187 compatible = "qcom,geni-spi"; 1188 reg = <0 0x00890000 0 0x4000>; 1189 #address-cells = <1>; 1190 #size-cells = <0>; 1191 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1192 clock-names = "se"; 1193 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1194 power-domains = <&rpmhpd SC8280XP_CX>; 1195 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1196 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1197 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1198 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1199 1200 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1201 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1202 dma-names = "tx", 1203 "rx"; 1204 1205 status = "disabled"; 1206 }; 1207 1208 i2c21: i2c@894000 { 1209 compatible = "qcom,geni-i2c"; 1210 reg = <0 0x00894000 0 0x4000>; 1211 clock-names = "se"; 1212 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1213 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1214 #address-cells = <1>; 1215 #size-cells = <0>; 1216 power-domains = <&rpmhpd SC8280XP_CX>; 1217 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1218 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1219 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1220 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1221 1222 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1223 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1224 dma-names = "tx", 1225 "rx"; 1226 1227 status = "disabled"; 1228 }; 1229 1230 spi21: spi@894000 { 1231 compatible = "qcom,geni-spi"; 1232 reg = <0 0x00894000 0 0x4000>; 1233 #address-cells = <1>; 1234 #size-cells = <0>; 1235 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1236 clock-names = "se"; 1237 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1238 power-domains = <&rpmhpd SC8280XP_CX>; 1239 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1240 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1241 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1242 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1243 1244 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1245 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1246 dma-names = "tx", 1247 "rx"; 1248 1249 status = "disabled"; 1250 }; 1251 1252 i2c22: i2c@898000 { 1253 compatible = "qcom,geni-i2c"; 1254 reg = <0 0x00898000 0 0x4000>; 1255 #address-cells = <1>; 1256 #size-cells = <0>; 1257 clock-names = "se"; 1258 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1259 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1260 power-domains = <&rpmhpd SC8280XP_CX>; 1261 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1262 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1263 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1264 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1265 1266 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1267 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1268 dma-names = "tx", 1269 "rx"; 1270 1271 status = "disabled"; 1272 }; 1273 1274 spi22: spi@898000 { 1275 compatible = "qcom,geni-spi"; 1276 reg = <0 0x00898000 0 0x4000>; 1277 #address-cells = <1>; 1278 #size-cells = <0>; 1279 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1280 clock-names = "se"; 1281 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1282 power-domains = <&rpmhpd SC8280XP_CX>; 1283 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1284 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1285 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1286 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1287 1288 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1289 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1290 dma-names = "tx", 1291 "rx"; 1292 1293 status = "disabled"; 1294 }; 1295 1296 i2c23: i2c@89c000 { 1297 compatible = "qcom,geni-i2c"; 1298 reg = <0 0x0089c000 0 0x4000>; 1299 #address-cells = <1>; 1300 #size-cells = <0>; 1301 clock-names = "se"; 1302 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1303 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1304 power-domains = <&rpmhpd SC8280XP_CX>; 1305 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1306 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1307 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1308 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1309 1310 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1311 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1312 dma-names = "tx", 1313 "rx"; 1314 1315 status = "disabled"; 1316 }; 1317 1318 spi23: spi@89c000 { 1319 compatible = "qcom,geni-spi"; 1320 reg = <0 0x0089c000 0 0x4000>; 1321 #address-cells = <1>; 1322 #size-cells = <0>; 1323 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1324 clock-names = "se"; 1325 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1326 power-domains = <&rpmhpd SC8280XP_CX>; 1327 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1328 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1329 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1330 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1331 1332 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1333 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1334 dma-names = "tx", 1335 "rx"; 1336 1337 status = "disabled"; 1338 }; 1339 }; 1340 1341 gpi_dma0: dma-controller@900000 { 1342 compatible = "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma"; 1343 reg = <0 0x00900000 0 0x60000>; 1344 1345 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1346 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1347 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1348 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1349 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1350 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1351 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1352 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1353 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1354 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1355 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1356 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1357 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1358 1359 dma-channels = <13>; 1360 dma-channel-mask = <0x1fff>; 1361 #dma-cells = <3>; 1362 1363 iommus = <&apps_smmu 0x576 0x0>; 1364 1365 status = "disabled"; 1366 }; 1367 1368 qup0: geniqup@9c0000 { 1369 compatible = "qcom,geni-se-qup"; 1370 reg = <0 0x009c0000 0 0x6000>; 1371 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1372 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1373 clock-names = "m-ahb", "s-ahb"; 1374 iommus = <&apps_smmu 0x563 0>; 1375 1376 #address-cells = <2>; 1377 #size-cells = <2>; 1378 ranges; 1379 1380 status = "disabled"; 1381 1382 i2c0: i2c@980000 { 1383 compatible = "qcom,geni-i2c"; 1384 reg = <0 0x00980000 0 0x4000>; 1385 #address-cells = <1>; 1386 #size-cells = <0>; 1387 clock-names = "se"; 1388 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1389 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1390 power-domains = <&rpmhpd SC8280XP_CX>; 1391 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1392 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1393 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1394 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1395 1396 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1397 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1398 dma-names = "tx", 1399 "rx"; 1400 1401 status = "disabled"; 1402 }; 1403 1404 spi0: spi@980000 { 1405 compatible = "qcom,geni-spi"; 1406 reg = <0 0x00980000 0 0x4000>; 1407 #address-cells = <1>; 1408 #size-cells = <0>; 1409 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1410 clock-names = "se"; 1411 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1412 power-domains = <&rpmhpd SC8280XP_CX>; 1413 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1414 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1415 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1416 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1417 1418 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1419 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1420 dma-names = "tx", 1421 "rx"; 1422 1423 status = "disabled"; 1424 }; 1425 1426 i2c1: i2c@984000 { 1427 compatible = "qcom,geni-i2c"; 1428 reg = <0 0x00984000 0 0x4000>; 1429 #address-cells = <1>; 1430 #size-cells = <0>; 1431 clock-names = "se"; 1432 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1433 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1434 power-domains = <&rpmhpd SC8280XP_CX>; 1435 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1436 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1437 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1438 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1439 1440 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1441 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1442 dma-names = "tx", 1443 "rx"; 1444 1445 status = "disabled"; 1446 }; 1447 1448 spi1: spi@984000 { 1449 compatible = "qcom,geni-spi"; 1450 reg = <0 0x00984000 0 0x4000>; 1451 #address-cells = <1>; 1452 #size-cells = <0>; 1453 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1454 clock-names = "se"; 1455 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1456 power-domains = <&rpmhpd SC8280XP_CX>; 1457 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1458 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1459 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1460 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1461 1462 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1463 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1464 dma-names = "tx", 1465 "rx"; 1466 1467 status = "disabled"; 1468 }; 1469 1470 i2c2: i2c@988000 { 1471 compatible = "qcom,geni-i2c"; 1472 reg = <0 0x00988000 0 0x4000>; 1473 #address-cells = <1>; 1474 #size-cells = <0>; 1475 clock-names = "se"; 1476 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1477 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1478 power-domains = <&rpmhpd SC8280XP_CX>; 1479 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1480 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1481 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1482 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1483 1484 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1485 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1486 dma-names = "tx", 1487 "rx"; 1488 1489 status = "disabled"; 1490 }; 1491 1492 spi2: spi@988000 { 1493 compatible = "qcom,geni-spi"; 1494 reg = <0 0x00988000 0 0x4000>; 1495 #address-cells = <1>; 1496 #size-cells = <0>; 1497 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1498 clock-names = "se"; 1499 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1500 power-domains = <&rpmhpd SC8280XP_CX>; 1501 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1502 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1503 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1504 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1505 1506 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1507 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1508 dma-names = "tx", 1509 "rx"; 1510 1511 status = "disabled"; 1512 }; 1513 1514 uart2: serial@988000 { 1515 compatible = "qcom,geni-uart"; 1516 reg = <0 0x00988000 0 0x4000>; 1517 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1518 clock-names = "se"; 1519 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1520 operating-points-v2 = <&qup_opp_table_100mhz>; 1521 power-domains = <&rpmhpd SC8280XP_CX>; 1522 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1523 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1524 interconnect-names = "qup-core", "qup-config"; 1525 status = "disabled"; 1526 }; 1527 1528 i2c3: i2c@98c000 { 1529 compatible = "qcom,geni-i2c"; 1530 reg = <0 0x0098c000 0 0x4000>; 1531 #address-cells = <1>; 1532 #size-cells = <0>; 1533 clock-names = "se"; 1534 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1535 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1536 power-domains = <&rpmhpd SC8280XP_CX>; 1537 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1538 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1539 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1540 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1541 1542 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1543 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1544 dma-names = "tx", 1545 "rx"; 1546 1547 status = "disabled"; 1548 }; 1549 1550 spi3: spi@98c000 { 1551 compatible = "qcom,geni-spi"; 1552 reg = <0 0x0098c000 0 0x4000>; 1553 #address-cells = <1>; 1554 #size-cells = <0>; 1555 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1556 clock-names = "se"; 1557 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1558 power-domains = <&rpmhpd SC8280XP_CX>; 1559 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1560 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1561 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1562 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1563 1564 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1565 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1566 dma-names = "tx", 1567 "rx"; 1568 1569 status = "disabled"; 1570 }; 1571 1572 i2c4: i2c@990000 { 1573 compatible = "qcom,geni-i2c"; 1574 reg = <0 0x00990000 0 0x4000>; 1575 clock-names = "se"; 1576 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1577 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1578 #address-cells = <1>; 1579 #size-cells = <0>; 1580 power-domains = <&rpmhpd SC8280XP_CX>; 1581 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1582 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1583 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1584 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1585 1586 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1587 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1588 dma-names = "tx", 1589 "rx"; 1590 1591 status = "disabled"; 1592 }; 1593 1594 spi4: spi@990000 { 1595 compatible = "qcom,geni-spi"; 1596 reg = <0 0x00990000 0 0x4000>; 1597 #address-cells = <1>; 1598 #size-cells = <0>; 1599 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1600 clock-names = "se"; 1601 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1602 power-domains = <&rpmhpd SC8280XP_CX>; 1603 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1604 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1605 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1606 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1607 1608 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1609 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1610 dma-names = "tx", 1611 "rx"; 1612 1613 status = "disabled"; 1614 }; 1615 1616 i2c5: i2c@994000 { 1617 compatible = "qcom,geni-i2c"; 1618 reg = <0 0x00994000 0 0x4000>; 1619 #address-cells = <1>; 1620 #size-cells = <0>; 1621 clock-names = "se"; 1622 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1623 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1624 power-domains = <&rpmhpd SC8280XP_CX>; 1625 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1626 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1627 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1628 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1629 1630 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1631 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1632 dma-names = "tx", 1633 "rx"; 1634 1635 status = "disabled"; 1636 }; 1637 1638 spi5: spi@994000 { 1639 compatible = "qcom,geni-spi"; 1640 reg = <0 0x00994000 0 0x4000>; 1641 #address-cells = <1>; 1642 #size-cells = <0>; 1643 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1644 clock-names = "se"; 1645 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1646 power-domains = <&rpmhpd SC8280XP_CX>; 1647 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1648 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1649 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1650 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1651 1652 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1653 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1654 dma-names = "tx", 1655 "rx"; 1656 1657 status = "disabled"; 1658 }; 1659 1660 i2c6: i2c@998000 { 1661 compatible = "qcom,geni-i2c"; 1662 reg = <0 0x00998000 0 0x4000>; 1663 #address-cells = <1>; 1664 #size-cells = <0>; 1665 clock-names = "se"; 1666 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1667 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1668 power-domains = <&rpmhpd SC8280XP_CX>; 1669 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1670 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1671 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1672 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1673 1674 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1675 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1676 dma-names = "tx", 1677 "rx"; 1678 1679 status = "disabled"; 1680 }; 1681 1682 spi6: spi@998000 { 1683 compatible = "qcom,geni-spi"; 1684 reg = <0 0x00998000 0 0x4000>; 1685 #address-cells = <1>; 1686 #size-cells = <0>; 1687 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1688 clock-names = "se"; 1689 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1690 power-domains = <&rpmhpd SC8280XP_CX>; 1691 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1692 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1693 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1694 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1695 1696 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1697 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1698 dma-names = "tx", 1699 "rx"; 1700 1701 status = "disabled"; 1702 }; 1703 1704 i2c7: i2c@99c000 { 1705 compatible = "qcom,geni-i2c"; 1706 reg = <0 0x0099c000 0 0x4000>; 1707 #address-cells = <1>; 1708 #size-cells = <0>; 1709 clock-names = "se"; 1710 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1711 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1712 power-domains = <&rpmhpd SC8280XP_CX>; 1713 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1714 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1715 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1716 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1717 1718 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1719 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1720 dma-names = "tx", 1721 "rx"; 1722 1723 status = "disabled"; 1724 }; 1725 1726 spi7: spi@99c000 { 1727 compatible = "qcom,geni-spi"; 1728 reg = <0 0x0099c000 0 0x4000>; 1729 #address-cells = <1>; 1730 #size-cells = <0>; 1731 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1732 clock-names = "se"; 1733 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1734 power-domains = <&rpmhpd SC8280XP_CX>; 1735 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1736 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1737 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1738 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1739 1740 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1741 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1742 dma-names = "tx", 1743 "rx"; 1744 1745 status = "disabled"; 1746 }; 1747 }; 1748 1749 gpi_dma1: dma-controller@a00000 { 1750 compatible = "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma"; 1751 reg = <0 0x00a00000 0 0x60000>; 1752 1753 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1754 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1755 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1756 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1757 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1758 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1765 1766 dma-channels = <12>; 1767 dma-channel-mask = <0xfff>; 1768 #dma-cells = <3>; 1769 1770 iommus = <&apps_smmu 0x96 0x0>; 1771 1772 status = "disabled"; 1773 }; 1774 1775 qup1: geniqup@ac0000 { 1776 compatible = "qcom,geni-se-qup"; 1777 reg = <0 0x00ac0000 0 0x6000>; 1778 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1779 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1780 clock-names = "m-ahb", "s-ahb"; 1781 iommus = <&apps_smmu 0x83 0>; 1782 1783 #address-cells = <2>; 1784 #size-cells = <2>; 1785 ranges; 1786 1787 status = "disabled"; 1788 1789 i2c8: i2c@a80000 { 1790 compatible = "qcom,geni-i2c"; 1791 reg = <0 0x00a80000 0 0x4000>; 1792 #address-cells = <1>; 1793 #size-cells = <0>; 1794 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1795 clock-names = "se"; 1796 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1797 power-domains = <&rpmhpd SC8280XP_CX>; 1798 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1799 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1800 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1801 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1802 1803 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1804 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1805 dma-names = "tx", 1806 "rx"; 1807 1808 status = "disabled"; 1809 }; 1810 1811 spi8: spi@a80000 { 1812 compatible = "qcom,geni-spi"; 1813 reg = <0 0x00a80000 0 0x4000>; 1814 #address-cells = <1>; 1815 #size-cells = <0>; 1816 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1817 clock-names = "se"; 1818 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1819 power-domains = <&rpmhpd SC8280XP_CX>; 1820 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1821 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1822 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1823 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1824 1825 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1826 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1827 dma-names = "tx", 1828 "rx"; 1829 1830 status = "disabled"; 1831 }; 1832 1833 i2c9: i2c@a84000 { 1834 compatible = "qcom,geni-i2c"; 1835 reg = <0 0x00a84000 0 0x4000>; 1836 #address-cells = <1>; 1837 #size-cells = <0>; 1838 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1839 clock-names = "se"; 1840 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1841 power-domains = <&rpmhpd SC8280XP_CX>; 1842 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1843 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1844 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1845 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1846 1847 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1848 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1849 dma-names = "tx", 1850 "rx"; 1851 1852 status = "disabled"; 1853 }; 1854 1855 spi9: spi@a84000 { 1856 compatible = "qcom,geni-spi"; 1857 reg = <0 0x00a84000 0 0x4000>; 1858 #address-cells = <1>; 1859 #size-cells = <0>; 1860 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1861 clock-names = "se"; 1862 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1863 power-domains = <&rpmhpd SC8280XP_CX>; 1864 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1865 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1866 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1867 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1868 1869 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1870 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1871 dma-names = "tx", 1872 "rx"; 1873 1874 status = "disabled"; 1875 }; 1876 1877 i2c10: i2c@a88000 { 1878 compatible = "qcom,geni-i2c"; 1879 reg = <0 0x00a88000 0 0x4000>; 1880 #address-cells = <1>; 1881 #size-cells = <0>; 1882 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1883 clock-names = "se"; 1884 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1885 power-domains = <&rpmhpd SC8280XP_CX>; 1886 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1887 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1888 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1889 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1890 1891 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1892 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1893 dma-names = "tx", 1894 "rx"; 1895 1896 status = "disabled"; 1897 }; 1898 1899 spi10: spi@a88000 { 1900 compatible = "qcom,geni-spi"; 1901 reg = <0 0x00a88000 0 0x4000>; 1902 #address-cells = <1>; 1903 #size-cells = <0>; 1904 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1905 clock-names = "se"; 1906 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1907 power-domains = <&rpmhpd SC8280XP_CX>; 1908 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1909 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1910 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1911 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1912 1913 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1914 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1915 dma-names = "tx", 1916 "rx"; 1917 1918 status = "disabled"; 1919 }; 1920 1921 i2c11: i2c@a8c000 { 1922 compatible = "qcom,geni-i2c"; 1923 reg = <0 0x00a8c000 0 0x4000>; 1924 #address-cells = <1>; 1925 #size-cells = <0>; 1926 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1927 clock-names = "se"; 1928 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1929 power-domains = <&rpmhpd SC8280XP_CX>; 1930 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1931 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1932 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1933 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1934 1935 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1936 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1937 dma-names = "tx", 1938 "rx"; 1939 1940 status = "disabled"; 1941 }; 1942 1943 spi11: spi@a8c000 { 1944 compatible = "qcom,geni-spi"; 1945 reg = <0 0x00a8c000 0 0x4000>; 1946 #address-cells = <1>; 1947 #size-cells = <0>; 1948 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1949 clock-names = "se"; 1950 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1951 power-domains = <&rpmhpd SC8280XP_CX>; 1952 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1953 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1954 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1955 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1956 1957 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1958 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1959 dma-names = "tx", 1960 "rx"; 1961 1962 status = "disabled"; 1963 }; 1964 1965 i2c12: i2c@a90000 { 1966 compatible = "qcom,geni-i2c"; 1967 reg = <0 0x00a90000 0 0x4000>; 1968 #address-cells = <1>; 1969 #size-cells = <0>; 1970 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1971 clock-names = "se"; 1972 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1973 power-domains = <&rpmhpd SC8280XP_CX>; 1974 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1975 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1976 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1977 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1978 1979 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1980 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1981 dma-names = "tx", 1982 "rx"; 1983 1984 status = "disabled"; 1985 }; 1986 1987 spi12: spi@a90000 { 1988 compatible = "qcom,geni-spi"; 1989 reg = <0 0x00a90000 0 0x4000>; 1990 #address-cells = <1>; 1991 #size-cells = <0>; 1992 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1993 clock-names = "se"; 1994 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1995 power-domains = <&rpmhpd SC8280XP_CX>; 1996 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1997 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1998 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1999 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2000 2001 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 2002 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 2003 dma-names = "tx", 2004 "rx"; 2005 2006 status = "disabled"; 2007 }; 2008 2009 i2c13: i2c@a94000 { 2010 compatible = "qcom,geni-i2c"; 2011 reg = <0 0x00a94000 0 0x4000>; 2012 #address-cells = <1>; 2013 #size-cells = <0>; 2014 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2015 clock-names = "se"; 2016 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2017 power-domains = <&rpmhpd SC8280XP_CX>; 2018 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2019 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 2020 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2021 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2022 2023 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 2024 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 2025 dma-names = "tx", 2026 "rx"; 2027 2028 status = "disabled"; 2029 }; 2030 2031 spi13: spi@a94000 { 2032 compatible = "qcom,geni-spi"; 2033 reg = <0 0x00a94000 0 0x4000>; 2034 #address-cells = <1>; 2035 #size-cells = <0>; 2036 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2037 clock-names = "se"; 2038 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2039 power-domains = <&rpmhpd SC8280XP_CX>; 2040 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2041 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 2042 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2043 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2044 2045 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 2046 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 2047 dma-names = "tx", 2048 "rx"; 2049 2050 status = "disabled"; 2051 }; 2052 2053 i2c14: i2c@a98000 { 2054 compatible = "qcom,geni-i2c"; 2055 reg = <0 0x00a98000 0 0x4000>; 2056 #address-cells = <1>; 2057 #size-cells = <0>; 2058 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2059 clock-names = "se"; 2060 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 2061 power-domains = <&rpmhpd SC8280XP_CX>; 2062 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2063 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 2064 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2065 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2066 2067 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 2068 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 2069 dma-names = "tx", 2070 "rx"; 2071 2072 status = "disabled"; 2073 }; 2074 2075 spi14: spi@a98000 { 2076 compatible = "qcom,geni-spi"; 2077 reg = <0 0x00a98000 0 0x4000>; 2078 #address-cells = <1>; 2079 #size-cells = <0>; 2080 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2081 clock-names = "se"; 2082 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 2083 power-domains = <&rpmhpd SC8280XP_CX>; 2084 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2085 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 2086 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2087 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2088 2089 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2090 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2091 dma-names = "tx", 2092 "rx"; 2093 2094 status = "disabled"; 2095 }; 2096 2097 i2c15: i2c@a9c000 { 2098 compatible = "qcom,geni-i2c"; 2099 reg = <0 0x00a9c000 0 0x4000>; 2100 #address-cells = <1>; 2101 #size-cells = <0>; 2102 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2103 clock-names = "se"; 2104 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 2105 power-domains = <&rpmhpd SC8280XP_CX>; 2106 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2107 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 2108 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2109 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2110 2111 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2112 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2113 dma-names = "tx", 2114 "rx"; 2115 2116 status = "disabled"; 2117 }; 2118 2119 spi15: spi@a9c000 { 2120 compatible = "qcom,geni-spi"; 2121 reg = <0 0x00a9c000 0 0x4000>; 2122 #address-cells = <1>; 2123 #size-cells = <0>; 2124 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2125 clock-names = "se"; 2126 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 2127 power-domains = <&rpmhpd SC8280XP_CX>; 2128 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2129 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 2130 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2131 interconnect-names = "qup-core", "qup-config", "qup-memory"; 2132 2133 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2134 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2135 dma-names = "tx", 2136 "rx"; 2137 2138 status = "disabled"; 2139 }; 2140 }; 2141 2142 rng: rng@10d3000 { 2143 compatible = "qcom,prng-ee"; 2144 reg = <0 0x010d3000 0 0x1000>; 2145 clocks = <&rpmhcc RPMH_HWKM_CLK>; 2146 clock-names = "core"; 2147 }; 2148 2149 pcie4: pcie@1c00000 { 2150 device_type = "pci"; 2151 compatible = "qcom,pcie-sc8280xp"; 2152 reg = <0x0 0x01c00000 0x0 0x3000>, 2153 <0x0 0x30000000 0x0 0xf1d>, 2154 <0x0 0x30000f20 0x0 0xa8>, 2155 <0x0 0x30001000 0x0 0x1000>, 2156 <0x0 0x30100000 0x0 0x100000>, 2157 <0x0 0x01c03000 0x0 0x1000>; 2158 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2159 #address-cells = <3>; 2160 #size-cells = <2>; 2161 ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>, 2162 <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>; 2163 bus-range = <0x00 0xff>; 2164 2165 dma-coherent; 2166 2167 linux,pci-domain = <6>; 2168 num-lanes = <1>; 2169 2170 msi-map = <0x0 &its 0xe0000 0x10000>; 2171 2172 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2173 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2174 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2175 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 2176 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2177 2178 #interrupt-cells = <1>; 2179 interrupt-map-mask = <0 0 0 0x7>; 2180 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2181 <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 2182 <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 2183 <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 2184 2185 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 2186 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 2187 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 2188 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 2189 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 2190 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2191 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2192 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>, 2193 <&gcc GCC_CNOC_PCIE4_QX_CLK>; 2194 clock-names = "aux", 2195 "cfg", 2196 "bus_master", 2197 "bus_slave", 2198 "slave_q2a", 2199 "ddrss_sf_tbu", 2200 "noc_aggr_4", 2201 "noc_aggr_south_sf", 2202 "cnoc_qx"; 2203 2204 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 2205 assigned-clock-rates = <19200000>; 2206 2207 interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>, 2208 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>; 2209 interconnect-names = "pcie-mem", "cpu-pcie"; 2210 2211 resets = <&gcc GCC_PCIE_4_BCR>; 2212 reset-names = "pci"; 2213 2214 power-domains = <&gcc PCIE_4_GDSC>; 2215 required-opps = <&rpmhpd_opp_nom>; 2216 2217 phys = <&pcie4_phy>; 2218 phy-names = "pciephy"; 2219 2220 status = "disabled"; 2221 2222 pcie4_port0: pcie@0 { 2223 device_type = "pci"; 2224 reg = <0x0 0x0 0x0 0x0 0x0>; 2225 bus-range = <0x01 0xff>; 2226 2227 #address-cells = <3>; 2228 #size-cells = <2>; 2229 ranges; 2230 }; 2231 }; 2232 2233 pcie4_phy: phy@1c06000 { 2234 compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy"; 2235 reg = <0x0 0x01c06000 0x0 0x2000>; 2236 2237 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 2238 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 2239 <&gcc GCC_PCIE_4_CLKREF_CLK>, 2240 <&gcc GCC_PCIE4_PHY_RCHNG_CLK>, 2241 <&gcc GCC_PCIE_4_PIPE_CLK>, 2242 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; 2243 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2244 "pipe", "pipediv2"; 2245 2246 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>; 2247 assigned-clock-rates = <100000000>; 2248 2249 power-domains = <&gcc PCIE_4_GDSC>; 2250 2251 resets = <&gcc GCC_PCIE_4_PHY_BCR>; 2252 reset-names = "phy"; 2253 2254 #clock-cells = <0>; 2255 clock-output-names = "pcie_4_pipe_clk"; 2256 2257 #phy-cells = <0>; 2258 2259 status = "disabled"; 2260 }; 2261 2262 pcie3b: pcie@1c08000 { 2263 device_type = "pci"; 2264 compatible = "qcom,pcie-sc8280xp"; 2265 reg = <0x0 0x01c08000 0x0 0x3000>, 2266 <0x0 0x32000000 0x0 0xf1d>, 2267 <0x0 0x32000f20 0x0 0xa8>, 2268 <0x0 0x32001000 0x0 0x1000>, 2269 <0x0 0x32100000 0x0 0x100000>, 2270 <0x0 0x01c0b000 0x0 0x1000>; 2271 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2272 #address-cells = <3>; 2273 #size-cells = <2>; 2274 ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>, 2275 <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>; 2276 bus-range = <0x00 0xff>; 2277 2278 dma-coherent; 2279 2280 linux,pci-domain = <5>; 2281 num-lanes = <2>; 2282 2283 msi-map = <0x0 &its 0xd0000 0x10000>; 2284 2285 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2286 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2287 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2288 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2289 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2290 2291 #interrupt-cells = <1>; 2292 interrupt-map-mask = <0 0 0 0x7>; 2293 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, 2294 <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 2295 <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>, 2296 <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 2297 2298 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 2299 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 2300 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, 2301 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, 2302 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, 2303 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2304 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2305 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2306 clock-names = "aux", 2307 "cfg", 2308 "bus_master", 2309 "bus_slave", 2310 "slave_q2a", 2311 "ddrss_sf_tbu", 2312 "noc_aggr_4", 2313 "noc_aggr_south_sf"; 2314 2315 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>; 2316 assigned-clock-rates = <19200000>; 2317 2318 interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>, 2319 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>; 2320 interconnect-names = "pcie-mem", "cpu-pcie"; 2321 2322 resets = <&gcc GCC_PCIE_3B_BCR>; 2323 reset-names = "pci"; 2324 2325 power-domains = <&gcc PCIE_3B_GDSC>; 2326 required-opps = <&rpmhpd_opp_nom>; 2327 2328 phys = <&pcie3b_phy>; 2329 phy-names = "pciephy"; 2330 2331 status = "disabled"; 2332 2333 pcie3b_port0: pcie@0 { 2334 device_type = "pci"; 2335 reg = <0x0 0x0 0x0 0x0 0x0>; 2336 bus-range = <0x01 0xff>; 2337 2338 #address-cells = <3>; 2339 #size-cells = <2>; 2340 ranges; 2341 }; 2342 }; 2343 2344 pcie3b_phy: phy@1c0e000 { 2345 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 2346 reg = <0x0 0x01c0e000 0x0 0x2000>; 2347 2348 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 2349 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 2350 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 2351 <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>, 2352 <&gcc GCC_PCIE_3B_PIPE_CLK>, 2353 <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>; 2354 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2355 "pipe", "pipediv2"; 2356 2357 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>; 2358 assigned-clock-rates = <100000000>; 2359 2360 power-domains = <&gcc PCIE_3B_GDSC>; 2361 2362 resets = <&gcc GCC_PCIE_3B_PHY_BCR>; 2363 reset-names = "phy"; 2364 2365 #clock-cells = <0>; 2366 clock-output-names = "pcie_3b_pipe_clk"; 2367 2368 #phy-cells = <0>; 2369 2370 status = "disabled"; 2371 }; 2372 2373 pcie3a: pcie@1c10000 { 2374 device_type = "pci"; 2375 compatible = "qcom,pcie-sc8280xp"; 2376 reg = <0x0 0x01c10000 0x0 0x3000>, 2377 <0x0 0x34000000 0x0 0xf1d>, 2378 <0x0 0x34000f20 0x0 0xa8>, 2379 <0x0 0x34001000 0x0 0x1000>, 2380 <0x0 0x34100000 0x0 0x100000>, 2381 <0x0 0x01c13000 0x0 0x1000>; 2382 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2383 #address-cells = <3>; 2384 #size-cells = <2>; 2385 ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>, 2386 <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>; 2387 bus-range = <0x00 0xff>; 2388 2389 dma-coherent; 2390 2391 linux,pci-domain = <4>; 2392 num-lanes = <4>; 2393 2394 msi-map = <0x0 &its 0xc0000 0x10000>; 2395 2396 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2397 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2398 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2399 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 2400 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2401 2402 #interrupt-cells = <1>; 2403 interrupt-map-mask = <0 0 0 0x7>; 2404 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 2405 <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>, 2406 <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, 2407 <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>; 2408 2409 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 2410 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 2411 <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>, 2412 <&gcc GCC_PCIE_3A_SLV_AXI_CLK>, 2413 <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>, 2414 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2415 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2416 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2417 clock-names = "aux", 2418 "cfg", 2419 "bus_master", 2420 "bus_slave", 2421 "slave_q2a", 2422 "ddrss_sf_tbu", 2423 "noc_aggr_4", 2424 "noc_aggr_south_sf"; 2425 2426 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>; 2427 assigned-clock-rates = <19200000>; 2428 2429 interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>, 2430 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>; 2431 interconnect-names = "pcie-mem", "cpu-pcie"; 2432 2433 resets = <&gcc GCC_PCIE_3A_BCR>; 2434 reset-names = "pci"; 2435 2436 power-domains = <&gcc PCIE_3A_GDSC>; 2437 required-opps = <&rpmhpd_opp_nom>; 2438 2439 phys = <&pcie3a_phy>; 2440 phy-names = "pciephy"; 2441 2442 status = "disabled"; 2443 2444 pcie3a_port0: pcie@0 { 2445 device_type = "pci"; 2446 reg = <0x0 0x0 0x0 0x0 0x0>; 2447 bus-range = <0x01 0xff>; 2448 2449 #address-cells = <3>; 2450 #size-cells = <2>; 2451 ranges; 2452 }; 2453 }; 2454 2455 pcie3a_phy: phy@1c14000 { 2456 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 2457 reg = <0x0 0x01c14000 0x0 0x2000>, 2458 <0x0 0x01c16000 0x0 0x2000>; 2459 2460 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 2461 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 2462 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 2463 <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>, 2464 <&gcc GCC_PCIE_3A_PIPE_CLK>, 2465 <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>; 2466 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2467 "pipe", "pipediv2"; 2468 2469 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>; 2470 assigned-clock-rates = <100000000>; 2471 2472 power-domains = <&gcc PCIE_3A_GDSC>; 2473 2474 resets = <&gcc GCC_PCIE_3A_PHY_BCR>; 2475 reset-names = "phy"; 2476 2477 qcom,4ln-config-sel = <&tcsr 0xa044 1>; 2478 2479 #clock-cells = <0>; 2480 clock-output-names = "pcie_3a_pipe_clk"; 2481 2482 #phy-cells = <0>; 2483 2484 status = "disabled"; 2485 }; 2486 2487 pcie2b: pcie@1c18000 { 2488 device_type = "pci"; 2489 compatible = "qcom,pcie-sc8280xp"; 2490 reg = <0x0 0x01c18000 0x0 0x3000>, 2491 <0x0 0x38000000 0x0 0xf1d>, 2492 <0x0 0x38000f20 0x0 0xa8>, 2493 <0x0 0x38001000 0x0 0x1000>, 2494 <0x0 0x38100000 0x0 0x100000>, 2495 <0x0 0x01c1b000 0x0 0x1000>; 2496 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2497 #address-cells = <3>; 2498 #size-cells = <2>; 2499 ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>, 2500 <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>; 2501 bus-range = <0x00 0xff>; 2502 2503 dma-coherent; 2504 2505 linux,pci-domain = <3>; 2506 num-lanes = <2>; 2507 2508 msi-map = <0x0 &its 0xb0000 0x10000>; 2509 2510 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 2511 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2512 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2513 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 2514 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2515 2516 #interrupt-cells = <1>; 2517 interrupt-map-mask = <0 0 0 0x7>; 2518 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2519 <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 2520 <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 2521 <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; 2522 2523 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2524 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2525 <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>, 2526 <&gcc GCC_PCIE_2B_SLV_AXI_CLK>, 2527 <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>, 2528 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2529 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2530 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2531 clock-names = "aux", 2532 "cfg", 2533 "bus_master", 2534 "bus_slave", 2535 "slave_q2a", 2536 "ddrss_sf_tbu", 2537 "noc_aggr_4", 2538 "noc_aggr_south_sf"; 2539 2540 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>; 2541 assigned-clock-rates = <19200000>; 2542 2543 interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>, 2544 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>; 2545 interconnect-names = "pcie-mem", "cpu-pcie"; 2546 2547 resets = <&gcc GCC_PCIE_2B_BCR>; 2548 reset-names = "pci"; 2549 2550 power-domains = <&gcc PCIE_2B_GDSC>; 2551 required-opps = <&rpmhpd_opp_nom>; 2552 2553 phys = <&pcie2b_phy>; 2554 phy-names = "pciephy"; 2555 2556 status = "disabled"; 2557 2558 pcie2b_port0: pcie@0 { 2559 device_type = "pci"; 2560 reg = <0x0 0x0 0x0 0x0 0x0>; 2561 bus-range = <0x01 0xff>; 2562 2563 #address-cells = <3>; 2564 #size-cells = <2>; 2565 ranges; 2566 }; 2567 }; 2568 2569 pcie2b_phy: phy@1c1e000 { 2570 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 2571 reg = <0x0 0x01c1e000 0x0 0x2000>; 2572 2573 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2574 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2575 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2576 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>, 2577 <&gcc GCC_PCIE_2B_PIPE_CLK>, 2578 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>; 2579 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2580 "pipe", "pipediv2"; 2581 2582 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>; 2583 assigned-clock-rates = <100000000>; 2584 2585 power-domains = <&gcc PCIE_2B_GDSC>; 2586 2587 resets = <&gcc GCC_PCIE_2B_PHY_BCR>; 2588 reset-names = "phy"; 2589 2590 #clock-cells = <0>; 2591 clock-output-names = "pcie_2b_pipe_clk"; 2592 2593 #phy-cells = <0>; 2594 2595 status = "disabled"; 2596 }; 2597 2598 pcie2a: pcie@1c20000 { 2599 device_type = "pci"; 2600 compatible = "qcom,pcie-sc8280xp"; 2601 reg = <0x0 0x01c20000 0x0 0x3000>, 2602 <0x0 0x3c000000 0x0 0xf1d>, 2603 <0x0 0x3c000f20 0x0 0xa8>, 2604 <0x0 0x3c001000 0x0 0x1000>, 2605 <0x0 0x3c100000 0x0 0x100000>, 2606 <0x0 0x01c23000 0x0 0x1000>; 2607 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2608 #address-cells = <3>; 2609 #size-cells = <2>; 2610 ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>, 2611 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>; 2612 bus-range = <0x00 0xff>; 2613 2614 dma-coherent; 2615 2616 linux,pci-domain = <2>; 2617 num-lanes = <4>; 2618 2619 msi-map = <0x0 &its 0xa0000 0x10000>; 2620 2621 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 2622 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, 2623 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, 2624 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>; 2625 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2626 2627 #interrupt-cells = <1>; 2628 interrupt-map-mask = <0 0 0 0x7>; 2629 interrupt-map = <0 0 0 1 &intc 0 GIC_SPI GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 2630 <0 0 0 2 &intc 0 GIC_SPI GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 2631 <0 0 0 3 &intc 0 GIC_SPI GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 2632 <0 0 0 4 &intc 0 GIC_SPI GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; 2633 2634 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2635 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2636 <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>, 2637 <&gcc GCC_PCIE_2A_SLV_AXI_CLK>, 2638 <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>, 2639 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2640 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2641 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2642 clock-names = "aux", 2643 "cfg", 2644 "bus_master", 2645 "bus_slave", 2646 "slave_q2a", 2647 "ddrss_sf_tbu", 2648 "noc_aggr_4", 2649 "noc_aggr_south_sf"; 2650 2651 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>; 2652 assigned-clock-rates = <19200000>; 2653 2654 interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>, 2655 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>; 2656 interconnect-names = "pcie-mem", "cpu-pcie"; 2657 2658 resets = <&gcc GCC_PCIE_2A_BCR>; 2659 reset-names = "pci"; 2660 2661 power-domains = <&gcc PCIE_2A_GDSC>; 2662 required-opps = <&rpmhpd_opp_nom>; 2663 2664 phys = <&pcie2a_phy>; 2665 phy-names = "pciephy"; 2666 2667 status = "disabled"; 2668 2669 pcie2a_port0: pcie@0 { 2670 device_type = "pci"; 2671 reg = <0x0 0x0 0x0 0x0 0x0>; 2672 bus-range = <0x01 0xff>; 2673 2674 #address-cells = <3>; 2675 #size-cells = <2>; 2676 ranges; 2677 }; 2678 }; 2679 2680 pcie2a_phy: phy@1c24000 { 2681 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 2682 reg = <0x0 0x01c24000 0x0 0x2000>, 2683 <0x0 0x01c26000 0x0 0x2000>; 2684 2685 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2686 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2687 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2688 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>, 2689 <&gcc GCC_PCIE_2A_PIPE_CLK>, 2690 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>; 2691 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2692 "pipe", "pipediv2"; 2693 2694 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>; 2695 assigned-clock-rates = <100000000>; 2696 2697 power-domains = <&gcc PCIE_2A_GDSC>; 2698 2699 resets = <&gcc GCC_PCIE_2A_PHY_BCR>; 2700 reset-names = "phy"; 2701 2702 qcom,4ln-config-sel = <&tcsr 0xa044 0>; 2703 2704 #clock-cells = <0>; 2705 clock-output-names = "pcie_2a_pipe_clk"; 2706 2707 #phy-cells = <0>; 2708 2709 status = "disabled"; 2710 }; 2711 2712 ufs_mem_hc: ufshc@1d84000 { 2713 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2714 "jedec,ufs-2.0"; 2715 reg = <0 0x01d84000 0 0x3000>; 2716 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2717 phys = <&ufs_mem_phy>; 2718 phy-names = "ufsphy"; 2719 lanes-per-direction = <2>; 2720 #reset-cells = <1>; 2721 resets = <&gcc GCC_UFS_PHY_BCR>; 2722 reset-names = "rst"; 2723 2724 power-domains = <&gcc UFS_PHY_GDSC>; 2725 required-opps = <&rpmhpd_opp_nom>; 2726 2727 iommus = <&apps_smmu 0xe0 0x0>; 2728 dma-coherent; 2729 2730 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2731 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2732 <&gcc GCC_UFS_PHY_AHB_CLK>, 2733 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2734 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2735 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2736 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2737 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2738 clock-names = "core_clk", 2739 "bus_aggr_clk", 2740 "iface_clk", 2741 "core_clk_unipro", 2742 "ref_clk", 2743 "tx_lane0_sync_clk", 2744 "rx_lane0_sync_clk", 2745 "rx_lane1_sync_clk"; 2746 freq-table-hz = <75000000 300000000>, 2747 <0 0>, 2748 <0 0>, 2749 <75000000 300000000>, 2750 <0 0>, 2751 <0 0>, 2752 <0 0>, 2753 <0 0>; 2754 status = "disabled"; 2755 }; 2756 2757 ufs_mem_phy: phy@1d87000 { 2758 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2759 reg = <0 0x01d87000 0 0x1000>; 2760 2761 clocks = <&rpmhcc RPMH_CXO_CLK>, 2762 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2763 <&gcc GCC_UFS_CARD_CLKREF_CLK>; 2764 clock-names = "ref", 2765 "ref_aux", 2766 "qref"; 2767 2768 power-domains = <&gcc UFS_PHY_GDSC>; 2769 2770 resets = <&ufs_mem_hc 0>; 2771 reset-names = "ufsphy"; 2772 2773 #phy-cells = <0>; 2774 2775 status = "disabled"; 2776 }; 2777 2778 ufs_card_hc: ufshc@1da4000 { 2779 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2780 "jedec,ufs-2.0"; 2781 reg = <0 0x01da4000 0 0x3000>; 2782 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2783 phys = <&ufs_card_phy>; 2784 phy-names = "ufsphy"; 2785 lanes-per-direction = <2>; 2786 #reset-cells = <1>; 2787 resets = <&gcc GCC_UFS_CARD_BCR>; 2788 reset-names = "rst"; 2789 2790 power-domains = <&gcc UFS_CARD_GDSC>; 2791 2792 iommus = <&apps_smmu 0x4a0 0x0>; 2793 dma-coherent; 2794 2795 clocks = <&gcc GCC_UFS_CARD_AXI_CLK>, 2796 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, 2797 <&gcc GCC_UFS_CARD_AHB_CLK>, 2798 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>, 2799 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2800 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>, 2801 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>, 2802 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>; 2803 clock-names = "core_clk", 2804 "bus_aggr_clk", 2805 "iface_clk", 2806 "core_clk_unipro", 2807 "ref_clk", 2808 "tx_lane0_sync_clk", 2809 "rx_lane0_sync_clk", 2810 "rx_lane1_sync_clk"; 2811 freq-table-hz = <75000000 300000000>, 2812 <0 0>, 2813 <0 0>, 2814 <75000000 300000000>, 2815 <0 0>, 2816 <0 0>, 2817 <0 0>, 2818 <0 0>; 2819 status = "disabled"; 2820 }; 2821 2822 ufs_card_phy: phy@1da7000 { 2823 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2824 reg = <0 0x01da7000 0 0x1000>; 2825 2826 clocks = <&rpmhcc RPMH_CXO_CLK>, 2827 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>, 2828 <&gcc GCC_UFS_1_CARD_CLKREF_CLK>; 2829 clock-names = "ref", 2830 "ref_aux", 2831 "qref"; 2832 2833 power-domains = <&gcc UFS_CARD_GDSC>; 2834 2835 resets = <&ufs_card_hc 0>; 2836 reset-names = "ufsphy"; 2837 2838 #phy-cells = <0>; 2839 2840 status = "disabled"; 2841 }; 2842 2843 tcsr_mutex: hwlock@1f40000 { 2844 compatible = "qcom,tcsr-mutex"; 2845 reg = <0x0 0x01f40000 0x0 0x20000>; 2846 #hwlock-cells = <1>; 2847 }; 2848 2849 tcsr: syscon@1fc0000 { 2850 compatible = "qcom,sc8280xp-tcsr", "syscon"; 2851 reg = <0x0 0x01fc0000 0x0 0x30000>; 2852 }; 2853 2854 remoteproc_slpi: remoteproc@2400000 { 2855 compatible = "qcom,sc8280xp-slpi-pas", "qcom,sm8350-slpi-pas"; 2856 reg = <0 0x02400000 0 0x10000>; 2857 2858 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2859 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2860 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2861 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2862 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2863 interrupt-names = "wdog", 2864 "fatal", 2865 "ready", 2866 "handover", 2867 "stop-ack"; 2868 2869 clocks = <&rpmhcc RPMH_CXO_CLK>; 2870 clock-names = "xo"; 2871 2872 power-domains = <&rpmhpd SC8280XP_LCX>, 2873 <&rpmhpd SC8280XP_LMX>; 2874 power-domain-names = "lcx", "lmx"; 2875 2876 memory-region = <&pil_slpi_mem>; 2877 2878 qcom,qmp = <&aoss_qmp>; 2879 2880 qcom,smem-states = <&smp2p_slpi_out 0>; 2881 qcom,smem-state-names = "stop"; 2882 2883 status = "disabled"; 2884 2885 glink-edge { 2886 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2887 IPCC_MPROC_SIGNAL_GLINK_QMP 2888 IRQ_TYPE_EDGE_RISING>; 2889 mboxes = <&ipcc IPCC_CLIENT_SLPI 2890 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2891 2892 label = "slpi"; 2893 qcom,remote-pid = <3>; 2894 2895 fastrpc { 2896 compatible = "qcom,fastrpc"; 2897 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2898 label = "sdsp"; 2899 qcom,non-secure-domain; 2900 #address-cells = <1>; 2901 #size-cells = <0>; 2902 2903 compute-cb@1 { 2904 compatible = "qcom,fastrpc-compute-cb"; 2905 reg = <1>; 2906 iommus = <&apps_smmu 0x0521 0x0>; 2907 }; 2908 2909 compute-cb@2 { 2910 compatible = "qcom,fastrpc-compute-cb"; 2911 reg = <2>; 2912 iommus = <&apps_smmu 0x0522 0x0>; 2913 }; 2914 2915 compute-cb@3 { 2916 compatible = "qcom,fastrpc-compute-cb"; 2917 reg = <3>; 2918 iommus = <&apps_smmu 0x0523 0x0>; 2919 }; 2920 }; 2921 }; 2922 }; 2923 2924 remoteproc_adsp: remoteproc@3000000 { 2925 compatible = "qcom,sc8280xp-adsp-pas"; 2926 reg = <0 0x03000000 0 0x10000>; 2927 2928 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2929 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2930 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2931 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2932 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, 2933 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; 2934 interrupt-names = "wdog", "fatal", "ready", 2935 "handover", "stop-ack", "shutdown-ack"; 2936 2937 clocks = <&rpmhcc RPMH_CXO_CLK>; 2938 clock-names = "xo"; 2939 2940 power-domains = <&rpmhpd SC8280XP_LCX>, 2941 <&rpmhpd SC8280XP_LMX>; 2942 power-domain-names = "lcx", "lmx"; 2943 2944 memory-region = <&pil_adsp_mem>; 2945 2946 qcom,qmp = <&aoss_qmp>; 2947 2948 qcom,smem-states = <&smp2p_adsp_out 0>; 2949 qcom,smem-state-names = "stop"; 2950 2951 status = "disabled"; 2952 2953 remoteproc_adsp_glink: glink-edge { 2954 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2955 IPCC_MPROC_SIGNAL_GLINK_QMP 2956 IRQ_TYPE_EDGE_RISING>; 2957 mboxes = <&ipcc IPCC_CLIENT_LPASS 2958 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2959 2960 label = "lpass"; 2961 qcom,remote-pid = <2>; 2962 2963 gpr { 2964 compatible = "qcom,gpr"; 2965 qcom,glink-channels = "adsp_apps"; 2966 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2967 qcom,intents = <512 20>; 2968 #address-cells = <1>; 2969 #size-cells = <0>; 2970 2971 q6apm: service@1 { 2972 compatible = "qcom,q6apm"; 2973 reg = <GPR_APM_MODULE_IID>; 2974 #sound-dai-cells = <0>; 2975 qcom,protection-domain = "avs/audio", 2976 "msm/adsp/audio_pd"; 2977 q6apmdai: dais { 2978 compatible = "qcom,q6apm-dais"; 2979 iommus = <&apps_smmu 0x0c01 0x0>; 2980 }; 2981 2982 q6apmbedai: bedais { 2983 compatible = "qcom,q6apm-lpass-dais"; 2984 #sound-dai-cells = <1>; 2985 }; 2986 }; 2987 2988 q6prm: service@2 { 2989 compatible = "qcom,q6prm"; 2990 reg = <GPR_PRM_MODULE_IID>; 2991 qcom,protection-domain = "avs/audio", 2992 "msm/adsp/audio_pd"; 2993 q6prmcc: clock-controller { 2994 compatible = "qcom,q6prm-lpass-clocks"; 2995 #clock-cells = <2>; 2996 }; 2997 }; 2998 }; 2999 }; 3000 }; 3001 3002 rxmacro: rxmacro@3200000 { 3003 compatible = "qcom,sc8280xp-lpass-rx-macro"; 3004 reg = <0 0x03200000 0 0x1000>; 3005 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3006 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3007 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3008 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3009 <&vamacro>; 3010 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 3011 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3012 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3013 assigned-clock-rates = <19200000>, <19200000>; 3014 3015 clock-output-names = "mclk"; 3016 #clock-cells = <0>; 3017 #sound-dai-cells = <1>; 3018 3019 pinctrl-names = "default"; 3020 pinctrl-0 = <&rx_swr_default>; 3021 3022 status = "disabled"; 3023 }; 3024 3025 swr1: soundwire@3210000 { 3026 compatible = "qcom,soundwire-v1.6.0"; 3027 reg = <0 0x03210000 0 0x2000>; 3028 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 3029 clocks = <&rxmacro>; 3030 clock-names = "iface"; 3031 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 3032 reset-names = "swr_audio_cgcr"; 3033 label = "RX"; 3034 3035 qcom,din-ports = <0>; 3036 qcom,dout-ports = <5>; 3037 3038 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 3039 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; 3040 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; 3041 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>; 3042 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>; 3043 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 3044 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>; 3045 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 3046 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 3047 3048 #sound-dai-cells = <1>; 3049 #address-cells = <2>; 3050 #size-cells = <0>; 3051 3052 status = "disabled"; 3053 }; 3054 3055 txmacro: txmacro@3220000 { 3056 compatible = "qcom,sc8280xp-lpass-tx-macro"; 3057 reg = <0 0x03220000 0 0x1000>; 3058 pinctrl-names = "default"; 3059 pinctrl-0 = <&tx_swr_default>; 3060 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3061 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3062 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3063 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3064 <&vamacro>; 3065 3066 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 3067 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3068 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3069 assigned-clock-rates = <19200000>, <19200000>; 3070 clock-output-names = "mclk"; 3071 3072 #clock-cells = <0>; 3073 #sound-dai-cells = <1>; 3074 3075 status = "disabled"; 3076 }; 3077 3078 wsamacro: codec@3240000 { 3079 compatible = "qcom,sc8280xp-lpass-wsa-macro"; 3080 reg = <0 0x03240000 0 0x1000>; 3081 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3082 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3083 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3084 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3085 <&vamacro>; 3086 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 3087 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3088 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3089 assigned-clock-rates = <19200000>, <19200000>; 3090 3091 #clock-cells = <0>; 3092 clock-output-names = "mclk"; 3093 #sound-dai-cells = <1>; 3094 3095 pinctrl-names = "default"; 3096 pinctrl-0 = <&wsa_swr_default>; 3097 3098 status = "disabled"; 3099 }; 3100 3101 swr0: soundwire@3250000 { 3102 reg = <0 0x03250000 0 0x2000>; 3103 compatible = "qcom,soundwire-v1.6.0"; 3104 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 3105 clocks = <&wsamacro>; 3106 clock-names = "iface"; 3107 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; 3108 reset-names = "swr_audio_cgcr"; 3109 label = "WSA"; 3110 3111 qcom,din-ports = <2>; 3112 qcom,dout-ports = <6>; 3113 3114 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 3115 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 3116 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 3117 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3118 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3119 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3120 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 3121 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3122 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 3123 3124 #sound-dai-cells = <1>; 3125 #address-cells = <2>; 3126 #size-cells = <0>; 3127 3128 status = "disabled"; 3129 }; 3130 3131 lpass_audiocc: clock-controller@32a9000 { 3132 compatible = "qcom,sc8280xp-lpassaudiocc"; 3133 reg = <0 0x032a9000 0 0x1000>; 3134 #clock-cells = <1>; 3135 #reset-cells = <1>; 3136 }; 3137 3138 swr2: soundwire@3330000 { 3139 compatible = "qcom,soundwire-v1.6.0"; 3140 reg = <0 0x03330000 0 0x2000>; 3141 interrupts = <GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>, 3142 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 3143 interrupt-names = "core", "wakeup"; 3144 3145 clocks = <&txmacro>; 3146 clock-names = "iface"; 3147 resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; 3148 reset-names = "swr_audio_cgcr"; 3149 label = "TX"; 3150 #sound-dai-cells = <1>; 3151 #address-cells = <2>; 3152 #size-cells = <0>; 3153 3154 qcom,din-ports = <4>; 3155 qcom,dout-ports = <0>; 3156 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 3157 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>; 3158 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 3159 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 3160 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 3161 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 3162 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 3163 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 3164 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>; 3165 3166 status = "disabled"; 3167 }; 3168 3169 vamacro: codec@3370000 { 3170 compatible = "qcom,sc8280xp-lpass-va-macro"; 3171 reg = <0 0x03370000 0 0x1000>; 3172 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3173 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3174 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3175 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3176 clock-names = "mclk", "macro", "dcodec", "npl"; 3177 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3178 assigned-clock-rates = <19200000>; 3179 3180 #clock-cells = <0>; 3181 clock-output-names = "fsgen"; 3182 #sound-dai-cells = <1>; 3183 3184 status = "disabled"; 3185 }; 3186 3187 lpass_tlmm: pinctrl@33c0000 { 3188 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl"; 3189 reg = <0 0x33c0000 0x0 0x20000>, 3190 <0 0x3550000 0x0 0x10000>; 3191 gpio-controller; 3192 #gpio-cells = <2>; 3193 gpio-ranges = <&lpass_tlmm 0 0 19>; 3194 3195 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3196 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3197 clock-names = "core", "audio"; 3198 3199 status = "disabled"; 3200 3201 tx_swr_default: tx-swr-default-state { 3202 clk-pins { 3203 pins = "gpio0"; 3204 function = "swr_tx_clk"; 3205 drive-strength = <2>; 3206 slew-rate = <1>; 3207 bias-disable; 3208 }; 3209 3210 data-pins { 3211 pins = "gpio1", "gpio2"; 3212 function = "swr_tx_data"; 3213 drive-strength = <2>; 3214 slew-rate = <1>; 3215 bias-bus-hold; 3216 }; 3217 }; 3218 3219 rx_swr_default: rx-swr-default-state { 3220 clk-pins { 3221 pins = "gpio3"; 3222 function = "swr_rx_clk"; 3223 drive-strength = <2>; 3224 slew-rate = <1>; 3225 bias-disable; 3226 }; 3227 3228 data-pins { 3229 pins = "gpio4", "gpio5"; 3230 function = "swr_rx_data"; 3231 drive-strength = <2>; 3232 slew-rate = <1>; 3233 bias-bus-hold; 3234 }; 3235 }; 3236 3237 dmic01_default: dmic01-default-state { 3238 clk-pins { 3239 pins = "gpio6"; 3240 function = "dmic1_clk"; 3241 drive-strength = <8>; 3242 output-high; 3243 }; 3244 3245 data-pins { 3246 pins = "gpio7"; 3247 function = "dmic1_data"; 3248 drive-strength = <8>; 3249 input-enable; 3250 }; 3251 }; 3252 3253 dmic01_sleep: dmic01-sleep-state { 3254 clk-pins { 3255 pins = "gpio6"; 3256 function = "dmic1_clk"; 3257 drive-strength = <2>; 3258 bias-disable; 3259 output-low; 3260 }; 3261 3262 data-pins { 3263 pins = "gpio7"; 3264 function = "dmic1_data"; 3265 drive-strength = <2>; 3266 bias-pull-down; 3267 input-enable; 3268 }; 3269 }; 3270 3271 dmic23_default: dmic23-default-state { 3272 clk-pins { 3273 pins = "gpio8"; 3274 function = "dmic2_clk"; 3275 drive-strength = <8>; 3276 output-high; 3277 }; 3278 3279 data-pins { 3280 pins = "gpio9"; 3281 function = "dmic2_data"; 3282 drive-strength = <8>; 3283 input-enable; 3284 }; 3285 }; 3286 3287 dmic23_sleep: dmic23-sleep-state { 3288 clk-pins { 3289 pins = "gpio8"; 3290 function = "dmic2_clk"; 3291 drive-strength = <2>; 3292 bias-disable; 3293 output-low; 3294 }; 3295 3296 data-pins { 3297 pins = "gpio9"; 3298 function = "dmic2_data"; 3299 drive-strength = <2>; 3300 bias-pull-down; 3301 input-enable; 3302 }; 3303 }; 3304 3305 wsa_swr_default: wsa-swr-default-state { 3306 clk-pins { 3307 pins = "gpio10"; 3308 function = "wsa_swr_clk"; 3309 drive-strength = <2>; 3310 slew-rate = <1>; 3311 bias-disable; 3312 }; 3313 3314 data-pins { 3315 pins = "gpio11"; 3316 function = "wsa_swr_data"; 3317 drive-strength = <2>; 3318 slew-rate = <1>; 3319 bias-bus-hold; 3320 }; 3321 }; 3322 3323 wsa2_swr_default: wsa2-swr-default-state { 3324 clk-pins { 3325 pins = "gpio15"; 3326 function = "wsa2_swr_clk"; 3327 drive-strength = <2>; 3328 slew-rate = <1>; 3329 bias-disable; 3330 }; 3331 3332 data-pins { 3333 pins = "gpio16"; 3334 function = "wsa2_swr_data"; 3335 drive-strength = <2>; 3336 slew-rate = <1>; 3337 bias-bus-hold; 3338 }; 3339 }; 3340 }; 3341 3342 lpasscc: clock-controller@33e0000 { 3343 compatible = "qcom,sc8280xp-lpasscc"; 3344 reg = <0 0x033e0000 0 0x12000>; 3345 #clock-cells = <1>; 3346 #reset-cells = <1>; 3347 }; 3348 3349 gpu: gpu@3d00000 { 3350 compatible = "qcom,adreno-690.0", "qcom,adreno"; 3351 3352 reg = <0 0x03d00000 0 0x40000>, 3353 <0 0x03d9e000 0 0x1000>, 3354 <0 0x03d61000 0 0x800>; 3355 reg-names = "kgsl_3d0_reg_memory", 3356 "cx_mem", 3357 "cx_dbgc"; 3358 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 3359 iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>; 3360 operating-points-v2 = <&gpu_opp_table>; 3361 3362 qcom,gmu = <&gmu>; 3363 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 3364 interconnect-names = "gfx-mem"; 3365 #cooling-cells = <2>; 3366 3367 status = "disabled"; 3368 3369 gpu_opp_table: opp-table { 3370 compatible = "operating-points-v2"; 3371 3372 opp-270000000 { 3373 opp-hz = /bits/ 64 <270000000>; 3374 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3375 opp-peak-kBps = <451000>; 3376 }; 3377 3378 opp-410000000 { 3379 opp-hz = /bits/ 64 <410000000>; 3380 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3381 opp-peak-kBps = <1555000>; 3382 }; 3383 3384 opp-500000000 { 3385 opp-hz = /bits/ 64 <500000000>; 3386 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3387 opp-peak-kBps = <1555000>; 3388 }; 3389 3390 opp-547000000 { 3391 opp-hz = /bits/ 64 <547000000>; 3392 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 3393 opp-peak-kBps = <1555000>; 3394 }; 3395 3396 opp-606000000 { 3397 opp-hz = /bits/ 64 <606000000>; 3398 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3399 opp-peak-kBps = <2736000>; 3400 }; 3401 3402 opp-640000000 { 3403 opp-hz = /bits/ 64 <640000000>; 3404 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3405 opp-peak-kBps = <2736000>; 3406 }; 3407 3408 opp-655000000 { 3409 opp-hz = /bits/ 64 <655000000>; 3410 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3411 opp-peak-kBps = <2736000>; 3412 }; 3413 3414 opp-690000000 { 3415 opp-hz = /bits/ 64 <690000000>; 3416 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3417 opp-peak-kBps = <2736000>; 3418 }; 3419 }; 3420 }; 3421 3422 gmu: gmu@3d6a000 { 3423 compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu"; 3424 reg = <0 0x03d6a000 0 0x34000>, 3425 <0 0x03de0000 0 0x10000>, 3426 <0 0x0b290000 0 0x10000>; 3427 reg-names = "gmu", "rscc", "gmu_pdc"; 3428 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 3429 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 3430 interrupt-names = "hfi", "gmu"; 3431 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 3432 <&gpucc GPU_CC_CXO_CLK>, 3433 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 3434 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3435 <&gpucc GPU_CC_AHB_CLK>, 3436 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3437 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 3438 clock-names = "gmu", 3439 "cxo", 3440 "axi", 3441 "memnoc", 3442 "ahb", 3443 "hub", 3444 "smmu_vote"; 3445 power-domains = <&gpucc GPU_CC_CX_GDSC>, 3446 <&gpucc GPU_CC_GX_GDSC>; 3447 power-domain-names = "cx", 3448 "gx"; 3449 iommus = <&gpu_smmu 5 0xc00>; 3450 operating-points-v2 = <&gmu_opp_table>; 3451 3452 gmu_opp_table: opp-table { 3453 compatible = "operating-points-v2"; 3454 3455 opp-200000000 { 3456 opp-hz = /bits/ 64 <200000000>; 3457 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3458 }; 3459 3460 opp-500000000 { 3461 opp-hz = /bits/ 64 <500000000>; 3462 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3463 }; 3464 }; 3465 }; 3466 3467 gpucc: clock-controller@3d90000 { 3468 compatible = "qcom,sc8280xp-gpucc"; 3469 reg = <0 0x03d90000 0 0x9000>; 3470 clocks = <&rpmhcc RPMH_CXO_CLK>, 3471 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3472 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3473 clock-names = "bi_tcxo", 3474 "gcc_gpu_gpll0_clk_src", 3475 "gcc_gpu_gpll0_div_clk_src"; 3476 3477 power-domains = <&rpmhpd SC8280XP_GFX>; 3478 #clock-cells = <1>; 3479 #reset-cells = <1>; 3480 #power-domain-cells = <1>; 3481 }; 3482 3483 gpu_smmu: iommu@3da0000 { 3484 compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu", 3485 "qcom,smmu-500", "arm,mmu-500"; 3486 reg = <0 0x03da0000 0 0x20000>; 3487 #iommu-cells = <2>; 3488 #global-interrupts = <2>; 3489 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 3490 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 3491 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 3492 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 3493 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 3494 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 3495 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 3496 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 3497 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 3498 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 3499 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 3500 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 3501 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, 3502 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>; 3503 3504 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3505 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 3506 <&gpucc GPU_CC_AHB_CLK>, 3507 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 3508 <&gpucc GPU_CC_CX_GMU_CLK>, 3509 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3510 <&gpucc GPU_CC_HUB_AON_CLK>; 3511 clock-names = "gcc_gpu_memnoc_gfx_clk", 3512 "gcc_gpu_snoc_dvm_gfx_clk", 3513 "gpu_cc_ahb_clk", 3514 "gpu_cc_hlos1_vote_gpu_smmu_clk", 3515 "gpu_cc_cx_gmu_clk", 3516 "gpu_cc_hub_cx_int_clk", 3517 "gpu_cc_hub_aon_clk"; 3518 3519 power-domains = <&gpucc GPU_CC_CX_GDSC>; 3520 dma-coherent; 3521 }; 3522 3523 sdc2: mmc@8804000 { 3524 compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5"; 3525 reg = <0 0x08804000 0 0x1000>; 3526 3527 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3528 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3529 interrupt-names = "hc_irq", "pwr_irq"; 3530 3531 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3532 <&gcc GCC_SDCC2_APPS_CLK>, 3533 <&rpmhcc RPMH_CXO_CLK>; 3534 clock-names = "iface", "core", "xo"; 3535 resets = <&gcc GCC_SDCC2_BCR>; 3536 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3537 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 3538 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3539 iommus = <&apps_smmu 0x4e0 0x0>; 3540 power-domains = <&rpmhpd SC8280XP_CX>; 3541 operating-points-v2 = <&sdc2_opp_table>; 3542 bus-width = <4>; 3543 dma-coherent; 3544 3545 status = "disabled"; 3546 3547 sdc2_opp_table: opp-table { 3548 compatible = "operating-points-v2"; 3549 3550 opp-100000000 { 3551 opp-hz = /bits/ 64 <100000000>; 3552 required-opps = <&rpmhpd_opp_low_svs>; 3553 opp-peak-kBps = <1800000 400000>; 3554 opp-avg-kBps = <100000 0>; 3555 }; 3556 3557 opp-202000000 { 3558 opp-hz = /bits/ 64 <202000000>; 3559 required-opps = <&rpmhpd_opp_svs_l1>; 3560 opp-peak-kBps = <5400000 1600000>; 3561 opp-avg-kBps = <200000 0>; 3562 }; 3563 }; 3564 }; 3565 3566 usb_0_hsphy: phy@88e5000 { 3567 compatible = "qcom,sc8280xp-usb-hs-phy", 3568 "qcom,usb-snps-hs-5nm-phy"; 3569 reg = <0 0x088e5000 0 0x400>; 3570 clocks = <&rpmhcc RPMH_CXO_CLK>; 3571 clock-names = "ref"; 3572 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3573 3574 #phy-cells = <0>; 3575 3576 status = "disabled"; 3577 }; 3578 3579 usb_2_hsphy0: phy@88e7000 { 3580 compatible = "qcom,sc8280xp-usb-hs-phy", 3581 "qcom,usb-snps-hs-5nm-phy"; 3582 reg = <0 0x088e7000 0 0x400>; 3583 clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>; 3584 clock-names = "ref"; 3585 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 3586 3587 #phy-cells = <0>; 3588 3589 status = "disabled"; 3590 }; 3591 3592 usb_2_hsphy1: phy@88e8000 { 3593 compatible = "qcom,sc8280xp-usb-hs-phy", 3594 "qcom,usb-snps-hs-5nm-phy"; 3595 reg = <0 0x088e8000 0 0x400>; 3596 clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>; 3597 clock-names = "ref"; 3598 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 3599 3600 #phy-cells = <0>; 3601 3602 status = "disabled"; 3603 }; 3604 3605 usb_2_hsphy2: phy@88e9000 { 3606 compatible = "qcom,sc8280xp-usb-hs-phy", 3607 "qcom,usb-snps-hs-5nm-phy"; 3608 reg = <0 0x088e9000 0 0x400>; 3609 clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>; 3610 clock-names = "ref"; 3611 resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>; 3612 3613 #phy-cells = <0>; 3614 3615 status = "disabled"; 3616 }; 3617 3618 usb_2_hsphy3: phy@88ea000 { 3619 compatible = "qcom,sc8280xp-usb-hs-phy", 3620 "qcom,usb-snps-hs-5nm-phy"; 3621 reg = <0 0x088ea000 0 0x400>; 3622 clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>; 3623 clock-names = "ref"; 3624 resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>; 3625 3626 #phy-cells = <0>; 3627 3628 status = "disabled"; 3629 }; 3630 3631 usb_0_qmpphy: phy@88eb000 { 3632 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 3633 reg = <0 0x088eb000 0 0x4000>; 3634 3635 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3636 <&gcc GCC_USB4_EUD_CLKREF_CLK>, 3637 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3638 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3639 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3640 3641 power-domains = <&gcc USB30_PRIM_GDSC>; 3642 3643 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3644 <&gcc GCC_USB4_DP_PHY_PRIM_BCR>; 3645 reset-names = "phy", "common"; 3646 3647 #clock-cells = <1>; 3648 #phy-cells = <1>; 3649 3650 status = "disabled"; 3651 3652 ports { 3653 #address-cells = <1>; 3654 #size-cells = <0>; 3655 3656 port@0 { 3657 reg = <0>; 3658 3659 usb_0_qmpphy_out: endpoint {}; 3660 }; 3661 3662 port@1 { 3663 reg = <1>; 3664 3665 usb_0_qmpphy_usb_ss_in: endpoint { 3666 remote-endpoint = <&usb_0_dwc3_ss>; 3667 }; 3668 }; 3669 3670 port@2 { 3671 reg = <2>; 3672 3673 usb_0_qmpphy_dp_in: endpoint {}; 3674 }; 3675 }; 3676 }; 3677 3678 usb_2_qmpphy0: phy@88ef000 { 3679 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 3680 reg = <0 0x088ef000 0 0x2000>; 3681 3682 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 3683 <&gcc GCC_USB3_MP0_CLKREF_CLK>, 3684 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 3685 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 3686 clock-names = "aux", "ref", "com_aux", "pipe"; 3687 3688 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 3689 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 3690 reset-names = "phy", "phy_phy"; 3691 3692 power-domains = <&gcc USB30_MP_GDSC>; 3693 3694 #clock-cells = <0>; 3695 clock-output-names = "usb2_phy0_pipe_clk"; 3696 3697 #phy-cells = <0>; 3698 3699 status = "disabled"; 3700 }; 3701 3702 usb_2_qmpphy1: phy@88f1000 { 3703 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 3704 reg = <0 0x088f1000 0 0x2000>; 3705 3706 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 3707 <&gcc GCC_USB3_MP1_CLKREF_CLK>, 3708 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 3709 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 3710 clock-names = "aux", "ref", "com_aux", "pipe"; 3711 3712 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, 3713 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 3714 reset-names = "phy", "phy_phy"; 3715 3716 power-domains = <&gcc USB30_MP_GDSC>; 3717 3718 #clock-cells = <0>; 3719 clock-output-names = "usb2_phy1_pipe_clk"; 3720 3721 #phy-cells = <0>; 3722 3723 status = "disabled"; 3724 }; 3725 3726 usb_1_hsphy: phy@8902000 { 3727 compatible = "qcom,sc8280xp-usb-hs-phy", 3728 "qcom,usb-snps-hs-5nm-phy"; 3729 reg = <0 0x08902000 0 0x400>; 3730 #phy-cells = <0>; 3731 3732 clocks = <&rpmhcc RPMH_CXO_CLK>; 3733 clock-names = "ref"; 3734 3735 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3736 3737 status = "disabled"; 3738 }; 3739 3740 usb_1_qmpphy: phy@8903000 { 3741 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 3742 reg = <0 0x08903000 0 0x4000>; 3743 3744 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3745 <&gcc GCC_USB4_CLKREF_CLK>, 3746 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 3747 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3748 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3749 3750 power-domains = <&gcc USB30_SEC_GDSC>; 3751 3752 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 3753 <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>; 3754 reset-names = "phy", "common"; 3755 3756 #clock-cells = <1>; 3757 #phy-cells = <1>; 3758 3759 status = "disabled"; 3760 3761 ports { 3762 #address-cells = <1>; 3763 #size-cells = <0>; 3764 3765 port@0 { 3766 reg = <0>; 3767 3768 usb_1_qmpphy_out: endpoint {}; 3769 }; 3770 3771 port@1 { 3772 reg = <1>; 3773 3774 usb_1_qmpphy_usb_ss_in: endpoint { 3775 remote-endpoint = <&usb_1_dwc3_ss>; 3776 }; 3777 }; 3778 3779 port@2 { 3780 reg = <2>; 3781 3782 usb_1_qmpphy_dp_in: endpoint {}; 3783 }; 3784 }; 3785 }; 3786 3787 mdss1_dp0_phy: phy@8909a00 { 3788 compatible = "qcom,sc8280xp-dp-phy"; 3789 reg = <0 0x08909a00 0 0x19c>, 3790 <0 0x08909200 0 0xec>, 3791 <0 0x08909600 0 0xec>, 3792 <0 0x08909000 0 0x1c8>; 3793 3794 clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 3795 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 3796 clock-names = "aux", "cfg_ahb"; 3797 power-domains = <&rpmhpd SC8280XP_MX>; 3798 3799 #clock-cells = <1>; 3800 #phy-cells = <0>; 3801 3802 status = "disabled"; 3803 }; 3804 3805 mdss1_dp1_phy: phy@890ca00 { 3806 compatible = "qcom,sc8280xp-dp-phy"; 3807 reg = <0 0x0890ca00 0 0x19c>, 3808 <0 0x0890c200 0 0xec>, 3809 <0 0x0890c600 0 0xec>, 3810 <0 0x0890c000 0 0x1c8>; 3811 3812 clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 3813 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 3814 clock-names = "aux", "cfg_ahb"; 3815 power-domains = <&rpmhpd SC8280XP_MX>; 3816 3817 #clock-cells = <1>; 3818 #phy-cells = <0>; 3819 3820 status = "disabled"; 3821 }; 3822 3823 pmu@9091000 { 3824 compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3825 reg = <0 0x09091000 0 0x1000>; 3826 3827 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3828 3829 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3830 3831 operating-points-v2 = <&llcc_bwmon_opp_table>; 3832 3833 llcc_bwmon_opp_table: opp-table { 3834 compatible = "operating-points-v2"; 3835 3836 opp-0 { 3837 opp-peak-kBps = <762000>; 3838 }; 3839 opp-1 { 3840 opp-peak-kBps = <1720000>; 3841 }; 3842 opp-2 { 3843 opp-peak-kBps = <2086000>; 3844 }; 3845 opp-3 { 3846 opp-peak-kBps = <2597000>; 3847 }; 3848 opp-4 { 3849 opp-peak-kBps = <2929000>; 3850 }; 3851 opp-5 { 3852 opp-peak-kBps = <3879000>; 3853 }; 3854 opp-6 { 3855 opp-peak-kBps = <5161000>; 3856 }; 3857 opp-7 { 3858 opp-peak-kBps = <5931000>; 3859 }; 3860 opp-8 { 3861 opp-peak-kBps = <6515000>; 3862 }; 3863 opp-9 { 3864 opp-peak-kBps = <7980000>; 3865 }; 3866 opp-10 { 3867 opp-peak-kBps = <8136000>; 3868 }; 3869 opp-11 { 3870 opp-peak-kBps = <10437000>; 3871 }; 3872 opp-12 { 3873 opp-peak-kBps = <12191000>; 3874 }; 3875 }; 3876 }; 3877 3878 pmu@90b6400 { 3879 compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon"; 3880 reg = <0 0x090b6400 0 0x600>; 3881 3882 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3883 3884 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3885 operating-points-v2 = <&cpu_bwmon_opp_table>; 3886 3887 cpu_bwmon_opp_table: opp-table { 3888 compatible = "operating-points-v2"; 3889 3890 opp-0 { 3891 opp-peak-kBps = <2288000>; 3892 }; 3893 opp-1 { 3894 opp-peak-kBps = <4577000>; 3895 }; 3896 opp-2 { 3897 opp-peak-kBps = <7110000>; 3898 }; 3899 opp-3 { 3900 opp-peak-kBps = <9155000>; 3901 }; 3902 opp-4 { 3903 opp-peak-kBps = <12298000>; 3904 }; 3905 opp-5 { 3906 opp-peak-kBps = <14236000>; 3907 }; 3908 opp-6 { 3909 opp-peak-kBps = <15258001>; 3910 }; 3911 }; 3912 }; 3913 3914 system-cache-controller@9200000 { 3915 compatible = "qcom,sc8280xp-llcc"; 3916 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 3917 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 3918 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, 3919 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, 3920 <0 0x09600000 0 0x58000>; 3921 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 3922 "llcc3_base", "llcc4_base", "llcc5_base", 3923 "llcc6_base", "llcc7_base", "llcc_broadcast_base"; 3924 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3925 }; 3926 3927 usb_2: usb@a4f8800 { 3928 compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3"; 3929 reg = <0 0x0a4f8800 0 0x400>; 3930 #address-cells = <2>; 3931 #size-cells = <2>; 3932 ranges; 3933 3934 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, 3935 <&gcc GCC_USB30_MP_MASTER_CLK>, 3936 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, 3937 <&gcc GCC_USB30_MP_SLEEP_CLK>, 3938 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 3939 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3940 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 3941 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 3942 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3943 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 3944 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 3945 3946 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 3947 <&gcc GCC_USB30_MP_MASTER_CLK>; 3948 assigned-clock-rates = <19200000>, <200000000>; 3949 3950 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 3951 <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 3952 <&intc GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>, 3953 <&intc GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, 3954 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3955 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3956 <&intc GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>, 3957 <&intc GIC_SPI 859 IRQ_TYPE_LEVEL_HIGH>, 3958 <&pdc 127 IRQ_TYPE_EDGE_BOTH>, 3959 <&pdc 126 IRQ_TYPE_EDGE_BOTH>, 3960 <&pdc 129 IRQ_TYPE_EDGE_BOTH>, 3961 <&pdc 128 IRQ_TYPE_EDGE_BOTH>, 3962 <&pdc 131 IRQ_TYPE_EDGE_BOTH>, 3963 <&pdc 130 IRQ_TYPE_EDGE_BOTH>, 3964 <&pdc 133 IRQ_TYPE_EDGE_BOTH>, 3965 <&pdc 132 IRQ_TYPE_EDGE_BOTH>, 3966 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, 3967 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 3968 3969 interrupt-names = "pwr_event_1", "pwr_event_2", 3970 "pwr_event_3", "pwr_event_4", 3971 "hs_phy_1", "hs_phy_2", 3972 "hs_phy_3", "hs_phy_4", 3973 "dp_hs_phy_1", "dm_hs_phy_1", 3974 "dp_hs_phy_2", "dm_hs_phy_2", 3975 "dp_hs_phy_3", "dm_hs_phy_3", 3976 "dp_hs_phy_4", "dm_hs_phy_4", 3977 "ss_phy_1", "ss_phy_2"; 3978 3979 power-domains = <&gcc USB30_MP_GDSC>; 3980 required-opps = <&rpmhpd_opp_nom>; 3981 3982 resets = <&gcc GCC_USB30_MP_BCR>; 3983 3984 interconnects = <&aggre1_noc MASTER_USB3_MP 0 &mc_virt SLAVE_EBI1 0>, 3985 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_MP 0>; 3986 interconnect-names = "usb-ddr", "apps-usb"; 3987 3988 wakeup-source; 3989 3990 status = "disabled"; 3991 3992 usb_2_dwc3: usb@a400000 { 3993 compatible = "snps,dwc3"; 3994 reg = <0 0x0a400000 0 0xcd00>; 3995 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3996 iommus = <&apps_smmu 0x800 0x0>; 3997 phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>, 3998 <&usb_2_hsphy1>, <&usb_2_qmpphy1>, 3999 <&usb_2_hsphy2>, 4000 <&usb_2_hsphy3>; 4001 phy-names = "usb2-0", "usb3-0", 4002 "usb2-1", "usb3-1", 4003 "usb2-2", 4004 "usb2-3"; 4005 dr_mode = "host"; 4006 snps,dis-u1-entry-quirk; 4007 snps,dis-u2-entry-quirk; 4008 }; 4009 }; 4010 4011 usb_0: usb@a6f8800 { 4012 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 4013 reg = <0 0x0a6f8800 0 0x400>; 4014 #address-cells = <2>; 4015 #size-cells = <2>; 4016 ranges; 4017 4018 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4019 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4020 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4021 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4022 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4023 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4024 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 4025 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 4026 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4027 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 4028 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 4029 4030 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4031 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4032 assigned-clock-rates = <19200000>, <200000000>; 4033 4034 interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 4035 <&intc GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, 4036 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4037 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4038 <&pdc 138 IRQ_TYPE_LEVEL_HIGH>; 4039 interrupt-names = "pwr_event", 4040 "hs_phy_irq", 4041 "dp_hs_phy_irq", 4042 "dm_hs_phy_irq", 4043 "ss_phy_irq"; 4044 4045 power-domains = <&gcc USB30_PRIM_GDSC>; 4046 required-opps = <&rpmhpd_opp_nom>; 4047 4048 resets = <&gcc GCC_USB30_PRIM_BCR>; 4049 4050 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 4051 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 4052 interconnect-names = "usb-ddr", "apps-usb"; 4053 4054 wakeup-source; 4055 4056 status = "disabled"; 4057 4058 usb_0_dwc3: usb@a600000 { 4059 compatible = "snps,dwc3"; 4060 reg = <0 0x0a600000 0 0xcd00>; 4061 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 4062 iommus = <&apps_smmu 0x820 0x0>; 4063 phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; 4064 phy-names = "usb2-phy", "usb3-phy"; 4065 snps,dis-u1-entry-quirk; 4066 snps,dis-u2-entry-quirk; 4067 4068 ports { 4069 #address-cells = <1>; 4070 #size-cells = <0>; 4071 4072 port@0 { 4073 reg = <0>; 4074 4075 usb_0_dwc3_hs: endpoint { 4076 }; 4077 }; 4078 4079 port@1 { 4080 reg = <1>; 4081 4082 usb_0_dwc3_ss: endpoint { 4083 remote-endpoint = <&usb_0_qmpphy_usb_ss_in>; 4084 }; 4085 }; 4086 }; 4087 }; 4088 }; 4089 4090 usb_1: usb@a8f8800 { 4091 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 4092 reg = <0 0x0a8f8800 0 0x400>; 4093 #address-cells = <2>; 4094 #size-cells = <2>; 4095 ranges; 4096 4097 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4098 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4099 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4100 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4101 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4102 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 4103 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 4104 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 4105 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 4106 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 4107 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 4108 4109 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4110 <&gcc GCC_USB30_SEC_MASTER_CLK>; 4111 assigned-clock-rates = <19200000>, <200000000>; 4112 4113 interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 4114 <&intc GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 4115 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 4116 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 4117 <&pdc 136 IRQ_TYPE_LEVEL_HIGH>; 4118 interrupt-names = "pwr_event", 4119 "hs_phy_irq", 4120 "dp_hs_phy_irq", 4121 "dm_hs_phy_irq", 4122 "ss_phy_irq"; 4123 4124 power-domains = <&gcc USB30_SEC_GDSC>; 4125 required-opps = <&rpmhpd_opp_nom>; 4126 4127 resets = <&gcc GCC_USB30_SEC_BCR>; 4128 4129 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 4130 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 4131 interconnect-names = "usb-ddr", "apps-usb"; 4132 4133 wakeup-source; 4134 4135 status = "disabled"; 4136 4137 usb_1_dwc3: usb@a800000 { 4138 compatible = "snps,dwc3"; 4139 reg = <0 0x0a800000 0 0xcd00>; 4140 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 4141 iommus = <&apps_smmu 0x860 0x0>; 4142 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4143 phy-names = "usb2-phy", "usb3-phy"; 4144 snps,dis-u1-entry-quirk; 4145 snps,dis-u2-entry-quirk; 4146 4147 ports { 4148 #address-cells = <1>; 4149 #size-cells = <0>; 4150 4151 port@0 { 4152 reg = <0>; 4153 4154 usb_1_dwc3_hs: endpoint { 4155 }; 4156 }; 4157 4158 port@1 { 4159 reg = <1>; 4160 4161 usb_1_dwc3_ss: endpoint { 4162 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 4163 }; 4164 }; 4165 }; 4166 }; 4167 }; 4168 4169 cci0: cci@ac4a000 { 4170 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 4171 reg = <0 0x0ac4a000 0 0x1000>; 4172 4173 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4174 4175 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 4176 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 4177 <&camcc CAMCC_CPAS_AHB_CLK>, 4178 <&camcc CAMCC_CCI_0_CLK>; 4179 clock-names = "camnoc_axi", 4180 "slow_ahb_src", 4181 "cpas_ahb", 4182 "cci"; 4183 4184 power-domains = <&camcc TITAN_TOP_GDSC>; 4185 4186 pinctrl-0 = <&cci0_default>; 4187 pinctrl-1 = <&cci0_sleep>; 4188 pinctrl-names = "default", "sleep"; 4189 4190 #address-cells = <1>; 4191 #size-cells = <0>; 4192 4193 status = "disabled"; 4194 4195 cci0_i2c0: i2c-bus@0 { 4196 reg = <0>; 4197 clock-frequency = <1000000>; 4198 #address-cells = <1>; 4199 #size-cells = <0>; 4200 }; 4201 4202 cci0_i2c1: i2c-bus@1 { 4203 reg = <1>; 4204 clock-frequency = <1000000>; 4205 #address-cells = <1>; 4206 #size-cells = <0>; 4207 }; 4208 }; 4209 4210 cci1: cci@ac4b000 { 4211 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 4212 reg = <0 0x0ac4b000 0 0x1000>; 4213 4214 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 4215 4216 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 4217 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 4218 <&camcc CAMCC_CPAS_AHB_CLK>, 4219 <&camcc CAMCC_CCI_1_CLK>; 4220 clock-names = "camnoc_axi", 4221 "slow_ahb_src", 4222 "cpas_ahb", 4223 "cci"; 4224 4225 power-domains = <&camcc TITAN_TOP_GDSC>; 4226 4227 pinctrl-0 = <&cci1_default>; 4228 pinctrl-1 = <&cci1_sleep>; 4229 pinctrl-names = "default", "sleep"; 4230 4231 #address-cells = <1>; 4232 #size-cells = <0>; 4233 4234 status = "disabled"; 4235 4236 cci1_i2c0: i2c-bus@0 { 4237 reg = <0>; 4238 clock-frequency = <1000000>; 4239 #address-cells = <1>; 4240 #size-cells = <0>; 4241 }; 4242 4243 cci1_i2c1: i2c-bus@1 { 4244 reg = <1>; 4245 clock-frequency = <1000000>; 4246 #address-cells = <1>; 4247 #size-cells = <0>; 4248 }; 4249 }; 4250 4251 cci2: cci@ac4c000 { 4252 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 4253 reg = <0 0x0ac4c000 0 0x1000>; 4254 4255 interrupts = <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>; 4256 4257 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 4258 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 4259 <&camcc CAMCC_CPAS_AHB_CLK>, 4260 <&camcc CAMCC_CCI_2_CLK>; 4261 clock-names = "camnoc_axi", 4262 "slow_ahb_src", 4263 "cpas_ahb", 4264 "cci"; 4265 power-domains = <&camcc TITAN_TOP_GDSC>; 4266 4267 pinctrl-0 = <&cci2_default>; 4268 pinctrl-1 = <&cci2_sleep>; 4269 pinctrl-names = "default", "sleep"; 4270 4271 #address-cells = <1>; 4272 #size-cells = <0>; 4273 4274 status = "disabled"; 4275 4276 cci2_i2c0: i2c-bus@0 { 4277 reg = <0>; 4278 clock-frequency = <1000000>; 4279 #address-cells = <1>; 4280 #size-cells = <0>; 4281 }; 4282 4283 cci2_i2c1: i2c-bus@1 { 4284 reg = <1>; 4285 clock-frequency = <1000000>; 4286 #address-cells = <1>; 4287 #size-cells = <0>; 4288 }; 4289 }; 4290 4291 cci3: cci@ac4d000 { 4292 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 4293 reg = <0 0x0ac4d000 0 0x1000>; 4294 4295 interrupts = <GIC_SPI 650 IRQ_TYPE_EDGE_RISING>; 4296 4297 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 4298 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 4299 <&camcc CAMCC_CPAS_AHB_CLK>, 4300 <&camcc CAMCC_CCI_3_CLK>; 4301 clock-names = "camnoc_axi", 4302 "slow_ahb_src", 4303 "cpas_ahb", 4304 "cci"; 4305 4306 power-domains = <&camcc TITAN_TOP_GDSC>; 4307 4308 pinctrl-0 = <&cci3_default>; 4309 pinctrl-1 = <&cci3_sleep>; 4310 pinctrl-names = "default", "sleep"; 4311 4312 #address-cells = <1>; 4313 #size-cells = <0>; 4314 4315 status = "disabled"; 4316 4317 cci3_i2c0: i2c-bus@0 { 4318 reg = <0>; 4319 clock-frequency = <1000000>; 4320 #address-cells = <1>; 4321 #size-cells = <0>; 4322 }; 4323 4324 cci3_i2c1: i2c-bus@1 { 4325 reg = <1>; 4326 clock-frequency = <1000000>; 4327 #address-cells = <1>; 4328 #size-cells = <0>; 4329 }; 4330 }; 4331 4332 camss: camss@ac5a000 { 4333 compatible = "qcom,sc8280xp-camss"; 4334 4335 reg = <0 0x0ac5a000 0 0x2000>, 4336 <0 0x0ac5c000 0 0x2000>, 4337 <0 0x0ac65000 0 0x2000>, 4338 <0 0x0ac67000 0 0x2000>, 4339 <0 0x0acaf000 0 0x4000>, 4340 <0 0x0acb3000 0 0x1000>, 4341 <0 0x0acb6000 0 0x4000>, 4342 <0 0x0acba000 0 0x1000>, 4343 <0 0x0acbd000 0 0x4000>, 4344 <0 0x0acc1000 0 0x1000>, 4345 <0 0x0acc4000 0 0x4000>, 4346 <0 0x0acc8000 0 0x1000>, 4347 <0 0x0accb000 0 0x4000>, 4348 <0 0x0accf000 0 0x1000>, 4349 <0 0x0acd2000 0 0x4000>, 4350 <0 0x0acd6000 0 0x1000>, 4351 <0 0x0acd9000 0 0x4000>, 4352 <0 0x0acdd000 0 0x1000>, 4353 <0 0x0ace0000 0 0x4000>, 4354 <0 0x0ace4000 0 0x1000>; 4355 reg-names = "csiphy2", 4356 "csiphy3", 4357 "csiphy0", 4358 "csiphy1", 4359 "vfe0", 4360 "csid0", 4361 "vfe1", 4362 "csid1", 4363 "vfe2", 4364 "csid2", 4365 "vfe_lite0", 4366 "csid0_lite", 4367 "vfe_lite1", 4368 "csid1_lite", 4369 "vfe_lite2", 4370 "csid2_lite", 4371 "vfe_lite3", 4372 "csid3_lite", 4373 "vfe3", 4374 "csid3"; 4375 4376 interrupts = <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, 4377 <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>, 4378 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 4379 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 4380 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 4381 <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, 4382 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 4383 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 4384 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, 4385 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 4386 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 4387 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 4388 <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>, 4389 <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>, 4390 <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>, 4391 <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>, 4392 <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>, 4393 <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>, 4394 <GIC_SPI 762 IRQ_TYPE_EDGE_RISING>, 4395 <GIC_SPI 764 IRQ_TYPE_EDGE_RISING>; 4396 interrupt-names = "csid1_lite", 4397 "vfe_lite1", 4398 "csiphy3", 4399 "csid0", 4400 "vfe0", 4401 "csid1", 4402 "vfe1", 4403 "csid0_lite", 4404 "vfe_lite0", 4405 "csiphy0", 4406 "csiphy1", 4407 "csiphy2", 4408 "csid2", 4409 "vfe2", 4410 "csid3_lite", 4411 "csid2_lite", 4412 "vfe_lite3", 4413 "vfe_lite2", 4414 "csid3", 4415 "vfe3"; 4416 4417 power-domains = <&camcc IFE_0_GDSC>, 4418 <&camcc IFE_1_GDSC>, 4419 <&camcc IFE_2_GDSC>, 4420 <&camcc IFE_3_GDSC>, 4421 <&camcc TITAN_TOP_GDSC>; 4422 power-domain-names = "ife0", 4423 "ife1", 4424 "ife2", 4425 "ife3", 4426 "top"; 4427 4428 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 4429 <&camcc CAMCC_CPAS_AHB_CLK>, 4430 <&camcc CAMCC_CSIPHY0_CLK>, 4431 <&camcc CAMCC_CSI0PHYTIMER_CLK>, 4432 <&camcc CAMCC_CSIPHY1_CLK>, 4433 <&camcc CAMCC_CSI1PHYTIMER_CLK>, 4434 <&camcc CAMCC_CSIPHY2_CLK>, 4435 <&camcc CAMCC_CSI2PHYTIMER_CLK>, 4436 <&camcc CAMCC_CSIPHY3_CLK>, 4437 <&camcc CAMCC_CSI3PHYTIMER_CLK>, 4438 <&camcc CAMCC_IFE_0_AXI_CLK>, 4439 <&camcc CAMCC_IFE_0_CLK>, 4440 <&camcc CAMCC_IFE_0_CPHY_RX_CLK>, 4441 <&camcc CAMCC_IFE_0_CSID_CLK>, 4442 <&camcc CAMCC_IFE_1_AXI_CLK>, 4443 <&camcc CAMCC_IFE_1_CLK>, 4444 <&camcc CAMCC_IFE_1_CPHY_RX_CLK>, 4445 <&camcc CAMCC_IFE_1_CSID_CLK>, 4446 <&camcc CAMCC_IFE_2_AXI_CLK>, 4447 <&camcc CAMCC_IFE_2_CLK>, 4448 <&camcc CAMCC_IFE_2_CPHY_RX_CLK>, 4449 <&camcc CAMCC_IFE_2_CSID_CLK>, 4450 <&camcc CAMCC_IFE_3_AXI_CLK>, 4451 <&camcc CAMCC_IFE_3_CLK>, 4452 <&camcc CAMCC_IFE_3_CPHY_RX_CLK>, 4453 <&camcc CAMCC_IFE_3_CSID_CLK>, 4454 <&camcc CAMCC_IFE_LITE_0_CLK>, 4455 <&camcc CAMCC_IFE_LITE_0_CPHY_RX_CLK>, 4456 <&camcc CAMCC_IFE_LITE_0_CSID_CLK>, 4457 <&camcc CAMCC_IFE_LITE_1_CLK>, 4458 <&camcc CAMCC_IFE_LITE_1_CPHY_RX_CLK>, 4459 <&camcc CAMCC_IFE_LITE_1_CSID_CLK>, 4460 <&camcc CAMCC_IFE_LITE_2_CLK>, 4461 <&camcc CAMCC_IFE_LITE_2_CPHY_RX_CLK>, 4462 <&camcc CAMCC_IFE_LITE_2_CSID_CLK>, 4463 <&camcc CAMCC_IFE_LITE_3_CLK>, 4464 <&camcc CAMCC_IFE_LITE_3_CPHY_RX_CLK>, 4465 <&camcc CAMCC_IFE_LITE_3_CSID_CLK>, 4466 <&gcc GCC_CAMERA_HF_AXI_CLK>, 4467 <&gcc GCC_CAMERA_SF_AXI_CLK>; 4468 clock-names = "camnoc_axi", 4469 "cpas_ahb", 4470 "csiphy0", 4471 "csiphy0_timer", 4472 "csiphy1", 4473 "csiphy1_timer", 4474 "csiphy2", 4475 "csiphy2_timer", 4476 "csiphy3", 4477 "csiphy3_timer", 4478 "vfe0_axi", 4479 "vfe0", 4480 "vfe0_cphy_rx", 4481 "vfe0_csid", 4482 "vfe1_axi", 4483 "vfe1", 4484 "vfe1_cphy_rx", 4485 "vfe1_csid", 4486 "vfe2_axi", 4487 "vfe2", 4488 "vfe2_cphy_rx", 4489 "vfe2_csid", 4490 "vfe3_axi", 4491 "vfe3", 4492 "vfe3_cphy_rx", 4493 "vfe3_csid", 4494 "vfe_lite0", 4495 "vfe_lite0_cphy_rx", 4496 "vfe_lite0_csid", 4497 "vfe_lite1", 4498 "vfe_lite1_cphy_rx", 4499 "vfe_lite1_csid", 4500 "vfe_lite2", 4501 "vfe_lite2_cphy_rx", 4502 "vfe_lite2_csid", 4503 "vfe_lite3", 4504 "vfe_lite3_cphy_rx", 4505 "vfe_lite3_csid", 4506 "gcc_axi_hf", 4507 "gcc_axi_sf"; 4508 4509 iommus = <&apps_smmu 0x2000 0x4e0>, 4510 <&apps_smmu 0x2020 0x4e0>, 4511 <&apps_smmu 0x2040 0x4e0>, 4512 <&apps_smmu 0x2060 0x4e0>, 4513 <&apps_smmu 0x2080 0x4e0>, 4514 <&apps_smmu 0x20e0 0x4e0>, 4515 <&apps_smmu 0x20c0 0x4e0>, 4516 <&apps_smmu 0x20a0 0x4e0>, 4517 <&apps_smmu 0x2400 0x4e0>, 4518 <&apps_smmu 0x2420 0x4e0>, 4519 <&apps_smmu 0x2440 0x4e0>, 4520 <&apps_smmu 0x2460 0x4e0>, 4521 <&apps_smmu 0x2480 0x4e0>, 4522 <&apps_smmu 0x24e0 0x4e0>, 4523 <&apps_smmu 0x24c0 0x4e0>, 4524 <&apps_smmu 0x24a0 0x4e0>; 4525 4526 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>, 4527 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>, 4528 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>, 4529 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>; 4530 interconnect-names = "cam_ahb", 4531 "cam_hf_mnoc", 4532 "cam_sf_mnoc", 4533 "cam_sf_icp_mnoc"; 4534 4535 status = "disabled"; 4536 4537 ports { 4538 #address-cells = <1>; 4539 #size-cells = <0>; 4540 4541 port@0 { 4542 reg = <0>; 4543 #address-cells = <1>; 4544 #size-cells = <0>; 4545 }; 4546 4547 port@1 { 4548 reg = <1>; 4549 #address-cells = <1>; 4550 #size-cells = <0>; 4551 }; 4552 4553 port@2 { 4554 reg = <2>; 4555 #address-cells = <1>; 4556 #size-cells = <0>; 4557 }; 4558 4559 port@3 { 4560 reg = <3>; 4561 #address-cells = <1>; 4562 #size-cells = <0>; 4563 }; 4564 }; 4565 }; 4566 4567 camcc: clock-controller@ad00000 { 4568 compatible = "qcom,sc8280xp-camcc"; 4569 reg = <0 0x0ad00000 0 0x20000>; 4570 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4571 <&rpmhcc RPMH_CXO_CLK>, 4572 <&rpmhcc RPMH_CXO_CLK_A>, 4573 <&sleep_clk>; 4574 power-domains = <&rpmhpd SC8280XP_MMCX>; 4575 required-opps = <&rpmhpd_opp_low_svs>; 4576 #clock-cells = <1>; 4577 #reset-cells = <1>; 4578 #power-domain-cells = <1>; 4579 }; 4580 4581 mdss0: display-subsystem@ae00000 { 4582 compatible = "qcom,sc8280xp-mdss"; 4583 reg = <0 0x0ae00000 0 0x1000>; 4584 reg-names = "mdss"; 4585 4586 clocks = <&gcc GCC_DISP_AHB_CLK>, 4587 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4588 <&dispcc0 DISP_CC_MDSS_MDP_CLK>; 4589 clock-names = "iface", 4590 "ahb", 4591 "core"; 4592 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4593 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 4594 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 4595 interconnect-names = "mdp0-mem", "mdp1-mem"; 4596 iommus = <&apps_smmu 0x1000 0x402>; 4597 power-domains = <&dispcc0 MDSS_GDSC>; 4598 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>; 4599 4600 interrupt-controller; 4601 #interrupt-cells = <1>; 4602 #address-cells = <2>; 4603 #size-cells = <2>; 4604 ranges; 4605 4606 status = "disabled"; 4607 4608 mdss0_mdp: display-controller@ae01000 { 4609 compatible = "qcom,sc8280xp-dpu"; 4610 reg = <0 0x0ae01000 0 0x8f000>, 4611 <0 0x0aeb0000 0 0x3000>; 4612 reg-names = "mdp", "vbif"; 4613 4614 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4615 <&gcc GCC_DISP_SF_AXI_CLK>, 4616 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4617 <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>, 4618 <&dispcc0 DISP_CC_MDSS_MDP_CLK>, 4619 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 4620 clock-names = "bus", 4621 "nrt_bus", 4622 "iface", 4623 "lut", 4624 "core", 4625 "vsync"; 4626 interrupt-parent = <&mdss0>; 4627 interrupts = <0>; 4628 power-domains = <&rpmhpd SC8280XP_MMCX>; 4629 4630 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 4631 assigned-clock-rates = <19200000>; 4632 operating-points-v2 = <&mdss0_mdp_opp_table>; 4633 4634 ports { 4635 #address-cells = <1>; 4636 #size-cells = <0>; 4637 4638 port@0 { 4639 reg = <0>; 4640 mdss0_intf0_out: endpoint { 4641 remote-endpoint = <&mdss0_dp0_in>; 4642 }; 4643 }; 4644 4645 port@4 { 4646 reg = <4>; 4647 mdss0_intf4_out: endpoint { 4648 remote-endpoint = <&mdss0_dp1_in>; 4649 }; 4650 }; 4651 4652 port@5 { 4653 reg = <5>; 4654 mdss0_intf5_out: endpoint { 4655 remote-endpoint = <&mdss0_dp3_in>; 4656 }; 4657 }; 4658 4659 port@6 { 4660 reg = <6>; 4661 mdss0_intf6_out: endpoint { 4662 remote-endpoint = <&mdss0_dp2_in>; 4663 }; 4664 }; 4665 }; 4666 4667 mdss0_mdp_opp_table: opp-table { 4668 compatible = "operating-points-v2"; 4669 4670 opp-200000000 { 4671 opp-hz = /bits/ 64 <200000000>; 4672 required-opps = <&rpmhpd_opp_low_svs>; 4673 }; 4674 4675 opp-300000000 { 4676 opp-hz = /bits/ 64 <300000000>; 4677 required-opps = <&rpmhpd_opp_svs>; 4678 }; 4679 4680 opp-375000000 { 4681 opp-hz = /bits/ 64 <375000000>; 4682 required-opps = <&rpmhpd_opp_svs_l1>; 4683 }; 4684 4685 opp-500000000 { 4686 opp-hz = /bits/ 64 <500000000>; 4687 required-opps = <&rpmhpd_opp_nom>; 4688 }; 4689 opp-600000000 { 4690 opp-hz = /bits/ 64 <600000000>; 4691 required-opps = <&rpmhpd_opp_turbo_l1>; 4692 }; 4693 }; 4694 }; 4695 4696 mdss0_dp0: displayport-controller@ae90000 { 4697 compatible = "qcom,sc8280xp-dp"; 4698 reg = <0 0xae90000 0 0x200>, 4699 <0 0xae90200 0 0x200>, 4700 <0 0xae90400 0 0x600>, 4701 <0 0xae91000 0 0x400>, 4702 <0 0xae91400 0 0x400>; 4703 interrupt-parent = <&mdss0>; 4704 interrupts = <12>; 4705 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4706 <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>, 4707 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>, 4708 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 4709 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 4710 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; 4711 clock-names = "core_iface", "core_aux", 4712 "ctrl_link", 4713 "ctrl_link_iface", 4714 "stream_pixel", 4715 "stream_1_pixel"; 4716 4717 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 4718 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 4719 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; 4720 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4721 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4722 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4723 4724 phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; 4725 phy-names = "dp"; 4726 4727 #sound-dai-cells = <0>; 4728 4729 operating-points-v2 = <&mdss0_dp0_opp_table>; 4730 power-domains = <&rpmhpd SC8280XP_MMCX>; 4731 4732 status = "disabled"; 4733 4734 ports { 4735 #address-cells = <1>; 4736 #size-cells = <0>; 4737 4738 port@0 { 4739 reg = <0>; 4740 4741 mdss0_dp0_in: endpoint { 4742 remote-endpoint = <&mdss0_intf0_out>; 4743 }; 4744 }; 4745 4746 port@1 { 4747 reg = <1>; 4748 4749 mdss0_dp0_out: endpoint { 4750 }; 4751 }; 4752 }; 4753 4754 mdss0_dp0_opp_table: opp-table { 4755 compatible = "operating-points-v2"; 4756 4757 opp-160000000 { 4758 opp-hz = /bits/ 64 <160000000>; 4759 required-opps = <&rpmhpd_opp_low_svs>; 4760 }; 4761 4762 opp-270000000 { 4763 opp-hz = /bits/ 64 <270000000>; 4764 required-opps = <&rpmhpd_opp_svs>; 4765 }; 4766 4767 opp-540000000 { 4768 opp-hz = /bits/ 64 <540000000>; 4769 required-opps = <&rpmhpd_opp_svs_l1>; 4770 }; 4771 4772 opp-810000000 { 4773 opp-hz = /bits/ 64 <810000000>; 4774 required-opps = <&rpmhpd_opp_nom>; 4775 }; 4776 }; 4777 }; 4778 4779 mdss0_dp1: displayport-controller@ae98000 { 4780 compatible = "qcom,sc8280xp-dp"; 4781 reg = <0 0xae98000 0 0x200>, 4782 <0 0xae98200 0 0x200>, 4783 <0 0xae98400 0 0x600>, 4784 <0 0xae99000 0 0x400>, 4785 <0 0xae99400 0 0x400>; 4786 interrupt-parent = <&mdss0>; 4787 interrupts = <13>; 4788 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4789 <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>, 4790 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>, 4791 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 4792 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, 4793 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; 4794 clock-names = "core_iface", "core_aux", 4795 "ctrl_link", 4796 "ctrl_link_iface", "stream_pixel", 4797 "stream_1_pixel"; 4798 4799 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 4800 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, 4801 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; 4802 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4803 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4804 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4805 4806 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 4807 phy-names = "dp"; 4808 4809 #sound-dai-cells = <0>; 4810 4811 operating-points-v2 = <&mdss0_dp1_opp_table>; 4812 power-domains = <&rpmhpd SC8280XP_MMCX>; 4813 4814 status = "disabled"; 4815 4816 ports { 4817 #address-cells = <1>; 4818 #size-cells = <0>; 4819 4820 port@0 { 4821 reg = <0>; 4822 4823 mdss0_dp1_in: endpoint { 4824 remote-endpoint = <&mdss0_intf4_out>; 4825 }; 4826 }; 4827 4828 port@1 { 4829 reg = <1>; 4830 4831 mdss0_dp1_out: endpoint { 4832 }; 4833 }; 4834 }; 4835 4836 mdss0_dp1_opp_table: opp-table { 4837 compatible = "operating-points-v2"; 4838 4839 opp-160000000 { 4840 opp-hz = /bits/ 64 <160000000>; 4841 required-opps = <&rpmhpd_opp_low_svs>; 4842 }; 4843 4844 opp-270000000 { 4845 opp-hz = /bits/ 64 <270000000>; 4846 required-opps = <&rpmhpd_opp_svs>; 4847 }; 4848 4849 opp-540000000 { 4850 opp-hz = /bits/ 64 <540000000>; 4851 required-opps = <&rpmhpd_opp_svs_l1>; 4852 }; 4853 4854 opp-810000000 { 4855 opp-hz = /bits/ 64 <810000000>; 4856 required-opps = <&rpmhpd_opp_nom>; 4857 }; 4858 }; 4859 }; 4860 4861 mdss0_dp2: displayport-controller@ae9a000 { 4862 compatible = "qcom,sc8280xp-dp"; 4863 reg = <0 0xae9a000 0 0x200>, 4864 <0 0xae9a200 0 0x200>, 4865 <0 0xae9a400 0 0x600>, 4866 <0 0xae9b000 0 0x400>, 4867 <0 0xae9b400 0 0x400>; 4868 4869 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4870 <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 4871 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>, 4872 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 4873 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, 4874 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; 4875 clock-names = "core_iface", "core_aux", 4876 "ctrl_link", 4877 "ctrl_link_iface", "stream_pixel", 4878 "stream_1_pixel"; 4879 interrupt-parent = <&mdss0>; 4880 interrupts = <14>; 4881 phys = <&mdss0_dp2_phy>; 4882 phy-names = "dp"; 4883 power-domains = <&rpmhpd SC8280XP_MMCX>; 4884 4885 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 4886 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, 4887 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; 4888 assigned-clock-parents = <&mdss0_dp2_phy 0>, 4889 <&mdss0_dp2_phy 1>, 4890 <&mdss0_dp2_phy 1>; 4891 operating-points-v2 = <&mdss0_dp2_opp_table>; 4892 4893 #sound-dai-cells = <0>; 4894 4895 status = "disabled"; 4896 4897 ports { 4898 #address-cells = <1>; 4899 #size-cells = <0>; 4900 4901 port@0 { 4902 reg = <0>; 4903 mdss0_dp2_in: endpoint { 4904 remote-endpoint = <&mdss0_intf6_out>; 4905 }; 4906 }; 4907 4908 port@1 { 4909 reg = <1>; 4910 4911 mdss0_dp2_out: endpoint { 4912 }; 4913 }; 4914 }; 4915 4916 mdss0_dp2_opp_table: opp-table { 4917 compatible = "operating-points-v2"; 4918 4919 opp-160000000 { 4920 opp-hz = /bits/ 64 <160000000>; 4921 required-opps = <&rpmhpd_opp_low_svs>; 4922 }; 4923 4924 opp-270000000 { 4925 opp-hz = /bits/ 64 <270000000>; 4926 required-opps = <&rpmhpd_opp_svs>; 4927 }; 4928 4929 opp-540000000 { 4930 opp-hz = /bits/ 64 <540000000>; 4931 required-opps = <&rpmhpd_opp_svs_l1>; 4932 }; 4933 4934 opp-810000000 { 4935 opp-hz = /bits/ 64 <810000000>; 4936 required-opps = <&rpmhpd_opp_nom>; 4937 }; 4938 }; 4939 }; 4940 4941 mdss0_dp3: displayport-controller@aea0000 { 4942 compatible = "qcom,sc8280xp-dp"; 4943 reg = <0 0xaea0000 0 0x200>, 4944 <0 0xaea0200 0 0x200>, 4945 <0 0xaea0400 0 0x600>, 4946 <0 0xaea1000 0 0x400>, 4947 <0 0xaea1400 0 0x400>; 4948 4949 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4950 <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 4951 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>, 4952 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 4953 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 4954 clock-names = "core_iface", "core_aux", 4955 "ctrl_link", 4956 "ctrl_link_iface", "stream_pixel"; 4957 interrupt-parent = <&mdss0>; 4958 interrupts = <15>; 4959 phys = <&mdss0_dp3_phy>; 4960 phy-names = "dp"; 4961 power-domains = <&rpmhpd SC8280XP_MMCX>; 4962 4963 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 4964 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 4965 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>; 4966 operating-points-v2 = <&mdss0_dp3_opp_table>; 4967 4968 #sound-dai-cells = <0>; 4969 4970 status = "disabled"; 4971 4972 ports { 4973 #address-cells = <1>; 4974 #size-cells = <0>; 4975 4976 port@0 { 4977 reg = <0>; 4978 mdss0_dp3_in: endpoint { 4979 remote-endpoint = <&mdss0_intf5_out>; 4980 }; 4981 }; 4982 4983 port@1 { 4984 reg = <1>; 4985 4986 mdss0_dp3_out: endpoint { 4987 }; 4988 }; 4989 }; 4990 4991 mdss0_dp3_opp_table: opp-table { 4992 compatible = "operating-points-v2"; 4993 4994 opp-160000000 { 4995 opp-hz = /bits/ 64 <160000000>; 4996 required-opps = <&rpmhpd_opp_low_svs>; 4997 }; 4998 4999 opp-270000000 { 5000 opp-hz = /bits/ 64 <270000000>; 5001 required-opps = <&rpmhpd_opp_svs>; 5002 }; 5003 5004 opp-540000000 { 5005 opp-hz = /bits/ 64 <540000000>; 5006 required-opps = <&rpmhpd_opp_svs_l1>; 5007 }; 5008 5009 opp-810000000 { 5010 opp-hz = /bits/ 64 <810000000>; 5011 required-opps = <&rpmhpd_opp_nom>; 5012 }; 5013 }; 5014 }; 5015 }; 5016 5017 mdss0_dp2_phy: phy@aec2a00 { 5018 compatible = "qcom,sc8280xp-dp-phy"; 5019 reg = <0 0x0aec2a00 0 0x19c>, 5020 <0 0x0aec2200 0 0xec>, 5021 <0 0x0aec2600 0 0xec>, 5022 <0 0x0aec2000 0 0x1c8>; 5023 5024 clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 5025 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 5026 clock-names = "aux", "cfg_ahb"; 5027 power-domains = <&rpmhpd SC8280XP_MX>; 5028 5029 #clock-cells = <1>; 5030 #phy-cells = <0>; 5031 5032 status = "disabled"; 5033 }; 5034 5035 mdss0_dp3_phy: phy@aec5a00 { 5036 compatible = "qcom,sc8280xp-dp-phy"; 5037 reg = <0 0x0aec5a00 0 0x19c>, 5038 <0 0x0aec5200 0 0xec>, 5039 <0 0x0aec5600 0 0xec>, 5040 <0 0x0aec5000 0 0x1c8>; 5041 5042 clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 5043 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 5044 clock-names = "aux", "cfg_ahb"; 5045 power-domains = <&rpmhpd SC8280XP_MX>; 5046 5047 #clock-cells = <1>; 5048 #phy-cells = <0>; 5049 5050 status = "disabled"; 5051 }; 5052 5053 dispcc0: clock-controller@af00000 { 5054 compatible = "qcom,sc8280xp-dispcc0"; 5055 reg = <0 0x0af00000 0 0x20000>; 5056 5057 clocks = <&gcc GCC_DISP_AHB_CLK>, 5058 <&rpmhcc RPMH_CXO_CLK>, 5059 <&sleep_clk>, 5060 <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5061 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5062 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5063 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5064 <&mdss0_dp2_phy 0>, 5065 <&mdss0_dp2_phy 1>, 5066 <&mdss0_dp3_phy 0>, 5067 <&mdss0_dp3_phy 1>, 5068 <0>, 5069 <0>, 5070 <0>, 5071 <0>; 5072 power-domains = <&rpmhpd SC8280XP_MMCX>; 5073 5074 #clock-cells = <1>; 5075 #power-domain-cells = <1>; 5076 #reset-cells = <1>; 5077 5078 status = "disabled"; 5079 }; 5080 5081 pdc: interrupt-controller@b220000 { 5082 compatible = "qcom,sc8280xp-pdc", "qcom,pdc"; 5083 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 5084 qcom,pdc-ranges = <0 480 40>, 5085 <40 140 14>, 5086 <54 263 1>, 5087 <55 306 4>, 5088 <59 312 3>, 5089 <62 374 2>, 5090 <64 434 2>, 5091 <66 438 3>, 5092 <69 86 1>, 5093 <70 520 54>, 5094 <124 609 28>, 5095 <159 638 1>, 5096 <160 720 8>, 5097 <168 801 1>, 5098 <169 728 30>, 5099 <199 416 2>, 5100 <201 449 1>, 5101 <202 89 1>, 5102 <203 451 1>, 5103 <204 462 1>, 5104 <205 264 1>, 5105 <206 579 1>, 5106 <207 653 1>, 5107 <208 656 1>, 5108 <209 659 1>, 5109 <210 122 1>, 5110 <211 699 1>, 5111 <212 705 1>, 5112 <213 450 1>, 5113 <214 643 1>, 5114 <216 646 5>, 5115 <221 390 5>, 5116 <226 700 3>, 5117 <229 240 3>, 5118 <232 269 1>, 5119 <233 377 1>, 5120 <234 372 1>, 5121 <235 138 1>, 5122 <236 857 1>, 5123 <237 860 1>, 5124 <238 137 1>, 5125 <239 668 1>, 5126 <240 366 1>, 5127 <241 949 1>, 5128 <242 815 5>, 5129 <247 769 1>, 5130 <248 768 1>, 5131 <249 663 1>, 5132 <250 799 2>, 5133 <252 798 1>, 5134 <253 765 1>, 5135 <254 763 1>, 5136 <255 454 1>, 5137 <258 139 1>, 5138 <259 786 2>, 5139 <261 370 2>, 5140 <263 158 2>; 5141 #interrupt-cells = <2>; 5142 interrupt-parent = <&intc>; 5143 interrupt-controller; 5144 }; 5145 5146 tsens2: thermal-sensor@c251000 { 5147 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 5148 reg = <0 0x0c251000 0 0x1ff>, 5149 <0 0x0c224000 0 0x8>; 5150 #qcom,sensors = <11>; 5151 interrupts-extended = <&pdc 122 IRQ_TYPE_LEVEL_HIGH>, 5152 <&pdc 124 IRQ_TYPE_LEVEL_HIGH>; 5153 interrupt-names = "uplow", "critical"; 5154 #thermal-sensor-cells = <1>; 5155 }; 5156 5157 tsens3: thermal-sensor@c252000 { 5158 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 5159 reg = <0 0x0c252000 0 0x1ff>, 5160 <0 0x0c225000 0 0x8>; 5161 #qcom,sensors = <5>; 5162 interrupts-extended = <&pdc 123 IRQ_TYPE_LEVEL_HIGH>, 5163 <&pdc 125 IRQ_TYPE_LEVEL_HIGH>; 5164 interrupt-names = "uplow", "critical"; 5165 #thermal-sensor-cells = <1>; 5166 }; 5167 5168 tsens0: thermal-sensor@c263000 { 5169 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 5170 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 5171 <0 0x0c222000 0 0x8>; /* SROT */ 5172 #qcom,sensors = <14>; 5173 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 5174 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 5175 interrupt-names = "uplow", "critical"; 5176 #thermal-sensor-cells = <1>; 5177 }; 5178 5179 restart@c264000 { 5180 compatible = "qcom,pshold"; 5181 reg = <0 0x0c264000 0 0x4>; 5182 /* TZ seems to block access */ 5183 status = "reserved"; 5184 }; 5185 5186 tsens1: thermal-sensor@c265000 { 5187 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 5188 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 5189 <0 0x0c223000 0 0x8>; /* SROT */ 5190 #qcom,sensors = <16>; 5191 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 5192 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 5193 interrupt-names = "uplow", "critical"; 5194 #thermal-sensor-cells = <1>; 5195 }; 5196 5197 aoss_qmp: power-management@c300000 { 5198 compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp"; 5199 reg = <0 0x0c300000 0 0x400>; 5200 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; 5201 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 5202 5203 #clock-cells = <0>; 5204 }; 5205 5206 sram@c3f0000 { 5207 compatible = "qcom,rpmh-stats"; 5208 reg = <0 0x0c3f0000 0 0x400>; 5209 qcom,qmp = <&aoss_qmp>; 5210 }; 5211 5212 spmi_bus: spmi@c440000 { 5213 compatible = "qcom,spmi-pmic-arb"; 5214 reg = <0 0x0c440000 0 0x1100>, 5215 <0 0x0c600000 0 0x2000000>, 5216 <0 0x0e600000 0 0x100000>, 5217 <0 0x0e700000 0 0xa0000>, 5218 <0 0x0c40a000 0 0x26000>; 5219 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 5220 interrupt-names = "periph_irq"; 5221 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5222 qcom,ee = <0>; 5223 qcom,channel = <0>; 5224 #address-cells = <2>; 5225 #size-cells = <0>; 5226 interrupt-controller; 5227 #interrupt-cells = <4>; 5228 }; 5229 5230 tlmm: pinctrl@f100000 { 5231 compatible = "qcom,sc8280xp-tlmm"; 5232 reg = <0 0x0f100000 0 0x300000>; 5233 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 5234 gpio-controller; 5235 #gpio-cells = <2>; 5236 interrupt-controller; 5237 #interrupt-cells = <2>; 5238 gpio-ranges = <&tlmm 0 0 230>; 5239 wakeup-parent = <&pdc>; 5240 5241 cci0_default: cci0-default-state { 5242 cci0_i2c0_default: cci0-i2c0-default-pins { 5243 /* cci_i2c_sda0, cci_i2c_scl0 */ 5244 pins = "gpio113", "gpio114"; 5245 function = "cci_i2c"; 5246 drive-strength = <2>; 5247 bias-pull-up; 5248 }; 5249 5250 cci0_i2c1_default: cci0-i2c1-default-pins { 5251 /* cci_i2c_sda1, cci_i2c_scl1 */ 5252 pins = "gpio115", "gpio116"; 5253 function = "cci_i2c"; 5254 drive-strength = <2>; 5255 bias-pull-up; 5256 }; 5257 }; 5258 5259 cci0_sleep: cci0-sleep-state { 5260 cci0_i2c0_sleep: cci0-i2c0-sleep-pins { 5261 /* cci_i2c_sda0, cci_i2c_scl0 */ 5262 pins = "gpio113", "gpio114"; 5263 function = "cci_i2c"; 5264 drive-strength = <2>; 5265 bias-pull-down; 5266 }; 5267 5268 cci0_i2c1_sleep: cci0-i2c1-sleep-pins { 5269 /* cci_i2c_sda1, cci_i2c_scl1 */ 5270 pins = "gpio115", "gpio116"; 5271 function = "cci_i2c"; 5272 drive-strength = <2>; 5273 bias-pull-down; 5274 }; 5275 }; 5276 5277 cci1_default: cci1-default-state { 5278 cci1_i2c0_default: cci1-i2c0-default-pins { 5279 /* cci_i2c_sda2, cci_i2c_scl2 */ 5280 pins = "gpio10","gpio11"; 5281 function = "cci_i2c"; 5282 drive-strength = <2>; 5283 bias-pull-up; 5284 }; 5285 5286 cci1_i2c1_default: cci1-i2c1-default-pins { 5287 /* cci_i2c_sda3, cci_i2c_scl3 */ 5288 pins = "gpio123","gpio124"; 5289 function = "cci_i2c"; 5290 drive-strength = <2>; 5291 bias-pull-up; 5292 }; 5293 }; 5294 5295 cci1_sleep: cci1-sleep-state { 5296 cci1_i2c0_sleep: cci1-i2c0-sleep-pins { 5297 /* cci_i2c_sda2, cci_i2c_scl2 */ 5298 pins = "gpio10","gpio11"; 5299 function = "cci_i2c"; 5300 drive-strength = <2>; 5301 bias-pull-down; 5302 }; 5303 5304 cci1_i2c1_sleep: cci1-i2c1-sleep-pins { 5305 /* cci_i2c_sda3, cci_i2c_scl3 */ 5306 pins = "gpio123","gpio124"; 5307 function = "cci_i2c"; 5308 drive-strength = <2>; 5309 bias-pull-down; 5310 }; 5311 }; 5312 5313 cci2_default: cci2-default-state { 5314 cci2_i2c0_default: cci2-i2c0-default-pins { 5315 /* cci_i2c_sda4, cci_i2c_scl4 */ 5316 pins = "gpio117","gpio118"; 5317 function = "cci_i2c"; 5318 drive-strength = <2>; 5319 bias-pull-up; 5320 }; 5321 5322 cci2_i2c1_default: cci2-i2c1-default-pins { 5323 /* cci_i2c_sda5, cci_i2c_scl5 */ 5324 pins = "gpio12","gpio13"; 5325 function = "cci_i2c"; 5326 drive-strength = <2>; 5327 bias-pull-up; 5328 }; 5329 }; 5330 5331 cci2_sleep: cci2-sleep-state { 5332 cci2_i2c0_sleep: cci2-i2c0-sleep-pins { 5333 /* cci_i2c_sda4, cci_i2c_scl4 */ 5334 pins = "gpio117","gpio118"; 5335 function = "cci_i2c"; 5336 drive-strength = <2>; 5337 bias-pull-down; 5338 }; 5339 5340 cci2_i2c1_sleep: cci2-i2c1-sleep-pins { 5341 /* cci_i2c_sda5, cci_i2c_scl5 */ 5342 pins = "gpio12","gpio13"; 5343 function = "cci_i2c"; 5344 drive-strength = <2>; 5345 bias-pull-down; 5346 }; 5347 }; 5348 5349 cci3_default: cci3-default-state { 5350 cci3_i2c0_default: cci3-i2c0-default-pins { 5351 /* cci_i2c_sda6, cci_i2c_scl6 */ 5352 pins = "gpio145","gpio146"; 5353 function = "cci_i2c"; 5354 drive-strength = <2>; 5355 bias-pull-up; 5356 }; 5357 5358 cci3_i2c1_default: cci3-i2c1-default-pins { 5359 /* cci_i2c_sda7, cci_i2c_scl7 */ 5360 pins = "gpio164","gpio165"; 5361 function = "cci_i2c"; 5362 drive-strength = <2>; 5363 bias-pull-up; 5364 }; 5365 }; 5366 5367 cci3_sleep: cci3-sleep-state { 5368 cci3_i2c0_sleep: cci3-i2c0-sleep-pins { 5369 /* cci_i2c_sda6, cci_i2c_scl6 */ 5370 pins = "gpio145","gpio146"; 5371 function = "cci_i2c"; 5372 drive-strength = <2>; 5373 bias-pull-down; 5374 }; 5375 5376 cci3_i2c1_sleep: cci3-i2c1-sleep-pins { 5377 /* cci_i2c_sda7, cci_i2c_scl7 */ 5378 pins = "gpio164","gpio165"; 5379 function = "cci_i2c"; 5380 drive-strength = <2>; 5381 bias-pull-down; 5382 }; 5383 }; 5384 5385 qup_uart18_default: qup-uart18-default-state { 5386 cts-pins { 5387 pins = "gpio66"; 5388 function = "qup18"; 5389 drive-strength = <2>; 5390 bias-disable; 5391 }; 5392 5393 rts-pins { 5394 pins = "gpio67"; 5395 function = "qup18"; 5396 drive-strength = <2>; 5397 bias-disable; 5398 }; 5399 5400 tx-pins { 5401 pins = "gpio68"; 5402 function = "qup18"; 5403 drive-strength = <2>; 5404 bias-disable; 5405 }; 5406 5407 rx-pins { 5408 pins = "gpio69"; 5409 function = "qup18"; 5410 drive-strength = <2>; 5411 bias-disable; 5412 }; 5413 }; 5414 }; 5415 5416 pcie_smmu: iommu@14f80000 { 5417 compatible = "arm,smmu-v3"; 5418 reg = <0 0x14f80000 0 0x80000>; 5419 #iommu-cells = <1>; 5420 interrupts = <GIC_SPI 951 IRQ_TYPE_EDGE_RISING>, 5421 <GIC_SPI 955 IRQ_TYPE_EDGE_RISING>, 5422 <GIC_SPI 953 IRQ_TYPE_EDGE_RISING>; 5423 interrupt-names = "eventq", 5424 "gerror", 5425 "cmdq-sync"; 5426 dma-coherent; 5427 status = "reserved"; /* Controlled by QHEE. */ 5428 }; 5429 5430 apps_smmu: iommu@15000000 { 5431 compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500"; 5432 reg = <0 0x15000000 0 0x100000>; 5433 #iommu-cells = <2>; 5434 #global-interrupts = <2>; 5435 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 5436 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5437 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5438 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5439 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5440 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5441 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5442 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5443 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5444 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5445 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5446 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5447 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5448 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5449 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5450 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5451 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5452 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5453 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5454 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5455 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5456 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5457 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5458 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5459 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5460 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5461 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5462 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5463 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5464 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5465 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5466 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5467 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5468 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5469 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5470 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5471 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5472 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5473 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5474 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5475 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5476 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5477 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5478 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5479 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5480 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5481 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5482 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5483 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5484 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5485 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5486 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5487 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5488 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5489 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5490 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5491 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5492 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5493 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5494 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5495 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5496 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5497 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5498 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5499 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5500 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5501 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5502 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5503 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5504 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5505 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5506 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5507 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5508 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5509 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5510 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5511 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5512 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5513 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5514 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5515 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 5516 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5517 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5518 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5519 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 5520 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5521 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5522 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5523 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5524 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5525 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5526 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5527 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 5528 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 5529 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 5530 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 5531 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 5532 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 5533 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 5534 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 5535 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 5536 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 5537 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 5538 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 5539 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 5540 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 5541 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 5542 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 5543 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 5544 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 5545 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 5546 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 5547 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 5548 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 5549 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 5550 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 5551 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 5552 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 5553 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 5554 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 5555 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 5556 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 5557 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 5558 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 5559 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 5560 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 5561 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 5562 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 5563 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>, 5564 <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>; 5565 dma-coherent; 5566 }; 5567 5568 intc: interrupt-controller@17a00000 { 5569 compatible = "arm,gic-v3"; 5570 interrupt-controller; 5571 #interrupt-cells = <3>; 5572 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 5573 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 5574 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5575 #redistributor-regions = <1>; 5576 redistributor-stride = <0 0x20000>; 5577 5578 #address-cells = <2>; 5579 #size-cells = <2>; 5580 ranges; 5581 5582 its: msi-controller@17a40000 { 5583 compatible = "arm,gic-v3-its"; 5584 reg = <0 0x17a40000 0 0x20000>; 5585 msi-controller; 5586 #msi-cells = <1>; 5587 }; 5588 }; 5589 5590 watchdog@17c10000 { 5591 compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt"; 5592 reg = <0 0x17c10000 0 0x1000>; 5593 clocks = <&sleep_clk>; 5594 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 5595 }; 5596 5597 timer@17c20000 { 5598 compatible = "arm,armv7-timer-mem"; 5599 reg = <0x0 0x17c20000 0x0 0x1000>; 5600 #address-cells = <1>; 5601 #size-cells = <1>; 5602 ranges = <0x0 0x0 0x0 0x20000000>; 5603 5604 frame@17c21000 { 5605 frame-number = <0>; 5606 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5607 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5608 reg = <0x17c21000 0x1000>, 5609 <0x17c22000 0x1000>; 5610 }; 5611 5612 frame@17c23000 { 5613 frame-number = <1>; 5614 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5615 reg = <0x17c23000 0x1000>; 5616 status = "disabled"; 5617 }; 5618 5619 frame@17c25000 { 5620 frame-number = <2>; 5621 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5622 reg = <0x17c25000 0x1000>; 5623 status = "disabled"; 5624 }; 5625 5626 frame@17c27000 { 5627 frame-number = <3>; 5628 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5629 reg = <0x17c26000 0x1000>; 5630 status = "disabled"; 5631 }; 5632 5633 frame@17c29000 { 5634 frame-number = <4>; 5635 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5636 reg = <0x17c29000 0x1000>; 5637 status = "disabled"; 5638 }; 5639 5640 frame@17c2b000 { 5641 frame-number = <5>; 5642 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5643 reg = <0x17c2b000 0x1000>; 5644 status = "disabled"; 5645 }; 5646 5647 frame@17c2d000 { 5648 frame-number = <6>; 5649 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5650 reg = <0x17c2d000 0x1000>; 5651 status = "disabled"; 5652 }; 5653 }; 5654 5655 apps_rsc: rsc@18200000 { 5656 compatible = "qcom,rpmh-rsc"; 5657 reg = <0x0 0x18200000 0x0 0x10000>, 5658 <0x0 0x18210000 0x0 0x10000>, 5659 <0x0 0x18220000 0x0 0x10000>; 5660 reg-names = "drv-0", "drv-1", "drv-2"; 5661 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5662 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5663 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5664 qcom,tcs-offset = <0xd00>; 5665 qcom,drv-id = <2>; 5666 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 5667 <WAKE_TCS 3>, <CONTROL_TCS 1>; 5668 label = "apps_rsc"; 5669 power-domains = <&cluster_pd>; 5670 5671 apps_bcm_voter: bcm-voter { 5672 compatible = "qcom,bcm-voter"; 5673 }; 5674 5675 rpmhcc: clock-controller { 5676 compatible = "qcom,sc8280xp-rpmh-clk"; 5677 #clock-cells = <1>; 5678 clock-names = "xo"; 5679 clocks = <&xo_board_clk>; 5680 }; 5681 5682 rpmhpd: power-controller { 5683 compatible = "qcom,sc8280xp-rpmhpd"; 5684 #power-domain-cells = <1>; 5685 operating-points-v2 = <&rpmhpd_opp_table>; 5686 5687 rpmhpd_opp_table: opp-table { 5688 compatible = "operating-points-v2"; 5689 5690 rpmhpd_opp_ret: opp1 { 5691 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5692 }; 5693 5694 rpmhpd_opp_min_svs: opp2 { 5695 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5696 }; 5697 5698 rpmhpd_opp_low_svs: opp3 { 5699 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5700 }; 5701 5702 rpmhpd_opp_svs: opp4 { 5703 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5704 }; 5705 5706 rpmhpd_opp_svs_l1: opp5 { 5707 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5708 }; 5709 5710 rpmhpd_opp_nom: opp6 { 5711 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5712 }; 5713 5714 rpmhpd_opp_nom_l1: opp7 { 5715 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5716 }; 5717 5718 rpmhpd_opp_nom_l2: opp8 { 5719 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5720 }; 5721 5722 rpmhpd_opp_turbo: opp9 { 5723 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5724 }; 5725 5726 rpmhpd_opp_turbo_l1: opp10 { 5727 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5728 }; 5729 }; 5730 }; 5731 }; 5732 5733 epss_l3: interconnect@18590000 { 5734 compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3"; 5735 reg = <0 0x18590000 0 0x1000>; 5736 5737 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5738 clock-names = "xo", "alternate"; 5739 5740 #interconnect-cells = <1>; 5741 }; 5742 5743 cpufreq_hw: cpufreq@18591000 { 5744 compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss"; 5745 reg = <0 0x18591000 0 0x1000>, 5746 <0 0x18592000 0 0x1000>; 5747 reg-names = "freq-domain0", "freq-domain1"; 5748 5749 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5750 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 5751 interrupt-names = "dcvsh-irq-0", 5752 "dcvsh-irq-1"; 5753 5754 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5755 clock-names = "xo", "alternate"; 5756 5757 #freq-domain-cells = <1>; 5758 #clock-cells = <1>; 5759 }; 5760 5761 remoteproc_nsp0: remoteproc@1b300000 { 5762 compatible = "qcom,sc8280xp-nsp0-pas"; 5763 reg = <0 0x1b300000 0 0x10000>; 5764 5765 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 5766 <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>, 5767 <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>, 5768 <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>, 5769 <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>; 5770 interrupt-names = "wdog", "fatal", "ready", 5771 "handover", "stop-ack"; 5772 5773 clocks = <&rpmhcc RPMH_CXO_CLK>; 5774 clock-names = "xo"; 5775 5776 power-domains = <&rpmhpd SC8280XP_NSP>; 5777 power-domain-names = "nsp"; 5778 5779 memory-region = <&pil_nsp0_mem>; 5780 5781 qcom,smem-states = <&smp2p_nsp0_out 0>; 5782 qcom,smem-state-names = "stop"; 5783 5784 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 5785 5786 status = "disabled"; 5787 5788 glink-edge { 5789 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 5790 IPCC_MPROC_SIGNAL_GLINK_QMP 5791 IRQ_TYPE_EDGE_RISING>; 5792 mboxes = <&ipcc IPCC_CLIENT_CDSP 5793 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5794 5795 label = "nsp0"; 5796 qcom,remote-pid = <5>; 5797 5798 fastrpc { 5799 compatible = "qcom,fastrpc"; 5800 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5801 label = "cdsp"; 5802 #address-cells = <1>; 5803 #size-cells = <0>; 5804 5805 compute-cb@1 { 5806 compatible = "qcom,fastrpc-compute-cb"; 5807 reg = <1>; 5808 iommus = <&apps_smmu 0x3181 0x0420>; 5809 }; 5810 5811 compute-cb@2 { 5812 compatible = "qcom,fastrpc-compute-cb"; 5813 reg = <2>; 5814 iommus = <&apps_smmu 0x3182 0x0420>; 5815 }; 5816 5817 compute-cb@3 { 5818 compatible = "qcom,fastrpc-compute-cb"; 5819 reg = <3>; 5820 iommus = <&apps_smmu 0x3183 0x0420>; 5821 }; 5822 5823 compute-cb@4 { 5824 compatible = "qcom,fastrpc-compute-cb"; 5825 reg = <4>; 5826 iommus = <&apps_smmu 0x3184 0x0420>; 5827 }; 5828 5829 compute-cb@5 { 5830 compatible = "qcom,fastrpc-compute-cb"; 5831 reg = <5>; 5832 iommus = <&apps_smmu 0x3185 0x0420>; 5833 }; 5834 5835 compute-cb@6 { 5836 compatible = "qcom,fastrpc-compute-cb"; 5837 reg = <6>; 5838 iommus = <&apps_smmu 0x3186 0x0420>; 5839 }; 5840 5841 compute-cb@7 { 5842 compatible = "qcom,fastrpc-compute-cb"; 5843 reg = <7>; 5844 iommus = <&apps_smmu 0x3187 0x0420>; 5845 }; 5846 5847 compute-cb@8 { 5848 compatible = "qcom,fastrpc-compute-cb"; 5849 reg = <8>; 5850 iommus = <&apps_smmu 0x3188 0x0420>; 5851 }; 5852 5853 compute-cb@9 { 5854 compatible = "qcom,fastrpc-compute-cb"; 5855 reg = <9>; 5856 iommus = <&apps_smmu 0x318b 0x0420>; 5857 }; 5858 5859 compute-cb@10 { 5860 compatible = "qcom,fastrpc-compute-cb"; 5861 reg = <10>; 5862 iommus = <&apps_smmu 0x318b 0x0420>; 5863 }; 5864 5865 compute-cb@11 { 5866 compatible = "qcom,fastrpc-compute-cb"; 5867 reg = <11>; 5868 iommus = <&apps_smmu 0x318c 0x0420>; 5869 }; 5870 5871 compute-cb@12 { 5872 compatible = "qcom,fastrpc-compute-cb"; 5873 reg = <12>; 5874 iommus = <&apps_smmu 0x318d 0x0420>; 5875 }; 5876 5877 compute-cb@13 { 5878 compatible = "qcom,fastrpc-compute-cb"; 5879 reg = <13>; 5880 iommus = <&apps_smmu 0x318e 0x0420>; 5881 }; 5882 5883 compute-cb@14 { 5884 compatible = "qcom,fastrpc-compute-cb"; 5885 reg = <14>; 5886 iommus = <&apps_smmu 0x318f 0x0420>; 5887 }; 5888 }; 5889 }; 5890 }; 5891 5892 remoteproc_nsp1: remoteproc@21300000 { 5893 compatible = "qcom,sc8280xp-nsp1-pas"; 5894 reg = <0 0x21300000 0 0x10000>; 5895 5896 interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_EDGE_RISING>, 5897 <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>, 5898 <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>, 5899 <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>, 5900 <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>; 5901 interrupt-names = "wdog", "fatal", "ready", 5902 "handover", "stop-ack"; 5903 5904 clocks = <&rpmhcc RPMH_CXO_CLK>; 5905 clock-names = "xo"; 5906 5907 power-domains = <&rpmhpd SC8280XP_NSP>; 5908 power-domain-names = "nsp"; 5909 5910 memory-region = <&pil_nsp1_mem>; 5911 5912 qcom,smem-states = <&smp2p_nsp1_out 0>; 5913 qcom,smem-state-names = "stop"; 5914 5915 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>; 5916 5917 status = "disabled"; 5918 5919 glink-edge { 5920 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 5921 IPCC_MPROC_SIGNAL_GLINK_QMP 5922 IRQ_TYPE_EDGE_RISING>; 5923 mboxes = <&ipcc IPCC_CLIENT_NSP1 5924 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5925 5926 label = "nsp1"; 5927 qcom,remote-pid = <12>; 5928 }; 5929 }; 5930 5931 mdss1: display-subsystem@22000000 { 5932 compatible = "qcom,sc8280xp-mdss"; 5933 reg = <0 0x22000000 0 0x1000>; 5934 reg-names = "mdss"; 5935 5936 clocks = <&gcc GCC_DISP_AHB_CLK>, 5937 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 5938 <&dispcc1 DISP_CC_MDSS_MDP_CLK>; 5939 clock-names = "iface", 5940 "ahb", 5941 "core"; 5942 interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>, 5943 <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>; 5944 interconnect-names = "mdp0-mem", "mdp1-mem"; 5945 interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; 5946 5947 iommus = <&apps_smmu 0x1800 0x402>; 5948 power-domains = <&dispcc1 MDSS_GDSC>; 5949 resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>; 5950 5951 interrupt-controller; 5952 #interrupt-cells = <1>; 5953 #address-cells = <2>; 5954 #size-cells = <2>; 5955 ranges; 5956 5957 status = "disabled"; 5958 5959 mdss1_mdp: display-controller@22001000 { 5960 compatible = "qcom,sc8280xp-dpu"; 5961 reg = <0 0x22001000 0 0x8f000>, 5962 <0 0x220b0000 0 0x3000>; 5963 reg-names = "mdp", "vbif"; 5964 5965 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 5966 <&gcc GCC_DISP_SF_AXI_CLK>, 5967 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 5968 <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>, 5969 <&dispcc1 DISP_CC_MDSS_MDP_CLK>, 5970 <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 5971 clock-names = "bus", 5972 "nrt_bus", 5973 "iface", 5974 "lut", 5975 "core", 5976 "vsync"; 5977 interrupt-parent = <&mdss1>; 5978 interrupts = <0>; 5979 power-domains = <&rpmhpd SC8280XP_MMCX>; 5980 5981 assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 5982 assigned-clock-rates = <19200000>; 5983 operating-points-v2 = <&mdss1_mdp_opp_table>; 5984 5985 ports { 5986 #address-cells = <1>; 5987 #size-cells = <0>; 5988 5989 port@0 { 5990 reg = <0>; 5991 mdss1_intf0_out: endpoint { 5992 remote-endpoint = <&mdss1_dp0_in>; 5993 }; 5994 }; 5995 5996 port@4 { 5997 reg = <4>; 5998 mdss1_intf4_out: endpoint { 5999 remote-endpoint = <&mdss1_dp1_in>; 6000 }; 6001 }; 6002 6003 port@5 { 6004 reg = <5>; 6005 mdss1_intf5_out: endpoint { 6006 remote-endpoint = <&mdss1_dp3_in>; 6007 }; 6008 }; 6009 6010 port@6 { 6011 reg = <6>; 6012 mdss1_intf6_out: endpoint { 6013 remote-endpoint = <&mdss1_dp2_in>; 6014 }; 6015 }; 6016 }; 6017 6018 mdss1_mdp_opp_table: opp-table { 6019 compatible = "operating-points-v2"; 6020 6021 opp-200000000 { 6022 opp-hz = /bits/ 64 <200000000>; 6023 required-opps = <&rpmhpd_opp_low_svs>; 6024 }; 6025 6026 opp-300000000 { 6027 opp-hz = /bits/ 64 <300000000>; 6028 required-opps = <&rpmhpd_opp_svs>; 6029 }; 6030 6031 opp-375000000 { 6032 opp-hz = /bits/ 64 <375000000>; 6033 required-opps = <&rpmhpd_opp_svs_l1>; 6034 }; 6035 6036 opp-500000000 { 6037 opp-hz = /bits/ 64 <500000000>; 6038 required-opps = <&rpmhpd_opp_nom>; 6039 }; 6040 opp-600000000 { 6041 opp-hz = /bits/ 64 <600000000>; 6042 required-opps = <&rpmhpd_opp_turbo_l1>; 6043 }; 6044 }; 6045 }; 6046 6047 mdss1_dp0: displayport-controller@22090000 { 6048 compatible = "qcom,sc8280xp-dp"; 6049 reg = <0 0x22090000 0 0x200>, 6050 <0 0x22090200 0 0x200>, 6051 <0 0x22090400 0 0x600>, 6052 <0 0x22091000 0 0x400>, 6053 <0 0x22091400 0 0x400>; 6054 6055 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6056 <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 6057 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>, 6058 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 6059 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 6060 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; 6061 clock-names = "core_iface", "core_aux", 6062 "ctrl_link", 6063 "ctrl_link_iface", "stream_pixel", 6064 "stream_1_pixel"; 6065 interrupt-parent = <&mdss1>; 6066 interrupts = <12>; 6067 phys = <&mdss1_dp0_phy>; 6068 phy-names = "dp"; 6069 power-domains = <&rpmhpd SC8280XP_MMCX>; 6070 6071 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 6072 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 6073 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; 6074 assigned-clock-parents = <&mdss1_dp0_phy 0>, 6075 <&mdss1_dp0_phy 1>, 6076 <&mdss1_dp0_phy 1>; 6077 operating-points-v2 = <&mdss1_dp0_opp_table>; 6078 6079 #sound-dai-cells = <0>; 6080 6081 status = "disabled"; 6082 6083 ports { 6084 #address-cells = <1>; 6085 #size-cells = <0>; 6086 6087 port@0 { 6088 reg = <0>; 6089 mdss1_dp0_in: endpoint { 6090 remote-endpoint = <&mdss1_intf0_out>; 6091 }; 6092 }; 6093 6094 port@1 { 6095 reg = <1>; 6096 6097 mdss1_dp0_out: endpoint { 6098 }; 6099 }; 6100 }; 6101 6102 mdss1_dp0_opp_table: opp-table { 6103 compatible = "operating-points-v2"; 6104 6105 opp-160000000 { 6106 opp-hz = /bits/ 64 <160000000>; 6107 required-opps = <&rpmhpd_opp_low_svs>; 6108 }; 6109 6110 opp-270000000 { 6111 opp-hz = /bits/ 64 <270000000>; 6112 required-opps = <&rpmhpd_opp_svs>; 6113 }; 6114 6115 opp-540000000 { 6116 opp-hz = /bits/ 64 <540000000>; 6117 required-opps = <&rpmhpd_opp_svs_l1>; 6118 }; 6119 6120 opp-810000000 { 6121 opp-hz = /bits/ 64 <810000000>; 6122 required-opps = <&rpmhpd_opp_nom>; 6123 }; 6124 }; 6125 }; 6126 6127 mdss1_dp1: displayport-controller@22098000 { 6128 compatible = "qcom,sc8280xp-dp"; 6129 reg = <0 0x22098000 0 0x200>, 6130 <0 0x22098200 0 0x200>, 6131 <0 0x22098400 0 0x600>, 6132 <0 0x22099000 0 0x400>, 6133 <0 0x22099400 0 0x400>; 6134 6135 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6136 <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 6137 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>, 6138 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 6139 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, 6140 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; 6141 clock-names = "core_iface", "core_aux", 6142 "ctrl_link", 6143 "ctrl_link_iface", "stream_pixel", 6144 "stream_1_pixel"; 6145 interrupt-parent = <&mdss1>; 6146 interrupts = <13>; 6147 phys = <&mdss1_dp1_phy>; 6148 phy-names = "dp"; 6149 power-domains = <&rpmhpd SC8280XP_MMCX>; 6150 6151 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 6152 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, 6153 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; 6154 assigned-clock-parents = <&mdss1_dp1_phy 0>, 6155 <&mdss1_dp1_phy 1>, 6156 <&mdss1_dp1_phy 1>; 6157 operating-points-v2 = <&mdss1_dp1_opp_table>; 6158 6159 #sound-dai-cells = <0>; 6160 6161 status = "disabled"; 6162 6163 ports { 6164 #address-cells = <1>; 6165 #size-cells = <0>; 6166 6167 port@0 { 6168 reg = <0>; 6169 mdss1_dp1_in: endpoint { 6170 remote-endpoint = <&mdss1_intf4_out>; 6171 }; 6172 }; 6173 6174 port@1 { 6175 reg = <1>; 6176 6177 mdss1_dp1_out: endpoint { 6178 }; 6179 }; 6180 }; 6181 6182 mdss1_dp1_opp_table: opp-table { 6183 compatible = "operating-points-v2"; 6184 6185 opp-160000000 { 6186 opp-hz = /bits/ 64 <160000000>; 6187 required-opps = <&rpmhpd_opp_low_svs>; 6188 }; 6189 6190 opp-270000000 { 6191 opp-hz = /bits/ 64 <270000000>; 6192 required-opps = <&rpmhpd_opp_svs>; 6193 }; 6194 6195 opp-540000000 { 6196 opp-hz = /bits/ 64 <540000000>; 6197 required-opps = <&rpmhpd_opp_svs_l1>; 6198 }; 6199 6200 opp-810000000 { 6201 opp-hz = /bits/ 64 <810000000>; 6202 required-opps = <&rpmhpd_opp_nom>; 6203 }; 6204 }; 6205 }; 6206 6207 mdss1_dp2: displayport-controller@2209a000 { 6208 compatible = "qcom,sc8280xp-dp"; 6209 reg = <0 0x2209a000 0 0x200>, 6210 <0 0x2209a200 0 0x200>, 6211 <0 0x2209a400 0 0x600>, 6212 <0 0x2209b000 0 0x400>, 6213 <0 0x2209b400 0 0x400>; 6214 6215 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6216 <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 6217 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>, 6218 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 6219 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, 6220 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; 6221 clock-names = "core_iface", "core_aux", 6222 "ctrl_link", 6223 "ctrl_link_iface", "stream_pixel", 6224 "stream_1_pixel"; 6225 interrupt-parent = <&mdss1>; 6226 interrupts = <14>; 6227 phys = <&mdss1_dp2_phy>; 6228 phy-names = "dp"; 6229 power-domains = <&rpmhpd SC8280XP_MMCX>; 6230 6231 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 6232 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, 6233 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; 6234 assigned-clock-parents = <&mdss1_dp2_phy 0>, 6235 <&mdss1_dp2_phy 1>, 6236 <&mdss1_dp2_phy 1>; 6237 operating-points-v2 = <&mdss1_dp2_opp_table>; 6238 6239 #sound-dai-cells = <0>; 6240 6241 status = "disabled"; 6242 6243 ports { 6244 #address-cells = <1>; 6245 #size-cells = <0>; 6246 6247 port@0 { 6248 reg = <0>; 6249 mdss1_dp2_in: endpoint { 6250 remote-endpoint = <&mdss1_intf6_out>; 6251 }; 6252 }; 6253 6254 port@1 { 6255 reg = <1>; 6256 6257 mdss1_dp2_out: endpoint { 6258 }; 6259 }; 6260 }; 6261 6262 mdss1_dp2_opp_table: opp-table { 6263 compatible = "operating-points-v2"; 6264 6265 opp-160000000 { 6266 opp-hz = /bits/ 64 <160000000>; 6267 required-opps = <&rpmhpd_opp_low_svs>; 6268 }; 6269 6270 opp-270000000 { 6271 opp-hz = /bits/ 64 <270000000>; 6272 required-opps = <&rpmhpd_opp_svs>; 6273 }; 6274 6275 opp-540000000 { 6276 opp-hz = /bits/ 64 <540000000>; 6277 required-opps = <&rpmhpd_opp_svs_l1>; 6278 }; 6279 6280 opp-810000000 { 6281 opp-hz = /bits/ 64 <810000000>; 6282 required-opps = <&rpmhpd_opp_nom>; 6283 }; 6284 }; 6285 }; 6286 6287 mdss1_dp3: displayport-controller@220a0000 { 6288 compatible = "qcom,sc8280xp-dp"; 6289 reg = <0 0x220a0000 0 0x200>, 6290 <0 0x220a0200 0 0x200>, 6291 <0 0x220a0400 0 0x600>, 6292 <0 0x220a1000 0 0x400>, 6293 <0 0x220a1400 0 0x400>; 6294 6295 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 6296 <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 6297 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK>, 6298 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 6299 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 6300 clock-names = "core_iface", "core_aux", 6301 "ctrl_link", 6302 "ctrl_link_iface", "stream_pixel"; 6303 interrupt-parent = <&mdss1>; 6304 interrupts = <15>; 6305 phys = <&mdss1_dp3_phy>; 6306 phy-names = "dp"; 6307 power-domains = <&rpmhpd SC8280XP_MMCX>; 6308 6309 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 6310 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 6311 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>; 6312 operating-points-v2 = <&mdss1_dp3_opp_table>; 6313 6314 #sound-dai-cells = <0>; 6315 6316 status = "disabled"; 6317 6318 ports { 6319 #address-cells = <1>; 6320 #size-cells = <0>; 6321 6322 port@0 { 6323 reg = <0>; 6324 mdss1_dp3_in: endpoint { 6325 remote-endpoint = <&mdss1_intf5_out>; 6326 }; 6327 }; 6328 6329 port@1 { 6330 reg = <1>; 6331 6332 mdss1_dp3_out: endpoint { 6333 }; 6334 }; 6335 }; 6336 6337 mdss1_dp3_opp_table: opp-table { 6338 compatible = "operating-points-v2"; 6339 6340 opp-160000000 { 6341 opp-hz = /bits/ 64 <160000000>; 6342 required-opps = <&rpmhpd_opp_low_svs>; 6343 }; 6344 6345 opp-270000000 { 6346 opp-hz = /bits/ 64 <270000000>; 6347 required-opps = <&rpmhpd_opp_svs>; 6348 }; 6349 6350 opp-540000000 { 6351 opp-hz = /bits/ 64 <540000000>; 6352 required-opps = <&rpmhpd_opp_svs_l1>; 6353 }; 6354 6355 opp-810000000 { 6356 opp-hz = /bits/ 64 <810000000>; 6357 required-opps = <&rpmhpd_opp_nom>; 6358 }; 6359 }; 6360 }; 6361 }; 6362 6363 mdss1_dp2_phy: phy@220c2a00 { 6364 compatible = "qcom,sc8280xp-dp-phy"; 6365 reg = <0 0x220c2a00 0 0x19c>, 6366 <0 0x220c2200 0 0xec>, 6367 <0 0x220c2600 0 0xec>, 6368 <0 0x220c2000 0 0x1c8>; 6369 6370 clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 6371 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 6372 clock-names = "aux", "cfg_ahb"; 6373 power-domains = <&rpmhpd SC8280XP_MX>; 6374 6375 #clock-cells = <1>; 6376 #phy-cells = <0>; 6377 6378 status = "disabled"; 6379 }; 6380 6381 mdss1_dp3_phy: phy@220c5a00 { 6382 compatible = "qcom,sc8280xp-dp-phy"; 6383 reg = <0 0x220c5a00 0 0x19c>, 6384 <0 0x220c5200 0 0xec>, 6385 <0 0x220c5600 0 0xec>, 6386 <0 0x220c5000 0 0x1c8>; 6387 6388 clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 6389 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 6390 clock-names = "aux", "cfg_ahb"; 6391 power-domains = <&rpmhpd SC8280XP_MX>; 6392 6393 #clock-cells = <1>; 6394 #phy-cells = <0>; 6395 6396 status = "disabled"; 6397 }; 6398 6399 dispcc1: clock-controller@22100000 { 6400 compatible = "qcom,sc8280xp-dispcc1"; 6401 reg = <0 0x22100000 0 0x20000>; 6402 6403 clocks = <&gcc GCC_DISP_AHB_CLK>, 6404 <&rpmhcc RPMH_CXO_CLK>, 6405 <0>, 6406 <&mdss1_dp0_phy 0>, 6407 <&mdss1_dp0_phy 1>, 6408 <&mdss1_dp1_phy 0>, 6409 <&mdss1_dp1_phy 1>, 6410 <&mdss1_dp2_phy 0>, 6411 <&mdss1_dp2_phy 1>, 6412 <&mdss1_dp3_phy 0>, 6413 <&mdss1_dp3_phy 1>, 6414 <0>, 6415 <0>, 6416 <0>, 6417 <0>; 6418 power-domains = <&rpmhpd SC8280XP_MMCX>; 6419 6420 #clock-cells = <1>; 6421 #power-domain-cells = <1>; 6422 #reset-cells = <1>; 6423 6424 status = "disabled"; 6425 }; 6426 6427 ethernet1: ethernet@23000000 { 6428 compatible = "qcom,sc8280xp-ethqos"; 6429 reg = <0x0 0x23000000 0x0 0x10000>, 6430 <0x0 0x23016000 0x0 0x100>; 6431 reg-names = "stmmaceth", "rgmii"; 6432 6433 clocks = <&gcc GCC_EMAC1_AXI_CLK>, 6434 <&gcc GCC_EMAC1_SLV_AHB_CLK>, 6435 <&gcc GCC_EMAC1_PTP_CLK>, 6436 <&gcc GCC_EMAC1_RGMII_CLK>; 6437 clock-names = "stmmaceth", 6438 "pclk", 6439 "ptp_ref", 6440 "rgmii"; 6441 6442 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, 6443 <GIC_SPI 919 IRQ_TYPE_LEVEL_HIGH>; 6444 interrupt-names = "macirq", "eth_lpi"; 6445 6446 iommus = <&apps_smmu 0x40 0xf>; 6447 power-domains = <&gcc EMAC_1_GDSC>; 6448 6449 snps,tso; 6450 snps,pbl = <32>; 6451 rx-fifo-depth = <4096>; 6452 tx-fifo-depth = <4096>; 6453 6454 status = "disabled"; 6455 }; 6456 }; 6457 6458 sound: sound { 6459 }; 6460 6461 thermal-zones { 6462 cpu0-thermal { 6463 polling-delay-passive = <250>; 6464 6465 thermal-sensors = <&tsens0 1>; 6466 6467 trips { 6468 cpu-crit { 6469 temperature = <110000>; 6470 hysteresis = <1000>; 6471 type = "critical"; 6472 }; 6473 }; 6474 }; 6475 6476 cpu1-thermal { 6477 polling-delay-passive = <250>; 6478 6479 thermal-sensors = <&tsens0 2>; 6480 6481 trips { 6482 cpu-crit { 6483 temperature = <110000>; 6484 hysteresis = <1000>; 6485 type = "critical"; 6486 }; 6487 }; 6488 }; 6489 6490 cpu2-thermal { 6491 polling-delay-passive = <250>; 6492 6493 thermal-sensors = <&tsens0 3>; 6494 6495 trips { 6496 cpu-crit { 6497 temperature = <110000>; 6498 hysteresis = <1000>; 6499 type = "critical"; 6500 }; 6501 }; 6502 }; 6503 6504 cpu3-thermal { 6505 polling-delay-passive = <250>; 6506 6507 thermal-sensors = <&tsens0 4>; 6508 6509 trips { 6510 cpu-crit { 6511 temperature = <110000>; 6512 hysteresis = <1000>; 6513 type = "critical"; 6514 }; 6515 }; 6516 }; 6517 6518 cpu4-thermal { 6519 polling-delay-passive = <250>; 6520 6521 thermal-sensors = <&tsens0 5>; 6522 6523 trips { 6524 cpu-crit { 6525 temperature = <110000>; 6526 hysteresis = <1000>; 6527 type = "critical"; 6528 }; 6529 }; 6530 }; 6531 6532 cpu5-thermal { 6533 polling-delay-passive = <250>; 6534 6535 thermal-sensors = <&tsens0 6>; 6536 6537 trips { 6538 cpu-crit { 6539 temperature = <110000>; 6540 hysteresis = <1000>; 6541 type = "critical"; 6542 }; 6543 }; 6544 }; 6545 6546 cpu6-thermal { 6547 polling-delay-passive = <250>; 6548 6549 thermal-sensors = <&tsens0 7>; 6550 6551 trips { 6552 cpu-crit { 6553 temperature = <110000>; 6554 hysteresis = <1000>; 6555 type = "critical"; 6556 }; 6557 }; 6558 }; 6559 6560 cpu7-thermal { 6561 polling-delay-passive = <250>; 6562 6563 thermal-sensors = <&tsens0 8>; 6564 6565 trips { 6566 cpu-crit { 6567 temperature = <110000>; 6568 hysteresis = <1000>; 6569 type = "critical"; 6570 }; 6571 }; 6572 }; 6573 6574 cluster0-thermal { 6575 polling-delay-passive = <250>; 6576 6577 thermal-sensors = <&tsens0 9>; 6578 6579 trips { 6580 cpu-crit { 6581 temperature = <110000>; 6582 hysteresis = <1000>; 6583 type = "critical"; 6584 }; 6585 }; 6586 }; 6587 6588 gpu-thermal { 6589 polling-delay-passive = <250>; 6590 6591 thermal-sensors = <&tsens2 2>; 6592 6593 cooling-maps { 6594 map0 { 6595 trip = <&gpu_alert0>; 6596 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6597 }; 6598 }; 6599 6600 trips { 6601 gpu_alert0: trip-point0 { 6602 temperature = <85000>; 6603 hysteresis = <1000>; 6604 type = "passive"; 6605 }; 6606 6607 trip-point1 { 6608 temperature = <110000>; 6609 hysteresis = <1000>; 6610 type = "critical"; 6611 }; 6612 }; 6613 }; 6614 6615 mem-thermal { 6616 polling-delay-passive = <250>; 6617 6618 thermal-sensors = <&tsens1 15>; 6619 6620 trips { 6621 trip-point0 { 6622 temperature = <90000>; 6623 hysteresis = <2000>; 6624 type = "hot"; 6625 }; 6626 }; 6627 }; 6628 }; 6629 6630 timer { 6631 compatible = "arm,armv8-timer"; 6632 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6633 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6634 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6635 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 6636 }; 6637}; 6638