1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Linaro Limited 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> 8#include <dt-bindings/clock/qcom,gcc-sc8280xp.h> 9#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sc8280xp-camcc.h> 12#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> 13#include <dt-bindings/interconnect/qcom,osm-l3.h> 14#include <dt-bindings/interconnect/qcom,sc8280xp.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/phy/phy-qcom-qmp.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/soc/qcom,gpr.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/sound/qcom,q6afe.h> 22#include <dt-bindings/thermal/thermal.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 clocks { 31 xo_board_clk: xo-board-clk { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 }; 35 36 sleep_clk: sleep-clk { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <32764>; 40 }; 41 }; 42 43 cpus { 44 #address-cells = <2>; 45 #size-cells = <0>; 46 47 CPU0: cpu@0 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a78c"; 50 reg = <0x0 0x0>; 51 clocks = <&cpufreq_hw 0>; 52 enable-method = "psci"; 53 capacity-dmips-mhz = <981>; 54 dynamic-power-coefficient = <549>; 55 next-level-cache = <&L2_0>; 56 power-domains = <&CPU_PD0>; 57 power-domain-names = "psci"; 58 qcom,freq-domain = <&cpufreq_hw 0>; 59 operating-points-v2 = <&cpu0_opp_table>; 60 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 61 #cooling-cells = <2>; 62 L2_0: l2-cache { 63 compatible = "cache"; 64 cache-level = <2>; 65 cache-unified; 66 next-level-cache = <&L3_0>; 67 L3_0: l3-cache { 68 compatible = "cache"; 69 cache-level = <3>; 70 cache-unified; 71 }; 72 }; 73 }; 74 75 CPU1: cpu@100 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a78c"; 78 reg = <0x0 0x100>; 79 clocks = <&cpufreq_hw 0>; 80 enable-method = "psci"; 81 capacity-dmips-mhz = <981>; 82 dynamic-power-coefficient = <549>; 83 next-level-cache = <&L2_100>; 84 power-domains = <&CPU_PD1>; 85 power-domain-names = "psci"; 86 qcom,freq-domain = <&cpufreq_hw 0>; 87 operating-points-v2 = <&cpu0_opp_table>; 88 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 89 #cooling-cells = <2>; 90 L2_100: l2-cache { 91 compatible = "cache"; 92 cache-level = <2>; 93 cache-unified; 94 next-level-cache = <&L3_0>; 95 }; 96 }; 97 98 CPU2: cpu@200 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a78c"; 101 reg = <0x0 0x200>; 102 clocks = <&cpufreq_hw 0>; 103 enable-method = "psci"; 104 capacity-dmips-mhz = <981>; 105 dynamic-power-coefficient = <549>; 106 next-level-cache = <&L2_200>; 107 power-domains = <&CPU_PD2>; 108 power-domain-names = "psci"; 109 qcom,freq-domain = <&cpufreq_hw 0>; 110 operating-points-v2 = <&cpu0_opp_table>; 111 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 112 #cooling-cells = <2>; 113 L2_200: l2-cache { 114 compatible = "cache"; 115 cache-level = <2>; 116 cache-unified; 117 next-level-cache = <&L3_0>; 118 }; 119 }; 120 121 CPU3: cpu@300 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a78c"; 124 reg = <0x0 0x300>; 125 clocks = <&cpufreq_hw 0>; 126 enable-method = "psci"; 127 capacity-dmips-mhz = <981>; 128 dynamic-power-coefficient = <549>; 129 next-level-cache = <&L2_300>; 130 power-domains = <&CPU_PD3>; 131 power-domain-names = "psci"; 132 qcom,freq-domain = <&cpufreq_hw 0>; 133 operating-points-v2 = <&cpu0_opp_table>; 134 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 135 #cooling-cells = <2>; 136 L2_300: l2-cache { 137 compatible = "cache"; 138 cache-level = <2>; 139 cache-unified; 140 next-level-cache = <&L3_0>; 141 }; 142 }; 143 144 CPU4: cpu@400 { 145 device_type = "cpu"; 146 compatible = "arm,cortex-x1c"; 147 reg = <0x0 0x400>; 148 clocks = <&cpufreq_hw 1>; 149 enable-method = "psci"; 150 capacity-dmips-mhz = <1024>; 151 dynamic-power-coefficient = <590>; 152 next-level-cache = <&L2_400>; 153 power-domains = <&CPU_PD4>; 154 power-domain-names = "psci"; 155 qcom,freq-domain = <&cpufreq_hw 1>; 156 operating-points-v2 = <&cpu4_opp_table>; 157 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 158 #cooling-cells = <2>; 159 L2_400: l2-cache { 160 compatible = "cache"; 161 cache-level = <2>; 162 cache-unified; 163 next-level-cache = <&L3_0>; 164 }; 165 }; 166 167 CPU5: cpu@500 { 168 device_type = "cpu"; 169 compatible = "arm,cortex-x1c"; 170 reg = <0x0 0x500>; 171 clocks = <&cpufreq_hw 1>; 172 enable-method = "psci"; 173 capacity-dmips-mhz = <1024>; 174 dynamic-power-coefficient = <590>; 175 next-level-cache = <&L2_500>; 176 power-domains = <&CPU_PD5>; 177 power-domain-names = "psci"; 178 qcom,freq-domain = <&cpufreq_hw 1>; 179 operating-points-v2 = <&cpu4_opp_table>; 180 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 181 #cooling-cells = <2>; 182 L2_500: l2-cache { 183 compatible = "cache"; 184 cache-level = <2>; 185 cache-unified; 186 next-level-cache = <&L3_0>; 187 }; 188 }; 189 190 CPU6: cpu@600 { 191 device_type = "cpu"; 192 compatible = "arm,cortex-x1c"; 193 reg = <0x0 0x600>; 194 clocks = <&cpufreq_hw 1>; 195 enable-method = "psci"; 196 capacity-dmips-mhz = <1024>; 197 dynamic-power-coefficient = <590>; 198 next-level-cache = <&L2_600>; 199 power-domains = <&CPU_PD6>; 200 power-domain-names = "psci"; 201 qcom,freq-domain = <&cpufreq_hw 1>; 202 operating-points-v2 = <&cpu4_opp_table>; 203 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 204 #cooling-cells = <2>; 205 L2_600: l2-cache { 206 compatible = "cache"; 207 cache-level = <2>; 208 cache-unified; 209 next-level-cache = <&L3_0>; 210 }; 211 }; 212 213 CPU7: cpu@700 { 214 device_type = "cpu"; 215 compatible = "arm,cortex-x1c"; 216 reg = <0x0 0x700>; 217 clocks = <&cpufreq_hw 1>; 218 enable-method = "psci"; 219 capacity-dmips-mhz = <1024>; 220 dynamic-power-coefficient = <590>; 221 next-level-cache = <&L2_700>; 222 power-domains = <&CPU_PD7>; 223 power-domain-names = "psci"; 224 qcom,freq-domain = <&cpufreq_hw 1>; 225 operating-points-v2 = <&cpu4_opp_table>; 226 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 227 #cooling-cells = <2>; 228 L2_700: l2-cache { 229 compatible = "cache"; 230 cache-level = <2>; 231 cache-unified; 232 next-level-cache = <&L3_0>; 233 }; 234 }; 235 236 cpu-map { 237 cluster0 { 238 core0 { 239 cpu = <&CPU0>; 240 }; 241 242 core1 { 243 cpu = <&CPU1>; 244 }; 245 246 core2 { 247 cpu = <&CPU2>; 248 }; 249 250 core3 { 251 cpu = <&CPU3>; 252 }; 253 254 core4 { 255 cpu = <&CPU4>; 256 }; 257 258 core5 { 259 cpu = <&CPU5>; 260 }; 261 262 core6 { 263 cpu = <&CPU6>; 264 }; 265 266 core7 { 267 cpu = <&CPU7>; 268 }; 269 }; 270 }; 271 272 idle-states { 273 entry-method = "psci"; 274 275 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 276 compatible = "arm,idle-state"; 277 idle-state-name = "little-rail-power-collapse"; 278 arm,psci-suspend-param = <0x40000004>; 279 entry-latency-us = <355>; 280 exit-latency-us = <909>; 281 min-residency-us = <3934>; 282 local-timer-stop; 283 }; 284 285 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 286 compatible = "arm,idle-state"; 287 idle-state-name = "big-rail-power-collapse"; 288 arm,psci-suspend-param = <0x40000004>; 289 entry-latency-us = <241>; 290 exit-latency-us = <1461>; 291 min-residency-us = <4488>; 292 local-timer-stop; 293 }; 294 }; 295 296 domain-idle-states { 297 CLUSTER_SLEEP_0: cluster-sleep-0 { 298 compatible = "domain-idle-state"; 299 arm,psci-suspend-param = <0x4100c344>; 300 entry-latency-us = <3263>; 301 exit-latency-us = <6562>; 302 min-residency-us = <9987>; 303 }; 304 }; 305 }; 306 307 firmware { 308 scm: scm { 309 compatible = "qcom,scm-sc8280xp", "qcom,scm"; 310 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 311 qcom,dload-mode = <&tcsr 0x13000>; 312 }; 313 }; 314 315 aggre1_noc: interconnect-aggre1-noc { 316 compatible = "qcom,sc8280xp-aggre1-noc"; 317 #interconnect-cells = <2>; 318 qcom,bcm-voters = <&apps_bcm_voter>; 319 }; 320 321 aggre2_noc: interconnect-aggre2-noc { 322 compatible = "qcom,sc8280xp-aggre2-noc"; 323 #interconnect-cells = <2>; 324 qcom,bcm-voters = <&apps_bcm_voter>; 325 }; 326 327 clk_virt: interconnect-clk-virt { 328 compatible = "qcom,sc8280xp-clk-virt"; 329 #interconnect-cells = <2>; 330 qcom,bcm-voters = <&apps_bcm_voter>; 331 }; 332 333 config_noc: interconnect-config-noc { 334 compatible = "qcom,sc8280xp-config-noc"; 335 #interconnect-cells = <2>; 336 qcom,bcm-voters = <&apps_bcm_voter>; 337 }; 338 339 dc_noc: interconnect-dc-noc { 340 compatible = "qcom,sc8280xp-dc-noc"; 341 #interconnect-cells = <2>; 342 qcom,bcm-voters = <&apps_bcm_voter>; 343 }; 344 345 gem_noc: interconnect-gem-noc { 346 compatible = "qcom,sc8280xp-gem-noc"; 347 #interconnect-cells = <2>; 348 qcom,bcm-voters = <&apps_bcm_voter>; 349 }; 350 351 lpass_noc: interconnect-lpass-ag-noc { 352 compatible = "qcom,sc8280xp-lpass-ag-noc"; 353 #interconnect-cells = <2>; 354 qcom,bcm-voters = <&apps_bcm_voter>; 355 }; 356 357 mc_virt: interconnect-mc-virt { 358 compatible = "qcom,sc8280xp-mc-virt"; 359 #interconnect-cells = <2>; 360 qcom,bcm-voters = <&apps_bcm_voter>; 361 }; 362 363 mmss_noc: interconnect-mmss-noc { 364 compatible = "qcom,sc8280xp-mmss-noc"; 365 #interconnect-cells = <2>; 366 qcom,bcm-voters = <&apps_bcm_voter>; 367 }; 368 369 nspa_noc: interconnect-nspa-noc { 370 compatible = "qcom,sc8280xp-nspa-noc"; 371 #interconnect-cells = <2>; 372 qcom,bcm-voters = <&apps_bcm_voter>; 373 }; 374 375 nspb_noc: interconnect-nspb-noc { 376 compatible = "qcom,sc8280xp-nspb-noc"; 377 #interconnect-cells = <2>; 378 qcom,bcm-voters = <&apps_bcm_voter>; 379 }; 380 381 system_noc: interconnect-system-noc { 382 compatible = "qcom,sc8280xp-system-noc"; 383 #interconnect-cells = <2>; 384 qcom,bcm-voters = <&apps_bcm_voter>; 385 }; 386 387 memory@80000000 { 388 device_type = "memory"; 389 /* We expect the bootloader to fill in the size */ 390 reg = <0x0 0x80000000 0x0 0x0>; 391 }; 392 393 cpu0_opp_table: opp-table-cpu0 { 394 compatible = "operating-points-v2"; 395 opp-shared; 396 397 opp-300000000 { 398 opp-hz = /bits/ 64 <300000000>; 399 opp-peak-kBps = <(300000 * 32)>; 400 }; 401 opp-403200000 { 402 opp-hz = /bits/ 64 <403200000>; 403 opp-peak-kBps = <(384000 * 32)>; 404 }; 405 opp-499200000 { 406 opp-hz = /bits/ 64 <499200000>; 407 opp-peak-kBps = <(480000 * 32)>; 408 }; 409 opp-595200000 { 410 opp-hz = /bits/ 64 <595200000>; 411 opp-peak-kBps = <(576000 * 32)>; 412 }; 413 opp-691200000 { 414 opp-hz = /bits/ 64 <691200000>; 415 opp-peak-kBps = <(672000 * 32)>; 416 }; 417 opp-806400000 { 418 opp-hz = /bits/ 64 <806400000>; 419 opp-peak-kBps = <(768000 * 32)>; 420 }; 421 opp-902400000 { 422 opp-hz = /bits/ 64 <902400000>; 423 opp-peak-kBps = <(864000 * 32)>; 424 }; 425 opp-1017600000 { 426 opp-hz = /bits/ 64 <1017600000>; 427 opp-peak-kBps = <(960000 * 32)>; 428 }; 429 opp-1113600000 { 430 opp-hz = /bits/ 64 <1113600000>; 431 opp-peak-kBps = <(1075200 * 32)>; 432 }; 433 opp-1209600000 { 434 opp-hz = /bits/ 64 <1209600000>; 435 opp-peak-kBps = <(1171200 * 32)>; 436 }; 437 opp-1324800000 { 438 opp-hz = /bits/ 64 <1324800000>; 439 opp-peak-kBps = <(1267200 * 32)>; 440 }; 441 opp-1440000000 { 442 opp-hz = /bits/ 64 <1440000000>; 443 opp-peak-kBps = <(1363200 * 32)>; 444 }; 445 opp-1555200000 { 446 opp-hz = /bits/ 64 <1555200000>; 447 opp-peak-kBps = <(1536000 * 32)>; 448 }; 449 opp-1670400000 { 450 opp-hz = /bits/ 64 <1670400000>; 451 opp-peak-kBps = <(1612800 * 32)>; 452 }; 453 opp-1785600000 { 454 opp-hz = /bits/ 64 <1785600000>; 455 opp-peak-kBps = <(1689600 * 32)>; 456 }; 457 opp-1881600000 { 458 opp-hz = /bits/ 64 <1881600000>; 459 opp-peak-kBps = <(1689600 * 32)>; 460 }; 461 opp-1996800000 { 462 opp-hz = /bits/ 64 <1996800000>; 463 opp-peak-kBps = <(1689600 * 32)>; 464 }; 465 opp-2112000000 { 466 opp-hz = /bits/ 64 <2112000000>; 467 opp-peak-kBps = <(1689600 * 32)>; 468 }; 469 opp-2227200000 { 470 opp-hz = /bits/ 64 <2227200000>; 471 opp-peak-kBps = <(1689600 * 32)>; 472 }; 473 opp-2342400000 { 474 opp-hz = /bits/ 64 <2342400000>; 475 opp-peak-kBps = <(1689600 * 32)>; 476 }; 477 opp-2438400000 { 478 opp-hz = /bits/ 64 <2438400000>; 479 opp-peak-kBps = <(1689600 * 32)>; 480 }; 481 }; 482 483 cpu4_opp_table: opp-table-cpu4 { 484 compatible = "operating-points-v2"; 485 opp-shared; 486 487 opp-825600000 { 488 opp-hz = /bits/ 64 <825600000>; 489 opp-peak-kBps = <(768000 * 32)>; 490 }; 491 opp-940800000 { 492 opp-hz = /bits/ 64 <940800000>; 493 opp-peak-kBps = <(864000 * 32)>; 494 }; 495 opp-1056000000 { 496 opp-hz = /bits/ 64 <1056000000>; 497 opp-peak-kBps = <(960000 * 32)>; 498 }; 499 opp-1171200000 { 500 opp-hz = /bits/ 64 <1171200000>; 501 opp-peak-kBps = <(1171200 * 32)>; 502 }; 503 opp-1286400000 { 504 opp-hz = /bits/ 64 <1286400000>; 505 opp-peak-kBps = <(1267200 * 32)>; 506 }; 507 opp-1401600000 { 508 opp-hz = /bits/ 64 <1401600000>; 509 opp-peak-kBps = <(1363200 * 32)>; 510 }; 511 opp-1516800000 { 512 opp-hz = /bits/ 64 <1516800000>; 513 opp-peak-kBps = <(1459200 * 32)>; 514 }; 515 opp-1632000000 { 516 opp-hz = /bits/ 64 <1632000000>; 517 opp-peak-kBps = <(1612800 * 32)>; 518 }; 519 opp-1747200000 { 520 opp-hz = /bits/ 64 <1747200000>; 521 opp-peak-kBps = <(1689600 * 32)>; 522 }; 523 opp-1862400000 { 524 opp-hz = /bits/ 64 <1862400000>; 525 opp-peak-kBps = <(1689600 * 32)>; 526 }; 527 opp-1977600000 { 528 opp-hz = /bits/ 64 <1977600000>; 529 opp-peak-kBps = <(1689600 * 32)>; 530 }; 531 opp-2073600000 { 532 opp-hz = /bits/ 64 <2073600000>; 533 opp-peak-kBps = <(1689600 * 32)>; 534 }; 535 opp-2169600000 { 536 opp-hz = /bits/ 64 <2169600000>; 537 opp-peak-kBps = <(1689600 * 32)>; 538 }; 539 opp-2284800000 { 540 opp-hz = /bits/ 64 <2284800000>; 541 opp-peak-kBps = <(1689600 * 32)>; 542 }; 543 opp-2400000000 { 544 opp-hz = /bits/ 64 <2400000000>; 545 opp-peak-kBps = <(1689600 * 32)>; 546 }; 547 opp-2496000000 { 548 opp-hz = /bits/ 64 <2496000000>; 549 opp-peak-kBps = <(1689600 * 32)>; 550 }; 551 opp-2592000000 { 552 opp-hz = /bits/ 64 <2592000000>; 553 opp-peak-kBps = <(1689600 * 32)>; 554 }; 555 opp-2688000000 { 556 opp-hz = /bits/ 64 <2688000000>; 557 opp-peak-kBps = <(1689600 * 32)>; 558 }; 559 opp-2803200000 { 560 opp-hz = /bits/ 64 <2803200000>; 561 opp-peak-kBps = <(1689600 * 32)>; 562 }; 563 opp-2899200000 { 564 opp-hz = /bits/ 64 <2899200000>; 565 opp-peak-kBps = <(1689600 * 32)>; 566 }; 567 opp-2995200000 { 568 opp-hz = /bits/ 64 <2995200000>; 569 opp-peak-kBps = <(1689600 * 32)>; 570 }; 571 }; 572 573 qup_opp_table_100mhz: opp-table-qup100mhz { 574 compatible = "operating-points-v2"; 575 576 opp-75000000 { 577 opp-hz = /bits/ 64 <75000000>; 578 required-opps = <&rpmhpd_opp_low_svs>; 579 }; 580 581 opp-100000000 { 582 opp-hz = /bits/ 64 <100000000>; 583 required-opps = <&rpmhpd_opp_svs>; 584 }; 585 }; 586 587 pmu { 588 compatible = "arm,armv8-pmuv3"; 589 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 590 }; 591 592 psci { 593 compatible = "arm,psci-1.0"; 594 method = "smc"; 595 596 CPU_PD0: power-domain-cpu0 { 597 #power-domain-cells = <0>; 598 power-domains = <&CLUSTER_PD>; 599 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 600 }; 601 602 CPU_PD1: power-domain-cpu1 { 603 #power-domain-cells = <0>; 604 power-domains = <&CLUSTER_PD>; 605 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 606 }; 607 608 CPU_PD2: power-domain-cpu2 { 609 #power-domain-cells = <0>; 610 power-domains = <&CLUSTER_PD>; 611 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 612 }; 613 614 CPU_PD3: power-domain-cpu3 { 615 #power-domain-cells = <0>; 616 power-domains = <&CLUSTER_PD>; 617 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 618 }; 619 620 CPU_PD4: power-domain-cpu4 { 621 #power-domain-cells = <0>; 622 power-domains = <&CLUSTER_PD>; 623 domain-idle-states = <&BIG_CPU_SLEEP_0>; 624 }; 625 626 CPU_PD5: power-domain-cpu5 { 627 #power-domain-cells = <0>; 628 power-domains = <&CLUSTER_PD>; 629 domain-idle-states = <&BIG_CPU_SLEEP_0>; 630 }; 631 632 CPU_PD6: power-domain-cpu6 { 633 #power-domain-cells = <0>; 634 power-domains = <&CLUSTER_PD>; 635 domain-idle-states = <&BIG_CPU_SLEEP_0>; 636 }; 637 638 CPU_PD7: power-domain-cpu7 { 639 #power-domain-cells = <0>; 640 power-domains = <&CLUSTER_PD>; 641 domain-idle-states = <&BIG_CPU_SLEEP_0>; 642 }; 643 644 CLUSTER_PD: power-domain-cpu-cluster0 { 645 #power-domain-cells = <0>; 646 domain-idle-states = <&CLUSTER_SLEEP_0>; 647 }; 648 }; 649 650 reserved-memory { 651 #address-cells = <2>; 652 #size-cells = <2>; 653 ranges; 654 655 reserved-region@80000000 { 656 reg = <0 0x80000000 0 0x860000>; 657 no-map; 658 }; 659 660 cmd_db: cmd-db-region@80860000 { 661 compatible = "qcom,cmd-db"; 662 reg = <0 0x80860000 0 0x20000>; 663 no-map; 664 }; 665 666 reserved-region@80880000 { 667 reg = <0 0x80880000 0 0x80000>; 668 no-map; 669 }; 670 671 smem_mem: smem-region@80900000 { 672 compatible = "qcom,smem"; 673 reg = <0 0x80900000 0 0x200000>; 674 no-map; 675 hwlocks = <&tcsr_mutex 3>; 676 }; 677 678 reserved-region@80b00000 { 679 reg = <0 0x80b00000 0 0x100000>; 680 no-map; 681 }; 682 683 reserved-region@83b00000 { 684 reg = <0 0x83b00000 0 0x1700000>; 685 no-map; 686 }; 687 688 reserved-region@85b00000 { 689 reg = <0 0x85b00000 0 0xc00000>; 690 no-map; 691 }; 692 693 pil_adsp_mem: adsp-region@86c00000 { 694 reg = <0 0x86c00000 0 0x2000000>; 695 no-map; 696 }; 697 698 pil_nsp0_mem: cdsp0-region@8a100000 { 699 reg = <0 0x8a100000 0 0x1e00000>; 700 no-map; 701 }; 702 703 pil_nsp1_mem: cdsp1-region@8c600000 { 704 reg = <0 0x8c600000 0 0x1e00000>; 705 no-map; 706 }; 707 708 reserved-region@aeb00000 { 709 reg = <0 0xaeb00000 0 0x16600000>; 710 no-map; 711 }; 712 }; 713 714 smp2p-adsp { 715 compatible = "qcom,smp2p"; 716 qcom,smem = <443>, <429>; 717 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 718 IPCC_MPROC_SIGNAL_SMP2P 719 IRQ_TYPE_EDGE_RISING>; 720 mboxes = <&ipcc IPCC_CLIENT_LPASS 721 IPCC_MPROC_SIGNAL_SMP2P>; 722 723 qcom,local-pid = <0>; 724 qcom,remote-pid = <2>; 725 726 smp2p_adsp_out: master-kernel { 727 qcom,entry-name = "master-kernel"; 728 #qcom,smem-state-cells = <1>; 729 }; 730 731 smp2p_adsp_in: slave-kernel { 732 qcom,entry-name = "slave-kernel"; 733 interrupt-controller; 734 #interrupt-cells = <2>; 735 }; 736 }; 737 738 smp2p-nsp0 { 739 compatible = "qcom,smp2p"; 740 qcom,smem = <94>, <432>; 741 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 742 IPCC_MPROC_SIGNAL_SMP2P 743 IRQ_TYPE_EDGE_RISING>; 744 mboxes = <&ipcc IPCC_CLIENT_CDSP 745 IPCC_MPROC_SIGNAL_SMP2P>; 746 747 qcom,local-pid = <0>; 748 qcom,remote-pid = <5>; 749 750 smp2p_nsp0_out: master-kernel { 751 qcom,entry-name = "master-kernel"; 752 #qcom,smem-state-cells = <1>; 753 }; 754 755 smp2p_nsp0_in: slave-kernel { 756 qcom,entry-name = "slave-kernel"; 757 interrupt-controller; 758 #interrupt-cells = <2>; 759 }; 760 }; 761 762 smp2p-nsp1 { 763 compatible = "qcom,smp2p"; 764 qcom,smem = <617>, <616>; 765 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 766 IPCC_MPROC_SIGNAL_SMP2P 767 IRQ_TYPE_EDGE_RISING>; 768 mboxes = <&ipcc IPCC_CLIENT_NSP1 769 IPCC_MPROC_SIGNAL_SMP2P>; 770 771 qcom,local-pid = <0>; 772 qcom,remote-pid = <12>; 773 774 smp2p_nsp1_out: master-kernel { 775 qcom,entry-name = "master-kernel"; 776 #qcom,smem-state-cells = <1>; 777 }; 778 779 smp2p_nsp1_in: slave-kernel { 780 qcom,entry-name = "slave-kernel"; 781 interrupt-controller; 782 #interrupt-cells = <2>; 783 }; 784 }; 785 786 soc: soc@0 { 787 compatible = "simple-bus"; 788 #address-cells = <2>; 789 #size-cells = <2>; 790 ranges = <0 0 0 0 0x10 0>; 791 dma-ranges = <0 0 0 0 0x10 0>; 792 793 ethernet0: ethernet@20000 { 794 compatible = "qcom,sc8280xp-ethqos"; 795 reg = <0x0 0x00020000 0x0 0x10000>, 796 <0x0 0x00036000 0x0 0x100>; 797 reg-names = "stmmaceth", "rgmii"; 798 799 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 800 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 801 <&gcc GCC_EMAC0_PTP_CLK>, 802 <&gcc GCC_EMAC0_RGMII_CLK>; 803 clock-names = "stmmaceth", 804 "pclk", 805 "ptp_ref", 806 "rgmii"; 807 808 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 809 <GIC_SPI 936 IRQ_TYPE_LEVEL_HIGH>; 810 interrupt-names = "macirq", "eth_lpi"; 811 812 iommus = <&apps_smmu 0x4c0 0xf>; 813 power-domains = <&gcc EMAC_0_GDSC>; 814 815 snps,tso; 816 snps,pbl = <32>; 817 rx-fifo-depth = <4096>; 818 tx-fifo-depth = <4096>; 819 820 status = "disabled"; 821 }; 822 823 gcc: clock-controller@100000 { 824 compatible = "qcom,gcc-sc8280xp"; 825 reg = <0x0 0x00100000 0x0 0x1f0000>; 826 #clock-cells = <1>; 827 #reset-cells = <1>; 828 #power-domain-cells = <1>; 829 clocks = <&rpmhcc RPMH_CXO_CLK>, 830 <&sleep_clk>, 831 <0>, 832 <0>, 833 <0>, 834 <0>, 835 <0>, 836 <0>, 837 <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 838 <0>, 839 <0>, 840 <0>, 841 <0>, 842 <0>, 843 <0>, 844 <0>, 845 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 846 <0>, 847 <0>, 848 <0>, 849 <0>, 850 <0>, 851 <0>, 852 <0>, 853 <0>, 854 <0>, 855 <&pcie2a_phy>, 856 <&pcie2b_phy>, 857 <&pcie3a_phy>, 858 <&pcie3b_phy>, 859 <&pcie4_phy>, 860 <0>, 861 <0>; 862 power-domains = <&rpmhpd SC8280XP_CX>; 863 }; 864 865 ipcc: mailbox@408000 { 866 compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc"; 867 reg = <0 0x00408000 0 0x1000>; 868 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 869 interrupt-controller; 870 #interrupt-cells = <3>; 871 #mbox-cells = <2>; 872 }; 873 874 qfprom: efuse@784000 { 875 compatible = "qcom,sc8280xp-qfprom", "qcom,qfprom"; 876 reg = <0 0x00784000 0 0x3000>; 877 #address-cells = <1>; 878 #size-cells = <1>; 879 880 gpu_speed_bin: gpu-speed-bin@18b { 881 reg = <0x18b 0x1>; 882 bits = <5 3>; 883 }; 884 }; 885 886 qup2: geniqup@8c0000 { 887 compatible = "qcom,geni-se-qup"; 888 reg = <0 0x008c0000 0 0x2000>; 889 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 890 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 891 clock-names = "m-ahb", "s-ahb"; 892 iommus = <&apps_smmu 0xa3 0>; 893 894 #address-cells = <2>; 895 #size-cells = <2>; 896 ranges; 897 898 status = "disabled"; 899 900 i2c16: i2c@880000 { 901 compatible = "qcom,geni-i2c"; 902 reg = <0 0x00880000 0 0x4000>; 903 #address-cells = <1>; 904 #size-cells = <0>; 905 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 906 clock-names = "se"; 907 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 908 power-domains = <&rpmhpd SC8280XP_CX>; 909 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 910 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 911 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 912 interconnect-names = "qup-core", "qup-config", "qup-memory"; 913 status = "disabled"; 914 }; 915 916 spi16: spi@880000 { 917 compatible = "qcom,geni-spi"; 918 reg = <0 0x00880000 0 0x4000>; 919 #address-cells = <1>; 920 #size-cells = <0>; 921 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 922 clock-names = "se"; 923 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 924 power-domains = <&rpmhpd SC8280XP_CX>; 925 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 926 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 927 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 928 interconnect-names = "qup-core", "qup-config", "qup-memory"; 929 status = "disabled"; 930 }; 931 932 i2c17: i2c@884000 { 933 compatible = "qcom,geni-i2c"; 934 reg = <0 0x00884000 0 0x4000>; 935 #address-cells = <1>; 936 #size-cells = <0>; 937 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 938 clock-names = "se"; 939 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 940 power-domains = <&rpmhpd SC8280XP_CX>; 941 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 942 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 943 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 944 interconnect-names = "qup-core", "qup-config", "qup-memory"; 945 status = "disabled"; 946 }; 947 948 spi17: spi@884000 { 949 compatible = "qcom,geni-spi"; 950 reg = <0 0x00884000 0 0x4000>; 951 #address-cells = <1>; 952 #size-cells = <0>; 953 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 954 clock-names = "se"; 955 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 956 power-domains = <&rpmhpd SC8280XP_CX>; 957 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 958 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 959 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 960 interconnect-names = "qup-core", "qup-config", "qup-memory"; 961 status = "disabled"; 962 }; 963 964 uart17: serial@884000 { 965 compatible = "qcom,geni-uart"; 966 reg = <0 0x00884000 0 0x4000>; 967 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 968 clock-names = "se"; 969 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 970 operating-points-v2 = <&qup_opp_table_100mhz>; 971 power-domains = <&rpmhpd SC8280XP_CX>; 972 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 973 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; 974 interconnect-names = "qup-core", "qup-config"; 975 status = "disabled"; 976 }; 977 978 i2c18: i2c@888000 { 979 compatible = "qcom,geni-i2c"; 980 reg = <0 0x00888000 0 0x4000>; 981 #address-cells = <1>; 982 #size-cells = <0>; 983 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 984 clock-names = "se"; 985 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 986 power-domains = <&rpmhpd SC8280XP_CX>; 987 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 988 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 989 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 990 interconnect-names = "qup-core", "qup-config", "qup-memory"; 991 status = "disabled"; 992 }; 993 994 spi18: spi@888000 { 995 compatible = "qcom,geni-spi"; 996 reg = <0 0x00888000 0 0x4000>; 997 #address-cells = <1>; 998 #size-cells = <0>; 999 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1000 clock-names = "se"; 1001 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1002 power-domains = <&rpmhpd SC8280XP_CX>; 1003 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1004 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1005 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1006 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1007 status = "disabled"; 1008 }; 1009 1010 i2c19: i2c@88c000 { 1011 compatible = "qcom,geni-i2c"; 1012 reg = <0 0x0088c000 0 0x4000>; 1013 #address-cells = <1>; 1014 #size-cells = <0>; 1015 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1016 clock-names = "se"; 1017 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1018 power-domains = <&rpmhpd SC8280XP_CX>; 1019 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1020 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1021 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1022 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1023 status = "disabled"; 1024 }; 1025 1026 spi19: spi@88c000 { 1027 compatible = "qcom,geni-spi"; 1028 reg = <0 0x0088c000 0 0x4000>; 1029 #address-cells = <1>; 1030 #size-cells = <0>; 1031 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1032 clock-names = "se"; 1033 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1034 power-domains = <&rpmhpd SC8280XP_CX>; 1035 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1036 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1037 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1038 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1039 status = "disabled"; 1040 }; 1041 1042 i2c20: i2c@890000 { 1043 compatible = "qcom,geni-i2c"; 1044 reg = <0 0x00890000 0 0x4000>; 1045 #address-cells = <1>; 1046 #size-cells = <0>; 1047 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1048 clock-names = "se"; 1049 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1050 power-domains = <&rpmhpd SC8280XP_CX>; 1051 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1052 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1053 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1054 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1055 status = "disabled"; 1056 }; 1057 1058 spi20: spi@890000 { 1059 compatible = "qcom,geni-spi"; 1060 reg = <0 0x00890000 0 0x4000>; 1061 #address-cells = <1>; 1062 #size-cells = <0>; 1063 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1064 clock-names = "se"; 1065 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1066 power-domains = <&rpmhpd SC8280XP_CX>; 1067 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1068 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1069 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1070 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1071 status = "disabled"; 1072 }; 1073 1074 i2c21: i2c@894000 { 1075 compatible = "qcom,geni-i2c"; 1076 reg = <0 0x00894000 0 0x4000>; 1077 clock-names = "se"; 1078 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1079 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 power-domains = <&rpmhpd SC8280XP_CX>; 1083 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1084 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1085 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1086 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1087 status = "disabled"; 1088 }; 1089 1090 spi21: spi@894000 { 1091 compatible = "qcom,geni-spi"; 1092 reg = <0 0x00894000 0 0x4000>; 1093 #address-cells = <1>; 1094 #size-cells = <0>; 1095 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1096 clock-names = "se"; 1097 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1098 power-domains = <&rpmhpd SC8280XP_CX>; 1099 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1100 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1101 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1102 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1103 status = "disabled"; 1104 }; 1105 1106 i2c22: i2c@898000 { 1107 compatible = "qcom,geni-i2c"; 1108 reg = <0 0x00898000 0 0x4000>; 1109 #address-cells = <1>; 1110 #size-cells = <0>; 1111 clock-names = "se"; 1112 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1113 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1114 power-domains = <&rpmhpd SC8280XP_CX>; 1115 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1116 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1117 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1118 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1119 status = "disabled"; 1120 }; 1121 1122 spi22: spi@898000 { 1123 compatible = "qcom,geni-spi"; 1124 reg = <0 0x00898000 0 0x4000>; 1125 #address-cells = <1>; 1126 #size-cells = <0>; 1127 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1128 clock-names = "se"; 1129 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1130 power-domains = <&rpmhpd SC8280XP_CX>; 1131 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1132 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1133 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1134 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1135 status = "disabled"; 1136 }; 1137 1138 i2c23: i2c@89c000 { 1139 compatible = "qcom,geni-i2c"; 1140 reg = <0 0x0089c000 0 0x4000>; 1141 #address-cells = <1>; 1142 #size-cells = <0>; 1143 clock-names = "se"; 1144 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1145 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1146 power-domains = <&rpmhpd SC8280XP_CX>; 1147 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1148 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1149 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1150 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1151 status = "disabled"; 1152 }; 1153 1154 spi23: spi@89c000 { 1155 compatible = "qcom,geni-spi"; 1156 reg = <0 0x0089c000 0 0x4000>; 1157 #address-cells = <1>; 1158 #size-cells = <0>; 1159 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1160 clock-names = "se"; 1161 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1162 power-domains = <&rpmhpd SC8280XP_CX>; 1163 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1164 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1165 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1166 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1167 status = "disabled"; 1168 }; 1169 }; 1170 1171 qup0: geniqup@9c0000 { 1172 compatible = "qcom,geni-se-qup"; 1173 reg = <0 0x009c0000 0 0x6000>; 1174 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1175 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1176 clock-names = "m-ahb", "s-ahb"; 1177 iommus = <&apps_smmu 0x563 0>; 1178 1179 #address-cells = <2>; 1180 #size-cells = <2>; 1181 ranges; 1182 1183 status = "disabled"; 1184 1185 i2c0: i2c@980000 { 1186 compatible = "qcom,geni-i2c"; 1187 reg = <0 0x00980000 0 0x4000>; 1188 #address-cells = <1>; 1189 #size-cells = <0>; 1190 clock-names = "se"; 1191 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1192 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1193 power-domains = <&rpmhpd SC8280XP_CX>; 1194 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1195 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1196 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1197 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1198 status = "disabled"; 1199 }; 1200 1201 spi0: spi@980000 { 1202 compatible = "qcom,geni-spi"; 1203 reg = <0 0x00980000 0 0x4000>; 1204 #address-cells = <1>; 1205 #size-cells = <0>; 1206 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1207 clock-names = "se"; 1208 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1209 power-domains = <&rpmhpd SC8280XP_CX>; 1210 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1211 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1212 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1213 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1214 status = "disabled"; 1215 }; 1216 1217 i2c1: i2c@984000 { 1218 compatible = "qcom,geni-i2c"; 1219 reg = <0 0x00984000 0 0x4000>; 1220 #address-cells = <1>; 1221 #size-cells = <0>; 1222 clock-names = "se"; 1223 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1224 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1225 power-domains = <&rpmhpd SC8280XP_CX>; 1226 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1227 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1228 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1229 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1230 status = "disabled"; 1231 }; 1232 1233 spi1: spi@984000 { 1234 compatible = "qcom,geni-spi"; 1235 reg = <0 0x00984000 0 0x4000>; 1236 #address-cells = <1>; 1237 #size-cells = <0>; 1238 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1239 clock-names = "se"; 1240 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1241 power-domains = <&rpmhpd SC8280XP_CX>; 1242 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1243 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1244 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1245 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1246 status = "disabled"; 1247 }; 1248 1249 i2c2: i2c@988000 { 1250 compatible = "qcom,geni-i2c"; 1251 reg = <0 0x00988000 0 0x4000>; 1252 #address-cells = <1>; 1253 #size-cells = <0>; 1254 clock-names = "se"; 1255 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1256 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1257 power-domains = <&rpmhpd SC8280XP_CX>; 1258 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1259 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1260 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1261 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1262 status = "disabled"; 1263 }; 1264 1265 spi2: spi@988000 { 1266 compatible = "qcom,geni-spi"; 1267 reg = <0 0x00988000 0 0x4000>; 1268 #address-cells = <1>; 1269 #size-cells = <0>; 1270 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1271 clock-names = "se"; 1272 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1273 power-domains = <&rpmhpd SC8280XP_CX>; 1274 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1275 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1276 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1277 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1278 status = "disabled"; 1279 }; 1280 1281 uart2: serial@988000 { 1282 compatible = "qcom,geni-uart"; 1283 reg = <0 0x00988000 0 0x4000>; 1284 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1285 clock-names = "se"; 1286 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1287 operating-points-v2 = <&qup_opp_table_100mhz>; 1288 power-domains = <&rpmhpd SC8280XP_CX>; 1289 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1290 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1291 interconnect-names = "qup-core", "qup-config"; 1292 status = "disabled"; 1293 }; 1294 1295 i2c3: i2c@98c000 { 1296 compatible = "qcom,geni-i2c"; 1297 reg = <0 0x0098c000 0 0x4000>; 1298 #address-cells = <1>; 1299 #size-cells = <0>; 1300 clock-names = "se"; 1301 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1302 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1303 power-domains = <&rpmhpd SC8280XP_CX>; 1304 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1305 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1306 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1307 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1308 status = "disabled"; 1309 }; 1310 1311 spi3: spi@98c000 { 1312 compatible = "qcom,geni-spi"; 1313 reg = <0 0x0098c000 0 0x4000>; 1314 #address-cells = <1>; 1315 #size-cells = <0>; 1316 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1317 clock-names = "se"; 1318 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1319 power-domains = <&rpmhpd SC8280XP_CX>; 1320 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1321 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1322 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1323 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1324 status = "disabled"; 1325 }; 1326 1327 i2c4: i2c@990000 { 1328 compatible = "qcom,geni-i2c"; 1329 reg = <0 0x00990000 0 0x4000>; 1330 clock-names = "se"; 1331 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1332 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1333 #address-cells = <1>; 1334 #size-cells = <0>; 1335 power-domains = <&rpmhpd SC8280XP_CX>; 1336 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1337 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1338 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1339 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1340 status = "disabled"; 1341 }; 1342 1343 spi4: spi@990000 { 1344 compatible = "qcom,geni-spi"; 1345 reg = <0 0x00990000 0 0x4000>; 1346 #address-cells = <1>; 1347 #size-cells = <0>; 1348 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1349 clock-names = "se"; 1350 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1351 power-domains = <&rpmhpd SC8280XP_CX>; 1352 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1353 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1354 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1355 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1356 status = "disabled"; 1357 }; 1358 1359 i2c5: i2c@994000 { 1360 compatible = "qcom,geni-i2c"; 1361 reg = <0 0x00994000 0 0x4000>; 1362 #address-cells = <1>; 1363 #size-cells = <0>; 1364 clock-names = "se"; 1365 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1366 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1367 power-domains = <&rpmhpd SC8280XP_CX>; 1368 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1369 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1370 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1371 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1372 status = "disabled"; 1373 }; 1374 1375 spi5: spi@994000 { 1376 compatible = "qcom,geni-spi"; 1377 reg = <0 0x00994000 0 0x4000>; 1378 #address-cells = <1>; 1379 #size-cells = <0>; 1380 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1381 clock-names = "se"; 1382 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1383 power-domains = <&rpmhpd SC8280XP_CX>; 1384 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1385 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1386 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1387 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1388 status = "disabled"; 1389 }; 1390 1391 i2c6: i2c@998000 { 1392 compatible = "qcom,geni-i2c"; 1393 reg = <0 0x00998000 0 0x4000>; 1394 #address-cells = <1>; 1395 #size-cells = <0>; 1396 clock-names = "se"; 1397 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1398 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1399 power-domains = <&rpmhpd SC8280XP_CX>; 1400 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1401 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1402 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1403 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1404 status = "disabled"; 1405 }; 1406 1407 spi6: spi@998000 { 1408 compatible = "qcom,geni-spi"; 1409 reg = <0 0x00998000 0 0x4000>; 1410 #address-cells = <1>; 1411 #size-cells = <0>; 1412 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1413 clock-names = "se"; 1414 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1415 power-domains = <&rpmhpd SC8280XP_CX>; 1416 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1417 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1418 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1419 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1420 status = "disabled"; 1421 }; 1422 1423 i2c7: i2c@99c000 { 1424 compatible = "qcom,geni-i2c"; 1425 reg = <0 0x0099c000 0 0x4000>; 1426 #address-cells = <1>; 1427 #size-cells = <0>; 1428 clock-names = "se"; 1429 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1430 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1431 power-domains = <&rpmhpd SC8280XP_CX>; 1432 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1433 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1434 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1435 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1436 status = "disabled"; 1437 }; 1438 1439 spi7: spi@99c000 { 1440 compatible = "qcom,geni-spi"; 1441 reg = <0 0x0099c000 0 0x4000>; 1442 #address-cells = <1>; 1443 #size-cells = <0>; 1444 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1445 clock-names = "se"; 1446 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1447 power-domains = <&rpmhpd SC8280XP_CX>; 1448 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1449 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1450 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1451 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1452 status = "disabled"; 1453 }; 1454 }; 1455 1456 qup1: geniqup@ac0000 { 1457 compatible = "qcom,geni-se-qup"; 1458 reg = <0 0x00ac0000 0 0x6000>; 1459 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1460 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1461 clock-names = "m-ahb", "s-ahb"; 1462 iommus = <&apps_smmu 0x83 0>; 1463 1464 #address-cells = <2>; 1465 #size-cells = <2>; 1466 ranges; 1467 1468 status = "disabled"; 1469 1470 i2c8: i2c@a80000 { 1471 compatible = "qcom,geni-i2c"; 1472 reg = <0 0x00a80000 0 0x4000>; 1473 #address-cells = <1>; 1474 #size-cells = <0>; 1475 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1476 clock-names = "se"; 1477 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1478 power-domains = <&rpmhpd SC8280XP_CX>; 1479 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1480 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1481 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1482 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1483 status = "disabled"; 1484 }; 1485 1486 spi8: spi@a80000 { 1487 compatible = "qcom,geni-spi"; 1488 reg = <0 0x00a80000 0 0x4000>; 1489 #address-cells = <1>; 1490 #size-cells = <0>; 1491 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1492 clock-names = "se"; 1493 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1494 power-domains = <&rpmhpd SC8280XP_CX>; 1495 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1496 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1497 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1498 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1499 status = "disabled"; 1500 }; 1501 1502 i2c9: i2c@a84000 { 1503 compatible = "qcom,geni-i2c"; 1504 reg = <0 0x00a84000 0 0x4000>; 1505 #address-cells = <1>; 1506 #size-cells = <0>; 1507 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1508 clock-names = "se"; 1509 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1510 power-domains = <&rpmhpd SC8280XP_CX>; 1511 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1512 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1513 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1514 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1515 status = "disabled"; 1516 }; 1517 1518 spi9: spi@a84000 { 1519 compatible = "qcom,geni-spi"; 1520 reg = <0 0x00a84000 0 0x4000>; 1521 #address-cells = <1>; 1522 #size-cells = <0>; 1523 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1524 clock-names = "se"; 1525 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1526 power-domains = <&rpmhpd SC8280XP_CX>; 1527 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1528 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1529 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1530 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1531 status = "disabled"; 1532 }; 1533 1534 i2c10: i2c@a88000 { 1535 compatible = "qcom,geni-i2c"; 1536 reg = <0 0x00a88000 0 0x4000>; 1537 #address-cells = <1>; 1538 #size-cells = <0>; 1539 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1540 clock-names = "se"; 1541 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1542 power-domains = <&rpmhpd SC8280XP_CX>; 1543 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1544 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1545 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1546 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1547 status = "disabled"; 1548 }; 1549 1550 spi10: spi@a88000 { 1551 compatible = "qcom,geni-spi"; 1552 reg = <0 0x00a88000 0 0x4000>; 1553 #address-cells = <1>; 1554 #size-cells = <0>; 1555 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1556 clock-names = "se"; 1557 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1558 power-domains = <&rpmhpd SC8280XP_CX>; 1559 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1560 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1561 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1562 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1563 status = "disabled"; 1564 }; 1565 1566 i2c11: i2c@a8c000 { 1567 compatible = "qcom,geni-i2c"; 1568 reg = <0 0x00a8c000 0 0x4000>; 1569 #address-cells = <1>; 1570 #size-cells = <0>; 1571 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1572 clock-names = "se"; 1573 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1574 power-domains = <&rpmhpd SC8280XP_CX>; 1575 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1576 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1577 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1578 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1579 status = "disabled"; 1580 }; 1581 1582 spi11: spi@a8c000 { 1583 compatible = "qcom,geni-spi"; 1584 reg = <0 0x00a8c000 0 0x4000>; 1585 #address-cells = <1>; 1586 #size-cells = <0>; 1587 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1588 clock-names = "se"; 1589 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1590 power-domains = <&rpmhpd SC8280XP_CX>; 1591 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1592 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1593 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1594 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1595 status = "disabled"; 1596 }; 1597 1598 i2c12: i2c@a90000 { 1599 compatible = "qcom,geni-i2c"; 1600 reg = <0 0x00a90000 0 0x4000>; 1601 #address-cells = <1>; 1602 #size-cells = <0>; 1603 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1604 clock-names = "se"; 1605 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1606 power-domains = <&rpmhpd SC8280XP_CX>; 1607 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1608 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1609 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1610 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1611 status = "disabled"; 1612 }; 1613 1614 spi12: spi@a90000 { 1615 compatible = "qcom,geni-spi"; 1616 reg = <0 0x00a90000 0 0x4000>; 1617 #address-cells = <1>; 1618 #size-cells = <0>; 1619 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1620 clock-names = "se"; 1621 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1622 power-domains = <&rpmhpd SC8280XP_CX>; 1623 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1624 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1625 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1626 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1627 status = "disabled"; 1628 }; 1629 1630 i2c13: i2c@a94000 { 1631 compatible = "qcom,geni-i2c"; 1632 reg = <0 0x00a94000 0 0x4000>; 1633 #address-cells = <1>; 1634 #size-cells = <0>; 1635 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1636 clock-names = "se"; 1637 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1638 power-domains = <&rpmhpd SC8280XP_CX>; 1639 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1640 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1641 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1642 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1643 status = "disabled"; 1644 }; 1645 1646 spi13: spi@a94000 { 1647 compatible = "qcom,geni-spi"; 1648 reg = <0 0x00a94000 0 0x4000>; 1649 #address-cells = <1>; 1650 #size-cells = <0>; 1651 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1652 clock-names = "se"; 1653 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1654 power-domains = <&rpmhpd SC8280XP_CX>; 1655 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1656 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1657 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1658 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1659 status = "disabled"; 1660 }; 1661 1662 i2c14: i2c@a98000 { 1663 compatible = "qcom,geni-i2c"; 1664 reg = <0 0x00a98000 0 0x4000>; 1665 #address-cells = <1>; 1666 #size-cells = <0>; 1667 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1668 clock-names = "se"; 1669 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1670 power-domains = <&rpmhpd SC8280XP_CX>; 1671 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1672 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1673 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1674 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1675 status = "disabled"; 1676 }; 1677 1678 spi14: spi@a98000 { 1679 compatible = "qcom,geni-spi"; 1680 reg = <0 0x00a98000 0 0x4000>; 1681 #address-cells = <1>; 1682 #size-cells = <0>; 1683 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1684 clock-names = "se"; 1685 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1686 power-domains = <&rpmhpd SC8280XP_CX>; 1687 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1688 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1689 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1690 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1691 status = "disabled"; 1692 }; 1693 1694 i2c15: i2c@a9c000 { 1695 compatible = "qcom,geni-i2c"; 1696 reg = <0 0x00a9c000 0 0x4000>; 1697 #address-cells = <1>; 1698 #size-cells = <0>; 1699 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1700 clock-names = "se"; 1701 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 1702 power-domains = <&rpmhpd SC8280XP_CX>; 1703 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1704 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1705 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1706 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1707 status = "disabled"; 1708 }; 1709 1710 spi15: spi@a9c000 { 1711 compatible = "qcom,geni-spi"; 1712 reg = <0 0x00a9c000 0 0x4000>; 1713 #address-cells = <1>; 1714 #size-cells = <0>; 1715 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1716 clock-names = "se"; 1717 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 1718 power-domains = <&rpmhpd SC8280XP_CX>; 1719 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1720 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1721 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1722 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1723 status = "disabled"; 1724 }; 1725 }; 1726 1727 rng: rng@10d3000 { 1728 compatible = "qcom,prng-ee"; 1729 reg = <0 0x010d3000 0 0x1000>; 1730 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1731 clock-names = "core"; 1732 }; 1733 1734 pcie4: pcie@1c00000 { 1735 device_type = "pci"; 1736 compatible = "qcom,pcie-sc8280xp"; 1737 reg = <0x0 0x01c00000 0x0 0x3000>, 1738 <0x0 0x30000000 0x0 0xf1d>, 1739 <0x0 0x30000f20 0x0 0xa8>, 1740 <0x0 0x30001000 0x0 0x1000>, 1741 <0x0 0x30100000 0x0 0x100000>, 1742 <0x0 0x01c03000 0x0 0x1000>; 1743 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1744 #address-cells = <3>; 1745 #size-cells = <2>; 1746 ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>, 1747 <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>; 1748 bus-range = <0x00 0xff>; 1749 1750 dma-coherent; 1751 1752 linux,pci-domain = <6>; 1753 num-lanes = <1>; 1754 1755 msi-map = <0x0 &its 0xe0000 0x10000>; 1756 1757 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1758 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 1761 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1762 1763 #interrupt-cells = <1>; 1764 interrupt-map-mask = <0 0 0 0x7>; 1765 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1766 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1767 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1768 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1769 1770 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 1771 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 1772 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 1773 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 1774 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 1775 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1776 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1777 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>, 1778 <&gcc GCC_CNOC_PCIE4_QX_CLK>; 1779 clock-names = "aux", 1780 "cfg", 1781 "bus_master", 1782 "bus_slave", 1783 "slave_q2a", 1784 "ddrss_sf_tbu", 1785 "noc_aggr_4", 1786 "noc_aggr_south_sf", 1787 "cnoc_qx"; 1788 1789 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 1790 assigned-clock-rates = <19200000>; 1791 1792 interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>, 1793 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>; 1794 interconnect-names = "pcie-mem", "cpu-pcie"; 1795 1796 resets = <&gcc GCC_PCIE_4_BCR>; 1797 reset-names = "pci"; 1798 1799 power-domains = <&gcc PCIE_4_GDSC>; 1800 required-opps = <&rpmhpd_opp_nom>; 1801 1802 phys = <&pcie4_phy>; 1803 phy-names = "pciephy"; 1804 1805 status = "disabled"; 1806 1807 pcie4_port0: pcie@0 { 1808 device_type = "pci"; 1809 reg = <0x0 0x0 0x0 0x0 0x0>; 1810 bus-range = <0x01 0xff>; 1811 1812 #address-cells = <3>; 1813 #size-cells = <2>; 1814 ranges; 1815 }; 1816 }; 1817 1818 pcie4_phy: phy@1c06000 { 1819 compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy"; 1820 reg = <0x0 0x01c06000 0x0 0x2000>; 1821 1822 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 1823 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 1824 <&gcc GCC_PCIE_4_CLKREF_CLK>, 1825 <&gcc GCC_PCIE4_PHY_RCHNG_CLK>, 1826 <&gcc GCC_PCIE_4_PIPE_CLK>, 1827 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; 1828 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1829 "pipe", "pipediv2"; 1830 1831 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>; 1832 assigned-clock-rates = <100000000>; 1833 1834 power-domains = <&gcc PCIE_4_GDSC>; 1835 1836 resets = <&gcc GCC_PCIE_4_PHY_BCR>; 1837 reset-names = "phy"; 1838 1839 #clock-cells = <0>; 1840 clock-output-names = "pcie_4_pipe_clk"; 1841 1842 #phy-cells = <0>; 1843 1844 status = "disabled"; 1845 }; 1846 1847 pcie3b: pcie@1c08000 { 1848 device_type = "pci"; 1849 compatible = "qcom,pcie-sc8280xp"; 1850 reg = <0x0 0x01c08000 0x0 0x3000>, 1851 <0x0 0x32000000 0x0 0xf1d>, 1852 <0x0 0x32000f20 0x0 0xa8>, 1853 <0x0 0x32001000 0x0 0x1000>, 1854 <0x0 0x32100000 0x0 0x100000>, 1855 <0x0 0x01c0b000 0x0 0x1000>; 1856 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1857 #address-cells = <3>; 1858 #size-cells = <2>; 1859 ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>, 1860 <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>; 1861 bus-range = <0x00 0xff>; 1862 1863 dma-coherent; 1864 1865 linux,pci-domain = <5>; 1866 num-lanes = <2>; 1867 1868 msi-map = <0x0 &its 0xd0000 0x10000>; 1869 1870 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1871 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1872 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1873 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1874 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1875 1876 #interrupt-cells = <1>; 1877 interrupt-map-mask = <0 0 0 0x7>; 1878 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, 1879 <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 1880 <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>, 1881 <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1882 1883 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 1884 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 1885 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, 1886 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, 1887 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, 1888 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1889 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1890 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 1891 clock-names = "aux", 1892 "cfg", 1893 "bus_master", 1894 "bus_slave", 1895 "slave_q2a", 1896 "ddrss_sf_tbu", 1897 "noc_aggr_4", 1898 "noc_aggr_south_sf"; 1899 1900 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>; 1901 assigned-clock-rates = <19200000>; 1902 1903 interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>, 1904 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>; 1905 interconnect-names = "pcie-mem", "cpu-pcie"; 1906 1907 resets = <&gcc GCC_PCIE_3B_BCR>; 1908 reset-names = "pci"; 1909 1910 power-domains = <&gcc PCIE_3B_GDSC>; 1911 required-opps = <&rpmhpd_opp_nom>; 1912 1913 phys = <&pcie3b_phy>; 1914 phy-names = "pciephy"; 1915 1916 status = "disabled"; 1917 1918 pcie3b_port0: pcie@0 { 1919 device_type = "pci"; 1920 reg = <0x0 0x0 0x0 0x0 0x0>; 1921 bus-range = <0x01 0xff>; 1922 1923 #address-cells = <3>; 1924 #size-cells = <2>; 1925 ranges; 1926 }; 1927 }; 1928 1929 pcie3b_phy: phy@1c0e000 { 1930 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 1931 reg = <0x0 0x01c0e000 0x0 0x2000>; 1932 1933 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 1934 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 1935 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 1936 <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>, 1937 <&gcc GCC_PCIE_3B_PIPE_CLK>, 1938 <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>; 1939 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1940 "pipe", "pipediv2"; 1941 1942 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>; 1943 assigned-clock-rates = <100000000>; 1944 1945 power-domains = <&gcc PCIE_3B_GDSC>; 1946 1947 resets = <&gcc GCC_PCIE_3B_PHY_BCR>; 1948 reset-names = "phy"; 1949 1950 #clock-cells = <0>; 1951 clock-output-names = "pcie_3b_pipe_clk"; 1952 1953 #phy-cells = <0>; 1954 1955 status = "disabled"; 1956 }; 1957 1958 pcie3a: pcie@1c10000 { 1959 device_type = "pci"; 1960 compatible = "qcom,pcie-sc8280xp"; 1961 reg = <0x0 0x01c10000 0x0 0x3000>, 1962 <0x0 0x34000000 0x0 0xf1d>, 1963 <0x0 0x34000f20 0x0 0xa8>, 1964 <0x0 0x34001000 0x0 0x1000>, 1965 <0x0 0x34100000 0x0 0x100000>, 1966 <0x0 0x01c13000 0x0 0x1000>; 1967 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1968 #address-cells = <3>; 1969 #size-cells = <2>; 1970 ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>, 1971 <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>; 1972 bus-range = <0x00 0xff>; 1973 1974 dma-coherent; 1975 1976 linux,pci-domain = <4>; 1977 num-lanes = <4>; 1978 1979 msi-map = <0x0 &its 0xc0000 0x10000>; 1980 1981 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1982 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1983 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1984 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1985 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1986 1987 #interrupt-cells = <1>; 1988 interrupt-map-mask = <0 0 0 0x7>; 1989 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 1990 <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>, 1991 <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, 1992 <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>; 1993 1994 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 1995 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 1996 <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>, 1997 <&gcc GCC_PCIE_3A_SLV_AXI_CLK>, 1998 <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>, 1999 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2000 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2001 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2002 clock-names = "aux", 2003 "cfg", 2004 "bus_master", 2005 "bus_slave", 2006 "slave_q2a", 2007 "ddrss_sf_tbu", 2008 "noc_aggr_4", 2009 "noc_aggr_south_sf"; 2010 2011 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>; 2012 assigned-clock-rates = <19200000>; 2013 2014 interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>, 2015 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>; 2016 interconnect-names = "pcie-mem", "cpu-pcie"; 2017 2018 resets = <&gcc GCC_PCIE_3A_BCR>; 2019 reset-names = "pci"; 2020 2021 power-domains = <&gcc PCIE_3A_GDSC>; 2022 required-opps = <&rpmhpd_opp_nom>; 2023 2024 phys = <&pcie3a_phy>; 2025 phy-names = "pciephy"; 2026 2027 status = "disabled"; 2028 2029 pcie3a_port0: pcie@0 { 2030 device_type = "pci"; 2031 reg = <0x0 0x0 0x0 0x0 0x0>; 2032 bus-range = <0x01 0xff>; 2033 2034 #address-cells = <3>; 2035 #size-cells = <2>; 2036 ranges; 2037 }; 2038 }; 2039 2040 pcie3a_phy: phy@1c14000 { 2041 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 2042 reg = <0x0 0x01c14000 0x0 0x2000>, 2043 <0x0 0x01c16000 0x0 0x2000>; 2044 2045 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 2046 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 2047 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 2048 <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>, 2049 <&gcc GCC_PCIE_3A_PIPE_CLK>, 2050 <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>; 2051 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2052 "pipe", "pipediv2"; 2053 2054 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>; 2055 assigned-clock-rates = <100000000>; 2056 2057 power-domains = <&gcc PCIE_3A_GDSC>; 2058 2059 resets = <&gcc GCC_PCIE_3A_PHY_BCR>; 2060 reset-names = "phy"; 2061 2062 qcom,4ln-config-sel = <&tcsr 0xa044 1>; 2063 2064 #clock-cells = <0>; 2065 clock-output-names = "pcie_3a_pipe_clk"; 2066 2067 #phy-cells = <0>; 2068 2069 status = "disabled"; 2070 }; 2071 2072 pcie2b: pcie@1c18000 { 2073 device_type = "pci"; 2074 compatible = "qcom,pcie-sc8280xp"; 2075 reg = <0x0 0x01c18000 0x0 0x3000>, 2076 <0x0 0x38000000 0x0 0xf1d>, 2077 <0x0 0x38000f20 0x0 0xa8>, 2078 <0x0 0x38001000 0x0 0x1000>, 2079 <0x0 0x38100000 0x0 0x100000>, 2080 <0x0 0x01c1b000 0x0 0x1000>; 2081 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2082 #address-cells = <3>; 2083 #size-cells = <2>; 2084 ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>, 2085 <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>; 2086 bus-range = <0x00 0xff>; 2087 2088 dma-coherent; 2089 2090 linux,pci-domain = <3>; 2091 num-lanes = <2>; 2092 2093 msi-map = <0x0 &its 0xb0000 0x10000>; 2094 2095 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 2096 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2097 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2098 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 2099 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2100 2101 #interrupt-cells = <1>; 2102 interrupt-map-mask = <0 0 0 0x7>; 2103 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2104 <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 2105 <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 2106 <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; 2107 2108 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2109 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2110 <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>, 2111 <&gcc GCC_PCIE_2B_SLV_AXI_CLK>, 2112 <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>, 2113 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2114 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2115 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2116 clock-names = "aux", 2117 "cfg", 2118 "bus_master", 2119 "bus_slave", 2120 "slave_q2a", 2121 "ddrss_sf_tbu", 2122 "noc_aggr_4", 2123 "noc_aggr_south_sf"; 2124 2125 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>; 2126 assigned-clock-rates = <19200000>; 2127 2128 interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>, 2129 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>; 2130 interconnect-names = "pcie-mem", "cpu-pcie"; 2131 2132 resets = <&gcc GCC_PCIE_2B_BCR>; 2133 reset-names = "pci"; 2134 2135 power-domains = <&gcc PCIE_2B_GDSC>; 2136 required-opps = <&rpmhpd_opp_nom>; 2137 2138 phys = <&pcie2b_phy>; 2139 phy-names = "pciephy"; 2140 2141 status = "disabled"; 2142 2143 pcie2b_port0: pcie@0 { 2144 device_type = "pci"; 2145 reg = <0x0 0x0 0x0 0x0 0x0>; 2146 bus-range = <0x01 0xff>; 2147 2148 #address-cells = <3>; 2149 #size-cells = <2>; 2150 ranges; 2151 }; 2152 }; 2153 2154 pcie2b_phy: phy@1c1e000 { 2155 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 2156 reg = <0x0 0x01c1e000 0x0 0x2000>; 2157 2158 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2159 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2160 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2161 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>, 2162 <&gcc GCC_PCIE_2B_PIPE_CLK>, 2163 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>; 2164 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2165 "pipe", "pipediv2"; 2166 2167 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>; 2168 assigned-clock-rates = <100000000>; 2169 2170 power-domains = <&gcc PCIE_2B_GDSC>; 2171 2172 resets = <&gcc GCC_PCIE_2B_PHY_BCR>; 2173 reset-names = "phy"; 2174 2175 #clock-cells = <0>; 2176 clock-output-names = "pcie_2b_pipe_clk"; 2177 2178 #phy-cells = <0>; 2179 2180 status = "disabled"; 2181 }; 2182 2183 pcie2a: pcie@1c20000 { 2184 device_type = "pci"; 2185 compatible = "qcom,pcie-sc8280xp"; 2186 reg = <0x0 0x01c20000 0x0 0x3000>, 2187 <0x0 0x3c000000 0x0 0xf1d>, 2188 <0x0 0x3c000f20 0x0 0xa8>, 2189 <0x0 0x3c001000 0x0 0x1000>, 2190 <0x0 0x3c100000 0x0 0x100000>, 2191 <0x0 0x01c23000 0x0 0x1000>; 2192 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2193 #address-cells = <3>; 2194 #size-cells = <2>; 2195 ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>, 2196 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>; 2197 bus-range = <0x00 0xff>; 2198 2199 dma-coherent; 2200 2201 linux,pci-domain = <2>; 2202 num-lanes = <4>; 2203 2204 msi-map = <0x0 &its 0xa0000 0x10000>; 2205 2206 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 2207 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, 2208 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, 2209 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>; 2210 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2211 2212 #interrupt-cells = <1>; 2213 interrupt-map-mask = <0 0 0 0x7>; 2214 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 2215 <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 2216 <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 2217 <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; 2218 2219 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2220 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2221 <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>, 2222 <&gcc GCC_PCIE_2A_SLV_AXI_CLK>, 2223 <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>, 2224 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2225 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2226 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2227 clock-names = "aux", 2228 "cfg", 2229 "bus_master", 2230 "bus_slave", 2231 "slave_q2a", 2232 "ddrss_sf_tbu", 2233 "noc_aggr_4", 2234 "noc_aggr_south_sf"; 2235 2236 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>; 2237 assigned-clock-rates = <19200000>; 2238 2239 interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>, 2240 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>; 2241 interconnect-names = "pcie-mem", "cpu-pcie"; 2242 2243 resets = <&gcc GCC_PCIE_2A_BCR>; 2244 reset-names = "pci"; 2245 2246 power-domains = <&gcc PCIE_2A_GDSC>; 2247 required-opps = <&rpmhpd_opp_nom>; 2248 2249 phys = <&pcie2a_phy>; 2250 phy-names = "pciephy"; 2251 2252 status = "disabled"; 2253 2254 pcie2a_port0: pcie@0 { 2255 device_type = "pci"; 2256 reg = <0x0 0x0 0x0 0x0 0x0>; 2257 bus-range = <0x01 0xff>; 2258 2259 #address-cells = <3>; 2260 #size-cells = <2>; 2261 ranges; 2262 }; 2263 }; 2264 2265 pcie2a_phy: phy@1c24000 { 2266 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 2267 reg = <0x0 0x01c24000 0x0 0x2000>, 2268 <0x0 0x01c26000 0x0 0x2000>; 2269 2270 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2271 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2272 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2273 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>, 2274 <&gcc GCC_PCIE_2A_PIPE_CLK>, 2275 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>; 2276 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2277 "pipe", "pipediv2"; 2278 2279 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>; 2280 assigned-clock-rates = <100000000>; 2281 2282 power-domains = <&gcc PCIE_2A_GDSC>; 2283 2284 resets = <&gcc GCC_PCIE_2A_PHY_BCR>; 2285 reset-names = "phy"; 2286 2287 qcom,4ln-config-sel = <&tcsr 0xa044 0>; 2288 2289 #clock-cells = <0>; 2290 clock-output-names = "pcie_2a_pipe_clk"; 2291 2292 #phy-cells = <0>; 2293 2294 status = "disabled"; 2295 }; 2296 2297 ufs_mem_hc: ufs@1d84000 { 2298 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2299 "jedec,ufs-2.0"; 2300 reg = <0 0x01d84000 0 0x3000>; 2301 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2302 phys = <&ufs_mem_phy>; 2303 phy-names = "ufsphy"; 2304 lanes-per-direction = <2>; 2305 #reset-cells = <1>; 2306 resets = <&gcc GCC_UFS_PHY_BCR>; 2307 reset-names = "rst"; 2308 2309 power-domains = <&gcc UFS_PHY_GDSC>; 2310 required-opps = <&rpmhpd_opp_nom>; 2311 2312 iommus = <&apps_smmu 0xe0 0x0>; 2313 dma-coherent; 2314 2315 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2316 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2317 <&gcc GCC_UFS_PHY_AHB_CLK>, 2318 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2319 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2320 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2321 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2322 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2323 clock-names = "core_clk", 2324 "bus_aggr_clk", 2325 "iface_clk", 2326 "core_clk_unipro", 2327 "ref_clk", 2328 "tx_lane0_sync_clk", 2329 "rx_lane0_sync_clk", 2330 "rx_lane1_sync_clk"; 2331 freq-table-hz = <75000000 300000000>, 2332 <0 0>, 2333 <0 0>, 2334 <75000000 300000000>, 2335 <0 0>, 2336 <0 0>, 2337 <0 0>, 2338 <0 0>; 2339 status = "disabled"; 2340 }; 2341 2342 ufs_mem_phy: phy@1d87000 { 2343 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2344 reg = <0 0x01d87000 0 0x1000>; 2345 2346 clocks = <&rpmhcc RPMH_CXO_CLK>, 2347 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2348 <&gcc GCC_UFS_CARD_CLKREF_CLK>; 2349 clock-names = "ref", 2350 "ref_aux", 2351 "qref"; 2352 2353 power-domains = <&gcc UFS_PHY_GDSC>; 2354 2355 resets = <&ufs_mem_hc 0>; 2356 reset-names = "ufsphy"; 2357 2358 #phy-cells = <0>; 2359 2360 status = "disabled"; 2361 }; 2362 2363 ufs_card_hc: ufs@1da4000 { 2364 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2365 "jedec,ufs-2.0"; 2366 reg = <0 0x01da4000 0 0x3000>; 2367 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2368 phys = <&ufs_card_phy>; 2369 phy-names = "ufsphy"; 2370 lanes-per-direction = <2>; 2371 #reset-cells = <1>; 2372 resets = <&gcc GCC_UFS_CARD_BCR>; 2373 reset-names = "rst"; 2374 2375 power-domains = <&gcc UFS_CARD_GDSC>; 2376 2377 iommus = <&apps_smmu 0x4a0 0x0>; 2378 dma-coherent; 2379 2380 clocks = <&gcc GCC_UFS_CARD_AXI_CLK>, 2381 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, 2382 <&gcc GCC_UFS_CARD_AHB_CLK>, 2383 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>, 2384 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2385 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>, 2386 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>, 2387 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>; 2388 clock-names = "core_clk", 2389 "bus_aggr_clk", 2390 "iface_clk", 2391 "core_clk_unipro", 2392 "ref_clk", 2393 "tx_lane0_sync_clk", 2394 "rx_lane0_sync_clk", 2395 "rx_lane1_sync_clk"; 2396 freq-table-hz = <75000000 300000000>, 2397 <0 0>, 2398 <0 0>, 2399 <75000000 300000000>, 2400 <0 0>, 2401 <0 0>, 2402 <0 0>, 2403 <0 0>; 2404 status = "disabled"; 2405 }; 2406 2407 ufs_card_phy: phy@1da7000 { 2408 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2409 reg = <0 0x01da7000 0 0x1000>; 2410 2411 clocks = <&rpmhcc RPMH_CXO_CLK>, 2412 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>, 2413 <&gcc GCC_UFS_1_CARD_CLKREF_CLK>; 2414 clock-names = "ref", 2415 "ref_aux", 2416 "qref"; 2417 2418 power-domains = <&gcc UFS_CARD_GDSC>; 2419 2420 resets = <&ufs_card_hc 0>; 2421 reset-names = "ufsphy"; 2422 2423 #phy-cells = <0>; 2424 2425 status = "disabled"; 2426 }; 2427 2428 tcsr_mutex: hwlock@1f40000 { 2429 compatible = "qcom,tcsr-mutex"; 2430 reg = <0x0 0x01f40000 0x0 0x20000>; 2431 #hwlock-cells = <1>; 2432 }; 2433 2434 tcsr: syscon@1fc0000 { 2435 compatible = "qcom,sc8280xp-tcsr", "syscon"; 2436 reg = <0x0 0x01fc0000 0x0 0x30000>; 2437 }; 2438 2439 gpu: gpu@3d00000 { 2440 compatible = "qcom,adreno-690.0", "qcom,adreno"; 2441 2442 reg = <0 0x03d00000 0 0x40000>, 2443 <0 0x03d9e000 0 0x1000>, 2444 <0 0x03d61000 0 0x800>; 2445 reg-names = "kgsl_3d0_reg_memory", 2446 "cx_mem", 2447 "cx_dbgc"; 2448 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2449 iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>; 2450 operating-points-v2 = <&gpu_opp_table>; 2451 2452 qcom,gmu = <&gmu>; 2453 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2454 interconnect-names = "gfx-mem"; 2455 #cooling-cells = <2>; 2456 2457 status = "disabled"; 2458 2459 gpu_opp_table: opp-table { 2460 compatible = "operating-points-v2"; 2461 2462 opp-270000000 { 2463 opp-hz = /bits/ 64 <270000000>; 2464 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2465 opp-peak-kBps = <451000>; 2466 }; 2467 2468 opp-410000000 { 2469 opp-hz = /bits/ 64 <410000000>; 2470 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2471 opp-peak-kBps = <1555000>; 2472 }; 2473 2474 opp-500000000 { 2475 opp-hz = /bits/ 64 <500000000>; 2476 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2477 opp-peak-kBps = <1555000>; 2478 }; 2479 2480 opp-547000000 { 2481 opp-hz = /bits/ 64 <547000000>; 2482 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2483 opp-peak-kBps = <1555000>; 2484 }; 2485 2486 opp-606000000 { 2487 opp-hz = /bits/ 64 <606000000>; 2488 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2489 opp-peak-kBps = <2736000>; 2490 }; 2491 2492 opp-640000000 { 2493 opp-hz = /bits/ 64 <640000000>; 2494 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2495 opp-peak-kBps = <2736000>; 2496 }; 2497 2498 opp-655000000 { 2499 opp-hz = /bits/ 64 <655000000>; 2500 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2501 opp-peak-kBps = <2736000>; 2502 }; 2503 2504 opp-690000000 { 2505 opp-hz = /bits/ 64 <690000000>; 2506 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2507 opp-peak-kBps = <2736000>; 2508 }; 2509 }; 2510 }; 2511 2512 gmu: gmu@3d6a000 { 2513 compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu"; 2514 reg = <0 0x03d6a000 0 0x34000>, 2515 <0 0x03de0000 0 0x10000>, 2516 <0 0x0b290000 0 0x10000>; 2517 reg-names = "gmu", "rscc", "gmu_pdc"; 2518 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2519 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2520 interrupt-names = "hfi", "gmu"; 2521 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2522 <&gpucc GPU_CC_CXO_CLK>, 2523 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2524 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2525 <&gpucc GPU_CC_AHB_CLK>, 2526 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2527 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2528 clock-names = "gmu", 2529 "cxo", 2530 "axi", 2531 "memnoc", 2532 "ahb", 2533 "hub", 2534 "smmu_vote"; 2535 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2536 <&gpucc GPU_CC_GX_GDSC>; 2537 power-domain-names = "cx", 2538 "gx"; 2539 iommus = <&gpu_smmu 5 0xc00>; 2540 operating-points-v2 = <&gmu_opp_table>; 2541 2542 gmu_opp_table: opp-table { 2543 compatible = "operating-points-v2"; 2544 2545 opp-200000000 { 2546 opp-hz = /bits/ 64 <200000000>; 2547 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2548 }; 2549 2550 opp-500000000 { 2551 opp-hz = /bits/ 64 <500000000>; 2552 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2553 }; 2554 }; 2555 }; 2556 2557 gpucc: clock-controller@3d90000 { 2558 compatible = "qcom,sc8280xp-gpucc"; 2559 reg = <0 0x03d90000 0 0x9000>; 2560 clocks = <&rpmhcc RPMH_CXO_CLK>, 2561 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2562 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2563 clock-names = "bi_tcxo", 2564 "gcc_gpu_gpll0_clk_src", 2565 "gcc_gpu_gpll0_div_clk_src"; 2566 2567 power-domains = <&rpmhpd SC8280XP_GFX>; 2568 #clock-cells = <1>; 2569 #reset-cells = <1>; 2570 #power-domain-cells = <1>; 2571 }; 2572 2573 gpu_smmu: iommu@3da0000 { 2574 compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu", 2575 "qcom,smmu-500", "arm,mmu-500"; 2576 reg = <0 0x03da0000 0 0x20000>; 2577 #iommu-cells = <2>; 2578 #global-interrupts = <2>; 2579 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2580 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2581 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2582 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2583 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2584 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2585 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2586 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2587 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2588 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2589 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2590 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2591 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, 2592 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>; 2593 2594 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2595 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2596 <&gpucc GPU_CC_AHB_CLK>, 2597 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2598 <&gpucc GPU_CC_CX_GMU_CLK>, 2599 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2600 <&gpucc GPU_CC_HUB_AON_CLK>; 2601 clock-names = "gcc_gpu_memnoc_gfx_clk", 2602 "gcc_gpu_snoc_dvm_gfx_clk", 2603 "gpu_cc_ahb_clk", 2604 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2605 "gpu_cc_cx_gmu_clk", 2606 "gpu_cc_hub_cx_int_clk", 2607 "gpu_cc_hub_aon_clk"; 2608 2609 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2610 dma-coherent; 2611 }; 2612 2613 usb_0_hsphy: phy@88e5000 { 2614 compatible = "qcom,sc8280xp-usb-hs-phy", 2615 "qcom,usb-snps-hs-5nm-phy"; 2616 reg = <0 0x088e5000 0 0x400>; 2617 clocks = <&rpmhcc RPMH_CXO_CLK>; 2618 clock-names = "ref"; 2619 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2620 2621 #phy-cells = <0>; 2622 2623 status = "disabled"; 2624 }; 2625 2626 usb_2_hsphy0: phy@88e7000 { 2627 compatible = "qcom,sc8280xp-usb-hs-phy", 2628 "qcom,usb-snps-hs-5nm-phy"; 2629 reg = <0 0x088e7000 0 0x400>; 2630 clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>; 2631 clock-names = "ref"; 2632 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 2633 2634 #phy-cells = <0>; 2635 2636 status = "disabled"; 2637 }; 2638 2639 usb_2_hsphy1: phy@88e8000 { 2640 compatible = "qcom,sc8280xp-usb-hs-phy", 2641 "qcom,usb-snps-hs-5nm-phy"; 2642 reg = <0 0x088e8000 0 0x400>; 2643 clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>; 2644 clock-names = "ref"; 2645 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 2646 2647 #phy-cells = <0>; 2648 2649 status = "disabled"; 2650 }; 2651 2652 usb_2_hsphy2: phy@88e9000 { 2653 compatible = "qcom,sc8280xp-usb-hs-phy", 2654 "qcom,usb-snps-hs-5nm-phy"; 2655 reg = <0 0x088e9000 0 0x400>; 2656 clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>; 2657 clock-names = "ref"; 2658 resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>; 2659 2660 #phy-cells = <0>; 2661 2662 status = "disabled"; 2663 }; 2664 2665 usb_2_hsphy3: phy@88ea000 { 2666 compatible = "qcom,sc8280xp-usb-hs-phy", 2667 "qcom,usb-snps-hs-5nm-phy"; 2668 reg = <0 0x088ea000 0 0x400>; 2669 clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>; 2670 clock-names = "ref"; 2671 resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>; 2672 2673 #phy-cells = <0>; 2674 2675 status = "disabled"; 2676 }; 2677 2678 usb_2_qmpphy0: phy@88ef000 { 2679 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 2680 reg = <0 0x088ef000 0 0x2000>; 2681 2682 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2683 <&gcc GCC_USB3_MP0_CLKREF_CLK>, 2684 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2685 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 2686 clock-names = "aux", "ref", "com_aux", "pipe"; 2687 2688 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 2689 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 2690 reset-names = "phy", "phy_phy"; 2691 2692 power-domains = <&gcc USB30_MP_GDSC>; 2693 2694 #clock-cells = <0>; 2695 clock-output-names = "usb2_phy0_pipe_clk"; 2696 2697 #phy-cells = <0>; 2698 2699 status = "disabled"; 2700 }; 2701 2702 usb_2_qmpphy1: phy@88f1000 { 2703 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 2704 reg = <0 0x088f1000 0 0x2000>; 2705 2706 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2707 <&gcc GCC_USB3_MP1_CLKREF_CLK>, 2708 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2709 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 2710 clock-names = "aux", "ref", "com_aux", "pipe"; 2711 2712 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, 2713 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 2714 reset-names = "phy", "phy_phy"; 2715 2716 power-domains = <&gcc USB30_MP_GDSC>; 2717 2718 #clock-cells = <0>; 2719 clock-output-names = "usb2_phy1_pipe_clk"; 2720 2721 #phy-cells = <0>; 2722 2723 status = "disabled"; 2724 }; 2725 2726 remoteproc_adsp: remoteproc@3000000 { 2727 compatible = "qcom,sc8280xp-adsp-pas"; 2728 reg = <0 0x03000000 0 0x100>; 2729 2730 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2731 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2732 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2733 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2734 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, 2735 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; 2736 interrupt-names = "wdog", "fatal", "ready", 2737 "handover", "stop-ack", "shutdown-ack"; 2738 2739 clocks = <&rpmhcc RPMH_CXO_CLK>; 2740 clock-names = "xo"; 2741 2742 power-domains = <&rpmhpd SC8280XP_LCX>, 2743 <&rpmhpd SC8280XP_LMX>; 2744 power-domain-names = "lcx", "lmx"; 2745 2746 memory-region = <&pil_adsp_mem>; 2747 2748 qcom,qmp = <&aoss_qmp>; 2749 2750 qcom,smem-states = <&smp2p_adsp_out 0>; 2751 qcom,smem-state-names = "stop"; 2752 2753 status = "disabled"; 2754 2755 remoteproc_adsp_glink: glink-edge { 2756 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2757 IPCC_MPROC_SIGNAL_GLINK_QMP 2758 IRQ_TYPE_EDGE_RISING>; 2759 mboxes = <&ipcc IPCC_CLIENT_LPASS 2760 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2761 2762 label = "lpass"; 2763 qcom,remote-pid = <2>; 2764 2765 gpr { 2766 compatible = "qcom,gpr"; 2767 qcom,glink-channels = "adsp_apps"; 2768 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2769 qcom,intents = <512 20>; 2770 #address-cells = <1>; 2771 #size-cells = <0>; 2772 2773 q6apm: service@1 { 2774 compatible = "qcom,q6apm"; 2775 reg = <GPR_APM_MODULE_IID>; 2776 #sound-dai-cells = <0>; 2777 qcom,protection-domain = "avs/audio", 2778 "msm/adsp/audio_pd"; 2779 q6apmdai: dais { 2780 compatible = "qcom,q6apm-dais"; 2781 iommus = <&apps_smmu 0x0c01 0x0>; 2782 }; 2783 2784 q6apmbedai: bedais { 2785 compatible = "qcom,q6apm-lpass-dais"; 2786 #sound-dai-cells = <1>; 2787 }; 2788 }; 2789 2790 q6prm: service@2 { 2791 compatible = "qcom,q6prm"; 2792 reg = <GPR_PRM_MODULE_IID>; 2793 qcom,protection-domain = "avs/audio", 2794 "msm/adsp/audio_pd"; 2795 q6prmcc: clock-controller { 2796 compatible = "qcom,q6prm-lpass-clocks"; 2797 #clock-cells = <2>; 2798 }; 2799 }; 2800 }; 2801 }; 2802 }; 2803 2804 rxmacro: rxmacro@3200000 { 2805 compatible = "qcom,sc8280xp-lpass-rx-macro"; 2806 reg = <0 0x03200000 0 0x1000>; 2807 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2808 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2809 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2810 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2811 <&vamacro>; 2812 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2813 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2814 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2815 assigned-clock-rates = <19200000>, <19200000>; 2816 2817 clock-output-names = "mclk"; 2818 #clock-cells = <0>; 2819 #sound-dai-cells = <1>; 2820 2821 pinctrl-names = "default"; 2822 pinctrl-0 = <&rx_swr_default>; 2823 2824 status = "disabled"; 2825 }; 2826 2827 swr1: soundwire@3210000 { 2828 compatible = "qcom,soundwire-v1.6.0"; 2829 reg = <0 0x03210000 0 0x2000>; 2830 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2831 clocks = <&rxmacro>; 2832 clock-names = "iface"; 2833 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2834 reset-names = "swr_audio_cgcr"; 2835 label = "RX"; 2836 2837 qcom,din-ports = <0>; 2838 qcom,dout-ports = <5>; 2839 2840 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2841 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; 2842 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; 2843 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>; 2844 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>; 2845 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2846 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>; 2847 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2848 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2849 2850 #sound-dai-cells = <1>; 2851 #address-cells = <2>; 2852 #size-cells = <0>; 2853 2854 status = "disabled"; 2855 }; 2856 2857 txmacro: txmacro@3220000 { 2858 compatible = "qcom,sc8280xp-lpass-tx-macro"; 2859 reg = <0 0x03220000 0 0x1000>; 2860 pinctrl-names = "default"; 2861 pinctrl-0 = <&tx_swr_default>; 2862 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2863 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2864 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2865 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2866 <&vamacro>; 2867 2868 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2869 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2870 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2871 assigned-clock-rates = <19200000>, <19200000>; 2872 clock-output-names = "mclk"; 2873 2874 #clock-cells = <0>; 2875 #sound-dai-cells = <1>; 2876 2877 status = "disabled"; 2878 }; 2879 2880 wsamacro: codec@3240000 { 2881 compatible = "qcom,sc8280xp-lpass-wsa-macro"; 2882 reg = <0 0x03240000 0 0x1000>; 2883 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2884 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2885 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2886 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2887 <&vamacro>; 2888 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2889 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2890 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2891 assigned-clock-rates = <19200000>, <19200000>; 2892 2893 #clock-cells = <0>; 2894 clock-output-names = "mclk"; 2895 #sound-dai-cells = <1>; 2896 2897 pinctrl-names = "default"; 2898 pinctrl-0 = <&wsa_swr_default>; 2899 2900 status = "disabled"; 2901 }; 2902 2903 swr0: soundwire@3250000 { 2904 reg = <0 0x03250000 0 0x2000>; 2905 compatible = "qcom,soundwire-v1.6.0"; 2906 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2907 clocks = <&wsamacro>; 2908 clock-names = "iface"; 2909 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; 2910 reset-names = "swr_audio_cgcr"; 2911 label = "WSA"; 2912 2913 qcom,din-ports = <2>; 2914 qcom,dout-ports = <6>; 2915 2916 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2917 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2918 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2919 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2920 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2921 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2922 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2923 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2924 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2925 2926 #sound-dai-cells = <1>; 2927 #address-cells = <2>; 2928 #size-cells = <0>; 2929 2930 status = "disabled"; 2931 }; 2932 2933 lpass_audiocc: clock-controller@32a9000 { 2934 compatible = "qcom,sc8280xp-lpassaudiocc"; 2935 reg = <0 0x032a9000 0 0x1000>; 2936 #clock-cells = <1>; 2937 #reset-cells = <1>; 2938 }; 2939 2940 swr2: soundwire@3330000 { 2941 compatible = "qcom,soundwire-v1.6.0"; 2942 reg = <0 0x03330000 0 0x2000>; 2943 interrupts = <GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>, 2944 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2945 interrupt-names = "core", "wakeup"; 2946 2947 clocks = <&txmacro>; 2948 clock-names = "iface"; 2949 resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; 2950 reset-names = "swr_audio_cgcr"; 2951 label = "TX"; 2952 #sound-dai-cells = <1>; 2953 #address-cells = <2>; 2954 #size-cells = <0>; 2955 2956 qcom,din-ports = <4>; 2957 qcom,dout-ports = <0>; 2958 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2959 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>; 2960 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2961 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2962 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2963 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2964 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2965 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2966 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>; 2967 2968 status = "disabled"; 2969 }; 2970 2971 vamacro: codec@3370000 { 2972 compatible = "qcom,sc8280xp-lpass-va-macro"; 2973 reg = <0 0x03370000 0 0x1000>; 2974 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2975 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2976 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2977 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2978 clock-names = "mclk", "macro", "dcodec", "npl"; 2979 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2980 assigned-clock-rates = <19200000>; 2981 2982 #clock-cells = <0>; 2983 clock-output-names = "fsgen"; 2984 #sound-dai-cells = <1>; 2985 2986 status = "disabled"; 2987 }; 2988 2989 lpass_tlmm: pinctrl@33c0000 { 2990 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl"; 2991 reg = <0 0x33c0000 0x0 0x20000>, 2992 <0 0x3550000 0x0 0x10000>; 2993 gpio-controller; 2994 #gpio-cells = <2>; 2995 gpio-ranges = <&lpass_tlmm 0 0 19>; 2996 2997 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2998 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2999 clock-names = "core", "audio"; 3000 3001 status = "disabled"; 3002 3003 tx_swr_default: tx-swr-default-state { 3004 clk-pins { 3005 pins = "gpio0"; 3006 function = "swr_tx_clk"; 3007 drive-strength = <2>; 3008 slew-rate = <1>; 3009 bias-disable; 3010 }; 3011 3012 data-pins { 3013 pins = "gpio1", "gpio2"; 3014 function = "swr_tx_data"; 3015 drive-strength = <2>; 3016 slew-rate = <1>; 3017 bias-bus-hold; 3018 }; 3019 }; 3020 3021 rx_swr_default: rx-swr-default-state { 3022 clk-pins { 3023 pins = "gpio3"; 3024 function = "swr_rx_clk"; 3025 drive-strength = <2>; 3026 slew-rate = <1>; 3027 bias-disable; 3028 }; 3029 3030 data-pins { 3031 pins = "gpio4", "gpio5"; 3032 function = "swr_rx_data"; 3033 drive-strength = <2>; 3034 slew-rate = <1>; 3035 bias-bus-hold; 3036 }; 3037 }; 3038 3039 dmic01_default: dmic01-default-state { 3040 clk-pins { 3041 pins = "gpio6"; 3042 function = "dmic1_clk"; 3043 drive-strength = <8>; 3044 output-high; 3045 }; 3046 3047 data-pins { 3048 pins = "gpio7"; 3049 function = "dmic1_data"; 3050 drive-strength = <8>; 3051 input-enable; 3052 }; 3053 }; 3054 3055 dmic01_sleep: dmic01-sleep-state { 3056 clk-pins { 3057 pins = "gpio6"; 3058 function = "dmic1_clk"; 3059 drive-strength = <2>; 3060 bias-disable; 3061 output-low; 3062 }; 3063 3064 data-pins { 3065 pins = "gpio7"; 3066 function = "dmic1_data"; 3067 drive-strength = <2>; 3068 bias-pull-down; 3069 input-enable; 3070 }; 3071 }; 3072 3073 dmic23_default: dmic23-default-state { 3074 clk-pins { 3075 pins = "gpio8"; 3076 function = "dmic2_clk"; 3077 drive-strength = <8>; 3078 output-high; 3079 }; 3080 3081 data-pins { 3082 pins = "gpio9"; 3083 function = "dmic2_data"; 3084 drive-strength = <8>; 3085 input-enable; 3086 }; 3087 }; 3088 3089 dmic23_sleep: dmic23-sleep-state { 3090 clk-pins { 3091 pins = "gpio8"; 3092 function = "dmic2_clk"; 3093 drive-strength = <2>; 3094 bias-disable; 3095 output-low; 3096 }; 3097 3098 data-pins { 3099 pins = "gpio9"; 3100 function = "dmic2_data"; 3101 drive-strength = <2>; 3102 bias-pull-down; 3103 input-enable; 3104 }; 3105 }; 3106 3107 wsa_swr_default: wsa-swr-default-state { 3108 clk-pins { 3109 pins = "gpio10"; 3110 function = "wsa_swr_clk"; 3111 drive-strength = <2>; 3112 slew-rate = <1>; 3113 bias-disable; 3114 }; 3115 3116 data-pins { 3117 pins = "gpio11"; 3118 function = "wsa_swr_data"; 3119 drive-strength = <2>; 3120 slew-rate = <1>; 3121 bias-bus-hold; 3122 }; 3123 }; 3124 3125 wsa2_swr_default: wsa2-swr-default-state { 3126 clk-pins { 3127 pins = "gpio15"; 3128 function = "wsa2_swr_clk"; 3129 drive-strength = <2>; 3130 slew-rate = <1>; 3131 bias-disable; 3132 }; 3133 3134 data-pins { 3135 pins = "gpio16"; 3136 function = "wsa2_swr_data"; 3137 drive-strength = <2>; 3138 slew-rate = <1>; 3139 bias-bus-hold; 3140 }; 3141 }; 3142 }; 3143 3144 lpasscc: clock-controller@33e0000 { 3145 compatible = "qcom,sc8280xp-lpasscc"; 3146 reg = <0 0x033e0000 0 0x12000>; 3147 #clock-cells = <1>; 3148 #reset-cells = <1>; 3149 }; 3150 3151 sdc2: mmc@8804000 { 3152 compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5"; 3153 reg = <0 0x08804000 0 0x1000>; 3154 3155 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3156 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3157 interrupt-names = "hc_irq", "pwr_irq"; 3158 3159 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3160 <&gcc GCC_SDCC2_APPS_CLK>, 3161 <&rpmhcc RPMH_CXO_CLK>; 3162 clock-names = "iface", "core", "xo"; 3163 resets = <&gcc GCC_SDCC2_BCR>; 3164 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3165 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 3166 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3167 iommus = <&apps_smmu 0x4e0 0x0>; 3168 power-domains = <&rpmhpd SC8280XP_CX>; 3169 operating-points-v2 = <&sdc2_opp_table>; 3170 bus-width = <4>; 3171 dma-coherent; 3172 3173 status = "disabled"; 3174 3175 sdc2_opp_table: opp-table { 3176 compatible = "operating-points-v2"; 3177 3178 opp-100000000 { 3179 opp-hz = /bits/ 64 <100000000>; 3180 required-opps = <&rpmhpd_opp_low_svs>; 3181 opp-peak-kBps = <1800000 400000>; 3182 opp-avg-kBps = <100000 0>; 3183 }; 3184 3185 opp-202000000 { 3186 opp-hz = /bits/ 64 <202000000>; 3187 required-opps = <&rpmhpd_opp_svs_l1>; 3188 opp-peak-kBps = <5400000 1600000>; 3189 opp-avg-kBps = <200000 0>; 3190 }; 3191 }; 3192 }; 3193 3194 usb_0_qmpphy: phy@88eb000 { 3195 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 3196 reg = <0 0x088eb000 0 0x4000>; 3197 3198 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3199 <&gcc GCC_USB4_EUD_CLKREF_CLK>, 3200 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3201 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3202 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3203 3204 power-domains = <&gcc USB30_PRIM_GDSC>; 3205 3206 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3207 <&gcc GCC_USB4_DP_PHY_PRIM_BCR>; 3208 reset-names = "phy", "common"; 3209 3210 #clock-cells = <1>; 3211 #phy-cells = <1>; 3212 3213 status = "disabled"; 3214 3215 ports { 3216 #address-cells = <1>; 3217 #size-cells = <0>; 3218 3219 port@0 { 3220 reg = <0>; 3221 3222 usb_0_qmpphy_out: endpoint {}; 3223 }; 3224 3225 port@2 { 3226 reg = <2>; 3227 3228 usb_0_qmpphy_dp_in: endpoint {}; 3229 }; 3230 }; 3231 }; 3232 3233 usb_1_hsphy: phy@8902000 { 3234 compatible = "qcom,sc8280xp-usb-hs-phy", 3235 "qcom,usb-snps-hs-5nm-phy"; 3236 reg = <0 0x08902000 0 0x400>; 3237 #phy-cells = <0>; 3238 3239 clocks = <&rpmhcc RPMH_CXO_CLK>; 3240 clock-names = "ref"; 3241 3242 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3243 3244 status = "disabled"; 3245 }; 3246 3247 usb_1_qmpphy: phy@8903000 { 3248 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 3249 reg = <0 0x08903000 0 0x4000>; 3250 3251 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3252 <&gcc GCC_USB4_CLKREF_CLK>, 3253 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 3254 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3255 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3256 3257 power-domains = <&gcc USB30_SEC_GDSC>; 3258 3259 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 3260 <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>; 3261 reset-names = "phy", "common"; 3262 3263 #clock-cells = <1>; 3264 #phy-cells = <1>; 3265 3266 status = "disabled"; 3267 3268 ports { 3269 #address-cells = <1>; 3270 #size-cells = <0>; 3271 3272 port@0 { 3273 reg = <0>; 3274 3275 usb_1_qmpphy_out: endpoint {}; 3276 }; 3277 3278 port@2 { 3279 reg = <2>; 3280 3281 usb_1_qmpphy_dp_in: endpoint {}; 3282 }; 3283 }; 3284 }; 3285 3286 mdss1_dp0_phy: phy@8909a00 { 3287 compatible = "qcom,sc8280xp-dp-phy"; 3288 reg = <0 0x08909a00 0 0x19c>, 3289 <0 0x08909200 0 0xec>, 3290 <0 0x08909600 0 0xec>, 3291 <0 0x08909000 0 0x1c8>; 3292 3293 clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 3294 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 3295 clock-names = "aux", "cfg_ahb"; 3296 power-domains = <&rpmhpd SC8280XP_MX>; 3297 3298 #clock-cells = <1>; 3299 #phy-cells = <0>; 3300 3301 status = "disabled"; 3302 }; 3303 3304 mdss1_dp1_phy: phy@890ca00 { 3305 compatible = "qcom,sc8280xp-dp-phy"; 3306 reg = <0 0x0890ca00 0 0x19c>, 3307 <0 0x0890c200 0 0xec>, 3308 <0 0x0890c600 0 0xec>, 3309 <0 0x0890c000 0 0x1c8>; 3310 3311 clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 3312 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 3313 clock-names = "aux", "cfg_ahb"; 3314 power-domains = <&rpmhpd SC8280XP_MX>; 3315 3316 #clock-cells = <1>; 3317 #phy-cells = <0>; 3318 3319 status = "disabled"; 3320 }; 3321 3322 pmu@9091000 { 3323 compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3324 reg = <0 0x09091000 0 0x1000>; 3325 3326 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3327 3328 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3329 3330 operating-points-v2 = <&llcc_bwmon_opp_table>; 3331 3332 llcc_bwmon_opp_table: opp-table { 3333 compatible = "operating-points-v2"; 3334 3335 opp-0 { 3336 opp-peak-kBps = <762000>; 3337 }; 3338 opp-1 { 3339 opp-peak-kBps = <1720000>; 3340 }; 3341 opp-2 { 3342 opp-peak-kBps = <2086000>; 3343 }; 3344 opp-3 { 3345 opp-peak-kBps = <2597000>; 3346 }; 3347 opp-4 { 3348 opp-peak-kBps = <2929000>; 3349 }; 3350 opp-5 { 3351 opp-peak-kBps = <3879000>; 3352 }; 3353 opp-6 { 3354 opp-peak-kBps = <5161000>; 3355 }; 3356 opp-7 { 3357 opp-peak-kBps = <5931000>; 3358 }; 3359 opp-8 { 3360 opp-peak-kBps = <6515000>; 3361 }; 3362 opp-9 { 3363 opp-peak-kBps = <7980000>; 3364 }; 3365 opp-10 { 3366 opp-peak-kBps = <8136000>; 3367 }; 3368 opp-11 { 3369 opp-peak-kBps = <10437000>; 3370 }; 3371 opp-12 { 3372 opp-peak-kBps = <12191000>; 3373 }; 3374 }; 3375 }; 3376 3377 pmu@90b6400 { 3378 compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon"; 3379 reg = <0 0x090b6400 0 0x600>; 3380 3381 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3382 3383 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3384 operating-points-v2 = <&cpu_bwmon_opp_table>; 3385 3386 cpu_bwmon_opp_table: opp-table { 3387 compatible = "operating-points-v2"; 3388 3389 opp-0 { 3390 opp-peak-kBps = <2288000>; 3391 }; 3392 opp-1 { 3393 opp-peak-kBps = <4577000>; 3394 }; 3395 opp-2 { 3396 opp-peak-kBps = <7110000>; 3397 }; 3398 opp-3 { 3399 opp-peak-kBps = <9155000>; 3400 }; 3401 opp-4 { 3402 opp-peak-kBps = <12298000>; 3403 }; 3404 opp-5 { 3405 opp-peak-kBps = <14236000>; 3406 }; 3407 opp-6 { 3408 opp-peak-kBps = <15258001>; 3409 }; 3410 }; 3411 }; 3412 3413 system-cache-controller@9200000 { 3414 compatible = "qcom,sc8280xp-llcc"; 3415 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 3416 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 3417 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, 3418 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, 3419 <0 0x09600000 0 0x58000>; 3420 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 3421 "llcc3_base", "llcc4_base", "llcc5_base", 3422 "llcc6_base", "llcc7_base", "llcc_broadcast_base"; 3423 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3424 }; 3425 3426 usb_2: usb@a4f8800 { 3427 compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3"; 3428 reg = <0 0x0a4f8800 0 0x400>; 3429 #address-cells = <2>; 3430 #size-cells = <2>; 3431 ranges; 3432 3433 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, 3434 <&gcc GCC_USB30_MP_MASTER_CLK>, 3435 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, 3436 <&gcc GCC_USB30_MP_SLEEP_CLK>, 3437 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 3438 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3439 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 3440 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 3441 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3442 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 3443 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 3444 3445 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 3446 <&gcc GCC_USB30_MP_MASTER_CLK>; 3447 assigned-clock-rates = <19200000>, <200000000>; 3448 3449 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 3450 <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 3451 <&intc GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>, 3452 <&intc GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, 3453 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3454 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3455 <&intc GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>, 3456 <&intc GIC_SPI 859 IRQ_TYPE_LEVEL_HIGH>, 3457 <&pdc 127 IRQ_TYPE_EDGE_BOTH>, 3458 <&pdc 126 IRQ_TYPE_EDGE_BOTH>, 3459 <&pdc 129 IRQ_TYPE_EDGE_BOTH>, 3460 <&pdc 128 IRQ_TYPE_EDGE_BOTH>, 3461 <&pdc 131 IRQ_TYPE_EDGE_BOTH>, 3462 <&pdc 130 IRQ_TYPE_EDGE_BOTH>, 3463 <&pdc 133 IRQ_TYPE_EDGE_BOTH>, 3464 <&pdc 132 IRQ_TYPE_EDGE_BOTH>, 3465 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, 3466 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 3467 3468 interrupt-names = "pwr_event_1", "pwr_event_2", 3469 "pwr_event_3", "pwr_event_4", 3470 "hs_phy_1", "hs_phy_2", 3471 "hs_phy_3", "hs_phy_4", 3472 "dp_hs_phy_1", "dm_hs_phy_1", 3473 "dp_hs_phy_2", "dm_hs_phy_2", 3474 "dp_hs_phy_3", "dm_hs_phy_3", 3475 "dp_hs_phy_4", "dm_hs_phy_4", 3476 "ss_phy_1", "ss_phy_2"; 3477 3478 power-domains = <&gcc USB30_MP_GDSC>; 3479 required-opps = <&rpmhpd_opp_nom>; 3480 3481 resets = <&gcc GCC_USB30_MP_BCR>; 3482 3483 interconnects = <&aggre1_noc MASTER_USB3_MP 0 &mc_virt SLAVE_EBI1 0>, 3484 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_MP 0>; 3485 interconnect-names = "usb-ddr", "apps-usb"; 3486 3487 wakeup-source; 3488 3489 status = "disabled"; 3490 3491 usb_2_dwc3: usb@a400000 { 3492 compatible = "snps,dwc3"; 3493 reg = <0 0x0a400000 0 0xcd00>; 3494 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3495 iommus = <&apps_smmu 0x800 0x0>; 3496 phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>, 3497 <&usb_2_hsphy1>, <&usb_2_qmpphy1>, 3498 <&usb_2_hsphy2>, 3499 <&usb_2_hsphy3>; 3500 phy-names = "usb2-0", "usb3-0", 3501 "usb2-1", "usb3-1", 3502 "usb2-2", 3503 "usb2-3"; 3504 dr_mode = "host"; 3505 }; 3506 }; 3507 3508 usb_0: usb@a6f8800 { 3509 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 3510 reg = <0 0x0a6f8800 0 0x400>; 3511 #address-cells = <2>; 3512 #size-cells = <2>; 3513 ranges; 3514 3515 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3516 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3517 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3518 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3519 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3520 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3521 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 3522 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 3523 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3524 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 3525 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 3526 3527 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3528 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3529 assigned-clock-rates = <19200000>, <200000000>; 3530 3531 interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 3532 <&intc GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, 3533 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3534 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3535 <&pdc 138 IRQ_TYPE_LEVEL_HIGH>; 3536 interrupt-names = "pwr_event", 3537 "hs_phy_irq", 3538 "dp_hs_phy_irq", 3539 "dm_hs_phy_irq", 3540 "ss_phy_irq"; 3541 3542 power-domains = <&gcc USB30_PRIM_GDSC>; 3543 required-opps = <&rpmhpd_opp_nom>; 3544 3545 resets = <&gcc GCC_USB30_PRIM_BCR>; 3546 3547 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3548 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 3549 interconnect-names = "usb-ddr", "apps-usb"; 3550 3551 wakeup-source; 3552 3553 status = "disabled"; 3554 3555 usb_0_dwc3: usb@a600000 { 3556 compatible = "snps,dwc3"; 3557 reg = <0 0x0a600000 0 0xcd00>; 3558 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 3559 iommus = <&apps_smmu 0x820 0x0>; 3560 phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; 3561 phy-names = "usb2-phy", "usb3-phy"; 3562 3563 port { 3564 usb_0_role_switch: endpoint { 3565 }; 3566 }; 3567 }; 3568 }; 3569 3570 usb_1: usb@a8f8800 { 3571 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 3572 reg = <0 0x0a8f8800 0 0x400>; 3573 #address-cells = <2>; 3574 #size-cells = <2>; 3575 ranges; 3576 3577 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3578 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3579 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3580 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3581 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3582 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3583 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 3584 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 3585 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3586 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 3587 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 3588 3589 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3590 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3591 assigned-clock-rates = <19200000>, <200000000>; 3592 3593 interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 3594 <&intc GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 3595 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 3596 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 3597 <&pdc 136 IRQ_TYPE_LEVEL_HIGH>; 3598 interrupt-names = "pwr_event", 3599 "hs_phy_irq", 3600 "dp_hs_phy_irq", 3601 "dm_hs_phy_irq", 3602 "ss_phy_irq"; 3603 3604 power-domains = <&gcc USB30_SEC_GDSC>; 3605 required-opps = <&rpmhpd_opp_nom>; 3606 3607 resets = <&gcc GCC_USB30_SEC_BCR>; 3608 3609 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 3610 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 3611 interconnect-names = "usb-ddr", "apps-usb"; 3612 3613 wakeup-source; 3614 3615 status = "disabled"; 3616 3617 usb_1_dwc3: usb@a800000 { 3618 compatible = "snps,dwc3"; 3619 reg = <0 0x0a800000 0 0xcd00>; 3620 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 3621 iommus = <&apps_smmu 0x860 0x0>; 3622 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 3623 phy-names = "usb2-phy", "usb3-phy"; 3624 3625 port { 3626 usb_1_role_switch: endpoint { 3627 }; 3628 }; 3629 }; 3630 }; 3631 3632 cci0: cci@ac4a000 { 3633 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 3634 reg = <0 0x0ac4a000 0 0x1000>; 3635 3636 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 3637 3638 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 3639 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 3640 <&camcc CAMCC_CPAS_AHB_CLK>, 3641 <&camcc CAMCC_CCI_0_CLK>; 3642 clock-names = "camnoc_axi", 3643 "slow_ahb_src", 3644 "cpas_ahb", 3645 "cci"; 3646 3647 power-domains = <&camcc TITAN_TOP_GDSC>; 3648 3649 pinctrl-0 = <&cci0_default>; 3650 pinctrl-1 = <&cci0_sleep>; 3651 pinctrl-names = "default", "sleep"; 3652 3653 #address-cells = <1>; 3654 #size-cells = <0>; 3655 3656 status = "disabled"; 3657 3658 cci0_i2c0: i2c-bus@0 { 3659 reg = <0>; 3660 clock-frequency = <1000000>; 3661 #address-cells = <1>; 3662 #size-cells = <0>; 3663 }; 3664 3665 cci0_i2c1: i2c-bus@1 { 3666 reg = <1>; 3667 clock-frequency = <1000000>; 3668 #address-cells = <1>; 3669 #size-cells = <0>; 3670 }; 3671 }; 3672 3673 cci1: cci@ac4b000 { 3674 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 3675 reg = <0 0x0ac4b000 0 0x1000>; 3676 3677 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 3678 3679 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 3680 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 3681 <&camcc CAMCC_CPAS_AHB_CLK>, 3682 <&camcc CAMCC_CCI_1_CLK>; 3683 clock-names = "camnoc_axi", 3684 "slow_ahb_src", 3685 "cpas_ahb", 3686 "cci"; 3687 3688 power-domains = <&camcc TITAN_TOP_GDSC>; 3689 3690 pinctrl-0 = <&cci1_default>; 3691 pinctrl-1 = <&cci1_sleep>; 3692 pinctrl-names = "default", "sleep"; 3693 3694 #address-cells = <1>; 3695 #size-cells = <0>; 3696 3697 status = "disabled"; 3698 3699 cci1_i2c0: i2c-bus@0 { 3700 reg = <0>; 3701 clock-frequency = <1000000>; 3702 #address-cells = <1>; 3703 #size-cells = <0>; 3704 }; 3705 3706 cci1_i2c1: i2c-bus@1 { 3707 reg = <1>; 3708 clock-frequency = <1000000>; 3709 #address-cells = <1>; 3710 #size-cells = <0>; 3711 }; 3712 }; 3713 3714 cci2: cci@ac4c000 { 3715 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 3716 reg = <0 0x0ac4c000 0 0x1000>; 3717 3718 interrupts = <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>; 3719 3720 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 3721 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 3722 <&camcc CAMCC_CPAS_AHB_CLK>, 3723 <&camcc CAMCC_CCI_2_CLK>; 3724 clock-names = "camnoc_axi", 3725 "slow_ahb_src", 3726 "cpas_ahb", 3727 "cci"; 3728 power-domains = <&camcc TITAN_TOP_GDSC>; 3729 3730 pinctrl-0 = <&cci2_default>; 3731 pinctrl-1 = <&cci2_sleep>; 3732 pinctrl-names = "default", "sleep"; 3733 3734 #address-cells = <1>; 3735 #size-cells = <0>; 3736 3737 status = "disabled"; 3738 3739 cci2_i2c0: i2c-bus@0 { 3740 reg = <0>; 3741 clock-frequency = <1000000>; 3742 #address-cells = <1>; 3743 #size-cells = <0>; 3744 }; 3745 3746 cci2_i2c1: i2c-bus@1 { 3747 reg = <1>; 3748 clock-frequency = <1000000>; 3749 #address-cells = <1>; 3750 #size-cells = <0>; 3751 }; 3752 }; 3753 3754 cci3: cci@ac4d000 { 3755 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 3756 reg = <0 0x0ac4d000 0 0x1000>; 3757 3758 interrupts = <GIC_SPI 650 IRQ_TYPE_EDGE_RISING>; 3759 3760 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 3761 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 3762 <&camcc CAMCC_CPAS_AHB_CLK>, 3763 <&camcc CAMCC_CCI_3_CLK>; 3764 clock-names = "camnoc_axi", 3765 "slow_ahb_src", 3766 "cpas_ahb", 3767 "cci"; 3768 3769 power-domains = <&camcc TITAN_TOP_GDSC>; 3770 3771 pinctrl-0 = <&cci3_default>; 3772 pinctrl-1 = <&cci3_sleep>; 3773 pinctrl-names = "default", "sleep"; 3774 3775 #address-cells = <1>; 3776 #size-cells = <0>; 3777 3778 status = "disabled"; 3779 3780 cci3_i2c0: i2c-bus@0 { 3781 reg = <0>; 3782 clock-frequency = <1000000>; 3783 #address-cells = <1>; 3784 #size-cells = <0>; 3785 }; 3786 3787 cci3_i2c1: i2c-bus@1 { 3788 reg = <1>; 3789 clock-frequency = <1000000>; 3790 #address-cells = <1>; 3791 #size-cells = <0>; 3792 }; 3793 }; 3794 3795 camss: camss@ac5a000 { 3796 compatible = "qcom,sc8280xp-camss"; 3797 3798 reg = <0 0x0ac5a000 0 0x2000>, 3799 <0 0x0ac5c000 0 0x2000>, 3800 <0 0x0ac65000 0 0x2000>, 3801 <0 0x0ac67000 0 0x2000>, 3802 <0 0x0acaf000 0 0x4000>, 3803 <0 0x0acb3000 0 0x1000>, 3804 <0 0x0acb6000 0 0x4000>, 3805 <0 0x0acba000 0 0x1000>, 3806 <0 0x0acbd000 0 0x4000>, 3807 <0 0x0acc1000 0 0x1000>, 3808 <0 0x0acc4000 0 0x4000>, 3809 <0 0x0acc8000 0 0x1000>, 3810 <0 0x0accb000 0 0x4000>, 3811 <0 0x0accf000 0 0x1000>, 3812 <0 0x0acd2000 0 0x4000>, 3813 <0 0x0acd6000 0 0x1000>, 3814 <0 0x0acd9000 0 0x4000>, 3815 <0 0x0acdd000 0 0x1000>, 3816 <0 0x0ace0000 0 0x4000>, 3817 <0 0x0ace4000 0 0x1000>; 3818 reg-names = "csiphy2", 3819 "csiphy3", 3820 "csiphy0", 3821 "csiphy1", 3822 "vfe0", 3823 "csid0", 3824 "vfe1", 3825 "csid1", 3826 "vfe2", 3827 "csid2", 3828 "vfe_lite0", 3829 "csid0_lite", 3830 "vfe_lite1", 3831 "csid1_lite", 3832 "vfe_lite2", 3833 "csid2_lite", 3834 "vfe_lite3", 3835 "csid3_lite", 3836 "vfe3", 3837 "csid3"; 3838 3839 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 3840 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 3841 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 3842 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 3843 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 3844 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 3845 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 3846 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 3847 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 3848 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, 3849 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, 3850 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, 3851 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>, 3852 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 3853 <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>, 3854 <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>, 3855 <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>, 3856 <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>, 3857 <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>, 3858 <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>; 3859 interrupt-names = "csid1_lite", 3860 "vfe_lite1", 3861 "csiphy3", 3862 "csid0", 3863 "vfe0", 3864 "csid1", 3865 "vfe1", 3866 "csid0_lite", 3867 "vfe_lite0", 3868 "csiphy0", 3869 "csiphy1", 3870 "csiphy2", 3871 "csid2", 3872 "vfe2", 3873 "csid3_lite", 3874 "csid2_lite", 3875 "vfe_lite3", 3876 "vfe_lite2", 3877 "csid3", 3878 "vfe3"; 3879 3880 power-domains = <&camcc IFE_0_GDSC>, 3881 <&camcc IFE_1_GDSC>, 3882 <&camcc IFE_2_GDSC>, 3883 <&camcc IFE_3_GDSC>, 3884 <&camcc TITAN_TOP_GDSC>; 3885 power-domain-names = "ife0", 3886 "ife1", 3887 "ife2", 3888 "ife3", 3889 "top"; 3890 3891 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 3892 <&camcc CAMCC_CPAS_AHB_CLK>, 3893 <&camcc CAMCC_CSIPHY0_CLK>, 3894 <&camcc CAMCC_CSI0PHYTIMER_CLK>, 3895 <&camcc CAMCC_CSIPHY1_CLK>, 3896 <&camcc CAMCC_CSI1PHYTIMER_CLK>, 3897 <&camcc CAMCC_CSIPHY2_CLK>, 3898 <&camcc CAMCC_CSI2PHYTIMER_CLK>, 3899 <&camcc CAMCC_CSIPHY3_CLK>, 3900 <&camcc CAMCC_CSI3PHYTIMER_CLK>, 3901 <&camcc CAMCC_IFE_0_AXI_CLK>, 3902 <&camcc CAMCC_IFE_0_CLK>, 3903 <&camcc CAMCC_IFE_0_CPHY_RX_CLK>, 3904 <&camcc CAMCC_IFE_0_CSID_CLK>, 3905 <&camcc CAMCC_IFE_1_AXI_CLK>, 3906 <&camcc CAMCC_IFE_1_CLK>, 3907 <&camcc CAMCC_IFE_1_CPHY_RX_CLK>, 3908 <&camcc CAMCC_IFE_1_CSID_CLK>, 3909 <&camcc CAMCC_IFE_2_AXI_CLK>, 3910 <&camcc CAMCC_IFE_2_CLK>, 3911 <&camcc CAMCC_IFE_2_CPHY_RX_CLK>, 3912 <&camcc CAMCC_IFE_2_CSID_CLK>, 3913 <&camcc CAMCC_IFE_3_AXI_CLK>, 3914 <&camcc CAMCC_IFE_3_CLK>, 3915 <&camcc CAMCC_IFE_3_CPHY_RX_CLK>, 3916 <&camcc CAMCC_IFE_3_CSID_CLK>, 3917 <&camcc CAMCC_IFE_LITE_0_CLK>, 3918 <&camcc CAMCC_IFE_LITE_0_CPHY_RX_CLK>, 3919 <&camcc CAMCC_IFE_LITE_0_CSID_CLK>, 3920 <&camcc CAMCC_IFE_LITE_1_CLK>, 3921 <&camcc CAMCC_IFE_LITE_1_CPHY_RX_CLK>, 3922 <&camcc CAMCC_IFE_LITE_1_CSID_CLK>, 3923 <&camcc CAMCC_IFE_LITE_2_CLK>, 3924 <&camcc CAMCC_IFE_LITE_2_CPHY_RX_CLK>, 3925 <&camcc CAMCC_IFE_LITE_2_CSID_CLK>, 3926 <&camcc CAMCC_IFE_LITE_3_CLK>, 3927 <&camcc CAMCC_IFE_LITE_3_CPHY_RX_CLK>, 3928 <&camcc CAMCC_IFE_LITE_3_CSID_CLK>, 3929 <&gcc GCC_CAMERA_HF_AXI_CLK>, 3930 <&gcc GCC_CAMERA_SF_AXI_CLK>; 3931 clock-names = "camnoc_axi", 3932 "cpas_ahb", 3933 "csiphy0", 3934 "csiphy0_timer", 3935 "csiphy1", 3936 "csiphy1_timer", 3937 "csiphy2", 3938 "csiphy2_timer", 3939 "csiphy3", 3940 "csiphy3_timer", 3941 "vfe0_axi", 3942 "vfe0", 3943 "vfe0_cphy_rx", 3944 "vfe0_csid", 3945 "vfe1_axi", 3946 "vfe1", 3947 "vfe1_cphy_rx", 3948 "vfe1_csid", 3949 "vfe2_axi", 3950 "vfe2", 3951 "vfe2_cphy_rx", 3952 "vfe2_csid", 3953 "vfe3_axi", 3954 "vfe3", 3955 "vfe3_cphy_rx", 3956 "vfe3_csid", 3957 "vfe_lite0", 3958 "vfe_lite0_cphy_rx", 3959 "vfe_lite0_csid", 3960 "vfe_lite1", 3961 "vfe_lite1_cphy_rx", 3962 "vfe_lite1_csid", 3963 "vfe_lite2", 3964 "vfe_lite2_cphy_rx", 3965 "vfe_lite2_csid", 3966 "vfe_lite3", 3967 "vfe_lite3_cphy_rx", 3968 "vfe_lite3_csid", 3969 "gcc_axi_hf", 3970 "gcc_axi_sf"; 3971 3972 iommus = <&apps_smmu 0x2000 0x4e0>, 3973 <&apps_smmu 0x2020 0x4e0>, 3974 <&apps_smmu 0x2040 0x4e0>, 3975 <&apps_smmu 0x2060 0x4e0>, 3976 <&apps_smmu 0x2080 0x4e0>, 3977 <&apps_smmu 0x20e0 0x4e0>, 3978 <&apps_smmu 0x20c0 0x4e0>, 3979 <&apps_smmu 0x20a0 0x4e0>, 3980 <&apps_smmu 0x2400 0x4e0>, 3981 <&apps_smmu 0x2420 0x4e0>, 3982 <&apps_smmu 0x2440 0x4e0>, 3983 <&apps_smmu 0x2460 0x4e0>, 3984 <&apps_smmu 0x2480 0x4e0>, 3985 <&apps_smmu 0x24e0 0x4e0>, 3986 <&apps_smmu 0x24c0 0x4e0>, 3987 <&apps_smmu 0x24a0 0x4e0>; 3988 3989 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>, 3990 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>, 3991 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>, 3992 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>; 3993 interconnect-names = "cam_ahb", 3994 "cam_hf_mnoc", 3995 "cam_sf_mnoc", 3996 "cam_sf_icp_mnoc"; 3997 3998 status = "disabled"; 3999 4000 ports { 4001 #address-cells = <1>; 4002 #size-cells = <0>; 4003 4004 port@0 { 4005 reg = <0>; 4006 #address-cells = <1>; 4007 #size-cells = <0>; 4008 }; 4009 4010 port@1 { 4011 reg = <1>; 4012 #address-cells = <1>; 4013 #size-cells = <0>; 4014 }; 4015 4016 port@2 { 4017 reg = <2>; 4018 #address-cells = <1>; 4019 #size-cells = <0>; 4020 }; 4021 4022 port@3 { 4023 reg = <3>; 4024 #address-cells = <1>; 4025 #size-cells = <0>; 4026 }; 4027 }; 4028 }; 4029 4030 camcc: clock-controller@ad00000 { 4031 compatible = "qcom,sc8280xp-camcc"; 4032 reg = <0 0x0ad00000 0 0x20000>; 4033 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4034 <&rpmhcc RPMH_CXO_CLK>, 4035 <&rpmhcc RPMH_CXO_CLK_A>, 4036 <&sleep_clk>; 4037 power-domains = <&rpmhpd SC8280XP_MMCX>; 4038 required-opps = <&rpmhpd_opp_low_svs>; 4039 #clock-cells = <1>; 4040 #reset-cells = <1>; 4041 #power-domain-cells = <1>; 4042 }; 4043 4044 mdss0: display-subsystem@ae00000 { 4045 compatible = "qcom,sc8280xp-mdss"; 4046 reg = <0 0x0ae00000 0 0x1000>; 4047 reg-names = "mdss"; 4048 4049 clocks = <&gcc GCC_DISP_AHB_CLK>, 4050 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4051 <&dispcc0 DISP_CC_MDSS_MDP_CLK>; 4052 clock-names = "iface", 4053 "ahb", 4054 "core"; 4055 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4056 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 4057 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 4058 interconnect-names = "mdp0-mem", "mdp1-mem"; 4059 iommus = <&apps_smmu 0x1000 0x402>; 4060 power-domains = <&dispcc0 MDSS_GDSC>; 4061 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>; 4062 4063 interrupt-controller; 4064 #interrupt-cells = <1>; 4065 #address-cells = <2>; 4066 #size-cells = <2>; 4067 ranges; 4068 4069 status = "disabled"; 4070 4071 mdss0_mdp: display-controller@ae01000 { 4072 compatible = "qcom,sc8280xp-dpu"; 4073 reg = <0 0x0ae01000 0 0x8f000>, 4074 <0 0x0aeb0000 0 0x2008>; 4075 reg-names = "mdp", "vbif"; 4076 4077 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4078 <&gcc GCC_DISP_SF_AXI_CLK>, 4079 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4080 <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>, 4081 <&dispcc0 DISP_CC_MDSS_MDP_CLK>, 4082 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 4083 clock-names = "bus", 4084 "nrt_bus", 4085 "iface", 4086 "lut", 4087 "core", 4088 "vsync"; 4089 interrupt-parent = <&mdss0>; 4090 interrupts = <0>; 4091 power-domains = <&rpmhpd SC8280XP_MMCX>; 4092 4093 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 4094 assigned-clock-rates = <19200000>; 4095 operating-points-v2 = <&mdss0_mdp_opp_table>; 4096 4097 ports { 4098 #address-cells = <1>; 4099 #size-cells = <0>; 4100 4101 port@0 { 4102 reg = <0>; 4103 mdss0_intf0_out: endpoint { 4104 remote-endpoint = <&mdss0_dp0_in>; 4105 }; 4106 }; 4107 4108 port@4 { 4109 reg = <4>; 4110 mdss0_intf4_out: endpoint { 4111 remote-endpoint = <&mdss0_dp1_in>; 4112 }; 4113 }; 4114 4115 port@5 { 4116 reg = <5>; 4117 mdss0_intf5_out: endpoint { 4118 remote-endpoint = <&mdss0_dp3_in>; 4119 }; 4120 }; 4121 4122 port@6 { 4123 reg = <6>; 4124 mdss0_intf6_out: endpoint { 4125 remote-endpoint = <&mdss0_dp2_in>; 4126 }; 4127 }; 4128 }; 4129 4130 mdss0_mdp_opp_table: opp-table { 4131 compatible = "operating-points-v2"; 4132 4133 opp-200000000 { 4134 opp-hz = /bits/ 64 <200000000>; 4135 required-opps = <&rpmhpd_opp_low_svs>; 4136 }; 4137 4138 opp-300000000 { 4139 opp-hz = /bits/ 64 <300000000>; 4140 required-opps = <&rpmhpd_opp_svs>; 4141 }; 4142 4143 opp-375000000 { 4144 opp-hz = /bits/ 64 <375000000>; 4145 required-opps = <&rpmhpd_opp_svs_l1>; 4146 }; 4147 4148 opp-500000000 { 4149 opp-hz = /bits/ 64 <500000000>; 4150 required-opps = <&rpmhpd_opp_nom>; 4151 }; 4152 opp-600000000 { 4153 opp-hz = /bits/ 64 <600000000>; 4154 required-opps = <&rpmhpd_opp_turbo_l1>; 4155 }; 4156 }; 4157 }; 4158 4159 mdss0_dp0: displayport-controller@ae90000 { 4160 compatible = "qcom,sc8280xp-dp"; 4161 reg = <0 0xae90000 0 0x200>, 4162 <0 0xae90200 0 0x200>, 4163 <0 0xae90400 0 0x600>, 4164 <0 0xae91000 0 0x400>, 4165 <0 0xae91400 0 0x400>; 4166 interrupt-parent = <&mdss0>; 4167 interrupts = <12>; 4168 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4169 <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>, 4170 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>, 4171 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 4172 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 4173 clock-names = "core_iface", "core_aux", 4174 "ctrl_link", 4175 "ctrl_link_iface", 4176 "stream_pixel"; 4177 4178 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 4179 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 4180 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4181 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4182 4183 phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; 4184 phy-names = "dp"; 4185 4186 #sound-dai-cells = <0>; 4187 4188 operating-points-v2 = <&mdss0_dp0_opp_table>; 4189 power-domains = <&rpmhpd SC8280XP_MMCX>; 4190 4191 status = "disabled"; 4192 4193 ports { 4194 #address-cells = <1>; 4195 #size-cells = <0>; 4196 4197 port@0 { 4198 reg = <0>; 4199 4200 mdss0_dp0_in: endpoint { 4201 remote-endpoint = <&mdss0_intf0_out>; 4202 }; 4203 }; 4204 4205 port@1 { 4206 reg = <1>; 4207 4208 mdss0_dp0_out: endpoint { 4209 }; 4210 }; 4211 }; 4212 4213 mdss0_dp0_opp_table: opp-table { 4214 compatible = "operating-points-v2"; 4215 4216 opp-160000000 { 4217 opp-hz = /bits/ 64 <160000000>; 4218 required-opps = <&rpmhpd_opp_low_svs>; 4219 }; 4220 4221 opp-270000000 { 4222 opp-hz = /bits/ 64 <270000000>; 4223 required-opps = <&rpmhpd_opp_svs>; 4224 }; 4225 4226 opp-540000000 { 4227 opp-hz = /bits/ 64 <540000000>; 4228 required-opps = <&rpmhpd_opp_svs_l1>; 4229 }; 4230 4231 opp-810000000 { 4232 opp-hz = /bits/ 64 <810000000>; 4233 required-opps = <&rpmhpd_opp_nom>; 4234 }; 4235 }; 4236 }; 4237 4238 mdss0_dp1: displayport-controller@ae98000 { 4239 compatible = "qcom,sc8280xp-dp"; 4240 reg = <0 0xae98000 0 0x200>, 4241 <0 0xae98200 0 0x200>, 4242 <0 0xae98400 0 0x600>, 4243 <0 0xae99000 0 0x400>, 4244 <0 0xae99400 0 0x400>; 4245 interrupt-parent = <&mdss0>; 4246 interrupts = <13>; 4247 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4248 <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>, 4249 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>, 4250 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 4251 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 4252 clock-names = "core_iface", "core_aux", 4253 "ctrl_link", 4254 "ctrl_link_iface", "stream_pixel"; 4255 4256 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 4257 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 4258 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4259 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4260 4261 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 4262 phy-names = "dp"; 4263 4264 #sound-dai-cells = <0>; 4265 4266 operating-points-v2 = <&mdss0_dp1_opp_table>; 4267 power-domains = <&rpmhpd SC8280XP_MMCX>; 4268 4269 status = "disabled"; 4270 4271 ports { 4272 #address-cells = <1>; 4273 #size-cells = <0>; 4274 4275 port@0 { 4276 reg = <0>; 4277 4278 mdss0_dp1_in: endpoint { 4279 remote-endpoint = <&mdss0_intf4_out>; 4280 }; 4281 }; 4282 4283 port@1 { 4284 reg = <1>; 4285 4286 mdss0_dp1_out: endpoint { 4287 }; 4288 }; 4289 }; 4290 4291 mdss0_dp1_opp_table: opp-table { 4292 compatible = "operating-points-v2"; 4293 4294 opp-160000000 { 4295 opp-hz = /bits/ 64 <160000000>; 4296 required-opps = <&rpmhpd_opp_low_svs>; 4297 }; 4298 4299 opp-270000000 { 4300 opp-hz = /bits/ 64 <270000000>; 4301 required-opps = <&rpmhpd_opp_svs>; 4302 }; 4303 4304 opp-540000000 { 4305 opp-hz = /bits/ 64 <540000000>; 4306 required-opps = <&rpmhpd_opp_svs_l1>; 4307 }; 4308 4309 opp-810000000 { 4310 opp-hz = /bits/ 64 <810000000>; 4311 required-opps = <&rpmhpd_opp_nom>; 4312 }; 4313 }; 4314 }; 4315 4316 mdss0_dp2: displayport-controller@ae9a000 { 4317 compatible = "qcom,sc8280xp-dp"; 4318 reg = <0 0xae9a000 0 0x200>, 4319 <0 0xae9a200 0 0x200>, 4320 <0 0xae9a400 0 0x600>, 4321 <0 0xae9b000 0 0x400>, 4322 <0 0xae9b400 0 0x400>; 4323 4324 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4325 <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 4326 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>, 4327 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 4328 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; 4329 clock-names = "core_iface", "core_aux", 4330 "ctrl_link", 4331 "ctrl_link_iface", "stream_pixel"; 4332 interrupt-parent = <&mdss0>; 4333 interrupts = <14>; 4334 phys = <&mdss0_dp2_phy>; 4335 phy-names = "dp"; 4336 power-domains = <&rpmhpd SC8280XP_MMCX>; 4337 4338 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 4339 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 4340 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>; 4341 operating-points-v2 = <&mdss0_dp2_opp_table>; 4342 4343 #sound-dai-cells = <0>; 4344 4345 status = "disabled"; 4346 4347 ports { 4348 #address-cells = <1>; 4349 #size-cells = <0>; 4350 4351 port@0 { 4352 reg = <0>; 4353 mdss0_dp2_in: endpoint { 4354 remote-endpoint = <&mdss0_intf6_out>; 4355 }; 4356 }; 4357 4358 port@1 { 4359 reg = <1>; 4360 }; 4361 }; 4362 4363 mdss0_dp2_opp_table: opp-table { 4364 compatible = "operating-points-v2"; 4365 4366 opp-160000000 { 4367 opp-hz = /bits/ 64 <160000000>; 4368 required-opps = <&rpmhpd_opp_low_svs>; 4369 }; 4370 4371 opp-270000000 { 4372 opp-hz = /bits/ 64 <270000000>; 4373 required-opps = <&rpmhpd_opp_svs>; 4374 }; 4375 4376 opp-540000000 { 4377 opp-hz = /bits/ 64 <540000000>; 4378 required-opps = <&rpmhpd_opp_svs_l1>; 4379 }; 4380 4381 opp-810000000 { 4382 opp-hz = /bits/ 64 <810000000>; 4383 required-opps = <&rpmhpd_opp_nom>; 4384 }; 4385 }; 4386 }; 4387 4388 mdss0_dp3: displayport-controller@aea0000 { 4389 compatible = "qcom,sc8280xp-dp"; 4390 reg = <0 0xaea0000 0 0x200>, 4391 <0 0xaea0200 0 0x200>, 4392 <0 0xaea0400 0 0x600>, 4393 <0 0xaea1000 0 0x400>, 4394 <0 0xaea1400 0 0x400>; 4395 4396 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4397 <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 4398 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>, 4399 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 4400 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 4401 clock-names = "core_iface", "core_aux", 4402 "ctrl_link", 4403 "ctrl_link_iface", "stream_pixel"; 4404 interrupt-parent = <&mdss0>; 4405 interrupts = <15>; 4406 phys = <&mdss0_dp3_phy>; 4407 phy-names = "dp"; 4408 power-domains = <&rpmhpd SC8280XP_MMCX>; 4409 4410 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 4411 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 4412 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>; 4413 operating-points-v2 = <&mdss0_dp3_opp_table>; 4414 4415 #sound-dai-cells = <0>; 4416 4417 status = "disabled"; 4418 4419 ports { 4420 #address-cells = <1>; 4421 #size-cells = <0>; 4422 4423 port@0 { 4424 reg = <0>; 4425 mdss0_dp3_in: endpoint { 4426 remote-endpoint = <&mdss0_intf5_out>; 4427 }; 4428 }; 4429 4430 port@1 { 4431 reg = <1>; 4432 }; 4433 }; 4434 4435 mdss0_dp3_opp_table: opp-table { 4436 compatible = "operating-points-v2"; 4437 4438 opp-160000000 { 4439 opp-hz = /bits/ 64 <160000000>; 4440 required-opps = <&rpmhpd_opp_low_svs>; 4441 }; 4442 4443 opp-270000000 { 4444 opp-hz = /bits/ 64 <270000000>; 4445 required-opps = <&rpmhpd_opp_svs>; 4446 }; 4447 4448 opp-540000000 { 4449 opp-hz = /bits/ 64 <540000000>; 4450 required-opps = <&rpmhpd_opp_svs_l1>; 4451 }; 4452 4453 opp-810000000 { 4454 opp-hz = /bits/ 64 <810000000>; 4455 required-opps = <&rpmhpd_opp_nom>; 4456 }; 4457 }; 4458 }; 4459 }; 4460 4461 mdss0_dp2_phy: phy@aec2a00 { 4462 compatible = "qcom,sc8280xp-dp-phy"; 4463 reg = <0 0x0aec2a00 0 0x19c>, 4464 <0 0x0aec2200 0 0xec>, 4465 <0 0x0aec2600 0 0xec>, 4466 <0 0x0aec2000 0 0x1c8>; 4467 4468 clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 4469 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 4470 clock-names = "aux", "cfg_ahb"; 4471 power-domains = <&rpmhpd SC8280XP_MX>; 4472 4473 #clock-cells = <1>; 4474 #phy-cells = <0>; 4475 4476 status = "disabled"; 4477 }; 4478 4479 mdss0_dp3_phy: phy@aec5a00 { 4480 compatible = "qcom,sc8280xp-dp-phy"; 4481 reg = <0 0x0aec5a00 0 0x19c>, 4482 <0 0x0aec5200 0 0xec>, 4483 <0 0x0aec5600 0 0xec>, 4484 <0 0x0aec5000 0 0x1c8>; 4485 4486 clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 4487 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 4488 clock-names = "aux", "cfg_ahb"; 4489 power-domains = <&rpmhpd SC8280XP_MX>; 4490 4491 #clock-cells = <1>; 4492 #phy-cells = <0>; 4493 4494 status = "disabled"; 4495 }; 4496 4497 dispcc0: clock-controller@af00000 { 4498 compatible = "qcom,sc8280xp-dispcc0"; 4499 reg = <0 0x0af00000 0 0x20000>; 4500 4501 clocks = <&gcc GCC_DISP_AHB_CLK>, 4502 <&rpmhcc RPMH_CXO_CLK>, 4503 <&sleep_clk>, 4504 <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4505 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4506 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4507 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4508 <&mdss0_dp2_phy 0>, 4509 <&mdss0_dp2_phy 1>, 4510 <&mdss0_dp3_phy 0>, 4511 <&mdss0_dp3_phy 1>, 4512 <0>, 4513 <0>, 4514 <0>, 4515 <0>; 4516 power-domains = <&rpmhpd SC8280XP_MMCX>; 4517 4518 #clock-cells = <1>; 4519 #power-domain-cells = <1>; 4520 #reset-cells = <1>; 4521 4522 status = "disabled"; 4523 }; 4524 4525 pdc: interrupt-controller@b220000 { 4526 compatible = "qcom,sc8280xp-pdc", "qcom,pdc"; 4527 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 4528 qcom,pdc-ranges = <0 480 40>, 4529 <40 140 14>, 4530 <54 263 1>, 4531 <55 306 4>, 4532 <59 312 3>, 4533 <62 374 2>, 4534 <64 434 2>, 4535 <66 438 3>, 4536 <69 86 1>, 4537 <70 520 54>, 4538 <124 609 28>, 4539 <159 638 1>, 4540 <160 720 8>, 4541 <168 801 1>, 4542 <169 728 30>, 4543 <199 416 2>, 4544 <201 449 1>, 4545 <202 89 1>, 4546 <203 451 1>, 4547 <204 462 1>, 4548 <205 264 1>, 4549 <206 579 1>, 4550 <207 653 1>, 4551 <208 656 1>, 4552 <209 659 1>, 4553 <210 122 1>, 4554 <211 699 1>, 4555 <212 705 1>, 4556 <213 450 1>, 4557 <214 643 1>, 4558 <216 646 5>, 4559 <221 390 5>, 4560 <226 700 3>, 4561 <229 240 3>, 4562 <232 269 1>, 4563 <233 377 1>, 4564 <234 372 1>, 4565 <235 138 1>, 4566 <236 857 1>, 4567 <237 860 1>, 4568 <238 137 1>, 4569 <239 668 1>, 4570 <240 366 1>, 4571 <241 949 1>, 4572 <242 815 5>, 4573 <247 769 1>, 4574 <248 768 1>, 4575 <249 663 1>, 4576 <250 799 2>, 4577 <252 798 1>, 4578 <253 765 1>, 4579 <254 763 1>, 4580 <255 454 1>, 4581 <258 139 1>, 4582 <259 786 2>, 4583 <261 370 2>, 4584 <263 158 2>; 4585 #interrupt-cells = <2>; 4586 interrupt-parent = <&intc>; 4587 interrupt-controller; 4588 }; 4589 4590 tsens2: thermal-sensor@c251000 { 4591 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 4592 reg = <0 0x0c251000 0 0x1ff>, 4593 <0 0x0c224000 0 0x8>; 4594 #qcom,sensors = <11>; 4595 interrupts-extended = <&pdc 122 IRQ_TYPE_LEVEL_HIGH>, 4596 <&pdc 124 IRQ_TYPE_LEVEL_HIGH>; 4597 interrupt-names = "uplow", "critical"; 4598 #thermal-sensor-cells = <1>; 4599 }; 4600 4601 tsens3: thermal-sensor@c252000 { 4602 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 4603 reg = <0 0x0c252000 0 0x1ff>, 4604 <0 0x0c225000 0 0x8>; 4605 #qcom,sensors = <5>; 4606 interrupts-extended = <&pdc 123 IRQ_TYPE_LEVEL_HIGH>, 4607 <&pdc 125 IRQ_TYPE_LEVEL_HIGH>; 4608 interrupt-names = "uplow", "critical"; 4609 #thermal-sensor-cells = <1>; 4610 }; 4611 4612 tsens0: thermal-sensor@c263000 { 4613 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 4614 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4615 <0 0x0c222000 0 0x8>; /* SROT */ 4616 #qcom,sensors = <14>; 4617 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 4618 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 4619 interrupt-names = "uplow", "critical"; 4620 #thermal-sensor-cells = <1>; 4621 }; 4622 4623 restart@c264000 { 4624 compatible = "qcom,pshold"; 4625 reg = <0 0x0c264000 0 0x4>; 4626 }; 4627 4628 tsens1: thermal-sensor@c265000 { 4629 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 4630 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4631 <0 0x0c223000 0 0x8>; /* SROT */ 4632 #qcom,sensors = <16>; 4633 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 4634 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 4635 interrupt-names = "uplow", "critical"; 4636 #thermal-sensor-cells = <1>; 4637 }; 4638 4639 aoss_qmp: power-management@c300000 { 4640 compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp"; 4641 reg = <0 0x0c300000 0 0x400>; 4642 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; 4643 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 4644 4645 #clock-cells = <0>; 4646 }; 4647 4648 sram@c3f0000 { 4649 compatible = "qcom,rpmh-stats"; 4650 reg = <0 0x0c3f0000 0 0x400>; 4651 qcom,qmp = <&aoss_qmp>; 4652 }; 4653 4654 spmi_bus: spmi@c440000 { 4655 compatible = "qcom,spmi-pmic-arb"; 4656 reg = <0 0x0c440000 0 0x1100>, 4657 <0 0x0c600000 0 0x2000000>, 4658 <0 0x0e600000 0 0x100000>, 4659 <0 0x0e700000 0 0xa0000>, 4660 <0 0x0c40a000 0 0x26000>; 4661 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4662 interrupt-names = "periph_irq"; 4663 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4664 qcom,ee = <0>; 4665 qcom,channel = <0>; 4666 #address-cells = <2>; 4667 #size-cells = <0>; 4668 interrupt-controller; 4669 #interrupt-cells = <4>; 4670 }; 4671 4672 tlmm: pinctrl@f100000 { 4673 compatible = "qcom,sc8280xp-tlmm"; 4674 reg = <0 0x0f100000 0 0x300000>; 4675 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4676 gpio-controller; 4677 #gpio-cells = <2>; 4678 interrupt-controller; 4679 #interrupt-cells = <2>; 4680 gpio-ranges = <&tlmm 0 0 230>; 4681 wakeup-parent = <&pdc>; 4682 4683 cci0_default: cci0-default-state { 4684 cci0_i2c0_default: cci0-i2c0-default-pins { 4685 /* cci_i2c_sda0, cci_i2c_scl0 */ 4686 pins = "gpio113", "gpio114"; 4687 function = "cci_i2c"; 4688 drive-strength = <2>; 4689 bias-pull-up; 4690 }; 4691 4692 cci0_i2c1_default: cci0-i2c1-default-pins { 4693 /* cci_i2c_sda1, cci_i2c_scl1 */ 4694 pins = "gpio115", "gpio116"; 4695 function = "cci_i2c"; 4696 drive-strength = <2>; 4697 bias-pull-up; 4698 }; 4699 }; 4700 4701 cci0_sleep: cci0-sleep-state { 4702 cci0_i2c0_sleep: cci0-i2c0-sleep-pins { 4703 /* cci_i2c_sda0, cci_i2c_scl0 */ 4704 pins = "gpio113", "gpio114"; 4705 function = "cci_i2c"; 4706 drive-strength = <2>; 4707 bias-pull-down; 4708 }; 4709 4710 cci0_i2c1_sleep: cci0-i2c1-sleep-pins { 4711 /* cci_i2c_sda1, cci_i2c_scl1 */ 4712 pins = "gpio115", "gpio116"; 4713 function = "cci_i2c"; 4714 drive-strength = <2>; 4715 bias-pull-down; 4716 }; 4717 }; 4718 4719 cci1_default: cci1-default-state { 4720 cci1_i2c0_default: cci1-i2c0-default-pins { 4721 /* cci_i2c_sda2, cci_i2c_scl2 */ 4722 pins = "gpio10","gpio11"; 4723 function = "cci_i2c"; 4724 drive-strength = <2>; 4725 bias-pull-up; 4726 }; 4727 4728 cci1_i2c1_default: cci1-i2c1-default-pins { 4729 /* cci_i2c_sda3, cci_i2c_scl3 */ 4730 pins = "gpio123","gpio124"; 4731 function = "cci_i2c"; 4732 drive-strength = <2>; 4733 bias-pull-up; 4734 }; 4735 }; 4736 4737 cci1_sleep: cci1-sleep-state { 4738 cci1_i2c0_sleep: cci1-i2c0-sleep-pins { 4739 /* cci_i2c_sda2, cci_i2c_scl2 */ 4740 pins = "gpio10","gpio11"; 4741 function = "cci_i2c"; 4742 drive-strength = <2>; 4743 bias-pull-down; 4744 }; 4745 4746 cci1_i2c1_sleep: cci1-i2c1-sleep-pins { 4747 /* cci_i2c_sda3, cci_i2c_scl3 */ 4748 pins = "gpio123","gpio124"; 4749 function = "cci_i2c"; 4750 drive-strength = <2>; 4751 bias-pull-down; 4752 }; 4753 }; 4754 4755 cci2_default: cci2-default-state { 4756 cci2_i2c0_default: cci2-i2c0-default-pins { 4757 /* cci_i2c_sda4, cci_i2c_scl4 */ 4758 pins = "gpio117","gpio118"; 4759 function = "cci_i2c"; 4760 drive-strength = <2>; 4761 bias-pull-up; 4762 }; 4763 4764 cci2_i2c1_default: cci2-i2c1-default-pins { 4765 /* cci_i2c_sda5, cci_i2c_scl5 */ 4766 pins = "gpio12","gpio13"; 4767 function = "cci_i2c"; 4768 drive-strength = <2>; 4769 bias-pull-up; 4770 }; 4771 }; 4772 4773 cci2_sleep: cci2-sleep-state { 4774 cci2_i2c0_sleep: cci2-i2c0-sleep-pins { 4775 /* cci_i2c_sda4, cci_i2c_scl4 */ 4776 pins = "gpio117","gpio118"; 4777 function = "cci_i2c"; 4778 drive-strength = <2>; 4779 bias-pull-down; 4780 }; 4781 4782 cci2_i2c1_sleep: cci2-i2c1-sleep-pins { 4783 /* cci_i2c_sda5, cci_i2c_scl5 */ 4784 pins = "gpio12","gpio13"; 4785 function = "cci_i2c"; 4786 drive-strength = <2>; 4787 bias-pull-down; 4788 }; 4789 }; 4790 4791 cci3_default: cci3-default-state { 4792 cci3_i2c0_default: cci3-i2c0-default-pins { 4793 /* cci_i2c_sda6, cci_i2c_scl6 */ 4794 pins = "gpio145","gpio146"; 4795 function = "cci_i2c"; 4796 drive-strength = <2>; 4797 bias-pull-up; 4798 }; 4799 4800 cci3_i2c1_default: cci3-i2c1-default-pins { 4801 /* cci_i2c_sda7, cci_i2c_scl7 */ 4802 pins = "gpio164","gpio165"; 4803 function = "cci_i2c"; 4804 drive-strength = <2>; 4805 bias-pull-up; 4806 }; 4807 }; 4808 4809 cci3_sleep: cci3-sleep-state { 4810 cci3_i2c0_sleep: cci3-i2c0-sleep-pins { 4811 /* cci_i2c_sda6, cci_i2c_scl6 */ 4812 pins = "gpio145","gpio146"; 4813 function = "cci_i2c"; 4814 drive-strength = <2>; 4815 bias-pull-down; 4816 }; 4817 4818 cci3_i2c1_sleep: cci3-i2c1-sleep-pins { 4819 /* cci_i2c_sda7, cci_i2c_scl7 */ 4820 pins = "gpio164","gpio165"; 4821 function = "cci_i2c"; 4822 drive-strength = <2>; 4823 bias-pull-down; 4824 }; 4825 }; 4826 }; 4827 4828 apps_smmu: iommu@15000000 { 4829 compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500"; 4830 reg = <0 0x15000000 0 0x100000>; 4831 #iommu-cells = <2>; 4832 #global-interrupts = <2>; 4833 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 4834 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4835 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4836 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4837 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4838 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4839 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4840 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4841 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4842 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4843 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4844 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4845 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4846 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4847 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4848 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4849 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4850 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4851 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4852 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4853 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4854 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4855 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4856 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4857 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4858 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4859 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4860 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4861 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4862 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4863 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4864 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4865 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4866 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4867 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4868 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4869 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4870 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4871 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4872 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4873 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4874 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4875 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4876 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4877 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4878 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4879 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4880 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4881 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4882 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4883 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4884 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4885 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4886 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4887 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4888 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4889 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4890 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4891 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4892 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4893 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4894 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4895 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4896 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4897 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4898 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4899 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4900 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4901 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4902 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4903 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4904 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4905 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4906 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4907 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4908 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 4909 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4910 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4911 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 4912 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4913 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 4914 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4915 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4916 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 4917 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 4918 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 4919 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 4920 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 4921 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 4922 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 4923 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 4924 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 4925 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 4926 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 4927 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 4928 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 4929 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4930 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 4931 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 4932 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 4933 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 4934 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 4935 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 4936 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 4937 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 4938 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 4939 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 4940 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 4941 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 4942 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 4943 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 4944 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 4945 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 4946 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 4947 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 4948 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 4949 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 4950 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 4951 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 4952 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 4953 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 4954 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 4955 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 4956 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 4957 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 4958 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 4959 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 4960 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 4961 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>, 4962 <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>; 4963 }; 4964 4965 intc: interrupt-controller@17a00000 { 4966 compatible = "arm,gic-v3"; 4967 interrupt-controller; 4968 #interrupt-cells = <3>; 4969 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4970 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4971 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4972 #redistributor-regions = <1>; 4973 redistributor-stride = <0 0x20000>; 4974 4975 #address-cells = <2>; 4976 #size-cells = <2>; 4977 ranges; 4978 4979 its: msi-controller@17a40000 { 4980 compatible = "arm,gic-v3-its"; 4981 reg = <0 0x17a40000 0 0x20000>; 4982 msi-controller; 4983 #msi-cells = <1>; 4984 }; 4985 }; 4986 4987 watchdog@17c10000 { 4988 compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt"; 4989 reg = <0 0x17c10000 0 0x1000>; 4990 clocks = <&sleep_clk>; 4991 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 4992 }; 4993 4994 timer@17c20000 { 4995 compatible = "arm,armv7-timer-mem"; 4996 reg = <0x0 0x17c20000 0x0 0x1000>; 4997 #address-cells = <1>; 4998 #size-cells = <1>; 4999 ranges = <0x0 0x0 0x0 0x20000000>; 5000 5001 frame@17c21000 { 5002 frame-number = <0>; 5003 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5004 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5005 reg = <0x17c21000 0x1000>, 5006 <0x17c22000 0x1000>; 5007 }; 5008 5009 frame@17c23000 { 5010 frame-number = <1>; 5011 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5012 reg = <0x17c23000 0x1000>; 5013 status = "disabled"; 5014 }; 5015 5016 frame@17c25000 { 5017 frame-number = <2>; 5018 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5019 reg = <0x17c25000 0x1000>; 5020 status = "disabled"; 5021 }; 5022 5023 frame@17c27000 { 5024 frame-number = <3>; 5025 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5026 reg = <0x17c26000 0x1000>; 5027 status = "disabled"; 5028 }; 5029 5030 frame@17c29000 { 5031 frame-number = <4>; 5032 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5033 reg = <0x17c29000 0x1000>; 5034 status = "disabled"; 5035 }; 5036 5037 frame@17c2b000 { 5038 frame-number = <5>; 5039 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5040 reg = <0x17c2b000 0x1000>; 5041 status = "disabled"; 5042 }; 5043 5044 frame@17c2d000 { 5045 frame-number = <6>; 5046 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5047 reg = <0x17c2d000 0x1000>; 5048 status = "disabled"; 5049 }; 5050 }; 5051 5052 apps_rsc: rsc@18200000 { 5053 compatible = "qcom,rpmh-rsc"; 5054 reg = <0x0 0x18200000 0x0 0x10000>, 5055 <0x0 0x18210000 0x0 0x10000>, 5056 <0x0 0x18220000 0x0 0x10000>; 5057 reg-names = "drv-0", "drv-1", "drv-2"; 5058 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5059 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5060 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5061 qcom,tcs-offset = <0xd00>; 5062 qcom,drv-id = <2>; 5063 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 5064 <WAKE_TCS 3>, <CONTROL_TCS 1>; 5065 label = "apps_rsc"; 5066 power-domains = <&CLUSTER_PD>; 5067 5068 apps_bcm_voter: bcm-voter { 5069 compatible = "qcom,bcm-voter"; 5070 }; 5071 5072 rpmhcc: clock-controller { 5073 compatible = "qcom,sc8280xp-rpmh-clk"; 5074 #clock-cells = <1>; 5075 clock-names = "xo"; 5076 clocks = <&xo_board_clk>; 5077 }; 5078 5079 rpmhpd: power-controller { 5080 compatible = "qcom,sc8280xp-rpmhpd"; 5081 #power-domain-cells = <1>; 5082 operating-points-v2 = <&rpmhpd_opp_table>; 5083 5084 rpmhpd_opp_table: opp-table { 5085 compatible = "operating-points-v2"; 5086 5087 rpmhpd_opp_ret: opp1 { 5088 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5089 }; 5090 5091 rpmhpd_opp_min_svs: opp2 { 5092 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5093 }; 5094 5095 rpmhpd_opp_low_svs: opp3 { 5096 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5097 }; 5098 5099 rpmhpd_opp_svs: opp4 { 5100 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5101 }; 5102 5103 rpmhpd_opp_svs_l1: opp5 { 5104 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5105 }; 5106 5107 rpmhpd_opp_nom: opp6 { 5108 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5109 }; 5110 5111 rpmhpd_opp_nom_l1: opp7 { 5112 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5113 }; 5114 5115 rpmhpd_opp_nom_l2: opp8 { 5116 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5117 }; 5118 5119 rpmhpd_opp_turbo: opp9 { 5120 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5121 }; 5122 5123 rpmhpd_opp_turbo_l1: opp10 { 5124 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5125 }; 5126 }; 5127 }; 5128 }; 5129 5130 epss_l3: interconnect@18590000 { 5131 compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3"; 5132 reg = <0 0x18590000 0 0x1000>; 5133 5134 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5135 clock-names = "xo", "alternate"; 5136 5137 #interconnect-cells = <1>; 5138 }; 5139 5140 cpufreq_hw: cpufreq@18591000 { 5141 compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss"; 5142 reg = <0 0x18591000 0 0x1000>, 5143 <0 0x18592000 0 0x1000>; 5144 reg-names = "freq-domain0", "freq-domain1"; 5145 5146 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5147 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 5148 interrupt-names = "dcvsh-irq-0", 5149 "dcvsh-irq-1"; 5150 5151 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5152 clock-names = "xo", "alternate"; 5153 5154 #freq-domain-cells = <1>; 5155 #clock-cells = <1>; 5156 }; 5157 5158 remoteproc_nsp0: remoteproc@1b300000 { 5159 compatible = "qcom,sc8280xp-nsp0-pas"; 5160 reg = <0 0x1b300000 0 0x100>; 5161 5162 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 5163 <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>, 5164 <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>, 5165 <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>, 5166 <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>; 5167 interrupt-names = "wdog", "fatal", "ready", 5168 "handover", "stop-ack"; 5169 5170 clocks = <&rpmhcc RPMH_CXO_CLK>; 5171 clock-names = "xo"; 5172 5173 power-domains = <&rpmhpd SC8280XP_NSP>; 5174 power-domain-names = "nsp"; 5175 5176 memory-region = <&pil_nsp0_mem>; 5177 5178 qcom,smem-states = <&smp2p_nsp0_out 0>; 5179 qcom,smem-state-names = "stop"; 5180 5181 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 5182 5183 status = "disabled"; 5184 5185 glink-edge { 5186 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 5187 IPCC_MPROC_SIGNAL_GLINK_QMP 5188 IRQ_TYPE_EDGE_RISING>; 5189 mboxes = <&ipcc IPCC_CLIENT_CDSP 5190 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5191 5192 label = "nsp0"; 5193 qcom,remote-pid = <5>; 5194 5195 fastrpc { 5196 compatible = "qcom,fastrpc"; 5197 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5198 label = "cdsp"; 5199 #address-cells = <1>; 5200 #size-cells = <0>; 5201 5202 compute-cb@1 { 5203 compatible = "qcom,fastrpc-compute-cb"; 5204 reg = <1>; 5205 iommus = <&apps_smmu 0x3181 0x0420>; 5206 }; 5207 5208 compute-cb@2 { 5209 compatible = "qcom,fastrpc-compute-cb"; 5210 reg = <2>; 5211 iommus = <&apps_smmu 0x3182 0x0420>; 5212 }; 5213 5214 compute-cb@3 { 5215 compatible = "qcom,fastrpc-compute-cb"; 5216 reg = <3>; 5217 iommus = <&apps_smmu 0x3183 0x0420>; 5218 }; 5219 5220 compute-cb@4 { 5221 compatible = "qcom,fastrpc-compute-cb"; 5222 reg = <4>; 5223 iommus = <&apps_smmu 0x3184 0x0420>; 5224 }; 5225 5226 compute-cb@5 { 5227 compatible = "qcom,fastrpc-compute-cb"; 5228 reg = <5>; 5229 iommus = <&apps_smmu 0x3185 0x0420>; 5230 }; 5231 5232 compute-cb@6 { 5233 compatible = "qcom,fastrpc-compute-cb"; 5234 reg = <6>; 5235 iommus = <&apps_smmu 0x3186 0x0420>; 5236 }; 5237 5238 compute-cb@7 { 5239 compatible = "qcom,fastrpc-compute-cb"; 5240 reg = <7>; 5241 iommus = <&apps_smmu 0x3187 0x0420>; 5242 }; 5243 5244 compute-cb@8 { 5245 compatible = "qcom,fastrpc-compute-cb"; 5246 reg = <8>; 5247 iommus = <&apps_smmu 0x3188 0x0420>; 5248 }; 5249 5250 compute-cb@9 { 5251 compatible = "qcom,fastrpc-compute-cb"; 5252 reg = <9>; 5253 iommus = <&apps_smmu 0x318b 0x0420>; 5254 }; 5255 5256 compute-cb@10 { 5257 compatible = "qcom,fastrpc-compute-cb"; 5258 reg = <10>; 5259 iommus = <&apps_smmu 0x318b 0x0420>; 5260 }; 5261 5262 compute-cb@11 { 5263 compatible = "qcom,fastrpc-compute-cb"; 5264 reg = <11>; 5265 iommus = <&apps_smmu 0x318c 0x0420>; 5266 }; 5267 5268 compute-cb@12 { 5269 compatible = "qcom,fastrpc-compute-cb"; 5270 reg = <12>; 5271 iommus = <&apps_smmu 0x318d 0x0420>; 5272 }; 5273 5274 compute-cb@13 { 5275 compatible = "qcom,fastrpc-compute-cb"; 5276 reg = <13>; 5277 iommus = <&apps_smmu 0x318e 0x0420>; 5278 }; 5279 5280 compute-cb@14 { 5281 compatible = "qcom,fastrpc-compute-cb"; 5282 reg = <14>; 5283 iommus = <&apps_smmu 0x318f 0x0420>; 5284 }; 5285 }; 5286 }; 5287 }; 5288 5289 remoteproc_nsp1: remoteproc@21300000 { 5290 compatible = "qcom,sc8280xp-nsp1-pas"; 5291 reg = <0 0x21300000 0 0x100>; 5292 5293 interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_EDGE_RISING>, 5294 <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>, 5295 <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>, 5296 <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>, 5297 <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>; 5298 interrupt-names = "wdog", "fatal", "ready", 5299 "handover", "stop-ack"; 5300 5301 clocks = <&rpmhcc RPMH_CXO_CLK>; 5302 clock-names = "xo"; 5303 5304 power-domains = <&rpmhpd SC8280XP_NSP>; 5305 power-domain-names = "nsp"; 5306 5307 memory-region = <&pil_nsp1_mem>; 5308 5309 qcom,smem-states = <&smp2p_nsp1_out 0>; 5310 qcom,smem-state-names = "stop"; 5311 5312 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>; 5313 5314 status = "disabled"; 5315 5316 glink-edge { 5317 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 5318 IPCC_MPROC_SIGNAL_GLINK_QMP 5319 IRQ_TYPE_EDGE_RISING>; 5320 mboxes = <&ipcc IPCC_CLIENT_NSP1 5321 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5322 5323 label = "nsp1"; 5324 qcom,remote-pid = <12>; 5325 }; 5326 }; 5327 5328 mdss1: display-subsystem@22000000 { 5329 compatible = "qcom,sc8280xp-mdss"; 5330 reg = <0 0x22000000 0 0x1000>; 5331 reg-names = "mdss"; 5332 5333 clocks = <&gcc GCC_DISP_AHB_CLK>, 5334 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 5335 <&dispcc1 DISP_CC_MDSS_MDP_CLK>; 5336 clock-names = "iface", 5337 "ahb", 5338 "core"; 5339 interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>, 5340 <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>; 5341 interconnect-names = "mdp0-mem", "mdp1-mem"; 5342 interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; 5343 5344 iommus = <&apps_smmu 0x1800 0x402>; 5345 power-domains = <&dispcc1 MDSS_GDSC>; 5346 resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>; 5347 5348 interrupt-controller; 5349 #interrupt-cells = <1>; 5350 #address-cells = <2>; 5351 #size-cells = <2>; 5352 ranges; 5353 5354 status = "disabled"; 5355 5356 mdss1_mdp: display-controller@22001000 { 5357 compatible = "qcom,sc8280xp-dpu"; 5358 reg = <0 0x22001000 0 0x8f000>, 5359 <0 0x220b0000 0 0x2008>; 5360 reg-names = "mdp", "vbif"; 5361 5362 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 5363 <&gcc GCC_DISP_SF_AXI_CLK>, 5364 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 5365 <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>, 5366 <&dispcc1 DISP_CC_MDSS_MDP_CLK>, 5367 <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 5368 clock-names = "bus", 5369 "nrt_bus", 5370 "iface", 5371 "lut", 5372 "core", 5373 "vsync"; 5374 interrupt-parent = <&mdss1>; 5375 interrupts = <0>; 5376 power-domains = <&rpmhpd SC8280XP_MMCX>; 5377 5378 assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 5379 assigned-clock-rates = <19200000>; 5380 operating-points-v2 = <&mdss1_mdp_opp_table>; 5381 5382 ports { 5383 #address-cells = <1>; 5384 #size-cells = <0>; 5385 5386 port@0 { 5387 reg = <0>; 5388 mdss1_intf0_out: endpoint { 5389 remote-endpoint = <&mdss1_dp0_in>; 5390 }; 5391 }; 5392 5393 port@4 { 5394 reg = <4>; 5395 mdss1_intf4_out: endpoint { 5396 remote-endpoint = <&mdss1_dp1_in>; 5397 }; 5398 }; 5399 5400 port@5 { 5401 reg = <5>; 5402 mdss1_intf5_out: endpoint { 5403 remote-endpoint = <&mdss1_dp3_in>; 5404 }; 5405 }; 5406 5407 port@6 { 5408 reg = <6>; 5409 mdss1_intf6_out: endpoint { 5410 remote-endpoint = <&mdss1_dp2_in>; 5411 }; 5412 }; 5413 }; 5414 5415 mdss1_mdp_opp_table: opp-table { 5416 compatible = "operating-points-v2"; 5417 5418 opp-200000000 { 5419 opp-hz = /bits/ 64 <200000000>; 5420 required-opps = <&rpmhpd_opp_low_svs>; 5421 }; 5422 5423 opp-300000000 { 5424 opp-hz = /bits/ 64 <300000000>; 5425 required-opps = <&rpmhpd_opp_svs>; 5426 }; 5427 5428 opp-375000000 { 5429 opp-hz = /bits/ 64 <375000000>; 5430 required-opps = <&rpmhpd_opp_svs_l1>; 5431 }; 5432 5433 opp-500000000 { 5434 opp-hz = /bits/ 64 <500000000>; 5435 required-opps = <&rpmhpd_opp_nom>; 5436 }; 5437 opp-600000000 { 5438 opp-hz = /bits/ 64 <600000000>; 5439 required-opps = <&rpmhpd_opp_turbo_l1>; 5440 }; 5441 }; 5442 }; 5443 5444 mdss1_dp0: displayport-controller@22090000 { 5445 compatible = "qcom,sc8280xp-dp"; 5446 reg = <0 0x22090000 0 0x200>, 5447 <0 0x22090200 0 0x200>, 5448 <0 0x22090400 0 0x600>, 5449 <0 0x22091000 0 0x400>, 5450 <0 0x22091400 0 0x400>; 5451 5452 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 5453 <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 5454 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>, 5455 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 5456 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 5457 clock-names = "core_iface", "core_aux", 5458 "ctrl_link", 5459 "ctrl_link_iface", "stream_pixel"; 5460 interrupt-parent = <&mdss1>; 5461 interrupts = <12>; 5462 phys = <&mdss1_dp0_phy>; 5463 phy-names = "dp"; 5464 power-domains = <&rpmhpd SC8280XP_MMCX>; 5465 5466 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 5467 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 5468 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>; 5469 operating-points-v2 = <&mdss1_dp0_opp_table>; 5470 5471 #sound-dai-cells = <0>; 5472 5473 status = "disabled"; 5474 5475 ports { 5476 #address-cells = <1>; 5477 #size-cells = <0>; 5478 5479 port@0 { 5480 reg = <0>; 5481 mdss1_dp0_in: endpoint { 5482 remote-endpoint = <&mdss1_intf0_out>; 5483 }; 5484 }; 5485 5486 port@1 { 5487 reg = <1>; 5488 }; 5489 }; 5490 5491 mdss1_dp0_opp_table: opp-table { 5492 compatible = "operating-points-v2"; 5493 5494 opp-160000000 { 5495 opp-hz = /bits/ 64 <160000000>; 5496 required-opps = <&rpmhpd_opp_low_svs>; 5497 }; 5498 5499 opp-270000000 { 5500 opp-hz = /bits/ 64 <270000000>; 5501 required-opps = <&rpmhpd_opp_svs>; 5502 }; 5503 5504 opp-540000000 { 5505 opp-hz = /bits/ 64 <540000000>; 5506 required-opps = <&rpmhpd_opp_svs_l1>; 5507 }; 5508 5509 opp-810000000 { 5510 opp-hz = /bits/ 64 <810000000>; 5511 required-opps = <&rpmhpd_opp_nom>; 5512 }; 5513 }; 5514 }; 5515 5516 mdss1_dp1: displayport-controller@22098000 { 5517 compatible = "qcom,sc8280xp-dp"; 5518 reg = <0 0x22098000 0 0x200>, 5519 <0 0x22098200 0 0x200>, 5520 <0 0x22098400 0 0x600>, 5521 <0 0x22099000 0 0x400>, 5522 <0 0x22099400 0 0x400>; 5523 5524 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 5525 <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 5526 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>, 5527 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 5528 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 5529 clock-names = "core_iface", "core_aux", 5530 "ctrl_link", 5531 "ctrl_link_iface", "stream_pixel"; 5532 interrupt-parent = <&mdss1>; 5533 interrupts = <13>; 5534 phys = <&mdss1_dp1_phy>; 5535 phy-names = "dp"; 5536 power-domains = <&rpmhpd SC8280XP_MMCX>; 5537 5538 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 5539 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 5540 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>; 5541 operating-points-v2 = <&mdss1_dp1_opp_table>; 5542 5543 #sound-dai-cells = <0>; 5544 5545 status = "disabled"; 5546 5547 ports { 5548 #address-cells = <1>; 5549 #size-cells = <0>; 5550 5551 port@0 { 5552 reg = <0>; 5553 mdss1_dp1_in: endpoint { 5554 remote-endpoint = <&mdss1_intf4_out>; 5555 }; 5556 }; 5557 5558 port@1 { 5559 reg = <1>; 5560 }; 5561 }; 5562 5563 mdss1_dp1_opp_table: opp-table { 5564 compatible = "operating-points-v2"; 5565 5566 opp-160000000 { 5567 opp-hz = /bits/ 64 <160000000>; 5568 required-opps = <&rpmhpd_opp_low_svs>; 5569 }; 5570 5571 opp-270000000 { 5572 opp-hz = /bits/ 64 <270000000>; 5573 required-opps = <&rpmhpd_opp_svs>; 5574 }; 5575 5576 opp-540000000 { 5577 opp-hz = /bits/ 64 <540000000>; 5578 required-opps = <&rpmhpd_opp_svs_l1>; 5579 }; 5580 5581 opp-810000000 { 5582 opp-hz = /bits/ 64 <810000000>; 5583 required-opps = <&rpmhpd_opp_nom>; 5584 }; 5585 }; 5586 }; 5587 5588 mdss1_dp2: displayport-controller@2209a000 { 5589 compatible = "qcom,sc8280xp-dp"; 5590 reg = <0 0x2209a000 0 0x200>, 5591 <0 0x2209a200 0 0x200>, 5592 <0 0x2209a400 0 0x600>, 5593 <0 0x2209b000 0 0x400>, 5594 <0 0x2209b400 0 0x400>; 5595 5596 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 5597 <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 5598 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>, 5599 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 5600 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; 5601 clock-names = "core_iface", "core_aux", 5602 "ctrl_link", 5603 "ctrl_link_iface", "stream_pixel"; 5604 interrupt-parent = <&mdss1>; 5605 interrupts = <14>; 5606 phys = <&mdss1_dp2_phy>; 5607 phy-names = "dp"; 5608 power-domains = <&rpmhpd SC8280XP_MMCX>; 5609 5610 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 5611 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 5612 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>; 5613 operating-points-v2 = <&mdss1_dp2_opp_table>; 5614 5615 #sound-dai-cells = <0>; 5616 5617 status = "disabled"; 5618 5619 ports { 5620 #address-cells = <1>; 5621 #size-cells = <0>; 5622 5623 port@0 { 5624 reg = <0>; 5625 mdss1_dp2_in: endpoint { 5626 remote-endpoint = <&mdss1_intf6_out>; 5627 }; 5628 }; 5629 5630 port@1 { 5631 reg = <1>; 5632 }; 5633 }; 5634 5635 mdss1_dp2_opp_table: opp-table { 5636 compatible = "operating-points-v2"; 5637 5638 opp-160000000 { 5639 opp-hz = /bits/ 64 <160000000>; 5640 required-opps = <&rpmhpd_opp_low_svs>; 5641 }; 5642 5643 opp-270000000 { 5644 opp-hz = /bits/ 64 <270000000>; 5645 required-opps = <&rpmhpd_opp_svs>; 5646 }; 5647 5648 opp-540000000 { 5649 opp-hz = /bits/ 64 <540000000>; 5650 required-opps = <&rpmhpd_opp_svs_l1>; 5651 }; 5652 5653 opp-810000000 { 5654 opp-hz = /bits/ 64 <810000000>; 5655 required-opps = <&rpmhpd_opp_nom>; 5656 }; 5657 }; 5658 }; 5659 5660 mdss1_dp3: displayport-controller@220a0000 { 5661 compatible = "qcom,sc8280xp-dp"; 5662 reg = <0 0x220a0000 0 0x200>, 5663 <0 0x220a0200 0 0x200>, 5664 <0 0x220a0400 0 0x600>, 5665 <0 0x220a1000 0 0x400>, 5666 <0 0x220a1400 0 0x400>; 5667 5668 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 5669 <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 5670 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK>, 5671 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 5672 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 5673 clock-names = "core_iface", "core_aux", 5674 "ctrl_link", 5675 "ctrl_link_iface", "stream_pixel"; 5676 interrupt-parent = <&mdss1>; 5677 interrupts = <15>; 5678 phys = <&mdss1_dp3_phy>; 5679 phy-names = "dp"; 5680 power-domains = <&rpmhpd SC8280XP_MMCX>; 5681 5682 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 5683 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 5684 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>; 5685 operating-points-v2 = <&mdss1_dp3_opp_table>; 5686 5687 #sound-dai-cells = <0>; 5688 5689 status = "disabled"; 5690 5691 ports { 5692 #address-cells = <1>; 5693 #size-cells = <0>; 5694 5695 port@0 { 5696 reg = <0>; 5697 mdss1_dp3_in: endpoint { 5698 remote-endpoint = <&mdss1_intf5_out>; 5699 }; 5700 }; 5701 5702 port@1 { 5703 reg = <1>; 5704 }; 5705 }; 5706 5707 mdss1_dp3_opp_table: opp-table { 5708 compatible = "operating-points-v2"; 5709 5710 opp-160000000 { 5711 opp-hz = /bits/ 64 <160000000>; 5712 required-opps = <&rpmhpd_opp_low_svs>; 5713 }; 5714 5715 opp-270000000 { 5716 opp-hz = /bits/ 64 <270000000>; 5717 required-opps = <&rpmhpd_opp_svs>; 5718 }; 5719 5720 opp-540000000 { 5721 opp-hz = /bits/ 64 <540000000>; 5722 required-opps = <&rpmhpd_opp_svs_l1>; 5723 }; 5724 5725 opp-810000000 { 5726 opp-hz = /bits/ 64 <810000000>; 5727 required-opps = <&rpmhpd_opp_nom>; 5728 }; 5729 }; 5730 }; 5731 }; 5732 5733 mdss1_dp2_phy: phy@220c2a00 { 5734 compatible = "qcom,sc8280xp-dp-phy"; 5735 reg = <0 0x220c2a00 0 0x19c>, 5736 <0 0x220c2200 0 0xec>, 5737 <0 0x220c2600 0 0xec>, 5738 <0 0x220c2000 0 0x1c8>; 5739 5740 clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 5741 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 5742 clock-names = "aux", "cfg_ahb"; 5743 power-domains = <&rpmhpd SC8280XP_MX>; 5744 5745 #clock-cells = <1>; 5746 #phy-cells = <0>; 5747 5748 status = "disabled"; 5749 }; 5750 5751 mdss1_dp3_phy: phy@220c5a00 { 5752 compatible = "qcom,sc8280xp-dp-phy"; 5753 reg = <0 0x220c5a00 0 0x19c>, 5754 <0 0x220c5200 0 0xec>, 5755 <0 0x220c5600 0 0xec>, 5756 <0 0x220c5000 0 0x1c8>; 5757 5758 clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 5759 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 5760 clock-names = "aux", "cfg_ahb"; 5761 power-domains = <&rpmhpd SC8280XP_MX>; 5762 5763 #clock-cells = <1>; 5764 #phy-cells = <0>; 5765 5766 status = "disabled"; 5767 }; 5768 5769 dispcc1: clock-controller@22100000 { 5770 compatible = "qcom,sc8280xp-dispcc1"; 5771 reg = <0 0x22100000 0 0x20000>; 5772 5773 clocks = <&gcc GCC_DISP_AHB_CLK>, 5774 <&rpmhcc RPMH_CXO_CLK>, 5775 <0>, 5776 <&mdss1_dp0_phy 0>, 5777 <&mdss1_dp0_phy 1>, 5778 <&mdss1_dp1_phy 0>, 5779 <&mdss1_dp1_phy 1>, 5780 <&mdss1_dp2_phy 0>, 5781 <&mdss1_dp2_phy 1>, 5782 <&mdss1_dp3_phy 0>, 5783 <&mdss1_dp3_phy 1>, 5784 <0>, 5785 <0>, 5786 <0>, 5787 <0>; 5788 power-domains = <&rpmhpd SC8280XP_MMCX>; 5789 5790 #clock-cells = <1>; 5791 #power-domain-cells = <1>; 5792 #reset-cells = <1>; 5793 5794 status = "disabled"; 5795 }; 5796 5797 ethernet1: ethernet@23000000 { 5798 compatible = "qcom,sc8280xp-ethqos"; 5799 reg = <0x0 0x23000000 0x0 0x10000>, 5800 <0x0 0x23016000 0x0 0x100>; 5801 reg-names = "stmmaceth", "rgmii"; 5802 5803 clocks = <&gcc GCC_EMAC1_AXI_CLK>, 5804 <&gcc GCC_EMAC1_SLV_AHB_CLK>, 5805 <&gcc GCC_EMAC1_PTP_CLK>, 5806 <&gcc GCC_EMAC1_RGMII_CLK>; 5807 clock-names = "stmmaceth", 5808 "pclk", 5809 "ptp_ref", 5810 "rgmii"; 5811 5812 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, 5813 <GIC_SPI 919 IRQ_TYPE_LEVEL_HIGH>; 5814 interrupt-names = "macirq", "eth_lpi"; 5815 5816 iommus = <&apps_smmu 0x40 0xf>; 5817 power-domains = <&gcc EMAC_1_GDSC>; 5818 5819 snps,tso; 5820 snps,pbl = <32>; 5821 rx-fifo-depth = <4096>; 5822 tx-fifo-depth = <4096>; 5823 5824 status = "disabled"; 5825 }; 5826 }; 5827 5828 sound: sound { 5829 }; 5830 5831 thermal-zones { 5832 cpu0-thermal { 5833 polling-delay-passive = <250>; 5834 polling-delay = <1000>; 5835 5836 thermal-sensors = <&tsens0 1>; 5837 5838 trips { 5839 cpu-crit { 5840 temperature = <110000>; 5841 hysteresis = <1000>; 5842 type = "critical"; 5843 }; 5844 }; 5845 }; 5846 5847 cpu1-thermal { 5848 polling-delay-passive = <250>; 5849 polling-delay = <1000>; 5850 5851 thermal-sensors = <&tsens0 2>; 5852 5853 trips { 5854 cpu-crit { 5855 temperature = <110000>; 5856 hysteresis = <1000>; 5857 type = "critical"; 5858 }; 5859 }; 5860 }; 5861 5862 cpu2-thermal { 5863 polling-delay-passive = <250>; 5864 polling-delay = <1000>; 5865 5866 thermal-sensors = <&tsens0 3>; 5867 5868 trips { 5869 cpu-crit { 5870 temperature = <110000>; 5871 hysteresis = <1000>; 5872 type = "critical"; 5873 }; 5874 }; 5875 }; 5876 5877 cpu3-thermal { 5878 polling-delay-passive = <250>; 5879 polling-delay = <1000>; 5880 5881 thermal-sensors = <&tsens0 4>; 5882 5883 trips { 5884 cpu-crit { 5885 temperature = <110000>; 5886 hysteresis = <1000>; 5887 type = "critical"; 5888 }; 5889 }; 5890 }; 5891 5892 cpu4-thermal { 5893 polling-delay-passive = <250>; 5894 polling-delay = <1000>; 5895 5896 thermal-sensors = <&tsens0 5>; 5897 5898 trips { 5899 cpu-crit { 5900 temperature = <110000>; 5901 hysteresis = <1000>; 5902 type = "critical"; 5903 }; 5904 }; 5905 }; 5906 5907 cpu5-thermal { 5908 polling-delay-passive = <250>; 5909 polling-delay = <1000>; 5910 5911 thermal-sensors = <&tsens0 6>; 5912 5913 trips { 5914 cpu-crit { 5915 temperature = <110000>; 5916 hysteresis = <1000>; 5917 type = "critical"; 5918 }; 5919 }; 5920 }; 5921 5922 cpu6-thermal { 5923 polling-delay-passive = <250>; 5924 polling-delay = <1000>; 5925 5926 thermal-sensors = <&tsens0 7>; 5927 5928 trips { 5929 cpu-crit { 5930 temperature = <110000>; 5931 hysteresis = <1000>; 5932 type = "critical"; 5933 }; 5934 }; 5935 }; 5936 5937 cpu7-thermal { 5938 polling-delay-passive = <250>; 5939 polling-delay = <1000>; 5940 5941 thermal-sensors = <&tsens0 8>; 5942 5943 trips { 5944 cpu-crit { 5945 temperature = <110000>; 5946 hysteresis = <1000>; 5947 type = "critical"; 5948 }; 5949 }; 5950 }; 5951 5952 cluster0-thermal { 5953 polling-delay-passive = <250>; 5954 polling-delay = <1000>; 5955 5956 thermal-sensors = <&tsens0 9>; 5957 5958 trips { 5959 cpu-crit { 5960 temperature = <110000>; 5961 hysteresis = <1000>; 5962 type = "critical"; 5963 }; 5964 }; 5965 }; 5966 5967 gpu-thermal { 5968 polling-delay-passive = <0>; 5969 polling-delay = <0>; 5970 5971 thermal-sensors = <&tsens2 2>; 5972 5973 trips { 5974 gpu-crit { 5975 temperature = <110000>; 5976 hysteresis = <1000>; 5977 type = "critical"; 5978 }; 5979 }; 5980 }; 5981 5982 mem-thermal { 5983 polling-delay-passive = <250>; 5984 polling-delay = <1000>; 5985 5986 thermal-sensors = <&tsens1 15>; 5987 5988 trips { 5989 trip-point0 { 5990 temperature = <90000>; 5991 hysteresis = <2000>; 5992 type = "hot"; 5993 }; 5994 }; 5995 }; 5996 }; 5997 5998 timer { 5999 compatible = "arm,armv8-timer"; 6000 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6001 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6002 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6003 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 6004 }; 6005}; 6006