1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2020-2023, Linaro Limited 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 9#include <dt-bindings/clock/qcom,gcc-sc8180x.h> 10#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/clock/qcom,sc8180x-camcc.h> 13#include <dt-bindings/clock/qcom,videocc-sm8150.h> 14#include <dt-bindings/interconnect/qcom,icc.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,sc8180x.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/phy/phy-qcom-qmp.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/thermal/thermal.h> 22 23/ { 24 interrupt-parent = <&intc>; 25 26 #address-cells = <2>; 27 #size-cells = <2>; 28 29 clocks { 30 xo_board_clk: xo-board { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <38400000>; 34 }; 35 36 sleep_clk: sleep-clk { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <32764>; 40 clock-output-names = "sleep_clk"; 41 }; 42 }; 43 44 cpus { 45 #address-cells = <2>; 46 #size-cells = <0>; 47 48 cpu0: cpu@0 { 49 device_type = "cpu"; 50 compatible = "qcom,kryo485"; 51 reg = <0x0 0x0>; 52 enable-method = "psci"; 53 capacity-dmips-mhz = <602>; 54 next-level-cache = <&l2_0>; 55 qcom,freq-domain = <&cpufreq_hw 0>; 56 operating-points-v2 = <&cpu0_opp_table>; 57 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 58 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 59 power-domains = <&cpu_pd0>; 60 power-domain-names = "psci"; 61 #cooling-cells = <2>; 62 clocks = <&cpufreq_hw 0>; 63 64 l2_0: l2-cache { 65 compatible = "cache"; 66 cache-level = <2>; 67 cache-unified; 68 next-level-cache = <&l3_0>; 69 l3_0: l3-cache { 70 compatible = "cache"; 71 cache-level = <3>; 72 cache-unified; 73 }; 74 }; 75 }; 76 77 cpu1: cpu@100 { 78 device_type = "cpu"; 79 compatible = "qcom,kryo485"; 80 reg = <0x0 0x100>; 81 enable-method = "psci"; 82 capacity-dmips-mhz = <602>; 83 next-level-cache = <&l2_100>; 84 qcom,freq-domain = <&cpufreq_hw 0>; 85 operating-points-v2 = <&cpu0_opp_table>; 86 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 87 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 88 power-domains = <&cpu_pd1>; 89 power-domain-names = "psci"; 90 #cooling-cells = <2>; 91 clocks = <&cpufreq_hw 0>; 92 93 l2_100: l2-cache { 94 compatible = "cache"; 95 cache-level = <2>; 96 cache-unified; 97 next-level-cache = <&l3_0>; 98 }; 99 100 }; 101 102 cpu2: cpu@200 { 103 device_type = "cpu"; 104 compatible = "qcom,kryo485"; 105 reg = <0x0 0x200>; 106 enable-method = "psci"; 107 capacity-dmips-mhz = <602>; 108 next-level-cache = <&l2_200>; 109 qcom,freq-domain = <&cpufreq_hw 0>; 110 operating-points-v2 = <&cpu0_opp_table>; 111 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 112 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 113 power-domains = <&cpu_pd2>; 114 power-domain-names = "psci"; 115 #cooling-cells = <2>; 116 clocks = <&cpufreq_hw 0>; 117 118 l2_200: l2-cache { 119 compatible = "cache"; 120 cache-level = <2>; 121 cache-unified; 122 next-level-cache = <&l3_0>; 123 }; 124 }; 125 126 cpu3: cpu@300 { 127 device_type = "cpu"; 128 compatible = "qcom,kryo485"; 129 reg = <0x0 0x300>; 130 enable-method = "psci"; 131 capacity-dmips-mhz = <602>; 132 next-level-cache = <&l2_300>; 133 qcom,freq-domain = <&cpufreq_hw 0>; 134 operating-points-v2 = <&cpu0_opp_table>; 135 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 136 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 137 power-domains = <&cpu_pd3>; 138 power-domain-names = "psci"; 139 #cooling-cells = <2>; 140 clocks = <&cpufreq_hw 0>; 141 142 l2_300: l2-cache { 143 compatible = "cache"; 144 cache-unified; 145 cache-level = <2>; 146 next-level-cache = <&l3_0>; 147 }; 148 }; 149 150 cpu4: cpu@400 { 151 device_type = "cpu"; 152 compatible = "qcom,kryo485"; 153 reg = <0x0 0x400>; 154 enable-method = "psci"; 155 capacity-dmips-mhz = <1024>; 156 next-level-cache = <&l2_400>; 157 qcom,freq-domain = <&cpufreq_hw 1>; 158 operating-points-v2 = <&cpu4_opp_table>; 159 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 160 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 161 power-domains = <&cpu_pd4>; 162 power-domain-names = "psci"; 163 #cooling-cells = <2>; 164 clocks = <&cpufreq_hw 1>; 165 166 l2_400: l2-cache { 167 compatible = "cache"; 168 cache-unified; 169 cache-level = <2>; 170 next-level-cache = <&l3_0>; 171 }; 172 }; 173 174 cpu5: cpu@500 { 175 device_type = "cpu"; 176 compatible = "qcom,kryo485"; 177 reg = <0x0 0x500>; 178 enable-method = "psci"; 179 capacity-dmips-mhz = <1024>; 180 next-level-cache = <&l2_500>; 181 qcom,freq-domain = <&cpufreq_hw 1>; 182 operating-points-v2 = <&cpu4_opp_table>; 183 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 184 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 185 power-domains = <&cpu_pd5>; 186 power-domain-names = "psci"; 187 #cooling-cells = <2>; 188 clocks = <&cpufreq_hw 1>; 189 190 l2_500: l2-cache { 191 compatible = "cache"; 192 cache-unified; 193 cache-level = <2>; 194 next-level-cache = <&l3_0>; 195 }; 196 }; 197 198 cpu6: cpu@600 { 199 device_type = "cpu"; 200 compatible = "qcom,kryo485"; 201 reg = <0x0 0x600>; 202 enable-method = "psci"; 203 capacity-dmips-mhz = <1024>; 204 next-level-cache = <&l2_600>; 205 qcom,freq-domain = <&cpufreq_hw 1>; 206 operating-points-v2 = <&cpu4_opp_table>; 207 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 208 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 209 power-domains = <&cpu_pd6>; 210 power-domain-names = "psci"; 211 #cooling-cells = <2>; 212 clocks = <&cpufreq_hw 1>; 213 214 l2_600: l2-cache { 215 compatible = "cache"; 216 cache-unified; 217 cache-level = <2>; 218 next-level-cache = <&l3_0>; 219 }; 220 }; 221 222 cpu7: cpu@700 { 223 device_type = "cpu"; 224 compatible = "qcom,kryo485"; 225 reg = <0x0 0x700>; 226 enable-method = "psci"; 227 capacity-dmips-mhz = <1024>; 228 next-level-cache = <&l2_700>; 229 qcom,freq-domain = <&cpufreq_hw 1>; 230 operating-points-v2 = <&cpu4_opp_table>; 231 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 232 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 233 power-domains = <&cpu_pd7>; 234 power-domain-names = "psci"; 235 #cooling-cells = <2>; 236 clocks = <&cpufreq_hw 1>; 237 238 l2_700: l2-cache { 239 compatible = "cache"; 240 cache-unified; 241 cache-level = <2>; 242 next-level-cache = <&l3_0>; 243 }; 244 }; 245 246 cpu-map { 247 cluster0 { 248 core0 { 249 cpu = <&cpu0>; 250 }; 251 252 core1 { 253 cpu = <&cpu1>; 254 }; 255 256 core2 { 257 cpu = <&cpu2>; 258 }; 259 260 core3 { 261 cpu = <&cpu3>; 262 }; 263 264 core4 { 265 cpu = <&cpu4>; 266 }; 267 268 core5 { 269 cpu = <&cpu5>; 270 }; 271 272 core6 { 273 cpu = <&cpu6>; 274 }; 275 276 core7 { 277 cpu = <&cpu7>; 278 }; 279 }; 280 }; 281 282 idle-states { 283 entry-method = "psci"; 284 285 little_cpu_sleep_0: cpu-sleep-0-0 { 286 compatible = "arm,idle-state"; 287 arm,psci-suspend-param = <0x40000004>; 288 entry-latency-us = <355>; 289 exit-latency-us = <909>; 290 min-residency-us = <3934>; 291 local-timer-stop; 292 }; 293 294 big_cpu_sleep_0: cpu-sleep-1-0 { 295 compatible = "arm,idle-state"; 296 arm,psci-suspend-param = <0x40000004>; 297 entry-latency-us = <2411>; 298 exit-latency-us = <1461>; 299 min-residency-us = <4488>; 300 local-timer-stop; 301 }; 302 }; 303 304 domain-idle-states { 305 cluster_sleep_apss_off: cluster-sleep-0 { 306 compatible = "domain-idle-state"; 307 arm,psci-suspend-param = <0x41000044>; 308 entry-latency-us = <3300>; 309 exit-latency-us = <3300>; 310 min-residency-us = <6000>; 311 }; 312 313 cluster_sleep_aoss_sleep: cluster-sleep-1 { 314 compatible = "domain-idle-state"; 315 arm,psci-suspend-param = <0x4100a344>; 316 entry-latency-us = <3263>; 317 exit-latency-us = <6562>; 318 min-residency-us = <9987>; 319 }; 320 }; 321 }; 322 323 cpu0_opp_table: opp-table-cpu0 { 324 compatible = "operating-points-v2"; 325 opp-shared; 326 327 opp-300000000 { 328 opp-hz = /bits/ 64 <300000000>; 329 opp-peak-kBps = <800000 9600000>; 330 }; 331 332 opp-422400000 { 333 opp-hz = /bits/ 64 <422400000>; 334 opp-peak-kBps = <800000 9600000>; 335 }; 336 337 opp-537600000 { 338 opp-hz = /bits/ 64 <537600000>; 339 opp-peak-kBps = <800000 12902400>; 340 }; 341 342 opp-652800000 { 343 opp-hz = /bits/ 64 <652800000>; 344 opp-peak-kBps = <800000 12902400>; 345 }; 346 347 opp-768000000 { 348 opp-hz = /bits/ 64 <768000000>; 349 opp-peak-kBps = <800000 15974400>; 350 }; 351 352 opp-883200000 { 353 opp-hz = /bits/ 64 <883200000>; 354 opp-peak-kBps = <1804000 19660800>; 355 }; 356 357 opp-998400000 { 358 opp-hz = /bits/ 64 <998400000>; 359 opp-peak-kBps = <1804000 19660800>; 360 }; 361 362 opp-1113600000 { 363 opp-hz = /bits/ 64 <1113600000>; 364 opp-peak-kBps = <1804000 22732800>; 365 }; 366 367 opp-1228800000 { 368 opp-hz = /bits/ 64 <1228800000>; 369 opp-peak-kBps = <1804000 22732800>; 370 }; 371 372 opp-1363200000 { 373 opp-hz = /bits/ 64 <1363200000>; 374 opp-peak-kBps = <2188000 25804800>; 375 }; 376 377 opp-1478400000 { 378 opp-hz = /bits/ 64 <1478400000>; 379 opp-peak-kBps = <2188000 31948800>; 380 }; 381 382 opp-1574400000 { 383 opp-hz = /bits/ 64 <1574400000>; 384 opp-peak-kBps = <3072000 31948800>; 385 }; 386 387 opp-1670400000 { 388 opp-hz = /bits/ 64 <1670400000>; 389 opp-peak-kBps = <3072000 31948800>; 390 }; 391 392 opp-1766400000 { 393 opp-hz = /bits/ 64 <1766400000>; 394 opp-peak-kBps = <3072000 31948800>; 395 }; 396 }; 397 398 cpu4_opp_table: opp-table-cpu4 { 399 compatible = "operating-points-v2"; 400 opp-shared; 401 402 opp-825600000 { 403 opp-hz = /bits/ 64 <825600000>; 404 opp-peak-kBps = <1804000 15974400>; 405 }; 406 407 opp-940800000 { 408 opp-hz = /bits/ 64 <940800000>; 409 opp-peak-kBps = <2188000 19660800>; 410 }; 411 412 opp-1056000000 { 413 opp-hz = /bits/ 64 <1056000000>; 414 opp-peak-kBps = <2188000 22732800>; 415 }; 416 417 opp-1171200000 { 418 opp-hz = /bits/ 64 <1171200000>; 419 opp-peak-kBps = <3072000 25804800>; 420 }; 421 422 opp-1286400000 { 423 opp-hz = /bits/ 64 <1286400000>; 424 opp-peak-kBps = <3072000 31948800>; 425 }; 426 427 opp-1420800000 { 428 opp-hz = /bits/ 64 <1420800000>; 429 opp-peak-kBps = <4068000 31948800>; 430 }; 431 432 opp-1536000000 { 433 opp-hz = /bits/ 64 <1536000000>; 434 opp-peak-kBps = <4068000 31948800>; 435 }; 436 437 opp-1651200000 { 438 opp-hz = /bits/ 64 <1651200000>; 439 opp-peak-kBps = <4068000 40550400>; 440 }; 441 442 opp-1766400000 { 443 opp-hz = /bits/ 64 <1766400000>; 444 opp-peak-kBps = <4068000 40550400>; 445 }; 446 447 opp-1881600000 { 448 opp-hz = /bits/ 64 <1881600000>; 449 opp-peak-kBps = <4068000 43008000>; 450 }; 451 452 opp-1996800000 { 453 opp-hz = /bits/ 64 <1996800000>; 454 opp-peak-kBps = <6220000 43008000>; 455 }; 456 457 opp-2131200000 { 458 opp-hz = /bits/ 64 <2131200000>; 459 opp-peak-kBps = <6220000 49152000>; 460 }; 461 462 opp-2246400000 { 463 opp-hz = /bits/ 64 <2246400000>; 464 opp-peak-kBps = <7216000 49152000>; 465 }; 466 467 opp-2361600000 { 468 opp-hz = /bits/ 64 <2361600000>; 469 opp-peak-kBps = <8368000 49152000>; 470 }; 471 472 opp-2457600000 { 473 opp-hz = /bits/ 64 <2457600000>; 474 opp-peak-kBps = <8368000 51609600>; 475 }; 476 477 opp-2553600000 { 478 opp-hz = /bits/ 64 <2553600000>; 479 opp-peak-kBps = <8368000 51609600>; 480 }; 481 482 opp-2649600000 { 483 opp-hz = /bits/ 64 <2649600000>; 484 opp-peak-kBps = <8368000 51609600>; 485 }; 486 487 opp-2745600000 { 488 opp-hz = /bits/ 64 <2745600000>; 489 opp-peak-kBps = <8368000 51609600>; 490 }; 491 492 opp-2841600000 { 493 opp-hz = /bits/ 64 <2841600000>; 494 opp-peak-kBps = <8368000 51609600>; 495 }; 496 497 opp-2918400000 { 498 opp-hz = /bits/ 64 <2918400000>; 499 opp-peak-kBps = <8368000 51609600>; 500 }; 501 502 opp-2995200000 { 503 opp-hz = /bits/ 64 <2995200000>; 504 opp-peak-kBps = <8368000 51609600>; 505 }; 506 }; 507 508 firmware { 509 scm: scm { 510 compatible = "qcom,scm-sc8180x", "qcom,scm"; 511 }; 512 }; 513 514 camnoc_virt: interconnect-camnoc-virt { 515 compatible = "qcom,sc8180x-camnoc-virt"; 516 #interconnect-cells = <2>; 517 qcom,bcm-voters = <&apps_bcm_voter>; 518 }; 519 520 mc_virt: interconnect-mc-virt { 521 compatible = "qcom,sc8180x-mc-virt"; 522 #interconnect-cells = <2>; 523 qcom,bcm-voters = <&apps_bcm_voter>; 524 }; 525 526 qup_virt: interconnect-qup-virt { 527 compatible = "qcom,sc8180x-qup-virt"; 528 #interconnect-cells = <2>; 529 qcom,bcm-voters = <&apps_bcm_voter>; 530 }; 531 532 memory@80000000 { 533 device_type = "memory"; 534 /* We expect the bootloader to fill in the size */ 535 reg = <0x0 0x80000000 0x0 0x0>; 536 }; 537 538 pmu { 539 compatible = "arm,armv8-pmuv3"; 540 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 541 }; 542 543 psci { 544 compatible = "arm,psci-1.0"; 545 method = "smc"; 546 547 cpu_pd0: power-domain-cpu0 { 548 #power-domain-cells = <0>; 549 power-domains = <&cluster_pd>; 550 domain-idle-states = <&little_cpu_sleep_0>; 551 }; 552 553 cpu_pd1: power-domain-cpu1 { 554 #power-domain-cells = <0>; 555 power-domains = <&cluster_pd>; 556 domain-idle-states = <&little_cpu_sleep_0>; 557 }; 558 559 cpu_pd2: power-domain-cpu2 { 560 #power-domain-cells = <0>; 561 power-domains = <&cluster_pd>; 562 domain-idle-states = <&little_cpu_sleep_0>; 563 }; 564 565 cpu_pd3: power-domain-cpu3 { 566 #power-domain-cells = <0>; 567 power-domains = <&cluster_pd>; 568 domain-idle-states = <&little_cpu_sleep_0>; 569 }; 570 571 cpu_pd4: power-domain-cpu4 { 572 #power-domain-cells = <0>; 573 power-domains = <&cluster_pd>; 574 domain-idle-states = <&big_cpu_sleep_0>; 575 }; 576 577 cpu_pd5: power-domain-cpu5 { 578 #power-domain-cells = <0>; 579 power-domains = <&cluster_pd>; 580 domain-idle-states = <&big_cpu_sleep_0>; 581 }; 582 583 cpu_pd6: power-domain-cpu6 { 584 #power-domain-cells = <0>; 585 power-domains = <&cluster_pd>; 586 domain-idle-states = <&big_cpu_sleep_0>; 587 }; 588 589 cpu_pd7: power-domain-cpu7 { 590 #power-domain-cells = <0>; 591 power-domains = <&cluster_pd>; 592 domain-idle-states = <&big_cpu_sleep_0>; 593 }; 594 595 cluster_pd: power-domain-cpu-cluster0 { 596 #power-domain-cells = <0>; 597 domain-idle-states = <&cluster_sleep_apss_off &cluster_sleep_aoss_sleep>; 598 }; 599 }; 600 601 reserved-memory { 602 #address-cells = <2>; 603 #size-cells = <2>; 604 ranges; 605 606 hyp_mem: hyp@85700000 { 607 reg = <0x0 0x85700000 0x0 0x600000>; 608 no-map; 609 }; 610 611 xbl_mem: xbl@85d00000 { 612 reg = <0x0 0x85d00000 0x0 0x140000>; 613 no-map; 614 }; 615 616 aop_mem: aop@85f00000 { 617 reg = <0x0 0x85f00000 0x0 0x20000>; 618 no-map; 619 }; 620 621 aop_cmd_db: cmd-db@85f20000 { 622 compatible = "qcom,cmd-db"; 623 reg = <0x0 0x85f20000 0x0 0x20000>; 624 no-map; 625 }; 626 627 reserved@85f40000 { 628 reg = <0x0 0x85f40000 0x0 0x10000>; 629 no-map; 630 }; 631 632 smem_mem: smem@86000000 { 633 compatible = "qcom,smem"; 634 reg = <0x0 0x86000000 0x0 0x200000>; 635 no-map; 636 hwlocks = <&tcsr_mutex 3>; 637 }; 638 639 reserved@86200000 { 640 reg = <0x0 0x86200000 0x0 0x3900000>; 641 no-map; 642 }; 643 644 reserved@89b00000 { 645 reg = <0x0 0x89b00000 0x0 0x1c00000>; 646 no-map; 647 }; 648 649 reserved@9d400000 { 650 reg = <0x0 0x9d400000 0x0 0x1000000>; 651 no-map; 652 }; 653 654 reserved@9e400000 { 655 reg = <0x0 0x9e400000 0x0 0x1400000>; 656 no-map; 657 }; 658 659 reserved@9f800000 { 660 reg = <0x0 0x9f800000 0x0 0x800000>; 661 no-map; 662 }; 663 }; 664 665 smp2p-cdsp { 666 compatible = "qcom,smp2p"; 667 qcom,smem = <94>, <432>; 668 669 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 670 671 mboxes = <&apss_shared 6>; 672 673 qcom,local-pid = <0>; 674 qcom,remote-pid = <5>; 675 676 cdsp_smp2p_out: master-kernel { 677 qcom,entry-name = "master-kernel"; 678 #qcom,smem-state-cells = <1>; 679 }; 680 681 cdsp_smp2p_in: slave-kernel { 682 qcom,entry-name = "slave-kernel"; 683 684 interrupt-controller; 685 #interrupt-cells = <2>; 686 }; 687 }; 688 689 smp2p-lpass { 690 compatible = "qcom,smp2p"; 691 qcom,smem = <443>, <429>; 692 693 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 694 695 mboxes = <&apss_shared 10>; 696 697 qcom,local-pid = <0>; 698 qcom,remote-pid = <2>; 699 700 adsp_smp2p_out: master-kernel { 701 qcom,entry-name = "master-kernel"; 702 #qcom,smem-state-cells = <1>; 703 }; 704 705 adsp_smp2p_in: slave-kernel { 706 qcom,entry-name = "slave-kernel"; 707 708 interrupt-controller; 709 #interrupt-cells = <2>; 710 }; 711 }; 712 713 smp2p-mpss { 714 compatible = "qcom,smp2p"; 715 qcom,smem = <435>, <428>; 716 717 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 718 719 mboxes = <&apss_shared 14>; 720 721 qcom,local-pid = <0>; 722 qcom,remote-pid = <1>; 723 724 modem_smp2p_out: master-kernel { 725 qcom,entry-name = "master-kernel"; 726 #qcom,smem-state-cells = <1>; 727 }; 728 729 modem_smp2p_in: slave-kernel { 730 qcom,entry-name = "slave-kernel"; 731 732 interrupt-controller; 733 #interrupt-cells = <2>; 734 }; 735 736 modem_smp2p_ipa_out: ipa-ap-to-modem { 737 qcom,entry-name = "ipa"; 738 #qcom,smem-state-cells = <1>; 739 }; 740 741 modem_smp2p_ipa_in: ipa-modem-to-ap { 742 qcom,entry-name = "ipa"; 743 interrupt-controller; 744 #interrupt-cells = <2>; 745 }; 746 747 modem_smp2p_wlan_in: wlan-wpss-to-ap { 748 qcom,entry-name = "wlan"; 749 interrupt-controller; 750 #interrupt-cells = <2>; 751 }; 752 }; 753 754 smp2p-slpi { 755 compatible = "qcom,smp2p"; 756 qcom,smem = <481>, <430>; 757 758 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 759 760 mboxes = <&apss_shared 26>; 761 762 qcom,local-pid = <0>; 763 qcom,remote-pid = <3>; 764 765 slpi_smp2p_out: master-kernel { 766 qcom,entry-name = "master-kernel"; 767 #qcom,smem-state-cells = <1>; 768 }; 769 770 slpi_smp2p_in: slave-kernel { 771 qcom,entry-name = "slave-kernel"; 772 773 interrupt-controller; 774 #interrupt-cells = <2>; 775 }; 776 }; 777 778 soc: soc@0 { 779 compatible = "simple-bus"; 780 #address-cells = <2>; 781 #size-cells = <2>; 782 ranges = <0 0 0 0 0x10 0>; 783 dma-ranges = <0 0 0 0 0x10 0>; 784 785 gcc: clock-controller@100000 { 786 compatible = "qcom,gcc-sc8180x"; 787 reg = <0x0 0x00100000 0x0 0x1f0000>; 788 #clock-cells = <1>; 789 #reset-cells = <1>; 790 #power-domain-cells = <1>; 791 clocks = <&rpmhcc RPMH_CXO_CLK>, 792 <&rpmhcc RPMH_CXO_CLK_A>, 793 <&sleep_clk>; 794 clock-names = "bi_tcxo", 795 "bi_tcxo_ao", 796 "sleep_clk"; 797 power-domains = <&rpmhpd SC8180X_CX>; 798 }; 799 800 qupv3_id_0: geniqup@8c0000 { 801 compatible = "qcom,geni-se-qup"; 802 reg = <0 0x008c0000 0 0x6000>; 803 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 804 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 805 clock-names = "m-ahb", "s-ahb"; 806 #address-cells = <2>; 807 #size-cells = <2>; 808 ranges; 809 iommus = <&apps_smmu 0x4c3 0>; 810 status = "disabled"; 811 812 i2c0: i2c@880000 { 813 compatible = "qcom,geni-i2c"; 814 reg = <0 0x00880000 0 0x4000>; 815 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 816 clock-names = "se"; 817 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 818 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 819 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 820 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 821 interconnect-names = "qup-core", "qup-config", "qup-memory"; 822 #address-cells = <1>; 823 #size-cells = <0>; 824 status = "disabled"; 825 }; 826 827 spi0: spi@880000 { 828 compatible = "qcom,geni-spi"; 829 reg = <0 0x00880000 0 0x4000>; 830 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 831 clock-names = "se"; 832 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 833 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 834 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 835 interconnect-names = "qup-core", "qup-config"; 836 #address-cells = <1>; 837 #size-cells = <0>; 838 status = "disabled"; 839 }; 840 841 uart0: serial@880000 { 842 compatible = "qcom,geni-uart"; 843 reg = <0 0x00880000 0 0x4000>; 844 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 845 clock-names = "se"; 846 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 847 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 848 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 849 interconnect-names = "qup-core", "qup-config"; 850 status = "disabled"; 851 }; 852 853 i2c1: i2c@884000 { 854 compatible = "qcom,geni-i2c"; 855 reg = <0 0x00884000 0 0x4000>; 856 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 857 clock-names = "se"; 858 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 859 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 860 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 861 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 862 interconnect-names = "qup-core", "qup-config", "qup-memory"; 863 #address-cells = <1>; 864 #size-cells = <0>; 865 status = "disabled"; 866 }; 867 868 spi1: spi@884000 { 869 compatible = "qcom,geni-spi"; 870 reg = <0 0x00884000 0 0x4000>; 871 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 872 clock-names = "se"; 873 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 874 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 875 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 876 interconnect-names = "qup-core", "qup-config"; 877 #address-cells = <1>; 878 #size-cells = <0>; 879 status = "disabled"; 880 }; 881 882 uart1: serial@884000 { 883 compatible = "qcom,geni-uart"; 884 reg = <0 0x00884000 0 0x4000>; 885 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 886 clock-names = "se"; 887 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 888 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 889 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 890 interconnect-names = "qup-core", "qup-config"; 891 status = "disabled"; 892 }; 893 894 i2c2: i2c@888000 { 895 compatible = "qcom,geni-i2c"; 896 reg = <0 0x00888000 0 0x4000>; 897 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 898 clock-names = "se"; 899 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 900 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 901 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 902 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 903 interconnect-names = "qup-core", "qup-config", "qup-memory"; 904 #address-cells = <1>; 905 #size-cells = <0>; 906 status = "disabled"; 907 }; 908 909 spi2: spi@888000 { 910 compatible = "qcom,geni-spi"; 911 reg = <0 0x00888000 0 0x4000>; 912 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 913 clock-names = "se"; 914 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 915 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 916 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 917 interconnect-names = "qup-core", "qup-config"; 918 #address-cells = <1>; 919 #size-cells = <0>; 920 status = "disabled"; 921 }; 922 923 uart2: serial@888000 { 924 compatible = "qcom,geni-uart"; 925 reg = <0 0x00888000 0 0x4000>; 926 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 927 clock-names = "se"; 928 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 929 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 930 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 931 interconnect-names = "qup-core", "qup-config"; 932 status = "disabled"; 933 }; 934 935 i2c3: i2c@88c000 { 936 compatible = "qcom,geni-i2c"; 937 reg = <0 0x0088c000 0 0x4000>; 938 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 939 clock-names = "se"; 940 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 941 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 942 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 943 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 944 interconnect-names = "qup-core", "qup-config", "qup-memory"; 945 #address-cells = <1>; 946 #size-cells = <0>; 947 status = "disabled"; 948 }; 949 950 spi3: spi@88c000 { 951 compatible = "qcom,geni-spi"; 952 reg = <0 0x0088c000 0 0x4000>; 953 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 954 clock-names = "se"; 955 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 956 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 957 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 958 interconnect-names = "qup-core", "qup-config"; 959 #address-cells = <1>; 960 #size-cells = <0>; 961 status = "disabled"; 962 }; 963 964 uart3: serial@88c000 { 965 compatible = "qcom,geni-uart"; 966 reg = <0 0x0088c000 0 0x4000>; 967 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 968 clock-names = "se"; 969 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 970 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 971 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 972 interconnect-names = "qup-core", "qup-config"; 973 status = "disabled"; 974 }; 975 976 i2c4: i2c@890000 { 977 compatible = "qcom,geni-i2c"; 978 reg = <0 0x00890000 0 0x4000>; 979 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 980 clock-names = "se"; 981 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 982 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 983 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 984 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 985 interconnect-names = "qup-core", "qup-config", "qup-memory"; 986 #address-cells = <1>; 987 #size-cells = <0>; 988 status = "disabled"; 989 }; 990 991 spi4: spi@890000 { 992 compatible = "qcom,geni-spi"; 993 reg = <0 0x00890000 0 0x4000>; 994 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 995 clock-names = "se"; 996 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 997 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 998 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 999 interconnect-names = "qup-core", "qup-config"; 1000 #address-cells = <1>; 1001 #size-cells = <0>; 1002 status = "disabled"; 1003 }; 1004 1005 uart4: serial@890000 { 1006 compatible = "qcom,geni-uart"; 1007 reg = <0 0x00890000 0 0x4000>; 1008 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1009 clock-names = "se"; 1010 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1011 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1012 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1013 interconnect-names = "qup-core", "qup-config"; 1014 status = "disabled"; 1015 }; 1016 1017 i2c5: i2c@894000 { 1018 compatible = "qcom,geni-i2c"; 1019 reg = <0 0x00894000 0 0x4000>; 1020 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1021 clock-names = "se"; 1022 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1023 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1024 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1025 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1026 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 status = "disabled"; 1030 }; 1031 1032 spi5: spi@894000 { 1033 compatible = "qcom,geni-spi"; 1034 reg = <0 0x00894000 0 0x4000>; 1035 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1036 clock-names = "se"; 1037 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1038 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1039 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1040 interconnect-names = "qup-core", "qup-config"; 1041 #address-cells = <1>; 1042 #size-cells = <0>; 1043 status = "disabled"; 1044 }; 1045 1046 uart5: serial@894000 { 1047 compatible = "qcom,geni-uart"; 1048 reg = <0 0x00894000 0 0x4000>; 1049 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1050 clock-names = "se"; 1051 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1052 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1053 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1054 interconnect-names = "qup-core", "qup-config"; 1055 status = "disabled"; 1056 }; 1057 1058 i2c6: i2c@898000 { 1059 compatible = "qcom,geni-i2c"; 1060 reg = <0 0x00898000 0 0x4000>; 1061 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1062 clock-names = "se"; 1063 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1064 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1065 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1066 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1067 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1068 #address-cells = <1>; 1069 #size-cells = <0>; 1070 status = "disabled"; 1071 }; 1072 1073 spi6: spi@898000 { 1074 compatible = "qcom,geni-spi"; 1075 reg = <0 0x00898000 0 0x4000>; 1076 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1077 clock-names = "se"; 1078 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1079 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1080 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1081 interconnect-names = "qup-core", "qup-config"; 1082 #address-cells = <1>; 1083 #size-cells = <0>; 1084 status = "disabled"; 1085 }; 1086 1087 uart6: serial@898000 { 1088 compatible = "qcom,geni-uart"; 1089 reg = <0 0x00898000 0 0x4000>; 1090 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1091 clock-names = "se"; 1092 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1093 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1094 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1095 interconnect-names = "qup-core", "qup-config"; 1096 status = "disabled"; 1097 }; 1098 1099 i2c7: i2c@89c000 { 1100 compatible = "qcom,geni-i2c"; 1101 reg = <0 0x0089c000 0 0x4000>; 1102 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1103 clock-names = "se"; 1104 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1105 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1106 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1107 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1108 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1109 #address-cells = <1>; 1110 #size-cells = <0>; 1111 status = "disabled"; 1112 }; 1113 1114 spi7: spi@89c000 { 1115 compatible = "qcom,geni-spi"; 1116 reg = <0 0x0089c000 0 0x4000>; 1117 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1118 clock-names = "se"; 1119 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1120 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1121 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1122 interconnect-names = "qup-core", "qup-config"; 1123 #address-cells = <1>; 1124 #size-cells = <0>; 1125 status = "disabled"; 1126 }; 1127 1128 uart7: serial@89c000 { 1129 compatible = "qcom,geni-uart"; 1130 reg = <0 0x0089c000 0 0x4000>; 1131 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1132 clock-names = "se"; 1133 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1134 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1135 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1136 interconnect-names = "qup-core", "qup-config"; 1137 status = "disabled"; 1138 }; 1139 }; 1140 1141 qupv3_id_1: geniqup@ac0000 { 1142 compatible = "qcom,geni-se-qup"; 1143 reg = <0x0 0x00ac0000 0x0 0x6000>; 1144 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1145 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1146 clock-names = "m-ahb", "s-ahb"; 1147 #address-cells = <2>; 1148 #size-cells = <2>; 1149 ranges; 1150 iommus = <&apps_smmu 0x603 0>; 1151 status = "disabled"; 1152 1153 i2c8: i2c@a80000 { 1154 compatible = "qcom,geni-i2c"; 1155 reg = <0 0x00a80000 0 0x4000>; 1156 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1157 clock-names = "se"; 1158 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1159 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1160 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1161 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1162 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1163 #address-cells = <1>; 1164 #size-cells = <0>; 1165 status = "disabled"; 1166 }; 1167 1168 spi8: spi@a80000 { 1169 compatible = "qcom,geni-spi"; 1170 reg = <0 0x00a80000 0 0x4000>; 1171 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1172 clock-names = "se"; 1173 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1174 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1175 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1176 interconnect-names = "qup-core", "qup-config"; 1177 #address-cells = <1>; 1178 #size-cells = <0>; 1179 status = "disabled"; 1180 }; 1181 1182 uart8: serial@a80000 { 1183 compatible = "qcom,geni-uart"; 1184 reg = <0 0x00a80000 0 0x4000>; 1185 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1186 clock-names = "se"; 1187 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1188 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1189 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1190 interconnect-names = "qup-core", "qup-config"; 1191 status = "disabled"; 1192 }; 1193 1194 i2c9: i2c@a84000 { 1195 compatible = "qcom,geni-i2c"; 1196 reg = <0 0x00a84000 0 0x4000>; 1197 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1198 clock-names = "se"; 1199 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1200 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1201 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1202 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1203 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1204 #address-cells = <1>; 1205 #size-cells = <0>; 1206 status = "disabled"; 1207 }; 1208 1209 spi9: spi@a84000 { 1210 compatible = "qcom,geni-spi"; 1211 reg = <0 0x00a84000 0 0x4000>; 1212 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1213 clock-names = "se"; 1214 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1215 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1216 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1217 interconnect-names = "qup-core", "qup-config"; 1218 #address-cells = <1>; 1219 #size-cells = <0>; 1220 status = "disabled"; 1221 }; 1222 1223 uart9: serial@a84000 { 1224 compatible = "qcom,geni-debug-uart"; 1225 reg = <0 0x00a84000 0 0x4000>; 1226 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1227 clock-names = "se"; 1228 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1229 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1230 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1231 interconnect-names = "qup-core", "qup-config"; 1232 status = "disabled"; 1233 }; 1234 1235 i2c10: i2c@a88000 { 1236 compatible = "qcom,geni-i2c"; 1237 reg = <0 0x00a88000 0 0x4000>; 1238 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1239 clock-names = "se"; 1240 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1241 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1242 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1243 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1244 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1245 #address-cells = <1>; 1246 #size-cells = <0>; 1247 status = "disabled"; 1248 }; 1249 1250 spi10: spi@a88000 { 1251 compatible = "qcom,geni-spi"; 1252 reg = <0 0x00a88000 0 0x4000>; 1253 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1254 clock-names = "se"; 1255 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1256 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1257 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1258 interconnect-names = "qup-core", "qup-config"; 1259 #address-cells = <1>; 1260 #size-cells = <0>; 1261 status = "disabled"; 1262 }; 1263 1264 uart10: serial@a88000 { 1265 compatible = "qcom,geni-uart"; 1266 reg = <0 0x00a88000 0 0x4000>; 1267 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1268 clock-names = "se"; 1269 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1270 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1271 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1272 interconnect-names = "qup-core", "qup-config"; 1273 status = "disabled"; 1274 }; 1275 1276 i2c11: i2c@a8c000 { 1277 compatible = "qcom,geni-i2c"; 1278 reg = <0 0x00a8c000 0 0x4000>; 1279 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1280 clock-names = "se"; 1281 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1282 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1283 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1284 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1285 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1286 #address-cells = <1>; 1287 #size-cells = <0>; 1288 status = "disabled"; 1289 }; 1290 1291 spi11: spi@a8c000 { 1292 compatible = "qcom,geni-spi"; 1293 reg = <0 0x00a8c000 0 0x4000>; 1294 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1295 clock-names = "se"; 1296 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1297 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1298 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1299 interconnect-names = "qup-core", "qup-config"; 1300 #address-cells = <1>; 1301 #size-cells = <0>; 1302 status = "disabled"; 1303 }; 1304 1305 uart11: serial@a8c000 { 1306 compatible = "qcom,geni-uart"; 1307 reg = <0 0x00a8c000 0 0x4000>; 1308 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1309 clock-names = "se"; 1310 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1311 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1312 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1313 interconnect-names = "qup-core", "qup-config"; 1314 status = "disabled"; 1315 }; 1316 1317 i2c12: i2c@a90000 { 1318 compatible = "qcom,geni-i2c"; 1319 reg = <0 0x00a90000 0 0x4000>; 1320 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1321 clock-names = "se"; 1322 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1323 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1324 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1325 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1326 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1327 #address-cells = <1>; 1328 #size-cells = <0>; 1329 status = "disabled"; 1330 }; 1331 1332 spi12: spi@a90000 { 1333 compatible = "qcom,geni-spi"; 1334 reg = <0 0x00a90000 0 0x4000>; 1335 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1336 clock-names = "se"; 1337 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1338 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1339 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1340 interconnect-names = "qup-core", "qup-config"; 1341 #address-cells = <1>; 1342 #size-cells = <0>; 1343 status = "disabled"; 1344 }; 1345 1346 uart12: serial@a90000 { 1347 compatible = "qcom,geni-uart"; 1348 reg = <0 0x00a90000 0 0x4000>; 1349 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1350 clock-names = "se"; 1351 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1352 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1353 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1354 interconnect-names = "qup-core", "qup-config"; 1355 status = "disabled"; 1356 }; 1357 1358 i2c16: i2c@a94000 { 1359 compatible = "qcom,geni-i2c"; 1360 reg = <0 0x00a94000 0 0x4000>; 1361 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1362 clock-names = "se"; 1363 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1364 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1365 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1366 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1367 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1368 #address-cells = <1>; 1369 #size-cells = <0>; 1370 status = "disabled"; 1371 }; 1372 1373 spi16: spi@a94000 { 1374 compatible = "qcom,geni-spi"; 1375 reg = <0 0x00a94000 0 0x4000>; 1376 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1377 clock-names = "se"; 1378 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1379 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1380 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1381 interconnect-names = "qup-core", "qup-config"; 1382 #address-cells = <1>; 1383 #size-cells = <0>; 1384 status = "disabled"; 1385 }; 1386 1387 uart16: serial@a94000 { 1388 compatible = "qcom,geni-uart"; 1389 reg = <0 0x00a94000 0 0x4000>; 1390 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1391 clock-names = "se"; 1392 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1393 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1394 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1395 interconnect-names = "qup-core", "qup-config"; 1396 status = "disabled"; 1397 }; 1398 }; 1399 1400 qupv3_id_2: geniqup@cc0000 { 1401 compatible = "qcom,geni-se-qup"; 1402 reg = <0x0 0x00cc0000 0x0 0x6000>; 1403 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1404 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1405 clock-names = "m-ahb", "s-ahb"; 1406 #address-cells = <2>; 1407 #size-cells = <2>; 1408 ranges; 1409 iommus = <&apps_smmu 0x7a3 0>; 1410 status = "disabled"; 1411 1412 i2c17: i2c@c80000 { 1413 compatible = "qcom,geni-i2c"; 1414 reg = <0 0x00c80000 0 0x4000>; 1415 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1416 clock-names = "se"; 1417 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1418 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1419 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1420 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1421 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1422 #address-cells = <1>; 1423 #size-cells = <0>; 1424 status = "disabled"; 1425 }; 1426 1427 spi17: spi@c80000 { 1428 compatible = "qcom,geni-spi"; 1429 reg = <0 0x00c80000 0 0x4000>; 1430 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1431 clock-names = "se"; 1432 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1433 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1434 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1435 interconnect-names = "qup-core", "qup-config"; 1436 #address-cells = <1>; 1437 #size-cells = <0>; 1438 status = "disabled"; 1439 }; 1440 1441 uart17: serial@c80000 { 1442 compatible = "qcom,geni-uart"; 1443 reg = <0 0x00c80000 0 0x4000>; 1444 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1445 clock-names = "se"; 1446 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1447 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1448 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1449 interconnect-names = "qup-core", "qup-config"; 1450 status = "disabled"; 1451 }; 1452 1453 i2c18: i2c@c84000 { 1454 compatible = "qcom,geni-i2c"; 1455 reg = <0 0x00c84000 0 0x4000>; 1456 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1457 clock-names = "se"; 1458 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1459 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1460 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1461 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1462 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1463 #address-cells = <1>; 1464 #size-cells = <0>; 1465 status = "disabled"; 1466 }; 1467 1468 spi18: spi@c84000 { 1469 compatible = "qcom,geni-spi"; 1470 reg = <0 0x00c84000 0 0x4000>; 1471 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1472 clock-names = "se"; 1473 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1474 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1475 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1476 interconnect-names = "qup-core", "qup-config"; 1477 #address-cells = <1>; 1478 #size-cells = <0>; 1479 status = "disabled"; 1480 }; 1481 1482 uart18: serial@c84000 { 1483 compatible = "qcom,geni-uart"; 1484 reg = <0 0x00c84000 0 0x4000>; 1485 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1486 clock-names = "se"; 1487 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1488 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1489 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1490 interconnect-names = "qup-core", "qup-config"; 1491 status = "disabled"; 1492 }; 1493 1494 i2c19: i2c@c88000 { 1495 compatible = "qcom,geni-i2c"; 1496 reg = <0 0x00c88000 0 0x4000>; 1497 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1498 clock-names = "se"; 1499 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1500 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1501 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1502 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1503 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1504 #address-cells = <1>; 1505 #size-cells = <0>; 1506 status = "disabled"; 1507 }; 1508 1509 spi19: spi@c88000 { 1510 compatible = "qcom,geni-spi"; 1511 reg = <0 0x00c88000 0 0x4000>; 1512 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1513 clock-names = "se"; 1514 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1515 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1516 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1517 interconnect-names = "qup-core", "qup-config"; 1518 #address-cells = <1>; 1519 #size-cells = <0>; 1520 status = "disabled"; 1521 }; 1522 1523 uart19: serial@c88000 { 1524 compatible = "qcom,geni-uart"; 1525 reg = <0 0x00c88000 0 0x4000>; 1526 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1527 clock-names = "se"; 1528 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1529 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1530 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1531 interconnect-names = "qup-core", "qup-config"; 1532 status = "disabled"; 1533 }; 1534 1535 i2c13: i2c@c8c000 { 1536 compatible = "qcom,geni-i2c"; 1537 reg = <0 0x00c8c000 0 0x4000>; 1538 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1539 clock-names = "se"; 1540 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1541 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1542 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1543 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1544 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1545 #address-cells = <1>; 1546 #size-cells = <0>; 1547 status = "disabled"; 1548 }; 1549 1550 spi13: spi@c8c000 { 1551 compatible = "qcom,geni-spi"; 1552 reg = <0 0x00c8c000 0 0x4000>; 1553 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1554 clock-names = "se"; 1555 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1556 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1557 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1558 interconnect-names = "qup-core", "qup-config"; 1559 #address-cells = <1>; 1560 #size-cells = <0>; 1561 status = "disabled"; 1562 }; 1563 1564 uart13: serial@c8c000 { 1565 compatible = "qcom,geni-uart"; 1566 reg = <0 0x00c8c000 0 0x4000>; 1567 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1568 clock-names = "se"; 1569 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1570 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1571 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1572 interconnect-names = "qup-core", "qup-config"; 1573 status = "disabled"; 1574 }; 1575 1576 i2c14: i2c@c90000 { 1577 compatible = "qcom,geni-i2c"; 1578 reg = <0 0x00c90000 0 0x4000>; 1579 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1580 clock-names = "se"; 1581 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1582 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1583 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1584 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1585 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1586 #address-cells = <1>; 1587 #size-cells = <0>; 1588 status = "disabled"; 1589 }; 1590 1591 spi14: spi@c90000 { 1592 compatible = "qcom,geni-spi"; 1593 reg = <0 0x00c90000 0 0x4000>; 1594 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1595 clock-names = "se"; 1596 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1597 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1598 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1599 interconnect-names = "qup-core", "qup-config"; 1600 #address-cells = <1>; 1601 #size-cells = <0>; 1602 status = "disabled"; 1603 }; 1604 1605 uart14: serial@c90000 { 1606 compatible = "qcom,geni-uart"; 1607 reg = <0 0x00c90000 0 0x4000>; 1608 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1609 clock-names = "se"; 1610 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1611 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1612 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1613 interconnect-names = "qup-core", "qup-config"; 1614 status = "disabled"; 1615 }; 1616 1617 i2c15: i2c@c94000 { 1618 compatible = "qcom,geni-i2c"; 1619 reg = <0 0x00c94000 0 0x4000>; 1620 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1621 clock-names = "se"; 1622 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1623 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1624 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1625 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1626 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 status = "disabled"; 1630 }; 1631 1632 spi15: spi@c94000 { 1633 compatible = "qcom,geni-spi"; 1634 reg = <0 0x00c94000 0 0x4000>; 1635 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1636 clock-names = "se"; 1637 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1638 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1639 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1640 interconnect-names = "qup-core", "qup-config"; 1641 #address-cells = <1>; 1642 #size-cells = <0>; 1643 status = "disabled"; 1644 }; 1645 1646 uart15: serial@c94000 { 1647 compatible = "qcom,geni-uart"; 1648 reg = <0 0x00c94000 0 0x4000>; 1649 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1650 clock-names = "se"; 1651 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1652 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1653 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1654 interconnect-names = "qup-core", "qup-config"; 1655 status = "disabled"; 1656 }; 1657 }; 1658 1659 config_noc: interconnect@1500000 { 1660 compatible = "qcom,sc8180x-config-noc"; 1661 reg = <0 0x01500000 0 0x7400>; 1662 #interconnect-cells = <2>; 1663 qcom,bcm-voters = <&apps_bcm_voter>; 1664 }; 1665 1666 system_noc: interconnect@1620000 { 1667 compatible = "qcom,sc8180x-system-noc"; 1668 reg = <0 0x01620000 0 0x19400>; 1669 #interconnect-cells = <2>; 1670 qcom,bcm-voters = <&apps_bcm_voter>; 1671 }; 1672 1673 aggre1_noc: interconnect@16e0000 { 1674 compatible = "qcom,sc8180x-aggre1-noc"; 1675 reg = <0 0x016e0000 0 0xd080>; 1676 #interconnect-cells = <2>; 1677 qcom,bcm-voters = <&apps_bcm_voter>; 1678 }; 1679 1680 aggre2_noc: interconnect@1700000 { 1681 compatible = "qcom,sc8180x-aggre2-noc"; 1682 reg = <0 0x01700000 0 0x20000>; 1683 #interconnect-cells = <2>; 1684 qcom,bcm-voters = <&apps_bcm_voter>; 1685 }; 1686 1687 compute_noc: interconnect@1720000 { 1688 compatible = "qcom,sc8180x-compute-noc"; 1689 reg = <0 0x01720000 0 0x7000>; 1690 #interconnect-cells = <2>; 1691 qcom,bcm-voters = <&apps_bcm_voter>; 1692 }; 1693 1694 mmss_noc: interconnect@1740000 { 1695 compatible = "qcom,sc8180x-mmss-noc"; 1696 reg = <0 0x01740000 0 0x1c100>; 1697 #interconnect-cells = <2>; 1698 qcom,bcm-voters = <&apps_bcm_voter>; 1699 }; 1700 1701 pcie0: pcie@1c00000 { 1702 compatible = "qcom,pcie-sc8180x"; 1703 reg = <0 0x01c00000 0 0x3000>, 1704 <0 0x60000000 0 0xf1d>, 1705 <0 0x60000f20 0 0xa8>, 1706 <0 0x60001000 0 0x1000>, 1707 <0 0x60100000 0 0x100000>; 1708 reg-names = "parf", 1709 "dbi", 1710 "elbi", 1711 "atu", 1712 "config"; 1713 device_type = "pci"; 1714 linux,pci-domain = <0>; 1715 bus-range = <0x00 0xff>; 1716 num-lanes = <2>; 1717 1718 #address-cells = <3>; 1719 #size-cells = <2>; 1720 1721 ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>, 1722 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1723 1724 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1725 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1726 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1727 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1728 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1729 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1730 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1731 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1732 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1733 interrupt-names = "msi0", 1734 "msi1", 1735 "msi2", 1736 "msi3", 1737 "msi4", 1738 "msi5", 1739 "msi6", 1740 "msi7", 1741 "global"; 1742 #interrupt-cells = <1>; 1743 interrupt-map-mask = <0 0 0 0x7>; 1744 interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1745 <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1746 <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1747 <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1748 1749 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1750 <&gcc GCC_PCIE_0_AUX_CLK>, 1751 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1752 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1753 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1754 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 1755 clock-names = "pipe", 1756 "aux", 1757 "cfg", 1758 "bus_master", 1759 "bus_slave", 1760 "slave_q2a"; 1761 1762 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 1763 assigned-clock-rates = <19200000>; 1764 1765 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, 1766 <0x100 &apps_smmu 0x1d81 0x1>; 1767 1768 resets = <&gcc GCC_PCIE_0_BCR>; 1769 reset-names = "pci"; 1770 1771 power-domains = <&gcc PCIE_0_GDSC>; 1772 1773 interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>, 1774 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; 1775 interconnect-names = "pcie-mem", "cpu-pcie"; 1776 1777 phys = <&pcie0_phy>; 1778 phy-names = "pciephy"; 1779 dma-coherent; 1780 1781 status = "disabled"; 1782 1783 pcie@0 { 1784 device_type = "pci"; 1785 reg = <0x0 0x0 0x0 0x0 0x0>; 1786 bus-range = <0x01 0xff>; 1787 1788 #address-cells = <3>; 1789 #size-cells = <2>; 1790 ranges; 1791 }; 1792 }; 1793 1794 pcie0_phy: phy@1c06000 { 1795 compatible = "qcom,sc8180x-qmp-pcie-phy"; 1796 reg = <0 0x01c06000 0 0x1000>; 1797 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1798 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1799 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1800 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, 1801 <&gcc GCC_PCIE_0_PIPE_CLK>; 1802 clock-names = "aux", 1803 "cfg_ahb", 1804 "ref", 1805 "refgen", 1806 "pipe"; 1807 #clock-cells = <0>; 1808 clock-output-names = "pcie_0_pipe_clk"; 1809 #phy-cells = <0>; 1810 1811 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1812 reset-names = "phy"; 1813 1814 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1815 assigned-clock-rates = <100000000>; 1816 1817 status = "disabled"; 1818 }; 1819 1820 pcie3: pcie@1c08000 { 1821 compatible = "qcom,pcie-sc8180x"; 1822 reg = <0 0x01c08000 0 0x3000>, 1823 <0 0x40000000 0 0xf1d>, 1824 <0 0x40000f20 0 0xa8>, 1825 <0 0x40001000 0 0x1000>, 1826 <0 0x40100000 0 0x100000>; 1827 reg-names = "parf", 1828 "dbi", 1829 "elbi", 1830 "atu", 1831 "config"; 1832 device_type = "pci"; 1833 linux,pci-domain = <3>; 1834 bus-range = <0x00 0xff>; 1835 num-lanes = <2>; 1836 1837 #address-cells = <3>; 1838 #size-cells = <2>; 1839 1840 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1841 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1842 1843 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 1852 interrupt-names = "msi0", 1853 "msi1", 1854 "msi2", 1855 "msi3", 1856 "msi4", 1857 "msi5", 1858 "msi6", 1859 "msi7", 1860 "global"; 1861 #interrupt-cells = <1>; 1862 interrupt-map-mask = <0 0 0 0x7>; 1863 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1864 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1865 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1866 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1867 1868 clocks = <&gcc GCC_PCIE_3_PIPE_CLK>, 1869 <&gcc GCC_PCIE_3_AUX_CLK>, 1870 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 1871 <&gcc GCC_PCIE_3_MSTR_AXI_CLK>, 1872 <&gcc GCC_PCIE_3_SLV_AXI_CLK>, 1873 <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>; 1874 clock-names = "pipe", 1875 "aux", 1876 "cfg", 1877 "bus_master", 1878 "bus_slave", 1879 "slave_q2a"; 1880 1881 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>; 1882 assigned-clock-rates = <19200000>; 1883 1884 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 1885 <0x100 &apps_smmu 0x1e01 0x1>; 1886 1887 resets = <&gcc GCC_PCIE_3_BCR>; 1888 reset-names = "pci"; 1889 1890 power-domains = <&gcc PCIE_3_GDSC>; 1891 1892 interconnects = <&aggre2_noc MASTER_PCIE_3 0 &mc_virt SLAVE_EBI_CH0 0>, 1893 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_3 0>; 1894 interconnect-names = "pcie-mem", "cpu-pcie"; 1895 1896 phys = <&pcie3_phy>; 1897 phy-names = "pciephy"; 1898 dma-coherent; 1899 1900 status = "disabled"; 1901 1902 pcie@0 { 1903 device_type = "pci"; 1904 reg = <0x0 0x0 0x0 0x0 0x0>; 1905 bus-range = <0x01 0xff>; 1906 1907 #address-cells = <3>; 1908 #size-cells = <2>; 1909 ranges; 1910 }; 1911 }; 1912 1913 pcie3_phy: phy@1c0c000 { 1914 compatible = "qcom,sc8180x-qmp-pcie-phy"; 1915 reg = <0 0x01c0c000 0 0x1000>; 1916 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1917 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 1918 <&gcc GCC_PCIE_3_CLKREF_CLK>, 1919 <&gcc GCC_PCIE3_PHY_REFGEN_CLK>, 1920 <&gcc GCC_PCIE_3_PIPE_CLK>; 1921 clock-names = "aux", 1922 "cfg_ahb", 1923 "ref", 1924 "refgen", 1925 "pipe"; 1926 #clock-cells = <0>; 1927 clock-output-names = "pcie_3_pipe_clk"; 1928 1929 #phy-cells = <0>; 1930 1931 resets = <&gcc GCC_PCIE_3_PHY_BCR>; 1932 reset-names = "phy"; 1933 1934 assigned-clocks = <&gcc GCC_PCIE3_PHY_REFGEN_CLK>; 1935 assigned-clock-rates = <100000000>; 1936 1937 status = "disabled"; 1938 }; 1939 1940 pcie1: pcie@1c10000 { 1941 compatible = "qcom,pcie-sc8180x"; 1942 reg = <0 0x01c10000 0 0x3000>, 1943 <0 0x68000000 0 0xf1d>, 1944 <0 0x68000f20 0 0xa8>, 1945 <0 0x68001000 0 0x1000>, 1946 <0 0x68100000 0 0x100000>; 1947 reg-names = "parf", 1948 "dbi", 1949 "elbi", 1950 "atu", 1951 "config"; 1952 device_type = "pci"; 1953 linux,pci-domain = <1>; 1954 bus-range = <0x00 0xff>; 1955 num-lanes = <2>; 1956 1957 #address-cells = <3>; 1958 #size-cells = <2>; 1959 1960 ranges = <0x01000000 0x0 0x68200000 0x0 0x68200000 0x0 0x100000>, 1961 <0x02000000 0x0 0x68300000 0x0 0x68300000 0x0 0x3d00000>; 1962 1963 interrupts = <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>, 1964 <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>, 1965 <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>, 1966 <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>, 1967 <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>, 1968 <GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>, 1969 <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>, 1970 <GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>, 1971 <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>; 1972 interrupt-names = "msi0", 1973 "msi1", 1974 "msi2", 1975 "msi3", 1976 "msi4", 1977 "msi5", 1978 "msi6", 1979 "msi7", 1980 "global"; 1981 #interrupt-cells = <1>; 1982 interrupt-map-mask = <0 0 0 0x7>; 1983 interrupt-map = <0 0 0 1 &intc GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1984 <0 0 0 2 &intc GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1985 <0 0 0 3 &intc GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1986 <0 0 0 4 &intc GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1987 1988 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1989 <&gcc GCC_PCIE_1_AUX_CLK>, 1990 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1991 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1992 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1993 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 1994 clock-names = "pipe", 1995 "aux", 1996 "cfg", 1997 "bus_master", 1998 "bus_slave", 1999 "slave_q2a"; 2000 2001 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2002 assigned-clock-rates = <19200000>; 2003 2004 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2005 <0x100 &apps_smmu 0x1c81 0x1>; 2006 2007 resets = <&gcc GCC_PCIE_1_BCR>; 2008 reset-names = "pci"; 2009 2010 power-domains = <&gcc PCIE_1_GDSC>; 2011 2012 interconnects = <&aggre2_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI_CH0 0>, 2013 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_1 0>; 2014 interconnect-names = "pcie-mem", "cpu-pcie"; 2015 2016 phys = <&pcie1_phy>; 2017 phy-names = "pciephy"; 2018 dma-coherent; 2019 2020 status = "disabled"; 2021 2022 pcie@0 { 2023 device_type = "pci"; 2024 reg = <0x0 0x0 0x0 0x0 0x0>; 2025 bus-range = <0x01 0xff>; 2026 2027 #address-cells = <3>; 2028 #size-cells = <2>; 2029 ranges; 2030 }; 2031 }; 2032 2033 pcie1_phy: phy@1c16000 { 2034 compatible = "qcom,sc8180x-qmp-pcie-phy"; 2035 reg = <0 0x01c16000 0 0x1000>; 2036 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2037 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2038 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2039 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, 2040 <&gcc GCC_PCIE_1_PIPE_CLK>; 2041 clock-names = "aux", 2042 "cfg_ahb", 2043 "ref", 2044 "refgen", 2045 "pipe"; 2046 #clock-cells = <0>; 2047 clock-output-names = "pcie_1_pipe_clk"; 2048 2049 #phy-cells = <0>; 2050 2051 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2052 reset-names = "phy"; 2053 2054 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2055 assigned-clock-rates = <100000000>; 2056 2057 status = "disabled"; 2058 }; 2059 2060 pcie2: pcie@1c18000 { 2061 compatible = "qcom,pcie-sc8180x"; 2062 reg = <0 0x01c18000 0 0x3000>, 2063 <0 0x70000000 0 0xf1d>, 2064 <0 0x70000f20 0 0xa8>, 2065 <0 0x70001000 0 0x1000>, 2066 <0 0x70100000 0 0x100000>; 2067 reg-names = "parf", 2068 "dbi", 2069 "elbi", 2070 "atu", 2071 "config"; 2072 device_type = "pci"; 2073 linux,pci-domain = <2>; 2074 bus-range = <0x00 0xff>; 2075 num-lanes = <4>; 2076 2077 #address-cells = <3>; 2078 #size-cells = <2>; 2079 2080 ranges = <0x01000000 0x0 0x70200000 0x0 0x70200000 0x0 0x100000>, 2081 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>; 2082 2083 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2084 <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>, 2085 <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>, 2086 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 2087 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>, 2088 <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>, 2089 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 2090 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 2091 <GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>; 2092 interrupt-names = "msi0", 2093 "msi1", 2094 "msi2", 2095 "msi3", 2096 "msi4", 2097 "msi5", 2098 "msi6", 2099 "msi7", 2100 "global"; 2101 #interrupt-cells = <1>; 2102 interrupt-map-mask = <0 0 0 0x7>; 2103 interrupt-map = <0 0 0 1 &intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2104 <0 0 0 2 &intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2105 <0 0 0 3 &intc GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2106 <0 0 0 4 &intc GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2107 2108 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2109 <&gcc GCC_PCIE_2_AUX_CLK>, 2110 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2111 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2112 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 2113 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>; 2114 clock-names = "pipe", 2115 "aux", 2116 "cfg", 2117 "bus_master", 2118 "bus_slave", 2119 "slave_q2a"; 2120 2121 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 2122 assigned-clock-rates = <19200000>; 2123 2124 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 2125 <0x100 &apps_smmu 0x1d01 0x1>; 2126 2127 resets = <&gcc GCC_PCIE_2_BCR>; 2128 reset-names = "pci"; 2129 2130 power-domains = <&gcc PCIE_2_GDSC>; 2131 2132 interconnects = <&aggre2_noc MASTER_PCIE_2 0 &mc_virt SLAVE_EBI_CH0 0>, 2133 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_2 0>; 2134 interconnect-names = "pcie-mem", "cpu-pcie"; 2135 2136 phys = <&pcie2_phy>; 2137 phy-names = "pciephy"; 2138 dma-coherent; 2139 2140 status = "disabled"; 2141 2142 pcie@0 { 2143 device_type = "pci"; 2144 reg = <0x0 0x0 0x0 0x0 0x0>; 2145 bus-range = <0x01 0xff>; 2146 2147 #address-cells = <3>; 2148 #size-cells = <2>; 2149 ranges; 2150 }; 2151 }; 2152 2153 pcie2_phy: phy@1c1c000 { 2154 compatible = "qcom,sc8180x-qmp-pcie-phy"; 2155 reg = <0 0x01c1c000 0 0x1000>; 2156 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2157 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2158 <&gcc GCC_PCIE_2_CLKREF_CLK>, 2159 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>, 2160 <&gcc GCC_PCIE_2_PIPE_CLK>; 2161 clock-names = "aux", 2162 "cfg_ahb", 2163 "ref", 2164 "refgen", 2165 "pipe"; 2166 #clock-cells = <0>; 2167 clock-output-names = "pcie_2_pipe_clk"; 2168 2169 #phy-cells = <0>; 2170 2171 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 2172 reset-names = "phy"; 2173 2174 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2175 assigned-clock-rates = <100000000>; 2176 2177 status = "disabled"; 2178 }; 2179 2180 ufs_mem_hc: ufshc@1d84000 { 2181 compatible = "qcom,sc8180x-ufshc", "qcom,ufshc", 2182 "jedec,ufs-2.0"; 2183 reg = <0 0x01d84000 0 0x2500>; 2184 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2185 phys = <&ufs_mem_phy>; 2186 phy-names = "ufsphy"; 2187 lanes-per-direction = <2>; 2188 #reset-cells = <1>; 2189 resets = <&gcc GCC_UFS_PHY_BCR>; 2190 reset-names = "rst"; 2191 2192 iommus = <&apps_smmu 0x300 0>; 2193 2194 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2195 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2196 <&gcc GCC_UFS_PHY_AHB_CLK>, 2197 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2198 <&rpmhcc RPMH_CXO_CLK>, 2199 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2200 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2201 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2202 clock-names = "core_clk", 2203 "bus_aggr_clk", 2204 "iface_clk", 2205 "core_clk_unipro", 2206 "ref_clk", 2207 "tx_lane0_sync_clk", 2208 "rx_lane0_sync_clk", 2209 "rx_lane1_sync_clk"; 2210 freq-table-hz = <37500000 300000000>, 2211 <0 0>, 2212 <0 0>, 2213 <37500000 300000000>, 2214 <0 0>, 2215 <0 0>, 2216 <0 0>, 2217 <0 0>; 2218 2219 power-domains = <&gcc UFS_PHY_GDSC>; 2220 2221 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2222 &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, 2223 <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS 2224 &config_noc SLAVE_UFS_MEM_0_CFG QCOM_ICC_TAG_ALWAYS>; 2225 interconnect-names = "ufs-ddr", "cpu-ufs"; 2226 2227 status = "disabled"; 2228 }; 2229 2230 ufs_mem_phy: phy-wrapper@1d87000 { 2231 compatible = "qcom,sc8180x-qmp-ufs-phy"; 2232 reg = <0 0x01d87000 0 0x1000>; 2233 2234 clocks = <&rpmhcc RPMH_CXO_CLK>, 2235 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2236 <&gcc GCC_UFS_MEM_CLKREF_EN>; 2237 clock-names = "ref", 2238 "ref_aux", 2239 "qref"; 2240 2241 resets = <&ufs_mem_hc 0>; 2242 reset-names = "ufsphy"; 2243 2244 power-domains = <&gcc UFS_PHY_GDSC>; 2245 2246 #phy-cells = <0>; 2247 2248 status = "disabled"; 2249 }; 2250 2251 tcsr_mutex: hwlock@1f40000 { 2252 compatible = "qcom,tcsr-mutex"; 2253 reg = <0x0 0x01f40000 0x0 0x40000>; 2254 #hwlock-cells = <1>; 2255 }; 2256 2257 gpu: gpu@2c00000 { 2258 compatible = "qcom,adreno-680.1", "qcom,adreno"; 2259 2260 reg = <0 0x02c00000 0 0x40000>; 2261 reg-names = "kgsl_3d0_reg_memory"; 2262 2263 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2264 2265 iommus = <&adreno_smmu 0 0xc01>; 2266 2267 operating-points-v2 = <&gpu_opp_table>; 2268 2269 interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &mc_virt SLAVE_EBI_CH0 0>; 2270 interconnect-names = "gfx-mem"; 2271 2272 qcom,gmu = <&gmu>; 2273 #cooling-cells = <2>; 2274 2275 status = "disabled"; 2276 2277 gpu_opp_table: opp-table { 2278 compatible = "operating-points-v2"; 2279 2280 opp-514000000 { 2281 opp-hz = /bits/ 64 <514000000>; 2282 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2283 }; 2284 2285 opp-500000000 { 2286 opp-hz = /bits/ 64 <500000000>; 2287 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2288 }; 2289 2290 opp-461000000 { 2291 opp-hz = /bits/ 64 <461000000>; 2292 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2293 }; 2294 2295 opp-405000000 { 2296 opp-hz = /bits/ 64 <405000000>; 2297 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2298 }; 2299 2300 opp-315000000 { 2301 opp-hz = /bits/ 64 <315000000>; 2302 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2303 }; 2304 2305 opp-256000000 { 2306 opp-hz = /bits/ 64 <256000000>; 2307 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2308 }; 2309 2310 opp-177000000 { 2311 opp-hz = /bits/ 64 <177000000>; 2312 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2313 }; 2314 }; 2315 }; 2316 2317 gmu: gmu@2c6a000 { 2318 compatible = "qcom,adreno-gmu-680.1", "qcom,adreno-gmu"; 2319 2320 reg = <0 0x02c6a000 0 0x30000>, 2321 <0 0x0b290000 0 0x10000>, 2322 <0 0x0b490000 0 0x10000>; 2323 reg-names = "gmu", 2324 "gmu_pdc", 2325 "gmu_pdc_seq"; 2326 2327 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2328 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2329 interrupt-names = "hfi", "gmu"; 2330 2331 clocks = <&gpucc GPU_CC_AHB_CLK>, 2332 <&gpucc GPU_CC_CX_GMU_CLK>, 2333 <&gpucc GPU_CC_CXO_CLK>, 2334 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2335 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2336 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2337 2338 power-domains = <&gpucc GPU_CX_GDSC>, 2339 <&gpucc GPU_GX_GDSC>; 2340 power-domain-names = "cx", "gx"; 2341 2342 iommus = <&adreno_smmu 5 0xc00>; 2343 2344 operating-points-v2 = <&gmu_opp_table>; 2345 2346 gmu_opp_table: opp-table { 2347 compatible = "operating-points-v2"; 2348 2349 opp-200000000 { 2350 opp-hz = /bits/ 64 <200000000>; 2351 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2352 }; 2353 2354 opp-500000000 { 2355 opp-hz = /bits/ 64 <500000000>; 2356 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2357 }; 2358 }; 2359 }; 2360 2361 gpucc: clock-controller@2c90000 { 2362 compatible = "qcom,sc8180x-gpucc"; 2363 reg = <0 0x02c90000 0 0x9000>; 2364 clocks = <&rpmhcc RPMH_CXO_CLK>, 2365 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2366 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2367 clock-names = "bi_tcxo", 2368 "gcc_gpu_gpll0_clk_src", 2369 "gcc_gpu_gpll0_div_clk_src"; 2370 #clock-cells = <1>; 2371 #reset-cells = <1>; 2372 #power-domain-cells = <1>; 2373 }; 2374 2375 adreno_smmu: iommu@2ca0000 { 2376 compatible = "qcom,sc8180x-smmu-500", "qcom,adreno-smmu", 2377 "qcom,smmu-500", "arm,mmu-500"; 2378 reg = <0 0x02ca0000 0 0x10000>; 2379 #iommu-cells = <2>; 2380 #global-interrupts = <1>; 2381 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 2382 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2383 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2384 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2385 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2386 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2387 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2388 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2389 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 2390 clocks = <&gpucc GPU_CC_AHB_CLK>, 2391 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2392 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2393 clock-names = "ahb", "bus", "iface"; 2394 2395 power-domains = <&gpucc GPU_CX_GDSC>; 2396 }; 2397 2398 tlmm: pinctrl@3100000 { 2399 compatible = "qcom,sc8180x-tlmm"; 2400 reg = <0 0x03100000 0 0x300000>, 2401 <0 0x03500000 0 0x700000>, 2402 <0 0x03d00000 0 0x300000>; 2403 reg-names = "west", "east", "south"; 2404 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2405 gpio-controller; 2406 #gpio-cells = <2>; 2407 interrupt-controller; 2408 #interrupt-cells = <2>; 2409 gpio-ranges = <&tlmm 0 0 191>; 2410 wakeup-parent = <&pdc>; 2411 }; 2412 2413 remoteproc_mpss: remoteproc@4080000 { 2414 compatible = "qcom,sc8180x-mpss-pas"; 2415 reg = <0x0 0x04080000 0x0 0x4040>; 2416 2417 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2418 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2419 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2420 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2421 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2422 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2423 interrupt-names = "wdog", "fatal", "ready", "handover", 2424 "stop-ack", "shutdown-ack"; 2425 2426 clocks = <&rpmhcc RPMH_CXO_CLK>; 2427 clock-names = "xo"; 2428 2429 power-domains = <&rpmhpd SC8180X_CX>, 2430 <&rpmhpd SC8180X_MSS>; 2431 power-domain-names = "cx", "mss"; 2432 2433 qcom,qmp = <&aoss_qmp>; 2434 2435 qcom,smem-states = <&modem_smp2p_out 0>; 2436 qcom,smem-state-names = "stop"; 2437 2438 glink-edge { 2439 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2440 label = "modem"; 2441 qcom,remote-pid = <1>; 2442 mboxes = <&apss_shared 12>; 2443 }; 2444 }; 2445 2446 remoteproc_cdsp: remoteproc@8300000 { 2447 compatible = "qcom,sc8180x-cdsp-pas"; 2448 reg = <0x0 0x08300000 0x0 0x4040>; 2449 2450 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2451 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2452 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2453 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2454 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2455 interrupt-names = "wdog", "fatal", "ready", 2456 "handover", "stop-ack"; 2457 2458 clocks = <&rpmhcc RPMH_CXO_CLK>; 2459 clock-names = "xo"; 2460 2461 power-domains = <&rpmhpd SC8180X_CX>; 2462 power-domain-names = "cx"; 2463 2464 qcom,qmp = <&aoss_qmp>; 2465 2466 qcom,smem-states = <&cdsp_smp2p_out 0>; 2467 qcom,smem-state-names = "stop"; 2468 2469 status = "disabled"; 2470 2471 glink-edge { 2472 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 2473 label = "cdsp"; 2474 qcom,remote-pid = <5>; 2475 mboxes = <&apss_shared 4>; 2476 }; 2477 }; 2478 2479 usb_prim_hsphy: phy@88e2000 { 2480 compatible = "qcom,sc8180x-usb-hs-phy", 2481 "qcom,usb-snps-hs-7nm-phy"; 2482 reg = <0 0x088e2000 0 0x400>; 2483 clocks = <&rpmhcc RPMH_CXO_CLK>; 2484 clock-names = "ref"; 2485 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2486 2487 #phy-cells = <0>; 2488 2489 status = "disabled"; 2490 }; 2491 2492 usb_sec_hsphy: phy@88e3000 { 2493 compatible = "qcom,sc8180x-usb-hs-phy", 2494 "qcom,usb-snps-hs-7nm-phy"; 2495 reg = <0 0x088e3000 0 0x400>; 2496 clocks = <&rpmhcc RPMH_CXO_CLK>; 2497 clock-names = "ref"; 2498 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2499 2500 #phy-cells = <0>; 2501 2502 status = "disabled"; 2503 }; 2504 2505 usb_mp_hsphy0: phy@88e4000 { 2506 compatible = "qcom,sc8180x-usb-hs-phy", 2507 "qcom,usb-snps-hs-7nm-phy"; 2508 reg = <0 0x088e4000 0 0x400>; 2509 #phy-cells = <0>; 2510 2511 clocks = <&rpmhcc RPMH_CXO_CLK>; 2512 clock-names = "ref"; 2513 2514 resets = <&gcc GCC_QUSB2PHY_MP0_BCR>; 2515 2516 status = "disabled"; 2517 }; 2518 2519 usb_mp_hsphy1: phy@88e5000 { 2520 compatible = "qcom,sc8180x-usb-hs-phy", 2521 "qcom,usb-snps-hs-7nm-phy"; 2522 reg = <0 0x088e5000 0 0x400>; 2523 #phy-cells = <0>; 2524 2525 clocks = <&rpmhcc RPMH_CXO_CLK>; 2526 clock-names = "ref"; 2527 2528 resets = <&gcc GCC_QUSB2PHY_MP1_BCR>; 2529 2530 status = "disabled"; 2531 }; 2532 2533 usb_prim_qmpphy: phy@88e8000 { 2534 compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; 2535 reg = <0 0x088e8000 0 0x3000>; 2536 2537 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2538 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2539 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2540 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2541 clock-names = "aux", 2542 "ref", 2543 "com_aux", 2544 "usb3_pipe"; 2545 2546 resets = <&gcc GCC_USB3_DP_PHY_PRIM_SP0_BCR>, 2547 <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>; 2548 reset-names = "phy", "common"; 2549 2550 #clock-cells = <1>; 2551 #phy-cells = <1>; 2552 2553 status = "disabled"; 2554 2555 ports { 2556 #address-cells = <1>; 2557 #size-cells = <0>; 2558 2559 port@0 { 2560 reg = <0>; 2561 2562 usb_prim_qmpphy_out: endpoint {}; 2563 }; 2564 2565 port@1 { 2566 reg = <1>; 2567 2568 usb_prim_qmpphy_usb_ss_in: endpoint { 2569 remote-endpoint = <&usb_prim_dwc3_ss>; 2570 }; 2571 }; 2572 2573 port@2 { 2574 reg = <2>; 2575 2576 usb_prim_qmpphy_dp_in: endpoint {}; 2577 }; 2578 }; 2579 }; 2580 2581 usb_mp_qmpphy0: phy@88eb000 { 2582 compatible = "qcom,sc8180x-qmp-usb3-uni-phy"; 2583 reg = <0 0x088eb000 0 0x1000>; 2584 2585 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2586 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2587 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2588 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 2589 clock-names = "aux", 2590 "ref", 2591 "com_aux", 2592 "pipe"; 2593 2594 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 2595 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 2596 reset-names = "phy", "phy_phy"; 2597 2598 power-domains = <&gcc USB30_MP_GDSC>; 2599 2600 #clock-cells = <0>; 2601 clock-output-names = "usb2_phy0_pipe_clk"; 2602 2603 #phy-cells = <0>; 2604 2605 status = "disabled"; 2606 }; 2607 2608 usb_mp_qmpphy1: phy@88ec000 { 2609 compatible = "qcom,sc8180x-qmp-usb3-uni-phy"; 2610 reg = <0 0x088ec000 0 0x1000>; 2611 2612 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2613 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2614 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2615 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 2616 clock-names = "aux", 2617 "ref", 2618 "com_aux", 2619 "pipe"; 2620 2621 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, 2622 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 2623 reset-names = "phy", "phy_phy"; 2624 2625 power-domains = <&gcc USB30_MP_GDSC>; 2626 2627 #clock-cells = <0>; 2628 clock-output-names = "usb2_phy1_pipe_clk"; 2629 2630 #phy-cells = <0>; 2631 2632 status = "disabled"; 2633 }; 2634 2635 usb_sec_qmpphy: phy@88ee000 { 2636 compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; 2637 reg = <0 0x088ed000 0 0x3000>; 2638 2639 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2640 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 2641 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2642 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2643 clock-names = "aux", 2644 "ref", 2645 "com_aux", 2646 "usb3_pipe"; 2647 resets = <&gcc GCC_USB3_DP_PHY_SEC_BCR>, 2648 <&gcc GCC_USB3_PHY_SEC_BCR>; 2649 reset-names = "phy", "common"; 2650 2651 #clock-cells = <1>; 2652 #phy-cells = <1>; 2653 2654 status = "disabled"; 2655 2656 ports { 2657 #address-cells = <1>; 2658 #size-cells = <0>; 2659 2660 port@0 { 2661 reg = <0>; 2662 2663 usb_sec_qmpphy_out: endpoint {}; 2664 }; 2665 2666 port@1 { 2667 reg = <1>; 2668 2669 usb_sec_qmpphy_usb_ss_in: endpoint { 2670 remote-endpoint = <&usb_sec_dwc3_ss>; 2671 }; 2672 }; 2673 2674 port@2 { 2675 reg = <2>; 2676 2677 usb_sec_qmpphy_dp_in: endpoint {}; 2678 }; 2679 }; 2680 }; 2681 2682 system-cache-controller@9200000 { 2683 compatible = "qcom,sc8180x-llcc"; 2684 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 2685 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 2686 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, 2687 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, 2688 <0 0x09600000 0 0x58000>; 2689 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2690 "llcc3_base", "llcc4_base", "llcc5_base", 2691 "llcc6_base", "llcc7_base", "llcc_broadcast_base"; 2692 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2693 }; 2694 2695 gem_noc: interconnect@9680000 { 2696 compatible = "qcom,sc8180x-gem-noc"; 2697 reg = <0 0x09680000 0 0x58200>; 2698 #interconnect-cells = <2>; 2699 qcom,bcm-voters = <&apps_bcm_voter>; 2700 }; 2701 2702 usb_mp: usb@a4f8800 { 2703 compatible = "qcom,sc8180x-dwc3-mp", "qcom,dwc3"; 2704 reg = <0 0x0a4f8800 0 0x400>; 2705 #address-cells = <2>; 2706 #size-cells = <2>; 2707 ranges; 2708 dma-ranges; 2709 2710 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, 2711 <&gcc GCC_USB30_MP_MASTER_CLK>, 2712 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, 2713 <&gcc GCC_USB30_MP_SLEEP_CLK>, 2714 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 2715 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 2716 clock-names = "cfg_noc", 2717 "core", 2718 "iface", 2719 "sleep", 2720 "mock_utmi", 2721 "xo"; 2722 2723 interconnects = <&aggre1_noc MASTER_USB3_2 0 &mc_virt SLAVE_EBI_CH0 0>, 2724 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_2 0>; 2725 interconnect-names = "usb-ddr", "apps-usb"; 2726 2727 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 2728 <&gcc GCC_USB30_MP_MASTER_CLK>; 2729 assigned-clock-rates = <19200000>, <200000000>; 2730 2731 interrupts-extended = <&intc GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>, 2732 <&intc GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH>, 2733 <&intc GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH>, 2734 <&intc GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH>, 2735 <&pdc 59 IRQ_TYPE_EDGE_BOTH>, 2736 <&pdc 46 IRQ_TYPE_EDGE_BOTH>, 2737 <&pdc 71 IRQ_TYPE_EDGE_BOTH>, 2738 <&pdc 68 IRQ_TYPE_EDGE_BOTH>, 2739 <&pdc 7 IRQ_TYPE_LEVEL_HIGH>, 2740 <&pdc 30 IRQ_TYPE_LEVEL_HIGH>; 2741 interrupt-names = "pwr_event_1", "pwr_event_2", 2742 "hs_phy_1", "hs_phy_2", 2743 "dp_hs_phy_1", "dm_hs_phy_1", 2744 "dp_hs_phy_2", "dm_hs_phy_2", 2745 "ss_phy_1", "ss_phy_2"; 2746 2747 power-domains = <&gcc USB30_MP_GDSC>; 2748 2749 resets = <&gcc GCC_USB30_MP_BCR>; 2750 2751 status = "disabled"; 2752 2753 usb_mp_dwc3: usb@a400000 { 2754 compatible = "snps,dwc3"; 2755 reg = <0 0x0a400000 0 0xcd00>; 2756 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>; 2757 iommus = <&apps_smmu 0x60 0>; 2758 snps,dis_u2_susphy_quirk; 2759 snps,dis_enblslpm_quirk; 2760 snps,dis-u1-entry-quirk; 2761 snps,dis-u2-entry-quirk; 2762 phys = <&usb_mp_hsphy0>, 2763 <&usb_mp_qmpphy0>, 2764 <&usb_mp_hsphy1>, 2765 <&usb_mp_qmpphy1>; 2766 phy-names = "usb2-0", 2767 "usb3-0", 2768 "usb2-1", 2769 "usb3-1"; 2770 dr_mode = "host"; 2771 }; 2772 }; 2773 2774 usb_prim: usb@a6f8800 { 2775 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3"; 2776 reg = <0 0x0a6f8800 0 0x400>; 2777 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2778 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2779 <&pdc 9 IRQ_TYPE_EDGE_BOTH>, 2780 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 2781 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; 2782 interrupt-names = "pwr_event", 2783 "hs_phy_irq", 2784 "dp_hs_phy_irq", 2785 "dm_hs_phy_irq", 2786 "ss_phy_irq"; 2787 2788 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2789 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2790 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2791 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2792 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2793 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 2794 clock-names = "cfg_noc", 2795 "core", 2796 "iface", 2797 "sleep", 2798 "mock_utmi", 2799 "xo"; 2800 resets = <&gcc GCC_USB30_PRIM_BCR>; 2801 power-domains = <&gcc USB30_PRIM_GDSC>; 2802 2803 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, 2804 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 2805 interconnect-names = "usb-ddr", "apps-usb"; 2806 2807 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2808 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2809 assigned-clock-rates = <19200000>, <200000000>; 2810 2811 #address-cells = <2>; 2812 #size-cells = <2>; 2813 ranges; 2814 dma-ranges; 2815 2816 status = "disabled"; 2817 2818 usb_prim_dwc3: usb@a600000 { 2819 compatible = "snps,dwc3"; 2820 reg = <0 0x0a600000 0 0xcd00>; 2821 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2822 iommus = <&apps_smmu 0x140 0>; 2823 snps,dis_u2_susphy_quirk; 2824 snps,dis_enblslpm_quirk; 2825 snps,dis-u1-entry-quirk; 2826 snps,dis-u2-entry-quirk; 2827 phys = <&usb_prim_hsphy>, <&usb_prim_qmpphy QMP_USB43DP_USB3_PHY>; 2828 phy-names = "usb2-phy", "usb3-phy"; 2829 2830 ports { 2831 #address-cells = <1>; 2832 #size-cells = <0>; 2833 2834 port@0 { 2835 reg = <0>; 2836 2837 usb_prim_dwc3_hs: endpoint { 2838 }; 2839 }; 2840 2841 port@1 { 2842 reg = <1>; 2843 2844 usb_prim_dwc3_ss: endpoint { 2845 remote-endpoint = <&usb_prim_qmpphy_usb_ss_in>; 2846 }; 2847 }; 2848 }; 2849 }; 2850 }; 2851 2852 usb_sec: usb@a8f8800 { 2853 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3"; 2854 reg = <0 0x0a8f8800 0 0x400>; 2855 2856 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2857 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2858 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2859 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2860 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2861 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 2862 clock-names = "cfg_noc", 2863 "core", 2864 "iface", 2865 "sleep", 2866 "mock_utmi", 2867 "xo"; 2868 resets = <&gcc GCC_USB30_SEC_BCR>; 2869 power-domains = <&gcc USB30_SEC_GDSC>; 2870 2871 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 2872 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2873 <&pdc 11 IRQ_TYPE_EDGE_BOTH>, 2874 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 2875 <&pdc 40 IRQ_TYPE_LEVEL_HIGH>; 2876 interrupt-names = "pwr_event", 2877 "hs_phy_irq", 2878 "dp_hs_phy_irq", 2879 "dm_hs_phy_irq", 2880 "ss_phy_irq"; 2881 2882 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2883 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2884 assigned-clock-rates = <19200000>, <200000000>; 2885 2886 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, 2887 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; 2888 interconnect-names = "usb-ddr", "apps-usb"; 2889 2890 #address-cells = <2>; 2891 #size-cells = <2>; 2892 ranges; 2893 dma-ranges; 2894 2895 status = "disabled"; 2896 2897 usb_sec_dwc3: usb@a800000 { 2898 compatible = "snps,dwc3"; 2899 reg = <0 0x0a800000 0 0xcd00>; 2900 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2901 iommus = <&apps_smmu 0x160 0>; 2902 snps,dis_u2_susphy_quirk; 2903 snps,dis_enblslpm_quirk; 2904 snps,dis-u1-entry-quirk; 2905 snps,dis-u2-entry-quirk; 2906 phys = <&usb_sec_hsphy>, <&usb_sec_qmpphy QMP_USB43DP_USB3_PHY>; 2907 phy-names = "usb2-phy", "usb3-phy"; 2908 2909 ports { 2910 #address-cells = <1>; 2911 #size-cells = <0>; 2912 2913 port@0 { 2914 reg = <0>; 2915 2916 usb_sec_dwc3_hs: endpoint { 2917 }; 2918 }; 2919 2920 port@1 { 2921 reg = <1>; 2922 2923 usb_sec_dwc3_ss: endpoint { 2924 remote-endpoint = <&usb_sec_qmpphy_usb_ss_in>; 2925 }; 2926 }; 2927 }; 2928 }; 2929 }; 2930 2931 videocc: clock-controller@ab00000 { 2932 compatible = "qcom,sc8180x-videocc", 2933 "qcom,sm8150-videocc"; 2934 reg = <0 0x0ab00000 0 0x10000>; 2935 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 2936 <&rpmhcc RPMH_CXO_CLK>; 2937 clock-names = "iface", "bi_tcxo"; 2938 power-domains = <&rpmhpd SC8180X_MMCX>; 2939 required-opps = <&rpmhpd_opp_low_svs>; 2940 #clock-cells = <1>; 2941 #reset-cells = <1>; 2942 #power-domain-cells = <1>; 2943 }; 2944 2945 camcc: clock-controller@ad00000 { 2946 compatible = "qcom,sc8180x-camcc"; 2947 reg = <0 0x0ad00000 0 0x20000>; 2948 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 2949 <&rpmhcc RPMH_CXO_CLK>, 2950 <&sleep_clk>; 2951 power-domains = <&rpmhpd SC8180X_MMCX>; 2952 required-opps = <&rpmhpd_opp_low_svs>; 2953 #clock-cells = <1>; 2954 #reset-cells = <1>; 2955 #power-domain-cells = <1>; 2956 }; 2957 2958 mdss: display-subsystem@ae00000 { 2959 compatible = "qcom,sc8180x-mdss"; 2960 reg = <0 0x0ae00000 0 0x1000>; 2961 reg-names = "mdss"; 2962 2963 power-domains = <&dispcc MDSS_GDSC>; 2964 2965 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2966 <&gcc GCC_DISP_HF_AXI_CLK>, 2967 <&gcc GCC_DISP_SF_AXI_CLK>, 2968 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2969 clock-names = "iface", 2970 "bus", 2971 "nrt_bus", 2972 "core"; 2973 2974 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2975 2976 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2977 interrupt-controller; 2978 #interrupt-cells = <1>; 2979 2980 interconnects = <&mmss_noc MASTER_MDP_PORT0 QCOM_ICC_TAG_ALWAYS 2981 &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, 2982 <&mmss_noc MASTER_MDP_PORT1 QCOM_ICC_TAG_ALWAYS 2983 &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, 2984 <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS 2985 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>; 2986 interconnect-names = "mdp0-mem", 2987 "mdp1-mem", 2988 "cpu-cfg"; 2989 2990 iommus = <&apps_smmu 0x800 0x420>; 2991 2992 #address-cells = <2>; 2993 #size-cells = <2>; 2994 ranges; 2995 2996 status = "disabled"; 2997 2998 mdss_mdp: display-controller@ae01000 { 2999 compatible = "qcom,sc8180x-dpu"; 3000 reg = <0 0x0ae01000 0 0x8f000>, 3001 <0 0x0aeb0000 0 0x3000>; 3002 reg-names = "mdp", "vbif"; 3003 3004 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3005 <&gcc GCC_DISP_HF_AXI_CLK>, 3006 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3007 <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3008 <&dispcc DISP_CC_MDSS_ROT_CLK>, 3009 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; 3010 clock-names = "iface", 3011 "bus", 3012 "core", 3013 "vsync", 3014 "rot", 3015 "lut"; 3016 3017 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3018 assigned-clock-rates = <19200000>; 3019 3020 operating-points-v2 = <&mdp_opp_table>; 3021 power-domains = <&rpmhpd SC8180X_MMCX>; 3022 3023 interrupt-parent = <&mdss>; 3024 interrupts = <0>; 3025 3026 ports { 3027 #address-cells = <1>; 3028 #size-cells = <0>; 3029 3030 port@0 { 3031 reg = <0>; 3032 dpu_intf0_out: endpoint { 3033 remote-endpoint = <&dp0_in>; 3034 }; 3035 }; 3036 3037 port@1 { 3038 reg = <1>; 3039 dpu_intf1_out: endpoint { 3040 remote-endpoint = <&mdss_dsi0_in>; 3041 }; 3042 }; 3043 3044 port@2 { 3045 reg = <2>; 3046 dpu_intf2_out: endpoint { 3047 remote-endpoint = <&mdss_dsi1_in>; 3048 }; 3049 }; 3050 3051 port@4 { 3052 reg = <4>; 3053 dpu_intf4_out: endpoint { 3054 remote-endpoint = <&dp1_in>; 3055 }; 3056 }; 3057 3058 port@5 { 3059 reg = <5>; 3060 dpu_intf5_out: endpoint { 3061 remote-endpoint = <&edp_in>; 3062 }; 3063 }; 3064 }; 3065 3066 mdp_opp_table: opp-table { 3067 compatible = "operating-points-v2"; 3068 3069 opp-200000000 { 3070 opp-hz = /bits/ 64 <200000000>; 3071 required-opps = <&rpmhpd_opp_low_svs>; 3072 }; 3073 3074 opp-300000000 { 3075 opp-hz = /bits/ 64 <300000000>; 3076 required-opps = <&rpmhpd_opp_svs>; 3077 }; 3078 3079 opp-345000000 { 3080 opp-hz = /bits/ 64 <345000000>; 3081 required-opps = <&rpmhpd_opp_svs_l1>; 3082 }; 3083 3084 opp-460000000 { 3085 opp-hz = /bits/ 64 <460000000>; 3086 required-opps = <&rpmhpd_opp_nom>; 3087 }; 3088 }; 3089 }; 3090 3091 mdss_dsi0: dsi@ae94000 { 3092 compatible = "qcom,sc8180x-dsi-ctrl", 3093 "qcom,mdss-dsi-ctrl"; 3094 reg = <0 0x0ae94000 0 0x400>; 3095 reg-names = "dsi_ctrl"; 3096 3097 interrupt-parent = <&mdss>; 3098 interrupts = <4>; 3099 3100 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3101 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3102 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3103 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3104 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3105 <&gcc GCC_DISP_HF_AXI_CLK>; 3106 clock-names = "byte", 3107 "byte_intf", 3108 "pixel", 3109 "core", 3110 "iface", 3111 "bus"; 3112 3113 operating-points-v2 = <&dsi_opp_table>; 3114 power-domains = <&rpmhpd SC8180X_MMCX>; 3115 3116 phys = <&mdss_dsi0_phy>; 3117 phy-names = "dsi"; 3118 3119 status = "disabled"; 3120 3121 ports { 3122 #address-cells = <1>; 3123 #size-cells = <0>; 3124 3125 port@0 { 3126 reg = <0>; 3127 mdss_dsi0_in: endpoint { 3128 remote-endpoint = <&dpu_intf1_out>; 3129 }; 3130 }; 3131 3132 port@1 { 3133 reg = <1>; 3134 mdss_dsi0_out: endpoint { 3135 }; 3136 }; 3137 }; 3138 3139 dsi_opp_table: opp-table { 3140 compatible = "operating-points-v2"; 3141 3142 opp-187500000 { 3143 opp-hz = /bits/ 64 <187500000>; 3144 required-opps = <&rpmhpd_opp_low_svs>; 3145 }; 3146 3147 opp-300000000 { 3148 opp-hz = /bits/ 64 <300000000>; 3149 required-opps = <&rpmhpd_opp_svs>; 3150 }; 3151 3152 opp-358000000 { 3153 opp-hz = /bits/ 64 <358000000>; 3154 required-opps = <&rpmhpd_opp_svs_l1>; 3155 }; 3156 }; 3157 }; 3158 3159 mdss_dsi0_phy: phy@ae94400 { 3160 compatible = "qcom,dsi-phy-7nm"; 3161 reg = <0 0x0ae94400 0 0x200>, 3162 <0 0x0ae94600 0 0x280>, 3163 <0 0x0ae94900 0 0x260>; 3164 reg-names = "dsi_phy", 3165 "dsi_phy_lane", 3166 "dsi_pll"; 3167 3168 #clock-cells = <1>; 3169 #phy-cells = <0>; 3170 3171 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3172 <&rpmhcc RPMH_CXO_CLK>; 3173 clock-names = "iface", "ref"; 3174 3175 status = "disabled"; 3176 }; 3177 3178 mdss_dsi1: dsi@ae96000 { 3179 compatible = "qcom,sc8180x-dsi-ctrl", 3180 "qcom,mdss-dsi-ctrl"; 3181 reg = <0 0x0ae96000 0 0x400>; 3182 reg-names = "dsi_ctrl"; 3183 3184 interrupt-parent = <&mdss>; 3185 interrupts = <5>; 3186 3187 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3188 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3189 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3190 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3191 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3192 <&gcc GCC_DISP_HF_AXI_CLK>; 3193 clock-names = "byte", 3194 "byte_intf", 3195 "pixel", 3196 "core", 3197 "iface", 3198 "bus"; 3199 3200 operating-points-v2 = <&dsi_opp_table>; 3201 power-domains = <&rpmhpd SC8180X_MMCX>; 3202 3203 phys = <&mdss_dsi1_phy>; 3204 phy-names = "dsi"; 3205 3206 status = "disabled"; 3207 3208 ports { 3209 #address-cells = <1>; 3210 #size-cells = <0>; 3211 3212 port@0 { 3213 reg = <0>; 3214 mdss_dsi1_in: endpoint { 3215 remote-endpoint = <&dpu_intf2_out>; 3216 }; 3217 }; 3218 3219 port@1 { 3220 reg = <1>; 3221 mdss_dsi1_out: endpoint { 3222 }; 3223 }; 3224 }; 3225 }; 3226 3227 mdss_dsi1_phy: phy@ae96400 { 3228 compatible = "qcom,dsi-phy-7nm"; 3229 reg = <0 0x0ae96400 0 0x200>, 3230 <0 0x0ae96600 0 0x280>, 3231 <0 0x0ae96900 0 0x260>; 3232 reg-names = "dsi_phy", 3233 "dsi_phy_lane", 3234 "dsi_pll"; 3235 3236 #clock-cells = <1>; 3237 #phy-cells = <0>; 3238 3239 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3240 <&rpmhcc RPMH_CXO_CLK>; 3241 clock-names = "iface", "ref"; 3242 3243 status = "disabled"; 3244 }; 3245 3246 mdss_dp0: displayport-controller@ae90000 { 3247 compatible = "qcom,sc8180x-dp"; 3248 reg = <0 0xae90000 0 0x200>, 3249 <0 0xae90200 0 0x200>, 3250 <0 0xae90400 0 0x600>, 3251 <0 0xae90a00 0 0x400>, 3252 <0 0xae91000 0 0x400>; 3253 interrupt-parent = <&mdss>; 3254 interrupts = <12>; 3255 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3256 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3257 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3258 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3259 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, 3260 <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; 3261 clock-names = "core_iface", 3262 "core_aux", 3263 "ctrl_link", 3264 "ctrl_link_iface", 3265 "stream_pixel", 3266 "stream_1_pixel"; 3267 3268 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3269 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>, 3270 <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; 3271 assigned-clock-parents = <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3272 <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3273 <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3274 3275 phys = <&usb_prim_qmpphy QMP_USB43DP_DP_PHY>; 3276 phy-names = "dp"; 3277 3278 #sound-dai-cells = <0>; 3279 3280 operating-points-v2 = <&dp0_opp_table>; 3281 power-domains = <&rpmhpd SC8180X_MMCX>; 3282 3283 status = "disabled"; 3284 3285 ports { 3286 #address-cells = <1>; 3287 #size-cells = <0>; 3288 3289 port@0 { 3290 reg = <0>; 3291 dp0_in: endpoint { 3292 remote-endpoint = <&dpu_intf0_out>; 3293 }; 3294 }; 3295 3296 port@1 { 3297 reg = <1>; 3298 mdss_dp0_out: endpoint { 3299 }; 3300 }; 3301 }; 3302 3303 dp0_opp_table: opp-table { 3304 compatible = "operating-points-v2"; 3305 3306 opp-160000000 { 3307 opp-hz = /bits/ 64 <160000000>; 3308 required-opps = <&rpmhpd_opp_low_svs>; 3309 }; 3310 3311 opp-270000000 { 3312 opp-hz = /bits/ 64 <270000000>; 3313 required-opps = <&rpmhpd_opp_svs>; 3314 }; 3315 3316 opp-540000000 { 3317 opp-hz = /bits/ 64 <540000000>; 3318 required-opps = <&rpmhpd_opp_svs_l1>; 3319 }; 3320 3321 opp-810000000 { 3322 opp-hz = /bits/ 64 <810000000>; 3323 required-opps = <&rpmhpd_opp_nom>; 3324 }; 3325 }; 3326 }; 3327 3328 mdss_dp1: displayport-controller@ae98000 { 3329 compatible = "qcom,sc8180x-dp"; 3330 reg = <0 0xae98000 0 0x200>, 3331 <0 0xae98200 0 0x200>, 3332 <0 0xae98400 0 0x600>, 3333 <0 0xae98a00 0 0x400>, 3334 <0 0xae99000 0 0x400>; 3335 interrupt-parent = <&mdss>; 3336 interrupts = <13>; 3337 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3338 <&dispcc DISP_CC_MDSS_DP_AUX1_CLK>, 3339 <&dispcc DISP_CC_MDSS_DP_LINK1_CLK>, 3340 <&dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>, 3341 <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>, 3342 <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; 3343 clock-names = "core_iface", 3344 "core_aux", 3345 "ctrl_link", 3346 "ctrl_link_iface", 3347 "stream_pixel", 3348 "stream_1_pixel"; 3349 3350 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>, 3351 <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>, 3352 <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>; 3353 assigned-clock-parents = <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3354 <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3355 <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3356 3357 phys = <&usb_sec_qmpphy QMP_USB43DP_DP_PHY>; 3358 phy-names = "dp"; 3359 3360 #sound-dai-cells = <0>; 3361 3362 operating-points-v2 = <&dp0_opp_table>; 3363 power-domains = <&rpmhpd SC8180X_MMCX>; 3364 3365 status = "disabled"; 3366 3367 ports { 3368 #address-cells = <1>; 3369 #size-cells = <0>; 3370 3371 port@0 { 3372 reg = <0>; 3373 dp1_in: endpoint { 3374 remote-endpoint = <&dpu_intf4_out>; 3375 }; 3376 }; 3377 3378 port@1 { 3379 reg = <1>; 3380 mdss_dp1_out: endpoint { 3381 }; 3382 }; 3383 }; 3384 3385 dp1_opp_table: opp-table { 3386 compatible = "operating-points-v2"; 3387 3388 opp-160000000 { 3389 opp-hz = /bits/ 64 <160000000>; 3390 required-opps = <&rpmhpd_opp_low_svs>; 3391 }; 3392 3393 opp-270000000 { 3394 opp-hz = /bits/ 64 <270000000>; 3395 required-opps = <&rpmhpd_opp_svs>; 3396 }; 3397 3398 opp-540000000 { 3399 opp-hz = /bits/ 64 <540000000>; 3400 required-opps = <&rpmhpd_opp_svs_l1>; 3401 }; 3402 3403 opp-810000000 { 3404 opp-hz = /bits/ 64 <810000000>; 3405 required-opps = <&rpmhpd_opp_nom>; 3406 }; 3407 }; 3408 }; 3409 3410 mdss_edp: displayport-controller@ae9a000 { 3411 compatible = "qcom,sc8180x-edp"; 3412 reg = <0 0xae9a000 0 0x200>, 3413 <0 0xae9a200 0 0x200>, 3414 <0 0xae9a400 0 0x600>, 3415 <0 0xae9aa00 0 0x400>, 3416 <0 0xae9b000 0 0x400>; 3417 interrupt-parent = <&mdss>; 3418 interrupts = <14>; 3419 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3420 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3421 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 3422 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 3423 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 3424 clock-names = "core_iface", 3425 "core_aux", 3426 "ctrl_link", 3427 "ctrl_link_iface", 3428 "stream_pixel"; 3429 3430 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 3431 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 3432 assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>; 3433 3434 phys = <&edp_phy>; 3435 phy-names = "dp"; 3436 3437 operating-points-v2 = <&edp_opp_table>; 3438 power-domains = <&rpmhpd SC8180X_MMCX>; 3439 3440 status = "disabled"; 3441 3442 ports { 3443 #address-cells = <1>; 3444 #size-cells = <0>; 3445 3446 port@0 { 3447 reg = <0>; 3448 edp_in: endpoint { 3449 remote-endpoint = <&dpu_intf5_out>; 3450 }; 3451 }; 3452 3453 port@1 { 3454 reg = <1>; 3455 3456 mdss_edp_out: endpoint { 3457 }; 3458 }; 3459 }; 3460 3461 edp_opp_table: opp-table { 3462 compatible = "operating-points-v2"; 3463 3464 opp-160000000 { 3465 opp-hz = /bits/ 64 <160000000>; 3466 required-opps = <&rpmhpd_opp_low_svs>; 3467 }; 3468 3469 opp-270000000 { 3470 opp-hz = /bits/ 64 <270000000>; 3471 required-opps = <&rpmhpd_opp_svs>; 3472 }; 3473 3474 opp-540000000 { 3475 opp-hz = /bits/ 64 <540000000>; 3476 required-opps = <&rpmhpd_opp_svs_l1>; 3477 }; 3478 3479 opp-810000000 { 3480 opp-hz = /bits/ 64 <810000000>; 3481 required-opps = <&rpmhpd_opp_nom>; 3482 }; 3483 }; 3484 }; 3485 }; 3486 3487 edp_phy: phy@aec2a00 { 3488 compatible = "qcom,sc8180x-edp-phy"; 3489 reg = <0 0x0aec2a00 0 0x1c0>, 3490 <0 0x0aec2200 0 0xa0>, 3491 <0 0x0aec2600 0 0xa0>, 3492 <0 0x0aec2000 0 0x19c>; 3493 3494 clocks = <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3495 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3496 clock-names = "aux", "cfg_ahb"; 3497 3498 power-domains = <&rpmhpd SC8180X_MX>; 3499 3500 #clock-cells = <1>; 3501 #phy-cells = <0>; 3502 }; 3503 3504 dispcc: clock-controller@af00000 { 3505 compatible = "qcom,sc8180x-dispcc"; 3506 reg = <0 0x0af00000 0 0x20000>; 3507 clocks = <&rpmhcc RPMH_CXO_CLK>, 3508 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 3509 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 3510 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 3511 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 3512 <&usb_prim_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3513 <&usb_prim_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3514 <&edp_phy 0>, 3515 <&edp_phy 1>, 3516 <&usb_sec_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3517 <&usb_sec_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3518 clock-names = "bi_tcxo", 3519 "dsi0_phy_pll_out_byteclk", 3520 "dsi0_phy_pll_out_dsiclk", 3521 "dsi1_phy_pll_out_byteclk", 3522 "dsi1_phy_pll_out_dsiclk", 3523 "dp_phy_pll_link_clk", 3524 "dp_phy_pll_vco_div_clk", 3525 "edp_phy_pll_link_clk", 3526 "edp_phy_pll_vco_div_clk", 3527 "dptx1_phy_pll_link_clk", 3528 "dptx1_phy_pll_vco_div_clk"; 3529 power-domains = <&rpmhpd SC8180X_MMCX>; 3530 required-opps = <&rpmhpd_opp_low_svs>; 3531 #clock-cells = <1>; 3532 #reset-cells = <1>; 3533 #power-domain-cells = <1>; 3534 }; 3535 3536 pdc: interrupt-controller@b220000 { 3537 compatible = "qcom,sc8180x-pdc", "qcom,pdc"; 3538 reg = <0 0x0b220000 0 0x30000>; 3539 qcom,pdc-ranges = <0 480 94>, <94 609 31>; 3540 #interrupt-cells = <2>; 3541 interrupt-parent = <&intc>; 3542 interrupt-controller; 3543 }; 3544 3545 tsens0: thermal-sensor@c263000 { 3546 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2"; 3547 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3548 <0 0x0c222000 0 0x1ff>; /* SROT */ 3549 #qcom,sensors = <16>; 3550 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3551 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3552 interrupt-names = "uplow", "critical"; 3553 #thermal-sensor-cells = <1>; 3554 }; 3555 3556 tsens1: thermal-sensor@c265000 { 3557 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2"; 3558 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3559 <0 0x0c223000 0 0x1ff>; /* SROT */ 3560 #qcom,sensors = <9>; 3561 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3562 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3563 interrupt-names = "uplow", "critical"; 3564 #thermal-sensor-cells = <1>; 3565 }; 3566 3567 aoss_qmp: power-management@c300000 { 3568 compatible = "qcom,sc8180x-aoss-qmp", "qcom,aoss-qmp"; 3569 reg = <0x0 0x0c300000 0x0 0x400>; 3570 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3571 mboxes = <&apss_shared 0>; 3572 3573 #clock-cells = <0>; 3574 }; 3575 3576 sram@c3f0000 { 3577 compatible = "qcom,rpmh-stats"; 3578 reg = <0x0 0x0c3f0000 0x0 0x400>; 3579 }; 3580 3581 spmi_bus: spmi@c440000 { 3582 compatible = "qcom,spmi-pmic-arb"; 3583 reg = <0x0 0x0c440000 0x0 0x0001100>, 3584 <0x0 0x0c600000 0x0 0x2000000>, 3585 <0x0 0x0e600000 0x0 0x0100000>, 3586 <0x0 0x0e700000 0x0 0x00a0000>, 3587 <0x0 0x0c40a000 0x0 0x0026000>; 3588 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3589 interrupt-names = "periph_irq"; 3590 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3591 qcom,ee = <0>; 3592 qcom,channel = <0>; 3593 #address-cells = <2>; 3594 #size-cells = <0>; 3595 interrupt-controller; 3596 #interrupt-cells = <4>; 3597 }; 3598 3599 apps_smmu: iommu@15000000 { 3600 compatible = "qcom,sc8180x-smmu-500", "arm,mmu-500"; 3601 reg = <0 0x15000000 0 0x100000>; 3602 #iommu-cells = <2>; 3603 #global-interrupts = <1>; 3604 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3605 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3606 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3607 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3608 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3609 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3610 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3611 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3612 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3613 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3614 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3615 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3616 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3617 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3618 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3619 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3620 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3621 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3622 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3623 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3624 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3625 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3626 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3627 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3628 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3629 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3630 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3631 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3632 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3633 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3634 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3635 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3636 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3637 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3638 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3639 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3640 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3641 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3642 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3643 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3644 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3645 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3646 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3647 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3648 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3649 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3650 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3651 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3652 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3653 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3654 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3655 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3656 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3657 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3658 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3659 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3660 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3661 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3662 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3663 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3664 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3665 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3666 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3667 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3668 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3669 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3670 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3671 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3672 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3673 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3674 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3675 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3676 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3677 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3678 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3679 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3680 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3681 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3682 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3683 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3684 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3685 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3686 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3687 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3688 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 3689 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 3690 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 3691 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 3692 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 3693 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 3694 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 3695 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 3696 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 3697 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 3698 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 3699 <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>, 3700 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>, 3701 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 3702 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>, 3703 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, 3704 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 3705 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, 3706 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>, 3707 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 3708 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 3709 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 3710 <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>; 3711 dma-coherent; 3712 }; 3713 3714 remoteproc_adsp: remoteproc@17300000 { 3715 compatible = "qcom,sc8180x-adsp-pas"; 3716 reg = <0x0 0x17300000 0x0 0x4040>; 3717 3718 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 3719 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3720 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3721 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3722 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3723 interrupt-names = "wdog", "fatal", "ready", 3724 "handover", "stop-ack"; 3725 3726 clocks = <&rpmhcc RPMH_CXO_CLK>; 3727 clock-names = "xo"; 3728 3729 power-domains = <&rpmhpd SC8180X_CX>; 3730 power-domain-names = "cx"; 3731 3732 qcom,qmp = <&aoss_qmp>; 3733 3734 qcom,smem-states = <&adsp_smp2p_out 0>; 3735 qcom,smem-state-names = "stop"; 3736 3737 status = "disabled"; 3738 3739 remoteproc_adsp_glink: glink-edge { 3740 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3741 label = "lpass"; 3742 qcom,remote-pid = <2>; 3743 mboxes = <&apss_shared 8>; 3744 }; 3745 }; 3746 3747 intc: interrupt-controller@17a00000 { 3748 compatible = "arm,gic-v3"; 3749 interrupt-controller; 3750 #address-cells = <0>; 3751 #interrupt-cells = <3>; 3752 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3753 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3754 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3755 #redistributor-regions = <1>; 3756 redistributor-stride = <0 0x20000>; 3757 }; 3758 3759 apss_shared: mailbox@17c00000 { 3760 compatible = "qcom,sc8180x-apss-shared", "qcom,sdm845-apss-shared"; 3761 reg = <0x0 0x17c00000 0x0 0x1000>; 3762 #mbox-cells = <1>; 3763 }; 3764 3765 timer@17c20000 { 3766 compatible = "arm,armv7-timer-mem"; 3767 reg = <0x0 0x17c20000 0x0 0x1000>; 3768 3769 #address-cells = <1>; 3770 #size-cells = <1>; 3771 ranges = <0 0 0 0x20000000>; 3772 3773 frame@17c21000 { 3774 reg = <0x17c21000 0x1000>, 3775 <0x17c22000 0x1000>; 3776 frame-number = <0>; 3777 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3778 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3779 }; 3780 3781 frame@17c23000 { 3782 reg = <0x17c23000 0x1000>; 3783 frame-number = <1>; 3784 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3785 status = "disabled"; 3786 }; 3787 3788 frame@17c25000 { 3789 reg = <0x17c25000 0x1000>; 3790 frame-number = <2>; 3791 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3792 status = "disabled"; 3793 }; 3794 3795 frame@17c27000 { 3796 reg = <0x17c26000 0x1000>; 3797 frame-number = <3>; 3798 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3799 status = "disabled"; 3800 }; 3801 3802 frame@17c29000 { 3803 reg = <0x17c29000 0x1000>; 3804 frame-number = <4>; 3805 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3806 status = "disabled"; 3807 }; 3808 3809 frame@17c2b000 { 3810 reg = <0x17c2b000 0x1000>; 3811 frame-number = <5>; 3812 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3813 status = "disabled"; 3814 }; 3815 3816 frame@17c2d000 { 3817 reg = <0x17c2d000 0x1000>; 3818 frame-number = <6>; 3819 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3820 status = "disabled"; 3821 }; 3822 }; 3823 3824 apps_rsc: rsc@18200000 { 3825 compatible = "qcom,rpmh-rsc"; 3826 reg = <0x0 0x18200000 0x0 0x10000>, 3827 <0x0 0x18210000 0x0 0x10000>, 3828 <0x0 0x18220000 0x0 0x10000>; 3829 reg-names = "drv-0", "drv-1", "drv-2"; 3830 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3831 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3832 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3833 qcom,tcs-offset = <0xd00>; 3834 qcom,drv-id = <2>; 3835 qcom,tcs-config = <ACTIVE_TCS 2>, 3836 <SLEEP_TCS 1>, 3837 <WAKE_TCS 1>, 3838 <CONTROL_TCS 0>; 3839 label = "apps_rsc"; 3840 power-domains = <&cluster_pd>; 3841 3842 apps_bcm_voter: bcm-voter { 3843 compatible = "qcom,bcm-voter"; 3844 }; 3845 3846 rpmhcc: clock-controller { 3847 compatible = "qcom,sc8180x-rpmh-clk"; 3848 #clock-cells = <1>; 3849 clock-names = "xo"; 3850 clocks = <&xo_board_clk>; 3851 }; 3852 3853 rpmhpd: power-controller { 3854 compatible = "qcom,sc8180x-rpmhpd"; 3855 #power-domain-cells = <1>; 3856 operating-points-v2 = <&rpmhpd_opp_table>; 3857 3858 rpmhpd_opp_table: opp-table { 3859 compatible = "operating-points-v2"; 3860 3861 rpmhpd_opp_ret: opp1 { 3862 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3863 }; 3864 3865 rpmhpd_opp_min_svs: opp2 { 3866 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3867 }; 3868 3869 rpmhpd_opp_low_svs: opp3 { 3870 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3871 }; 3872 3873 rpmhpd_opp_svs: opp4 { 3874 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3875 }; 3876 3877 rpmhpd_opp_svs_l1: opp5 { 3878 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3879 }; 3880 3881 rpmhpd_opp_nom: opp6 { 3882 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3883 }; 3884 3885 rpmhpd_opp_nom_l1: opp7 { 3886 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3887 }; 3888 3889 rpmhpd_opp_nom_l2: opp8 { 3890 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3891 }; 3892 3893 rpmhpd_opp_turbo: opp9 { 3894 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3895 }; 3896 3897 rpmhpd_opp_turbo_l1: opp10 { 3898 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3899 }; 3900 }; 3901 }; 3902 }; 3903 3904 osm_l3: interconnect@18321000 { 3905 compatible = "qcom,sc8180x-osm-l3", "qcom,osm-l3"; 3906 reg = <0 0x18321000 0 0x1400>; 3907 3908 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3909 clock-names = "xo", "alternate"; 3910 3911 #interconnect-cells = <1>; 3912 }; 3913 3914 lmh@18350800 { 3915 compatible = "qcom,sc8180x-lmh"; 3916 reg = <0 0x18350800 0 0x400>; 3917 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3918 cpus = <&cpu4>; 3919 qcom,lmh-temp-arm-millicelsius = <65000>; 3920 qcom,lmh-temp-low-millicelsius = <94500>; 3921 qcom,lmh-temp-high-millicelsius = <95000>; 3922 interrupt-controller; 3923 #interrupt-cells = <1>; 3924 }; 3925 3926 lmh@18358800 { 3927 compatible = "qcom,sc8180x-lmh"; 3928 reg = <0 0x18358800 0 0x400>; 3929 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3930 cpus = <&cpu0>; 3931 qcom,lmh-temp-arm-millicelsius = <65000>; 3932 qcom,lmh-temp-low-millicelsius = <94500>; 3933 qcom,lmh-temp-high-millicelsius = <95000>; 3934 interrupt-controller; 3935 #interrupt-cells = <1>; 3936 }; 3937 3938 cpufreq_hw: cpufreq@18323000 { 3939 compatible = "qcom,sc8180x-cpufreq-hw", "qcom,cpufreq-hw"; 3940 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 3941 reg-names = "freq-domain0", "freq-domain1"; 3942 3943 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3944 clock-names = "xo", "alternate"; 3945 3946 #freq-domain-cells = <1>; 3947 #clock-cells = <1>; 3948 }; 3949 3950 wifi: wifi@18800000 { 3951 compatible = "qcom,wcn3990-wifi"; 3952 reg = <0 0x18800000 0 0x800000>; 3953 reg-names = "membase"; 3954 clock-names = "cxo_ref_clk_pin"; 3955 clocks = <&rpmhcc RPMH_RF_CLK2>; 3956 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 3957 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 3958 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 3959 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 3960 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3961 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3962 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 3963 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3964 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3965 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3966 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3967 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 3968 iommus = <&apps_smmu 0x0640 0x1>; 3969 qcom,msa-fixed-perm; 3970 status = "disabled"; 3971 }; 3972 }; 3973 3974 thermal-zones { 3975 cpu0-thermal { 3976 polling-delay-passive = <250>; 3977 3978 thermal-sensors = <&tsens0 1>; 3979 3980 trips { 3981 cpu-crit { 3982 temperature = <110000>; 3983 hysteresis = <1000>; 3984 type = "critical"; 3985 }; 3986 }; 3987 }; 3988 3989 cpu1-thermal { 3990 polling-delay-passive = <250>; 3991 3992 thermal-sensors = <&tsens0 2>; 3993 3994 trips { 3995 cpu-crit { 3996 temperature = <110000>; 3997 hysteresis = <1000>; 3998 type = "critical"; 3999 }; 4000 }; 4001 }; 4002 4003 cpu2-thermal { 4004 polling-delay-passive = <250>; 4005 4006 thermal-sensors = <&tsens0 3>; 4007 4008 trips { 4009 cpu-crit { 4010 temperature = <110000>; 4011 hysteresis = <1000>; 4012 type = "critical"; 4013 }; 4014 }; 4015 }; 4016 4017 cpu3-thermal { 4018 polling-delay-passive = <250>; 4019 4020 thermal-sensors = <&tsens0 4>; 4021 4022 trips { 4023 cpu-crit { 4024 temperature = <110000>; 4025 hysteresis = <1000>; 4026 type = "critical"; 4027 }; 4028 }; 4029 }; 4030 4031 cpu4-top-thermal { 4032 polling-delay-passive = <250>; 4033 4034 thermal-sensors = <&tsens0 7>; 4035 4036 trips { 4037 cpu-crit { 4038 temperature = <110000>; 4039 hysteresis = <1000>; 4040 type = "critical"; 4041 }; 4042 }; 4043 }; 4044 4045 cpu5-top-thermal { 4046 polling-delay-passive = <250>; 4047 4048 thermal-sensors = <&tsens0 8>; 4049 4050 trips { 4051 cpu-crit { 4052 temperature = <110000>; 4053 hysteresis = <1000>; 4054 type = "critical"; 4055 }; 4056 }; 4057 }; 4058 4059 cpu6-top-thermal { 4060 polling-delay-passive = <250>; 4061 4062 thermal-sensors = <&tsens0 9>; 4063 4064 trips { 4065 cpu-crit { 4066 temperature = <110000>; 4067 hysteresis = <1000>; 4068 type = "critical"; 4069 }; 4070 }; 4071 }; 4072 4073 cpu7-top-thermal { 4074 polling-delay-passive = <250>; 4075 4076 thermal-sensors = <&tsens0 10>; 4077 4078 trips { 4079 cpu-crit { 4080 temperature = <110000>; 4081 hysteresis = <1000>; 4082 type = "critical"; 4083 }; 4084 }; 4085 }; 4086 4087 cpu4-bottom-thermal { 4088 polling-delay-passive = <250>; 4089 4090 thermal-sensors = <&tsens0 11>; 4091 4092 trips { 4093 cpu-crit { 4094 temperature = <110000>; 4095 hysteresis = <1000>; 4096 type = "critical"; 4097 }; 4098 }; 4099 }; 4100 4101 cpu5-bottom-thermal { 4102 polling-delay-passive = <250>; 4103 4104 thermal-sensors = <&tsens0 12>; 4105 4106 trips { 4107 cpu-crit { 4108 temperature = <110000>; 4109 hysteresis = <1000>; 4110 type = "critical"; 4111 }; 4112 }; 4113 }; 4114 4115 cpu6-bottom-thermal { 4116 polling-delay-passive = <250>; 4117 4118 thermal-sensors = <&tsens0 13>; 4119 4120 trips { 4121 cpu-crit { 4122 temperature = <110000>; 4123 hysteresis = <1000>; 4124 type = "critical"; 4125 }; 4126 }; 4127 }; 4128 4129 cpu7-bottom-thermal { 4130 polling-delay-passive = <250>; 4131 4132 thermal-sensors = <&tsens0 14>; 4133 4134 trips { 4135 cpu-crit { 4136 temperature = <110000>; 4137 hysteresis = <1000>; 4138 type = "critical"; 4139 }; 4140 }; 4141 }; 4142 4143 aoss0-thermal { 4144 polling-delay-passive = <250>; 4145 4146 thermal-sensors = <&tsens0 0>; 4147 4148 trips { 4149 trip-point0 { 4150 temperature = <90000>; 4151 hysteresis = <2000>; 4152 type = "hot"; 4153 }; 4154 }; 4155 }; 4156 4157 cluster0-thermal { 4158 polling-delay-passive = <250>; 4159 4160 thermal-sensors = <&tsens0 5>; 4161 4162 trips { 4163 cluster-crit { 4164 temperature = <110000>; 4165 hysteresis = <2000>; 4166 type = "critical"; 4167 }; 4168 }; 4169 }; 4170 4171 cluster1-thermal { 4172 polling-delay-passive = <250>; 4173 4174 thermal-sensors = <&tsens0 6>; 4175 4176 trips { 4177 cluster-crit { 4178 temperature = <110000>; 4179 hysteresis = <2000>; 4180 type = "critical"; 4181 }; 4182 }; 4183 }; 4184 4185 gpu-top-thermal { 4186 polling-delay-passive = <250>; 4187 4188 thermal-sensors = <&tsens0 15>; 4189 4190 cooling-maps { 4191 map0 { 4192 trip = <&gpu_top_alert0>; 4193 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4194 }; 4195 }; 4196 4197 trips { 4198 gpu_top_alert0: trip-point0 { 4199 temperature = <85000>; 4200 hysteresis = <1000>; 4201 type = "passive"; 4202 }; 4203 4204 trip-point1 { 4205 temperature = <90000>; 4206 hysteresis = <1000>; 4207 type = "hot"; 4208 }; 4209 4210 trip-point2 { 4211 temperature = <110000>; 4212 hysteresis = <1000>; 4213 type = "critical"; 4214 }; 4215 }; 4216 }; 4217 4218 aoss1-thermal { 4219 polling-delay-passive = <250>; 4220 4221 thermal-sensors = <&tsens1 0>; 4222 4223 trips { 4224 trip-point0 { 4225 temperature = <90000>; 4226 hysteresis = <2000>; 4227 type = "hot"; 4228 }; 4229 }; 4230 }; 4231 4232 wlan-thermal { 4233 polling-delay-passive = <250>; 4234 4235 thermal-sensors = <&tsens1 1>; 4236 4237 trips { 4238 trip-point0 { 4239 temperature = <90000>; 4240 hysteresis = <2000>; 4241 type = "hot"; 4242 }; 4243 }; 4244 }; 4245 4246 video-thermal { 4247 polling-delay-passive = <250>; 4248 4249 thermal-sensors = <&tsens1 2>; 4250 4251 trips { 4252 trip-point0 { 4253 temperature = <90000>; 4254 hysteresis = <2000>; 4255 type = "hot"; 4256 }; 4257 }; 4258 }; 4259 4260 mem-thermal { 4261 polling-delay-passive = <250>; 4262 4263 thermal-sensors = <&tsens1 3>; 4264 4265 trips { 4266 trip-point0 { 4267 temperature = <90000>; 4268 hysteresis = <2000>; 4269 type = "hot"; 4270 }; 4271 }; 4272 }; 4273 4274 q6-hvx-thermal { 4275 polling-delay-passive = <250>; 4276 4277 thermal-sensors = <&tsens1 4>; 4278 4279 trips { 4280 trip-point0 { 4281 temperature = <90000>; 4282 hysteresis = <2000>; 4283 type = "hot"; 4284 }; 4285 }; 4286 }; 4287 4288 camera-thermal { 4289 polling-delay-passive = <250>; 4290 4291 thermal-sensors = <&tsens1 5>; 4292 4293 trips { 4294 trip-point0 { 4295 temperature = <90000>; 4296 hysteresis = <2000>; 4297 type = "hot"; 4298 }; 4299 }; 4300 }; 4301 4302 compute-thermal { 4303 polling-delay-passive = <250>; 4304 4305 thermal-sensors = <&tsens1 6>; 4306 4307 trips { 4308 trip-point0 { 4309 temperature = <90000>; 4310 hysteresis = <2000>; 4311 type = "hot"; 4312 }; 4313 }; 4314 }; 4315 4316 mdm-dsp-thermal { 4317 polling-delay-passive = <250>; 4318 4319 thermal-sensors = <&tsens1 7>; 4320 4321 trips { 4322 trip-point0 { 4323 temperature = <90000>; 4324 hysteresis = <2000>; 4325 type = "hot"; 4326 }; 4327 }; 4328 }; 4329 4330 npu-thermal { 4331 polling-delay-passive = <250>; 4332 4333 thermal-sensors = <&tsens1 8>; 4334 4335 trips { 4336 trip-point0 { 4337 temperature = <90000>; 4338 hysteresis = <2000>; 4339 type = "hot"; 4340 }; 4341 }; 4342 }; 4343 4344 gpu-bottom-thermal { 4345 polling-delay-passive = <250>; 4346 4347 thermal-sensors = <&tsens1 11>; 4348 4349 cooling-maps { 4350 map0 { 4351 trip = <&gpu_bottom_alert0>; 4352 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4353 }; 4354 }; 4355 4356 trips { 4357 gpu_bottom_alert0: trip-point0 { 4358 temperature = <85000>; 4359 hysteresis = <1000>; 4360 type = "passive"; 4361 }; 4362 4363 trip-point1 { 4364 temperature = <90000>; 4365 hysteresis = <1000>; 4366 type = "hot"; 4367 }; 4368 4369 trip-point2 { 4370 temperature = <110000>; 4371 hysteresis = <1000>; 4372 type = "critical"; 4373 }; 4374 }; 4375 }; 4376 }; 4377 4378 timer { 4379 compatible = "arm,armv8-timer"; 4380 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4381 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4382 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4383 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4384 }; 4385}; 4386