1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2020-2023, Linaro Limited 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,gcc-sc8180x.h> 9#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/interconnect/qcom,icc.h> 12#include <dt-bindings/interconnect/qcom,osm-l3.h> 13#include <dt-bindings/interconnect/qcom,sc8180x.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/power/qcom-rpmpd.h> 16#include <dt-bindings/soc/qcom,rpmh-rsc.h> 17#include <dt-bindings/thermal/thermal.h> 18 19/ { 20 interrupt-parent = <&intc>; 21 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 clocks { 26 xo_board_clk: xo-board { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 clock-frequency = <38400000>; 30 }; 31 32 sleep_clk: sleep-clk { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <32764>; 36 clock-output-names = "sleep_clk"; 37 }; 38 }; 39 40 cpus { 41 #address-cells = <2>; 42 #size-cells = <0>; 43 44 CPU0: cpu@0 { 45 device_type = "cpu"; 46 compatible = "qcom,kryo485"; 47 reg = <0x0 0x0>; 48 enable-method = "psci"; 49 capacity-dmips-mhz = <602>; 50 next-level-cache = <&L2_0>; 51 qcom,freq-domain = <&cpufreq_hw 0>; 52 operating-points-v2 = <&cpu0_opp_table>; 53 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 54 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 55 power-domains = <&CPU_PD0>; 56 power-domain-names = "psci"; 57 #cooling-cells = <2>; 58 clocks = <&cpufreq_hw 0>; 59 60 L2_0: l2-cache { 61 compatible = "cache"; 62 cache-level = <2>; 63 cache-unified; 64 next-level-cache = <&L3_0>; 65 L3_0: l3-cache { 66 compatible = "cache"; 67 cache-level = <3>; 68 cache-unified; 69 }; 70 }; 71 }; 72 73 CPU1: cpu@100 { 74 device_type = "cpu"; 75 compatible = "qcom,kryo485"; 76 reg = <0x0 0x100>; 77 enable-method = "psci"; 78 capacity-dmips-mhz = <602>; 79 next-level-cache = <&L2_100>; 80 qcom,freq-domain = <&cpufreq_hw 0>; 81 operating-points-v2 = <&cpu0_opp_table>; 82 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 83 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 84 power-domains = <&CPU_PD1>; 85 power-domain-names = "psci"; 86 #cooling-cells = <2>; 87 clocks = <&cpufreq_hw 0>; 88 89 L2_100: l2-cache { 90 compatible = "cache"; 91 cache-level = <2>; 92 cache-unified; 93 next-level-cache = <&L3_0>; 94 }; 95 96 }; 97 98 CPU2: cpu@200 { 99 device_type = "cpu"; 100 compatible = "qcom,kryo485"; 101 reg = <0x0 0x200>; 102 enable-method = "psci"; 103 capacity-dmips-mhz = <602>; 104 next-level-cache = <&L2_200>; 105 qcom,freq-domain = <&cpufreq_hw 0>; 106 operating-points-v2 = <&cpu0_opp_table>; 107 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 108 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 109 power-domains = <&CPU_PD2>; 110 power-domain-names = "psci"; 111 #cooling-cells = <2>; 112 clocks = <&cpufreq_hw 0>; 113 114 L2_200: l2-cache { 115 compatible = "cache"; 116 cache-level = <2>; 117 cache-unified; 118 next-level-cache = <&L3_0>; 119 }; 120 }; 121 122 CPU3: cpu@300 { 123 device_type = "cpu"; 124 compatible = "qcom,kryo485"; 125 reg = <0x0 0x300>; 126 enable-method = "psci"; 127 capacity-dmips-mhz = <602>; 128 next-level-cache = <&L2_300>; 129 qcom,freq-domain = <&cpufreq_hw 0>; 130 operating-points-v2 = <&cpu0_opp_table>; 131 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 132 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 133 power-domains = <&CPU_PD3>; 134 power-domain-names = "psci"; 135 #cooling-cells = <2>; 136 clocks = <&cpufreq_hw 0>; 137 138 L2_300: l2-cache { 139 compatible = "cache"; 140 cache-unified; 141 cache-level = <2>; 142 next-level-cache = <&L3_0>; 143 }; 144 }; 145 146 CPU4: cpu@400 { 147 device_type = "cpu"; 148 compatible = "qcom,kryo485"; 149 reg = <0x0 0x400>; 150 enable-method = "psci"; 151 capacity-dmips-mhz = <1024>; 152 next-level-cache = <&L2_400>; 153 qcom,freq-domain = <&cpufreq_hw 1>; 154 operating-points-v2 = <&cpu4_opp_table>; 155 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 156 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 157 power-domains = <&CPU_PD4>; 158 power-domain-names = "psci"; 159 #cooling-cells = <2>; 160 clocks = <&cpufreq_hw 1>; 161 162 L2_400: l2-cache { 163 compatible = "cache"; 164 cache-unified; 165 cache-level = <2>; 166 next-level-cache = <&L3_0>; 167 }; 168 }; 169 170 CPU5: cpu@500 { 171 device_type = "cpu"; 172 compatible = "qcom,kryo485"; 173 reg = <0x0 0x500>; 174 enable-method = "psci"; 175 capacity-dmips-mhz = <1024>; 176 next-level-cache = <&L2_500>; 177 qcom,freq-domain = <&cpufreq_hw 1>; 178 operating-points-v2 = <&cpu4_opp_table>; 179 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 180 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 181 power-domains = <&CPU_PD5>; 182 power-domain-names = "psci"; 183 #cooling-cells = <2>; 184 clocks = <&cpufreq_hw 1>; 185 186 L2_500: l2-cache { 187 compatible = "cache"; 188 cache-unified; 189 cache-level = <2>; 190 next-level-cache = <&L3_0>; 191 }; 192 }; 193 194 CPU6: cpu@600 { 195 device_type = "cpu"; 196 compatible = "qcom,kryo485"; 197 reg = <0x0 0x600>; 198 enable-method = "psci"; 199 capacity-dmips-mhz = <1024>; 200 next-level-cache = <&L2_600>; 201 qcom,freq-domain = <&cpufreq_hw 1>; 202 operating-points-v2 = <&cpu4_opp_table>; 203 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 204 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 205 power-domains = <&CPU_PD6>; 206 power-domain-names = "psci"; 207 #cooling-cells = <2>; 208 clocks = <&cpufreq_hw 1>; 209 210 L2_600: l2-cache { 211 compatible = "cache"; 212 cache-unified; 213 cache-level = <2>; 214 next-level-cache = <&L3_0>; 215 }; 216 }; 217 218 CPU7: cpu@700 { 219 device_type = "cpu"; 220 compatible = "qcom,kryo485"; 221 reg = <0x0 0x700>; 222 enable-method = "psci"; 223 capacity-dmips-mhz = <1024>; 224 next-level-cache = <&L2_700>; 225 qcom,freq-domain = <&cpufreq_hw 1>; 226 operating-points-v2 = <&cpu4_opp_table>; 227 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 228 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 229 power-domains = <&CPU_PD7>; 230 power-domain-names = "psci"; 231 #cooling-cells = <2>; 232 clocks = <&cpufreq_hw 1>; 233 234 L2_700: l2-cache { 235 compatible = "cache"; 236 cache-unified; 237 cache-level = <2>; 238 next-level-cache = <&L3_0>; 239 }; 240 }; 241 242 cpu-map { 243 cluster0 { 244 core0 { 245 cpu = <&CPU0>; 246 }; 247 248 core1 { 249 cpu = <&CPU1>; 250 }; 251 252 core2 { 253 cpu = <&CPU2>; 254 }; 255 256 core3 { 257 cpu = <&CPU3>; 258 }; 259 260 core4 { 261 cpu = <&CPU4>; 262 }; 263 264 core5 { 265 cpu = <&CPU5>; 266 }; 267 268 core6 { 269 cpu = <&CPU6>; 270 }; 271 272 core7 { 273 cpu = <&CPU7>; 274 }; 275 }; 276 }; 277 278 idle-states { 279 entry-method = "psci"; 280 281 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 282 compatible = "arm,idle-state"; 283 arm,psci-suspend-param = <0x40000004>; 284 entry-latency-us = <355>; 285 exit-latency-us = <909>; 286 min-residency-us = <3934>; 287 local-timer-stop; 288 }; 289 290 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 291 compatible = "arm,idle-state"; 292 arm,psci-suspend-param = <0x40000004>; 293 entry-latency-us = <2411>; 294 exit-latency-us = <1461>; 295 min-residency-us = <4488>; 296 local-timer-stop; 297 }; 298 }; 299 300 domain-idle-states { 301 CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { 302 compatible = "domain-idle-state"; 303 arm,psci-suspend-param = <0x41000044>; 304 entry-latency-us = <3300>; 305 exit-latency-us = <3300>; 306 min-residency-us = <6000>; 307 }; 308 309 CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 { 310 compatible = "domain-idle-state"; 311 arm,psci-suspend-param = <0x4100a344>; 312 entry-latency-us = <3263>; 313 exit-latency-us = <6562>; 314 min-residency-us = <9987>; 315 }; 316 }; 317 }; 318 319 cpu0_opp_table: opp-table-cpu0 { 320 compatible = "operating-points-v2"; 321 opp-shared; 322 323 opp-300000000 { 324 opp-hz = /bits/ 64 <300000000>; 325 opp-peak-kBps = <800000 9600000>; 326 }; 327 328 opp-422400000 { 329 opp-hz = /bits/ 64 <422400000>; 330 opp-peak-kBps = <800000 9600000>; 331 }; 332 333 opp-537600000 { 334 opp-hz = /bits/ 64 <537600000>; 335 opp-peak-kBps = <800000 12902400>; 336 }; 337 338 opp-652800000 { 339 opp-hz = /bits/ 64 <652800000>; 340 opp-peak-kBps = <800000 12902400>; 341 }; 342 343 opp-768000000 { 344 opp-hz = /bits/ 64 <768000000>; 345 opp-peak-kBps = <800000 15974400>; 346 }; 347 348 opp-883200000 { 349 opp-hz = /bits/ 64 <883200000>; 350 opp-peak-kBps = <1804000 19660800>; 351 }; 352 353 opp-998400000 { 354 opp-hz = /bits/ 64 <998400000>; 355 opp-peak-kBps = <1804000 19660800>; 356 }; 357 358 opp-1113600000 { 359 opp-hz = /bits/ 64 <1113600000>; 360 opp-peak-kBps = <1804000 22732800>; 361 }; 362 363 opp-1228800000 { 364 opp-hz = /bits/ 64 <1228800000>; 365 opp-peak-kBps = <1804000 22732800>; 366 }; 367 368 opp-1363200000 { 369 opp-hz = /bits/ 64 <1363200000>; 370 opp-peak-kBps = <2188000 25804800>; 371 }; 372 373 opp-1478400000 { 374 opp-hz = /bits/ 64 <1478400000>; 375 opp-peak-kBps = <2188000 31948800>; 376 }; 377 378 opp-1574400000 { 379 opp-hz = /bits/ 64 <1574400000>; 380 opp-peak-kBps = <3072000 31948800>; 381 }; 382 383 opp-1670400000 { 384 opp-hz = /bits/ 64 <1670400000>; 385 opp-peak-kBps = <3072000 31948800>; 386 }; 387 388 opp-1766400000 { 389 opp-hz = /bits/ 64 <1766400000>; 390 opp-peak-kBps = <3072000 31948800>; 391 }; 392 }; 393 394 cpu4_opp_table: opp-table-cpu4 { 395 compatible = "operating-points-v2"; 396 opp-shared; 397 398 opp-825600000 { 399 opp-hz = /bits/ 64 <825600000>; 400 opp-peak-kBps = <1804000 15974400>; 401 }; 402 403 opp-940800000 { 404 opp-hz = /bits/ 64 <940800000>; 405 opp-peak-kBps = <2188000 19660800>; 406 }; 407 408 opp-1056000000 { 409 opp-hz = /bits/ 64 <1056000000>; 410 opp-peak-kBps = <2188000 22732800>; 411 }; 412 413 opp-1171200000 { 414 opp-hz = /bits/ 64 <1171200000>; 415 opp-peak-kBps = <3072000 25804800>; 416 }; 417 418 opp-1286400000 { 419 opp-hz = /bits/ 64 <1286400000>; 420 opp-peak-kBps = <3072000 31948800>; 421 }; 422 423 opp-1420800000 { 424 opp-hz = /bits/ 64 <1420800000>; 425 opp-peak-kBps = <4068000 31948800>; 426 }; 427 428 opp-1536000000 { 429 opp-hz = /bits/ 64 <1536000000>; 430 opp-peak-kBps = <4068000 31948800>; 431 }; 432 433 opp-1651200000 { 434 opp-hz = /bits/ 64 <1651200000>; 435 opp-peak-kBps = <4068000 40550400>; 436 }; 437 438 opp-1766400000 { 439 opp-hz = /bits/ 64 <1766400000>; 440 opp-peak-kBps = <4068000 40550400>; 441 }; 442 443 opp-1881600000 { 444 opp-hz = /bits/ 64 <1881600000>; 445 opp-peak-kBps = <4068000 43008000>; 446 }; 447 448 opp-1996800000 { 449 opp-hz = /bits/ 64 <1996800000>; 450 opp-peak-kBps = <6220000 43008000>; 451 }; 452 453 opp-2131200000 { 454 opp-hz = /bits/ 64 <2131200000>; 455 opp-peak-kBps = <6220000 49152000>; 456 }; 457 458 opp-2246400000 { 459 opp-hz = /bits/ 64 <2246400000>; 460 opp-peak-kBps = <7216000 49152000>; 461 }; 462 463 opp-2361600000 { 464 opp-hz = /bits/ 64 <2361600000>; 465 opp-peak-kBps = <8368000 49152000>; 466 }; 467 468 opp-2457600000 { 469 opp-hz = /bits/ 64 <2457600000>; 470 opp-peak-kBps = <8368000 51609600>; 471 }; 472 473 opp-2553600000 { 474 opp-hz = /bits/ 64 <2553600000>; 475 opp-peak-kBps = <8368000 51609600>; 476 }; 477 478 opp-2649600000 { 479 opp-hz = /bits/ 64 <2649600000>; 480 opp-peak-kBps = <8368000 51609600>; 481 }; 482 483 opp-2745600000 { 484 opp-hz = /bits/ 64 <2745600000>; 485 opp-peak-kBps = <8368000 51609600>; 486 }; 487 488 opp-2841600000 { 489 opp-hz = /bits/ 64 <2841600000>; 490 opp-peak-kBps = <8368000 51609600>; 491 }; 492 493 opp-2918400000 { 494 opp-hz = /bits/ 64 <2918400000>; 495 opp-peak-kBps = <8368000 51609600>; 496 }; 497 498 opp-2995200000 { 499 opp-hz = /bits/ 64 <2995200000>; 500 opp-peak-kBps = <8368000 51609600>; 501 }; 502 }; 503 504 firmware { 505 scm: scm { 506 compatible = "qcom,scm-sc8180x", "qcom,scm"; 507 }; 508 }; 509 510 camnoc_virt: interconnect-camnoc-virt { 511 compatible = "qcom,sc8180x-camnoc-virt"; 512 #interconnect-cells = <2>; 513 qcom,bcm-voters = <&apps_bcm_voter>; 514 }; 515 516 mc_virt: interconnect-mc-virt { 517 compatible = "qcom,sc8180x-mc-virt"; 518 #interconnect-cells = <2>; 519 qcom,bcm-voters = <&apps_bcm_voter>; 520 }; 521 522 qup_virt: interconnect-qup-virt { 523 compatible = "qcom,sc8180x-qup-virt"; 524 #interconnect-cells = <2>; 525 qcom,bcm-voters = <&apps_bcm_voter>; 526 }; 527 528 memory@80000000 { 529 device_type = "memory"; 530 /* We expect the bootloader to fill in the size */ 531 reg = <0x0 0x80000000 0x0 0x0>; 532 }; 533 534 pmu { 535 compatible = "arm,armv8-pmuv3"; 536 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 537 }; 538 539 psci { 540 compatible = "arm,psci-1.0"; 541 method = "smc"; 542 543 CPU_PD0: power-domain-cpu0 { 544 #power-domain-cells = <0>; 545 power-domains = <&CLUSTER_PD>; 546 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 547 }; 548 549 CPU_PD1: power-domain-cpu1 { 550 #power-domain-cells = <0>; 551 power-domains = <&CLUSTER_PD>; 552 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 553 }; 554 555 CPU_PD2: power-domain-cpu2 { 556 #power-domain-cells = <0>; 557 power-domains = <&CLUSTER_PD>; 558 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 559 }; 560 561 CPU_PD3: power-domain-cpu3 { 562 #power-domain-cells = <0>; 563 power-domains = <&CLUSTER_PD>; 564 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 565 }; 566 567 CPU_PD4: power-domain-cpu4 { 568 #power-domain-cells = <0>; 569 power-domains = <&CLUSTER_PD>; 570 domain-idle-states = <&BIG_CPU_SLEEP_0>; 571 }; 572 573 CPU_PD5: power-domain-cpu5 { 574 #power-domain-cells = <0>; 575 power-domains = <&CLUSTER_PD>; 576 domain-idle-states = <&BIG_CPU_SLEEP_0>; 577 }; 578 579 CPU_PD6: power-domain-cpu6 { 580 #power-domain-cells = <0>; 581 power-domains = <&CLUSTER_PD>; 582 domain-idle-states = <&BIG_CPU_SLEEP_0>; 583 }; 584 585 CPU_PD7: power-domain-cpu7 { 586 #power-domain-cells = <0>; 587 power-domains = <&CLUSTER_PD>; 588 domain-idle-states = <&BIG_CPU_SLEEP_0>; 589 }; 590 591 CLUSTER_PD: power-domain-cpu-cluster0 { 592 #power-domain-cells = <0>; 593 domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLEEP>; 594 }; 595 }; 596 597 reserved-memory { 598 #address-cells = <2>; 599 #size-cells = <2>; 600 ranges; 601 602 hyp_mem: hyp@85700000 { 603 reg = <0x0 0x85700000 0x0 0x600000>; 604 no-map; 605 }; 606 607 xbl_mem: xbl@85d00000 { 608 reg = <0x0 0x85d00000 0x0 0x140000>; 609 no-map; 610 }; 611 612 aop_mem: aop@85f00000 { 613 reg = <0x0 0x85f00000 0x0 0x20000>; 614 no-map; 615 }; 616 617 aop_cmd_db: cmd-db@85f20000 { 618 compatible = "qcom,cmd-db"; 619 reg = <0x0 0x85f20000 0x0 0x20000>; 620 no-map; 621 }; 622 623 reserved@85f40000 { 624 reg = <0x0 0x85f40000 0x0 0x10000>; 625 no-map; 626 }; 627 628 smem_mem: smem@86000000 { 629 compatible = "qcom,smem"; 630 reg = <0x0 0x86000000 0x0 0x200000>; 631 no-map; 632 hwlocks = <&tcsr_mutex 3>; 633 }; 634 635 reserved@86200000 { 636 reg = <0x0 0x86200000 0x0 0x3900000>; 637 no-map; 638 }; 639 640 reserved@89b00000 { 641 reg = <0x0 0x89b00000 0x0 0x1c00000>; 642 no-map; 643 }; 644 645 reserved@9d400000 { 646 reg = <0x0 0x9d400000 0x0 0x1000000>; 647 no-map; 648 }; 649 650 reserved@9e400000 { 651 reg = <0x0 0x9e400000 0x0 0x1400000>; 652 no-map; 653 }; 654 655 reserved@9f800000 { 656 reg = <0x0 0x9f800000 0x0 0x800000>; 657 no-map; 658 }; 659 }; 660 661 smp2p-cdsp { 662 compatible = "qcom,smp2p"; 663 qcom,smem = <94>, <432>; 664 665 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 666 667 mboxes = <&apss_shared 6>; 668 669 qcom,local-pid = <0>; 670 qcom,remote-pid = <5>; 671 672 cdsp_smp2p_out: master-kernel { 673 qcom,entry-name = "master-kernel"; 674 #qcom,smem-state-cells = <1>; 675 }; 676 677 cdsp_smp2p_in: slave-kernel { 678 qcom,entry-name = "slave-kernel"; 679 680 interrupt-controller; 681 #interrupt-cells = <2>; 682 }; 683 }; 684 685 smp2p-lpass { 686 compatible = "qcom,smp2p"; 687 qcom,smem = <443>, <429>; 688 689 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 690 691 mboxes = <&apss_shared 10>; 692 693 qcom,local-pid = <0>; 694 qcom,remote-pid = <2>; 695 696 adsp_smp2p_out: master-kernel { 697 qcom,entry-name = "master-kernel"; 698 #qcom,smem-state-cells = <1>; 699 }; 700 701 adsp_smp2p_in: slave-kernel { 702 qcom,entry-name = "slave-kernel"; 703 704 interrupt-controller; 705 #interrupt-cells = <2>; 706 }; 707 }; 708 709 smp2p-mpss { 710 compatible = "qcom,smp2p"; 711 qcom,smem = <435>, <428>; 712 713 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 714 715 mboxes = <&apss_shared 14>; 716 717 qcom,local-pid = <0>; 718 qcom,remote-pid = <1>; 719 720 modem_smp2p_out: master-kernel { 721 qcom,entry-name = "master-kernel"; 722 #qcom,smem-state-cells = <1>; 723 }; 724 725 modem_smp2p_in: slave-kernel { 726 qcom,entry-name = "slave-kernel"; 727 728 interrupt-controller; 729 #interrupt-cells = <2>; 730 }; 731 732 modem_smp2p_ipa_out: ipa-ap-to-modem { 733 qcom,entry-name = "ipa"; 734 #qcom,smem-state-cells = <1>; 735 }; 736 737 modem_smp2p_ipa_in: ipa-modem-to-ap { 738 qcom,entry-name = "ipa"; 739 interrupt-controller; 740 #interrupt-cells = <2>; 741 }; 742 743 modem_smp2p_wlan_in: wlan-wpss-to-ap { 744 qcom,entry-name = "wlan"; 745 interrupt-controller; 746 #interrupt-cells = <2>; 747 }; 748 }; 749 750 smp2p-slpi { 751 compatible = "qcom,smp2p"; 752 qcom,smem = <481>, <430>; 753 754 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 755 756 mboxes = <&apss_shared 26>; 757 758 qcom,local-pid = <0>; 759 qcom,remote-pid = <3>; 760 761 slpi_smp2p_out: master-kernel { 762 qcom,entry-name = "master-kernel"; 763 #qcom,smem-state-cells = <1>; 764 }; 765 766 slpi_smp2p_in: slave-kernel { 767 qcom,entry-name = "slave-kernel"; 768 769 interrupt-controller; 770 #interrupt-cells = <2>; 771 }; 772 }; 773 774 soc: soc@0 { 775 compatible = "simple-bus"; 776 #address-cells = <2>; 777 #size-cells = <2>; 778 ranges = <0 0 0 0 0x10 0>; 779 dma-ranges = <0 0 0 0 0x10 0>; 780 781 gcc: clock-controller@100000 { 782 compatible = "qcom,gcc-sc8180x"; 783 reg = <0x0 0x00100000 0x0 0x1f0000>; 784 #clock-cells = <1>; 785 #reset-cells = <1>; 786 #power-domain-cells = <1>; 787 clocks = <&rpmhcc RPMH_CXO_CLK>, 788 <&rpmhcc RPMH_CXO_CLK_A>, 789 <&sleep_clk>; 790 clock-names = "bi_tcxo", 791 "bi_tcxo_ao", 792 "sleep_clk"; 793 power-domains = <&rpmhpd SC8180X_CX>; 794 }; 795 796 qupv3_id_0: geniqup@8c0000 { 797 compatible = "qcom,geni-se-qup"; 798 reg = <0 0x008c0000 0 0x6000>; 799 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 800 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 801 clock-names = "m-ahb", "s-ahb"; 802 #address-cells = <2>; 803 #size-cells = <2>; 804 ranges; 805 iommus = <&apps_smmu 0x4c3 0>; 806 status = "disabled"; 807 808 i2c0: i2c@880000 { 809 compatible = "qcom,geni-i2c"; 810 reg = <0 0x00880000 0 0x4000>; 811 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 812 clock-names = "se"; 813 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 814 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 815 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 816 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 817 interconnect-names = "qup-core", "qup-config", "qup-memory"; 818 #address-cells = <1>; 819 #size-cells = <0>; 820 status = "disabled"; 821 }; 822 823 spi0: spi@880000 { 824 compatible = "qcom,geni-spi"; 825 reg = <0 0x00880000 0 0x4000>; 826 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 827 clock-names = "se"; 828 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 829 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 830 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 831 interconnect-names = "qup-core", "qup-config"; 832 #address-cells = <1>; 833 #size-cells = <0>; 834 status = "disabled"; 835 }; 836 837 uart0: serial@880000 { 838 compatible = "qcom,geni-uart"; 839 reg = <0 0x00880000 0 0x4000>; 840 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 841 clock-names = "se"; 842 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 843 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 844 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 845 interconnect-names = "qup-core", "qup-config"; 846 status = "disabled"; 847 }; 848 849 i2c1: i2c@884000 { 850 compatible = "qcom,geni-i2c"; 851 reg = <0 0x00884000 0 0x4000>; 852 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 853 clock-names = "se"; 854 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 855 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 856 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 857 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 858 interconnect-names = "qup-core", "qup-config", "qup-memory"; 859 #address-cells = <1>; 860 #size-cells = <0>; 861 status = "disabled"; 862 }; 863 864 spi1: spi@884000 { 865 compatible = "qcom,geni-spi"; 866 reg = <0 0x00884000 0 0x4000>; 867 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 868 clock-names = "se"; 869 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 870 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 871 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 872 interconnect-names = "qup-core", "qup-config"; 873 #address-cells = <1>; 874 #size-cells = <0>; 875 status = "disabled"; 876 }; 877 878 uart1: serial@884000 { 879 compatible = "qcom,geni-uart"; 880 reg = <0 0x00884000 0 0x4000>; 881 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 882 clock-names = "se"; 883 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 884 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 885 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 886 interconnect-names = "qup-core", "qup-config"; 887 status = "disabled"; 888 }; 889 890 i2c2: i2c@888000 { 891 compatible = "qcom,geni-i2c"; 892 reg = <0 0x00888000 0 0x4000>; 893 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 894 clock-names = "se"; 895 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 896 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 897 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 898 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 899 interconnect-names = "qup-core", "qup-config", "qup-memory"; 900 #address-cells = <1>; 901 #size-cells = <0>; 902 status = "disabled"; 903 }; 904 905 spi2: spi@888000 { 906 compatible = "qcom,geni-spi"; 907 reg = <0 0x00888000 0 0x4000>; 908 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 909 clock-names = "se"; 910 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 911 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 912 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 913 interconnect-names = "qup-core", "qup-config"; 914 #address-cells = <1>; 915 #size-cells = <0>; 916 status = "disabled"; 917 }; 918 919 uart2: serial@888000 { 920 compatible = "qcom,geni-uart"; 921 reg = <0 0x00888000 0 0x4000>; 922 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 923 clock-names = "se"; 924 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 925 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 926 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 927 interconnect-names = "qup-core", "qup-config"; 928 status = "disabled"; 929 }; 930 931 i2c3: i2c@88c000 { 932 compatible = "qcom,geni-i2c"; 933 reg = <0 0x0088c000 0 0x4000>; 934 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 935 clock-names = "se"; 936 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 937 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 938 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 939 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 940 interconnect-names = "qup-core", "qup-config", "qup-memory"; 941 #address-cells = <1>; 942 #size-cells = <0>; 943 status = "disabled"; 944 }; 945 946 spi3: spi@88c000 { 947 compatible = "qcom,geni-spi"; 948 reg = <0 0x0088c000 0 0x4000>; 949 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 950 clock-names = "se"; 951 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 952 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 953 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 954 interconnect-names = "qup-core", "qup-config"; 955 #address-cells = <1>; 956 #size-cells = <0>; 957 status = "disabled"; 958 }; 959 960 uart3: serial@88c000 { 961 compatible = "qcom,geni-uart"; 962 reg = <0 0x0088c000 0 0x4000>; 963 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 964 clock-names = "se"; 965 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 966 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 967 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 968 interconnect-names = "qup-core", "qup-config"; 969 status = "disabled"; 970 }; 971 972 i2c4: i2c@890000 { 973 compatible = "qcom,geni-i2c"; 974 reg = <0 0x00890000 0 0x4000>; 975 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 976 clock-names = "se"; 977 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 978 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 979 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 980 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 981 interconnect-names = "qup-core", "qup-config", "qup-memory"; 982 #address-cells = <1>; 983 #size-cells = <0>; 984 status = "disabled"; 985 }; 986 987 spi4: spi@890000 { 988 compatible = "qcom,geni-spi"; 989 reg = <0 0x00890000 0 0x4000>; 990 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 991 clock-names = "se"; 992 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 993 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 994 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 995 interconnect-names = "qup-core", "qup-config"; 996 #address-cells = <1>; 997 #size-cells = <0>; 998 status = "disabled"; 999 }; 1000 1001 uart4: serial@890000 { 1002 compatible = "qcom,geni-uart"; 1003 reg = <0 0x00890000 0 0x4000>; 1004 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1005 clock-names = "se"; 1006 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1007 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1008 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1009 interconnect-names = "qup-core", "qup-config"; 1010 status = "disabled"; 1011 }; 1012 1013 i2c5: i2c@894000 { 1014 compatible = "qcom,geni-i2c"; 1015 reg = <0 0x00894000 0 0x4000>; 1016 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1017 clock-names = "se"; 1018 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1019 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1020 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1021 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1022 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1023 #address-cells = <1>; 1024 #size-cells = <0>; 1025 status = "disabled"; 1026 }; 1027 1028 spi5: spi@894000 { 1029 compatible = "qcom,geni-spi"; 1030 reg = <0 0x00894000 0 0x4000>; 1031 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1032 clock-names = "se"; 1033 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1034 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1035 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1036 interconnect-names = "qup-core", "qup-config"; 1037 #address-cells = <1>; 1038 #size-cells = <0>; 1039 status = "disabled"; 1040 }; 1041 1042 uart5: serial@894000 { 1043 compatible = "qcom,geni-uart"; 1044 reg = <0 0x00894000 0 0x4000>; 1045 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1046 clock-names = "se"; 1047 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1048 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1049 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1050 interconnect-names = "qup-core", "qup-config"; 1051 status = "disabled"; 1052 }; 1053 1054 i2c6: i2c@898000 { 1055 compatible = "qcom,geni-i2c"; 1056 reg = <0 0x00898000 0 0x4000>; 1057 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1058 clock-names = "se"; 1059 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1060 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1061 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1062 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1063 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1064 #address-cells = <1>; 1065 #size-cells = <0>; 1066 status = "disabled"; 1067 }; 1068 1069 spi6: spi@898000 { 1070 compatible = "qcom,geni-spi"; 1071 reg = <0 0x00898000 0 0x4000>; 1072 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1073 clock-names = "se"; 1074 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1075 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1076 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1077 interconnect-names = "qup-core", "qup-config"; 1078 #address-cells = <1>; 1079 #size-cells = <0>; 1080 status = "disabled"; 1081 }; 1082 1083 uart6: serial@898000 { 1084 compatible = "qcom,geni-uart"; 1085 reg = <0 0x00898000 0 0x4000>; 1086 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1087 clock-names = "se"; 1088 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1089 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1090 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1091 interconnect-names = "qup-core", "qup-config"; 1092 status = "disabled"; 1093 }; 1094 1095 i2c7: i2c@89c000 { 1096 compatible = "qcom,geni-i2c"; 1097 reg = <0 0x0089c000 0 0x4000>; 1098 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1099 clock-names = "se"; 1100 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1101 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1102 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1103 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1104 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1105 #address-cells = <1>; 1106 #size-cells = <0>; 1107 status = "disabled"; 1108 }; 1109 1110 spi7: spi@89c000 { 1111 compatible = "qcom,geni-spi"; 1112 reg = <0 0x0089c000 0 0x4000>; 1113 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1114 clock-names = "se"; 1115 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1116 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1117 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1118 interconnect-names = "qup-core", "qup-config"; 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 status = "disabled"; 1122 }; 1123 1124 uart7: serial@89c000 { 1125 compatible = "qcom,geni-uart"; 1126 reg = <0 0x0089c000 0 0x4000>; 1127 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1128 clock-names = "se"; 1129 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1130 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1131 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1132 interconnect-names = "qup-core", "qup-config"; 1133 status = "disabled"; 1134 }; 1135 }; 1136 1137 qupv3_id_1: geniqup@ac0000 { 1138 compatible = "qcom,geni-se-qup"; 1139 reg = <0x0 0x00ac0000 0x0 0x6000>; 1140 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1141 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1142 clock-names = "m-ahb", "s-ahb"; 1143 #address-cells = <2>; 1144 #size-cells = <2>; 1145 ranges; 1146 iommus = <&apps_smmu 0x603 0>; 1147 status = "disabled"; 1148 1149 i2c8: i2c@a80000 { 1150 compatible = "qcom,geni-i2c"; 1151 reg = <0 0x00a80000 0 0x4000>; 1152 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1153 clock-names = "se"; 1154 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1155 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1156 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1157 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1158 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1159 #address-cells = <1>; 1160 #size-cells = <0>; 1161 status = "disabled"; 1162 }; 1163 1164 spi8: spi@a80000 { 1165 compatible = "qcom,geni-spi"; 1166 reg = <0 0x00a80000 0 0x4000>; 1167 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1168 clock-names = "se"; 1169 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1170 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1171 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1172 interconnect-names = "qup-core", "qup-config"; 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 status = "disabled"; 1176 }; 1177 1178 uart8: serial@a80000 { 1179 compatible = "qcom,geni-uart"; 1180 reg = <0 0x00a80000 0 0x4000>; 1181 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1182 clock-names = "se"; 1183 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1184 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1185 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1186 interconnect-names = "qup-core", "qup-config"; 1187 status = "disabled"; 1188 }; 1189 1190 i2c9: i2c@a84000 { 1191 compatible = "qcom,geni-i2c"; 1192 reg = <0 0x00a84000 0 0x4000>; 1193 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1194 clock-names = "se"; 1195 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1196 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1197 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1198 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1199 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1200 #address-cells = <1>; 1201 #size-cells = <0>; 1202 status = "disabled"; 1203 }; 1204 1205 spi9: spi@a84000 { 1206 compatible = "qcom,geni-spi"; 1207 reg = <0 0x00a84000 0 0x4000>; 1208 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1209 clock-names = "se"; 1210 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1211 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1212 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1213 interconnect-names = "qup-core", "qup-config"; 1214 #address-cells = <1>; 1215 #size-cells = <0>; 1216 status = "disabled"; 1217 }; 1218 1219 uart9: serial@a84000 { 1220 compatible = "qcom,geni-debug-uart"; 1221 reg = <0 0x00a84000 0 0x4000>; 1222 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1223 clock-names = "se"; 1224 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1225 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1226 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1227 interconnect-names = "qup-core", "qup-config"; 1228 status = "disabled"; 1229 }; 1230 1231 i2c10: i2c@a88000 { 1232 compatible = "qcom,geni-i2c"; 1233 reg = <0 0x00a88000 0 0x4000>; 1234 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1235 clock-names = "se"; 1236 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1237 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1238 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1239 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1240 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1241 #address-cells = <1>; 1242 #size-cells = <0>; 1243 status = "disabled"; 1244 }; 1245 1246 spi10: spi@a88000 { 1247 compatible = "qcom,geni-spi"; 1248 reg = <0 0x00a88000 0 0x4000>; 1249 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1250 clock-names = "se"; 1251 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1252 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1253 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1254 interconnect-names = "qup-core", "qup-config"; 1255 #address-cells = <1>; 1256 #size-cells = <0>; 1257 status = "disabled"; 1258 }; 1259 1260 uart10: serial@a88000 { 1261 compatible = "qcom,geni-uart"; 1262 reg = <0 0x00a88000 0 0x4000>; 1263 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1264 clock-names = "se"; 1265 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1266 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1267 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1268 interconnect-names = "qup-core", "qup-config"; 1269 status = "disabled"; 1270 }; 1271 1272 i2c11: i2c@a8c000 { 1273 compatible = "qcom,geni-i2c"; 1274 reg = <0 0x00a8c000 0 0x4000>; 1275 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1276 clock-names = "se"; 1277 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1278 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1279 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1280 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1281 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 status = "disabled"; 1285 }; 1286 1287 spi11: spi@a8c000 { 1288 compatible = "qcom,geni-spi"; 1289 reg = <0 0x00a8c000 0 0x4000>; 1290 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1291 clock-names = "se"; 1292 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1293 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1294 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1295 interconnect-names = "qup-core", "qup-config"; 1296 #address-cells = <1>; 1297 #size-cells = <0>; 1298 status = "disabled"; 1299 }; 1300 1301 uart11: serial@a8c000 { 1302 compatible = "qcom,geni-uart"; 1303 reg = <0 0x00a8c000 0 0x4000>; 1304 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1305 clock-names = "se"; 1306 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1307 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1308 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1309 interconnect-names = "qup-core", "qup-config"; 1310 status = "disabled"; 1311 }; 1312 1313 i2c12: i2c@a90000 { 1314 compatible = "qcom,geni-i2c"; 1315 reg = <0 0x00a90000 0 0x4000>; 1316 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1317 clock-names = "se"; 1318 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1319 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1320 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1321 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1322 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1323 #address-cells = <1>; 1324 #size-cells = <0>; 1325 status = "disabled"; 1326 }; 1327 1328 spi12: spi@a90000 { 1329 compatible = "qcom,geni-spi"; 1330 reg = <0 0x00a90000 0 0x4000>; 1331 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1332 clock-names = "se"; 1333 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1334 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1335 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1336 interconnect-names = "qup-core", "qup-config"; 1337 #address-cells = <1>; 1338 #size-cells = <0>; 1339 status = "disabled"; 1340 }; 1341 1342 uart12: serial@a90000 { 1343 compatible = "qcom,geni-uart"; 1344 reg = <0 0x00a90000 0 0x4000>; 1345 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1346 clock-names = "se"; 1347 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1348 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1349 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1350 interconnect-names = "qup-core", "qup-config"; 1351 status = "disabled"; 1352 }; 1353 1354 i2c16: i2c@a94000 { 1355 compatible = "qcom,geni-i2c"; 1356 reg = <0 0x00a94000 0 0x4000>; 1357 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1358 clock-names = "se"; 1359 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1360 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1361 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1362 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1363 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1364 #address-cells = <1>; 1365 #size-cells = <0>; 1366 status = "disabled"; 1367 }; 1368 1369 spi16: spi@a94000 { 1370 compatible = "qcom,geni-spi"; 1371 reg = <0 0x00a94000 0 0x4000>; 1372 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1373 clock-names = "se"; 1374 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1375 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1376 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1377 interconnect-names = "qup-core", "qup-config"; 1378 #address-cells = <1>; 1379 #size-cells = <0>; 1380 status = "disabled"; 1381 }; 1382 1383 uart16: serial@a94000 { 1384 compatible = "qcom,geni-uart"; 1385 reg = <0 0x00a94000 0 0x4000>; 1386 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1387 clock-names = "se"; 1388 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1389 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1390 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1391 interconnect-names = "qup-core", "qup-config"; 1392 status = "disabled"; 1393 }; 1394 }; 1395 1396 qupv3_id_2: geniqup@cc0000 { 1397 compatible = "qcom,geni-se-qup"; 1398 reg = <0x0 0x00cc0000 0x0 0x6000>; 1399 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1400 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1401 clock-names = "m-ahb", "s-ahb"; 1402 #address-cells = <2>; 1403 #size-cells = <2>; 1404 ranges; 1405 iommus = <&apps_smmu 0x7a3 0>; 1406 status = "disabled"; 1407 1408 i2c17: i2c@c80000 { 1409 compatible = "qcom,geni-i2c"; 1410 reg = <0 0x00c80000 0 0x4000>; 1411 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1412 clock-names = "se"; 1413 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1414 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1415 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1416 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1417 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1418 #address-cells = <1>; 1419 #size-cells = <0>; 1420 status = "disabled"; 1421 }; 1422 1423 spi17: spi@c80000 { 1424 compatible = "qcom,geni-spi"; 1425 reg = <0 0x00c80000 0 0x4000>; 1426 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1427 clock-names = "se"; 1428 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1429 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1430 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1431 interconnect-names = "qup-core", "qup-config"; 1432 #address-cells = <1>; 1433 #size-cells = <0>; 1434 status = "disabled"; 1435 }; 1436 1437 uart17: serial@c80000 { 1438 compatible = "qcom,geni-uart"; 1439 reg = <0 0x00c80000 0 0x4000>; 1440 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1441 clock-names = "se"; 1442 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1443 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1444 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1445 interconnect-names = "qup-core", "qup-config"; 1446 status = "disabled"; 1447 }; 1448 1449 i2c18: i2c@c84000 { 1450 compatible = "qcom,geni-i2c"; 1451 reg = <0 0x00c84000 0 0x4000>; 1452 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1453 clock-names = "se"; 1454 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1455 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1456 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1457 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1458 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1459 #address-cells = <1>; 1460 #size-cells = <0>; 1461 status = "disabled"; 1462 }; 1463 1464 spi18: spi@c84000 { 1465 compatible = "qcom,geni-spi"; 1466 reg = <0 0x00c84000 0 0x4000>; 1467 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1468 clock-names = "se"; 1469 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1470 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1471 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1472 interconnect-names = "qup-core", "qup-config"; 1473 #address-cells = <1>; 1474 #size-cells = <0>; 1475 status = "disabled"; 1476 }; 1477 1478 uart18: serial@c84000 { 1479 compatible = "qcom,geni-uart"; 1480 reg = <0 0x00c84000 0 0x4000>; 1481 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1482 clock-names = "se"; 1483 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1484 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1485 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1486 interconnect-names = "qup-core", "qup-config"; 1487 status = "disabled"; 1488 }; 1489 1490 i2c19: i2c@c88000 { 1491 compatible = "qcom,geni-i2c"; 1492 reg = <0 0x00c88000 0 0x4000>; 1493 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1494 clock-names = "se"; 1495 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1496 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1497 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1498 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1499 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1500 #address-cells = <1>; 1501 #size-cells = <0>; 1502 status = "disabled"; 1503 }; 1504 1505 spi19: spi@c88000 { 1506 compatible = "qcom,geni-spi"; 1507 reg = <0 0x00c88000 0 0x4000>; 1508 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1509 clock-names = "se"; 1510 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1511 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1512 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1513 interconnect-names = "qup-core", "qup-config"; 1514 #address-cells = <1>; 1515 #size-cells = <0>; 1516 status = "disabled"; 1517 }; 1518 1519 uart19: serial@c88000 { 1520 compatible = "qcom,geni-uart"; 1521 reg = <0 0x00c88000 0 0x4000>; 1522 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1523 clock-names = "se"; 1524 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1525 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1526 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1527 interconnect-names = "qup-core", "qup-config"; 1528 status = "disabled"; 1529 }; 1530 1531 i2c13: i2c@c8c000 { 1532 compatible = "qcom,geni-i2c"; 1533 reg = <0 0x00c8c000 0 0x4000>; 1534 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1535 clock-names = "se"; 1536 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1537 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1538 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1539 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1540 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1541 #address-cells = <1>; 1542 #size-cells = <0>; 1543 status = "disabled"; 1544 }; 1545 1546 spi13: spi@c8c000 { 1547 compatible = "qcom,geni-spi"; 1548 reg = <0 0x00c8c000 0 0x4000>; 1549 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1550 clock-names = "se"; 1551 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1552 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1553 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1554 interconnect-names = "qup-core", "qup-config"; 1555 #address-cells = <1>; 1556 #size-cells = <0>; 1557 status = "disabled"; 1558 }; 1559 1560 uart13: serial@c8c000 { 1561 compatible = "qcom,geni-uart"; 1562 reg = <0 0x00c8c000 0 0x4000>; 1563 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1564 clock-names = "se"; 1565 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1566 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1567 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1568 interconnect-names = "qup-core", "qup-config"; 1569 status = "disabled"; 1570 }; 1571 1572 i2c14: i2c@c90000 { 1573 compatible = "qcom,geni-i2c"; 1574 reg = <0 0x00c90000 0 0x4000>; 1575 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1576 clock-names = "se"; 1577 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1578 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1579 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1580 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1581 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1582 #address-cells = <1>; 1583 #size-cells = <0>; 1584 status = "disabled"; 1585 }; 1586 1587 spi14: spi@c90000 { 1588 compatible = "qcom,geni-spi"; 1589 reg = <0 0x00c90000 0 0x4000>; 1590 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1591 clock-names = "se"; 1592 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1593 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1594 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1595 interconnect-names = "qup-core", "qup-config"; 1596 #address-cells = <1>; 1597 #size-cells = <0>; 1598 status = "disabled"; 1599 }; 1600 1601 uart14: serial@c90000 { 1602 compatible = "qcom,geni-uart"; 1603 reg = <0 0x00c90000 0 0x4000>; 1604 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1605 clock-names = "se"; 1606 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1607 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1608 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1609 interconnect-names = "qup-core", "qup-config"; 1610 status = "disabled"; 1611 }; 1612 1613 i2c15: i2c@c94000 { 1614 compatible = "qcom,geni-i2c"; 1615 reg = <0 0x00c94000 0 0x4000>; 1616 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1617 clock-names = "se"; 1618 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1619 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1620 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1621 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1622 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1623 #address-cells = <1>; 1624 #size-cells = <0>; 1625 status = "disabled"; 1626 }; 1627 1628 spi15: spi@c94000 { 1629 compatible = "qcom,geni-spi"; 1630 reg = <0 0x00c94000 0 0x4000>; 1631 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1632 clock-names = "se"; 1633 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1634 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1635 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1636 interconnect-names = "qup-core", "qup-config"; 1637 #address-cells = <1>; 1638 #size-cells = <0>; 1639 status = "disabled"; 1640 }; 1641 1642 uart15: serial@c94000 { 1643 compatible = "qcom,geni-uart"; 1644 reg = <0 0x00c94000 0 0x4000>; 1645 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1646 clock-names = "se"; 1647 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1648 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1649 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1650 interconnect-names = "qup-core", "qup-config"; 1651 status = "disabled"; 1652 }; 1653 }; 1654 1655 config_noc: interconnect@1500000 { 1656 compatible = "qcom,sc8180x-config-noc"; 1657 reg = <0 0x01500000 0 0x7400>; 1658 #interconnect-cells = <2>; 1659 qcom,bcm-voters = <&apps_bcm_voter>; 1660 }; 1661 1662 system_noc: interconnect@1620000 { 1663 compatible = "qcom,sc8180x-system-noc"; 1664 reg = <0 0x01620000 0 0x19400>; 1665 #interconnect-cells = <2>; 1666 qcom,bcm-voters = <&apps_bcm_voter>; 1667 }; 1668 1669 aggre1_noc: interconnect@16e0000 { 1670 compatible = "qcom,sc8180x-aggre1-noc"; 1671 reg = <0 0x016e0000 0 0xd080>; 1672 #interconnect-cells = <2>; 1673 qcom,bcm-voters = <&apps_bcm_voter>; 1674 }; 1675 1676 aggre2_noc: interconnect@1700000 { 1677 compatible = "qcom,sc8180x-aggre2-noc"; 1678 reg = <0 0x01700000 0 0x20000>; 1679 #interconnect-cells = <2>; 1680 qcom,bcm-voters = <&apps_bcm_voter>; 1681 }; 1682 1683 compute_noc: interconnect@1720000 { 1684 compatible = "qcom,sc8180x-compute-noc"; 1685 reg = <0 0x01720000 0 0x7000>; 1686 #interconnect-cells = <2>; 1687 qcom,bcm-voters = <&apps_bcm_voter>; 1688 }; 1689 1690 mmss_noc: interconnect@1740000 { 1691 compatible = "qcom,sc8180x-mmss-noc"; 1692 reg = <0 0x01740000 0 0x1c100>; 1693 #interconnect-cells = <2>; 1694 qcom,bcm-voters = <&apps_bcm_voter>; 1695 }; 1696 1697 pcie0: pcie@1c00000 { 1698 compatible = "qcom,pcie-sc8180x"; 1699 reg = <0 0x01c00000 0 0x3000>, 1700 <0 0x60000000 0 0xf1d>, 1701 <0 0x60000f20 0 0xa8>, 1702 <0 0x60001000 0 0x1000>, 1703 <0 0x60100000 0 0x100000>; 1704 reg-names = "parf", 1705 "dbi", 1706 "elbi", 1707 "atu", 1708 "config"; 1709 device_type = "pci"; 1710 linux,pci-domain = <0>; 1711 bus-range = <0x00 0xff>; 1712 num-lanes = <2>; 1713 1714 #address-cells = <3>; 1715 #size-cells = <2>; 1716 1717 ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>, 1718 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1719 1720 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1721 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1722 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1723 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1724 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1725 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1726 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1727 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1728 interrupt-names = "msi0", 1729 "msi1", 1730 "msi2", 1731 "msi3", 1732 "msi4", 1733 "msi5", 1734 "msi6", 1735 "msi7"; 1736 #interrupt-cells = <1>; 1737 interrupt-map-mask = <0 0 0 0x7>; 1738 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1739 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1740 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1741 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1742 1743 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1744 <&gcc GCC_PCIE_0_AUX_CLK>, 1745 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1746 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1747 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1748 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1749 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1750 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1751 clock-names = "pipe", 1752 "aux", 1753 "cfg", 1754 "bus_master", 1755 "bus_slave", 1756 "slave_q2a", 1757 "ref", 1758 "tbu"; 1759 1760 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 1761 assigned-clock-rates = <19200000>; 1762 1763 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, 1764 <0x100 &apps_smmu 0x1d81 0x1>; 1765 1766 resets = <&gcc GCC_PCIE_0_BCR>; 1767 reset-names = "pci"; 1768 1769 power-domains = <&gcc PCIE_0_GDSC>; 1770 1771 interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>, 1772 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; 1773 interconnect-names = "pcie-mem", "cpu-pcie"; 1774 1775 phys = <&pcie0_phy>; 1776 phy-names = "pciephy"; 1777 dma-coherent; 1778 1779 status = "disabled"; 1780 }; 1781 1782 pcie0_phy: phy@1c06000 { 1783 compatible = "qcom,sc8180x-qmp-pcie-phy"; 1784 reg = <0 0x01c06000 0 0x1000>; 1785 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1786 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1787 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1788 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, 1789 <&gcc GCC_PCIE_0_PIPE_CLK>; 1790 clock-names = "aux", 1791 "cfg_ahb", 1792 "ref", 1793 "refgen", 1794 "pipe"; 1795 #clock-cells = <0>; 1796 clock-output-names = "pcie_0_pipe_clk"; 1797 #phy-cells = <0>; 1798 1799 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1800 reset-names = "phy"; 1801 1802 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1803 assigned-clock-rates = <100000000>; 1804 1805 status = "disabled"; 1806 }; 1807 1808 pcie3: pcie@1c08000 { 1809 compatible = "qcom,pcie-sc8180x"; 1810 reg = <0 0x01c08000 0 0x3000>, 1811 <0 0x40000000 0 0xf1d>, 1812 <0 0x40000f20 0 0xa8>, 1813 <0 0x40001000 0 0x1000>, 1814 <0 0x40100000 0 0x100000>; 1815 reg-names = "parf", 1816 "dbi", 1817 "elbi", 1818 "atu", 1819 "config"; 1820 device_type = "pci"; 1821 linux,pci-domain = <3>; 1822 bus-range = <0x00 0xff>; 1823 num-lanes = <2>; 1824 1825 #address-cells = <3>; 1826 #size-cells = <2>; 1827 1828 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1829 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1830 1831 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1832 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1833 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1834 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1835 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1836 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1837 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 1838 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1839 interrupt-names = "msi0", 1840 "msi1", 1841 "msi2", 1842 "msi3", 1843 "msi4", 1844 "msi5", 1845 "msi6", 1846 "msi7"; 1847 #interrupt-cells = <1>; 1848 interrupt-map-mask = <0 0 0 0x7>; 1849 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1850 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1851 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1852 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1853 1854 clocks = <&gcc GCC_PCIE_3_PIPE_CLK>, 1855 <&gcc GCC_PCIE_3_AUX_CLK>, 1856 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 1857 <&gcc GCC_PCIE_3_MSTR_AXI_CLK>, 1858 <&gcc GCC_PCIE_3_SLV_AXI_CLK>, 1859 <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>, 1860 <&gcc GCC_PCIE_3_CLKREF_CLK>, 1861 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1862 clock-names = "pipe", 1863 "aux", 1864 "cfg", 1865 "bus_master", 1866 "bus_slave", 1867 "slave_q2a", 1868 "ref", 1869 "tbu"; 1870 1871 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>; 1872 assigned-clock-rates = <19200000>; 1873 1874 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 1875 <0x100 &apps_smmu 0x1e01 0x1>; 1876 1877 resets = <&gcc GCC_PCIE_3_BCR>; 1878 reset-names = "pci"; 1879 1880 power-domains = <&gcc PCIE_3_GDSC>; 1881 1882 interconnects = <&aggre2_noc MASTER_PCIE_3 0 &mc_virt SLAVE_EBI_CH0 0>, 1883 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; 1884 interconnect-names = "pcie-mem", "cpu-pcie"; 1885 1886 phys = <&pcie3_phy>; 1887 phy-names = "pciephy"; 1888 dma-coherent; 1889 1890 status = "disabled"; 1891 }; 1892 1893 pcie3_phy: phy@1c0c000 { 1894 compatible = "qcom,sc8180x-qmp-pcie-phy"; 1895 reg = <0 0x01c0c000 0 0x1000>; 1896 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1897 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 1898 <&gcc GCC_PCIE_3_CLKREF_CLK>, 1899 <&gcc GCC_PCIE3_PHY_REFGEN_CLK>, 1900 <&gcc GCC_PCIE_3_PIPE_CLK>; 1901 clock-names = "aux", 1902 "cfg_ahb", 1903 "ref", 1904 "refgen", 1905 "pipe"; 1906 #clock-cells = <0>; 1907 clock-output-names = "pcie_3_pipe_clk"; 1908 1909 #phy-cells = <0>; 1910 1911 resets = <&gcc GCC_PCIE_3_PHY_BCR>; 1912 reset-names = "phy"; 1913 1914 assigned-clocks = <&gcc GCC_PCIE3_PHY_REFGEN_CLK>; 1915 assigned-clock-rates = <100000000>; 1916 1917 status = "disabled"; 1918 }; 1919 1920 pcie1: pcie@1c10000 { 1921 compatible = "qcom,pcie-sc8180x"; 1922 reg = <0 0x01c10000 0 0x3000>, 1923 <0 0x68000000 0 0xf1d>, 1924 <0 0x68000f20 0 0xa8>, 1925 <0 0x68001000 0 0x1000>, 1926 <0 0x68100000 0 0x100000>; 1927 reg-names = "parf", 1928 "dbi", 1929 "elbi", 1930 "atu", 1931 "config"; 1932 device_type = "pci"; 1933 linux,pci-domain = <1>; 1934 bus-range = <0x00 0xff>; 1935 num-lanes = <2>; 1936 1937 #address-cells = <3>; 1938 #size-cells = <2>; 1939 1940 ranges = <0x01000000 0x0 0x68200000 0x0 0x68200000 0x0 0x100000>, 1941 <0x02000000 0x0 0x68300000 0x0 0x68300000 0x0 0x3d00000>; 1942 1943 interrupts = <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>, 1944 <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>, 1945 <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>, 1946 <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>, 1947 <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>, 1948 <GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>, 1949 <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>, 1950 <GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>; 1951 interrupt-names = "msi0", 1952 "msi1", 1953 "msi2", 1954 "msi3", 1955 "msi4", 1956 "msi5", 1957 "msi6", 1958 "msi7"; 1959 #interrupt-cells = <1>; 1960 interrupt-map-mask = <0 0 0 0x7>; 1961 interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1962 <0 0 0 2 &intc 0 746 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1963 <0 0 0 3 &intc 0 745 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1964 <0 0 0 4 &intc 0 744 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1965 1966 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1967 <&gcc GCC_PCIE_1_AUX_CLK>, 1968 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1969 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1970 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1971 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1972 <&gcc GCC_PCIE_1_CLKREF_CLK>, 1973 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1974 clock-names = "pipe", 1975 "aux", 1976 "cfg", 1977 "bus_master", 1978 "bus_slave", 1979 "slave_q2a", 1980 "ref", 1981 "tbu"; 1982 1983 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1984 assigned-clock-rates = <19200000>; 1985 1986 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1987 <0x100 &apps_smmu 0x1c81 0x1>; 1988 1989 resets = <&gcc GCC_PCIE_1_BCR>; 1990 reset-names = "pci"; 1991 1992 power-domains = <&gcc PCIE_1_GDSC>; 1993 1994 interconnects = <&aggre2_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI_CH0 0>, 1995 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; 1996 interconnect-names = "pcie-mem", "cpu-pcie"; 1997 1998 phys = <&pcie1_phy>; 1999 phy-names = "pciephy"; 2000 dma-coherent; 2001 2002 status = "disabled"; 2003 }; 2004 2005 pcie1_phy: phy@1c16000 { 2006 compatible = "qcom,sc8180x-qmp-pcie-phy"; 2007 reg = <0 0x01c16000 0 0x1000>; 2008 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2009 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2010 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2011 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, 2012 <&gcc GCC_PCIE_1_PIPE_CLK>; 2013 clock-names = "aux", 2014 "cfg_ahb", 2015 "ref", 2016 "refgen", 2017 "pipe"; 2018 #clock-cells = <0>; 2019 clock-output-names = "pcie_1_pipe_clk"; 2020 2021 #phy-cells = <0>; 2022 2023 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2024 reset-names = "phy"; 2025 2026 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2027 assigned-clock-rates = <100000000>; 2028 2029 status = "disabled"; 2030 }; 2031 2032 pcie2: pcie@1c18000 { 2033 compatible = "qcom,pcie-sc8180x"; 2034 reg = <0 0x01c18000 0 0x3000>, 2035 <0 0x70000000 0 0xf1d>, 2036 <0 0x70000f20 0 0xa8>, 2037 <0 0x70001000 0 0x1000>, 2038 <0 0x70100000 0 0x100000>; 2039 reg-names = "parf", 2040 "dbi", 2041 "elbi", 2042 "atu", 2043 "config"; 2044 device_type = "pci"; 2045 linux,pci-domain = <2>; 2046 bus-range = <0x00 0xff>; 2047 num-lanes = <4>; 2048 2049 #address-cells = <3>; 2050 #size-cells = <2>; 2051 2052 ranges = <0x01000000 0x0 0x70200000 0x0 0x70200000 0x0 0x100000>, 2053 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>; 2054 2055 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2056 <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>, 2057 <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>, 2058 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 2059 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>, 2060 <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>, 2061 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 2062 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>; 2063 interrupt-names = "msi0", 2064 "msi1", 2065 "msi2", 2066 "msi3", 2067 "msi4", 2068 "msi5", 2069 "msi6", 2070 "msi7"; 2071 #interrupt-cells = <1>; 2072 interrupt-map-mask = <0 0 0 0x7>; 2073 interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2074 <0 0 0 2 &intc 0 662 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2075 <0 0 0 3 &intc 0 661 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2076 <0 0 0 4 &intc 0 660 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2077 2078 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2079 <&gcc GCC_PCIE_2_AUX_CLK>, 2080 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2081 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2082 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 2083 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 2084 <&gcc GCC_PCIE_2_CLKREF_CLK>, 2085 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2086 clock-names = "pipe", 2087 "aux", 2088 "cfg", 2089 "bus_master", 2090 "bus_slave", 2091 "slave_q2a", 2092 "ref", 2093 "tbu"; 2094 2095 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 2096 assigned-clock-rates = <19200000>; 2097 2098 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 2099 <0x100 &apps_smmu 0x1d01 0x1>; 2100 2101 resets = <&gcc GCC_PCIE_2_BCR>; 2102 reset-names = "pci"; 2103 2104 power-domains = <&gcc PCIE_2_GDSC>; 2105 2106 interconnects = <&aggre2_noc MASTER_PCIE_2 0 &mc_virt SLAVE_EBI_CH0 0>, 2107 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; 2108 interconnect-names = "pcie-mem", "cpu-pcie"; 2109 2110 phys = <&pcie2_phy>; 2111 phy-names = "pciephy"; 2112 dma-coherent; 2113 2114 status = "disabled"; 2115 }; 2116 2117 pcie2_phy: phy@1c1c000 { 2118 compatible = "qcom,sc8180x-qmp-pcie-phy"; 2119 reg = <0 0x01c1c000 0 0x1000>; 2120 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2121 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2122 <&gcc GCC_PCIE_2_CLKREF_CLK>, 2123 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>, 2124 <&gcc GCC_PCIE_2_PIPE_CLK>; 2125 clock-names = "aux", 2126 "cfg_ahb", 2127 "ref", 2128 "refgen", 2129 "pipe"; 2130 #clock-cells = <0>; 2131 clock-output-names = "pcie_2_pipe_clk"; 2132 2133 #phy-cells = <0>; 2134 2135 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 2136 reset-names = "phy"; 2137 2138 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2139 assigned-clock-rates = <100000000>; 2140 2141 status = "disabled"; 2142 }; 2143 2144 ufs_mem_hc: ufshc@1d84000 { 2145 compatible = "qcom,sc8180x-ufshc", "qcom,ufshc", 2146 "jedec,ufs-2.0"; 2147 reg = <0 0x01d84000 0 0x2500>; 2148 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2149 phys = <&ufs_mem_phy>; 2150 phy-names = "ufsphy"; 2151 lanes-per-direction = <2>; 2152 #reset-cells = <1>; 2153 resets = <&gcc GCC_UFS_PHY_BCR>; 2154 reset-names = "rst"; 2155 2156 iommus = <&apps_smmu 0x300 0>; 2157 2158 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2159 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2160 <&gcc GCC_UFS_PHY_AHB_CLK>, 2161 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2162 <&rpmhcc RPMH_CXO_CLK>, 2163 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2164 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2165 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2166 clock-names = "core_clk", 2167 "bus_aggr_clk", 2168 "iface_clk", 2169 "core_clk_unipro", 2170 "ref_clk", 2171 "tx_lane0_sync_clk", 2172 "rx_lane0_sync_clk", 2173 "rx_lane1_sync_clk"; 2174 freq-table-hz = <37500000 300000000>, 2175 <0 0>, 2176 <0 0>, 2177 <37500000 300000000>, 2178 <0 0>, 2179 <0 0>, 2180 <0 0>, 2181 <0 0>; 2182 2183 power-domains = <&gcc UFS_PHY_GDSC>; 2184 2185 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2186 &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, 2187 <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS 2188 &config_noc SLAVE_UFS_MEM_0_CFG QCOM_ICC_TAG_ALWAYS>; 2189 interconnect-names = "ufs-ddr", "cpu-ufs"; 2190 2191 status = "disabled"; 2192 }; 2193 2194 ufs_mem_phy: phy-wrapper@1d87000 { 2195 compatible = "qcom,sc8180x-qmp-ufs-phy"; 2196 reg = <0 0x01d87000 0 0x1000>; 2197 2198 clocks = <&rpmhcc RPMH_CXO_CLK>, 2199 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2200 <&gcc GCC_UFS_MEM_CLKREF_EN>; 2201 clock-names = "ref", 2202 "ref_aux", 2203 "qref"; 2204 2205 resets = <&ufs_mem_hc 0>; 2206 reset-names = "ufsphy"; 2207 2208 #phy-cells = <0>; 2209 2210 status = "disabled"; 2211 }; 2212 2213 ipa_virt: interconnect@1e00000 { 2214 compatible = "qcom,sc8180x-ipa-virt"; 2215 reg = <0 0x01e00000 0 0x1000>; 2216 #interconnect-cells = <2>; 2217 qcom,bcm-voters = <&apps_bcm_voter>; 2218 }; 2219 2220 tcsr_mutex: hwlock@1f40000 { 2221 compatible = "qcom,tcsr-mutex"; 2222 reg = <0x0 0x01f40000 0x0 0x40000>; 2223 #hwlock-cells = <1>; 2224 }; 2225 2226 gpu: gpu@2c00000 { 2227 compatible = "qcom,adreno-680.1", "qcom,adreno"; 2228 #stream-id-cells = <16>; 2229 2230 reg = <0 0x02c00000 0 0x40000>; 2231 reg-names = "kgsl_3d0_reg_memory"; 2232 2233 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2234 2235 iommus = <&adreno_smmu 0 0xc01>; 2236 2237 operating-points-v2 = <&gpu_opp_table>; 2238 2239 interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &mc_virt SLAVE_EBI_CH0 0>; 2240 interconnect-names = "gfx-mem"; 2241 2242 qcom,gmu = <&gmu>; 2243 #cooling-cells = <2>; 2244 2245 status = "disabled"; 2246 2247 gpu_opp_table: opp-table { 2248 compatible = "operating-points-v2"; 2249 2250 opp-514000000 { 2251 opp-hz = /bits/ 64 <514000000>; 2252 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2253 }; 2254 2255 opp-500000000 { 2256 opp-hz = /bits/ 64 <500000000>; 2257 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2258 }; 2259 2260 opp-461000000 { 2261 opp-hz = /bits/ 64 <461000000>; 2262 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2263 }; 2264 2265 opp-405000000 { 2266 opp-hz = /bits/ 64 <405000000>; 2267 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2268 }; 2269 2270 opp-315000000 { 2271 opp-hz = /bits/ 64 <315000000>; 2272 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2273 }; 2274 2275 opp-256000000 { 2276 opp-hz = /bits/ 64 <256000000>; 2277 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2278 }; 2279 2280 opp-177000000 { 2281 opp-hz = /bits/ 64 <177000000>; 2282 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2283 }; 2284 }; 2285 }; 2286 2287 gmu: gmu@2c6a000 { 2288 compatible = "qcom,adreno-gmu-680.1", "qcom,adreno-gmu"; 2289 2290 reg = <0 0x02c6a000 0 0x30000>, 2291 <0 0x0b290000 0 0x10000>, 2292 <0 0x0b490000 0 0x10000>; 2293 reg-names = "gmu", 2294 "gmu_pdc", 2295 "gmu_pdc_seq"; 2296 2297 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2298 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2299 interrupt-names = "hfi", "gmu"; 2300 2301 clocks = <&gpucc GPU_CC_AHB_CLK>, 2302 <&gpucc GPU_CC_CX_GMU_CLK>, 2303 <&gpucc GPU_CC_CXO_CLK>, 2304 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2305 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2306 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2307 2308 power-domains = <&gpucc GPU_CX_GDSC>, 2309 <&gpucc GPU_GX_GDSC>; 2310 power-domain-names = "cx", "gx"; 2311 2312 iommus = <&adreno_smmu 5 0xc00>; 2313 2314 operating-points-v2 = <&gmu_opp_table>; 2315 2316 gmu_opp_table: opp-table { 2317 compatible = "operating-points-v2"; 2318 2319 opp-200000000 { 2320 opp-hz = /bits/ 64 <200000000>; 2321 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2322 }; 2323 2324 opp-500000000 { 2325 opp-hz = /bits/ 64 <500000000>; 2326 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2327 }; 2328 }; 2329 }; 2330 2331 gpucc: clock-controller@2c90000 { 2332 compatible = "qcom,sc8180x-gpucc"; 2333 reg = <0 0x02c90000 0 0x9000>; 2334 clocks = <&rpmhcc RPMH_CXO_CLK>, 2335 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2336 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2337 clock-names = "bi_tcxo", 2338 "gcc_gpu_gpll0_clk_src", 2339 "gcc_gpu_gpll0_div_clk_src"; 2340 #clock-cells = <1>; 2341 #reset-cells = <1>; 2342 #power-domain-cells = <1>; 2343 }; 2344 2345 adreno_smmu: iommu@2ca0000 { 2346 compatible = "qcom,sc8180x-smmu-500", "qcom,adreno-smmu", 2347 "qcom,smmu-500", "arm,mmu-500"; 2348 reg = <0 0x02ca0000 0 0x10000>; 2349 #iommu-cells = <2>; 2350 #global-interrupts = <1>; 2351 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 2352 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2353 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2354 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2355 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2356 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2357 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2358 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2359 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 2360 clocks = <&gpucc GPU_CC_AHB_CLK>, 2361 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2362 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2363 clock-names = "ahb", "bus", "iface"; 2364 2365 power-domains = <&gpucc GPU_CX_GDSC>; 2366 }; 2367 2368 tlmm: pinctrl@3100000 { 2369 compatible = "qcom,sc8180x-tlmm"; 2370 reg = <0 0x03100000 0 0x300000>, 2371 <0 0x03500000 0 0x700000>, 2372 <0 0x03d00000 0 0x300000>; 2373 reg-names = "west", "east", "south"; 2374 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2375 gpio-controller; 2376 #gpio-cells = <2>; 2377 interrupt-controller; 2378 #interrupt-cells = <2>; 2379 gpio-ranges = <&tlmm 0 0 191>; 2380 wakeup-parent = <&pdc>; 2381 }; 2382 2383 remoteproc_mpss: remoteproc@4080000 { 2384 compatible = "qcom,sc8180x-mpss-pas"; 2385 reg = <0x0 0x04080000 0x0 0x4040>; 2386 2387 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2388 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2389 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2390 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2391 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2392 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2393 interrupt-names = "wdog", "fatal", "ready", "handover", 2394 "stop-ack", "shutdown-ack"; 2395 2396 clocks = <&rpmhcc RPMH_CXO_CLK>; 2397 clock-names = "xo"; 2398 2399 power-domains = <&rpmhpd SC8180X_CX>, 2400 <&rpmhpd SC8180X_MSS>; 2401 power-domain-names = "cx", "mss"; 2402 2403 qcom,qmp = <&aoss_qmp>; 2404 2405 qcom,smem-states = <&modem_smp2p_out 0>; 2406 qcom,smem-state-names = "stop"; 2407 2408 glink-edge { 2409 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2410 label = "modem"; 2411 qcom,remote-pid = <1>; 2412 mboxes = <&apss_shared 12>; 2413 }; 2414 }; 2415 2416 remoteproc_cdsp: remoteproc@8300000 { 2417 compatible = "qcom,sc8180x-cdsp-pas"; 2418 reg = <0x0 0x08300000 0x0 0x4040>; 2419 2420 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2421 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2422 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2423 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2424 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2425 interrupt-names = "wdog", "fatal", "ready", 2426 "handover", "stop-ack"; 2427 2428 clocks = <&rpmhcc RPMH_CXO_CLK>; 2429 clock-names = "xo"; 2430 2431 power-domains = <&rpmhpd SC8180X_CX>; 2432 power-domain-names = "cx"; 2433 2434 qcom,qmp = <&aoss_qmp>; 2435 2436 qcom,smem-states = <&cdsp_smp2p_out 0>; 2437 qcom,smem-state-names = "stop"; 2438 2439 status = "disabled"; 2440 2441 glink-edge { 2442 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 2443 label = "cdsp"; 2444 qcom,remote-pid = <5>; 2445 mboxes = <&apss_shared 4>; 2446 }; 2447 }; 2448 2449 usb_prim_hsphy: phy@88e2000 { 2450 compatible = "qcom,sc8180x-usb-hs-phy", 2451 "qcom,usb-snps-hs-7nm-phy"; 2452 reg = <0 0x088e2000 0 0x400>; 2453 clocks = <&rpmhcc RPMH_CXO_CLK>; 2454 clock-names = "ref"; 2455 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2456 2457 #phy-cells = <0>; 2458 2459 status = "disabled"; 2460 }; 2461 2462 usb_sec_hsphy: phy@88e3000 { 2463 compatible = "qcom,sc8180x-usb-hs-phy", 2464 "qcom,usb-snps-hs-7nm-phy"; 2465 reg = <0 0x088e3000 0 0x400>; 2466 clocks = <&rpmhcc RPMH_CXO_CLK>; 2467 clock-names = "ref"; 2468 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2469 2470 #phy-cells = <0>; 2471 2472 status = "disabled"; 2473 }; 2474 2475 usb_prim_qmpphy: phy@88e9000 { 2476 compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; 2477 reg = <0 0x088e9000 0 0x18c>, 2478 <0 0x088e8000 0 0x38>, 2479 <0 0x088ea000 0 0x40>; 2480 reg-names = "reg-base", "dp_com"; 2481 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2482 <&rpmhcc RPMH_CXO_CLK>, 2483 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2484 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2485 clock-names = "aux", 2486 "ref_clk_src", 2487 "ref", 2488 "com_aux"; 2489 resets = <&gcc GCC_USB3_DP_PHY_PRIM_SP0_BCR>, 2490 <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>; 2491 reset-names = "phy", "common"; 2492 2493 #clock-cells = <1>; 2494 #address-cells = <2>; 2495 #size-cells = <2>; 2496 ranges; 2497 2498 status = "disabled"; 2499 2500 ports { 2501 #address-cells = <1>; 2502 #size-cells = <0>; 2503 2504 port@0 { 2505 reg = <0>; 2506 2507 usb_prim_qmpphy_out: endpoint {}; 2508 }; 2509 2510 port@2 { 2511 reg = <2>; 2512 2513 usb_prim_qmpphy_dp_in: endpoint {}; 2514 }; 2515 }; 2516 2517 usb_prim_ssphy: usb3-phy@88e9200 { 2518 reg = <0 0x088e9200 0 0x200>, 2519 <0 0x088e9400 0 0x200>, 2520 <0 0x088e9c00 0 0x218>, 2521 <0 0x088e9600 0 0x200>, 2522 <0 0x088e9800 0 0x200>, 2523 <0 0x088e9a00 0 0x100>; 2524 #phy-cells = <0>; 2525 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2526 clock-names = "pipe0"; 2527 clock-output-names = "usb3_prim_phy_pipe_clk_src"; 2528 }; 2529 2530 usb_prim_dpphy: dp-phy@88ea200 { 2531 reg = <0 0x088ea200 0 0x200>, 2532 <0 0x088ea400 0 0x200>, 2533 <0 0x088eaa00 0 0x200>, 2534 <0 0x088ea600 0 0x200>, 2535 <0 0x088ea800 0 0x200>; 2536 #clock-cells = <1>; 2537 #phy-cells = <0>; 2538 }; 2539 }; 2540 2541 usb_sec_qmpphy: phy@88ee000 { 2542 compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; 2543 reg = <0 0x088ee000 0 0x18c>, 2544 <0 0x088ed000 0 0x10>, 2545 <0 0x088ef000 0 0x40>; 2546 reg-names = "reg-base", "dp_com"; 2547 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2548 <&rpmhcc RPMH_CXO_CLK>, 2549 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 2550 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2551 clock-names = "aux", 2552 "ref_clk_src", 2553 "ref", 2554 "com_aux"; 2555 resets = <&gcc GCC_USB3_DP_PHY_SEC_BCR>, 2556 <&gcc GCC_USB3_PHY_SEC_BCR>; 2557 reset-names = "phy", "common"; 2558 2559 #clock-cells = <1>; 2560 #address-cells = <2>; 2561 #size-cells = <2>; 2562 ranges; 2563 2564 status = "disabled"; 2565 2566 ports { 2567 #address-cells = <1>; 2568 #size-cells = <0>; 2569 2570 port@0 { 2571 reg = <0>; 2572 2573 usb_sec_qmpphy_out: endpoint {}; 2574 }; 2575 2576 port@2 { 2577 reg = <2>; 2578 2579 usb_sec_qmpphy_dp_in: endpoint {}; 2580 }; 2581 }; 2582 2583 usb_sec_ssphy: usb3-phy@88e9200 { 2584 reg = <0 0x088ee200 0 0x200>, 2585 <0 0x088ee400 0 0x200>, 2586 <0 0x088eec00 0 0x218>, 2587 <0 0x088ee600 0 0x200>, 2588 <0 0x088ee800 0 0x200>, 2589 <0 0x088eea00 0 0x100>; 2590 #phy-cells = <0>; 2591 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2592 clock-names = "pipe0"; 2593 clock-output-names = "usb3_sec_phy_pipe_clk_src"; 2594 }; 2595 2596 usb_sec_dpphy: dp-phy@88ef200 { 2597 reg = <0 0x088ef200 0 0x200>, 2598 <0 0x088ef400 0 0x200>, 2599 <0 0x088efa00 0 0x200>, 2600 <0 0x088ef600 0 0x200>, 2601 <0 0x088ef800 0 0x200>; 2602 #clock-cells = <1>; 2603 #phy-cells = <0>; 2604 clock-output-names = "qmp_dptx1_phy_pll_link_clk", 2605 "qmp_dptx1_phy_pll_vco_div_clk"; 2606 }; 2607 }; 2608 2609 system-cache-controller@9200000 { 2610 compatible = "qcom,sc8180x-llcc"; 2611 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, 2612 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, 2613 <0 0x09600000 0 0x50000>; 2614 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2615 "llcc3_base", "llcc_broadcast_base"; 2616 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2617 }; 2618 2619 gem_noc: interconnect@9680000 { 2620 compatible = "qcom,sc8180x-gem-noc"; 2621 reg = <0 0x09680000 0 0x58200>; 2622 #interconnect-cells = <2>; 2623 qcom,bcm-voters = <&apps_bcm_voter>; 2624 }; 2625 2626 usb_prim: usb@a6f8800 { 2627 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3"; 2628 reg = <0 0x0a6f8800 0 0x400>; 2629 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2630 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 2631 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 2632 <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 2633 interrupt-names = "hs_phy_irq", 2634 "ss_phy_irq", 2635 "dm_hs_phy_irq", 2636 "dp_hs_phy_irq"; 2637 2638 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2639 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2640 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2641 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2642 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2643 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 2644 clock-names = "cfg_noc", 2645 "core", 2646 "iface", 2647 "sleep", 2648 "mock_utmi", 2649 "xo"; 2650 resets = <&gcc GCC_USB30_PRIM_BCR>; 2651 power-domains = <&gcc USB30_PRIM_GDSC>; 2652 2653 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, 2654 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 2655 interconnect-names = "usb-ddr", "apps-usb"; 2656 2657 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2658 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2659 assigned-clock-rates = <19200000>, <200000000>; 2660 2661 #address-cells = <2>; 2662 #size-cells = <2>; 2663 ranges; 2664 dma-ranges; 2665 2666 status = "disabled"; 2667 2668 usb_prim_dwc3: usb@a600000 { 2669 compatible = "snps,dwc3"; 2670 reg = <0 0x0a600000 0 0xcd00>; 2671 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2672 iommus = <&apps_smmu 0x140 0>; 2673 snps,dis_u2_susphy_quirk; 2674 snps,dis_enblslpm_quirk; 2675 phys = <&usb_prim_hsphy>, <&usb_prim_ssphy>; 2676 phy-names = "usb2-phy", "usb3-phy"; 2677 2678 port { 2679 usb_prim_role_switch: endpoint { 2680 }; 2681 }; 2682 }; 2683 }; 2684 2685 usb_sec: usb@a8f8800 { 2686 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3"; 2687 reg = <0 0x0a8f8800 0 0x400>; 2688 2689 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2690 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2691 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2692 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2693 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2694 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 2695 clock-names = "cfg_noc", 2696 "core", 2697 "iface", 2698 "sleep", 2699 "mock_utmi", 2700 "xo"; 2701 resets = <&gcc GCC_USB30_SEC_BCR>; 2702 power-domains = <&gcc USB30_SEC_GDSC>; 2703 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2704 <&pdc 7 IRQ_TYPE_LEVEL_HIGH>, 2705 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 2706 <&pdc 11 IRQ_TYPE_EDGE_BOTH>; 2707 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2708 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2709 2710 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2711 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2712 assigned-clock-rates = <19200000>, <200000000>; 2713 2714 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, 2715 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; 2716 interconnect-names = "usb-ddr", "apps-usb"; 2717 2718 #address-cells = <2>; 2719 #size-cells = <2>; 2720 ranges; 2721 dma-ranges; 2722 2723 status = "disabled"; 2724 2725 usb_sec_dwc3: usb@a800000 { 2726 compatible = "snps,dwc3"; 2727 reg = <0 0x0a800000 0 0xcd00>; 2728 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2729 iommus = <&apps_smmu 0x160 0>; 2730 snps,dis_u2_susphy_quirk; 2731 snps,dis_enblslpm_quirk; 2732 phys = <&usb_sec_hsphy>, <&usb_sec_ssphy>; 2733 phy-names = "usb2-phy", "usb3-phy"; 2734 2735 port { 2736 usb_sec_role_switch: endpoint { 2737 }; 2738 }; 2739 }; 2740 }; 2741 2742 mdss: mdss@ae00000 { 2743 compatible = "qcom,sc8180x-mdss"; 2744 reg = <0 0x0ae00000 0 0x1000>; 2745 reg-names = "mdss"; 2746 2747 power-domains = <&dispcc MDSS_GDSC>; 2748 2749 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2750 <&gcc GCC_DISP_HF_AXI_CLK>, 2751 <&gcc GCC_DISP_SF_AXI_CLK>, 2752 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2753 clock-names = "iface", 2754 "bus", 2755 "nrt_bus", 2756 "core"; 2757 2758 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2759 2760 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2761 interrupt-controller; 2762 #interrupt-cells = <1>; 2763 2764 interconnects = <&mmss_noc MASTER_MDP_PORT0 QCOM_ICC_TAG_ALWAYS 2765 &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, 2766 <&mmss_noc MASTER_MDP_PORT1 QCOM_ICC_TAG_ALWAYS 2767 &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, 2768 <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS 2769 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>; 2770 interconnect-names = "mdp0-mem", 2771 "mdp1-mem", 2772 "cpu-cfg"; 2773 2774 iommus = <&apps_smmu 0x800 0x420>; 2775 2776 #address-cells = <2>; 2777 #size-cells = <2>; 2778 ranges; 2779 2780 status = "disabled"; 2781 2782 mdss_mdp: mdp@ae01000 { 2783 compatible = "qcom,sc8180x-dpu"; 2784 reg = <0 0x0ae01000 0 0x8f000>, 2785 <0 0x0aeb0000 0 0x2008>; 2786 reg-names = "mdp", "vbif"; 2787 2788 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2789 <&gcc GCC_DISP_HF_AXI_CLK>, 2790 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2791 <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 2792 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2793 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; 2794 clock-names = "iface", 2795 "bus", 2796 "core", 2797 "vsync", 2798 "rot", 2799 "lut"; 2800 2801 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2802 assigned-clock-rates = <19200000>; 2803 2804 operating-points-v2 = <&mdp_opp_table>; 2805 power-domains = <&rpmhpd SC8180X_MMCX>; 2806 2807 interrupt-parent = <&mdss>; 2808 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 2809 2810 ports { 2811 #address-cells = <1>; 2812 #size-cells = <0>; 2813 2814 port@0 { 2815 reg = <0>; 2816 dpu_intf0_out: endpoint { 2817 remote-endpoint = <&dp0_in>; 2818 }; 2819 }; 2820 2821 port@1 { 2822 reg = <1>; 2823 dpu_intf1_out: endpoint { 2824 remote-endpoint = <&mdss_dsi0_in>; 2825 }; 2826 }; 2827 2828 port@2 { 2829 reg = <2>; 2830 dpu_intf2_out: endpoint { 2831 remote-endpoint = <&mdss_dsi1_in>; 2832 }; 2833 }; 2834 2835 port@4 { 2836 reg = <4>; 2837 dpu_intf4_out: endpoint { 2838 remote-endpoint = <&dp1_in>; 2839 }; 2840 }; 2841 2842 port@5 { 2843 reg = <5>; 2844 dpu_intf5_out: endpoint { 2845 remote-endpoint = <&edp_in>; 2846 }; 2847 }; 2848 }; 2849 2850 mdp_opp_table: opp-table { 2851 compatible = "operating-points-v2"; 2852 2853 opp-200000000 { 2854 opp-hz = /bits/ 64 <200000000>; 2855 required-opps = <&rpmhpd_opp_low_svs>; 2856 }; 2857 2858 opp-300000000 { 2859 opp-hz = /bits/ 64 <300000000>; 2860 required-opps = <&rpmhpd_opp_svs>; 2861 }; 2862 2863 opp-345000000 { 2864 opp-hz = /bits/ 64 <345000000>; 2865 required-opps = <&rpmhpd_opp_svs_l1>; 2866 }; 2867 2868 opp-460000000 { 2869 opp-hz = /bits/ 64 <460000000>; 2870 required-opps = <&rpmhpd_opp_nom>; 2871 }; 2872 }; 2873 }; 2874 2875 mdss_dsi0: dsi@ae94000 { 2876 compatible = "qcom,mdss-dsi-ctrl"; 2877 reg = <0 0x0ae94000 0 0x400>; 2878 reg-names = "dsi_ctrl"; 2879 2880 interrupt-parent = <&mdss>; 2881 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 2882 2883 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2884 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2885 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2886 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2887 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2888 <&gcc GCC_DISP_HF_AXI_CLK>; 2889 clock-names = "byte", 2890 "byte_intf", 2891 "pixel", 2892 "core", 2893 "iface", 2894 "bus"; 2895 2896 operating-points-v2 = <&dsi_opp_table>; 2897 power-domains = <&rpmhpd SC8180X_MMCX>; 2898 2899 phys = <&mdss_dsi0_phy>; 2900 phy-names = "dsi"; 2901 2902 status = "disabled"; 2903 2904 ports { 2905 #address-cells = <1>; 2906 #size-cells = <0>; 2907 2908 port@0 { 2909 reg = <0>; 2910 mdss_dsi0_in: endpoint { 2911 remote-endpoint = <&dpu_intf1_out>; 2912 }; 2913 }; 2914 2915 port@1 { 2916 reg = <1>; 2917 mdss_dsi0_out: endpoint { 2918 }; 2919 }; 2920 }; 2921 2922 dsi_opp_table: opp-table { 2923 compatible = "operating-points-v2"; 2924 2925 opp-187500000 { 2926 opp-hz = /bits/ 64 <187500000>; 2927 required-opps = <&rpmhpd_opp_low_svs>; 2928 }; 2929 2930 opp-300000000 { 2931 opp-hz = /bits/ 64 <300000000>; 2932 required-opps = <&rpmhpd_opp_svs>; 2933 }; 2934 2935 opp-358000000 { 2936 opp-hz = /bits/ 64 <358000000>; 2937 required-opps = <&rpmhpd_opp_svs_l1>; 2938 }; 2939 }; 2940 }; 2941 2942 mdss_dsi0_phy: dsi-phy@ae94400 { 2943 compatible = "qcom,dsi-phy-7nm"; 2944 reg = <0 0x0ae94400 0 0x200>, 2945 <0 0x0ae94600 0 0x280>, 2946 <0 0x0ae94900 0 0x260>; 2947 reg-names = "dsi_phy", 2948 "dsi_phy_lane", 2949 "dsi_pll"; 2950 2951 #clock-cells = <1>; 2952 #phy-cells = <0>; 2953 2954 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2955 <&rpmhcc RPMH_CXO_CLK>; 2956 clock-names = "iface", "ref"; 2957 2958 status = "disabled"; 2959 }; 2960 2961 mdss_dsi1: dsi@ae96000 { 2962 compatible = "qcom,mdss-dsi-ctrl"; 2963 reg = <0 0x0ae96000 0 0x400>; 2964 reg-names = "dsi_ctrl"; 2965 2966 interrupt-parent = <&mdss>; 2967 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 2968 2969 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2970 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2971 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2972 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2973 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2974 <&gcc GCC_DISP_HF_AXI_CLK>; 2975 clock-names = "byte", 2976 "byte_intf", 2977 "pixel", 2978 "core", 2979 "iface", 2980 "bus"; 2981 2982 operating-points-v2 = <&dsi_opp_table>; 2983 power-domains = <&rpmhpd SC8180X_MMCX>; 2984 2985 phys = <&mdss_dsi1_phy>; 2986 phy-names = "dsi"; 2987 2988 status = "disabled"; 2989 2990 ports { 2991 #address-cells = <1>; 2992 #size-cells = <0>; 2993 2994 port@0 { 2995 reg = <0>; 2996 mdss_dsi1_in: endpoint { 2997 remote-endpoint = <&dpu_intf2_out>; 2998 }; 2999 }; 3000 3001 port@1 { 3002 reg = <1>; 3003 mdss_dsi1_out: endpoint { 3004 }; 3005 }; 3006 }; 3007 }; 3008 3009 mdss_dsi1_phy: dsi-phy@ae96400 { 3010 compatible = "qcom,dsi-phy-7nm"; 3011 reg = <0 0x0ae96400 0 0x200>, 3012 <0 0x0ae96600 0 0x280>, 3013 <0 0x0ae96900 0 0x260>; 3014 reg-names = "dsi_phy", 3015 "dsi_phy_lane", 3016 "dsi_pll"; 3017 3018 #clock-cells = <1>; 3019 #phy-cells = <0>; 3020 3021 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3022 <&rpmhcc RPMH_CXO_CLK>; 3023 clock-names = "iface", "ref"; 3024 3025 status = "disabled"; 3026 }; 3027 3028 mdss_dp0: displayport-controller@ae90000 { 3029 compatible = "qcom,sc8180x-dp"; 3030 reg = <0 0xae90000 0 0x200>, 3031 <0 0xae90200 0 0x200>, 3032 <0 0xae90400 0 0x600>, 3033 <0 0xae90a00 0 0x400>; 3034 interrupt-parent = <&mdss>; 3035 interrupts = <12>; 3036 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3037 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3038 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3039 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3040 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3041 clock-names = "core_iface", 3042 "core_aux", 3043 "ctrl_link", 3044 "ctrl_link_iface", 3045 "stream_pixel"; 3046 3047 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3048 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3049 assigned-clock-parents = <&usb_prim_dpphy 0>, <&usb_prim_dpphy 1>; 3050 3051 phys = <&usb_prim_dpphy>; 3052 phy-names = "dp"; 3053 3054 #sound-dai-cells = <0>; 3055 3056 operating-points-v2 = <&dp0_opp_table>; 3057 power-domains = <&rpmhpd SC8180X_MMCX>; 3058 3059 status = "disabled"; 3060 3061 ports { 3062 #address-cells = <1>; 3063 #size-cells = <0>; 3064 3065 port@0 { 3066 reg = <0>; 3067 dp0_in: endpoint { 3068 remote-endpoint = <&dpu_intf0_out>; 3069 }; 3070 }; 3071 3072 port@1 { 3073 reg = <1>; 3074 mdss_dp0_out: endpoint { 3075 }; 3076 }; 3077 }; 3078 3079 dp0_opp_table: opp-table { 3080 compatible = "operating-points-v2"; 3081 3082 opp-160000000 { 3083 opp-hz = /bits/ 64 <160000000>; 3084 required-opps = <&rpmhpd_opp_low_svs>; 3085 }; 3086 3087 opp-270000000 { 3088 opp-hz = /bits/ 64 <270000000>; 3089 required-opps = <&rpmhpd_opp_svs>; 3090 }; 3091 3092 opp-540000000 { 3093 opp-hz = /bits/ 64 <540000000>; 3094 required-opps = <&rpmhpd_opp_svs_l1>; 3095 }; 3096 3097 opp-810000000 { 3098 opp-hz = /bits/ 64 <810000000>; 3099 required-opps = <&rpmhpd_opp_nom>; 3100 }; 3101 }; 3102 }; 3103 3104 mdss_dp1: displayport-controller@ae98000 { 3105 compatible = "qcom,sc8180x-dp"; 3106 reg = <0 0xae98000 0 0x200>, 3107 <0 0xae98200 0 0x200>, 3108 <0 0xae98400 0 0x600>, 3109 <0 0xae98a00 0 0x400>; 3110 interrupt-parent = <&mdss>; 3111 interrupts = <13>; 3112 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3113 <&dispcc DISP_CC_MDSS_DP_AUX1_CLK>, 3114 <&dispcc DISP_CC_MDSS_DP_LINK1_CLK>, 3115 <&dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>, 3116 <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>; 3117 clock-names = "core_iface", 3118 "core_aux", 3119 "ctrl_link", 3120 "ctrl_link_iface", 3121 "stream_pixel"; 3122 3123 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>, 3124 <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>; 3125 assigned-clock-parents = <&usb_sec_dpphy 0>, <&usb_sec_dpphy 1>; 3126 3127 phys = <&usb_sec_dpphy>; 3128 phy-names = "dp"; 3129 3130 #sound-dai-cells = <0>; 3131 3132 operating-points-v2 = <&dp0_opp_table>; 3133 power-domains = <&rpmhpd SC8180X_MMCX>; 3134 3135 status = "disabled"; 3136 3137 ports { 3138 #address-cells = <1>; 3139 #size-cells = <0>; 3140 3141 port@0 { 3142 reg = <0>; 3143 dp1_in: endpoint { 3144 remote-endpoint = <&dpu_intf4_out>; 3145 }; 3146 }; 3147 3148 port@1 { 3149 reg = <1>; 3150 mdss_dp1_out: endpoint { 3151 }; 3152 }; 3153 }; 3154 3155 dp1_opp_table: opp-table { 3156 compatible = "operating-points-v2"; 3157 3158 opp-160000000 { 3159 opp-hz = /bits/ 64 <160000000>; 3160 required-opps = <&rpmhpd_opp_low_svs>; 3161 }; 3162 3163 opp-270000000 { 3164 opp-hz = /bits/ 64 <270000000>; 3165 required-opps = <&rpmhpd_opp_svs>; 3166 }; 3167 3168 opp-540000000 { 3169 opp-hz = /bits/ 64 <540000000>; 3170 required-opps = <&rpmhpd_opp_svs_l1>; 3171 }; 3172 3173 opp-810000000 { 3174 opp-hz = /bits/ 64 <810000000>; 3175 required-opps = <&rpmhpd_opp_nom>; 3176 }; 3177 }; 3178 }; 3179 3180 mdss_edp: displayport-controller@ae9a000 { 3181 compatible = "qcom,sc8180x-edp"; 3182 reg = <0 0xae9a000 0 0x200>, 3183 <0 0xae9a200 0 0x200>, 3184 <0 0xae9a400 0 0x600>, 3185 <0 0xae9aa00 0 0x400>; 3186 interrupt-parent = <&mdss>; 3187 interrupts = <14>; 3188 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3189 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3190 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 3191 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 3192 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 3193 clock-names = "core_iface", 3194 "core_aux", 3195 "ctrl_link", 3196 "ctrl_link_iface", 3197 "stream_pixel"; 3198 3199 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 3200 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 3201 assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>; 3202 3203 phys = <&edp_phy>; 3204 phy-names = "dp"; 3205 3206 operating-points-v2 = <&edp_opp_table>; 3207 power-domains = <&rpmhpd SC8180X_MMCX>; 3208 3209 status = "disabled"; 3210 3211 ports { 3212 #address-cells = <1>; 3213 #size-cells = <0>; 3214 3215 port@0 { 3216 reg = <0>; 3217 edp_in: endpoint { 3218 remote-endpoint = <&dpu_intf5_out>; 3219 }; 3220 }; 3221 }; 3222 3223 edp_opp_table: opp-table { 3224 compatible = "operating-points-v2"; 3225 3226 opp-160000000 { 3227 opp-hz = /bits/ 64 <160000000>; 3228 required-opps = <&rpmhpd_opp_low_svs>; 3229 }; 3230 3231 opp-270000000 { 3232 opp-hz = /bits/ 64 <270000000>; 3233 required-opps = <&rpmhpd_opp_svs>; 3234 }; 3235 3236 opp-540000000 { 3237 opp-hz = /bits/ 64 <540000000>; 3238 required-opps = <&rpmhpd_opp_svs_l1>; 3239 }; 3240 3241 opp-810000000 { 3242 opp-hz = /bits/ 64 <810000000>; 3243 required-opps = <&rpmhpd_opp_nom>; 3244 }; 3245 }; 3246 }; 3247 }; 3248 3249 edp_phy: phy@aec2a00 { 3250 compatible = "qcom,sc8180x-edp-phy"; 3251 reg = <0 0x0aec2a00 0 0x1c0>, 3252 <0 0x0aec2200 0 0xa0>, 3253 <0 0x0aec2600 0 0xa0>, 3254 <0 0x0aec2000 0 0x19c>; 3255 3256 clocks = <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3257 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3258 clock-names = "aux", "cfg_ahb"; 3259 3260 power-domains = <&rpmhpd SC8180X_MX>; 3261 3262 #clock-cells = <1>; 3263 #phy-cells = <0>; 3264 }; 3265 3266 dispcc: clock-controller@af00000 { 3267 compatible = "qcom,sc8180x-dispcc"; 3268 reg = <0 0x0af00000 0 0x20000>; 3269 clocks = <&rpmhcc RPMH_CXO_CLK>, 3270 <&sleep_clk>, 3271 <&usb_prim_dpphy 0>, 3272 <&usb_prim_dpphy 1>, 3273 <&usb_sec_dpphy 0>, 3274 <&usb_sec_dpphy 1>, 3275 <&edp_phy 0>, 3276 <&edp_phy 1>; 3277 clock-names = "bi_tcxo", 3278 "sleep_clk", 3279 "dp_phy_pll_link_clk", 3280 "dp_phy_pll_vco_div_clk", 3281 "dptx1_phy_pll_link_clk", 3282 "dptx1_phy_pll_vco_div_clk", 3283 "edp_phy_pll_link_clk", 3284 "edp_phy_pll_vco_div_clk"; 3285 power-domains = <&rpmhpd SC8180X_MMCX>; 3286 required-opps = <&rpmhpd_opp_low_svs>; 3287 #clock-cells = <1>; 3288 #reset-cells = <1>; 3289 #power-domain-cells = <1>; 3290 }; 3291 3292 pdc: interrupt-controller@b220000 { 3293 compatible = "qcom,sc8180x-pdc", "qcom,pdc"; 3294 reg = <0 0x0b220000 0 0x30000>; 3295 qcom,pdc-ranges = <0 480 94>, <94 609 31>; 3296 #interrupt-cells = <2>; 3297 interrupt-parent = <&intc>; 3298 interrupt-controller; 3299 }; 3300 3301 tsens0: thermal-sensor@c263000 { 3302 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2"; 3303 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3304 <0 0x0c222000 0 0x1ff>; /* SROT */ 3305 #qcom,sensors = <16>; 3306 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3307 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3308 interrupt-names = "uplow", "critical"; 3309 #thermal-sensor-cells = <1>; 3310 }; 3311 3312 tsens1: thermal-sensor@c265000 { 3313 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2"; 3314 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3315 <0 0x0c223000 0 0x1ff>; /* SROT */ 3316 #qcom,sensors = <9>; 3317 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3318 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3319 interrupt-names = "uplow", "critical"; 3320 #thermal-sensor-cells = <1>; 3321 }; 3322 3323 aoss_qmp: power-controller@c300000 { 3324 compatible = "qcom,sc8180x-aoss-qmp", "qcom,aoss-qmp"; 3325 reg = <0x0 0x0c300000 0x0 0x400>; 3326 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3327 mboxes = <&apss_shared 0>; 3328 3329 #clock-cells = <0>; 3330 #power-domain-cells = <1>; 3331 }; 3332 3333 sram@c3f0000 { 3334 compatible = "qcom,rpmh-stats"; 3335 reg = <0x0 0x0c3f0000 0x0 0x400>; 3336 }; 3337 3338 spmi_bus: spmi@c440000 { 3339 compatible = "qcom,spmi-pmic-arb"; 3340 reg = <0x0 0x0c440000 0x0 0x0001100>, 3341 <0x0 0x0c600000 0x0 0x2000000>, 3342 <0x0 0x0e600000 0x0 0x0100000>, 3343 <0x0 0x0e700000 0x0 0x00a0000>, 3344 <0x0 0x0c40a000 0x0 0x0026000>; 3345 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3346 interrupt-names = "periph_irq"; 3347 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3348 qcom,ee = <0>; 3349 qcom,channel = <0>; 3350 #address-cells = <2>; 3351 #size-cells = <0>; 3352 interrupt-controller; 3353 #interrupt-cells = <4>; 3354 }; 3355 3356 apps_smmu: iommu@15000000 { 3357 compatible = "qcom,sc8180x-smmu-500", "arm,mmu-500"; 3358 reg = <0 0x15000000 0 0x100000>; 3359 #iommu-cells = <2>; 3360 #global-interrupts = <1>; 3361 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3362 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3363 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3364 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3365 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3366 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3367 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3368 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3369 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3370 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3371 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3372 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3373 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3374 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3375 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3376 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3377 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3378 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3379 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3380 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3381 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3382 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3383 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3384 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3385 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3386 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3387 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3388 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3389 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3390 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3391 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3392 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3393 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3394 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3395 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3396 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3397 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3398 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3399 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3400 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3401 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3402 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3403 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3404 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3405 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3406 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3407 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3408 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3409 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3410 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3411 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3412 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3413 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3414 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3415 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3416 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3417 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3418 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3419 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3420 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3421 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3422 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3423 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3424 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3425 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3426 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3427 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3428 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3429 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3430 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3431 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3432 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3433 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3434 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3435 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3436 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3437 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3438 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3439 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3440 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3441 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3442 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3443 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3444 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3445 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 3446 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 3447 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 3448 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 3449 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 3450 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 3451 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 3452 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 3453 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 3454 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 3455 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 3456 <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>, 3457 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>, 3458 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 3459 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>, 3460 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, 3461 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 3462 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, 3463 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>, 3464 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 3465 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 3466 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 3467 <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>; 3468 3469 }; 3470 3471 remoteproc_adsp: remoteproc@17300000 { 3472 compatible = "qcom,sc8180x-adsp-pas"; 3473 reg = <0x0 0x17300000 0x0 0x4040>; 3474 3475 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 3476 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3477 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3478 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3479 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3480 interrupt-names = "wdog", "fatal", "ready", 3481 "handover", "stop-ack"; 3482 3483 clocks = <&rpmhcc RPMH_CXO_CLK>; 3484 clock-names = "xo"; 3485 3486 power-domains = <&rpmhpd SC8180X_CX>; 3487 power-domain-names = "cx"; 3488 3489 qcom,qmp = <&aoss_qmp>; 3490 3491 qcom,smem-states = <&adsp_smp2p_out 0>; 3492 qcom,smem-state-names = "stop"; 3493 3494 status = "disabled"; 3495 3496 remoteproc_adsp_glink: glink-edge { 3497 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3498 label = "lpass"; 3499 qcom,remote-pid = <2>; 3500 mboxes = <&apss_shared 8>; 3501 }; 3502 }; 3503 3504 intc: interrupt-controller@17a00000 { 3505 compatible = "arm,gic-v3"; 3506 interrupt-controller; 3507 #interrupt-cells = <3>; 3508 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3509 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3510 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3511 #redistributor-regions = <1>; 3512 redistributor-stride = <0 0x20000>; 3513 }; 3514 3515 apss_shared: mailbox@17c00000 { 3516 compatible = "qcom,sc8180x-apss-shared", "qcom,sdm845-apss-shared"; 3517 reg = <0x0 0x17c00000 0x0 0x1000>; 3518 #mbox-cells = <1>; 3519 }; 3520 3521 timer@17c20000 { 3522 compatible = "arm,armv7-timer-mem"; 3523 reg = <0x0 0x17c20000 0x0 0x1000>; 3524 3525 #address-cells = <1>; 3526 #size-cells = <1>; 3527 ranges = <0 0 0 0x20000000>; 3528 3529 frame@17c21000 { 3530 reg = <0x17c21000 0x1000>, 3531 <0x17c22000 0x1000>; 3532 frame-number = <0>; 3533 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3534 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3535 }; 3536 3537 frame@17c23000 { 3538 reg = <0x17c23000 0x1000>; 3539 frame-number = <1>; 3540 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3541 status = "disabled"; 3542 }; 3543 3544 frame@17c25000 { 3545 reg = <0x17c25000 0x1000>; 3546 frame-number = <2>; 3547 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3548 status = "disabled"; 3549 }; 3550 3551 frame@17c27000 { 3552 reg = <0x17c26000 0x1000>; 3553 frame-number = <3>; 3554 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3555 status = "disabled"; 3556 }; 3557 3558 frame@17c29000 { 3559 reg = <0x17c29000 0x1000>; 3560 frame-number = <4>; 3561 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3562 status = "disabled"; 3563 }; 3564 3565 frame@17c2b000 { 3566 reg = <0x17c2b000 0x1000>; 3567 frame-number = <5>; 3568 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3569 status = "disabled"; 3570 }; 3571 3572 frame@17c2d000 { 3573 reg = <0x17c2d000 0x1000>; 3574 frame-number = <6>; 3575 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3576 status = "disabled"; 3577 }; 3578 }; 3579 3580 apps_rsc: rsc@18200000 { 3581 compatible = "qcom,rpmh-rsc"; 3582 reg = <0x0 0x18200000 0x0 0x10000>, 3583 <0x0 0x18210000 0x0 0x10000>, 3584 <0x0 0x18220000 0x0 0x10000>; 3585 reg-names = "drv-0", "drv-1", "drv-2"; 3586 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3587 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3588 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3589 qcom,tcs-offset = <0xd00>; 3590 qcom,drv-id = <2>; 3591 qcom,tcs-config = <ACTIVE_TCS 2>, 3592 <SLEEP_TCS 1>, 3593 <WAKE_TCS 1>, 3594 <CONTROL_TCS 0>; 3595 label = "apps_rsc"; 3596 power-domains = <&CLUSTER_PD>; 3597 3598 apps_bcm_voter: bcm-voter { 3599 compatible = "qcom,bcm-voter"; 3600 }; 3601 3602 rpmhcc: clock-controller { 3603 compatible = "qcom,sc8180x-rpmh-clk"; 3604 #clock-cells = <1>; 3605 clock-names = "xo"; 3606 clocks = <&xo_board_clk>; 3607 }; 3608 3609 rpmhpd: power-controller { 3610 compatible = "qcom,sc8180x-rpmhpd"; 3611 #power-domain-cells = <1>; 3612 operating-points-v2 = <&rpmhpd_opp_table>; 3613 3614 rpmhpd_opp_table: opp-table { 3615 compatible = "operating-points-v2"; 3616 3617 rpmhpd_opp_ret: opp1 { 3618 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3619 }; 3620 3621 rpmhpd_opp_min_svs: opp2 { 3622 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3623 }; 3624 3625 rpmhpd_opp_low_svs: opp3 { 3626 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3627 }; 3628 3629 rpmhpd_opp_svs: opp4 { 3630 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3631 }; 3632 3633 rpmhpd_opp_svs_l1: opp5 { 3634 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3635 }; 3636 3637 rpmhpd_opp_nom: opp6 { 3638 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3639 }; 3640 3641 rpmhpd_opp_nom_l1: opp7 { 3642 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3643 }; 3644 3645 rpmhpd_opp_nom_l2: opp8 { 3646 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3647 }; 3648 3649 rpmhpd_opp_turbo: opp9 { 3650 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3651 }; 3652 3653 rpmhpd_opp_turbo_l1: opp10 { 3654 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3655 }; 3656 }; 3657 }; 3658 }; 3659 3660 osm_l3: interconnect@18321000 { 3661 compatible = "qcom,sc8180x-osm-l3", "qcom,osm-l3"; 3662 reg = <0 0x18321000 0 0x1400>; 3663 3664 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3665 clock-names = "xo", "alternate"; 3666 3667 #interconnect-cells = <1>; 3668 }; 3669 3670 lmh@18350800 { 3671 compatible = "qcom,sc8180x-lmh"; 3672 reg = <0 0x18350800 0 0x400>; 3673 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3674 cpus = <&CPU4>; 3675 qcom,lmh-temp-arm-millicelsius = <65000>; 3676 qcom,lmh-temp-low-millicelsius = <94500>; 3677 qcom,lmh-temp-high-millicelsius = <95000>; 3678 interrupt-controller; 3679 #interrupt-cells = <1>; 3680 }; 3681 3682 lmh@18358800 { 3683 compatible = "qcom,sc8180x-lmh"; 3684 reg = <0 0x18358800 0 0x400>; 3685 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3686 cpus = <&CPU0>; 3687 qcom,lmh-temp-arm-millicelsius = <65000>; 3688 qcom,lmh-temp-low-millicelsius = <94500>; 3689 qcom,lmh-temp-high-millicelsius = <95000>; 3690 interrupt-controller; 3691 #interrupt-cells = <1>; 3692 }; 3693 3694 cpufreq_hw: cpufreq@18323000 { 3695 compatible = "qcom,cpufreq-hw"; 3696 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 3697 reg-names = "freq-domain0", "freq-domain1"; 3698 3699 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3700 clock-names = "xo", "alternate"; 3701 3702 #freq-domain-cells = <1>; 3703 #clock-cells = <1>; 3704 }; 3705 3706 wifi: wifi@18800000 { 3707 compatible = "qcom,wcn3990-wifi"; 3708 reg = <0 0x18800000 0 0x800000>; 3709 reg-names = "membase"; 3710 clock-names = "cxo_ref_clk_pin"; 3711 clocks = <&rpmhcc RPMH_RF_CLK2>; 3712 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 3713 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 3714 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 3715 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 3716 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3717 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3718 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 3719 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3720 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3721 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3722 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3723 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 3724 iommus = <&apps_smmu 0x0640 0x1>; 3725 qcom,msa-fixed-perm; 3726 status = "disabled"; 3727 }; 3728 }; 3729 3730 thermal-zones { 3731 cpu0-thermal { 3732 polling-delay-passive = <250>; 3733 polling-delay = <1000>; 3734 3735 thermal-sensors = <&tsens0 1>; 3736 3737 trips { 3738 cpu-crit { 3739 temperature = <110000>; 3740 hysteresis = <1000>; 3741 type = "critical"; 3742 }; 3743 }; 3744 }; 3745 3746 cpu1-thermal { 3747 polling-delay-passive = <250>; 3748 polling-delay = <1000>; 3749 3750 thermal-sensors = <&tsens0 2>; 3751 3752 trips { 3753 cpu-crit { 3754 temperature = <110000>; 3755 hysteresis = <1000>; 3756 type = "critical"; 3757 }; 3758 }; 3759 }; 3760 3761 cpu2-thermal { 3762 polling-delay-passive = <250>; 3763 polling-delay = <1000>; 3764 3765 thermal-sensors = <&tsens0 3>; 3766 3767 trips { 3768 cpu-crit { 3769 temperature = <110000>; 3770 hysteresis = <1000>; 3771 type = "critical"; 3772 }; 3773 }; 3774 }; 3775 3776 cpu3-thermal { 3777 polling-delay-passive = <250>; 3778 polling-delay = <1000>; 3779 3780 thermal-sensors = <&tsens0 4>; 3781 3782 trips { 3783 cpu-crit { 3784 temperature = <110000>; 3785 hysteresis = <1000>; 3786 type = "critical"; 3787 }; 3788 }; 3789 }; 3790 3791 cpu4-top-thermal { 3792 polling-delay-passive = <250>; 3793 polling-delay = <1000>; 3794 3795 thermal-sensors = <&tsens0 7>; 3796 3797 trips { 3798 cpu-crit { 3799 temperature = <110000>; 3800 hysteresis = <1000>; 3801 type = "critical"; 3802 }; 3803 }; 3804 }; 3805 3806 cpu5-top-thermal { 3807 polling-delay-passive = <250>; 3808 polling-delay = <1000>; 3809 3810 thermal-sensors = <&tsens0 8>; 3811 3812 trips { 3813 cpu-crit { 3814 temperature = <110000>; 3815 hysteresis = <1000>; 3816 type = "critical"; 3817 }; 3818 }; 3819 }; 3820 3821 cpu6-top-thermal { 3822 polling-delay-passive = <250>; 3823 polling-delay = <1000>; 3824 3825 thermal-sensors = <&tsens0 9>; 3826 3827 trips { 3828 cpu-crit { 3829 temperature = <110000>; 3830 hysteresis = <1000>; 3831 type = "critical"; 3832 }; 3833 }; 3834 }; 3835 3836 cpu7-top-thermal { 3837 polling-delay-passive = <250>; 3838 polling-delay = <1000>; 3839 3840 thermal-sensors = <&tsens0 10>; 3841 3842 trips { 3843 cpu-crit { 3844 temperature = <110000>; 3845 hysteresis = <1000>; 3846 type = "critical"; 3847 }; 3848 }; 3849 }; 3850 3851 cpu4-bottom-thermal { 3852 polling-delay-passive = <250>; 3853 polling-delay = <1000>; 3854 3855 thermal-sensors = <&tsens0 11>; 3856 3857 trips { 3858 cpu-crit { 3859 temperature = <110000>; 3860 hysteresis = <1000>; 3861 type = "critical"; 3862 }; 3863 }; 3864 }; 3865 3866 cpu5-bottom-thermal { 3867 polling-delay-passive = <250>; 3868 polling-delay = <1000>; 3869 3870 thermal-sensors = <&tsens0 12>; 3871 3872 trips { 3873 cpu-crit { 3874 temperature = <110000>; 3875 hysteresis = <1000>; 3876 type = "critical"; 3877 }; 3878 }; 3879 }; 3880 3881 cpu6-bottom-thermal { 3882 polling-delay-passive = <250>; 3883 polling-delay = <1000>; 3884 3885 thermal-sensors = <&tsens0 13>; 3886 3887 trips { 3888 cpu-crit { 3889 temperature = <110000>; 3890 hysteresis = <1000>; 3891 type = "critical"; 3892 }; 3893 }; 3894 }; 3895 3896 cpu7-bottom-thermal { 3897 polling-delay-passive = <250>; 3898 polling-delay = <1000>; 3899 3900 thermal-sensors = <&tsens0 14>; 3901 3902 trips { 3903 cpu-crit { 3904 temperature = <110000>; 3905 hysteresis = <1000>; 3906 type = "critical"; 3907 }; 3908 }; 3909 }; 3910 3911 aoss0-thermal { 3912 polling-delay-passive = <250>; 3913 polling-delay = <1000>; 3914 3915 thermal-sensors = <&tsens0 0>; 3916 3917 trips { 3918 trip-point0 { 3919 temperature = <90000>; 3920 hysteresis = <2000>; 3921 type = "hot"; 3922 }; 3923 }; 3924 }; 3925 3926 cluster0-thermal { 3927 polling-delay-passive = <250>; 3928 polling-delay = <1000>; 3929 3930 thermal-sensors = <&tsens0 5>; 3931 3932 trips { 3933 cluster-crit { 3934 temperature = <110000>; 3935 hysteresis = <2000>; 3936 type = "critical"; 3937 }; 3938 }; 3939 }; 3940 3941 cluster1-thermal { 3942 polling-delay-passive = <250>; 3943 polling-delay = <1000>; 3944 3945 thermal-sensors = <&tsens0 6>; 3946 3947 trips { 3948 cluster-crit { 3949 temperature = <110000>; 3950 hysteresis = <2000>; 3951 type = "critical"; 3952 }; 3953 }; 3954 }; 3955 3956 gpu-top-thermal { 3957 polling-delay-passive = <250>; 3958 polling-delay = <1000>; 3959 3960 thermal-sensors = <&tsens0 15>; 3961 3962 cooling-maps { 3963 map0 { 3964 trip = <&gpu_top_alert0>; 3965 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3966 }; 3967 }; 3968 3969 trips { 3970 gpu_top_alert0: trip-point0 { 3971 temperature = <90000>; 3972 hysteresis = <2000>; 3973 type = "hot"; 3974 }; 3975 }; 3976 }; 3977 3978 aoss1-thermal { 3979 polling-delay-passive = <250>; 3980 polling-delay = <1000>; 3981 3982 thermal-sensors = <&tsens1 0>; 3983 3984 trips { 3985 trip-point0 { 3986 temperature = <90000>; 3987 hysteresis = <2000>; 3988 type = "hot"; 3989 }; 3990 }; 3991 }; 3992 3993 wlan-thermal { 3994 polling-delay-passive = <250>; 3995 polling-delay = <1000>; 3996 3997 thermal-sensors = <&tsens1 1>; 3998 3999 trips { 4000 trip-point0 { 4001 temperature = <90000>; 4002 hysteresis = <2000>; 4003 type = "hot"; 4004 }; 4005 }; 4006 }; 4007 4008 video-thermal { 4009 polling-delay-passive = <250>; 4010 polling-delay = <1000>; 4011 4012 thermal-sensors = <&tsens1 2>; 4013 4014 trips { 4015 trip-point0 { 4016 temperature = <90000>; 4017 hysteresis = <2000>; 4018 type = "hot"; 4019 }; 4020 }; 4021 }; 4022 4023 mem-thermal { 4024 polling-delay-passive = <250>; 4025 polling-delay = <1000>; 4026 4027 thermal-sensors = <&tsens1 3>; 4028 4029 trips { 4030 trip-point0 { 4031 temperature = <90000>; 4032 hysteresis = <2000>; 4033 type = "hot"; 4034 }; 4035 }; 4036 }; 4037 4038 q6-hvx-thermal { 4039 polling-delay-passive = <250>; 4040 polling-delay = <1000>; 4041 4042 thermal-sensors = <&tsens1 4>; 4043 4044 trips { 4045 trip-point0 { 4046 temperature = <90000>; 4047 hysteresis = <2000>; 4048 type = "hot"; 4049 }; 4050 }; 4051 }; 4052 4053 camera-thermal { 4054 polling-delay-passive = <250>; 4055 polling-delay = <1000>; 4056 4057 thermal-sensors = <&tsens1 5>; 4058 4059 trips { 4060 trip-point0 { 4061 temperature = <90000>; 4062 hysteresis = <2000>; 4063 type = "hot"; 4064 }; 4065 }; 4066 }; 4067 4068 compute-thermal { 4069 polling-delay-passive = <250>; 4070 polling-delay = <1000>; 4071 4072 thermal-sensors = <&tsens1 6>; 4073 4074 trips { 4075 trip-point0 { 4076 temperature = <90000>; 4077 hysteresis = <2000>; 4078 type = "hot"; 4079 }; 4080 }; 4081 }; 4082 4083 mdm-dsp-thermal { 4084 polling-delay-passive = <250>; 4085 polling-delay = <1000>; 4086 4087 thermal-sensors = <&tsens1 7>; 4088 4089 trips { 4090 trip-point0 { 4091 temperature = <90000>; 4092 hysteresis = <2000>; 4093 type = "hot"; 4094 }; 4095 }; 4096 }; 4097 4098 npu-thermal { 4099 polling-delay-passive = <250>; 4100 polling-delay = <1000>; 4101 4102 thermal-sensors = <&tsens1 8>; 4103 4104 trips { 4105 trip-point0 { 4106 temperature = <90000>; 4107 hysteresis = <2000>; 4108 type = "hot"; 4109 }; 4110 }; 4111 }; 4112 4113 gpu-bottom-thermal { 4114 polling-delay-passive = <250>; 4115 polling-delay = <1000>; 4116 4117 thermal-sensors = <&tsens1 11>; 4118 4119 cooling-maps { 4120 map0 { 4121 trip = <&gpu_bottom_alert0>; 4122 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4123 }; 4124 }; 4125 4126 trips { 4127 gpu_bottom_alert0: trip-point0 { 4128 temperature = <90000>; 4129 hysteresis = <2000>; 4130 type = "hot"; 4131 }; 4132 }; 4133 }; 4134 }; 4135 4136 timer { 4137 compatible = "arm,armv8-timer"; 4138 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4139 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4140 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4141 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4142 }; 4143}; 4144