1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2020-2023, Linaro Limited 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,gcc-sc8180x.h> 9#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/interconnect/qcom,icc.h> 12#include <dt-bindings/interconnect/qcom,osm-l3.h> 13#include <dt-bindings/interconnect/qcom,sc8180x.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/power/qcom-rpmpd.h> 16#include <dt-bindings/soc/qcom,rpmh-rsc.h> 17#include <dt-bindings/thermal/thermal.h> 18 19/ { 20 interrupt-parent = <&intc>; 21 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 clocks { 26 xo_board_clk: xo-board { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 clock-frequency = <38400000>; 30 }; 31 32 sleep_clk: sleep-clk { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <32764>; 36 clock-output-names = "sleep_clk"; 37 }; 38 }; 39 40 cpus { 41 #address-cells = <2>; 42 #size-cells = <0>; 43 44 CPU0: cpu@0 { 45 device_type = "cpu"; 46 compatible = "qcom,kryo485"; 47 reg = <0x0 0x0>; 48 enable-method = "psci"; 49 capacity-dmips-mhz = <602>; 50 next-level-cache = <&L2_0>; 51 qcom,freq-domain = <&cpufreq_hw 0>; 52 operating-points-v2 = <&cpu0_opp_table>; 53 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 54 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 55 power-domains = <&CPU_PD0>; 56 power-domain-names = "psci"; 57 #cooling-cells = <2>; 58 clocks = <&cpufreq_hw 0>; 59 60 L2_0: l2-cache { 61 compatible = "cache"; 62 cache-level = <2>; 63 cache-unified; 64 next-level-cache = <&L3_0>; 65 L3_0: l3-cache { 66 compatible = "cache"; 67 cache-level = <3>; 68 cache-unified; 69 }; 70 }; 71 }; 72 73 CPU1: cpu@100 { 74 device_type = "cpu"; 75 compatible = "qcom,kryo485"; 76 reg = <0x0 0x100>; 77 enable-method = "psci"; 78 capacity-dmips-mhz = <602>; 79 next-level-cache = <&L2_100>; 80 qcom,freq-domain = <&cpufreq_hw 0>; 81 operating-points-v2 = <&cpu0_opp_table>; 82 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 83 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 84 power-domains = <&CPU_PD1>; 85 power-domain-names = "psci"; 86 #cooling-cells = <2>; 87 clocks = <&cpufreq_hw 0>; 88 89 L2_100: l2-cache { 90 compatible = "cache"; 91 cache-level = <2>; 92 cache-unified; 93 next-level-cache = <&L3_0>; 94 }; 95 96 }; 97 98 CPU2: cpu@200 { 99 device_type = "cpu"; 100 compatible = "qcom,kryo485"; 101 reg = <0x0 0x200>; 102 enable-method = "psci"; 103 capacity-dmips-mhz = <602>; 104 next-level-cache = <&L2_200>; 105 qcom,freq-domain = <&cpufreq_hw 0>; 106 operating-points-v2 = <&cpu0_opp_table>; 107 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 108 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 109 power-domains = <&CPU_PD2>; 110 power-domain-names = "psci"; 111 #cooling-cells = <2>; 112 clocks = <&cpufreq_hw 0>; 113 114 L2_200: l2-cache { 115 compatible = "cache"; 116 cache-level = <2>; 117 cache-unified; 118 next-level-cache = <&L3_0>; 119 }; 120 }; 121 122 CPU3: cpu@300 { 123 device_type = "cpu"; 124 compatible = "qcom,kryo485"; 125 reg = <0x0 0x300>; 126 enable-method = "psci"; 127 capacity-dmips-mhz = <602>; 128 next-level-cache = <&L2_300>; 129 qcom,freq-domain = <&cpufreq_hw 0>; 130 operating-points-v2 = <&cpu0_opp_table>; 131 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 132 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 133 power-domains = <&CPU_PD3>; 134 power-domain-names = "psci"; 135 #cooling-cells = <2>; 136 clocks = <&cpufreq_hw 0>; 137 138 L2_300: l2-cache { 139 compatible = "cache"; 140 cache-unified; 141 cache-level = <2>; 142 next-level-cache = <&L3_0>; 143 }; 144 }; 145 146 CPU4: cpu@400 { 147 device_type = "cpu"; 148 compatible = "qcom,kryo485"; 149 reg = <0x0 0x400>; 150 enable-method = "psci"; 151 capacity-dmips-mhz = <1024>; 152 next-level-cache = <&L2_400>; 153 qcom,freq-domain = <&cpufreq_hw 1>; 154 operating-points-v2 = <&cpu4_opp_table>; 155 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 156 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 157 power-domains = <&CPU_PD4>; 158 power-domain-names = "psci"; 159 #cooling-cells = <2>; 160 clocks = <&cpufreq_hw 1>; 161 162 L2_400: l2-cache { 163 compatible = "cache"; 164 cache-unified; 165 cache-level = <2>; 166 next-level-cache = <&L3_0>; 167 }; 168 }; 169 170 CPU5: cpu@500 { 171 device_type = "cpu"; 172 compatible = "qcom,kryo485"; 173 reg = <0x0 0x500>; 174 enable-method = "psci"; 175 capacity-dmips-mhz = <1024>; 176 next-level-cache = <&L2_500>; 177 qcom,freq-domain = <&cpufreq_hw 1>; 178 operating-points-v2 = <&cpu4_opp_table>; 179 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 180 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 181 power-domains = <&CPU_PD5>; 182 power-domain-names = "psci"; 183 #cooling-cells = <2>; 184 clocks = <&cpufreq_hw 1>; 185 186 L2_500: l2-cache { 187 compatible = "cache"; 188 cache-unified; 189 cache-level = <2>; 190 next-level-cache = <&L3_0>; 191 }; 192 }; 193 194 CPU6: cpu@600 { 195 device_type = "cpu"; 196 compatible = "qcom,kryo485"; 197 reg = <0x0 0x600>; 198 enable-method = "psci"; 199 capacity-dmips-mhz = <1024>; 200 next-level-cache = <&L2_600>; 201 qcom,freq-domain = <&cpufreq_hw 1>; 202 operating-points-v2 = <&cpu4_opp_table>; 203 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 204 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 205 power-domains = <&CPU_PD6>; 206 power-domain-names = "psci"; 207 #cooling-cells = <2>; 208 clocks = <&cpufreq_hw 1>; 209 210 L2_600: l2-cache { 211 compatible = "cache"; 212 cache-unified; 213 cache-level = <2>; 214 next-level-cache = <&L3_0>; 215 }; 216 }; 217 218 CPU7: cpu@700 { 219 device_type = "cpu"; 220 compatible = "qcom,kryo485"; 221 reg = <0x0 0x700>; 222 enable-method = "psci"; 223 capacity-dmips-mhz = <1024>; 224 next-level-cache = <&L2_700>; 225 qcom,freq-domain = <&cpufreq_hw 1>; 226 operating-points-v2 = <&cpu4_opp_table>; 227 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 228 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 229 power-domains = <&CPU_PD7>; 230 power-domain-names = "psci"; 231 #cooling-cells = <2>; 232 clocks = <&cpufreq_hw 1>; 233 234 L2_700: l2-cache { 235 compatible = "cache"; 236 cache-unified; 237 cache-level = <2>; 238 next-level-cache = <&L3_0>; 239 }; 240 }; 241 242 cpu-map { 243 cluster0 { 244 core0 { 245 cpu = <&CPU0>; 246 }; 247 248 core1 { 249 cpu = <&CPU1>; 250 }; 251 252 core2 { 253 cpu = <&CPU2>; 254 }; 255 256 core3 { 257 cpu = <&CPU3>; 258 }; 259 260 core4 { 261 cpu = <&CPU4>; 262 }; 263 264 core5 { 265 cpu = <&CPU5>; 266 }; 267 268 core6 { 269 cpu = <&CPU6>; 270 }; 271 272 core7 { 273 cpu = <&CPU7>; 274 }; 275 }; 276 }; 277 278 idle-states { 279 entry-method = "psci"; 280 281 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 282 compatible = "arm,idle-state"; 283 arm,psci-suspend-param = <0x40000004>; 284 entry-latency-us = <355>; 285 exit-latency-us = <909>; 286 min-residency-us = <3934>; 287 local-timer-stop; 288 }; 289 290 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 291 compatible = "arm,idle-state"; 292 arm,psci-suspend-param = <0x40000004>; 293 entry-latency-us = <2411>; 294 exit-latency-us = <1461>; 295 min-residency-us = <4488>; 296 local-timer-stop; 297 }; 298 }; 299 300 domain-idle-states { 301 CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { 302 compatible = "domain-idle-state"; 303 arm,psci-suspend-param = <0x41000044>; 304 entry-latency-us = <3300>; 305 exit-latency-us = <3300>; 306 min-residency-us = <6000>; 307 }; 308 309 CLUSTER_SLEEP_AOSS_SLEEP: cluster-sleep-1 { 310 compatible = "domain-idle-state"; 311 arm,psci-suspend-param = <0x4100a344>; 312 entry-latency-us = <3263>; 313 exit-latency-us = <6562>; 314 min-residency-us = <9987>; 315 }; 316 }; 317 }; 318 319 cpu0_opp_table: opp-table-cpu0 { 320 compatible = "operating-points-v2"; 321 opp-shared; 322 323 opp-300000000 { 324 opp-hz = /bits/ 64 <300000000>; 325 opp-peak-kBps = <800000 9600000>; 326 }; 327 328 opp-422400000 { 329 opp-hz = /bits/ 64 <422400000>; 330 opp-peak-kBps = <800000 9600000>; 331 }; 332 333 opp-537600000 { 334 opp-hz = /bits/ 64 <537600000>; 335 opp-peak-kBps = <800000 12902400>; 336 }; 337 338 opp-652800000 { 339 opp-hz = /bits/ 64 <652800000>; 340 opp-peak-kBps = <800000 12902400>; 341 }; 342 343 opp-768000000 { 344 opp-hz = /bits/ 64 <768000000>; 345 opp-peak-kBps = <800000 15974400>; 346 }; 347 348 opp-883200000 { 349 opp-hz = /bits/ 64 <883200000>; 350 opp-peak-kBps = <1804000 19660800>; 351 }; 352 353 opp-998400000 { 354 opp-hz = /bits/ 64 <998400000>; 355 opp-peak-kBps = <1804000 19660800>; 356 }; 357 358 opp-1113600000 { 359 opp-hz = /bits/ 64 <1113600000>; 360 opp-peak-kBps = <1804000 22732800>; 361 }; 362 363 opp-1228800000 { 364 opp-hz = /bits/ 64 <1228800000>; 365 opp-peak-kBps = <1804000 22732800>; 366 }; 367 368 opp-1363200000 { 369 opp-hz = /bits/ 64 <1363200000>; 370 opp-peak-kBps = <2188000 25804800>; 371 }; 372 373 opp-1478400000 { 374 opp-hz = /bits/ 64 <1478400000>; 375 opp-peak-kBps = <2188000 31948800>; 376 }; 377 378 opp-1574400000 { 379 opp-hz = /bits/ 64 <1574400000>; 380 opp-peak-kBps = <3072000 31948800>; 381 }; 382 383 opp-1670400000 { 384 opp-hz = /bits/ 64 <1670400000>; 385 opp-peak-kBps = <3072000 31948800>; 386 }; 387 388 opp-1766400000 { 389 opp-hz = /bits/ 64 <1766400000>; 390 opp-peak-kBps = <3072000 31948800>; 391 }; 392 }; 393 394 cpu4_opp_table: opp-table-cpu4 { 395 compatible = "operating-points-v2"; 396 opp-shared; 397 398 opp-825600000 { 399 opp-hz = /bits/ 64 <825600000>; 400 opp-peak-kBps = <1804000 15974400>; 401 }; 402 403 opp-940800000 { 404 opp-hz = /bits/ 64 <940800000>; 405 opp-peak-kBps = <2188000 19660800>; 406 }; 407 408 opp-1056000000 { 409 opp-hz = /bits/ 64 <1056000000>; 410 opp-peak-kBps = <2188000 22732800>; 411 }; 412 413 opp-1171200000 { 414 opp-hz = /bits/ 64 <1171200000>; 415 opp-peak-kBps = <3072000 25804800>; 416 }; 417 418 opp-1286400000 { 419 opp-hz = /bits/ 64 <1286400000>; 420 opp-peak-kBps = <3072000 31948800>; 421 }; 422 423 opp-1420800000 { 424 opp-hz = /bits/ 64 <1420800000>; 425 opp-peak-kBps = <4068000 31948800>; 426 }; 427 428 opp-1536000000 { 429 opp-hz = /bits/ 64 <1536000000>; 430 opp-peak-kBps = <4068000 31948800>; 431 }; 432 433 opp-1651200000 { 434 opp-hz = /bits/ 64 <1651200000>; 435 opp-peak-kBps = <4068000 40550400>; 436 }; 437 438 opp-1766400000 { 439 opp-hz = /bits/ 64 <1766400000>; 440 opp-peak-kBps = <4068000 40550400>; 441 }; 442 443 opp-1881600000 { 444 opp-hz = /bits/ 64 <1881600000>; 445 opp-peak-kBps = <4068000 43008000>; 446 }; 447 448 opp-1996800000 { 449 opp-hz = /bits/ 64 <1996800000>; 450 opp-peak-kBps = <6220000 43008000>; 451 }; 452 453 opp-2131200000 { 454 opp-hz = /bits/ 64 <2131200000>; 455 opp-peak-kBps = <6220000 49152000>; 456 }; 457 458 opp-2246400000 { 459 opp-hz = /bits/ 64 <2246400000>; 460 opp-peak-kBps = <7216000 49152000>; 461 }; 462 463 opp-2361600000 { 464 opp-hz = /bits/ 64 <2361600000>; 465 opp-peak-kBps = <8368000 49152000>; 466 }; 467 468 opp-2457600000 { 469 opp-hz = /bits/ 64 <2457600000>; 470 opp-peak-kBps = <8368000 51609600>; 471 }; 472 473 opp-2553600000 { 474 opp-hz = /bits/ 64 <2553600000>; 475 opp-peak-kBps = <8368000 51609600>; 476 }; 477 478 opp-2649600000 { 479 opp-hz = /bits/ 64 <2649600000>; 480 opp-peak-kBps = <8368000 51609600>; 481 }; 482 483 opp-2745600000 { 484 opp-hz = /bits/ 64 <2745600000>; 485 opp-peak-kBps = <8368000 51609600>; 486 }; 487 488 opp-2841600000 { 489 opp-hz = /bits/ 64 <2841600000>; 490 opp-peak-kBps = <8368000 51609600>; 491 }; 492 493 opp-2918400000 { 494 opp-hz = /bits/ 64 <2918400000>; 495 opp-peak-kBps = <8368000 51609600>; 496 }; 497 498 opp-2995200000 { 499 opp-hz = /bits/ 64 <2995200000>; 500 opp-peak-kBps = <8368000 51609600>; 501 }; 502 }; 503 504 firmware { 505 scm: scm { 506 compatible = "qcom,scm-sc8180x", "qcom,scm"; 507 }; 508 }; 509 510 camnoc_virt: interconnect-camnoc-virt { 511 compatible = "qcom,sc8180x-camnoc-virt"; 512 #interconnect-cells = <2>; 513 qcom,bcm-voters = <&apps_bcm_voter>; 514 }; 515 516 mc_virt: interconnect-mc-virt { 517 compatible = "qcom,sc8180x-mc-virt"; 518 #interconnect-cells = <2>; 519 qcom,bcm-voters = <&apps_bcm_voter>; 520 }; 521 522 qup_virt: interconnect-qup-virt { 523 compatible = "qcom,sc8180x-qup-virt"; 524 #interconnect-cells = <2>; 525 qcom,bcm-voters = <&apps_bcm_voter>; 526 }; 527 528 memory@80000000 { 529 device_type = "memory"; 530 /* We expect the bootloader to fill in the size */ 531 reg = <0x0 0x80000000 0x0 0x0>; 532 }; 533 534 pmu { 535 compatible = "arm,armv8-pmuv3"; 536 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 537 }; 538 539 psci { 540 compatible = "arm,psci-1.0"; 541 method = "smc"; 542 543 CPU_PD0: power-domain-cpu0 { 544 #power-domain-cells = <0>; 545 power-domains = <&CLUSTER_PD>; 546 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 547 }; 548 549 CPU_PD1: power-domain-cpu1 { 550 #power-domain-cells = <0>; 551 power-domains = <&CLUSTER_PD>; 552 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 553 }; 554 555 CPU_PD2: power-domain-cpu2 { 556 #power-domain-cells = <0>; 557 power-domains = <&CLUSTER_PD>; 558 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 559 }; 560 561 CPU_PD3: power-domain-cpu3 { 562 #power-domain-cells = <0>; 563 power-domains = <&CLUSTER_PD>; 564 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 565 }; 566 567 CPU_PD4: power-domain-cpu4 { 568 #power-domain-cells = <0>; 569 power-domains = <&CLUSTER_PD>; 570 domain-idle-states = <&BIG_CPU_SLEEP_0>; 571 }; 572 573 CPU_PD5: power-domain-cpu5 { 574 #power-domain-cells = <0>; 575 power-domains = <&CLUSTER_PD>; 576 domain-idle-states = <&BIG_CPU_SLEEP_0>; 577 }; 578 579 CPU_PD6: power-domain-cpu6 { 580 #power-domain-cells = <0>; 581 power-domains = <&CLUSTER_PD>; 582 domain-idle-states = <&BIG_CPU_SLEEP_0>; 583 }; 584 585 CPU_PD7: power-domain-cpu7 { 586 #power-domain-cells = <0>; 587 power-domains = <&CLUSTER_PD>; 588 domain-idle-states = <&BIG_CPU_SLEEP_0>; 589 }; 590 591 CLUSTER_PD: power-domain-cpu-cluster0 { 592 #power-domain-cells = <0>; 593 domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_AOSS_SLEEP>; 594 }; 595 }; 596 597 reserved-memory { 598 #address-cells = <2>; 599 #size-cells = <2>; 600 ranges; 601 602 hyp_mem: hyp@85700000 { 603 reg = <0x0 0x85700000 0x0 0x600000>; 604 no-map; 605 }; 606 607 xbl_mem: xbl@85d00000 { 608 reg = <0x0 0x85d00000 0x0 0x140000>; 609 no-map; 610 }; 611 612 aop_mem: aop@85f00000 { 613 reg = <0x0 0x85f00000 0x0 0x20000>; 614 no-map; 615 }; 616 617 aop_cmd_db: cmd-db@85f20000 { 618 compatible = "qcom,cmd-db"; 619 reg = <0x0 0x85f20000 0x0 0x20000>; 620 no-map; 621 }; 622 623 reserved@85f40000 { 624 reg = <0x0 0x85f40000 0x0 0x10000>; 625 no-map; 626 }; 627 628 smem_mem: smem@86000000 { 629 compatible = "qcom,smem"; 630 reg = <0x0 0x86000000 0x0 0x200000>; 631 no-map; 632 hwlocks = <&tcsr_mutex 3>; 633 }; 634 635 reserved@86200000 { 636 reg = <0x0 0x86200000 0x0 0x3900000>; 637 no-map; 638 }; 639 640 reserved@89b00000 { 641 reg = <0x0 0x89b00000 0x0 0x1c00000>; 642 no-map; 643 }; 644 645 reserved@9d400000 { 646 reg = <0x0 0x9d400000 0x0 0x1000000>; 647 no-map; 648 }; 649 650 reserved@9e400000 { 651 reg = <0x0 0x9e400000 0x0 0x1400000>; 652 no-map; 653 }; 654 655 reserved@9f800000 { 656 reg = <0x0 0x9f800000 0x0 0x800000>; 657 no-map; 658 }; 659 }; 660 661 smp2p-cdsp { 662 compatible = "qcom,smp2p"; 663 qcom,smem = <94>, <432>; 664 665 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 666 667 mboxes = <&apss_shared 6>; 668 669 qcom,local-pid = <0>; 670 qcom,remote-pid = <5>; 671 672 cdsp_smp2p_out: master-kernel { 673 qcom,entry-name = "master-kernel"; 674 #qcom,smem-state-cells = <1>; 675 }; 676 677 cdsp_smp2p_in: slave-kernel { 678 qcom,entry-name = "slave-kernel"; 679 680 interrupt-controller; 681 #interrupt-cells = <2>; 682 }; 683 }; 684 685 smp2p-lpass { 686 compatible = "qcom,smp2p"; 687 qcom,smem = <443>, <429>; 688 689 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 690 691 mboxes = <&apss_shared 10>; 692 693 qcom,local-pid = <0>; 694 qcom,remote-pid = <2>; 695 696 adsp_smp2p_out: master-kernel { 697 qcom,entry-name = "master-kernel"; 698 #qcom,smem-state-cells = <1>; 699 }; 700 701 adsp_smp2p_in: slave-kernel { 702 qcom,entry-name = "slave-kernel"; 703 704 interrupt-controller; 705 #interrupt-cells = <2>; 706 }; 707 }; 708 709 smp2p-mpss { 710 compatible = "qcom,smp2p"; 711 qcom,smem = <435>, <428>; 712 713 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 714 715 mboxes = <&apss_shared 14>; 716 717 qcom,local-pid = <0>; 718 qcom,remote-pid = <1>; 719 720 modem_smp2p_out: master-kernel { 721 qcom,entry-name = "master-kernel"; 722 #qcom,smem-state-cells = <1>; 723 }; 724 725 modem_smp2p_in: slave-kernel { 726 qcom,entry-name = "slave-kernel"; 727 728 interrupt-controller; 729 #interrupt-cells = <2>; 730 }; 731 732 modem_smp2p_ipa_out: ipa-ap-to-modem { 733 qcom,entry-name = "ipa"; 734 #qcom,smem-state-cells = <1>; 735 }; 736 737 modem_smp2p_ipa_in: ipa-modem-to-ap { 738 qcom,entry-name = "ipa"; 739 interrupt-controller; 740 #interrupt-cells = <2>; 741 }; 742 743 modem_smp2p_wlan_in: wlan-wpss-to-ap { 744 qcom,entry-name = "wlan"; 745 interrupt-controller; 746 #interrupt-cells = <2>; 747 }; 748 }; 749 750 smp2p-slpi { 751 compatible = "qcom,smp2p"; 752 qcom,smem = <481>, <430>; 753 754 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 755 756 mboxes = <&apss_shared 26>; 757 758 qcom,local-pid = <0>; 759 qcom,remote-pid = <3>; 760 761 slpi_smp2p_out: master-kernel { 762 qcom,entry-name = "master-kernel"; 763 #qcom,smem-state-cells = <1>; 764 }; 765 766 slpi_smp2p_in: slave-kernel { 767 qcom,entry-name = "slave-kernel"; 768 769 interrupt-controller; 770 #interrupt-cells = <2>; 771 }; 772 }; 773 774 soc: soc@0 { 775 compatible = "simple-bus"; 776 #address-cells = <2>; 777 #size-cells = <2>; 778 ranges = <0 0 0 0 0x10 0>; 779 dma-ranges = <0 0 0 0 0x10 0>; 780 781 gcc: clock-controller@100000 { 782 compatible = "qcom,gcc-sc8180x"; 783 reg = <0x0 0x00100000 0x0 0x1f0000>; 784 #clock-cells = <1>; 785 #reset-cells = <1>; 786 #power-domain-cells = <1>; 787 clocks = <&rpmhcc RPMH_CXO_CLK>, 788 <&rpmhcc RPMH_CXO_CLK_A>, 789 <&sleep_clk>; 790 clock-names = "bi_tcxo", 791 "bi_tcxo_ao", 792 "sleep_clk"; 793 power-domains = <&rpmhpd SC8180X_CX>; 794 }; 795 796 qupv3_id_0: geniqup@8c0000 { 797 compatible = "qcom,geni-se-qup"; 798 reg = <0 0x008c0000 0 0x6000>; 799 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 800 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 801 clock-names = "m-ahb", "s-ahb"; 802 #address-cells = <2>; 803 #size-cells = <2>; 804 ranges; 805 iommus = <&apps_smmu 0x4c3 0>; 806 status = "disabled"; 807 808 i2c0: i2c@880000 { 809 compatible = "qcom,geni-i2c"; 810 reg = <0 0x00880000 0 0x4000>; 811 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 812 clock-names = "se"; 813 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 814 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 815 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 816 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 817 interconnect-names = "qup-core", "qup-config", "qup-memory"; 818 #address-cells = <1>; 819 #size-cells = <0>; 820 status = "disabled"; 821 }; 822 823 spi0: spi@880000 { 824 compatible = "qcom,geni-spi"; 825 reg = <0 0x00880000 0 0x4000>; 826 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 827 clock-names = "se"; 828 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 829 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 830 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 831 interconnect-names = "qup-core", "qup-config"; 832 #address-cells = <1>; 833 #size-cells = <0>; 834 status = "disabled"; 835 }; 836 837 uart0: serial@880000 { 838 compatible = "qcom,geni-uart"; 839 reg = <0 0x00880000 0 0x4000>; 840 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 841 clock-names = "se"; 842 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 843 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 844 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 845 interconnect-names = "qup-core", "qup-config"; 846 status = "disabled"; 847 }; 848 849 i2c1: i2c@884000 { 850 compatible = "qcom,geni-i2c"; 851 reg = <0 0x00884000 0 0x4000>; 852 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 853 clock-names = "se"; 854 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 855 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 856 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 857 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 858 interconnect-names = "qup-core", "qup-config", "qup-memory"; 859 #address-cells = <1>; 860 #size-cells = <0>; 861 status = "disabled"; 862 }; 863 864 spi1: spi@884000 { 865 compatible = "qcom,geni-spi"; 866 reg = <0 0x00884000 0 0x4000>; 867 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 868 clock-names = "se"; 869 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 870 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 871 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 872 interconnect-names = "qup-core", "qup-config"; 873 #address-cells = <1>; 874 #size-cells = <0>; 875 status = "disabled"; 876 }; 877 878 uart1: serial@884000 { 879 compatible = "qcom,geni-uart"; 880 reg = <0 0x00884000 0 0x4000>; 881 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 882 clock-names = "se"; 883 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 884 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 885 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 886 interconnect-names = "qup-core", "qup-config"; 887 status = "disabled"; 888 }; 889 890 i2c2: i2c@888000 { 891 compatible = "qcom,geni-i2c"; 892 reg = <0 0x00888000 0 0x4000>; 893 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 894 clock-names = "se"; 895 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 896 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 897 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 898 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 899 interconnect-names = "qup-core", "qup-config", "qup-memory"; 900 #address-cells = <1>; 901 #size-cells = <0>; 902 status = "disabled"; 903 }; 904 905 spi2: spi@888000 { 906 compatible = "qcom,geni-spi"; 907 reg = <0 0x00888000 0 0x4000>; 908 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 909 clock-names = "se"; 910 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 911 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 912 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 913 interconnect-names = "qup-core", "qup-config"; 914 #address-cells = <1>; 915 #size-cells = <0>; 916 status = "disabled"; 917 }; 918 919 uart2: serial@888000 { 920 compatible = "qcom,geni-uart"; 921 reg = <0 0x00888000 0 0x4000>; 922 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 923 clock-names = "se"; 924 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 925 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 926 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 927 interconnect-names = "qup-core", "qup-config"; 928 status = "disabled"; 929 }; 930 931 i2c3: i2c@88c000 { 932 compatible = "qcom,geni-i2c"; 933 reg = <0 0x0088c000 0 0x4000>; 934 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 935 clock-names = "se"; 936 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 937 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 938 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 939 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 940 interconnect-names = "qup-core", "qup-config", "qup-memory"; 941 #address-cells = <1>; 942 #size-cells = <0>; 943 status = "disabled"; 944 }; 945 946 spi3: spi@88c000 { 947 compatible = "qcom,geni-spi"; 948 reg = <0 0x0088c000 0 0x4000>; 949 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 950 clock-names = "se"; 951 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 952 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 953 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 954 interconnect-names = "qup-core", "qup-config"; 955 #address-cells = <1>; 956 #size-cells = <0>; 957 status = "disabled"; 958 }; 959 960 uart3: serial@88c000 { 961 compatible = "qcom,geni-uart"; 962 reg = <0 0x0088c000 0 0x4000>; 963 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 964 clock-names = "se"; 965 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 966 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 967 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 968 interconnect-names = "qup-core", "qup-config"; 969 status = "disabled"; 970 }; 971 972 i2c4: i2c@890000 { 973 compatible = "qcom,geni-i2c"; 974 reg = <0 0x00890000 0 0x4000>; 975 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 976 clock-names = "se"; 977 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 978 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 979 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 980 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 981 interconnect-names = "qup-core", "qup-config", "qup-memory"; 982 #address-cells = <1>; 983 #size-cells = <0>; 984 status = "disabled"; 985 }; 986 987 spi4: spi@890000 { 988 compatible = "qcom,geni-spi"; 989 reg = <0 0x00890000 0 0x4000>; 990 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 991 clock-names = "se"; 992 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 993 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 994 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 995 interconnect-names = "qup-core", "qup-config"; 996 #address-cells = <1>; 997 #size-cells = <0>; 998 status = "disabled"; 999 }; 1000 1001 uart4: serial@890000 { 1002 compatible = "qcom,geni-uart"; 1003 reg = <0 0x00890000 0 0x4000>; 1004 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1005 clock-names = "se"; 1006 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1007 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1008 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1009 interconnect-names = "qup-core", "qup-config"; 1010 status = "disabled"; 1011 }; 1012 1013 i2c5: i2c@894000 { 1014 compatible = "qcom,geni-i2c"; 1015 reg = <0 0x00894000 0 0x4000>; 1016 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1017 clock-names = "se"; 1018 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1019 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1020 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1021 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1022 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1023 #address-cells = <1>; 1024 #size-cells = <0>; 1025 status = "disabled"; 1026 }; 1027 1028 spi5: spi@894000 { 1029 compatible = "qcom,geni-spi"; 1030 reg = <0 0x00894000 0 0x4000>; 1031 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1032 clock-names = "se"; 1033 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1034 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1035 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1036 interconnect-names = "qup-core", "qup-config"; 1037 #address-cells = <1>; 1038 #size-cells = <0>; 1039 status = "disabled"; 1040 }; 1041 1042 uart5: serial@894000 { 1043 compatible = "qcom,geni-uart"; 1044 reg = <0 0x00894000 0 0x4000>; 1045 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1046 clock-names = "se"; 1047 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1048 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1049 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1050 interconnect-names = "qup-core", "qup-config"; 1051 status = "disabled"; 1052 }; 1053 1054 i2c6: i2c@898000 { 1055 compatible = "qcom,geni-i2c"; 1056 reg = <0 0x00898000 0 0x4000>; 1057 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1058 clock-names = "se"; 1059 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1060 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1061 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1062 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1063 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1064 #address-cells = <1>; 1065 #size-cells = <0>; 1066 status = "disabled"; 1067 }; 1068 1069 spi6: spi@898000 { 1070 compatible = "qcom,geni-spi"; 1071 reg = <0 0x00898000 0 0x4000>; 1072 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1073 clock-names = "se"; 1074 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1075 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1076 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1077 interconnect-names = "qup-core", "qup-config"; 1078 #address-cells = <1>; 1079 #size-cells = <0>; 1080 status = "disabled"; 1081 }; 1082 1083 uart6: serial@898000 { 1084 compatible = "qcom,geni-uart"; 1085 reg = <0 0x00898000 0 0x4000>; 1086 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1087 clock-names = "se"; 1088 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1089 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1090 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1091 interconnect-names = "qup-core", "qup-config"; 1092 status = "disabled"; 1093 }; 1094 1095 i2c7: i2c@89c000 { 1096 compatible = "qcom,geni-i2c"; 1097 reg = <0 0x0089c000 0 0x4000>; 1098 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1099 clock-names = "se"; 1100 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1101 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1102 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1103 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1104 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1105 #address-cells = <1>; 1106 #size-cells = <0>; 1107 status = "disabled"; 1108 }; 1109 1110 spi7: spi@89c000 { 1111 compatible = "qcom,geni-spi"; 1112 reg = <0 0x0089c000 0 0x4000>; 1113 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1114 clock-names = "se"; 1115 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1116 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1117 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1118 interconnect-names = "qup-core", "qup-config"; 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 status = "disabled"; 1122 }; 1123 1124 uart7: serial@89c000 { 1125 compatible = "qcom,geni-uart"; 1126 reg = <0 0x0089c000 0 0x4000>; 1127 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1128 clock-names = "se"; 1129 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1130 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1131 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1132 interconnect-names = "qup-core", "qup-config"; 1133 status = "disabled"; 1134 }; 1135 }; 1136 1137 qupv3_id_1: geniqup@ac0000 { 1138 compatible = "qcom,geni-se-qup"; 1139 reg = <0x0 0x00ac0000 0x0 0x6000>; 1140 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1141 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1142 clock-names = "m-ahb", "s-ahb"; 1143 #address-cells = <2>; 1144 #size-cells = <2>; 1145 ranges; 1146 iommus = <&apps_smmu 0x603 0>; 1147 status = "disabled"; 1148 1149 i2c8: i2c@a80000 { 1150 compatible = "qcom,geni-i2c"; 1151 reg = <0 0x00a80000 0 0x4000>; 1152 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1153 clock-names = "se"; 1154 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1155 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1156 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1157 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1158 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1159 #address-cells = <1>; 1160 #size-cells = <0>; 1161 status = "disabled"; 1162 }; 1163 1164 spi8: spi@a80000 { 1165 compatible = "qcom,geni-spi"; 1166 reg = <0 0x00a80000 0 0x4000>; 1167 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1168 clock-names = "se"; 1169 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1170 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1171 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1172 interconnect-names = "qup-core", "qup-config"; 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 status = "disabled"; 1176 }; 1177 1178 uart8: serial@a80000 { 1179 compatible = "qcom,geni-uart"; 1180 reg = <0 0x00a80000 0 0x4000>; 1181 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1182 clock-names = "se"; 1183 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1184 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1185 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1186 interconnect-names = "qup-core", "qup-config"; 1187 status = "disabled"; 1188 }; 1189 1190 i2c9: i2c@a84000 { 1191 compatible = "qcom,geni-i2c"; 1192 reg = <0 0x00a84000 0 0x4000>; 1193 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1194 clock-names = "se"; 1195 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1196 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1197 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1198 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1199 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1200 #address-cells = <1>; 1201 #size-cells = <0>; 1202 status = "disabled"; 1203 }; 1204 1205 spi9: spi@a84000 { 1206 compatible = "qcom,geni-spi"; 1207 reg = <0 0x00a84000 0 0x4000>; 1208 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1209 clock-names = "se"; 1210 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1211 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1212 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1213 interconnect-names = "qup-core", "qup-config"; 1214 #address-cells = <1>; 1215 #size-cells = <0>; 1216 status = "disabled"; 1217 }; 1218 1219 uart9: serial@a84000 { 1220 compatible = "qcom,geni-debug-uart"; 1221 reg = <0 0x00a84000 0 0x4000>; 1222 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1223 clock-names = "se"; 1224 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1225 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1226 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1227 interconnect-names = "qup-core", "qup-config"; 1228 status = "disabled"; 1229 }; 1230 1231 i2c10: i2c@a88000 { 1232 compatible = "qcom,geni-i2c"; 1233 reg = <0 0x00a88000 0 0x4000>; 1234 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1235 clock-names = "se"; 1236 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1237 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1238 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1239 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1240 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1241 #address-cells = <1>; 1242 #size-cells = <0>; 1243 status = "disabled"; 1244 }; 1245 1246 spi10: spi@a88000 { 1247 compatible = "qcom,geni-spi"; 1248 reg = <0 0x00a88000 0 0x4000>; 1249 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1250 clock-names = "se"; 1251 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1252 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1253 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1254 interconnect-names = "qup-core", "qup-config"; 1255 #address-cells = <1>; 1256 #size-cells = <0>; 1257 status = "disabled"; 1258 }; 1259 1260 uart10: serial@a88000 { 1261 compatible = "qcom,geni-uart"; 1262 reg = <0 0x00a88000 0 0x4000>; 1263 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1264 clock-names = "se"; 1265 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1266 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1267 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1268 interconnect-names = "qup-core", "qup-config"; 1269 status = "disabled"; 1270 }; 1271 1272 i2c11: i2c@a8c000 { 1273 compatible = "qcom,geni-i2c"; 1274 reg = <0 0x00a8c000 0 0x4000>; 1275 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1276 clock-names = "se"; 1277 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1278 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1279 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1280 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1281 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 status = "disabled"; 1285 }; 1286 1287 spi11: spi@a8c000 { 1288 compatible = "qcom,geni-spi"; 1289 reg = <0 0x00a8c000 0 0x4000>; 1290 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1291 clock-names = "se"; 1292 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1293 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1294 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1295 interconnect-names = "qup-core", "qup-config"; 1296 #address-cells = <1>; 1297 #size-cells = <0>; 1298 status = "disabled"; 1299 }; 1300 1301 uart11: serial@a8c000 { 1302 compatible = "qcom,geni-uart"; 1303 reg = <0 0x00a8c000 0 0x4000>; 1304 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1305 clock-names = "se"; 1306 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1307 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1308 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1309 interconnect-names = "qup-core", "qup-config"; 1310 status = "disabled"; 1311 }; 1312 1313 i2c12: i2c@a90000 { 1314 compatible = "qcom,geni-i2c"; 1315 reg = <0 0x00a90000 0 0x4000>; 1316 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1317 clock-names = "se"; 1318 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1319 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1320 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1321 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1322 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1323 #address-cells = <1>; 1324 #size-cells = <0>; 1325 status = "disabled"; 1326 }; 1327 1328 spi12: spi@a90000 { 1329 compatible = "qcom,geni-spi"; 1330 reg = <0 0x00a90000 0 0x4000>; 1331 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1332 clock-names = "se"; 1333 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1334 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1335 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1336 interconnect-names = "qup-core", "qup-config"; 1337 #address-cells = <1>; 1338 #size-cells = <0>; 1339 status = "disabled"; 1340 }; 1341 1342 uart12: serial@a90000 { 1343 compatible = "qcom,geni-uart"; 1344 reg = <0 0x00a90000 0 0x4000>; 1345 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1346 clock-names = "se"; 1347 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1348 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1349 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1350 interconnect-names = "qup-core", "qup-config"; 1351 status = "disabled"; 1352 }; 1353 1354 i2c16: i2c@a94000 { 1355 compatible = "qcom,geni-i2c"; 1356 reg = <0 0x00a94000 0 0x4000>; 1357 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1358 clock-names = "se"; 1359 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1360 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1361 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1362 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1363 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1364 #address-cells = <1>; 1365 #size-cells = <0>; 1366 status = "disabled"; 1367 }; 1368 1369 spi16: spi@a94000 { 1370 compatible = "qcom,geni-spi"; 1371 reg = <0 0x00a94000 0 0x4000>; 1372 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1373 clock-names = "se"; 1374 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1375 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1376 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1377 interconnect-names = "qup-core", "qup-config"; 1378 #address-cells = <1>; 1379 #size-cells = <0>; 1380 status = "disabled"; 1381 }; 1382 1383 uart16: serial@a94000 { 1384 compatible = "qcom,geni-uart"; 1385 reg = <0 0x00a94000 0 0x4000>; 1386 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1387 clock-names = "se"; 1388 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1389 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1390 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1391 interconnect-names = "qup-core", "qup-config"; 1392 status = "disabled"; 1393 }; 1394 }; 1395 1396 qupv3_id_2: geniqup@cc0000 { 1397 compatible = "qcom,geni-se-qup"; 1398 reg = <0x0 0x00cc0000 0x0 0x6000>; 1399 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1400 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1401 clock-names = "m-ahb", "s-ahb"; 1402 #address-cells = <2>; 1403 #size-cells = <2>; 1404 ranges; 1405 iommus = <&apps_smmu 0x7a3 0>; 1406 status = "disabled"; 1407 1408 i2c17: i2c@c80000 { 1409 compatible = "qcom,geni-i2c"; 1410 reg = <0 0x00c80000 0 0x4000>; 1411 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1412 clock-names = "se"; 1413 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1414 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1415 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1416 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1417 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1418 #address-cells = <1>; 1419 #size-cells = <0>; 1420 status = "disabled"; 1421 }; 1422 1423 spi17: spi@c80000 { 1424 compatible = "qcom,geni-spi"; 1425 reg = <0 0x00c80000 0 0x4000>; 1426 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1427 clock-names = "se"; 1428 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1429 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1430 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1431 interconnect-names = "qup-core", "qup-config"; 1432 #address-cells = <1>; 1433 #size-cells = <0>; 1434 status = "disabled"; 1435 }; 1436 1437 uart17: serial@c80000 { 1438 compatible = "qcom,geni-uart"; 1439 reg = <0 0x00c80000 0 0x4000>; 1440 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1441 clock-names = "se"; 1442 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1443 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1444 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1445 interconnect-names = "qup-core", "qup-config"; 1446 status = "disabled"; 1447 }; 1448 1449 i2c18: i2c@c84000 { 1450 compatible = "qcom,geni-i2c"; 1451 reg = <0 0x00c84000 0 0x4000>; 1452 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1453 clock-names = "se"; 1454 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1455 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1456 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1457 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1458 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1459 #address-cells = <1>; 1460 #size-cells = <0>; 1461 status = "disabled"; 1462 }; 1463 1464 spi18: spi@c84000 { 1465 compatible = "qcom,geni-spi"; 1466 reg = <0 0x00c84000 0 0x4000>; 1467 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1468 clock-names = "se"; 1469 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1470 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1471 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1472 interconnect-names = "qup-core", "qup-config"; 1473 #address-cells = <1>; 1474 #size-cells = <0>; 1475 status = "disabled"; 1476 }; 1477 1478 uart18: serial@c84000 { 1479 compatible = "qcom,geni-uart"; 1480 reg = <0 0x00c84000 0 0x4000>; 1481 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1482 clock-names = "se"; 1483 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1484 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1485 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1486 interconnect-names = "qup-core", "qup-config"; 1487 status = "disabled"; 1488 }; 1489 1490 i2c19: i2c@c88000 { 1491 compatible = "qcom,geni-i2c"; 1492 reg = <0 0x00c88000 0 0x4000>; 1493 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1494 clock-names = "se"; 1495 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1496 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1497 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1498 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1499 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1500 #address-cells = <1>; 1501 #size-cells = <0>; 1502 status = "disabled"; 1503 }; 1504 1505 spi19: spi@c88000 { 1506 compatible = "qcom,geni-spi"; 1507 reg = <0 0x00c88000 0 0x4000>; 1508 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1509 clock-names = "se"; 1510 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1511 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1512 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1513 interconnect-names = "qup-core", "qup-config"; 1514 #address-cells = <1>; 1515 #size-cells = <0>; 1516 status = "disabled"; 1517 }; 1518 1519 uart19: serial@c88000 { 1520 compatible = "qcom,geni-uart"; 1521 reg = <0 0x00c88000 0 0x4000>; 1522 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1523 clock-names = "se"; 1524 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1525 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1526 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1527 interconnect-names = "qup-core", "qup-config"; 1528 status = "disabled"; 1529 }; 1530 1531 i2c13: i2c@c8c000 { 1532 compatible = "qcom,geni-i2c"; 1533 reg = <0 0x00c8c000 0 0x4000>; 1534 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1535 clock-names = "se"; 1536 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1537 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1538 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1539 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1540 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1541 #address-cells = <1>; 1542 #size-cells = <0>; 1543 status = "disabled"; 1544 }; 1545 1546 spi13: spi@c8c000 { 1547 compatible = "qcom,geni-spi"; 1548 reg = <0 0x00c8c000 0 0x4000>; 1549 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1550 clock-names = "se"; 1551 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1552 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1553 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1554 interconnect-names = "qup-core", "qup-config"; 1555 #address-cells = <1>; 1556 #size-cells = <0>; 1557 status = "disabled"; 1558 }; 1559 1560 uart13: serial@c8c000 { 1561 compatible = "qcom,geni-uart"; 1562 reg = <0 0x00c8c000 0 0x4000>; 1563 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1564 clock-names = "se"; 1565 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1566 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1567 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1568 interconnect-names = "qup-core", "qup-config"; 1569 status = "disabled"; 1570 }; 1571 1572 i2c14: i2c@c90000 { 1573 compatible = "qcom,geni-i2c"; 1574 reg = <0 0x00c90000 0 0x4000>; 1575 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1576 clock-names = "se"; 1577 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1578 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1579 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1580 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1581 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1582 #address-cells = <1>; 1583 #size-cells = <0>; 1584 status = "disabled"; 1585 }; 1586 1587 spi14: spi@c90000 { 1588 compatible = "qcom,geni-spi"; 1589 reg = <0 0x00c90000 0 0x4000>; 1590 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1591 clock-names = "se"; 1592 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1593 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1594 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1595 interconnect-names = "qup-core", "qup-config"; 1596 #address-cells = <1>; 1597 #size-cells = <0>; 1598 status = "disabled"; 1599 }; 1600 1601 uart14: serial@c90000 { 1602 compatible = "qcom,geni-uart"; 1603 reg = <0 0x00c90000 0 0x4000>; 1604 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1605 clock-names = "se"; 1606 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1607 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1608 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1609 interconnect-names = "qup-core", "qup-config"; 1610 status = "disabled"; 1611 }; 1612 1613 i2c15: i2c@c94000 { 1614 compatible = "qcom,geni-i2c"; 1615 reg = <0 0x00c94000 0 0x4000>; 1616 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1617 clock-names = "se"; 1618 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1619 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1620 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1621 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1622 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1623 #address-cells = <1>; 1624 #size-cells = <0>; 1625 status = "disabled"; 1626 }; 1627 1628 spi15: spi@c94000 { 1629 compatible = "qcom,geni-spi"; 1630 reg = <0 0x00c94000 0 0x4000>; 1631 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1632 clock-names = "se"; 1633 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1634 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1635 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1636 interconnect-names = "qup-core", "qup-config"; 1637 #address-cells = <1>; 1638 #size-cells = <0>; 1639 status = "disabled"; 1640 }; 1641 1642 uart15: serial@c94000 { 1643 compatible = "qcom,geni-uart"; 1644 reg = <0 0x00c94000 0 0x4000>; 1645 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1646 clock-names = "se"; 1647 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1648 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1649 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1650 interconnect-names = "qup-core", "qup-config"; 1651 status = "disabled"; 1652 }; 1653 }; 1654 1655 config_noc: interconnect@1500000 { 1656 compatible = "qcom,sc8180x-config-noc"; 1657 reg = <0 0x01500000 0 0x7400>; 1658 #interconnect-cells = <2>; 1659 qcom,bcm-voters = <&apps_bcm_voter>; 1660 }; 1661 1662 system_noc: interconnect@1620000 { 1663 compatible = "qcom,sc8180x-system-noc"; 1664 reg = <0 0x01620000 0 0x19400>; 1665 #interconnect-cells = <2>; 1666 qcom,bcm-voters = <&apps_bcm_voter>; 1667 }; 1668 1669 aggre1_noc: interconnect@16e0000 { 1670 compatible = "qcom,sc8180x-aggre1-noc"; 1671 reg = <0 0x016e0000 0 0xd080>; 1672 #interconnect-cells = <2>; 1673 qcom,bcm-voters = <&apps_bcm_voter>; 1674 }; 1675 1676 aggre2_noc: interconnect@1700000 { 1677 compatible = "qcom,sc8180x-aggre2-noc"; 1678 reg = <0 0x01700000 0 0x20000>; 1679 #interconnect-cells = <2>; 1680 qcom,bcm-voters = <&apps_bcm_voter>; 1681 }; 1682 1683 compute_noc: interconnect@1720000 { 1684 compatible = "qcom,sc8180x-compute-noc"; 1685 reg = <0 0x01720000 0 0x7000>; 1686 #interconnect-cells = <2>; 1687 qcom,bcm-voters = <&apps_bcm_voter>; 1688 }; 1689 1690 mmss_noc: interconnect@1740000 { 1691 compatible = "qcom,sc8180x-mmss-noc"; 1692 reg = <0 0x01740000 0 0x1c100>; 1693 #interconnect-cells = <2>; 1694 qcom,bcm-voters = <&apps_bcm_voter>; 1695 }; 1696 1697 pcie0: pcie@1c00000 { 1698 compatible = "qcom,pcie-sc8180x"; 1699 reg = <0 0x01c00000 0 0x3000>, 1700 <0 0x60000000 0 0xf1d>, 1701 <0 0x60000f20 0 0xa8>, 1702 <0 0x60001000 0 0x1000>, 1703 <0 0x60100000 0 0x100000>; 1704 reg-names = "parf", 1705 "dbi", 1706 "elbi", 1707 "atu", 1708 "config"; 1709 device_type = "pci"; 1710 linux,pci-domain = <0>; 1711 bus-range = <0x00 0xff>; 1712 num-lanes = <2>; 1713 1714 #address-cells = <3>; 1715 #size-cells = <2>; 1716 1717 ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>, 1718 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1719 1720 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1721 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1722 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1723 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1724 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1725 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1726 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1727 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1728 interrupt-names = "msi0", 1729 "msi1", 1730 "msi2", 1731 "msi3", 1732 "msi4", 1733 "msi5", 1734 "msi6", 1735 "msi7"; 1736 #interrupt-cells = <1>; 1737 interrupt-map-mask = <0 0 0 0x7>; 1738 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1739 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1740 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1741 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1742 1743 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1744 <&gcc GCC_PCIE_0_AUX_CLK>, 1745 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1746 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1747 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1748 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1749 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1750 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1751 clock-names = "pipe", 1752 "aux", 1753 "cfg", 1754 "bus_master", 1755 "bus_slave", 1756 "slave_q2a", 1757 "ref", 1758 "tbu"; 1759 1760 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 1761 assigned-clock-rates = <19200000>; 1762 1763 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, 1764 <0x100 &apps_smmu 0x1d81 0x1>; 1765 1766 resets = <&gcc GCC_PCIE_0_BCR>; 1767 reset-names = "pci"; 1768 1769 power-domains = <&gcc PCIE_0_GDSC>; 1770 1771 interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>, 1772 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; 1773 interconnect-names = "pcie-mem", "cpu-pcie"; 1774 1775 phys = <&pcie0_phy>; 1776 phy-names = "pciephy"; 1777 dma-coherent; 1778 1779 status = "disabled"; 1780 1781 pcie@0 { 1782 device_type = "pci"; 1783 reg = <0x0 0x0 0x0 0x0 0x0>; 1784 bus-range = <0x01 0xff>; 1785 1786 #address-cells = <3>; 1787 #size-cells = <2>; 1788 ranges; 1789 }; 1790 }; 1791 1792 pcie0_phy: phy@1c06000 { 1793 compatible = "qcom,sc8180x-qmp-pcie-phy"; 1794 reg = <0 0x01c06000 0 0x1000>; 1795 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1796 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1797 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1798 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, 1799 <&gcc GCC_PCIE_0_PIPE_CLK>; 1800 clock-names = "aux", 1801 "cfg_ahb", 1802 "ref", 1803 "refgen", 1804 "pipe"; 1805 #clock-cells = <0>; 1806 clock-output-names = "pcie_0_pipe_clk"; 1807 #phy-cells = <0>; 1808 1809 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1810 reset-names = "phy"; 1811 1812 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1813 assigned-clock-rates = <100000000>; 1814 1815 status = "disabled"; 1816 }; 1817 1818 pcie3: pcie@1c08000 { 1819 compatible = "qcom,pcie-sc8180x"; 1820 reg = <0 0x01c08000 0 0x3000>, 1821 <0 0x40000000 0 0xf1d>, 1822 <0 0x40000f20 0 0xa8>, 1823 <0 0x40001000 0 0x1000>, 1824 <0 0x40100000 0 0x100000>; 1825 reg-names = "parf", 1826 "dbi", 1827 "elbi", 1828 "atu", 1829 "config"; 1830 device_type = "pci"; 1831 linux,pci-domain = <3>; 1832 bus-range = <0x00 0xff>; 1833 num-lanes = <2>; 1834 1835 #address-cells = <3>; 1836 #size-cells = <2>; 1837 1838 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1839 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1840 1841 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1842 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1843 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1844 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1845 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1846 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1849 interrupt-names = "msi0", 1850 "msi1", 1851 "msi2", 1852 "msi3", 1853 "msi4", 1854 "msi5", 1855 "msi6", 1856 "msi7"; 1857 #interrupt-cells = <1>; 1858 interrupt-map-mask = <0 0 0 0x7>; 1859 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1860 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1861 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1862 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1863 1864 clocks = <&gcc GCC_PCIE_3_PIPE_CLK>, 1865 <&gcc GCC_PCIE_3_AUX_CLK>, 1866 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 1867 <&gcc GCC_PCIE_3_MSTR_AXI_CLK>, 1868 <&gcc GCC_PCIE_3_SLV_AXI_CLK>, 1869 <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>, 1870 <&gcc GCC_PCIE_3_CLKREF_CLK>, 1871 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1872 clock-names = "pipe", 1873 "aux", 1874 "cfg", 1875 "bus_master", 1876 "bus_slave", 1877 "slave_q2a", 1878 "ref", 1879 "tbu"; 1880 1881 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>; 1882 assigned-clock-rates = <19200000>; 1883 1884 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 1885 <0x100 &apps_smmu 0x1e01 0x1>; 1886 1887 resets = <&gcc GCC_PCIE_3_BCR>; 1888 reset-names = "pci"; 1889 1890 power-domains = <&gcc PCIE_3_GDSC>; 1891 1892 interconnects = <&aggre2_noc MASTER_PCIE_3 0 &mc_virt SLAVE_EBI_CH0 0>, 1893 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; 1894 interconnect-names = "pcie-mem", "cpu-pcie"; 1895 1896 phys = <&pcie3_phy>; 1897 phy-names = "pciephy"; 1898 dma-coherent; 1899 1900 status = "disabled"; 1901 1902 pcie@0 { 1903 device_type = "pci"; 1904 reg = <0x0 0x0 0x0 0x0 0x0>; 1905 bus-range = <0x01 0xff>; 1906 1907 #address-cells = <3>; 1908 #size-cells = <2>; 1909 ranges; 1910 }; 1911 }; 1912 1913 pcie3_phy: phy@1c0c000 { 1914 compatible = "qcom,sc8180x-qmp-pcie-phy"; 1915 reg = <0 0x01c0c000 0 0x1000>; 1916 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1917 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 1918 <&gcc GCC_PCIE_3_CLKREF_CLK>, 1919 <&gcc GCC_PCIE3_PHY_REFGEN_CLK>, 1920 <&gcc GCC_PCIE_3_PIPE_CLK>; 1921 clock-names = "aux", 1922 "cfg_ahb", 1923 "ref", 1924 "refgen", 1925 "pipe"; 1926 #clock-cells = <0>; 1927 clock-output-names = "pcie_3_pipe_clk"; 1928 1929 #phy-cells = <0>; 1930 1931 resets = <&gcc GCC_PCIE_3_PHY_BCR>; 1932 reset-names = "phy"; 1933 1934 assigned-clocks = <&gcc GCC_PCIE3_PHY_REFGEN_CLK>; 1935 assigned-clock-rates = <100000000>; 1936 1937 status = "disabled"; 1938 }; 1939 1940 pcie1: pcie@1c10000 { 1941 compatible = "qcom,pcie-sc8180x"; 1942 reg = <0 0x01c10000 0 0x3000>, 1943 <0 0x68000000 0 0xf1d>, 1944 <0 0x68000f20 0 0xa8>, 1945 <0 0x68001000 0 0x1000>, 1946 <0 0x68100000 0 0x100000>; 1947 reg-names = "parf", 1948 "dbi", 1949 "elbi", 1950 "atu", 1951 "config"; 1952 device_type = "pci"; 1953 linux,pci-domain = <1>; 1954 bus-range = <0x00 0xff>; 1955 num-lanes = <2>; 1956 1957 #address-cells = <3>; 1958 #size-cells = <2>; 1959 1960 ranges = <0x01000000 0x0 0x68200000 0x0 0x68200000 0x0 0x100000>, 1961 <0x02000000 0x0 0x68300000 0x0 0x68300000 0x0 0x3d00000>; 1962 1963 interrupts = <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>, 1964 <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>, 1965 <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>, 1966 <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>, 1967 <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>, 1968 <GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>, 1969 <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>, 1970 <GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>; 1971 interrupt-names = "msi0", 1972 "msi1", 1973 "msi2", 1974 "msi3", 1975 "msi4", 1976 "msi5", 1977 "msi6", 1978 "msi7"; 1979 #interrupt-cells = <1>; 1980 interrupt-map-mask = <0 0 0 0x7>; 1981 interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1982 <0 0 0 2 &intc 0 746 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1983 <0 0 0 3 &intc 0 745 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1984 <0 0 0 4 &intc 0 744 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1985 1986 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1987 <&gcc GCC_PCIE_1_AUX_CLK>, 1988 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1989 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1990 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1991 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1992 <&gcc GCC_PCIE_1_CLKREF_CLK>, 1993 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1994 clock-names = "pipe", 1995 "aux", 1996 "cfg", 1997 "bus_master", 1998 "bus_slave", 1999 "slave_q2a", 2000 "ref", 2001 "tbu"; 2002 2003 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2004 assigned-clock-rates = <19200000>; 2005 2006 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2007 <0x100 &apps_smmu 0x1c81 0x1>; 2008 2009 resets = <&gcc GCC_PCIE_1_BCR>; 2010 reset-names = "pci"; 2011 2012 power-domains = <&gcc PCIE_1_GDSC>; 2013 2014 interconnects = <&aggre2_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI_CH0 0>, 2015 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; 2016 interconnect-names = "pcie-mem", "cpu-pcie"; 2017 2018 phys = <&pcie1_phy>; 2019 phy-names = "pciephy"; 2020 dma-coherent; 2021 2022 status = "disabled"; 2023 2024 pcie@0 { 2025 device_type = "pci"; 2026 reg = <0x0 0x0 0x0 0x0 0x0>; 2027 bus-range = <0x01 0xff>; 2028 2029 #address-cells = <3>; 2030 #size-cells = <2>; 2031 ranges; 2032 }; 2033 }; 2034 2035 pcie1_phy: phy@1c16000 { 2036 compatible = "qcom,sc8180x-qmp-pcie-phy"; 2037 reg = <0 0x01c16000 0 0x1000>; 2038 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2039 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2040 <&gcc GCC_PCIE_1_CLKREF_CLK>, 2041 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, 2042 <&gcc GCC_PCIE_1_PIPE_CLK>; 2043 clock-names = "aux", 2044 "cfg_ahb", 2045 "ref", 2046 "refgen", 2047 "pipe"; 2048 #clock-cells = <0>; 2049 clock-output-names = "pcie_1_pipe_clk"; 2050 2051 #phy-cells = <0>; 2052 2053 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2054 reset-names = "phy"; 2055 2056 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2057 assigned-clock-rates = <100000000>; 2058 2059 status = "disabled"; 2060 }; 2061 2062 pcie2: pcie@1c18000 { 2063 compatible = "qcom,pcie-sc8180x"; 2064 reg = <0 0x01c18000 0 0x3000>, 2065 <0 0x70000000 0 0xf1d>, 2066 <0 0x70000f20 0 0xa8>, 2067 <0 0x70001000 0 0x1000>, 2068 <0 0x70100000 0 0x100000>; 2069 reg-names = "parf", 2070 "dbi", 2071 "elbi", 2072 "atu", 2073 "config"; 2074 device_type = "pci"; 2075 linux,pci-domain = <2>; 2076 bus-range = <0x00 0xff>; 2077 num-lanes = <4>; 2078 2079 #address-cells = <3>; 2080 #size-cells = <2>; 2081 2082 ranges = <0x01000000 0x0 0x70200000 0x0 0x70200000 0x0 0x100000>, 2083 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>; 2084 2085 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2086 <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>, 2087 <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>, 2088 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 2089 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>, 2090 <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>, 2091 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 2092 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>; 2093 interrupt-names = "msi0", 2094 "msi1", 2095 "msi2", 2096 "msi3", 2097 "msi4", 2098 "msi5", 2099 "msi6", 2100 "msi7"; 2101 #interrupt-cells = <1>; 2102 interrupt-map-mask = <0 0 0 0x7>; 2103 interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2104 <0 0 0 2 &intc 0 662 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2105 <0 0 0 3 &intc 0 661 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2106 <0 0 0 4 &intc 0 660 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2107 2108 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2109 <&gcc GCC_PCIE_2_AUX_CLK>, 2110 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2111 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2112 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 2113 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 2114 <&gcc GCC_PCIE_2_CLKREF_CLK>, 2115 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2116 clock-names = "pipe", 2117 "aux", 2118 "cfg", 2119 "bus_master", 2120 "bus_slave", 2121 "slave_q2a", 2122 "ref", 2123 "tbu"; 2124 2125 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 2126 assigned-clock-rates = <19200000>; 2127 2128 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 2129 <0x100 &apps_smmu 0x1d01 0x1>; 2130 2131 resets = <&gcc GCC_PCIE_2_BCR>; 2132 reset-names = "pci"; 2133 2134 power-domains = <&gcc PCIE_2_GDSC>; 2135 2136 interconnects = <&aggre2_noc MASTER_PCIE_2 0 &mc_virt SLAVE_EBI_CH0 0>, 2137 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; 2138 interconnect-names = "pcie-mem", "cpu-pcie"; 2139 2140 phys = <&pcie2_phy>; 2141 phy-names = "pciephy"; 2142 dma-coherent; 2143 2144 status = "disabled"; 2145 2146 pcie@0 { 2147 device_type = "pci"; 2148 reg = <0x0 0x0 0x0 0x0 0x0>; 2149 bus-range = <0x01 0xff>; 2150 2151 #address-cells = <3>; 2152 #size-cells = <2>; 2153 ranges; 2154 }; 2155 }; 2156 2157 pcie2_phy: phy@1c1c000 { 2158 compatible = "qcom,sc8180x-qmp-pcie-phy"; 2159 reg = <0 0x01c1c000 0 0x1000>; 2160 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2161 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2162 <&gcc GCC_PCIE_2_CLKREF_CLK>, 2163 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>, 2164 <&gcc GCC_PCIE_2_PIPE_CLK>; 2165 clock-names = "aux", 2166 "cfg_ahb", 2167 "ref", 2168 "refgen", 2169 "pipe"; 2170 #clock-cells = <0>; 2171 clock-output-names = "pcie_2_pipe_clk"; 2172 2173 #phy-cells = <0>; 2174 2175 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 2176 reset-names = "phy"; 2177 2178 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2179 assigned-clock-rates = <100000000>; 2180 2181 status = "disabled"; 2182 }; 2183 2184 ufs_mem_hc: ufshc@1d84000 { 2185 compatible = "qcom,sc8180x-ufshc", "qcom,ufshc", 2186 "jedec,ufs-2.0"; 2187 reg = <0 0x01d84000 0 0x2500>; 2188 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2189 phys = <&ufs_mem_phy>; 2190 phy-names = "ufsphy"; 2191 lanes-per-direction = <2>; 2192 #reset-cells = <1>; 2193 resets = <&gcc GCC_UFS_PHY_BCR>; 2194 reset-names = "rst"; 2195 2196 iommus = <&apps_smmu 0x300 0>; 2197 2198 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2199 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2200 <&gcc GCC_UFS_PHY_AHB_CLK>, 2201 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2202 <&rpmhcc RPMH_CXO_CLK>, 2203 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2204 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2205 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2206 clock-names = "core_clk", 2207 "bus_aggr_clk", 2208 "iface_clk", 2209 "core_clk_unipro", 2210 "ref_clk", 2211 "tx_lane0_sync_clk", 2212 "rx_lane0_sync_clk", 2213 "rx_lane1_sync_clk"; 2214 freq-table-hz = <37500000 300000000>, 2215 <0 0>, 2216 <0 0>, 2217 <37500000 300000000>, 2218 <0 0>, 2219 <0 0>, 2220 <0 0>, 2221 <0 0>; 2222 2223 power-domains = <&gcc UFS_PHY_GDSC>; 2224 2225 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2226 &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, 2227 <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS 2228 &config_noc SLAVE_UFS_MEM_0_CFG QCOM_ICC_TAG_ALWAYS>; 2229 interconnect-names = "ufs-ddr", "cpu-ufs"; 2230 2231 status = "disabled"; 2232 }; 2233 2234 ufs_mem_phy: phy-wrapper@1d87000 { 2235 compatible = "qcom,sc8180x-qmp-ufs-phy"; 2236 reg = <0 0x01d87000 0 0x1000>; 2237 2238 clocks = <&rpmhcc RPMH_CXO_CLK>, 2239 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2240 <&gcc GCC_UFS_MEM_CLKREF_EN>; 2241 clock-names = "ref", 2242 "ref_aux", 2243 "qref"; 2244 2245 resets = <&ufs_mem_hc 0>; 2246 reset-names = "ufsphy"; 2247 2248 #phy-cells = <0>; 2249 2250 status = "disabled"; 2251 }; 2252 2253 ipa_virt: interconnect@1e00000 { 2254 compatible = "qcom,sc8180x-ipa-virt"; 2255 reg = <0 0x01e00000 0 0x1000>; 2256 #interconnect-cells = <2>; 2257 qcom,bcm-voters = <&apps_bcm_voter>; 2258 }; 2259 2260 tcsr_mutex: hwlock@1f40000 { 2261 compatible = "qcom,tcsr-mutex"; 2262 reg = <0x0 0x01f40000 0x0 0x40000>; 2263 #hwlock-cells = <1>; 2264 }; 2265 2266 gpu: gpu@2c00000 { 2267 compatible = "qcom,adreno-680.1", "qcom,adreno"; 2268 2269 reg = <0 0x02c00000 0 0x40000>; 2270 reg-names = "kgsl_3d0_reg_memory"; 2271 2272 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2273 2274 iommus = <&adreno_smmu 0 0xc01>; 2275 2276 operating-points-v2 = <&gpu_opp_table>; 2277 2278 interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &mc_virt SLAVE_EBI_CH0 0>; 2279 interconnect-names = "gfx-mem"; 2280 2281 qcom,gmu = <&gmu>; 2282 #cooling-cells = <2>; 2283 2284 status = "disabled"; 2285 2286 gpu_opp_table: opp-table { 2287 compatible = "operating-points-v2"; 2288 2289 opp-514000000 { 2290 opp-hz = /bits/ 64 <514000000>; 2291 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2292 }; 2293 2294 opp-500000000 { 2295 opp-hz = /bits/ 64 <500000000>; 2296 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2297 }; 2298 2299 opp-461000000 { 2300 opp-hz = /bits/ 64 <461000000>; 2301 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2302 }; 2303 2304 opp-405000000 { 2305 opp-hz = /bits/ 64 <405000000>; 2306 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2307 }; 2308 2309 opp-315000000 { 2310 opp-hz = /bits/ 64 <315000000>; 2311 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2312 }; 2313 2314 opp-256000000 { 2315 opp-hz = /bits/ 64 <256000000>; 2316 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2317 }; 2318 2319 opp-177000000 { 2320 opp-hz = /bits/ 64 <177000000>; 2321 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2322 }; 2323 }; 2324 }; 2325 2326 gmu: gmu@2c6a000 { 2327 compatible = "qcom,adreno-gmu-680.1", "qcom,adreno-gmu"; 2328 2329 reg = <0 0x02c6a000 0 0x30000>, 2330 <0 0x0b290000 0 0x10000>, 2331 <0 0x0b490000 0 0x10000>; 2332 reg-names = "gmu", 2333 "gmu_pdc", 2334 "gmu_pdc_seq"; 2335 2336 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2337 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2338 interrupt-names = "hfi", "gmu"; 2339 2340 clocks = <&gpucc GPU_CC_AHB_CLK>, 2341 <&gpucc GPU_CC_CX_GMU_CLK>, 2342 <&gpucc GPU_CC_CXO_CLK>, 2343 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2344 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2345 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2346 2347 power-domains = <&gpucc GPU_CX_GDSC>, 2348 <&gpucc GPU_GX_GDSC>; 2349 power-domain-names = "cx", "gx"; 2350 2351 iommus = <&adreno_smmu 5 0xc00>; 2352 2353 operating-points-v2 = <&gmu_opp_table>; 2354 2355 gmu_opp_table: opp-table { 2356 compatible = "operating-points-v2"; 2357 2358 opp-200000000 { 2359 opp-hz = /bits/ 64 <200000000>; 2360 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2361 }; 2362 2363 opp-500000000 { 2364 opp-hz = /bits/ 64 <500000000>; 2365 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2366 }; 2367 }; 2368 }; 2369 2370 gpucc: clock-controller@2c90000 { 2371 compatible = "qcom,sc8180x-gpucc"; 2372 reg = <0 0x02c90000 0 0x9000>; 2373 clocks = <&rpmhcc RPMH_CXO_CLK>, 2374 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2375 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2376 clock-names = "bi_tcxo", 2377 "gcc_gpu_gpll0_clk_src", 2378 "gcc_gpu_gpll0_div_clk_src"; 2379 #clock-cells = <1>; 2380 #reset-cells = <1>; 2381 #power-domain-cells = <1>; 2382 }; 2383 2384 adreno_smmu: iommu@2ca0000 { 2385 compatible = "qcom,sc8180x-smmu-500", "qcom,adreno-smmu", 2386 "qcom,smmu-500", "arm,mmu-500"; 2387 reg = <0 0x02ca0000 0 0x10000>; 2388 #iommu-cells = <2>; 2389 #global-interrupts = <1>; 2390 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 2391 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2392 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2393 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2394 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2395 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2396 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2397 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2398 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 2399 clocks = <&gpucc GPU_CC_AHB_CLK>, 2400 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2401 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2402 clock-names = "ahb", "bus", "iface"; 2403 2404 power-domains = <&gpucc GPU_CX_GDSC>; 2405 }; 2406 2407 tlmm: pinctrl@3100000 { 2408 compatible = "qcom,sc8180x-tlmm"; 2409 reg = <0 0x03100000 0 0x300000>, 2410 <0 0x03500000 0 0x700000>, 2411 <0 0x03d00000 0 0x300000>; 2412 reg-names = "west", "east", "south"; 2413 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2414 gpio-controller; 2415 #gpio-cells = <2>; 2416 interrupt-controller; 2417 #interrupt-cells = <2>; 2418 gpio-ranges = <&tlmm 0 0 191>; 2419 wakeup-parent = <&pdc>; 2420 }; 2421 2422 remoteproc_mpss: remoteproc@4080000 { 2423 compatible = "qcom,sc8180x-mpss-pas"; 2424 reg = <0x0 0x04080000 0x0 0x4040>; 2425 2426 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2427 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2428 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2429 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2430 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2431 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2432 interrupt-names = "wdog", "fatal", "ready", "handover", 2433 "stop-ack", "shutdown-ack"; 2434 2435 clocks = <&rpmhcc RPMH_CXO_CLK>; 2436 clock-names = "xo"; 2437 2438 power-domains = <&rpmhpd SC8180X_CX>, 2439 <&rpmhpd SC8180X_MSS>; 2440 power-domain-names = "cx", "mss"; 2441 2442 qcom,qmp = <&aoss_qmp>; 2443 2444 qcom,smem-states = <&modem_smp2p_out 0>; 2445 qcom,smem-state-names = "stop"; 2446 2447 glink-edge { 2448 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2449 label = "modem"; 2450 qcom,remote-pid = <1>; 2451 mboxes = <&apss_shared 12>; 2452 }; 2453 }; 2454 2455 remoteproc_cdsp: remoteproc@8300000 { 2456 compatible = "qcom,sc8180x-cdsp-pas"; 2457 reg = <0x0 0x08300000 0x0 0x4040>; 2458 2459 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2460 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2461 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2462 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2463 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2464 interrupt-names = "wdog", "fatal", "ready", 2465 "handover", "stop-ack"; 2466 2467 clocks = <&rpmhcc RPMH_CXO_CLK>; 2468 clock-names = "xo"; 2469 2470 power-domains = <&rpmhpd SC8180X_CX>; 2471 power-domain-names = "cx"; 2472 2473 qcom,qmp = <&aoss_qmp>; 2474 2475 qcom,smem-states = <&cdsp_smp2p_out 0>; 2476 qcom,smem-state-names = "stop"; 2477 2478 status = "disabled"; 2479 2480 glink-edge { 2481 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 2482 label = "cdsp"; 2483 qcom,remote-pid = <5>; 2484 mboxes = <&apss_shared 4>; 2485 }; 2486 }; 2487 2488 usb_prim_hsphy: phy@88e2000 { 2489 compatible = "qcom,sc8180x-usb-hs-phy", 2490 "qcom,usb-snps-hs-7nm-phy"; 2491 reg = <0 0x088e2000 0 0x400>; 2492 clocks = <&rpmhcc RPMH_CXO_CLK>; 2493 clock-names = "ref"; 2494 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2495 2496 #phy-cells = <0>; 2497 2498 status = "disabled"; 2499 }; 2500 2501 usb_sec_hsphy: phy@88e3000 { 2502 compatible = "qcom,sc8180x-usb-hs-phy", 2503 "qcom,usb-snps-hs-7nm-phy"; 2504 reg = <0 0x088e3000 0 0x400>; 2505 clocks = <&rpmhcc RPMH_CXO_CLK>; 2506 clock-names = "ref"; 2507 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2508 2509 #phy-cells = <0>; 2510 2511 status = "disabled"; 2512 }; 2513 2514 usb_prim_qmpphy: phy@88e9000 { 2515 compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; 2516 reg = <0 0x088e9000 0 0x18c>, 2517 <0 0x088e8000 0 0x38>, 2518 <0 0x088ea000 0 0x40>; 2519 reg-names = "reg-base", "dp_com"; 2520 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2521 <&rpmhcc RPMH_CXO_CLK>, 2522 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2523 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2524 clock-names = "aux", 2525 "ref_clk_src", 2526 "ref", 2527 "com_aux"; 2528 resets = <&gcc GCC_USB3_DP_PHY_PRIM_SP0_BCR>, 2529 <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>; 2530 reset-names = "phy", "common"; 2531 2532 #clock-cells = <1>; 2533 #address-cells = <2>; 2534 #size-cells = <2>; 2535 ranges; 2536 2537 status = "disabled"; 2538 2539 ports { 2540 #address-cells = <1>; 2541 #size-cells = <0>; 2542 2543 port@0 { 2544 reg = <0>; 2545 2546 usb_prim_qmpphy_out: endpoint {}; 2547 }; 2548 2549 port@2 { 2550 reg = <2>; 2551 2552 usb_prim_qmpphy_dp_in: endpoint {}; 2553 }; 2554 }; 2555 2556 usb_prim_ssphy: usb3-phy@88e9200 { 2557 reg = <0 0x088e9200 0 0x200>, 2558 <0 0x088e9400 0 0x200>, 2559 <0 0x088e9c00 0 0x218>, 2560 <0 0x088e9600 0 0x200>, 2561 <0 0x088e9800 0 0x200>, 2562 <0 0x088e9a00 0 0x100>; 2563 #phy-cells = <0>; 2564 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2565 clock-names = "pipe0"; 2566 clock-output-names = "usb3_prim_phy_pipe_clk_src"; 2567 }; 2568 2569 usb_prim_dpphy: dp-phy@88ea200 { 2570 reg = <0 0x088ea200 0 0x200>, 2571 <0 0x088ea400 0 0x200>, 2572 <0 0x088eaa00 0 0x200>, 2573 <0 0x088ea600 0 0x200>, 2574 <0 0x088ea800 0 0x200>; 2575 #clock-cells = <1>; 2576 #phy-cells = <0>; 2577 }; 2578 }; 2579 2580 usb_sec_qmpphy: phy@88ee000 { 2581 compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; 2582 reg = <0 0x088ee000 0 0x18c>, 2583 <0 0x088ed000 0 0x10>, 2584 <0 0x088ef000 0 0x40>; 2585 reg-names = "reg-base", "dp_com"; 2586 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2587 <&rpmhcc RPMH_CXO_CLK>, 2588 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 2589 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2590 clock-names = "aux", 2591 "ref_clk_src", 2592 "ref", 2593 "com_aux"; 2594 resets = <&gcc GCC_USB3_DP_PHY_SEC_BCR>, 2595 <&gcc GCC_USB3_PHY_SEC_BCR>; 2596 reset-names = "phy", "common"; 2597 2598 #clock-cells = <1>; 2599 #address-cells = <2>; 2600 #size-cells = <2>; 2601 ranges; 2602 2603 status = "disabled"; 2604 2605 ports { 2606 #address-cells = <1>; 2607 #size-cells = <0>; 2608 2609 port@0 { 2610 reg = <0>; 2611 2612 usb_sec_qmpphy_out: endpoint {}; 2613 }; 2614 2615 port@2 { 2616 reg = <2>; 2617 2618 usb_sec_qmpphy_dp_in: endpoint {}; 2619 }; 2620 }; 2621 2622 usb_sec_ssphy: usb3-phy@88e9200 { 2623 reg = <0 0x088ee200 0 0x200>, 2624 <0 0x088ee400 0 0x200>, 2625 <0 0x088eec00 0 0x218>, 2626 <0 0x088ee600 0 0x200>, 2627 <0 0x088ee800 0 0x200>, 2628 <0 0x088eea00 0 0x100>; 2629 #phy-cells = <0>; 2630 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2631 clock-names = "pipe0"; 2632 clock-output-names = "usb3_sec_phy_pipe_clk_src"; 2633 }; 2634 2635 usb_sec_dpphy: dp-phy@88ef200 { 2636 reg = <0 0x088ef200 0 0x200>, 2637 <0 0x088ef400 0 0x200>, 2638 <0 0x088efa00 0 0x200>, 2639 <0 0x088ef600 0 0x200>, 2640 <0 0x088ef800 0 0x200>; 2641 #clock-cells = <1>; 2642 #phy-cells = <0>; 2643 clock-output-names = "qmp_dptx1_phy_pll_link_clk", 2644 "qmp_dptx1_phy_pll_vco_div_clk"; 2645 }; 2646 }; 2647 2648 system-cache-controller@9200000 { 2649 compatible = "qcom,sc8180x-llcc"; 2650 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, 2651 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, 2652 <0 0x09600000 0 0x50000>; 2653 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2654 "llcc3_base", "llcc_broadcast_base"; 2655 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2656 }; 2657 2658 gem_noc: interconnect@9680000 { 2659 compatible = "qcom,sc8180x-gem-noc"; 2660 reg = <0 0x09680000 0 0x58200>; 2661 #interconnect-cells = <2>; 2662 qcom,bcm-voters = <&apps_bcm_voter>; 2663 }; 2664 2665 usb_prim: usb@a6f8800 { 2666 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3"; 2667 reg = <0 0x0a6f8800 0 0x400>; 2668 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2669 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 2670 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 2671 <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 2672 interrupt-names = "hs_phy_irq", 2673 "ss_phy_irq", 2674 "dm_hs_phy_irq", 2675 "dp_hs_phy_irq"; 2676 2677 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2678 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2679 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2680 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2681 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2682 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 2683 clock-names = "cfg_noc", 2684 "core", 2685 "iface", 2686 "sleep", 2687 "mock_utmi", 2688 "xo"; 2689 resets = <&gcc GCC_USB30_PRIM_BCR>; 2690 power-domains = <&gcc USB30_PRIM_GDSC>; 2691 2692 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, 2693 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 2694 interconnect-names = "usb-ddr", "apps-usb"; 2695 2696 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2697 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2698 assigned-clock-rates = <19200000>, <200000000>; 2699 2700 #address-cells = <2>; 2701 #size-cells = <2>; 2702 ranges; 2703 dma-ranges; 2704 2705 status = "disabled"; 2706 2707 usb_prim_dwc3: usb@a600000 { 2708 compatible = "snps,dwc3"; 2709 reg = <0 0x0a600000 0 0xcd00>; 2710 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2711 iommus = <&apps_smmu 0x140 0>; 2712 snps,dis_u2_susphy_quirk; 2713 snps,dis_enblslpm_quirk; 2714 phys = <&usb_prim_hsphy>, <&usb_prim_ssphy>; 2715 phy-names = "usb2-phy", "usb3-phy"; 2716 2717 port { 2718 usb_prim_role_switch: endpoint { 2719 }; 2720 }; 2721 }; 2722 }; 2723 2724 usb_sec: usb@a8f8800 { 2725 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3"; 2726 reg = <0 0x0a8f8800 0 0x400>; 2727 2728 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2729 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2730 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2731 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2732 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2733 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 2734 clock-names = "cfg_noc", 2735 "core", 2736 "iface", 2737 "sleep", 2738 "mock_utmi", 2739 "xo"; 2740 resets = <&gcc GCC_USB30_SEC_BCR>; 2741 power-domains = <&gcc USB30_SEC_GDSC>; 2742 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2743 <&pdc 40 IRQ_TYPE_LEVEL_HIGH>, 2744 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 2745 <&pdc 11 IRQ_TYPE_EDGE_BOTH>; 2746 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2747 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2748 2749 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2750 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2751 assigned-clock-rates = <19200000>, <200000000>; 2752 2753 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, 2754 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; 2755 interconnect-names = "usb-ddr", "apps-usb"; 2756 2757 #address-cells = <2>; 2758 #size-cells = <2>; 2759 ranges; 2760 dma-ranges; 2761 2762 status = "disabled"; 2763 2764 usb_sec_dwc3: usb@a800000 { 2765 compatible = "snps,dwc3"; 2766 reg = <0 0x0a800000 0 0xcd00>; 2767 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2768 iommus = <&apps_smmu 0x160 0>; 2769 snps,dis_u2_susphy_quirk; 2770 snps,dis_enblslpm_quirk; 2771 phys = <&usb_sec_hsphy>, <&usb_sec_ssphy>; 2772 phy-names = "usb2-phy", "usb3-phy"; 2773 2774 port { 2775 usb_sec_role_switch: endpoint { 2776 }; 2777 }; 2778 }; 2779 }; 2780 2781 mdss: mdss@ae00000 { 2782 compatible = "qcom,sc8180x-mdss"; 2783 reg = <0 0x0ae00000 0 0x1000>; 2784 reg-names = "mdss"; 2785 2786 power-domains = <&dispcc MDSS_GDSC>; 2787 2788 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2789 <&gcc GCC_DISP_HF_AXI_CLK>, 2790 <&gcc GCC_DISP_SF_AXI_CLK>, 2791 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2792 clock-names = "iface", 2793 "bus", 2794 "nrt_bus", 2795 "core"; 2796 2797 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2798 2799 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2800 interrupt-controller; 2801 #interrupt-cells = <1>; 2802 2803 interconnects = <&mmss_noc MASTER_MDP_PORT0 QCOM_ICC_TAG_ALWAYS 2804 &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, 2805 <&mmss_noc MASTER_MDP_PORT1 QCOM_ICC_TAG_ALWAYS 2806 &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, 2807 <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ALWAYS 2808 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>; 2809 interconnect-names = "mdp0-mem", 2810 "mdp1-mem", 2811 "cpu-cfg"; 2812 2813 iommus = <&apps_smmu 0x800 0x420>; 2814 2815 #address-cells = <2>; 2816 #size-cells = <2>; 2817 ranges; 2818 2819 status = "disabled"; 2820 2821 mdss_mdp: mdp@ae01000 { 2822 compatible = "qcom,sc8180x-dpu"; 2823 reg = <0 0x0ae01000 0 0x8f000>, 2824 <0 0x0aeb0000 0 0x2008>; 2825 reg-names = "mdp", "vbif"; 2826 2827 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2828 <&gcc GCC_DISP_HF_AXI_CLK>, 2829 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2830 <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 2831 <&dispcc DISP_CC_MDSS_ROT_CLK>, 2832 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; 2833 clock-names = "iface", 2834 "bus", 2835 "core", 2836 "vsync", 2837 "rot", 2838 "lut"; 2839 2840 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2841 assigned-clock-rates = <19200000>; 2842 2843 operating-points-v2 = <&mdp_opp_table>; 2844 power-domains = <&rpmhpd SC8180X_MMCX>; 2845 2846 interrupt-parent = <&mdss>; 2847 interrupts = <0>; 2848 2849 ports { 2850 #address-cells = <1>; 2851 #size-cells = <0>; 2852 2853 port@0 { 2854 reg = <0>; 2855 dpu_intf0_out: endpoint { 2856 remote-endpoint = <&dp0_in>; 2857 }; 2858 }; 2859 2860 port@1 { 2861 reg = <1>; 2862 dpu_intf1_out: endpoint { 2863 remote-endpoint = <&mdss_dsi0_in>; 2864 }; 2865 }; 2866 2867 port@2 { 2868 reg = <2>; 2869 dpu_intf2_out: endpoint { 2870 remote-endpoint = <&mdss_dsi1_in>; 2871 }; 2872 }; 2873 2874 port@4 { 2875 reg = <4>; 2876 dpu_intf4_out: endpoint { 2877 remote-endpoint = <&dp1_in>; 2878 }; 2879 }; 2880 2881 port@5 { 2882 reg = <5>; 2883 dpu_intf5_out: endpoint { 2884 remote-endpoint = <&edp_in>; 2885 }; 2886 }; 2887 }; 2888 2889 mdp_opp_table: opp-table { 2890 compatible = "operating-points-v2"; 2891 2892 opp-200000000 { 2893 opp-hz = /bits/ 64 <200000000>; 2894 required-opps = <&rpmhpd_opp_low_svs>; 2895 }; 2896 2897 opp-300000000 { 2898 opp-hz = /bits/ 64 <300000000>; 2899 required-opps = <&rpmhpd_opp_svs>; 2900 }; 2901 2902 opp-345000000 { 2903 opp-hz = /bits/ 64 <345000000>; 2904 required-opps = <&rpmhpd_opp_svs_l1>; 2905 }; 2906 2907 opp-460000000 { 2908 opp-hz = /bits/ 64 <460000000>; 2909 required-opps = <&rpmhpd_opp_nom>; 2910 }; 2911 }; 2912 }; 2913 2914 mdss_dsi0: dsi@ae94000 { 2915 compatible = "qcom,mdss-dsi-ctrl"; 2916 reg = <0 0x0ae94000 0 0x400>; 2917 reg-names = "dsi_ctrl"; 2918 2919 interrupt-parent = <&mdss>; 2920 interrupts = <4>; 2921 2922 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2923 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2924 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2925 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2926 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2927 <&gcc GCC_DISP_HF_AXI_CLK>; 2928 clock-names = "byte", 2929 "byte_intf", 2930 "pixel", 2931 "core", 2932 "iface", 2933 "bus"; 2934 2935 operating-points-v2 = <&dsi_opp_table>; 2936 power-domains = <&rpmhpd SC8180X_MMCX>; 2937 2938 phys = <&mdss_dsi0_phy>; 2939 phy-names = "dsi"; 2940 2941 status = "disabled"; 2942 2943 ports { 2944 #address-cells = <1>; 2945 #size-cells = <0>; 2946 2947 port@0 { 2948 reg = <0>; 2949 mdss_dsi0_in: endpoint { 2950 remote-endpoint = <&dpu_intf1_out>; 2951 }; 2952 }; 2953 2954 port@1 { 2955 reg = <1>; 2956 mdss_dsi0_out: endpoint { 2957 }; 2958 }; 2959 }; 2960 2961 dsi_opp_table: opp-table { 2962 compatible = "operating-points-v2"; 2963 2964 opp-187500000 { 2965 opp-hz = /bits/ 64 <187500000>; 2966 required-opps = <&rpmhpd_opp_low_svs>; 2967 }; 2968 2969 opp-300000000 { 2970 opp-hz = /bits/ 64 <300000000>; 2971 required-opps = <&rpmhpd_opp_svs>; 2972 }; 2973 2974 opp-358000000 { 2975 opp-hz = /bits/ 64 <358000000>; 2976 required-opps = <&rpmhpd_opp_svs_l1>; 2977 }; 2978 }; 2979 }; 2980 2981 mdss_dsi0_phy: dsi-phy@ae94400 { 2982 compatible = "qcom,dsi-phy-7nm"; 2983 reg = <0 0x0ae94400 0 0x200>, 2984 <0 0x0ae94600 0 0x280>, 2985 <0 0x0ae94900 0 0x260>; 2986 reg-names = "dsi_phy", 2987 "dsi_phy_lane", 2988 "dsi_pll"; 2989 2990 #clock-cells = <1>; 2991 #phy-cells = <0>; 2992 2993 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2994 <&rpmhcc RPMH_CXO_CLK>; 2995 clock-names = "iface", "ref"; 2996 2997 status = "disabled"; 2998 }; 2999 3000 mdss_dsi1: dsi@ae96000 { 3001 compatible = "qcom,mdss-dsi-ctrl"; 3002 reg = <0 0x0ae96000 0 0x400>; 3003 reg-names = "dsi_ctrl"; 3004 3005 interrupt-parent = <&mdss>; 3006 interrupts = <5>; 3007 3008 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3009 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3010 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3011 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3012 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3013 <&gcc GCC_DISP_HF_AXI_CLK>; 3014 clock-names = "byte", 3015 "byte_intf", 3016 "pixel", 3017 "core", 3018 "iface", 3019 "bus"; 3020 3021 operating-points-v2 = <&dsi_opp_table>; 3022 power-domains = <&rpmhpd SC8180X_MMCX>; 3023 3024 phys = <&mdss_dsi1_phy>; 3025 phy-names = "dsi"; 3026 3027 status = "disabled"; 3028 3029 ports { 3030 #address-cells = <1>; 3031 #size-cells = <0>; 3032 3033 port@0 { 3034 reg = <0>; 3035 mdss_dsi1_in: endpoint { 3036 remote-endpoint = <&dpu_intf2_out>; 3037 }; 3038 }; 3039 3040 port@1 { 3041 reg = <1>; 3042 mdss_dsi1_out: endpoint { 3043 }; 3044 }; 3045 }; 3046 }; 3047 3048 mdss_dsi1_phy: dsi-phy@ae96400 { 3049 compatible = "qcom,dsi-phy-7nm"; 3050 reg = <0 0x0ae96400 0 0x200>, 3051 <0 0x0ae96600 0 0x280>, 3052 <0 0x0ae96900 0 0x260>; 3053 reg-names = "dsi_phy", 3054 "dsi_phy_lane", 3055 "dsi_pll"; 3056 3057 #clock-cells = <1>; 3058 #phy-cells = <0>; 3059 3060 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3061 <&rpmhcc RPMH_CXO_CLK>; 3062 clock-names = "iface", "ref"; 3063 3064 status = "disabled"; 3065 }; 3066 3067 mdss_dp0: displayport-controller@ae90000 { 3068 compatible = "qcom,sc8180x-dp"; 3069 reg = <0 0xae90000 0 0x200>, 3070 <0 0xae90200 0 0x200>, 3071 <0 0xae90400 0 0x600>, 3072 <0 0xae90a00 0 0x400>, 3073 <0 0xae91000 0 0x400>; 3074 interrupt-parent = <&mdss>; 3075 interrupts = <12>; 3076 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3077 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 3078 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 3079 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 3080 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 3081 clock-names = "core_iface", 3082 "core_aux", 3083 "ctrl_link", 3084 "ctrl_link_iface", 3085 "stream_pixel"; 3086 3087 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 3088 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 3089 assigned-clock-parents = <&usb_prim_dpphy 0>, <&usb_prim_dpphy 1>; 3090 3091 phys = <&usb_prim_dpphy>; 3092 phy-names = "dp"; 3093 3094 #sound-dai-cells = <0>; 3095 3096 operating-points-v2 = <&dp0_opp_table>; 3097 power-domains = <&rpmhpd SC8180X_MMCX>; 3098 3099 status = "disabled"; 3100 3101 ports { 3102 #address-cells = <1>; 3103 #size-cells = <0>; 3104 3105 port@0 { 3106 reg = <0>; 3107 dp0_in: endpoint { 3108 remote-endpoint = <&dpu_intf0_out>; 3109 }; 3110 }; 3111 3112 port@1 { 3113 reg = <1>; 3114 mdss_dp0_out: endpoint { 3115 }; 3116 }; 3117 }; 3118 3119 dp0_opp_table: opp-table { 3120 compatible = "operating-points-v2"; 3121 3122 opp-160000000 { 3123 opp-hz = /bits/ 64 <160000000>; 3124 required-opps = <&rpmhpd_opp_low_svs>; 3125 }; 3126 3127 opp-270000000 { 3128 opp-hz = /bits/ 64 <270000000>; 3129 required-opps = <&rpmhpd_opp_svs>; 3130 }; 3131 3132 opp-540000000 { 3133 opp-hz = /bits/ 64 <540000000>; 3134 required-opps = <&rpmhpd_opp_svs_l1>; 3135 }; 3136 3137 opp-810000000 { 3138 opp-hz = /bits/ 64 <810000000>; 3139 required-opps = <&rpmhpd_opp_nom>; 3140 }; 3141 }; 3142 }; 3143 3144 mdss_dp1: displayport-controller@ae98000 { 3145 compatible = "qcom,sc8180x-dp"; 3146 reg = <0 0xae98000 0 0x200>, 3147 <0 0xae98200 0 0x200>, 3148 <0 0xae98400 0 0x600>, 3149 <0 0xae98a00 0 0x400>, 3150 <0 0xae99000 0 0x400>; 3151 interrupt-parent = <&mdss>; 3152 interrupts = <13>; 3153 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3154 <&dispcc DISP_CC_MDSS_DP_AUX1_CLK>, 3155 <&dispcc DISP_CC_MDSS_DP_LINK1_CLK>, 3156 <&dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>, 3157 <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>; 3158 clock-names = "core_iface", 3159 "core_aux", 3160 "ctrl_link", 3161 "ctrl_link_iface", 3162 "stream_pixel"; 3163 3164 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>, 3165 <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>; 3166 assigned-clock-parents = <&usb_sec_dpphy 0>, <&usb_sec_dpphy 1>; 3167 3168 phys = <&usb_sec_dpphy>; 3169 phy-names = "dp"; 3170 3171 #sound-dai-cells = <0>; 3172 3173 operating-points-v2 = <&dp0_opp_table>; 3174 power-domains = <&rpmhpd SC8180X_MMCX>; 3175 3176 status = "disabled"; 3177 3178 ports { 3179 #address-cells = <1>; 3180 #size-cells = <0>; 3181 3182 port@0 { 3183 reg = <0>; 3184 dp1_in: endpoint { 3185 remote-endpoint = <&dpu_intf4_out>; 3186 }; 3187 }; 3188 3189 port@1 { 3190 reg = <1>; 3191 mdss_dp1_out: endpoint { 3192 }; 3193 }; 3194 }; 3195 3196 dp1_opp_table: opp-table { 3197 compatible = "operating-points-v2"; 3198 3199 opp-160000000 { 3200 opp-hz = /bits/ 64 <160000000>; 3201 required-opps = <&rpmhpd_opp_low_svs>; 3202 }; 3203 3204 opp-270000000 { 3205 opp-hz = /bits/ 64 <270000000>; 3206 required-opps = <&rpmhpd_opp_svs>; 3207 }; 3208 3209 opp-540000000 { 3210 opp-hz = /bits/ 64 <540000000>; 3211 required-opps = <&rpmhpd_opp_svs_l1>; 3212 }; 3213 3214 opp-810000000 { 3215 opp-hz = /bits/ 64 <810000000>; 3216 required-opps = <&rpmhpd_opp_nom>; 3217 }; 3218 }; 3219 }; 3220 3221 mdss_edp: displayport-controller@ae9a000 { 3222 compatible = "qcom,sc8180x-edp"; 3223 reg = <0 0xae9a000 0 0x200>, 3224 <0 0xae9a200 0 0x200>, 3225 <0 0xae9a400 0 0x600>, 3226 <0 0xae9aa00 0 0x400>; 3227 interrupt-parent = <&mdss>; 3228 interrupts = <14>; 3229 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3230 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3231 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 3232 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 3233 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 3234 clock-names = "core_iface", 3235 "core_aux", 3236 "ctrl_link", 3237 "ctrl_link_iface", 3238 "stream_pixel"; 3239 3240 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 3241 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 3242 assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>; 3243 3244 phys = <&edp_phy>; 3245 phy-names = "dp"; 3246 3247 operating-points-v2 = <&edp_opp_table>; 3248 power-domains = <&rpmhpd SC8180X_MMCX>; 3249 3250 status = "disabled"; 3251 3252 ports { 3253 #address-cells = <1>; 3254 #size-cells = <0>; 3255 3256 port@0 { 3257 reg = <0>; 3258 edp_in: endpoint { 3259 remote-endpoint = <&dpu_intf5_out>; 3260 }; 3261 }; 3262 }; 3263 3264 edp_opp_table: opp-table { 3265 compatible = "operating-points-v2"; 3266 3267 opp-160000000 { 3268 opp-hz = /bits/ 64 <160000000>; 3269 required-opps = <&rpmhpd_opp_low_svs>; 3270 }; 3271 3272 opp-270000000 { 3273 opp-hz = /bits/ 64 <270000000>; 3274 required-opps = <&rpmhpd_opp_svs>; 3275 }; 3276 3277 opp-540000000 { 3278 opp-hz = /bits/ 64 <540000000>; 3279 required-opps = <&rpmhpd_opp_svs_l1>; 3280 }; 3281 3282 opp-810000000 { 3283 opp-hz = /bits/ 64 <810000000>; 3284 required-opps = <&rpmhpd_opp_nom>; 3285 }; 3286 }; 3287 }; 3288 }; 3289 3290 edp_phy: phy@aec2a00 { 3291 compatible = "qcom,sc8180x-edp-phy"; 3292 reg = <0 0x0aec2a00 0 0x1c0>, 3293 <0 0x0aec2200 0 0xa0>, 3294 <0 0x0aec2600 0 0xa0>, 3295 <0 0x0aec2000 0 0x19c>; 3296 3297 clocks = <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3298 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3299 clock-names = "aux", "cfg_ahb"; 3300 3301 power-domains = <&rpmhpd SC8180X_MX>; 3302 3303 #clock-cells = <1>; 3304 #phy-cells = <0>; 3305 }; 3306 3307 dispcc: clock-controller@af00000 { 3308 compatible = "qcom,sc8180x-dispcc"; 3309 reg = <0 0x0af00000 0 0x20000>; 3310 clocks = <&rpmhcc RPMH_CXO_CLK>, 3311 <&sleep_clk>, 3312 <&usb_prim_dpphy 0>, 3313 <&usb_prim_dpphy 1>, 3314 <&usb_sec_dpphy 0>, 3315 <&usb_sec_dpphy 1>, 3316 <&edp_phy 0>, 3317 <&edp_phy 1>; 3318 clock-names = "bi_tcxo", 3319 "sleep_clk", 3320 "dp_phy_pll_link_clk", 3321 "dp_phy_pll_vco_div_clk", 3322 "dptx1_phy_pll_link_clk", 3323 "dptx1_phy_pll_vco_div_clk", 3324 "edp_phy_pll_link_clk", 3325 "edp_phy_pll_vco_div_clk"; 3326 power-domains = <&rpmhpd SC8180X_MMCX>; 3327 required-opps = <&rpmhpd_opp_low_svs>; 3328 #clock-cells = <1>; 3329 #reset-cells = <1>; 3330 #power-domain-cells = <1>; 3331 }; 3332 3333 pdc: interrupt-controller@b220000 { 3334 compatible = "qcom,sc8180x-pdc", "qcom,pdc"; 3335 reg = <0 0x0b220000 0 0x30000>; 3336 qcom,pdc-ranges = <0 480 94>, <94 609 31>; 3337 #interrupt-cells = <2>; 3338 interrupt-parent = <&intc>; 3339 interrupt-controller; 3340 }; 3341 3342 tsens0: thermal-sensor@c263000 { 3343 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2"; 3344 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3345 <0 0x0c222000 0 0x1ff>; /* SROT */ 3346 #qcom,sensors = <16>; 3347 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3348 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3349 interrupt-names = "uplow", "critical"; 3350 #thermal-sensor-cells = <1>; 3351 }; 3352 3353 tsens1: thermal-sensor@c265000 { 3354 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2"; 3355 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3356 <0 0x0c223000 0 0x1ff>; /* SROT */ 3357 #qcom,sensors = <9>; 3358 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3359 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3360 interrupt-names = "uplow", "critical"; 3361 #thermal-sensor-cells = <1>; 3362 }; 3363 3364 aoss_qmp: power-controller@c300000 { 3365 compatible = "qcom,sc8180x-aoss-qmp", "qcom,aoss-qmp"; 3366 reg = <0x0 0x0c300000 0x0 0x400>; 3367 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3368 mboxes = <&apss_shared 0>; 3369 3370 #clock-cells = <0>; 3371 #power-domain-cells = <1>; 3372 }; 3373 3374 sram@c3f0000 { 3375 compatible = "qcom,rpmh-stats"; 3376 reg = <0x0 0x0c3f0000 0x0 0x400>; 3377 }; 3378 3379 spmi_bus: spmi@c440000 { 3380 compatible = "qcom,spmi-pmic-arb"; 3381 reg = <0x0 0x0c440000 0x0 0x0001100>, 3382 <0x0 0x0c600000 0x0 0x2000000>, 3383 <0x0 0x0e600000 0x0 0x0100000>, 3384 <0x0 0x0e700000 0x0 0x00a0000>, 3385 <0x0 0x0c40a000 0x0 0x0026000>; 3386 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3387 interrupt-names = "periph_irq"; 3388 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3389 qcom,ee = <0>; 3390 qcom,channel = <0>; 3391 #address-cells = <2>; 3392 #size-cells = <0>; 3393 interrupt-controller; 3394 #interrupt-cells = <4>; 3395 }; 3396 3397 apps_smmu: iommu@15000000 { 3398 compatible = "qcom,sc8180x-smmu-500", "arm,mmu-500"; 3399 reg = <0 0x15000000 0 0x100000>; 3400 #iommu-cells = <2>; 3401 #global-interrupts = <1>; 3402 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3403 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3404 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3405 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3406 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3407 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3408 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3409 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3410 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3411 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3412 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3413 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3414 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3415 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3416 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3417 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3418 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3419 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3420 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3421 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3422 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3423 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3424 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3425 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3426 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3427 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3428 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3429 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3430 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3431 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3432 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3433 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3434 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3435 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3436 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3437 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3438 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3439 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3440 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3441 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3442 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3443 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3444 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3445 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3446 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3447 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3448 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3449 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3450 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3451 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3452 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3453 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3454 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3455 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3456 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3457 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3458 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3459 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3460 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3461 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3462 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3463 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3464 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3465 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3466 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3467 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3468 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3469 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3470 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3471 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3472 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3473 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3474 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3475 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3476 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3477 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3478 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3479 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3480 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3481 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3482 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3483 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3484 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3485 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3486 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 3487 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 3488 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 3489 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 3490 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 3491 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 3492 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 3493 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 3494 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 3495 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 3496 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 3497 <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>, 3498 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>, 3499 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 3500 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>, 3501 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, 3502 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 3503 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, 3504 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>, 3505 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 3506 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 3507 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 3508 <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>; 3509 3510 }; 3511 3512 remoteproc_adsp: remoteproc@17300000 { 3513 compatible = "qcom,sc8180x-adsp-pas"; 3514 reg = <0x0 0x17300000 0x0 0x4040>; 3515 3516 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 3517 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3518 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3519 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3520 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3521 interrupt-names = "wdog", "fatal", "ready", 3522 "handover", "stop-ack"; 3523 3524 clocks = <&rpmhcc RPMH_CXO_CLK>; 3525 clock-names = "xo"; 3526 3527 power-domains = <&rpmhpd SC8180X_CX>; 3528 power-domain-names = "cx"; 3529 3530 qcom,qmp = <&aoss_qmp>; 3531 3532 qcom,smem-states = <&adsp_smp2p_out 0>; 3533 qcom,smem-state-names = "stop"; 3534 3535 status = "disabled"; 3536 3537 remoteproc_adsp_glink: glink-edge { 3538 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3539 label = "lpass"; 3540 qcom,remote-pid = <2>; 3541 mboxes = <&apss_shared 8>; 3542 }; 3543 }; 3544 3545 intc: interrupt-controller@17a00000 { 3546 compatible = "arm,gic-v3"; 3547 interrupt-controller; 3548 #interrupt-cells = <3>; 3549 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3550 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3551 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3552 #redistributor-regions = <1>; 3553 redistributor-stride = <0 0x20000>; 3554 }; 3555 3556 apss_shared: mailbox@17c00000 { 3557 compatible = "qcom,sc8180x-apss-shared", "qcom,sdm845-apss-shared"; 3558 reg = <0x0 0x17c00000 0x0 0x1000>; 3559 #mbox-cells = <1>; 3560 }; 3561 3562 timer@17c20000 { 3563 compatible = "arm,armv7-timer-mem"; 3564 reg = <0x0 0x17c20000 0x0 0x1000>; 3565 3566 #address-cells = <1>; 3567 #size-cells = <1>; 3568 ranges = <0 0 0 0x20000000>; 3569 3570 frame@17c21000 { 3571 reg = <0x17c21000 0x1000>, 3572 <0x17c22000 0x1000>; 3573 frame-number = <0>; 3574 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3575 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3576 }; 3577 3578 frame@17c23000 { 3579 reg = <0x17c23000 0x1000>; 3580 frame-number = <1>; 3581 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3582 status = "disabled"; 3583 }; 3584 3585 frame@17c25000 { 3586 reg = <0x17c25000 0x1000>; 3587 frame-number = <2>; 3588 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3589 status = "disabled"; 3590 }; 3591 3592 frame@17c27000 { 3593 reg = <0x17c26000 0x1000>; 3594 frame-number = <3>; 3595 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3596 status = "disabled"; 3597 }; 3598 3599 frame@17c29000 { 3600 reg = <0x17c29000 0x1000>; 3601 frame-number = <4>; 3602 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3603 status = "disabled"; 3604 }; 3605 3606 frame@17c2b000 { 3607 reg = <0x17c2b000 0x1000>; 3608 frame-number = <5>; 3609 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3610 status = "disabled"; 3611 }; 3612 3613 frame@17c2d000 { 3614 reg = <0x17c2d000 0x1000>; 3615 frame-number = <6>; 3616 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3617 status = "disabled"; 3618 }; 3619 }; 3620 3621 apps_rsc: rsc@18200000 { 3622 compatible = "qcom,rpmh-rsc"; 3623 reg = <0x0 0x18200000 0x0 0x10000>, 3624 <0x0 0x18210000 0x0 0x10000>, 3625 <0x0 0x18220000 0x0 0x10000>; 3626 reg-names = "drv-0", "drv-1", "drv-2"; 3627 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3628 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3629 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3630 qcom,tcs-offset = <0xd00>; 3631 qcom,drv-id = <2>; 3632 qcom,tcs-config = <ACTIVE_TCS 2>, 3633 <SLEEP_TCS 1>, 3634 <WAKE_TCS 1>, 3635 <CONTROL_TCS 0>; 3636 label = "apps_rsc"; 3637 power-domains = <&CLUSTER_PD>; 3638 3639 apps_bcm_voter: bcm-voter { 3640 compatible = "qcom,bcm-voter"; 3641 }; 3642 3643 rpmhcc: clock-controller { 3644 compatible = "qcom,sc8180x-rpmh-clk"; 3645 #clock-cells = <1>; 3646 clock-names = "xo"; 3647 clocks = <&xo_board_clk>; 3648 }; 3649 3650 rpmhpd: power-controller { 3651 compatible = "qcom,sc8180x-rpmhpd"; 3652 #power-domain-cells = <1>; 3653 operating-points-v2 = <&rpmhpd_opp_table>; 3654 3655 rpmhpd_opp_table: opp-table { 3656 compatible = "operating-points-v2"; 3657 3658 rpmhpd_opp_ret: opp1 { 3659 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3660 }; 3661 3662 rpmhpd_opp_min_svs: opp2 { 3663 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3664 }; 3665 3666 rpmhpd_opp_low_svs: opp3 { 3667 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3668 }; 3669 3670 rpmhpd_opp_svs: opp4 { 3671 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3672 }; 3673 3674 rpmhpd_opp_svs_l1: opp5 { 3675 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3676 }; 3677 3678 rpmhpd_opp_nom: opp6 { 3679 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3680 }; 3681 3682 rpmhpd_opp_nom_l1: opp7 { 3683 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3684 }; 3685 3686 rpmhpd_opp_nom_l2: opp8 { 3687 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3688 }; 3689 3690 rpmhpd_opp_turbo: opp9 { 3691 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3692 }; 3693 3694 rpmhpd_opp_turbo_l1: opp10 { 3695 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3696 }; 3697 }; 3698 }; 3699 }; 3700 3701 osm_l3: interconnect@18321000 { 3702 compatible = "qcom,sc8180x-osm-l3", "qcom,osm-l3"; 3703 reg = <0 0x18321000 0 0x1400>; 3704 3705 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3706 clock-names = "xo", "alternate"; 3707 3708 #interconnect-cells = <1>; 3709 }; 3710 3711 lmh@18350800 { 3712 compatible = "qcom,sc8180x-lmh"; 3713 reg = <0 0x18350800 0 0x400>; 3714 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3715 cpus = <&CPU4>; 3716 qcom,lmh-temp-arm-millicelsius = <65000>; 3717 qcom,lmh-temp-low-millicelsius = <94500>; 3718 qcom,lmh-temp-high-millicelsius = <95000>; 3719 interrupt-controller; 3720 #interrupt-cells = <1>; 3721 }; 3722 3723 lmh@18358800 { 3724 compatible = "qcom,sc8180x-lmh"; 3725 reg = <0 0x18358800 0 0x400>; 3726 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3727 cpus = <&CPU0>; 3728 qcom,lmh-temp-arm-millicelsius = <65000>; 3729 qcom,lmh-temp-low-millicelsius = <94500>; 3730 qcom,lmh-temp-high-millicelsius = <95000>; 3731 interrupt-controller; 3732 #interrupt-cells = <1>; 3733 }; 3734 3735 cpufreq_hw: cpufreq@18323000 { 3736 compatible = "qcom,cpufreq-hw"; 3737 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 3738 reg-names = "freq-domain0", "freq-domain1"; 3739 3740 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3741 clock-names = "xo", "alternate"; 3742 3743 #freq-domain-cells = <1>; 3744 #clock-cells = <1>; 3745 }; 3746 3747 wifi: wifi@18800000 { 3748 compatible = "qcom,wcn3990-wifi"; 3749 reg = <0 0x18800000 0 0x800000>; 3750 reg-names = "membase"; 3751 clock-names = "cxo_ref_clk_pin"; 3752 clocks = <&rpmhcc RPMH_RF_CLK2>; 3753 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 3754 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 3755 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 3756 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 3757 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3758 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3759 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 3760 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3761 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3762 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3763 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3764 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 3765 iommus = <&apps_smmu 0x0640 0x1>; 3766 qcom,msa-fixed-perm; 3767 status = "disabled"; 3768 }; 3769 }; 3770 3771 thermal-zones { 3772 cpu0-thermal { 3773 polling-delay-passive = <250>; 3774 polling-delay = <1000>; 3775 3776 thermal-sensors = <&tsens0 1>; 3777 3778 trips { 3779 cpu-crit { 3780 temperature = <110000>; 3781 hysteresis = <1000>; 3782 type = "critical"; 3783 }; 3784 }; 3785 }; 3786 3787 cpu1-thermal { 3788 polling-delay-passive = <250>; 3789 polling-delay = <1000>; 3790 3791 thermal-sensors = <&tsens0 2>; 3792 3793 trips { 3794 cpu-crit { 3795 temperature = <110000>; 3796 hysteresis = <1000>; 3797 type = "critical"; 3798 }; 3799 }; 3800 }; 3801 3802 cpu2-thermal { 3803 polling-delay-passive = <250>; 3804 polling-delay = <1000>; 3805 3806 thermal-sensors = <&tsens0 3>; 3807 3808 trips { 3809 cpu-crit { 3810 temperature = <110000>; 3811 hysteresis = <1000>; 3812 type = "critical"; 3813 }; 3814 }; 3815 }; 3816 3817 cpu3-thermal { 3818 polling-delay-passive = <250>; 3819 polling-delay = <1000>; 3820 3821 thermal-sensors = <&tsens0 4>; 3822 3823 trips { 3824 cpu-crit { 3825 temperature = <110000>; 3826 hysteresis = <1000>; 3827 type = "critical"; 3828 }; 3829 }; 3830 }; 3831 3832 cpu4-top-thermal { 3833 polling-delay-passive = <250>; 3834 polling-delay = <1000>; 3835 3836 thermal-sensors = <&tsens0 7>; 3837 3838 trips { 3839 cpu-crit { 3840 temperature = <110000>; 3841 hysteresis = <1000>; 3842 type = "critical"; 3843 }; 3844 }; 3845 }; 3846 3847 cpu5-top-thermal { 3848 polling-delay-passive = <250>; 3849 polling-delay = <1000>; 3850 3851 thermal-sensors = <&tsens0 8>; 3852 3853 trips { 3854 cpu-crit { 3855 temperature = <110000>; 3856 hysteresis = <1000>; 3857 type = "critical"; 3858 }; 3859 }; 3860 }; 3861 3862 cpu6-top-thermal { 3863 polling-delay-passive = <250>; 3864 polling-delay = <1000>; 3865 3866 thermal-sensors = <&tsens0 9>; 3867 3868 trips { 3869 cpu-crit { 3870 temperature = <110000>; 3871 hysteresis = <1000>; 3872 type = "critical"; 3873 }; 3874 }; 3875 }; 3876 3877 cpu7-top-thermal { 3878 polling-delay-passive = <250>; 3879 polling-delay = <1000>; 3880 3881 thermal-sensors = <&tsens0 10>; 3882 3883 trips { 3884 cpu-crit { 3885 temperature = <110000>; 3886 hysteresis = <1000>; 3887 type = "critical"; 3888 }; 3889 }; 3890 }; 3891 3892 cpu4-bottom-thermal { 3893 polling-delay-passive = <250>; 3894 polling-delay = <1000>; 3895 3896 thermal-sensors = <&tsens0 11>; 3897 3898 trips { 3899 cpu-crit { 3900 temperature = <110000>; 3901 hysteresis = <1000>; 3902 type = "critical"; 3903 }; 3904 }; 3905 }; 3906 3907 cpu5-bottom-thermal { 3908 polling-delay-passive = <250>; 3909 polling-delay = <1000>; 3910 3911 thermal-sensors = <&tsens0 12>; 3912 3913 trips { 3914 cpu-crit { 3915 temperature = <110000>; 3916 hysteresis = <1000>; 3917 type = "critical"; 3918 }; 3919 }; 3920 }; 3921 3922 cpu6-bottom-thermal { 3923 polling-delay-passive = <250>; 3924 polling-delay = <1000>; 3925 3926 thermal-sensors = <&tsens0 13>; 3927 3928 trips { 3929 cpu-crit { 3930 temperature = <110000>; 3931 hysteresis = <1000>; 3932 type = "critical"; 3933 }; 3934 }; 3935 }; 3936 3937 cpu7-bottom-thermal { 3938 polling-delay-passive = <250>; 3939 polling-delay = <1000>; 3940 3941 thermal-sensors = <&tsens0 14>; 3942 3943 trips { 3944 cpu-crit { 3945 temperature = <110000>; 3946 hysteresis = <1000>; 3947 type = "critical"; 3948 }; 3949 }; 3950 }; 3951 3952 aoss0-thermal { 3953 polling-delay-passive = <250>; 3954 polling-delay = <1000>; 3955 3956 thermal-sensors = <&tsens0 0>; 3957 3958 trips { 3959 trip-point0 { 3960 temperature = <90000>; 3961 hysteresis = <2000>; 3962 type = "hot"; 3963 }; 3964 }; 3965 }; 3966 3967 cluster0-thermal { 3968 polling-delay-passive = <250>; 3969 polling-delay = <1000>; 3970 3971 thermal-sensors = <&tsens0 5>; 3972 3973 trips { 3974 cluster-crit { 3975 temperature = <110000>; 3976 hysteresis = <2000>; 3977 type = "critical"; 3978 }; 3979 }; 3980 }; 3981 3982 cluster1-thermal { 3983 polling-delay-passive = <250>; 3984 polling-delay = <1000>; 3985 3986 thermal-sensors = <&tsens0 6>; 3987 3988 trips { 3989 cluster-crit { 3990 temperature = <110000>; 3991 hysteresis = <2000>; 3992 type = "critical"; 3993 }; 3994 }; 3995 }; 3996 3997 gpu-top-thermal { 3998 polling-delay-passive = <250>; 3999 polling-delay = <1000>; 4000 4001 thermal-sensors = <&tsens0 15>; 4002 4003 cooling-maps { 4004 map0 { 4005 trip = <&gpu_top_alert0>; 4006 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4007 }; 4008 }; 4009 4010 trips { 4011 gpu_top_alert0: trip-point0 { 4012 temperature = <90000>; 4013 hysteresis = <2000>; 4014 type = "hot"; 4015 }; 4016 }; 4017 }; 4018 4019 aoss1-thermal { 4020 polling-delay-passive = <250>; 4021 polling-delay = <1000>; 4022 4023 thermal-sensors = <&tsens1 0>; 4024 4025 trips { 4026 trip-point0 { 4027 temperature = <90000>; 4028 hysteresis = <2000>; 4029 type = "hot"; 4030 }; 4031 }; 4032 }; 4033 4034 wlan-thermal { 4035 polling-delay-passive = <250>; 4036 polling-delay = <1000>; 4037 4038 thermal-sensors = <&tsens1 1>; 4039 4040 trips { 4041 trip-point0 { 4042 temperature = <90000>; 4043 hysteresis = <2000>; 4044 type = "hot"; 4045 }; 4046 }; 4047 }; 4048 4049 video-thermal { 4050 polling-delay-passive = <250>; 4051 polling-delay = <1000>; 4052 4053 thermal-sensors = <&tsens1 2>; 4054 4055 trips { 4056 trip-point0 { 4057 temperature = <90000>; 4058 hysteresis = <2000>; 4059 type = "hot"; 4060 }; 4061 }; 4062 }; 4063 4064 mem-thermal { 4065 polling-delay-passive = <250>; 4066 polling-delay = <1000>; 4067 4068 thermal-sensors = <&tsens1 3>; 4069 4070 trips { 4071 trip-point0 { 4072 temperature = <90000>; 4073 hysteresis = <2000>; 4074 type = "hot"; 4075 }; 4076 }; 4077 }; 4078 4079 q6-hvx-thermal { 4080 polling-delay-passive = <250>; 4081 polling-delay = <1000>; 4082 4083 thermal-sensors = <&tsens1 4>; 4084 4085 trips { 4086 trip-point0 { 4087 temperature = <90000>; 4088 hysteresis = <2000>; 4089 type = "hot"; 4090 }; 4091 }; 4092 }; 4093 4094 camera-thermal { 4095 polling-delay-passive = <250>; 4096 polling-delay = <1000>; 4097 4098 thermal-sensors = <&tsens1 5>; 4099 4100 trips { 4101 trip-point0 { 4102 temperature = <90000>; 4103 hysteresis = <2000>; 4104 type = "hot"; 4105 }; 4106 }; 4107 }; 4108 4109 compute-thermal { 4110 polling-delay-passive = <250>; 4111 polling-delay = <1000>; 4112 4113 thermal-sensors = <&tsens1 6>; 4114 4115 trips { 4116 trip-point0 { 4117 temperature = <90000>; 4118 hysteresis = <2000>; 4119 type = "hot"; 4120 }; 4121 }; 4122 }; 4123 4124 mdm-dsp-thermal { 4125 polling-delay-passive = <250>; 4126 polling-delay = <1000>; 4127 4128 thermal-sensors = <&tsens1 7>; 4129 4130 trips { 4131 trip-point0 { 4132 temperature = <90000>; 4133 hysteresis = <2000>; 4134 type = "hot"; 4135 }; 4136 }; 4137 }; 4138 4139 npu-thermal { 4140 polling-delay-passive = <250>; 4141 polling-delay = <1000>; 4142 4143 thermal-sensors = <&tsens1 8>; 4144 4145 trips { 4146 trip-point0 { 4147 temperature = <90000>; 4148 hysteresis = <2000>; 4149 type = "hot"; 4150 }; 4151 }; 4152 }; 4153 4154 gpu-bottom-thermal { 4155 polling-delay-passive = <250>; 4156 polling-delay = <1000>; 4157 4158 thermal-sensors = <&tsens1 11>; 4159 4160 cooling-maps { 4161 map0 { 4162 trip = <&gpu_bottom_alert0>; 4163 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4164 }; 4165 }; 4166 4167 trips { 4168 gpu_bottom_alert0: trip-point0 { 4169 temperature = <90000>; 4170 hysteresis = <2000>; 4171 type = "hot"; 4172 }; 4173 }; 4174 }; 4175 }; 4176 4177 timer { 4178 compatible = "arm,armv8-timer"; 4179 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4180 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4181 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4182 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4183 }; 4184}; 4185