1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2020-2023, Linaro Limited 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,gcc-sc8180x.h> 9#include <dt-bindings/clock/qcom,gpucc-sm8150.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/interconnect/qcom,osm-l3.h> 12#include <dt-bindings/interconnect/qcom,sc8180x.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15#include <dt-bindings/soc/qcom,rpmh-rsc.h> 16#include <dt-bindings/thermal/thermal.h> 17 18/ { 19 interrupt-parent = <&intc>; 20 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 clocks { 25 xo_board_clk: xo-board { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <38400000>; 29 }; 30 31 sleep_clk: sleep-clk { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <32764>; 35 clock-output-names = "sleep_clk"; 36 }; 37 }; 38 39 cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 CPU0: cpu@0 { 44 device_type = "cpu"; 45 compatible = "qcom,kryo485"; 46 reg = <0x0 0x0>; 47 enable-method = "psci"; 48 capacity-dmips-mhz = <602>; 49 next-level-cache = <&L2_0>; 50 qcom,freq-domain = <&cpufreq_hw 0>; 51 operating-points-v2 = <&cpu0_opp_table>; 52 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 53 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 54 power-domains = <&CPU_PD0>; 55 power-domain-names = "psci"; 56 #cooling-cells = <2>; 57 clocks = <&cpufreq_hw 0>; 58 59 L2_0: l2-cache { 60 compatible = "cache"; 61 cache-level = <2>; 62 cache-unified; 63 next-level-cache = <&L3_0>; 64 L3_0: l3-cache { 65 compatible = "cache"; 66 cache-level = <3>; 67 cache-unified; 68 }; 69 }; 70 }; 71 72 CPU1: cpu@100 { 73 device_type = "cpu"; 74 compatible = "qcom,kryo485"; 75 reg = <0x0 0x100>; 76 enable-method = "psci"; 77 capacity-dmips-mhz = <602>; 78 next-level-cache = <&L2_100>; 79 qcom,freq-domain = <&cpufreq_hw 0>; 80 operating-points-v2 = <&cpu0_opp_table>; 81 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 82 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 83 power-domains = <&CPU_PD1>; 84 power-domain-names = "psci"; 85 #cooling-cells = <2>; 86 clocks = <&cpufreq_hw 0>; 87 88 L2_100: l2-cache { 89 compatible = "cache"; 90 cache-level = <2>; 91 cache-unified; 92 next-level-cache = <&L3_0>; 93 }; 94 95 }; 96 97 CPU2: cpu@200 { 98 device_type = "cpu"; 99 compatible = "qcom,kryo485"; 100 reg = <0x0 0x200>; 101 enable-method = "psci"; 102 capacity-dmips-mhz = <602>; 103 next-level-cache = <&L2_200>; 104 qcom,freq-domain = <&cpufreq_hw 0>; 105 operating-points-v2 = <&cpu0_opp_table>; 106 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 107 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 108 power-domains = <&CPU_PD2>; 109 power-domain-names = "psci"; 110 #cooling-cells = <2>; 111 clocks = <&cpufreq_hw 0>; 112 113 L2_200: l2-cache { 114 compatible = "cache"; 115 cache-level = <2>; 116 cache-unified; 117 next-level-cache = <&L3_0>; 118 }; 119 }; 120 121 CPU3: cpu@300 { 122 device_type = "cpu"; 123 compatible = "qcom,kryo485"; 124 reg = <0x0 0x300>; 125 enable-method = "psci"; 126 capacity-dmips-mhz = <602>; 127 next-level-cache = <&L2_300>; 128 qcom,freq-domain = <&cpufreq_hw 0>; 129 operating-points-v2 = <&cpu0_opp_table>; 130 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 131 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 132 power-domains = <&CPU_PD3>; 133 power-domain-names = "psci"; 134 #cooling-cells = <2>; 135 clocks = <&cpufreq_hw 0>; 136 137 L2_300: l2-cache { 138 compatible = "cache"; 139 cache-unified; 140 cache-level = <2>; 141 next-level-cache = <&L3_0>; 142 }; 143 }; 144 145 CPU4: cpu@400 { 146 device_type = "cpu"; 147 compatible = "qcom,kryo485"; 148 reg = <0x0 0x400>; 149 enable-method = "psci"; 150 capacity-dmips-mhz = <1024>; 151 next-level-cache = <&L2_400>; 152 qcom,freq-domain = <&cpufreq_hw 1>; 153 operating-points-v2 = <&cpu4_opp_table>; 154 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 155 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 156 power-domains = <&CPU_PD4>; 157 power-domain-names = "psci"; 158 #cooling-cells = <2>; 159 clocks = <&cpufreq_hw 1>; 160 161 L2_400: l2-cache { 162 compatible = "cache"; 163 cache-unified; 164 cache-level = <2>; 165 next-level-cache = <&L3_0>; 166 }; 167 }; 168 169 CPU5: cpu@500 { 170 device_type = "cpu"; 171 compatible = "qcom,kryo485"; 172 reg = <0x0 0x500>; 173 enable-method = "psci"; 174 capacity-dmips-mhz = <1024>; 175 next-level-cache = <&L2_500>; 176 qcom,freq-domain = <&cpufreq_hw 1>; 177 operating-points-v2 = <&cpu4_opp_table>; 178 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 179 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 180 power-domains = <&CPU_PD5>; 181 power-domain-names = "psci"; 182 #cooling-cells = <2>; 183 clocks = <&cpufreq_hw 1>; 184 185 L2_500: l2-cache { 186 compatible = "cache"; 187 cache-unified; 188 cache-level = <2>; 189 next-level-cache = <&L3_0>; 190 }; 191 }; 192 193 CPU6: cpu@600 { 194 device_type = "cpu"; 195 compatible = "qcom,kryo485"; 196 reg = <0x0 0x600>; 197 enable-method = "psci"; 198 capacity-dmips-mhz = <1024>; 199 next-level-cache = <&L2_600>; 200 qcom,freq-domain = <&cpufreq_hw 1>; 201 operating-points-v2 = <&cpu4_opp_table>; 202 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 203 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 204 power-domains = <&CPU_PD6>; 205 power-domain-names = "psci"; 206 #cooling-cells = <2>; 207 clocks = <&cpufreq_hw 1>; 208 209 L2_600: l2-cache { 210 compatible = "cache"; 211 cache-unified; 212 cache-level = <2>; 213 next-level-cache = <&L3_0>; 214 }; 215 }; 216 217 CPU7: cpu@700 { 218 device_type = "cpu"; 219 compatible = "qcom,kryo485"; 220 reg = <0x0 0x700>; 221 enable-method = "psci"; 222 capacity-dmips-mhz = <1024>; 223 next-level-cache = <&L2_700>; 224 qcom,freq-domain = <&cpufreq_hw 1>; 225 operating-points-v2 = <&cpu4_opp_table>; 226 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &mc_virt SLAVE_EBI_CH0 3>, 227 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 228 power-domains = <&CPU_PD7>; 229 power-domain-names = "psci"; 230 #cooling-cells = <2>; 231 clocks = <&cpufreq_hw 1>; 232 233 L2_700: l2-cache { 234 compatible = "cache"; 235 cache-unified; 236 cache-level = <2>; 237 next-level-cache = <&L3_0>; 238 }; 239 }; 240 241 cpu-map { 242 cluster0 { 243 core0 { 244 cpu = <&CPU0>; 245 }; 246 247 core1 { 248 cpu = <&CPU1>; 249 }; 250 251 core2 { 252 cpu = <&CPU2>; 253 }; 254 255 core3 { 256 cpu = <&CPU3>; 257 }; 258 259 core4 { 260 cpu = <&CPU4>; 261 }; 262 263 core5 { 264 cpu = <&CPU5>; 265 }; 266 267 core6 { 268 cpu = <&CPU6>; 269 }; 270 271 core7 { 272 cpu = <&CPU7>; 273 }; 274 }; 275 }; 276 277 idle-states { 278 entry-method = "psci"; 279 280 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 281 compatible = "arm,idle-state"; 282 arm,psci-suspend-param = <0x40000004>; 283 entry-latency-us = <355>; 284 exit-latency-us = <909>; 285 min-residency-us = <3934>; 286 local-timer-stop; 287 }; 288 289 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 290 compatible = "arm,idle-state"; 291 arm,psci-suspend-param = <0x40000004>; 292 entry-latency-us = <241>; 293 exit-latency-us = <1461>; 294 min-residency-us = <4488>; 295 local-timer-stop; 296 }; 297 }; 298 299 domain-idle-states { 300 CLUSTER_SLEEP_0: cluster-sleep-0 { 301 compatible = "domain-idle-state"; 302 arm,psci-suspend-param = <0x4100a344>; 303 entry-latency-us = <3263>; 304 exit-latency-us = <6562>; 305 min-residency-us = <9987>; 306 }; 307 }; 308 }; 309 310 cpu0_opp_table: opp-table-cpu0 { 311 compatible = "operating-points-v2"; 312 opp-shared; 313 314 opp-300000000 { 315 opp-hz = /bits/ 64 <300000000>; 316 opp-peak-kBps = <800000 9600000>; 317 }; 318 319 opp-422400000 { 320 opp-hz = /bits/ 64 <422400000>; 321 opp-peak-kBps = <800000 9600000>; 322 }; 323 324 opp-537600000 { 325 opp-hz = /bits/ 64 <537600000>; 326 opp-peak-kBps = <800000 12902400>; 327 }; 328 329 opp-652800000 { 330 opp-hz = /bits/ 64 <652800000>; 331 opp-peak-kBps = <800000 12902400>; 332 }; 333 334 opp-768000000 { 335 opp-hz = /bits/ 64 <768000000>; 336 opp-peak-kBps = <800000 15974400>; 337 }; 338 339 opp-883200000 { 340 opp-hz = /bits/ 64 <883200000>; 341 opp-peak-kBps = <1804000 19660800>; 342 }; 343 344 opp-998400000 { 345 opp-hz = /bits/ 64 <998400000>; 346 opp-peak-kBps = <1804000 19660800>; 347 }; 348 349 opp-1113600000 { 350 opp-hz = /bits/ 64 <1113600000>; 351 opp-peak-kBps = <1804000 22732800>; 352 }; 353 354 opp-1228800000 { 355 opp-hz = /bits/ 64 <1228800000>; 356 opp-peak-kBps = <1804000 22732800>; 357 }; 358 359 opp-1363200000 { 360 opp-hz = /bits/ 64 <1363200000>; 361 opp-peak-kBps = <2188000 25804800>; 362 }; 363 364 opp-1478400000 { 365 opp-hz = /bits/ 64 <1478400000>; 366 opp-peak-kBps = <2188000 31948800>; 367 }; 368 369 opp-1574400000 { 370 opp-hz = /bits/ 64 <1574400000>; 371 opp-peak-kBps = <3072000 31948800>; 372 }; 373 374 opp-1670400000 { 375 opp-hz = /bits/ 64 <1670400000>; 376 opp-peak-kBps = <3072000 31948800>; 377 }; 378 379 opp-1766400000 { 380 opp-hz = /bits/ 64 <1766400000>; 381 opp-peak-kBps = <3072000 31948800>; 382 }; 383 }; 384 385 cpu4_opp_table: opp-table-cpu4 { 386 compatible = "operating-points-v2"; 387 opp-shared; 388 389 opp-825600000 { 390 opp-hz = /bits/ 64 <825600000>; 391 opp-peak-kBps = <1804000 15974400>; 392 }; 393 394 opp-940800000 { 395 opp-hz = /bits/ 64 <940800000>; 396 opp-peak-kBps = <2188000 19660800>; 397 }; 398 399 opp-1056000000 { 400 opp-hz = /bits/ 64 <1056000000>; 401 opp-peak-kBps = <2188000 22732800>; 402 }; 403 404 opp-1171200000 { 405 opp-hz = /bits/ 64 <1171200000>; 406 opp-peak-kBps = <3072000 25804800>; 407 }; 408 409 opp-1286400000 { 410 opp-hz = /bits/ 64 <1286400000>; 411 opp-peak-kBps = <3072000 31948800>; 412 }; 413 414 opp-1420800000 { 415 opp-hz = /bits/ 64 <1420800000>; 416 opp-peak-kBps = <4068000 31948800>; 417 }; 418 419 opp-1536000000 { 420 opp-hz = /bits/ 64 <1536000000>; 421 opp-peak-kBps = <4068000 31948800>; 422 }; 423 424 opp-1651200000 { 425 opp-hz = /bits/ 64 <1651200000>; 426 opp-peak-kBps = <4068000 40550400>; 427 }; 428 429 opp-1766400000 { 430 opp-hz = /bits/ 64 <1766400000>; 431 opp-peak-kBps = <4068000 40550400>; 432 }; 433 434 opp-1881600000 { 435 opp-hz = /bits/ 64 <1881600000>; 436 opp-peak-kBps = <4068000 43008000>; 437 }; 438 439 opp-1996800000 { 440 opp-hz = /bits/ 64 <1996800000>; 441 opp-peak-kBps = <6220000 43008000>; 442 }; 443 444 opp-2131200000 { 445 opp-hz = /bits/ 64 <2131200000>; 446 opp-peak-kBps = <6220000 49152000>; 447 }; 448 449 opp-2246400000 { 450 opp-hz = /bits/ 64 <2246400000>; 451 opp-peak-kBps = <7216000 49152000>; 452 }; 453 454 opp-2361600000 { 455 opp-hz = /bits/ 64 <2361600000>; 456 opp-peak-kBps = <8368000 49152000>; 457 }; 458 459 opp-2457600000 { 460 opp-hz = /bits/ 64 <2457600000>; 461 opp-peak-kBps = <8368000 51609600>; 462 }; 463 464 opp-2553600000 { 465 opp-hz = /bits/ 64 <2553600000>; 466 opp-peak-kBps = <8368000 51609600>; 467 }; 468 469 opp-2649600000 { 470 opp-hz = /bits/ 64 <2649600000>; 471 opp-peak-kBps = <8368000 51609600>; 472 }; 473 474 opp-2745600000 { 475 opp-hz = /bits/ 64 <2745600000>; 476 opp-peak-kBps = <8368000 51609600>; 477 }; 478 479 opp-2841600000 { 480 opp-hz = /bits/ 64 <2841600000>; 481 opp-peak-kBps = <8368000 51609600>; 482 }; 483 484 opp-2918400000 { 485 opp-hz = /bits/ 64 <2918400000>; 486 opp-peak-kBps = <8368000 51609600>; 487 }; 488 489 opp-2995200000 { 490 opp-hz = /bits/ 64 <2995200000>; 491 opp-peak-kBps = <8368000 51609600>; 492 }; 493 }; 494 495 firmware { 496 scm: scm { 497 compatible = "qcom,scm-sc8180x", "qcom,scm"; 498 }; 499 }; 500 501 camnoc_virt: interconnect-camnoc-virt { 502 compatible = "qcom,sc8180x-camnoc-virt"; 503 #interconnect-cells = <2>; 504 qcom,bcm-voters = <&apps_bcm_voter>; 505 }; 506 507 mc_virt: interconnect-mc-virt { 508 compatible = "qcom,sc8180x-mc-virt"; 509 #interconnect-cells = <2>; 510 qcom,bcm-voters = <&apps_bcm_voter>; 511 }; 512 513 qup_virt: interconnect-qup-virt { 514 compatible = "qcom,sc8180x-qup-virt"; 515 #interconnect-cells = <2>; 516 qcom,bcm-voters = <&apps_bcm_voter>; 517 }; 518 519 memory@80000000 { 520 device_type = "memory"; 521 /* We expect the bootloader to fill in the size */ 522 reg = <0x0 0x80000000 0x0 0x0>; 523 }; 524 525 pmu { 526 compatible = "arm,armv8-pmuv3"; 527 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 528 }; 529 530 psci { 531 compatible = "arm,psci-1.0"; 532 method = "smc"; 533 534 CPU_PD0: power-domain-cpu0 { 535 #power-domain-cells = <0>; 536 power-domains = <&CLUSTER_PD>; 537 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 538 }; 539 540 CPU_PD1: power-domain-cpu1 { 541 #power-domain-cells = <0>; 542 power-domains = <&CLUSTER_PD>; 543 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 544 }; 545 546 CPU_PD2: power-domain-cpu2 { 547 #power-domain-cells = <0>; 548 power-domains = <&CLUSTER_PD>; 549 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 550 }; 551 552 CPU_PD3: power-domain-cpu3 { 553 #power-domain-cells = <0>; 554 power-domains = <&CLUSTER_PD>; 555 domain-idle-states = <&LITTLE_CPU_SLEEP_0>; 556 }; 557 558 CPU_PD4: power-domain-cpu4 { 559 #power-domain-cells = <0>; 560 power-domains = <&CLUSTER_PD>; 561 domain-idle-states = <&BIG_CPU_SLEEP_0>; 562 }; 563 564 CPU_PD5: power-domain-cpu5 { 565 #power-domain-cells = <0>; 566 power-domains = <&CLUSTER_PD>; 567 domain-idle-states = <&BIG_CPU_SLEEP_0>; 568 }; 569 570 CPU_PD6: power-domain-cpu6 { 571 #power-domain-cells = <0>; 572 power-domains = <&CLUSTER_PD>; 573 domain-idle-states = <&BIG_CPU_SLEEP_0>; 574 }; 575 576 CPU_PD7: power-domain-cpu7 { 577 #power-domain-cells = <0>; 578 power-domains = <&CLUSTER_PD>; 579 domain-idle-states = <&BIG_CPU_SLEEP_0>; 580 }; 581 582 CLUSTER_PD: power-domain-cpu-cluster0 { 583 #power-domain-cells = <0>; 584 domain-idle-states = <&CLUSTER_SLEEP_0>; 585 }; 586 }; 587 588 reserved-memory { 589 #address-cells = <2>; 590 #size-cells = <2>; 591 ranges; 592 593 hyp_mem: hyp@85700000 { 594 reg = <0x0 0x85700000 0x0 0x600000>; 595 no-map; 596 }; 597 598 xbl_mem: xbl@85d00000 { 599 reg = <0x0 0x85d00000 0x0 0x140000>; 600 no-map; 601 }; 602 603 aop_mem: aop@85f00000 { 604 reg = <0x0 0x85f00000 0x0 0x20000>; 605 no-map; 606 }; 607 608 aop_cmd_db: cmd-db@85f20000 { 609 compatible = "qcom,cmd-db"; 610 reg = <0x0 0x85f20000 0x0 0x20000>; 611 no-map; 612 }; 613 614 reserved@85f40000 { 615 reg = <0x0 0x85f40000 0x0 0x10000>; 616 no-map; 617 }; 618 619 smem_mem: smem@86000000 { 620 compatible = "qcom,smem"; 621 reg = <0x0 0x86000000 0x0 0x200000>; 622 no-map; 623 hwlocks = <&tcsr_mutex 3>; 624 }; 625 626 reserved@86200000 { 627 reg = <0x0 0x86200000 0x0 0x3900000>; 628 no-map; 629 }; 630 631 reserved@89b00000 { 632 reg = <0x0 0x89b00000 0x0 0x1c00000>; 633 no-map; 634 }; 635 636 reserved@9d400000 { 637 reg = <0x0 0x9d400000 0x0 0x1000000>; 638 no-map; 639 }; 640 641 reserved@9e400000 { 642 reg = <0x0 0x9e400000 0x0 0x1400000>; 643 no-map; 644 }; 645 646 reserved@9f800000 { 647 reg = <0x0 0x9f800000 0x0 0x800000>; 648 no-map; 649 }; 650 }; 651 652 smp2p-cdsp { 653 compatible = "qcom,smp2p"; 654 qcom,smem = <94>, <432>; 655 656 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 657 658 mboxes = <&apss_shared 6>; 659 660 qcom,local-pid = <0>; 661 qcom,remote-pid = <5>; 662 663 cdsp_smp2p_out: master-kernel { 664 qcom,entry-name = "master-kernel"; 665 #qcom,smem-state-cells = <1>; 666 }; 667 668 cdsp_smp2p_in: slave-kernel { 669 qcom,entry-name = "slave-kernel"; 670 671 interrupt-controller; 672 #interrupt-cells = <2>; 673 }; 674 }; 675 676 smp2p-lpass { 677 compatible = "qcom,smp2p"; 678 qcom,smem = <443>, <429>; 679 680 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 681 682 mboxes = <&apss_shared 10>; 683 684 qcom,local-pid = <0>; 685 qcom,remote-pid = <2>; 686 687 adsp_smp2p_out: master-kernel { 688 qcom,entry-name = "master-kernel"; 689 #qcom,smem-state-cells = <1>; 690 }; 691 692 adsp_smp2p_in: slave-kernel { 693 qcom,entry-name = "slave-kernel"; 694 695 interrupt-controller; 696 #interrupt-cells = <2>; 697 }; 698 }; 699 700 smp2p-mpss { 701 compatible = "qcom,smp2p"; 702 qcom,smem = <435>, <428>; 703 704 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 705 706 mboxes = <&apss_shared 14>; 707 708 qcom,local-pid = <0>; 709 qcom,remote-pid = <1>; 710 711 modem_smp2p_out: master-kernel { 712 qcom,entry-name = "master-kernel"; 713 #qcom,smem-state-cells = <1>; 714 }; 715 716 modem_smp2p_in: slave-kernel { 717 qcom,entry-name = "slave-kernel"; 718 719 interrupt-controller; 720 #interrupt-cells = <2>; 721 }; 722 723 modem_smp2p_ipa_out: ipa-ap-to-modem { 724 qcom,entry-name = "ipa"; 725 #qcom,smem-state-cells = <1>; 726 }; 727 728 modem_smp2p_ipa_in: ipa-modem-to-ap { 729 qcom,entry-name = "ipa"; 730 interrupt-controller; 731 #interrupt-cells = <2>; 732 }; 733 734 modem_smp2p_wlan_in: wlan-wpss-to-ap { 735 qcom,entry-name = "wlan"; 736 interrupt-controller; 737 #interrupt-cells = <2>; 738 }; 739 }; 740 741 smp2p-slpi { 742 compatible = "qcom,smp2p"; 743 qcom,smem = <481>, <430>; 744 745 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 746 747 mboxes = <&apss_shared 26>; 748 749 qcom,local-pid = <0>; 750 qcom,remote-pid = <3>; 751 752 slpi_smp2p_out: master-kernel { 753 qcom,entry-name = "master-kernel"; 754 #qcom,smem-state-cells = <1>; 755 }; 756 757 slpi_smp2p_in: slave-kernel { 758 qcom,entry-name = "slave-kernel"; 759 760 interrupt-controller; 761 #interrupt-cells = <2>; 762 }; 763 }; 764 765 soc: soc@0 { 766 compatible = "simple-bus"; 767 #address-cells = <2>; 768 #size-cells = <2>; 769 ranges = <0 0 0 0 0x10 0>; 770 dma-ranges = <0 0 0 0 0x10 0>; 771 772 gcc: clock-controller@100000 { 773 compatible = "qcom,gcc-sc8180x"; 774 reg = <0x0 0x00100000 0x0 0x1f0000>; 775 #clock-cells = <1>; 776 #reset-cells = <1>; 777 #power-domain-cells = <1>; 778 clocks = <&rpmhcc RPMH_CXO_CLK>, 779 <&rpmhcc RPMH_CXO_CLK_A>, 780 <&sleep_clk>; 781 clock-names = "bi_tcxo", 782 "bi_tcxo_ao", 783 "sleep_clk"; 784 }; 785 786 qupv3_id_0: geniqup@8c0000 { 787 compatible = "qcom,geni-se-qup"; 788 reg = <0 0x008c0000 0 0x6000>; 789 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 790 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 791 clock-names = "m-ahb", "s-ahb"; 792 #address-cells = <2>; 793 #size-cells = <2>; 794 ranges; 795 iommus = <&apps_smmu 0x4c3 0>; 796 status = "disabled"; 797 798 i2c0: i2c@880000 { 799 compatible = "qcom,geni-i2c"; 800 reg = <0 0x00880000 0 0x4000>; 801 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 802 clock-names = "se"; 803 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 804 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 805 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 806 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 807 interconnect-names = "qup-core", "qup-config", "qup-memory"; 808 #address-cells = <1>; 809 #size-cells = <0>; 810 status = "disabled"; 811 }; 812 813 spi0: spi@880000 { 814 compatible = "qcom,geni-spi"; 815 reg = <0 0x00880000 0 0x4000>; 816 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 817 clock-names = "se"; 818 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 819 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 820 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 821 interconnect-names = "qup-core", "qup-config"; 822 #address-cells = <1>; 823 #size-cells = <0>; 824 status = "disabled"; 825 }; 826 827 uart0: serial@880000 { 828 compatible = "qcom,geni-uart"; 829 reg = <0 0x00880000 0 0x4000>; 830 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 831 clock-names = "se"; 832 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 833 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 834 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 835 interconnect-names = "qup-core", "qup-config"; 836 status = "disabled"; 837 }; 838 839 i2c1: i2c@884000 { 840 compatible = "qcom,geni-i2c"; 841 reg = <0 0x00884000 0 0x4000>; 842 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 843 clock-names = "se"; 844 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 845 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 846 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 847 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 848 interconnect-names = "qup-core", "qup-config", "qup-memory"; 849 #address-cells = <1>; 850 #size-cells = <0>; 851 status = "disabled"; 852 }; 853 854 spi1: spi@884000 { 855 compatible = "qcom,geni-spi"; 856 reg = <0 0x00884000 0 0x4000>; 857 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 858 clock-names = "se"; 859 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 860 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 861 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 862 interconnect-names = "qup-core", "qup-config"; 863 #address-cells = <1>; 864 #size-cells = <0>; 865 status = "disabled"; 866 }; 867 868 uart1: serial@884000 { 869 compatible = "qcom,geni-uart"; 870 reg = <0 0x00884000 0 0x4000>; 871 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 872 clock-names = "se"; 873 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 874 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 875 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 876 interconnect-names = "qup-core", "qup-config"; 877 status = "disabled"; 878 }; 879 880 i2c2: i2c@888000 { 881 compatible = "qcom,geni-i2c"; 882 reg = <0 0x00888000 0 0x4000>; 883 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 884 clock-names = "se"; 885 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 886 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 887 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 888 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 889 interconnect-names = "qup-core", "qup-config", "qup-memory"; 890 #address-cells = <1>; 891 #size-cells = <0>; 892 status = "disabled"; 893 }; 894 895 spi2: spi@888000 { 896 compatible = "qcom,geni-spi"; 897 reg = <0 0x00888000 0 0x4000>; 898 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 899 clock-names = "se"; 900 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 901 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 902 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 903 interconnect-names = "qup-core", "qup-config"; 904 #address-cells = <1>; 905 #size-cells = <0>; 906 status = "disabled"; 907 }; 908 909 uart2: serial@888000 { 910 compatible = "qcom,geni-uart"; 911 reg = <0 0x00888000 0 0x4000>; 912 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 913 clock-names = "se"; 914 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 915 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 916 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 917 interconnect-names = "qup-core", "qup-config"; 918 status = "disabled"; 919 }; 920 921 i2c3: i2c@88c000 { 922 compatible = "qcom,geni-i2c"; 923 reg = <0 0x0088c000 0 0x4000>; 924 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 925 clock-names = "se"; 926 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 927 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 928 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 929 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 930 interconnect-names = "qup-core", "qup-config", "qup-memory"; 931 #address-cells = <1>; 932 #size-cells = <0>; 933 status = "disabled"; 934 }; 935 936 spi3: spi@88c000 { 937 compatible = "qcom,geni-spi"; 938 reg = <0 0x0088c000 0 0x4000>; 939 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 940 clock-names = "se"; 941 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 942 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 943 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 944 interconnect-names = "qup-core", "qup-config"; 945 #address-cells = <1>; 946 #size-cells = <0>; 947 status = "disabled"; 948 }; 949 950 uart3: serial@88c000 { 951 compatible = "qcom,geni-uart"; 952 reg = <0 0x0088c000 0 0x4000>; 953 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 954 clock-names = "se"; 955 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 956 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 957 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 958 interconnect-names = "qup-core", "qup-config"; 959 status = "disabled"; 960 }; 961 962 i2c4: i2c@890000 { 963 compatible = "qcom,geni-i2c"; 964 reg = <0 0x00890000 0 0x4000>; 965 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 966 clock-names = "se"; 967 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 968 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 969 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 970 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 971 interconnect-names = "qup-core", "qup-config", "qup-memory"; 972 #address-cells = <1>; 973 #size-cells = <0>; 974 status = "disabled"; 975 }; 976 977 spi4: spi@890000 { 978 compatible = "qcom,geni-spi"; 979 reg = <0 0x00890000 0 0x4000>; 980 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 981 clock-names = "se"; 982 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 983 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 984 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 985 interconnect-names = "qup-core", "qup-config"; 986 #address-cells = <1>; 987 #size-cells = <0>; 988 status = "disabled"; 989 }; 990 991 uart4: serial@890000 { 992 compatible = "qcom,geni-uart"; 993 reg = <0 0x00890000 0 0x4000>; 994 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 995 clock-names = "se"; 996 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 997 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 998 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 999 interconnect-names = "qup-core", "qup-config"; 1000 status = "disabled"; 1001 }; 1002 1003 i2c5: i2c@894000 { 1004 compatible = "qcom,geni-i2c"; 1005 reg = <0 0x00894000 0 0x4000>; 1006 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1007 clock-names = "se"; 1008 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1009 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1010 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1011 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1012 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1013 #address-cells = <1>; 1014 #size-cells = <0>; 1015 status = "disabled"; 1016 }; 1017 1018 spi5: spi@894000 { 1019 compatible = "qcom,geni-spi"; 1020 reg = <0 0x00894000 0 0x4000>; 1021 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1022 clock-names = "se"; 1023 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1024 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1025 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1026 interconnect-names = "qup-core", "qup-config"; 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 status = "disabled"; 1030 }; 1031 1032 uart5: serial@894000 { 1033 compatible = "qcom,geni-uart"; 1034 reg = <0 0x00894000 0 0x4000>; 1035 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1036 clock-names = "se"; 1037 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1038 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1039 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1040 interconnect-names = "qup-core", "qup-config"; 1041 status = "disabled"; 1042 }; 1043 1044 i2c6: i2c@898000 { 1045 compatible = "qcom,geni-i2c"; 1046 reg = <0 0x00898000 0 0x4000>; 1047 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1048 clock-names = "se"; 1049 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1050 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1051 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1052 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1053 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1054 #address-cells = <1>; 1055 #size-cells = <0>; 1056 status = "disabled"; 1057 }; 1058 1059 spi6: spi@898000 { 1060 compatible = "qcom,geni-spi"; 1061 reg = <0 0x00898000 0 0x4000>; 1062 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1063 clock-names = "se"; 1064 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1065 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1066 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1067 interconnect-names = "qup-core", "qup-config"; 1068 #address-cells = <1>; 1069 #size-cells = <0>; 1070 status = "disabled"; 1071 }; 1072 1073 uart6: serial@898000 { 1074 compatible = "qcom,geni-uart"; 1075 reg = <0 0x00898000 0 0x4000>; 1076 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1077 clock-names = "se"; 1078 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1079 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1080 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1081 interconnect-names = "qup-core", "qup-config"; 1082 status = "disabled"; 1083 }; 1084 1085 i2c7: i2c@89c000 { 1086 compatible = "qcom,geni-i2c"; 1087 reg = <0 0x0089c000 0 0x4000>; 1088 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1089 clock-names = "se"; 1090 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1091 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1092 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1093 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1094 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1095 #address-cells = <1>; 1096 #size-cells = <0>; 1097 status = "disabled"; 1098 }; 1099 1100 spi7: spi@89c000 { 1101 compatible = "qcom,geni-spi"; 1102 reg = <0 0x0089c000 0 0x4000>; 1103 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1104 clock-names = "se"; 1105 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1106 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1107 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1108 interconnect-names = "qup-core", "qup-config"; 1109 #address-cells = <1>; 1110 #size-cells = <0>; 1111 status = "disabled"; 1112 }; 1113 1114 uart7: serial@89c000 { 1115 compatible = "qcom,geni-uart"; 1116 reg = <0 0x0089c000 0 0x4000>; 1117 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1118 clock-names = "se"; 1119 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1120 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1121 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1122 interconnect-names = "qup-core", "qup-config"; 1123 status = "disabled"; 1124 }; 1125 }; 1126 1127 qupv3_id_1: geniqup@ac0000 { 1128 compatible = "qcom,geni-se-qup"; 1129 reg = <0x0 0x00ac0000 0x0 0x6000>; 1130 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1131 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1132 clock-names = "m-ahb", "s-ahb"; 1133 #address-cells = <2>; 1134 #size-cells = <2>; 1135 ranges; 1136 iommus = <&apps_smmu 0x603 0>; 1137 status = "disabled"; 1138 1139 i2c8: i2c@a80000 { 1140 compatible = "qcom,geni-i2c"; 1141 reg = <0 0x00a80000 0 0x4000>; 1142 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1143 clock-names = "se"; 1144 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1145 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1146 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1147 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1148 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1149 #address-cells = <1>; 1150 #size-cells = <0>; 1151 status = "disabled"; 1152 }; 1153 1154 spi8: spi@a80000 { 1155 compatible = "qcom,geni-spi"; 1156 reg = <0 0x00a80000 0 0x4000>; 1157 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1158 clock-names = "se"; 1159 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1160 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1161 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1162 interconnect-names = "qup-core", "qup-config"; 1163 #address-cells = <1>; 1164 #size-cells = <0>; 1165 status = "disabled"; 1166 }; 1167 1168 uart8: serial@a80000 { 1169 compatible = "qcom,geni-uart"; 1170 reg = <0 0x00a80000 0 0x4000>; 1171 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1172 clock-names = "se"; 1173 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1174 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1175 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1176 interconnect-names = "qup-core", "qup-config"; 1177 status = "disabled"; 1178 }; 1179 1180 i2c9: i2c@a84000 { 1181 compatible = "qcom,geni-i2c"; 1182 reg = <0 0x00a84000 0 0x4000>; 1183 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1184 clock-names = "se"; 1185 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1186 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1187 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1188 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1189 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1190 #address-cells = <1>; 1191 #size-cells = <0>; 1192 status = "disabled"; 1193 }; 1194 1195 spi9: spi@a84000 { 1196 compatible = "qcom,geni-spi"; 1197 reg = <0 0x00a84000 0 0x4000>; 1198 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1199 clock-names = "se"; 1200 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1201 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1202 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1203 interconnect-names = "qup-core", "qup-config"; 1204 #address-cells = <1>; 1205 #size-cells = <0>; 1206 status = "disabled"; 1207 }; 1208 1209 uart9: serial@a84000 { 1210 compatible = "qcom,geni-debug-uart"; 1211 reg = <0 0x00a84000 0 0x4000>; 1212 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1213 clock-names = "se"; 1214 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1215 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1216 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1217 interconnect-names = "qup-core", "qup-config"; 1218 status = "disabled"; 1219 }; 1220 1221 i2c10: i2c@a88000 { 1222 compatible = "qcom,geni-i2c"; 1223 reg = <0 0x00a88000 0 0x4000>; 1224 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1225 clock-names = "se"; 1226 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1227 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1228 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1229 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1230 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1231 #address-cells = <1>; 1232 #size-cells = <0>; 1233 status = "disabled"; 1234 }; 1235 1236 spi10: spi@a88000 { 1237 compatible = "qcom,geni-spi"; 1238 reg = <0 0x00a88000 0 0x4000>; 1239 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1240 clock-names = "se"; 1241 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1242 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1243 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1244 interconnect-names = "qup-core", "qup-config"; 1245 #address-cells = <1>; 1246 #size-cells = <0>; 1247 status = "disabled"; 1248 }; 1249 1250 uart10: serial@a88000 { 1251 compatible = "qcom,geni-uart"; 1252 reg = <0 0x00a88000 0 0x4000>; 1253 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1254 clock-names = "se"; 1255 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1256 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1257 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1258 interconnect-names = "qup-core", "qup-config"; 1259 status = "disabled"; 1260 }; 1261 1262 i2c11: i2c@a8c000 { 1263 compatible = "qcom,geni-i2c"; 1264 reg = <0 0x00a8c000 0 0x4000>; 1265 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1266 clock-names = "se"; 1267 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1268 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1269 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1270 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1271 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1272 #address-cells = <1>; 1273 #size-cells = <0>; 1274 status = "disabled"; 1275 }; 1276 1277 spi11: spi@a8c000 { 1278 compatible = "qcom,geni-spi"; 1279 reg = <0 0x00a8c000 0 0x4000>; 1280 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1281 clock-names = "se"; 1282 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1283 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1284 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1285 interconnect-names = "qup-core", "qup-config"; 1286 #address-cells = <1>; 1287 #size-cells = <0>; 1288 status = "disabled"; 1289 }; 1290 1291 uart11: serial@a8c000 { 1292 compatible = "qcom,geni-uart"; 1293 reg = <0 0x00a8c000 0 0x4000>; 1294 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1295 clock-names = "se"; 1296 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1297 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1298 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1299 interconnect-names = "qup-core", "qup-config"; 1300 status = "disabled"; 1301 }; 1302 1303 i2c12: i2c@a90000 { 1304 compatible = "qcom,geni-i2c"; 1305 reg = <0 0x00a90000 0 0x4000>; 1306 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1307 clock-names = "se"; 1308 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1309 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1310 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1311 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1312 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1313 #address-cells = <1>; 1314 #size-cells = <0>; 1315 status = "disabled"; 1316 }; 1317 1318 spi12: spi@a90000 { 1319 compatible = "qcom,geni-spi"; 1320 reg = <0 0x00a90000 0 0x4000>; 1321 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1322 clock-names = "se"; 1323 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1324 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1325 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1326 interconnect-names = "qup-core", "qup-config"; 1327 #address-cells = <1>; 1328 #size-cells = <0>; 1329 status = "disabled"; 1330 }; 1331 1332 uart12: serial@a90000 { 1333 compatible = "qcom,geni-uart"; 1334 reg = <0 0x00a90000 0 0x4000>; 1335 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1336 clock-names = "se"; 1337 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1338 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1339 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1340 interconnect-names = "qup-core", "qup-config"; 1341 status = "disabled"; 1342 }; 1343 1344 i2c16: i2c@a94000 { 1345 compatible = "qcom,geni-i2c"; 1346 reg = <0 0x00a94000 0 0x4000>; 1347 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1348 clock-names = "se"; 1349 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1350 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1351 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1352 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1353 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1354 #address-cells = <1>; 1355 #size-cells = <0>; 1356 status = "disabled"; 1357 }; 1358 1359 spi16: spi@a94000 { 1360 compatible = "qcom,geni-spi"; 1361 reg = <0 0x00a94000 0 0x4000>; 1362 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1363 clock-names = "se"; 1364 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1365 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1366 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1367 interconnect-names = "qup-core", "qup-config"; 1368 #address-cells = <1>; 1369 #size-cells = <0>; 1370 status = "disabled"; 1371 }; 1372 1373 uart16: serial@a94000 { 1374 compatible = "qcom,geni-uart"; 1375 reg = <0 0x00a94000 0 0x4000>; 1376 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1377 clock-names = "se"; 1378 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1379 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1380 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 1381 interconnect-names = "qup-core", "qup-config"; 1382 status = "disabled"; 1383 }; 1384 }; 1385 1386 qupv3_id_2: geniqup@cc0000 { 1387 compatible = "qcom,geni-se-qup"; 1388 reg = <0x0 0x00cc0000 0x0 0x6000>; 1389 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1390 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1391 clock-names = "m-ahb", "s-ahb"; 1392 #address-cells = <2>; 1393 #size-cells = <2>; 1394 ranges; 1395 iommus = <&apps_smmu 0x7a3 0>; 1396 status = "disabled"; 1397 1398 i2c17: i2c@c80000 { 1399 compatible = "qcom,geni-i2c"; 1400 reg = <0 0x00c80000 0 0x4000>; 1401 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1402 clock-names = "se"; 1403 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1404 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1405 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1406 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1407 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1408 #address-cells = <1>; 1409 #size-cells = <0>; 1410 status = "disabled"; 1411 }; 1412 1413 spi17: spi@c80000 { 1414 compatible = "qcom,geni-spi"; 1415 reg = <0 0x00c80000 0 0x4000>; 1416 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1417 clock-names = "se"; 1418 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1419 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1420 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1421 interconnect-names = "qup-core", "qup-config"; 1422 #address-cells = <1>; 1423 #size-cells = <0>; 1424 status = "disabled"; 1425 }; 1426 1427 uart17: serial@c80000 { 1428 compatible = "qcom,geni-uart"; 1429 reg = <0 0x00c80000 0 0x4000>; 1430 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1431 clock-names = "se"; 1432 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1433 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1434 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1435 interconnect-names = "qup-core", "qup-config"; 1436 status = "disabled"; 1437 }; 1438 1439 i2c18: i2c@c84000 { 1440 compatible = "qcom,geni-i2c"; 1441 reg = <0 0x00c84000 0 0x4000>; 1442 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1443 clock-names = "se"; 1444 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1445 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1446 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1447 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1448 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1449 #address-cells = <1>; 1450 #size-cells = <0>; 1451 status = "disabled"; 1452 }; 1453 1454 spi18: spi@c84000 { 1455 compatible = "qcom,geni-spi"; 1456 reg = <0 0x00c84000 0 0x4000>; 1457 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1458 clock-names = "se"; 1459 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1460 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1461 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1462 interconnect-names = "qup-core", "qup-config"; 1463 #address-cells = <1>; 1464 #size-cells = <0>; 1465 status = "disabled"; 1466 }; 1467 1468 uart18: serial@c84000 { 1469 compatible = "qcom,geni-uart"; 1470 reg = <0 0x00c84000 0 0x4000>; 1471 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1472 clock-names = "se"; 1473 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1474 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1475 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1476 interconnect-names = "qup-core", "qup-config"; 1477 status = "disabled"; 1478 }; 1479 1480 i2c19: i2c@c88000 { 1481 compatible = "qcom,geni-i2c"; 1482 reg = <0 0x00c88000 0 0x4000>; 1483 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1484 clock-names = "se"; 1485 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1486 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1487 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1488 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1489 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1490 #address-cells = <1>; 1491 #size-cells = <0>; 1492 status = "disabled"; 1493 }; 1494 1495 spi19: spi@c88000 { 1496 compatible = "qcom,geni-spi"; 1497 reg = <0 0x00c88000 0 0x4000>; 1498 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1499 clock-names = "se"; 1500 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1501 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1502 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1503 interconnect-names = "qup-core", "qup-config"; 1504 #address-cells = <1>; 1505 #size-cells = <0>; 1506 status = "disabled"; 1507 }; 1508 1509 uart19: serial@c88000 { 1510 compatible = "qcom,geni-uart"; 1511 reg = <0 0x00c88000 0 0x4000>; 1512 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1513 clock-names = "se"; 1514 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1515 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1516 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1517 interconnect-names = "qup-core", "qup-config"; 1518 status = "disabled"; 1519 }; 1520 1521 i2c13: i2c@c8c000 { 1522 compatible = "qcom,geni-i2c"; 1523 reg = <0 0x00c8c000 0 0x4000>; 1524 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1525 clock-names = "se"; 1526 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1527 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1528 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1529 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1530 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1531 #address-cells = <1>; 1532 #size-cells = <0>; 1533 status = "disabled"; 1534 }; 1535 1536 spi13: spi@c8c000 { 1537 compatible = "qcom,geni-spi"; 1538 reg = <0 0x00c8c000 0 0x4000>; 1539 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1540 clock-names = "se"; 1541 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1542 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1543 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1544 interconnect-names = "qup-core", "qup-config"; 1545 #address-cells = <1>; 1546 #size-cells = <0>; 1547 status = "disabled"; 1548 }; 1549 1550 uart13: serial@c8c000 { 1551 compatible = "qcom,geni-uart"; 1552 reg = <0 0x00c8c000 0 0x4000>; 1553 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1554 clock-names = "se"; 1555 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1556 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1557 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1558 interconnect-names = "qup-core", "qup-config"; 1559 status = "disabled"; 1560 }; 1561 1562 i2c14: i2c@c90000 { 1563 compatible = "qcom,geni-i2c"; 1564 reg = <0 0x00c90000 0 0x4000>; 1565 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1566 clock-names = "se"; 1567 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1568 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1569 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1570 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1571 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1572 #address-cells = <1>; 1573 #size-cells = <0>; 1574 status = "disabled"; 1575 }; 1576 1577 spi14: spi@c90000 { 1578 compatible = "qcom,geni-spi"; 1579 reg = <0 0x00c90000 0 0x4000>; 1580 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1581 clock-names = "se"; 1582 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1583 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1584 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1585 interconnect-names = "qup-core", "qup-config"; 1586 #address-cells = <1>; 1587 #size-cells = <0>; 1588 status = "disabled"; 1589 }; 1590 1591 uart14: serial@c90000 { 1592 compatible = "qcom,geni-uart"; 1593 reg = <0 0x00c90000 0 0x4000>; 1594 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1595 clock-names = "se"; 1596 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1597 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1598 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1599 interconnect-names = "qup-core", "qup-config"; 1600 status = "disabled"; 1601 }; 1602 1603 i2c15: i2c@c94000 { 1604 compatible = "qcom,geni-i2c"; 1605 reg = <0 0x00c94000 0 0x4000>; 1606 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1607 clock-names = "se"; 1608 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1609 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1610 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1611 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1612 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1613 #address-cells = <1>; 1614 #size-cells = <0>; 1615 status = "disabled"; 1616 }; 1617 1618 spi15: spi@c94000 { 1619 compatible = "qcom,geni-spi"; 1620 reg = <0 0x00c94000 0 0x4000>; 1621 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1622 clock-names = "se"; 1623 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1624 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1625 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1626 interconnect-names = "qup-core", "qup-config"; 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 status = "disabled"; 1630 }; 1631 1632 uart15: serial@c94000 { 1633 compatible = "qcom,geni-uart"; 1634 reg = <0 0x00c94000 0 0x4000>; 1635 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1636 clock-names = "se"; 1637 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1638 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1639 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1640 interconnect-names = "qup-core", "qup-config"; 1641 status = "disabled"; 1642 }; 1643 }; 1644 1645 config_noc: interconnect@1500000 { 1646 compatible = "qcom,sc8180x-config-noc"; 1647 reg = <0 0x01500000 0 0x7400>; 1648 #interconnect-cells = <2>; 1649 qcom,bcm-voters = <&apps_bcm_voter>; 1650 }; 1651 1652 system_noc: interconnect@1620000 { 1653 compatible = "qcom,sc8180x-system-noc"; 1654 reg = <0 0x01620000 0 0x19400>; 1655 #interconnect-cells = <2>; 1656 qcom,bcm-voters = <&apps_bcm_voter>; 1657 }; 1658 1659 aggre1_noc: interconnect@16e0000 { 1660 compatible = "qcom,sc8180x-aggre1-noc"; 1661 reg = <0 0x016e0000 0 0xd080>; 1662 #interconnect-cells = <2>; 1663 qcom,bcm-voters = <&apps_bcm_voter>; 1664 }; 1665 1666 aggre2_noc: interconnect@1700000 { 1667 compatible = "qcom,sc8180x-aggre2-noc"; 1668 reg = <0 0x01700000 0 0x20000>; 1669 #interconnect-cells = <2>; 1670 qcom,bcm-voters = <&apps_bcm_voter>; 1671 }; 1672 1673 compute_noc: interconnect@1720000 { 1674 compatible = "qcom,sc8180x-compute-noc"; 1675 reg = <0 0x01720000 0 0x7000>; 1676 #interconnect-cells = <2>; 1677 qcom,bcm-voters = <&apps_bcm_voter>; 1678 }; 1679 1680 mmss_noc: interconnect@1740000 { 1681 compatible = "qcom,sc8180x-mmss-noc"; 1682 reg = <0 0x01740000 0 0x1c100>; 1683 #interconnect-cells = <2>; 1684 qcom,bcm-voters = <&apps_bcm_voter>; 1685 }; 1686 1687 pcie0: pci@1c00000 { 1688 compatible = "qcom,pcie-sc8180x"; 1689 reg = <0 0x01c00000 0 0x3000>, 1690 <0 0x60000000 0 0xf1d>, 1691 <0 0x60000f20 0 0xa8>, 1692 <0 0x60001000 0 0x1000>, 1693 <0 0x60100000 0 0x100000>; 1694 reg-names = "parf", 1695 "dbi", 1696 "elbi", 1697 "atu", 1698 "config"; 1699 device_type = "pci"; 1700 linux,pci-domain = <0>; 1701 bus-range = <0x00 0xff>; 1702 num-lanes = <2>; 1703 1704 #address-cells = <3>; 1705 #size-cells = <2>; 1706 1707 ranges = <0x01000000 0x0 0x60200000 0x0 0x60200000 0x0 0x100000>, 1708 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1709 1710 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1711 interrupt-names = "msi"; 1712 #interrupt-cells = <1>; 1713 interrupt-map-mask = <0 0 0 0x7>; 1714 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1715 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1716 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1717 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1718 1719 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1720 <&gcc GCC_PCIE_0_AUX_CLK>, 1721 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1722 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1723 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1724 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1725 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1726 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1727 clock-names = "pipe", 1728 "aux", 1729 "cfg", 1730 "bus_master", 1731 "bus_slave", 1732 "slave_q2a", 1733 "ref", 1734 "tbu"; 1735 1736 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 1737 assigned-clock-rates = <19200000>; 1738 1739 iommus = <&apps_smmu 0x1d80 0x7f>; 1740 iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, 1741 <0x100 &apps_smmu 0x1d81 0x1>; 1742 1743 resets = <&gcc GCC_PCIE_0_BCR>; 1744 reset-names = "pci"; 1745 1746 power-domains = <&gcc PCIE_0_GDSC>; 1747 1748 interconnects = <&aggre2_noc MASTER_PCIE 0 &mc_virt SLAVE_EBI_CH0 0>, 1749 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; 1750 interconnect-names = "pcie-mem", "cpu-pcie"; 1751 1752 phys = <&pcie0_phy>; 1753 phy-names = "pciephy"; 1754 1755 status = "disabled"; 1756 }; 1757 1758 pcie0_phy: phy@1c06000 { 1759 compatible = "qcom,sc8180x-qmp-pcie-phy"; 1760 reg = <0 0x01c06000 0 0x1000>; 1761 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1762 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1763 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1764 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, 1765 <&gcc GCC_PCIE_0_PIPE_CLK>; 1766 clock-names = "aux", 1767 "cfg_ahb", 1768 "ref", 1769 "refgen", 1770 "pipe"; 1771 #clock-cells = <0>; 1772 clock-output-names = "pcie_0_pipe_clk"; 1773 #phy-cells = <0>; 1774 1775 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1776 reset-names = "phy"; 1777 1778 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1779 assigned-clock-rates = <100000000>; 1780 1781 status = "disabled"; 1782 }; 1783 1784 pcie3: pci@1c08000 { 1785 compatible = "qcom,pcie-sc8180x"; 1786 reg = <0 0x01c08000 0 0x3000>, 1787 <0 0x40000000 0 0xf1d>, 1788 <0 0x40000f20 0 0xa8>, 1789 <0 0x40001000 0 0x1000>, 1790 <0 0x40100000 0 0x100000>; 1791 reg-names = "parf", 1792 "dbi", 1793 "elbi", 1794 "atu", 1795 "config"; 1796 device_type = "pci"; 1797 linux,pci-domain = <3>; 1798 bus-range = <0x00 0xff>; 1799 num-lanes = <2>; 1800 1801 #address-cells = <3>; 1802 #size-cells = <2>; 1803 1804 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1805 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1806 1807 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 1808 interrupt-names = "msi"; 1809 #interrupt-cells = <1>; 1810 interrupt-map-mask = <0 0 0 0x7>; 1811 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1812 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1813 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1814 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1815 1816 clocks = <&gcc GCC_PCIE_3_PIPE_CLK>, 1817 <&gcc GCC_PCIE_3_AUX_CLK>, 1818 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 1819 <&gcc GCC_PCIE_3_MSTR_AXI_CLK>, 1820 <&gcc GCC_PCIE_3_SLV_AXI_CLK>, 1821 <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>, 1822 <&gcc GCC_PCIE_3_CLKREF_CLK>, 1823 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1824 clock-names = "pipe", 1825 "aux", 1826 "cfg", 1827 "bus_master", 1828 "bus_slave", 1829 "slave_q2a", 1830 "ref", 1831 "tbu"; 1832 1833 assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>; 1834 assigned-clock-rates = <19200000>; 1835 1836 iommus = <&apps_smmu 0x1e00 0x7f>; 1837 iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, 1838 <0x100 &apps_smmu 0x1e01 0x1>; 1839 1840 resets = <&gcc GCC_PCIE_3_BCR>; 1841 reset-names = "pci"; 1842 1843 power-domains = <&gcc PCIE_3_GDSC>; 1844 1845 interconnects = <&aggre2_noc MASTER_PCIE_3 0 &mc_virt SLAVE_EBI_CH0 0>, 1846 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; 1847 interconnect-names = "pcie-mem", "cpu-pcie"; 1848 1849 phys = <&pcie3_phy>; 1850 phy-names = "pciephy"; 1851 1852 status = "disabled"; 1853 }; 1854 1855 pcie3_phy: phy@1c0c000 { 1856 compatible = "qcom,sc8180x-qmp-pcie-phy"; 1857 reg = <0 0x01c0c000 0 0x1000>; 1858 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1859 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 1860 <&gcc GCC_PCIE_3_CLKREF_CLK>, 1861 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>, 1862 <&gcc GCC_PCIE_3_PIPE_CLK>; 1863 clock-names = "aux", 1864 "cfg_ahb", 1865 "ref", 1866 "refgen", 1867 "pipe"; 1868 #clock-cells = <0>; 1869 clock-output-names = "pcie_3_pipe_clk"; 1870 1871 #phy-cells = <0>; 1872 1873 resets = <&gcc GCC_PCIE_3_PHY_BCR>; 1874 reset-names = "phy"; 1875 1876 assigned-clocks = <&gcc GCC_PCIE3_PHY_REFGEN_CLK>; 1877 assigned-clock-rates = <100000000>; 1878 1879 status = "disabled"; 1880 }; 1881 1882 pcie1: pci@1c10000 { 1883 compatible = "qcom,pcie-sc8180x"; 1884 reg = <0 0x01c10000 0 0x3000>, 1885 <0 0x68000000 0 0xf1d>, 1886 <0 0x68000f20 0 0xa8>, 1887 <0 0x68001000 0 0x1000>, 1888 <0 0x68100000 0 0x100000>; 1889 reg-names = "parf", 1890 "dbi", 1891 "elbi", 1892 "atu", 1893 "config"; 1894 device_type = "pci"; 1895 linux,pci-domain = <1>; 1896 bus-range = <0x00 0xff>; 1897 num-lanes = <2>; 1898 1899 #address-cells = <3>; 1900 #size-cells = <2>; 1901 1902 ranges = <0x01000000 0x0 0x68200000 0x0 0x68200000 0x0 0x100000>, 1903 <0x02000000 0x0 0x68300000 0x0 0x68300000 0x0 0x3d00000>; 1904 1905 interrupts = <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>; 1906 interrupt-names = "msi"; 1907 #interrupt-cells = <1>; 1908 interrupt-map-mask = <0 0 0 0x7>; 1909 interrupt-map = <0 0 0 1 &intc 0 747 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1910 <0 0 0 2 &intc 0 746 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1911 <0 0 0 3 &intc 0 745 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1912 <0 0 0 4 &intc 0 744 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1913 1914 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1915 <&gcc GCC_PCIE_1_AUX_CLK>, 1916 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1917 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1918 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1919 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1920 <&gcc GCC_PCIE_1_CLKREF_CLK>, 1921 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1922 clock-names = "pipe", 1923 "aux", 1924 "cfg", 1925 "bus_master", 1926 "bus_slave", 1927 "slave_q2a", 1928 "ref", 1929 "tbu"; 1930 1931 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1932 assigned-clock-rates = <19200000>; 1933 1934 iommus = <&apps_smmu 0x1c80 0x7f>; 1935 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1936 <0x100 &apps_smmu 0x1c81 0x1>; 1937 1938 resets = <&gcc GCC_PCIE_1_BCR>; 1939 reset-names = "pci"; 1940 1941 power-domains = <&gcc PCIE_1_GDSC>; 1942 1943 interconnects = <&aggre2_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI_CH0 0>, 1944 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; 1945 interconnect-names = "pcie-mem", "cpu-pcie"; 1946 1947 phys = <&pcie1_phy>; 1948 phy-names = "pciephy"; 1949 1950 status = "disabled"; 1951 }; 1952 1953 pcie1_phy: phy@1c16000 { 1954 compatible = "qcom,sc8180x-qmp-pcie-phy"; 1955 reg = <0 0x01c16000 0 0x1000>; 1956 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1957 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1958 <&gcc GCC_PCIE_1_CLKREF_CLK>, 1959 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, 1960 <&gcc GCC_PCIE_1_PIPE_CLK>; 1961 clock-names = "aux", 1962 "cfg_ahb", 1963 "ref", 1964 "refgen", 1965 "pipe"; 1966 #clock-cells = <0>; 1967 clock-output-names = "pcie_1_pipe_clk"; 1968 1969 #phy-cells = <0>; 1970 1971 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1972 reset-names = "phy"; 1973 1974 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 1975 assigned-clock-rates = <100000000>; 1976 1977 status = "disabled"; 1978 }; 1979 1980 pcie2: pci@1c18000 { 1981 compatible = "qcom,pcie-sc8180x"; 1982 reg = <0 0x01c18000 0 0x3000>, 1983 <0 0x70000000 0 0xf1d>, 1984 <0 0x70000f20 0 0xa8>, 1985 <0 0x70001000 0 0x1000>, 1986 <0 0x70100000 0 0x100000>; 1987 reg-names = "parf", 1988 "dbi", 1989 "elbi", 1990 "atu", 1991 "config"; 1992 device_type = "pci"; 1993 linux,pci-domain = <2>; 1994 bus-range = <0x00 0xff>; 1995 num-lanes = <4>; 1996 1997 #address-cells = <3>; 1998 #size-cells = <2>; 1999 2000 ranges = <0x01000000 0x0 0x70200000 0x0 0x70200000 0x0 0x100000>, 2001 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>; 2002 2003 interrupts = <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>; 2004 interrupt-names = "msi"; 2005 #interrupt-cells = <1>; 2006 interrupt-map-mask = <0 0 0 0x7>; 2007 interrupt-map = <0 0 0 1 &intc 0 663 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2008 <0 0 0 2 &intc 0 662 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2009 <0 0 0 3 &intc 0 661 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2010 <0 0 0 4 &intc 0 660 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2011 2012 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2013 <&gcc GCC_PCIE_2_AUX_CLK>, 2014 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2015 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2016 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 2017 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 2018 <&gcc GCC_PCIE_2_CLKREF_CLK>, 2019 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 2020 clock-names = "pipe", 2021 "aux", 2022 "cfg", 2023 "bus_master", 2024 "bus_slave", 2025 "slave_q2a", 2026 "ref", 2027 "tbu"; 2028 2029 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 2030 assigned-clock-rates = <19200000>; 2031 2032 iommus = <&apps_smmu 0x1d00 0x7f>; 2033 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 2034 <0x100 &apps_smmu 0x1d01 0x1>; 2035 2036 resets = <&gcc GCC_PCIE_2_BCR>; 2037 reset-names = "pci"; 2038 2039 power-domains = <&gcc PCIE_2_GDSC>; 2040 2041 interconnects = <&aggre2_noc MASTER_PCIE_2 0 &mc_virt SLAVE_EBI_CH0 0>, 2042 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; 2043 interconnect-names = "pcie-mem", "cpu-pcie"; 2044 2045 phys = <&pcie2_phy>; 2046 phy-names = "pciephy"; 2047 2048 status = "disabled"; 2049 }; 2050 2051 pcie2_phy: phy@1c1c000 { 2052 compatible = "qcom,sc8180x-qmp-pcie-phy"; 2053 reg = <0 0x01c1c000 0 0x1000>; 2054 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2055 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2056 <&gcc GCC_PCIE_2_CLKREF_CLK>, 2057 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>, 2058 <&gcc GCC_PCIE_2_PIPE_CLK>; 2059 clock-names = "aux", 2060 "cfg_ahb", 2061 "ref", 2062 "refgen", 2063 "pipe"; 2064 #clock-cells = <0>; 2065 clock-output-names = "pcie_3_pipe_clk"; 2066 2067 #phy-cells = <0>; 2068 2069 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 2070 reset-names = "phy"; 2071 2072 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2073 assigned-clock-rates = <100000000>; 2074 2075 status = "disabled"; 2076 }; 2077 2078 ufs_mem_hc: ufshc@1d84000 { 2079 compatible = "qcom,sc8180x-ufshc", "qcom,ufshc", 2080 "jedec,ufs-2.0"; 2081 reg = <0 0x01d84000 0 0x2500>; 2082 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2083 phys = <&ufs_mem_phy>; 2084 phy-names = "ufsphy"; 2085 lanes-per-direction = <2>; 2086 #reset-cells = <1>; 2087 resets = <&gcc GCC_UFS_PHY_BCR>; 2088 reset-names = "rst"; 2089 2090 iommus = <&apps_smmu 0x300 0>; 2091 2092 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2093 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2094 <&gcc GCC_UFS_PHY_AHB_CLK>, 2095 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2096 <&rpmhcc RPMH_CXO_CLK>, 2097 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2098 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2099 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2100 clock-names = "core_clk", 2101 "bus_aggr_clk", 2102 "iface_clk", 2103 "core_clk_unipro", 2104 "ref_clk", 2105 "tx_lane0_sync_clk", 2106 "rx_lane0_sync_clk", 2107 "rx_lane1_sync_clk"; 2108 freq-table-hz = <37500000 300000000>, 2109 <0 0>, 2110 <0 0>, 2111 <37500000 300000000>, 2112 <0 0>, 2113 <0 0>, 2114 <0 0>, 2115 <0 0>; 2116 2117 status = "disabled"; 2118 }; 2119 2120 ufs_mem_phy: phy-wrapper@1d87000 { 2121 compatible = "qcom,sc8180x-qmp-ufs-phy"; 2122 reg = <0 0x01d87000 0 0x1000>; 2123 2124 clocks = <&rpmhcc RPMH_CXO_CLK>, 2125 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 2126 clock-names = "ref", 2127 "ref_aux"; 2128 2129 resets = <&ufs_mem_hc 0>; 2130 reset-names = "ufsphy"; 2131 2132 #phy-cells = <0>; 2133 2134 status = "disabled"; 2135 }; 2136 2137 ipa_virt: interconnect@1e00000 { 2138 compatible = "qcom,sc8180x-ipa-virt"; 2139 reg = <0 0x01e00000 0 0x1000>; 2140 #interconnect-cells = <2>; 2141 qcom,bcm-voters = <&apps_bcm_voter>; 2142 }; 2143 2144 tcsr_mutex: hwlock@1f40000 { 2145 compatible = "qcom,tcsr-mutex"; 2146 reg = <0x0 0x01f40000 0x0 0x40000>; 2147 #hwlock-cells = <1>; 2148 }; 2149 2150 gpu: gpu@2c00000 { 2151 compatible = "qcom,adreno-680.1", "qcom,adreno"; 2152 #stream-id-cells = <16>; 2153 2154 reg = <0 0x02c00000 0 0x40000>; 2155 reg-names = "kgsl_3d0_reg_memory"; 2156 2157 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2158 2159 iommus = <&adreno_smmu 0 0xc01>; 2160 2161 operating-points-v2 = <&gpu_opp_table>; 2162 2163 interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &mc_virt SLAVE_EBI_CH0 0>; 2164 interconnect-names = "gfx-mem"; 2165 2166 qcom,gmu = <&gmu>; 2167 status = "disabled"; 2168 2169 gpu_opp_table: opp-table { 2170 compatible = "operating-points-v2"; 2171 2172 opp-514000000 { 2173 opp-hz = /bits/ 64 <514000000>; 2174 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2175 }; 2176 2177 opp-500000000 { 2178 opp-hz = /bits/ 64 <500000000>; 2179 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2180 }; 2181 2182 opp-461000000 { 2183 opp-hz = /bits/ 64 <461000000>; 2184 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2185 }; 2186 2187 opp-405000000 { 2188 opp-hz = /bits/ 64 <405000000>; 2189 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2190 }; 2191 2192 opp-315000000 { 2193 opp-hz = /bits/ 64 <315000000>; 2194 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2195 }; 2196 2197 opp-256000000 { 2198 opp-hz = /bits/ 64 <256000000>; 2199 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2200 }; 2201 2202 opp-177000000 { 2203 opp-hz = /bits/ 64 <177000000>; 2204 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2205 }; 2206 }; 2207 }; 2208 2209 gmu: gmu@2c6a000 { 2210 compatible = "qcom,adreno-gmu-680.1", "qcom,adreno-gmu"; 2211 2212 reg = <0 0x02c6a000 0 0x30000>, 2213 <0 0x0b290000 0 0x10000>, 2214 <0 0x0b490000 0 0x10000>; 2215 reg-names = "gmu", 2216 "gmu_pdc", 2217 "gmu_pdc_seq"; 2218 2219 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2220 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2221 interrupt-names = "hfi", "gmu"; 2222 2223 clocks = <&gpucc GPU_CC_AHB_CLK>, 2224 <&gpucc GPU_CC_CX_GMU_CLK>, 2225 <&gpucc GPU_CC_CXO_CLK>, 2226 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2227 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2228 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 2229 2230 power-domains = <&gpucc GPU_CX_GDSC>, 2231 <&gpucc GPU_GX_GDSC>; 2232 power-domain-names = "cx", "gx"; 2233 2234 iommus = <&adreno_smmu 5 0xc00>; 2235 2236 operating-points-v2 = <&gmu_opp_table>; 2237 2238 gmu_opp_table: opp-table { 2239 compatible = "operating-points-v2"; 2240 2241 opp-200000000 { 2242 opp-hz = /bits/ 64 <200000000>; 2243 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2244 }; 2245 2246 opp-500000000 { 2247 opp-hz = /bits/ 64 <500000000>; 2248 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2249 }; 2250 }; 2251 }; 2252 2253 gpucc: clock-controller@2c90000 { 2254 compatible = "qcom,sc8180x-gpucc"; 2255 reg = <0 0x02c90000 0 0x9000>; 2256 clocks = <&rpmhcc RPMH_CXO_CLK>, 2257 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2258 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2259 clock-names = "bi_tcxo", 2260 "gcc_gpu_gpll0_clk_src", 2261 "gcc_gpu_gpll0_div_clk_src"; 2262 #clock-cells = <1>; 2263 #reset-cells = <1>; 2264 #power-domain-cells = <1>; 2265 }; 2266 2267 adreno_smmu: iommu@2ca0000 { 2268 compatible = "qcom,sc8180x-smmu-500", "qcom,adreno-smmu", 2269 "qcom,smmu-500", "arm,mmu-500"; 2270 reg = <0 0x02ca0000 0 0x10000>; 2271 #iommu-cells = <2>; 2272 #global-interrupts = <1>; 2273 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 2274 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2275 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2276 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2277 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2278 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2279 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2280 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2281 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; 2282 clocks = <&gpucc GPU_CC_AHB_CLK>, 2283 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2284 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 2285 clock-names = "ahb", "bus", "iface"; 2286 2287 power-domains = <&gpucc GPU_CX_GDSC>; 2288 }; 2289 2290 tlmm: pinctrl@3100000 { 2291 compatible = "qcom,sc8180x-tlmm"; 2292 reg = <0 0x03100000 0 0x300000>, 2293 <0 0x03500000 0 0x700000>, 2294 <0 0x03d00000 0 0x300000>; 2295 reg-names = "west", "east", "south"; 2296 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2297 gpio-controller; 2298 #gpio-cells = <2>; 2299 interrupt-controller; 2300 #interrupt-cells = <2>; 2301 gpio-ranges = <&tlmm 0 0 191>; 2302 wakeup-parent = <&pdc>; 2303 }; 2304 2305 remoteproc_mpss: remoteproc@4080000 { 2306 compatible = "qcom,sc8180x-mpss-pas"; 2307 reg = <0x0 0x04080000 0x0 0x4040>; 2308 2309 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2310 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2311 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2312 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2313 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2314 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2315 interrupt-names = "wdog", "fatal", "ready", "handover", 2316 "stop-ack", "shutdown-ack"; 2317 2318 clocks = <&rpmhcc RPMH_CXO_CLK>; 2319 clock-names = "xo"; 2320 2321 power-domains = <&rpmhpd SC8180X_CX>, 2322 <&rpmhpd SC8180X_MSS>; 2323 power-domain-names = "cx", "mss"; 2324 2325 qcom,qmp = <&aoss_qmp>; 2326 2327 qcom,smem-states = <&modem_smp2p_out 0>; 2328 qcom,smem-state-names = "stop"; 2329 2330 glink-edge { 2331 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2332 label = "modem"; 2333 qcom,remote-pid = <1>; 2334 mboxes = <&apss_shared 12>; 2335 }; 2336 }; 2337 2338 remoteproc_cdsp: remoteproc@8300000 { 2339 compatible = "qcom,sc8180x-cdsp-pas"; 2340 reg = <0x0 0x08300000 0x0 0x4040>; 2341 2342 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2343 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2344 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2345 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2346 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2347 interrupt-names = "wdog", "fatal", "ready", 2348 "handover", "stop-ack"; 2349 2350 clocks = <&rpmhcc RPMH_CXO_CLK>; 2351 clock-names = "xo"; 2352 2353 power-domains = <&rpmhpd SC8180X_CX>; 2354 power-domain-names = "cx"; 2355 2356 qcom,qmp = <&aoss_qmp>; 2357 2358 qcom,smem-states = <&cdsp_smp2p_out 0>; 2359 qcom,smem-state-names = "stop"; 2360 2361 status = "disabled"; 2362 2363 glink-edge { 2364 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 2365 label = "cdsp"; 2366 qcom,remote-pid = <5>; 2367 mboxes = <&apss_shared 4>; 2368 }; 2369 }; 2370 2371 usb_prim_hsphy: phy@88e2000 { 2372 compatible = "qcom,sc8180x-usb-hs-phy", 2373 "qcom,usb-snps-hs-7nm-phy"; 2374 reg = <0 0x088e2000 0 0x400>; 2375 clocks = <&rpmhcc RPMH_CXO_CLK>; 2376 clock-names = "ref"; 2377 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2378 2379 #phy-cells = <0>; 2380 2381 status = "disabled"; 2382 }; 2383 2384 usb_sec_hsphy: phy@88e3000 { 2385 compatible = "qcom,sc8180x-usb-hs-phy", 2386 "qcom,usb-snps-hs-7nm-phy"; 2387 reg = <0 0x088e3000 0 0x400>; 2388 clocks = <&rpmhcc RPMH_CXO_CLK>; 2389 clock-names = "ref"; 2390 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2391 2392 #phy-cells = <0>; 2393 2394 status = "disabled"; 2395 }; 2396 2397 usb_prim_qmpphy: phy@88e9000 { 2398 compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; 2399 reg = <0 0x088e9000 0 0x18c>, 2400 <0 0x088e8000 0 0x38>, 2401 <0 0x088ea000 0 0x40>; 2402 reg-names = "reg-base", "dp_com"; 2403 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2404 <&rpmhcc RPMH_CXO_CLK>, 2405 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2406 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2407 clock-names = "aux", 2408 "ref_clk_src", 2409 "ref", 2410 "com_aux"; 2411 resets = <&gcc GCC_USB3_DP_PHY_PRIM_SP0_BCR>, 2412 <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>; 2413 reset-names = "phy", "common"; 2414 2415 #clock-cells = <1>; 2416 #address-cells = <2>; 2417 #size-cells = <2>; 2418 ranges; 2419 2420 status = "disabled"; 2421 2422 ports { 2423 #address-cells = <1>; 2424 #size-cells = <0>; 2425 2426 port@0 { 2427 reg = <0>; 2428 2429 usb_prim_qmpphy_out: endpoint {}; 2430 }; 2431 2432 port@2 { 2433 reg = <2>; 2434 2435 usb_prim_qmpphy_dp_in: endpoint {}; 2436 }; 2437 }; 2438 2439 usb_prim_ssphy: usb3-phy@88e9200 { 2440 reg = <0 0x088e9200 0 0x200>, 2441 <0 0x088e9400 0 0x200>, 2442 <0 0x088e9c00 0 0x218>, 2443 <0 0x088e9600 0 0x200>, 2444 <0 0x088e9800 0 0x200>, 2445 <0 0x088e9a00 0 0x100>; 2446 #phy-cells = <0>; 2447 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2448 clock-names = "pipe0"; 2449 clock-output-names = "usb3_prim_phy_pipe_clk_src"; 2450 }; 2451 2452 usb_prim_dpphy: dp-phy@88ea200 { 2453 reg = <0 0x088ea200 0 0x200>, 2454 <0 0x088ea400 0 0x200>, 2455 <0 0x088eaa00 0 0x200>, 2456 <0 0x088ea600 0 0x200>, 2457 <0 0x088ea800 0 0x200>; 2458 #clock-cells = <1>; 2459 #phy-cells = <0>; 2460 }; 2461 }; 2462 2463 usb_sec_qmpphy: phy@88ee000 { 2464 compatible = "qcom,sc8180x-qmp-usb3-dp-phy"; 2465 reg = <0 0x088ee000 0 0x18c>, 2466 <0 0x088ed000 0 0x10>, 2467 <0 0x088ef000 0 0x40>; 2468 reg-names = "reg-base", "dp_com"; 2469 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2470 <&rpmhcc RPMH_CXO_CLK>, 2471 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 2472 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2473 clock-names = "aux", 2474 "ref_clk_src", 2475 "ref", 2476 "com_aux"; 2477 resets = <&gcc GCC_USB3_DP_PHY_SEC_BCR>, 2478 <&gcc GCC_USB3_PHY_SEC_BCR>; 2479 reset-names = "phy", "common"; 2480 2481 #clock-cells = <1>; 2482 #address-cells = <2>; 2483 #size-cells = <2>; 2484 ranges; 2485 2486 status = "disabled"; 2487 2488 ports { 2489 #address-cells = <1>; 2490 #size-cells = <0>; 2491 2492 port@0 { 2493 reg = <0>; 2494 2495 usb_sec_qmpphy_out: endpoint {}; 2496 }; 2497 2498 port@2 { 2499 reg = <2>; 2500 2501 usb_sec_qmpphy_dp_in: endpoint {}; 2502 }; 2503 }; 2504 2505 usb_sec_ssphy: usb3-phy@88e9200 { 2506 reg = <0 0x088ee200 0 0x200>, 2507 <0 0x088ee400 0 0x200>, 2508 <0 0x088eec00 0 0x218>, 2509 <0 0x088ee600 0 0x200>, 2510 <0 0x088ee800 0 0x200>, 2511 <0 0x088eea00 0 0x100>; 2512 #phy-cells = <0>; 2513 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2514 clock-names = "pipe0"; 2515 clock-output-names = "usb3_sec_phy_pipe_clk_src"; 2516 }; 2517 2518 usb_sec_dpphy: dp-phy@88ef200 { 2519 reg = <0 0x088ef200 0 0x200>, 2520 <0 0x088ef400 0 0x200>, 2521 <0 0x088efa00 0 0x200>, 2522 <0 0x088ef600 0 0x200>, 2523 <0 0x088ef800 0 0x200>; 2524 #clock-cells = <1>; 2525 #phy-cells = <0>; 2526 clock-output-names = "qmp_dptx1_phy_pll_link_clk", 2527 "qmp_dptx1_phy_pll_vco_div_clk"; 2528 }; 2529 }; 2530 2531 system-cache-controller@9200000 { 2532 compatible = "qcom,sc8180x-llcc"; 2533 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, 2534 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, 2535 <0 0x09600000 0 0x50000>; 2536 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2537 "llcc3_base", "llcc_broadcast_base"; 2538 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 2539 }; 2540 2541 gem_noc: interconnect@9680000 { 2542 compatible = "qcom,sc8180x-gem-noc"; 2543 reg = <0 0x09680000 0 0x58200>; 2544 #interconnect-cells = <2>; 2545 qcom,bcm-voters = <&apps_bcm_voter>; 2546 }; 2547 2548 usb_prim: usb@a6f8800 { 2549 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3"; 2550 reg = <0 0x0a6f8800 0 0x400>; 2551 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2552 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 2553 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 2554 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 2555 interrupt-names = "hs_phy_irq", 2556 "ss_phy_irq", 2557 "dm_hs_phy_irq", 2558 "dp_hs_phy_irq"; 2559 2560 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2561 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2562 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2563 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2564 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2565 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 2566 clock-names = "cfg_noc", 2567 "core", 2568 "iface", 2569 "sleep", 2570 "mock_utmi", 2571 "xo"; 2572 resets = <&gcc GCC_USB30_PRIM_BCR>; 2573 power-domains = <&gcc USB30_PRIM_GDSC>; 2574 2575 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, 2576 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 2577 interconnect-names = "usb-ddr", "apps-usb"; 2578 2579 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2580 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2581 assigned-clock-rates = <19200000>, <200000000>; 2582 2583 #address-cells = <2>; 2584 #size-cells = <2>; 2585 ranges; 2586 dma-ranges; 2587 2588 status = "disabled"; 2589 2590 usb_prim_dwc3: usb@a600000 { 2591 compatible = "snps,dwc3"; 2592 reg = <0 0x0a600000 0 0xcd00>; 2593 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2594 iommus = <&apps_smmu 0x140 0>; 2595 snps,dis_u2_susphy_quirk; 2596 snps,dis_enblslpm_quirk; 2597 phys = <&usb_prim_hsphy>, <&usb_prim_ssphy>; 2598 phy-names = "usb2-phy", "usb3-phy"; 2599 2600 port { 2601 usb_prim_role_switch: endpoint { 2602 }; 2603 }; 2604 }; 2605 }; 2606 2607 usb_sec: usb@a8f8800 { 2608 compatible = "qcom,sc8180x-dwc3", "qcom,dwc3"; 2609 reg = <0 0x0a8f8800 0 0x400>; 2610 2611 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2612 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2613 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2614 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2615 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2616 <&gcc GCC_USB3_SEC_CLKREF_CLK>; 2617 clock-names = "cfg_noc", 2618 "core", 2619 "iface", 2620 "sleep", 2621 "mock_utmi", 2622 "xo"; 2623 resets = <&gcc GCC_USB30_SEC_BCR>; 2624 power-domains = <&gcc USB30_SEC_GDSC>; 2625 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2626 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 2627 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 2628 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 2629 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2630 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2631 2632 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2633 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2634 assigned-clock-rates = <19200000>, <200000000>; 2635 2636 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, 2637 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; 2638 interconnect-names = "usb-ddr", "apps-usb"; 2639 2640 #address-cells = <2>; 2641 #size-cells = <2>; 2642 ranges; 2643 dma-ranges; 2644 2645 status = "disabled"; 2646 2647 usb_sec_dwc3: usb@a800000 { 2648 compatible = "snps,dwc3"; 2649 reg = <0 0x0a800000 0 0xcd00>; 2650 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2651 iommus = <&apps_smmu 0x160 0>; 2652 snps,dis_u2_susphy_quirk; 2653 snps,dis_enblslpm_quirk; 2654 phys = <&usb_sec_hsphy>, <&usb_sec_ssphy>; 2655 phy-names = "usb2-phy", "usb3-phy"; 2656 2657 port { 2658 usb_sec_role_switch: endpoint { 2659 }; 2660 }; 2661 }; 2662 }; 2663 2664 mdss: mdss@ae00000 { 2665 compatible = "qcom,sc8180x-mdss"; 2666 reg = <0 0x0ae00000 0 0x1000>; 2667 reg-names = "mdss"; 2668 2669 power-domains = <&dispcc MDSS_GDSC>; 2670 2671 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2672 <&gcc GCC_DISP_HF_AXI_CLK>, 2673 <&gcc GCC_DISP_SF_AXI_CLK>, 2674 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2675 clock-names = "iface", 2676 "bus", 2677 "nrt_bus", 2678 "core"; 2679 2680 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2681 2682 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2683 interrupt-controller; 2684 #interrupt-cells = <1>; 2685 2686 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>, 2687 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>; 2688 interconnect-names = "mdp0-mem", "mdp1-mem"; 2689 2690 iommus = <&apps_smmu 0x800 0x420>; 2691 2692 #address-cells = <2>; 2693 #size-cells = <2>; 2694 ranges; 2695 2696 status = "disabled"; 2697 2698 mdss_mdp: mdp@ae01000 { 2699 compatible = "qcom,sc8180x-dpu"; 2700 reg = <0 0x0ae01000 0 0x8f000>, 2701 <0 0x0aeb0000 0 0x2008>; 2702 reg-names = "mdp", "vbif"; 2703 2704 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2705 <&gcc GCC_DISP_HF_AXI_CLK>, 2706 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2707 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2708 clock-names = "iface", 2709 "bus", 2710 "core", 2711 "vsync"; 2712 2713 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 2714 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2715 assigned-clock-rates = <460000000>, 2716 <19200000>; 2717 2718 operating-points-v2 = <&mdp_opp_table>; 2719 power-domains = <&rpmhpd SC8180X_MMCX>; 2720 2721 interrupt-parent = <&mdss>; 2722 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 2723 2724 ports { 2725 #address-cells = <1>; 2726 #size-cells = <0>; 2727 2728 port@0 { 2729 reg = <0>; 2730 dpu_intf0_out: endpoint { 2731 remote-endpoint = <&dp0_in>; 2732 }; 2733 }; 2734 2735 port@1 { 2736 reg = <1>; 2737 dpu_intf1_out: endpoint { 2738 remote-endpoint = <&mdss_dsi0_in>; 2739 }; 2740 }; 2741 2742 port@2 { 2743 reg = <2>; 2744 dpu_intf2_out: endpoint { 2745 remote-endpoint = <&mdss_dsi1_in>; 2746 }; 2747 }; 2748 2749 port@4 { 2750 reg = <4>; 2751 dpu_intf4_out: endpoint { 2752 remote-endpoint = <&dp1_in>; 2753 }; 2754 }; 2755 2756 port@5 { 2757 reg = <5>; 2758 dpu_intf5_out: endpoint { 2759 remote-endpoint = <&edp_in>; 2760 }; 2761 }; 2762 }; 2763 2764 mdp_opp_table: opp-table { 2765 compatible = "operating-points-v2"; 2766 2767 opp-200000000 { 2768 opp-hz = /bits/ 64 <200000000>; 2769 required-opps = <&rpmhpd_opp_low_svs>; 2770 }; 2771 2772 opp-300000000 { 2773 opp-hz = /bits/ 64 <300000000>; 2774 required-opps = <&rpmhpd_opp_svs>; 2775 }; 2776 2777 opp-345000000 { 2778 opp-hz = /bits/ 64 <345000000>; 2779 required-opps = <&rpmhpd_opp_svs_l1>; 2780 }; 2781 2782 opp-460000000 { 2783 opp-hz = /bits/ 64 <460000000>; 2784 required-opps = <&rpmhpd_opp_nom>; 2785 }; 2786 }; 2787 }; 2788 2789 mdss_dsi0: dsi@ae94000 { 2790 compatible = "qcom,mdss-dsi-ctrl"; 2791 reg = <0 0x0ae94000 0 0x400>; 2792 reg-names = "dsi_ctrl"; 2793 2794 interrupt-parent = <&mdss>; 2795 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 2796 2797 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2798 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2799 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2800 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2801 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2802 <&gcc GCC_DISP_HF_AXI_CLK>; 2803 clock-names = "byte", 2804 "byte_intf", 2805 "pixel", 2806 "core", 2807 "iface", 2808 "bus"; 2809 2810 operating-points-v2 = <&dsi_opp_table>; 2811 power-domains = <&rpmhpd SC8180X_MMCX>; 2812 2813 phys = <&mdss_dsi0_phy>; 2814 phy-names = "dsi"; 2815 2816 status = "disabled"; 2817 2818 ports { 2819 #address-cells = <1>; 2820 #size-cells = <0>; 2821 2822 port@0 { 2823 reg = <0>; 2824 mdss_dsi0_in: endpoint { 2825 remote-endpoint = <&dpu_intf1_out>; 2826 }; 2827 }; 2828 2829 port@1 { 2830 reg = <1>; 2831 mdss_dsi0_out: endpoint { 2832 }; 2833 }; 2834 }; 2835 2836 dsi_opp_table: opp-table { 2837 compatible = "operating-points-v2"; 2838 2839 opp-187500000 { 2840 opp-hz = /bits/ 64 <187500000>; 2841 required-opps = <&rpmhpd_opp_low_svs>; 2842 }; 2843 2844 opp-300000000 { 2845 opp-hz = /bits/ 64 <300000000>; 2846 required-opps = <&rpmhpd_opp_svs>; 2847 }; 2848 2849 opp-358000000 { 2850 opp-hz = /bits/ 64 <358000000>; 2851 required-opps = <&rpmhpd_opp_svs_l1>; 2852 }; 2853 }; 2854 }; 2855 2856 mdss_dsi0_phy: dsi-phy@ae94400 { 2857 compatible = "qcom,dsi-phy-7nm"; 2858 reg = <0 0x0ae94400 0 0x200>, 2859 <0 0x0ae94600 0 0x280>, 2860 <0 0x0ae94900 0 0x260>; 2861 reg-names = "dsi_phy", 2862 "dsi_phy_lane", 2863 "dsi_pll"; 2864 2865 #clock-cells = <1>; 2866 #phy-cells = <0>; 2867 2868 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2869 <&rpmhcc RPMH_CXO_CLK>; 2870 clock-names = "iface", "ref"; 2871 2872 status = "disabled"; 2873 }; 2874 2875 mdss_dsi1: dsi@ae96000 { 2876 compatible = "qcom,mdss-dsi-ctrl"; 2877 reg = <0 0x0ae96000 0 0x400>; 2878 reg-names = "dsi_ctrl"; 2879 2880 interrupt-parent = <&mdss>; 2881 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 2882 2883 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2884 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2885 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2886 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2887 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2888 <&gcc GCC_DISP_HF_AXI_CLK>; 2889 clock-names = "byte", 2890 "byte_intf", 2891 "pixel", 2892 "core", 2893 "iface", 2894 "bus"; 2895 2896 operating-points-v2 = <&dsi_opp_table>; 2897 power-domains = <&rpmhpd SC8180X_MMCX>; 2898 2899 phys = <&mdss_dsi1_phy>; 2900 phy-names = "dsi"; 2901 2902 status = "disabled"; 2903 2904 ports { 2905 #address-cells = <1>; 2906 #size-cells = <0>; 2907 2908 port@0 { 2909 reg = <0>; 2910 mdss_dsi1_in: endpoint { 2911 remote-endpoint = <&dpu_intf2_out>; 2912 }; 2913 }; 2914 2915 port@1 { 2916 reg = <1>; 2917 mdss_dsi1_out: endpoint { 2918 }; 2919 }; 2920 }; 2921 }; 2922 2923 mdss_dsi1_phy: dsi-phy@ae96400 { 2924 compatible = "qcom,dsi-phy-7nm"; 2925 reg = <0 0x0ae96400 0 0x200>, 2926 <0 0x0ae96600 0 0x280>, 2927 <0 0x0ae96900 0 0x260>; 2928 reg-names = "dsi_phy", 2929 "dsi_phy_lane", 2930 "dsi_pll"; 2931 2932 #clock-cells = <1>; 2933 #phy-cells = <0>; 2934 2935 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2936 <&rpmhcc RPMH_CXO_CLK>; 2937 clock-names = "iface", "ref"; 2938 2939 status = "disabled"; 2940 }; 2941 2942 mdss_dp0: displayport-controller@ae90000 { 2943 compatible = "qcom,sc8180x-dp"; 2944 reg = <0 0xae90000 0 0x200>, 2945 <0 0xae90200 0 0x200>, 2946 <0 0xae90400 0 0x600>, 2947 <0 0xae90a00 0 0x400>; 2948 interrupt-parent = <&mdss>; 2949 interrupts = <12>; 2950 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2951 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 2952 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 2953 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 2954 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 2955 clock-names = "core_iface", 2956 "core_aux", 2957 "ctrl_link", 2958 "ctrl_link_iface", 2959 "stream_pixel"; 2960 2961 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 2962 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 2963 assigned-clock-parents = <&usb_prim_dpphy 0>, <&usb_prim_dpphy 1>; 2964 2965 phys = <&usb_prim_dpphy>; 2966 phy-names = "dp"; 2967 2968 #sound-dai-cells = <0>; 2969 2970 operating-points-v2 = <&dp0_opp_table>; 2971 power-domains = <&rpmhpd SC8180X_MMCX>; 2972 2973 status = "disabled"; 2974 2975 ports { 2976 #address-cells = <1>; 2977 #size-cells = <0>; 2978 2979 port@0 { 2980 reg = <0>; 2981 dp0_in: endpoint { 2982 remote-endpoint = <&dpu_intf0_out>; 2983 }; 2984 }; 2985 2986 port@1 { 2987 reg = <1>; 2988 mdss_dp0_out: endpoint { 2989 }; 2990 }; 2991 }; 2992 2993 dp0_opp_table: opp-table { 2994 compatible = "operating-points-v2"; 2995 2996 opp-160000000 { 2997 opp-hz = /bits/ 64 <160000000>; 2998 required-opps = <&rpmhpd_opp_low_svs>; 2999 }; 3000 3001 opp-270000000 { 3002 opp-hz = /bits/ 64 <270000000>; 3003 required-opps = <&rpmhpd_opp_svs>; 3004 }; 3005 3006 opp-540000000 { 3007 opp-hz = /bits/ 64 <540000000>; 3008 required-opps = <&rpmhpd_opp_svs_l1>; 3009 }; 3010 3011 opp-810000000 { 3012 opp-hz = /bits/ 64 <810000000>; 3013 required-opps = <&rpmhpd_opp_nom>; 3014 }; 3015 }; 3016 }; 3017 3018 mdss_dp1: displayport-controller@ae98000 { 3019 compatible = "qcom,sc8180x-dp"; 3020 reg = <0 0xae98000 0 0x200>, 3021 <0 0xae98200 0 0x200>, 3022 <0 0xae98400 0 0x600>, 3023 <0 0xae98a00 0 0x400>; 3024 interrupt-parent = <&mdss>; 3025 interrupts = <13>; 3026 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3027 <&dispcc DISP_CC_MDSS_DP_AUX1_CLK>, 3028 <&dispcc DISP_CC_MDSS_DP_LINK1_CLK>, 3029 <&dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>, 3030 <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>; 3031 clock-names = "core_iface", 3032 "core_aux", 3033 "ctrl_link", 3034 "ctrl_link_iface", 3035 "stream_pixel"; 3036 3037 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>, 3038 <&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>; 3039 assigned-clock-parents = <&usb_sec_dpphy 0>, <&usb_sec_dpphy 1>; 3040 3041 phys = <&usb_sec_dpphy>; 3042 phy-names = "dp"; 3043 3044 #sound-dai-cells = <0>; 3045 3046 operating-points-v2 = <&dp0_opp_table>; 3047 power-domains = <&rpmhpd SC8180X_MMCX>; 3048 3049 status = "disabled"; 3050 3051 ports { 3052 #address-cells = <1>; 3053 #size-cells = <0>; 3054 3055 port@0 { 3056 reg = <0>; 3057 dp1_in: endpoint { 3058 remote-endpoint = <&dpu_intf4_out>; 3059 }; 3060 }; 3061 3062 port@1 { 3063 reg = <1>; 3064 mdss_dp1_out: endpoint { 3065 }; 3066 }; 3067 }; 3068 3069 dp1_opp_table: opp-table { 3070 compatible = "operating-points-v2"; 3071 3072 opp-160000000 { 3073 opp-hz = /bits/ 64 <160000000>; 3074 required-opps = <&rpmhpd_opp_low_svs>; 3075 }; 3076 3077 opp-270000000 { 3078 opp-hz = /bits/ 64 <270000000>; 3079 required-opps = <&rpmhpd_opp_svs>; 3080 }; 3081 3082 opp-540000000 { 3083 opp-hz = /bits/ 64 <540000000>; 3084 required-opps = <&rpmhpd_opp_svs_l1>; 3085 }; 3086 3087 opp-810000000 { 3088 opp-hz = /bits/ 64 <810000000>; 3089 required-opps = <&rpmhpd_opp_nom>; 3090 }; 3091 }; 3092 }; 3093 3094 mdss_edp: displayport-controller@ae9a000 { 3095 compatible = "qcom,sc8180x-edp"; 3096 reg = <0 0xae9a000 0 0x200>, 3097 <0 0xae9a200 0 0x200>, 3098 <0 0xae9a400 0 0x600>, 3099 <0 0xae9aa00 0 0x400>; 3100 interrupt-parent = <&mdss>; 3101 interrupts = <14>; 3102 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3103 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3104 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 3105 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 3106 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 3107 clock-names = "core_iface", 3108 "core_aux", 3109 "ctrl_link", 3110 "ctrl_link_iface", 3111 "stream_pixel"; 3112 3113 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 3114 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 3115 assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>; 3116 3117 phys = <&edp_phy>; 3118 phy-names = "dp"; 3119 3120 #sound-dai-cells = <0>; 3121 3122 operating-points-v2 = <&edp_opp_table>; 3123 power-domains = <&rpmhpd SC8180X_MMCX>; 3124 3125 status = "disabled"; 3126 3127 ports { 3128 #address-cells = <1>; 3129 #size-cells = <0>; 3130 3131 port@0 { 3132 reg = <0>; 3133 edp_in: endpoint { 3134 remote-endpoint = <&dpu_intf5_out>; 3135 }; 3136 }; 3137 }; 3138 3139 edp_opp_table: opp-table { 3140 compatible = "operating-points-v2"; 3141 3142 opp-160000000 { 3143 opp-hz = /bits/ 64 <160000000>; 3144 required-opps = <&rpmhpd_opp_low_svs>; 3145 }; 3146 3147 opp-270000000 { 3148 opp-hz = /bits/ 64 <270000000>; 3149 required-opps = <&rpmhpd_opp_svs>; 3150 }; 3151 3152 opp-540000000 { 3153 opp-hz = /bits/ 64 <540000000>; 3154 required-opps = <&rpmhpd_opp_svs_l1>; 3155 }; 3156 3157 opp-810000000 { 3158 opp-hz = /bits/ 64 <810000000>; 3159 required-opps = <&rpmhpd_opp_nom>; 3160 }; 3161 }; 3162 }; 3163 }; 3164 3165 edp_phy: phy@aec2a00 { 3166 compatible = "qcom,sc8180x-edp-phy"; 3167 reg = <0 0x0aec2a00 0 0x1c0>, 3168 <0 0x0aec2200 0 0xa0>, 3169 <0 0x0aec2600 0 0xa0>, 3170 <0 0x0aec2000 0 0x19c>; 3171 3172 clocks = <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 3173 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3174 clock-names = "aux", "cfg_ahb"; 3175 3176 power-domains = <&dispcc MDSS_GDSC>; 3177 3178 #clock-cells = <1>; 3179 #phy-cells = <0>; 3180 }; 3181 3182 dispcc: clock-controller@af00000 { 3183 compatible = "qcom,sc8180x-dispcc"; 3184 reg = <0 0x0af00000 0 0x20000>; 3185 clocks = <&rpmhcc RPMH_CXO_CLK>, 3186 <&sleep_clk>, 3187 <&usb_prim_dpphy 0>, 3188 <&usb_prim_dpphy 1>, 3189 <&usb_sec_dpphy 0>, 3190 <&usb_sec_dpphy 1>, 3191 <&edp_phy 0>, 3192 <&edp_phy 1>; 3193 clock-names = "bi_tcxo", 3194 "sleep_clk", 3195 "dp_phy_pll_link_clk", 3196 "dp_phy_pll_vco_div_clk", 3197 "dptx1_phy_pll_link_clk", 3198 "dptx1_phy_pll_vco_div_clk", 3199 "edp_phy_pll_link_clk", 3200 "edp_phy_pll_vco_div_clk"; 3201 power-domains = <&rpmhpd SC8180X_MMCX>; 3202 #clock-cells = <1>; 3203 #reset-cells = <1>; 3204 #power-domain-cells = <1>; 3205 }; 3206 3207 pdc: interrupt-controller@b220000 { 3208 compatible = "qcom,sc8180x-pdc", "qcom,pdc"; 3209 reg = <0 0x0b220000 0 0x30000>; 3210 qcom,pdc-ranges = <0 480 94>, <94 609 31>; 3211 #interrupt-cells = <2>; 3212 interrupt-parent = <&intc>; 3213 interrupt-controller; 3214 }; 3215 3216 tsens0: thermal-sensor@c263000 { 3217 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2"; 3218 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3219 <0 0x0c222000 0 0x1ff>; /* SROT */ 3220 #qcom,sensors = <16>; 3221 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3222 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3223 interrupt-names = "uplow", "critical"; 3224 #thermal-sensor-cells = <1>; 3225 }; 3226 3227 tsens1: thermal-sensor@c265000 { 3228 compatible = "qcom,sc8180x-tsens", "qcom,tsens-v2"; 3229 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3230 <0 0x0c223000 0 0x1ff>; /* SROT */ 3231 #qcom,sensors = <9>; 3232 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3233 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3234 interrupt-names = "uplow", "critical"; 3235 #thermal-sensor-cells = <1>; 3236 }; 3237 3238 aoss_qmp: power-controller@c300000 { 3239 compatible = "qcom,sc8180x-aoss-qmp", "qcom,aoss-qmp"; 3240 reg = <0x0 0x0c300000 0x0 0x100000>; 3241 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3242 mboxes = <&apss_shared 0>; 3243 3244 #clock-cells = <0>; 3245 #power-domain-cells = <1>; 3246 }; 3247 3248 spmi_bus: spmi@c440000 { 3249 compatible = "qcom,spmi-pmic-arb"; 3250 reg = <0x0 0x0c440000 0x0 0x0001100>, 3251 <0x0 0x0c600000 0x0 0x2000000>, 3252 <0x0 0x0e600000 0x0 0x0100000>, 3253 <0x0 0x0e700000 0x0 0x00a0000>, 3254 <0x0 0x0c40a000 0x0 0x0026000>; 3255 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3256 interrupt-names = "periph_irq"; 3257 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3258 qcom,ee = <0>; 3259 qcom,channel = <0>; 3260 #address-cells = <2>; 3261 #size-cells = <0>; 3262 interrupt-controller; 3263 #interrupt-cells = <4>; 3264 }; 3265 3266 apps_smmu: iommu@15000000 { 3267 compatible = "qcom,sc8180x-smmu-500", "arm,mmu-500"; 3268 reg = <0 0x15000000 0 0x100000>; 3269 #iommu-cells = <2>; 3270 #global-interrupts = <1>; 3271 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3272 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3273 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3274 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3275 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3276 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3277 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3278 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3279 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3280 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3281 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3282 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3283 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3284 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3285 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3286 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3287 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3288 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3289 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3290 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3291 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3292 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3293 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3294 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3295 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3296 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3297 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3298 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3299 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3300 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3301 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3302 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3303 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3304 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3305 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3306 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3307 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3308 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3309 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3310 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3311 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3312 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3313 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3314 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3315 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3316 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3317 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3318 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3319 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3320 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3321 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3322 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3323 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3324 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3325 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3326 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3327 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3328 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3329 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3330 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3331 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3332 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3333 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3334 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3335 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3336 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3337 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3338 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3339 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3340 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3341 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3342 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3343 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3344 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3345 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3346 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3347 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3348 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3349 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3350 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3351 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3352 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3353 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 3354 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3355 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 3356 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 3357 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 3358 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 3359 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 3360 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 3361 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 3362 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 3363 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 3364 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 3365 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 3366 <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>, 3367 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>, 3368 <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 3369 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>, 3370 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, 3371 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 3372 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, 3373 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>, 3374 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 3375 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 3376 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 3377 <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>; 3378 3379 }; 3380 3381 remoteproc_adsp: remoteproc@17300000 { 3382 compatible = "qcom,sc8180x-adsp-pas"; 3383 reg = <0x0 0x17300000 0x0 0x4040>; 3384 3385 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 3386 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3387 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3388 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3389 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3390 interrupt-names = "wdog", "fatal", "ready", 3391 "handover", "stop-ack"; 3392 3393 clocks = <&rpmhcc RPMH_CXO_CLK>; 3394 clock-names = "xo"; 3395 3396 power-domains = <&rpmhpd SC8180X_CX>; 3397 power-domain-names = "cx"; 3398 3399 qcom,qmp = <&aoss_qmp>; 3400 3401 qcom,smem-states = <&adsp_smp2p_out 0>; 3402 qcom,smem-state-names = "stop"; 3403 3404 status = "disabled"; 3405 3406 remoteproc_adsp_glink: glink-edge { 3407 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 3408 label = "lpass"; 3409 qcom,remote-pid = <2>; 3410 mboxes = <&apss_shared 8>; 3411 }; 3412 }; 3413 3414 intc: interrupt-controller@17a00000 { 3415 compatible = "arm,gic-v3"; 3416 interrupt-controller; 3417 #interrupt-cells = <3>; 3418 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3419 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3420 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3421 }; 3422 3423 apss_shared: mailbox@17c00000 { 3424 compatible = "qcom,sc8180x-apss-shared"; 3425 reg = <0x0 0x17c00000 0x0 0x1000>; 3426 #mbox-cells = <1>; 3427 }; 3428 3429 timer@17c20000 { 3430 compatible = "arm,armv7-timer-mem"; 3431 reg = <0x0 0x17c20000 0x0 0x1000>; 3432 3433 #address-cells = <1>; 3434 #size-cells = <1>; 3435 ranges = <0 0 0 0x20000000>; 3436 3437 frame@17c21000 { 3438 reg = <0x17c21000 0x1000>, 3439 <0x17c22000 0x1000>; 3440 frame-number = <0>; 3441 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3442 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3443 }; 3444 3445 frame@17c23000 { 3446 reg = <0x17c23000 0x1000>; 3447 frame-number = <1>; 3448 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3449 status = "disabled"; 3450 }; 3451 3452 frame@17c25000 { 3453 reg = <0x17c25000 0x1000>; 3454 frame-number = <2>; 3455 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3456 status = "disabled"; 3457 }; 3458 3459 frame@17c27000 { 3460 reg = <0x17c26000 0x1000>; 3461 frame-number = <3>; 3462 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3463 status = "disabled"; 3464 }; 3465 3466 frame@17c29000 { 3467 reg = <0x17c29000 0x1000>; 3468 frame-number = <4>; 3469 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3470 status = "disabled"; 3471 }; 3472 3473 frame@17c2b000 { 3474 reg = <0x17c2b000 0x1000>; 3475 frame-number = <5>; 3476 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3477 status = "disabled"; 3478 }; 3479 3480 frame@17c2d000 { 3481 reg = <0x17c2d000 0x1000>; 3482 frame-number = <6>; 3483 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3484 status = "disabled"; 3485 }; 3486 }; 3487 3488 apps_rsc: rsc@18200000 { 3489 compatible = "qcom,rpmh-rsc"; 3490 reg = <0x0 0x18200000 0x0 0x10000>, 3491 <0x0 0x18210000 0x0 0x10000>, 3492 <0x0 0x18220000 0x0 0x10000>; 3493 reg-names = "drv-0", "drv-1", "drv-2"; 3494 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3495 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3496 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3497 qcom,tcs-offset = <0xd00>; 3498 qcom,drv-id = <2>; 3499 qcom,tcs-config = <ACTIVE_TCS 2>, 3500 <SLEEP_TCS 1>, 3501 <WAKE_TCS 1>, 3502 <CONTROL_TCS 0>; 3503 label = "apps_rsc"; 3504 power-domains = <&CLUSTER_PD>; 3505 3506 apps_bcm_voter: bcm-voter { 3507 compatible = "qcom,bcm-voter"; 3508 }; 3509 3510 rpmhcc: clock-controller { 3511 compatible = "qcom,sc8180x-rpmh-clk"; 3512 #clock-cells = <1>; 3513 clock-names = "xo"; 3514 clocks = <&xo_board_clk>; 3515 }; 3516 3517 rpmhpd: power-controller { 3518 compatible = "qcom,sc8180x-rpmhpd"; 3519 #power-domain-cells = <1>; 3520 operating-points-v2 = <&rpmhpd_opp_table>; 3521 3522 rpmhpd_opp_table: opp-table { 3523 compatible = "operating-points-v2"; 3524 3525 rpmhpd_opp_ret: opp1 { 3526 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3527 }; 3528 3529 rpmhpd_opp_min_svs: opp2 { 3530 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3531 }; 3532 3533 rpmhpd_opp_low_svs: opp3 { 3534 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3535 }; 3536 3537 rpmhpd_opp_svs: opp4 { 3538 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3539 }; 3540 3541 rpmhpd_opp_svs_l1: opp5 { 3542 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3543 }; 3544 3545 rpmhpd_opp_nom: opp6 { 3546 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3547 }; 3548 3549 rpmhpd_opp_nom_l1: opp7 { 3550 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3551 }; 3552 3553 rpmhpd_opp_nom_l2: opp8 { 3554 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3555 }; 3556 3557 rpmhpd_opp_turbo: opp9 { 3558 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3559 }; 3560 3561 rpmhpd_opp_turbo_l1: opp10 { 3562 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3563 }; 3564 }; 3565 }; 3566 }; 3567 3568 osm_l3: interconnect@18321000 { 3569 compatible = "qcom,sc8180x-osm-l3", "qcom,osm-l3"; 3570 reg = <0 0x18321000 0 0x1400>; 3571 3572 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3573 clock-names = "xo", "alternate"; 3574 3575 #interconnect-cells = <1>; 3576 }; 3577 3578 lmh@18350800 { 3579 compatible = "qcom,sc8180x-lmh"; 3580 reg = <0 0x18350800 0 0x400>; 3581 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 3582 cpus = <&CPU4>; 3583 qcom,lmh-temp-arm-millicelsius = <65000>; 3584 qcom,lmh-temp-low-millicelsius = <94500>; 3585 qcom,lmh-temp-high-millicelsius = <95000>; 3586 interrupt-controller; 3587 #interrupt-cells = <1>; 3588 }; 3589 3590 lmh@18358800 { 3591 compatible = "qcom,sc8180x-lmh"; 3592 reg = <0 0x18358800 0 0x400>; 3593 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 3594 cpus = <&CPU0>; 3595 qcom,lmh-temp-arm-millicelsius = <65000>; 3596 qcom,lmh-temp-low-millicelsius = <94500>; 3597 qcom,lmh-temp-high-millicelsius = <95000>; 3598 interrupt-controller; 3599 #interrupt-cells = <1>; 3600 }; 3601 3602 cpufreq_hw: cpufreq@18323000 { 3603 compatible = "qcom,cpufreq-hw"; 3604 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 3605 reg-names = "freq-domain0", "freq-domain1"; 3606 3607 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3608 clock-names = "xo", "alternate"; 3609 3610 #freq-domain-cells = <1>; 3611 #clock-cells = <1>; 3612 }; 3613 3614 wifi: wifi@18800000 { 3615 compatible = "qcom,wcn3990-wifi"; 3616 reg = <0 0x18800000 0 0x800000>; 3617 reg-names = "membase"; 3618 clock-names = "cxo_ref_clk_pin"; 3619 clocks = <&rpmhcc RPMH_RF_CLK2>; 3620 interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 3621 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 3622 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 3623 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 3624 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3625 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3626 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 3627 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3628 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3629 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3630 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3631 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 3632 iommus = <&apps_smmu 0x0640 0x1>; 3633 qcom,msa-fixed-perm; 3634 status = "disabled"; 3635 }; 3636 }; 3637 3638 thermal-zones { 3639 cpu0-thermal { 3640 polling-delay-passive = <250>; 3641 polling-delay = <1000>; 3642 3643 thermal-sensors = <&tsens0 1>; 3644 3645 trips { 3646 cpu-crit { 3647 temperature = <110000>; 3648 hysteresis = <1000>; 3649 type = "critical"; 3650 }; 3651 }; 3652 }; 3653 3654 cpu1-thermal { 3655 polling-delay-passive = <250>; 3656 polling-delay = <1000>; 3657 3658 thermal-sensors = <&tsens0 2>; 3659 3660 trips { 3661 cpu-crit { 3662 temperature = <110000>; 3663 hysteresis = <1000>; 3664 type = "critical"; 3665 }; 3666 }; 3667 }; 3668 3669 cpu2-thermal { 3670 polling-delay-passive = <250>; 3671 polling-delay = <1000>; 3672 3673 thermal-sensors = <&tsens0 3>; 3674 3675 trips { 3676 cpu-crit { 3677 temperature = <110000>; 3678 hysteresis = <1000>; 3679 type = "critical"; 3680 }; 3681 }; 3682 }; 3683 3684 cpu3-thermal { 3685 polling-delay-passive = <250>; 3686 polling-delay = <1000>; 3687 3688 thermal-sensors = <&tsens0 4>; 3689 3690 trips { 3691 cpu-crit { 3692 temperature = <110000>; 3693 hysteresis = <1000>; 3694 type = "critical"; 3695 }; 3696 }; 3697 }; 3698 3699 cpu4-top-thermal { 3700 polling-delay-passive = <250>; 3701 polling-delay = <1000>; 3702 3703 thermal-sensors = <&tsens0 7>; 3704 3705 trips { 3706 cpu-crit { 3707 temperature = <110000>; 3708 hysteresis = <1000>; 3709 type = "critical"; 3710 }; 3711 }; 3712 }; 3713 3714 cpu5-top-thermal { 3715 polling-delay-passive = <250>; 3716 polling-delay = <1000>; 3717 3718 thermal-sensors = <&tsens0 8>; 3719 3720 trips { 3721 cpu-crit { 3722 temperature = <110000>; 3723 hysteresis = <1000>; 3724 type = "critical"; 3725 }; 3726 }; 3727 }; 3728 3729 cpu6-top-thermal { 3730 polling-delay-passive = <250>; 3731 polling-delay = <1000>; 3732 3733 thermal-sensors = <&tsens0 9>; 3734 3735 trips { 3736 cpu-crit { 3737 temperature = <110000>; 3738 hysteresis = <1000>; 3739 type = "critical"; 3740 }; 3741 }; 3742 }; 3743 3744 cpu7-top-thermal { 3745 polling-delay-passive = <250>; 3746 polling-delay = <1000>; 3747 3748 thermal-sensors = <&tsens0 10>; 3749 3750 trips { 3751 cpu-crit { 3752 temperature = <110000>; 3753 hysteresis = <1000>; 3754 type = "critical"; 3755 }; 3756 }; 3757 }; 3758 3759 cpu4-bottom-thermal { 3760 polling-delay-passive = <250>; 3761 polling-delay = <1000>; 3762 3763 thermal-sensors = <&tsens0 11>; 3764 3765 trips { 3766 cpu-crit { 3767 temperature = <110000>; 3768 hysteresis = <1000>; 3769 type = "critical"; 3770 }; 3771 }; 3772 }; 3773 3774 cpu5-bottom-thermal { 3775 polling-delay-passive = <250>; 3776 polling-delay = <1000>; 3777 3778 thermal-sensors = <&tsens0 12>; 3779 3780 trips { 3781 cpu-crit { 3782 temperature = <110000>; 3783 hysteresis = <1000>; 3784 type = "critical"; 3785 }; 3786 }; 3787 }; 3788 3789 cpu6-bottom-thermal { 3790 polling-delay-passive = <250>; 3791 polling-delay = <1000>; 3792 3793 thermal-sensors = <&tsens0 13>; 3794 3795 trips { 3796 cpu-crit { 3797 temperature = <110000>; 3798 hysteresis = <1000>; 3799 type = "critical"; 3800 }; 3801 }; 3802 }; 3803 3804 cpu7-bottom-thermal { 3805 polling-delay-passive = <250>; 3806 polling-delay = <1000>; 3807 3808 thermal-sensors = <&tsens0 14>; 3809 3810 trips { 3811 cpu-crit { 3812 temperature = <110000>; 3813 hysteresis = <1000>; 3814 type = "critical"; 3815 }; 3816 }; 3817 }; 3818 3819 aoss0-thermal { 3820 polling-delay-passive = <250>; 3821 polling-delay = <1000>; 3822 3823 thermal-sensors = <&tsens0 0>; 3824 3825 trips { 3826 trip-point0 { 3827 temperature = <90000>; 3828 hysteresis = <2000>; 3829 type = "hot"; 3830 }; 3831 }; 3832 }; 3833 3834 cluster0-thermal { 3835 polling-delay-passive = <250>; 3836 polling-delay = <1000>; 3837 3838 thermal-sensors = <&tsens0 5>; 3839 3840 trips { 3841 cluster-crit { 3842 temperature = <110000>; 3843 hysteresis = <2000>; 3844 type = "critical"; 3845 }; 3846 }; 3847 }; 3848 3849 cluster1-thermal { 3850 polling-delay-passive = <250>; 3851 polling-delay = <1000>; 3852 3853 thermal-sensors = <&tsens0 6>; 3854 3855 trips { 3856 cluster-crit { 3857 temperature = <110000>; 3858 hysteresis = <2000>; 3859 type = "critical"; 3860 }; 3861 }; 3862 }; 3863 3864 gpu-top-thermal { 3865 polling-delay-passive = <250>; 3866 polling-delay = <1000>; 3867 3868 thermal-sensors = <&tsens0 15>; 3869 3870 trips { 3871 trip-point0 { 3872 temperature = <90000>; 3873 hysteresis = <2000>; 3874 type = "hot"; 3875 }; 3876 }; 3877 }; 3878 3879 aoss1-thermal { 3880 polling-delay-passive = <250>; 3881 polling-delay = <1000>; 3882 3883 thermal-sensors = <&tsens1 0>; 3884 3885 trips { 3886 trip-point0 { 3887 temperature = <90000>; 3888 hysteresis = <2000>; 3889 type = "hot"; 3890 }; 3891 }; 3892 }; 3893 3894 wlan-thermal { 3895 polling-delay-passive = <250>; 3896 polling-delay = <1000>; 3897 3898 thermal-sensors = <&tsens1 1>; 3899 3900 trips { 3901 trip-point0 { 3902 temperature = <90000>; 3903 hysteresis = <2000>; 3904 type = "hot"; 3905 }; 3906 }; 3907 }; 3908 3909 video-thermal { 3910 polling-delay-passive = <250>; 3911 polling-delay = <1000>; 3912 3913 thermal-sensors = <&tsens1 2>; 3914 3915 trips { 3916 trip-point0 { 3917 temperature = <90000>; 3918 hysteresis = <2000>; 3919 type = "hot"; 3920 }; 3921 }; 3922 }; 3923 3924 mem-thermal { 3925 polling-delay-passive = <250>; 3926 polling-delay = <1000>; 3927 3928 thermal-sensors = <&tsens1 3>; 3929 3930 trips { 3931 trip-point0 { 3932 temperature = <90000>; 3933 hysteresis = <2000>; 3934 type = "hot"; 3935 }; 3936 }; 3937 }; 3938 3939 q6-hvx-thermal { 3940 polling-delay-passive = <250>; 3941 polling-delay = <1000>; 3942 3943 thermal-sensors = <&tsens1 4>; 3944 3945 trips { 3946 trip-point0 { 3947 temperature = <90000>; 3948 hysteresis = <2000>; 3949 type = "hot"; 3950 }; 3951 }; 3952 }; 3953 3954 camera-thermal { 3955 polling-delay-passive = <250>; 3956 polling-delay = <1000>; 3957 3958 thermal-sensors = <&tsens1 5>; 3959 3960 trips { 3961 trip-point0 { 3962 temperature = <90000>; 3963 hysteresis = <2000>; 3964 type = "hot"; 3965 }; 3966 }; 3967 }; 3968 3969 compute-thermal { 3970 polling-delay-passive = <250>; 3971 polling-delay = <1000>; 3972 3973 thermal-sensors = <&tsens1 6>; 3974 3975 trips { 3976 trip-point0 { 3977 temperature = <90000>; 3978 hysteresis = <2000>; 3979 type = "hot"; 3980 }; 3981 }; 3982 }; 3983 3984 mdm-dsp-thermal { 3985 polling-delay-passive = <250>; 3986 polling-delay = <1000>; 3987 3988 thermal-sensors = <&tsens1 7>; 3989 3990 trips { 3991 trip-point0 { 3992 temperature = <90000>; 3993 hysteresis = <2000>; 3994 type = "hot"; 3995 }; 3996 }; 3997 }; 3998 3999 npu-thermal { 4000 polling-delay-passive = <250>; 4001 polling-delay = <1000>; 4002 4003 thermal-sensors = <&tsens1 8>; 4004 4005 trips { 4006 trip-point0 { 4007 temperature = <90000>; 4008 hysteresis = <2000>; 4009 type = "hot"; 4010 }; 4011 }; 4012 }; 4013 4014 gpu-bottom-thermal { 4015 polling-delay-passive = <250>; 4016 polling-delay = <1000>; 4017 4018 thermal-sensors = <&tsens1 11>; 4019 4020 trips { 4021 trip-point0 { 4022 temperature = <90000>; 4023 hysteresis = <2000>; 4024 type = "hot"; 4025 }; 4026 }; 4027 }; 4028 }; 4029 4030 timer { 4031 compatible = "arm,armv8-timer"; 4032 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 4033 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 4034 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 4035 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 4036 }; 4037}; 4038