1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 10#include <dt-bindings/clock/qcom,gcc-sc7280.h> 11#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 13#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 14#include <dt-bindings/clock/qcom,rpmh.h> 15#include <dt-bindings/clock/qcom,videocc-sc7280.h> 16#include <dt-bindings/dma/qcom-gpi.h> 17#include <dt-bindings/firmware/qcom,scm.h> 18#include <dt-bindings/gpio/gpio.h> 19#include <dt-bindings/interconnect/qcom,icc.h> 20#include <dt-bindings/interconnect/qcom,osm-l3.h> 21#include <dt-bindings/interconnect/qcom,sc7280.h> 22#include <dt-bindings/interrupt-controller/arm-gic.h> 23#include <dt-bindings/mailbox/qcom-ipcc.h> 24#include <dt-bindings/phy/phy-qcom-qmp.h> 25#include <dt-bindings/power/qcom-rpmpd.h> 26#include <dt-bindings/reset/qcom,sdm845-aoss.h> 27#include <dt-bindings/reset/qcom,sdm845-pdc.h> 28#include <dt-bindings/soc/qcom,apr.h> 29#include <dt-bindings/soc/qcom,rpmh-rsc.h> 30#include <dt-bindings/sound/qcom,lpass.h> 31#include <dt-bindings/sound/qcom,q6afe.h> 32#include <dt-bindings/sound/qcom,q6asm.h> 33#include <dt-bindings/thermal/thermal.h> 34 35/ { 36 interrupt-parent = <&intc>; 37 38 #address-cells = <2>; 39 #size-cells = <2>; 40 41 chosen { }; 42 43 aliases { 44 i2c0 = &i2c0; 45 i2c1 = &i2c1; 46 i2c2 = &i2c2; 47 i2c3 = &i2c3; 48 i2c4 = &i2c4; 49 i2c5 = &i2c5; 50 i2c6 = &i2c6; 51 i2c7 = &i2c7; 52 i2c8 = &i2c8; 53 i2c9 = &i2c9; 54 i2c10 = &i2c10; 55 i2c11 = &i2c11; 56 i2c12 = &i2c12; 57 i2c13 = &i2c13; 58 i2c14 = &i2c14; 59 i2c15 = &i2c15; 60 mmc1 = &sdhc_1; 61 mmc2 = &sdhc_2; 62 spi0 = &spi0; 63 spi1 = &spi1; 64 spi2 = &spi2; 65 spi3 = &spi3; 66 spi4 = &spi4; 67 spi5 = &spi5; 68 spi6 = &spi6; 69 spi7 = &spi7; 70 spi8 = &spi8; 71 spi9 = &spi9; 72 spi10 = &spi10; 73 spi11 = &spi11; 74 spi12 = &spi12; 75 spi13 = &spi13; 76 spi14 = &spi14; 77 spi15 = &spi15; 78 }; 79 80 clocks { 81 xo_board: xo-board { 82 compatible = "fixed-clock"; 83 clock-frequency = <76800000>; 84 #clock-cells = <0>; 85 }; 86 87 sleep_clk: sleep-clk { 88 compatible = "fixed-clock"; 89 clock-frequency = <32764>; 90 #clock-cells = <0>; 91 }; 92 }; 93 94 reserved-memory { 95 #address-cells = <2>; 96 #size-cells = <2>; 97 ranges; 98 99 wlan_ce_mem: wlan-ce@4cd000 { 100 no-map; 101 reg = <0x0 0x004cd000 0x0 0x1000>; 102 }; 103 104 hyp_mem: hyp@80000000 { 105 reg = <0x0 0x80000000 0x0 0x600000>; 106 no-map; 107 }; 108 109 xbl_mem: xbl@80600000 { 110 reg = <0x0 0x80600000 0x0 0x200000>; 111 no-map; 112 }; 113 114 aop_mem: aop@80800000 { 115 reg = <0x0 0x80800000 0x0 0x60000>; 116 no-map; 117 }; 118 119 aop_cmd_db_mem: aop-cmd-db@80860000 { 120 reg = <0x0 0x80860000 0x0 0x20000>; 121 compatible = "qcom,cmd-db"; 122 no-map; 123 }; 124 125 reserved_xbl_uefi_log: xbl-uefi-res@80880000 { 126 reg = <0x0 0x80884000 0x0 0x10000>; 127 no-map; 128 }; 129 130 sec_apps_mem: sec-apps@808ff000 { 131 reg = <0x0 0x808ff000 0x0 0x1000>; 132 no-map; 133 }; 134 135 smem_mem: smem@80900000 { 136 reg = <0x0 0x80900000 0x0 0x200000>; 137 no-map; 138 }; 139 140 cpucp_mem: cpucp@80b00000 { 141 no-map; 142 reg = <0x0 0x80b00000 0x0 0x100000>; 143 }; 144 145 wlan_fw_mem: wlan-fw@80c00000 { 146 reg = <0x0 0x80c00000 0x0 0xc00000>; 147 no-map; 148 }; 149 150 adsp_mem: adsp@86700000 { 151 reg = <0x0 0x86700000 0x0 0x2800000>; 152 no-map; 153 }; 154 155 video_mem: video@8b200000 { 156 reg = <0x0 0x8b200000 0x0 0x500000>; 157 no-map; 158 }; 159 160 cdsp_mem: cdsp@88f00000 { 161 reg = <0x0 0x88f00000 0x0 0x1e00000>; 162 no-map; 163 }; 164 165 ipa_fw_mem: ipa-fw@8b700000 { 166 reg = <0 0x8b700000 0 0x10000>; 167 no-map; 168 }; 169 170 gpu_zap_mem: zap@8b71a000 { 171 reg = <0 0x8b71a000 0 0x2000>; 172 no-map; 173 }; 174 175 mpss_mem: mpss@8b800000 { 176 reg = <0x0 0x8b800000 0x0 0xf600000>; 177 no-map; 178 }; 179 180 wpss_mem: wpss@9ae00000 { 181 reg = <0x0 0x9ae00000 0x0 0x1900000>; 182 no-map; 183 }; 184 185 rmtfs_mem: rmtfs@9c900000 { 186 compatible = "qcom,rmtfs-mem"; 187 reg = <0x0 0x9c900000 0x0 0x280000>; 188 no-map; 189 190 qcom,client-id = <1>; 191 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 192 }; 193 }; 194 195 cpus { 196 #address-cells = <2>; 197 #size-cells = <0>; 198 199 cpu0: cpu@0 { 200 device_type = "cpu"; 201 compatible = "qcom,kryo"; 202 reg = <0x0 0x0>; 203 clocks = <&cpufreq_hw 0>; 204 enable-method = "psci"; 205 power-domains = <&cpu_pd0>; 206 power-domain-names = "psci"; 207 next-level-cache = <&l2_0>; 208 operating-points-v2 = <&cpu0_opp_table>; 209 capacity-dmips-mhz = <1024>; 210 dynamic-power-coefficient = <100>; 211 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 212 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 213 qcom,freq-domain = <&cpufreq_hw 0>; 214 #cooling-cells = <2>; 215 l2_0: l2-cache { 216 compatible = "cache"; 217 cache-level = <2>; 218 cache-unified; 219 next-level-cache = <&l3_0>; 220 l3_0: l3-cache { 221 compatible = "cache"; 222 cache-level = <3>; 223 cache-unified; 224 }; 225 }; 226 }; 227 228 cpu1: cpu@100 { 229 device_type = "cpu"; 230 compatible = "qcom,kryo"; 231 reg = <0x0 0x100>; 232 clocks = <&cpufreq_hw 0>; 233 enable-method = "psci"; 234 power-domains = <&cpu_pd1>; 235 power-domain-names = "psci"; 236 next-level-cache = <&l2_100>; 237 operating-points-v2 = <&cpu0_opp_table>; 238 capacity-dmips-mhz = <1024>; 239 dynamic-power-coefficient = <100>; 240 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 241 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 242 qcom,freq-domain = <&cpufreq_hw 0>; 243 #cooling-cells = <2>; 244 l2_100: l2-cache { 245 compatible = "cache"; 246 cache-level = <2>; 247 cache-unified; 248 next-level-cache = <&l3_0>; 249 }; 250 }; 251 252 cpu2: cpu@200 { 253 device_type = "cpu"; 254 compatible = "qcom,kryo"; 255 reg = <0x0 0x200>; 256 clocks = <&cpufreq_hw 0>; 257 enable-method = "psci"; 258 power-domains = <&cpu_pd2>; 259 power-domain-names = "psci"; 260 next-level-cache = <&l2_200>; 261 operating-points-v2 = <&cpu0_opp_table>; 262 capacity-dmips-mhz = <1024>; 263 dynamic-power-coefficient = <100>; 264 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 265 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 266 qcom,freq-domain = <&cpufreq_hw 0>; 267 #cooling-cells = <2>; 268 l2_200: l2-cache { 269 compatible = "cache"; 270 cache-level = <2>; 271 cache-unified; 272 next-level-cache = <&l3_0>; 273 }; 274 }; 275 276 cpu3: cpu@300 { 277 device_type = "cpu"; 278 compatible = "qcom,kryo"; 279 reg = <0x0 0x300>; 280 clocks = <&cpufreq_hw 0>; 281 enable-method = "psci"; 282 power-domains = <&cpu_pd3>; 283 power-domain-names = "psci"; 284 next-level-cache = <&l2_300>; 285 operating-points-v2 = <&cpu0_opp_table>; 286 capacity-dmips-mhz = <1024>; 287 dynamic-power-coefficient = <100>; 288 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 289 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 290 qcom,freq-domain = <&cpufreq_hw 0>; 291 #cooling-cells = <2>; 292 l2_300: l2-cache { 293 compatible = "cache"; 294 cache-level = <2>; 295 cache-unified; 296 next-level-cache = <&l3_0>; 297 }; 298 }; 299 300 cpu4: cpu@400 { 301 device_type = "cpu"; 302 compatible = "qcom,kryo"; 303 reg = <0x0 0x400>; 304 clocks = <&cpufreq_hw 1>; 305 enable-method = "psci"; 306 power-domains = <&cpu_pd4>; 307 power-domain-names = "psci"; 308 next-level-cache = <&l2_400>; 309 operating-points-v2 = <&cpu4_opp_table>; 310 capacity-dmips-mhz = <1946>; 311 dynamic-power-coefficient = <520>; 312 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 313 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 314 qcom,freq-domain = <&cpufreq_hw 1>; 315 #cooling-cells = <2>; 316 l2_400: l2-cache { 317 compatible = "cache"; 318 cache-level = <2>; 319 cache-unified; 320 next-level-cache = <&l3_0>; 321 }; 322 }; 323 324 cpu5: cpu@500 { 325 device_type = "cpu"; 326 compatible = "qcom,kryo"; 327 reg = <0x0 0x500>; 328 clocks = <&cpufreq_hw 1>; 329 enable-method = "psci"; 330 power-domains = <&cpu_pd5>; 331 power-domain-names = "psci"; 332 next-level-cache = <&l2_500>; 333 operating-points-v2 = <&cpu4_opp_table>; 334 capacity-dmips-mhz = <1946>; 335 dynamic-power-coefficient = <520>; 336 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 337 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 338 qcom,freq-domain = <&cpufreq_hw 1>; 339 #cooling-cells = <2>; 340 l2_500: l2-cache { 341 compatible = "cache"; 342 cache-level = <2>; 343 cache-unified; 344 next-level-cache = <&l3_0>; 345 }; 346 }; 347 348 cpu6: cpu@600 { 349 device_type = "cpu"; 350 compatible = "qcom,kryo"; 351 reg = <0x0 0x600>; 352 clocks = <&cpufreq_hw 1>; 353 enable-method = "psci"; 354 power-domains = <&cpu_pd6>; 355 power-domain-names = "psci"; 356 next-level-cache = <&l2_600>; 357 operating-points-v2 = <&cpu4_opp_table>; 358 capacity-dmips-mhz = <1946>; 359 dynamic-power-coefficient = <520>; 360 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 361 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 362 qcom,freq-domain = <&cpufreq_hw 1>; 363 #cooling-cells = <2>; 364 l2_600: l2-cache { 365 compatible = "cache"; 366 cache-level = <2>; 367 cache-unified; 368 next-level-cache = <&l3_0>; 369 }; 370 }; 371 372 cpu7: cpu@700 { 373 device_type = "cpu"; 374 compatible = "qcom,kryo"; 375 reg = <0x0 0x700>; 376 clocks = <&cpufreq_hw 2>; 377 enable-method = "psci"; 378 power-domains = <&cpu_pd7>; 379 power-domain-names = "psci"; 380 next-level-cache = <&l2_700>; 381 operating-points-v2 = <&cpu7_opp_table>; 382 capacity-dmips-mhz = <1985>; 383 dynamic-power-coefficient = <552>; 384 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 385 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 386 qcom,freq-domain = <&cpufreq_hw 2>; 387 #cooling-cells = <2>; 388 l2_700: l2-cache { 389 compatible = "cache"; 390 cache-level = <2>; 391 cache-unified; 392 next-level-cache = <&l3_0>; 393 }; 394 }; 395 396 cpu-map { 397 cluster0 { 398 core0 { 399 cpu = <&cpu0>; 400 }; 401 402 core1 { 403 cpu = <&cpu1>; 404 }; 405 406 core2 { 407 cpu = <&cpu2>; 408 }; 409 410 core3 { 411 cpu = <&cpu3>; 412 }; 413 414 core4 { 415 cpu = <&cpu4>; 416 }; 417 418 core5 { 419 cpu = <&cpu5>; 420 }; 421 422 core6 { 423 cpu = <&cpu6>; 424 }; 425 426 core7 { 427 cpu = <&cpu7>; 428 }; 429 }; 430 }; 431 432 idle-states { 433 entry-method = "psci"; 434 435 little_cpu_sleep_0: cpu-sleep-0-0 { 436 compatible = "arm,idle-state"; 437 idle-state-name = "little-power-down"; 438 arm,psci-suspend-param = <0x40000003>; 439 entry-latency-us = <549>; 440 exit-latency-us = <901>; 441 min-residency-us = <1774>; 442 local-timer-stop; 443 }; 444 445 little_cpu_sleep_1: cpu-sleep-0-1 { 446 compatible = "arm,idle-state"; 447 idle-state-name = "little-rail-power-down"; 448 arm,psci-suspend-param = <0x40000004>; 449 entry-latency-us = <702>; 450 exit-latency-us = <915>; 451 min-residency-us = <4001>; 452 local-timer-stop; 453 }; 454 455 big_cpu_sleep_0: cpu-sleep-1-0 { 456 compatible = "arm,idle-state"; 457 idle-state-name = "big-power-down"; 458 arm,psci-suspend-param = <0x40000003>; 459 entry-latency-us = <523>; 460 exit-latency-us = <1244>; 461 min-residency-us = <2207>; 462 local-timer-stop; 463 }; 464 465 big_cpu_sleep_1: cpu-sleep-1-1 { 466 compatible = "arm,idle-state"; 467 idle-state-name = "big-rail-power-down"; 468 arm,psci-suspend-param = <0x40000004>; 469 entry-latency-us = <526>; 470 exit-latency-us = <1854>; 471 min-residency-us = <5555>; 472 local-timer-stop; 473 }; 474 }; 475 476 domain_idle_states: domain-idle-states { 477 cluster_sleep_apss_off: cluster-sleep-0 { 478 compatible = "domain-idle-state"; 479 arm,psci-suspend-param = <0x41000044>; 480 entry-latency-us = <2752>; 481 exit-latency-us = <3048>; 482 min-residency-us = <6118>; 483 }; 484 485 cluster_sleep_cx_ret: cluster-sleep-1 { 486 compatible = "domain-idle-state"; 487 arm,psci-suspend-param = <0x41001344>; 488 entry-latency-us = <3263>; 489 exit-latency-us = <4562>; 490 min-residency-us = <8467>; 491 }; 492 493 cluster_sleep_llcc_off: cluster-sleep-2 { 494 compatible = "domain-idle-state"; 495 arm,psci-suspend-param = <0x4100b344>; 496 entry-latency-us = <3638>; 497 exit-latency-us = <6562>; 498 min-residency-us = <9826>; 499 }; 500 }; 501 }; 502 503 cpu0_opp_table: opp-table-cpu0 { 504 compatible = "operating-points-v2"; 505 opp-shared; 506 507 cpu0_opp_300mhz: opp-300000000 { 508 opp-hz = /bits/ 64 <300000000>; 509 opp-peak-kBps = <800000 9600000>; 510 }; 511 512 cpu0_opp_691mhz: opp-691200000 { 513 opp-hz = /bits/ 64 <691200000>; 514 opp-peak-kBps = <800000 17817600>; 515 }; 516 517 cpu0_opp_806mhz: opp-806400000 { 518 opp-hz = /bits/ 64 <806400000>; 519 opp-peak-kBps = <800000 20889600>; 520 }; 521 522 cpu0_opp_941mhz: opp-940800000 { 523 opp-hz = /bits/ 64 <940800000>; 524 opp-peak-kBps = <1804000 24576000>; 525 }; 526 527 cpu0_opp_1152mhz: opp-1152000000 { 528 opp-hz = /bits/ 64 <1152000000>; 529 opp-peak-kBps = <2188000 27033600>; 530 }; 531 532 cpu0_opp_1325mhz: opp-1324800000 { 533 opp-hz = /bits/ 64 <1324800000>; 534 opp-peak-kBps = <2188000 33792000>; 535 }; 536 537 cpu0_opp_1517mhz: opp-1516800000 { 538 opp-hz = /bits/ 64 <1516800000>; 539 opp-peak-kBps = <3072000 38092800>; 540 }; 541 542 cpu0_opp_1651mhz: opp-1651200000 { 543 opp-hz = /bits/ 64 <1651200000>; 544 opp-peak-kBps = <3072000 41779200>; 545 }; 546 547 cpu0_opp_1805mhz: opp-1804800000 { 548 opp-hz = /bits/ 64 <1804800000>; 549 opp-peak-kBps = <4068000 48537600>; 550 }; 551 552 cpu0_opp_1958mhz: opp-1958400000 { 553 opp-hz = /bits/ 64 <1958400000>; 554 opp-peak-kBps = <4068000 48537600>; 555 }; 556 557 cpu0_opp_2016mhz: opp-2016000000 { 558 opp-hz = /bits/ 64 <2016000000>; 559 opp-peak-kBps = <6220000 48537600>; 560 }; 561 }; 562 563 cpu4_opp_table: opp-table-cpu4 { 564 compatible = "operating-points-v2"; 565 opp-shared; 566 567 cpu4_opp_691mhz: opp-691200000 { 568 opp-hz = /bits/ 64 <691200000>; 569 opp-peak-kBps = <1804000 9600000>; 570 }; 571 572 cpu4_opp_941mhz: opp-940800000 { 573 opp-hz = /bits/ 64 <940800000>; 574 opp-peak-kBps = <2188000 17817600>; 575 }; 576 577 cpu4_opp_1229mhz: opp-1228800000 { 578 opp-hz = /bits/ 64 <1228800000>; 579 opp-peak-kBps = <4068000 24576000>; 580 }; 581 582 cpu4_opp_1344mhz: opp-1344000000 { 583 opp-hz = /bits/ 64 <1344000000>; 584 opp-peak-kBps = <4068000 24576000>; 585 }; 586 587 cpu4_opp_1517mhz: opp-1516800000 { 588 opp-hz = /bits/ 64 <1516800000>; 589 opp-peak-kBps = <4068000 24576000>; 590 }; 591 592 cpu4_opp_1651mhz: opp-1651200000 { 593 opp-hz = /bits/ 64 <1651200000>; 594 opp-peak-kBps = <6220000 38092800>; 595 }; 596 597 cpu4_opp_1901mhz: opp-1900800000 { 598 opp-hz = /bits/ 64 <1900800000>; 599 opp-peak-kBps = <6220000 44851200>; 600 }; 601 602 cpu4_opp_2054mhz: opp-2054400000 { 603 opp-hz = /bits/ 64 <2054400000>; 604 opp-peak-kBps = <6220000 44851200>; 605 }; 606 607 cpu4_opp_2112mhz: opp-2112000000 { 608 opp-hz = /bits/ 64 <2112000000>; 609 opp-peak-kBps = <6220000 44851200>; 610 }; 611 612 cpu4_opp_2131mhz: opp-2131200000 { 613 opp-hz = /bits/ 64 <2131200000>; 614 opp-peak-kBps = <6220000 44851200>; 615 }; 616 617 cpu4_opp_2208mhz: opp-2208000000 { 618 opp-hz = /bits/ 64 <2208000000>; 619 opp-peak-kBps = <6220000 44851200>; 620 }; 621 622 cpu4_opp_2400mhz: opp-2400000000 { 623 opp-hz = /bits/ 64 <2400000000>; 624 opp-peak-kBps = <12787200 48537600>; 625 }; 626 627 cpu4_opp_2611mhz: opp-2611200000 { 628 opp-hz = /bits/ 64 <2611200000>; 629 opp-peak-kBps = <12787200 48537600>; 630 }; 631 }; 632 633 cpu7_opp_table: opp-table-cpu7 { 634 compatible = "operating-points-v2"; 635 opp-shared; 636 637 cpu7_opp_806mhz: opp-806400000 { 638 opp-hz = /bits/ 64 <806400000>; 639 opp-peak-kBps = <1804000 9600000>; 640 }; 641 642 cpu7_opp_1056mhz: opp-1056000000 { 643 opp-hz = /bits/ 64 <1056000000>; 644 opp-peak-kBps = <2188000 17817600>; 645 }; 646 647 cpu7_opp_1325mhz: opp-1324800000 { 648 opp-hz = /bits/ 64 <1324800000>; 649 opp-peak-kBps = <4068000 24576000>; 650 }; 651 652 cpu7_opp_1517mhz: opp-1516800000 { 653 opp-hz = /bits/ 64 <1516800000>; 654 opp-peak-kBps = <4068000 24576000>; 655 }; 656 657 cpu7_opp_1766mhz: opp-1766400000 { 658 opp-hz = /bits/ 64 <1766400000>; 659 opp-peak-kBps = <6220000 38092800>; 660 }; 661 662 cpu7_opp_1862mhz: opp-1862400000 { 663 opp-hz = /bits/ 64 <1862400000>; 664 opp-peak-kBps = <6220000 38092800>; 665 }; 666 667 cpu7_opp_2035mhz: opp-2035200000 { 668 opp-hz = /bits/ 64 <2035200000>; 669 opp-peak-kBps = <6220000 38092800>; 670 }; 671 672 cpu7_opp_2112mhz: opp-2112000000 { 673 opp-hz = /bits/ 64 <2112000000>; 674 opp-peak-kBps = <6220000 44851200>; 675 }; 676 677 cpu7_opp_2208mhz: opp-2208000000 { 678 opp-hz = /bits/ 64 <2208000000>; 679 opp-peak-kBps = <6220000 44851200>; 680 }; 681 682 cpu7_opp_2381mhz: opp-2380800000 { 683 opp-hz = /bits/ 64 <2380800000>; 684 opp-peak-kBps = <6832000 44851200>; 685 }; 686 687 cpu7_opp_2400mhz: opp-2400000000 { 688 opp-hz = /bits/ 64 <2400000000>; 689 opp-peak-kBps = <12787200 48537600>; 690 }; 691 692 cpu7_opp_2515mhz: opp-2515200000 { 693 opp-hz = /bits/ 64 <2515200000>; 694 opp-peak-kBps = <12787200 48537600>; 695 }; 696 697 cpu7_opp_2707mhz: opp-2707200000 { 698 opp-hz = /bits/ 64 <2707200000>; 699 opp-peak-kBps = <12787200 48537600>; 700 }; 701 702 cpu7_opp_3014mhz: opp-3014400000 { 703 opp-hz = /bits/ 64 <3014400000>; 704 opp-peak-kBps = <12787200 48537600>; 705 }; 706 }; 707 708 memory@80000000 { 709 device_type = "memory"; 710 /* We expect the bootloader to fill in the size */ 711 reg = <0 0x80000000 0 0>; 712 }; 713 714 firmware { 715 scm: scm { 716 compatible = "qcom,scm-sc7280", "qcom,scm"; 717 qcom,dload-mode = <&tcsr_2 0x13000>; 718 }; 719 }; 720 721 clk_virt: interconnect { 722 compatible = "qcom,sc7280-clk-virt"; 723 #interconnect-cells = <2>; 724 qcom,bcm-voters = <&apps_bcm_voter>; 725 }; 726 727 smem { 728 compatible = "qcom,smem"; 729 memory-region = <&smem_mem>; 730 hwlocks = <&tcsr_mutex 3>; 731 }; 732 733 smp2p-adsp { 734 compatible = "qcom,smp2p"; 735 qcom,smem = <443>, <429>; 736 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 737 IPCC_MPROC_SIGNAL_SMP2P 738 IRQ_TYPE_EDGE_RISING>; 739 mboxes = <&ipcc IPCC_CLIENT_LPASS 740 IPCC_MPROC_SIGNAL_SMP2P>; 741 742 qcom,local-pid = <0>; 743 qcom,remote-pid = <2>; 744 745 adsp_smp2p_out: master-kernel { 746 qcom,entry-name = "master-kernel"; 747 #qcom,smem-state-cells = <1>; 748 }; 749 750 adsp_smp2p_in: slave-kernel { 751 qcom,entry-name = "slave-kernel"; 752 interrupt-controller; 753 #interrupt-cells = <2>; 754 }; 755 }; 756 757 smp2p-cdsp { 758 compatible = "qcom,smp2p"; 759 qcom,smem = <94>, <432>; 760 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 761 IPCC_MPROC_SIGNAL_SMP2P 762 IRQ_TYPE_EDGE_RISING>; 763 mboxes = <&ipcc IPCC_CLIENT_CDSP 764 IPCC_MPROC_SIGNAL_SMP2P>; 765 766 qcom,local-pid = <0>; 767 qcom,remote-pid = <5>; 768 769 cdsp_smp2p_out: master-kernel { 770 qcom,entry-name = "master-kernel"; 771 #qcom,smem-state-cells = <1>; 772 }; 773 774 cdsp_smp2p_in: slave-kernel { 775 qcom,entry-name = "slave-kernel"; 776 interrupt-controller; 777 #interrupt-cells = <2>; 778 }; 779 }; 780 781 smp2p-mpss { 782 compatible = "qcom,smp2p"; 783 qcom,smem = <435>, <428>; 784 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 785 IPCC_MPROC_SIGNAL_SMP2P 786 IRQ_TYPE_EDGE_RISING>; 787 mboxes = <&ipcc IPCC_CLIENT_MPSS 788 IPCC_MPROC_SIGNAL_SMP2P>; 789 790 qcom,local-pid = <0>; 791 qcom,remote-pid = <1>; 792 793 modem_smp2p_out: master-kernel { 794 qcom,entry-name = "master-kernel"; 795 #qcom,smem-state-cells = <1>; 796 }; 797 798 modem_smp2p_in: slave-kernel { 799 qcom,entry-name = "slave-kernel"; 800 interrupt-controller; 801 #interrupt-cells = <2>; 802 }; 803 804 ipa_smp2p_out: ipa-ap-to-modem { 805 qcom,entry-name = "ipa"; 806 #qcom,smem-state-cells = <1>; 807 }; 808 809 ipa_smp2p_in: ipa-modem-to-ap { 810 qcom,entry-name = "ipa"; 811 interrupt-controller; 812 #interrupt-cells = <2>; 813 }; 814 }; 815 816 smp2p-wpss { 817 compatible = "qcom,smp2p"; 818 qcom,smem = <617>, <616>; 819 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 820 IPCC_MPROC_SIGNAL_SMP2P 821 IRQ_TYPE_EDGE_RISING>; 822 mboxes = <&ipcc IPCC_CLIENT_WPSS 823 IPCC_MPROC_SIGNAL_SMP2P>; 824 825 qcom,local-pid = <0>; 826 qcom,remote-pid = <13>; 827 828 wpss_smp2p_out: master-kernel { 829 qcom,entry-name = "master-kernel"; 830 #qcom,smem-state-cells = <1>; 831 }; 832 833 wpss_smp2p_in: slave-kernel { 834 qcom,entry-name = "slave-kernel"; 835 interrupt-controller; 836 #interrupt-cells = <2>; 837 }; 838 839 wlan_smp2p_out: wlan-ap-to-wpss { 840 qcom,entry-name = "wlan"; 841 #qcom,smem-state-cells = <1>; 842 }; 843 844 wlan_smp2p_in: wlan-wpss-to-ap { 845 qcom,entry-name = "wlan"; 846 interrupt-controller; 847 #interrupt-cells = <2>; 848 }; 849 }; 850 851 pmu-a55 { 852 compatible = "arm,cortex-a55-pmu"; 853 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 854 }; 855 856 pmu-a78 { 857 compatible = "arm,cortex-a78-pmu"; 858 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 859 }; 860 861 psci { 862 compatible = "arm,psci-1.0"; 863 method = "smc"; 864 865 cpu_pd0: power-domain-cpu0 { 866 #power-domain-cells = <0>; 867 power-domains = <&cluster_pd>; 868 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 869 }; 870 871 cpu_pd1: power-domain-cpu1 { 872 #power-domain-cells = <0>; 873 power-domains = <&cluster_pd>; 874 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 875 }; 876 877 cpu_pd2: power-domain-cpu2 { 878 #power-domain-cells = <0>; 879 power-domains = <&cluster_pd>; 880 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 881 }; 882 883 cpu_pd3: power-domain-cpu3 { 884 #power-domain-cells = <0>; 885 power-domains = <&cluster_pd>; 886 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 887 }; 888 889 cpu_pd4: power-domain-cpu4 { 890 #power-domain-cells = <0>; 891 power-domains = <&cluster_pd>; 892 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 893 }; 894 895 cpu_pd5: power-domain-cpu5 { 896 #power-domain-cells = <0>; 897 power-domains = <&cluster_pd>; 898 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 899 }; 900 901 cpu_pd6: power-domain-cpu6 { 902 #power-domain-cells = <0>; 903 power-domains = <&cluster_pd>; 904 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 905 }; 906 907 cpu_pd7: power-domain-cpu7 { 908 #power-domain-cells = <0>; 909 power-domains = <&cluster_pd>; 910 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 911 }; 912 913 cluster_pd: power-domain-cluster { 914 #power-domain-cells = <0>; 915 domain-idle-states = <&cluster_sleep_apss_off &cluster_sleep_cx_ret &cluster_sleep_llcc_off>; 916 }; 917 }; 918 919 qspi_opp_table: opp-table-qspi { 920 compatible = "operating-points-v2"; 921 922 opp-75000000 { 923 opp-hz = /bits/ 64 <75000000>; 924 required-opps = <&rpmhpd_opp_low_svs>; 925 }; 926 927 opp-150000000 { 928 opp-hz = /bits/ 64 <150000000>; 929 required-opps = <&rpmhpd_opp_svs>; 930 }; 931 932 opp-200000000 { 933 opp-hz = /bits/ 64 <200000000>; 934 required-opps = <&rpmhpd_opp_svs_l1>; 935 }; 936 937 opp-300000000 { 938 opp-hz = /bits/ 64 <300000000>; 939 required-opps = <&rpmhpd_opp_nom>; 940 }; 941 }; 942 943 qup_opp_table: opp-table-qup { 944 compatible = "operating-points-v2"; 945 946 opp-75000000 { 947 opp-hz = /bits/ 64 <75000000>; 948 required-opps = <&rpmhpd_opp_low_svs>; 949 }; 950 951 opp-100000000 { 952 opp-hz = /bits/ 64 <100000000>; 953 required-opps = <&rpmhpd_opp_svs>; 954 }; 955 956 opp-128000000 { 957 opp-hz = /bits/ 64 <128000000>; 958 required-opps = <&rpmhpd_opp_nom>; 959 }; 960 }; 961 962 soc: soc@0 { 963 #address-cells = <2>; 964 #size-cells = <2>; 965 ranges = <0 0 0 0 0x10 0>; 966 dma-ranges = <0 0 0 0 0x10 0>; 967 compatible = "simple-bus"; 968 969 gcc: clock-controller@100000 { 970 compatible = "qcom,gcc-sc7280"; 971 reg = <0 0x00100000 0 0x1f0000>; 972 clocks = <&rpmhcc RPMH_CXO_CLK>, 973 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 974 <0>, <&pcie1_phy>, 975 <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, 976 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 977 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 978 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 979 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 980 "ufs_phy_tx_symbol_0_clk", 981 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 982 #clock-cells = <1>; 983 #reset-cells = <1>; 984 #power-domain-cells = <1>; 985 power-domains = <&rpmhpd SC7280_CX>; 986 }; 987 988 ipcc: mailbox@408000 { 989 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 990 reg = <0 0x00408000 0 0x1000>; 991 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 992 interrupt-controller; 993 #interrupt-cells = <3>; 994 #mbox-cells = <2>; 995 }; 996 997 qfprom: efuse@784000 { 998 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 999 reg = <0 0x00784000 0 0xa20>, 1000 <0 0x00780000 0 0xa20>, 1001 <0 0x00782000 0 0x120>, 1002 <0 0x00786000 0 0x1fff>; 1003 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 1004 clock-names = "core"; 1005 power-domains = <&rpmhpd SC7280_MX>; 1006 #address-cells = <1>; 1007 #size-cells = <1>; 1008 1009 gpu_speed_bin: gpu-speed-bin@1e9 { 1010 reg = <0x1e9 0x2>; 1011 bits = <5 8>; 1012 }; 1013 }; 1014 1015 sdhc_1: mmc@7c4000 { 1016 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 1017 pinctrl-names = "default", "sleep"; 1018 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 1019 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 1020 status = "disabled"; 1021 1022 reg = <0 0x007c4000 0 0x1000>, 1023 <0 0x007c5000 0 0x1000>; 1024 reg-names = "hc", "cqhci"; 1025 1026 iommus = <&apps_smmu 0xc0 0x0>; 1027 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 1028 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 1029 interrupt-names = "hc_irq", "pwr_irq"; 1030 1031 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1032 <&gcc GCC_SDCC1_APPS_CLK>, 1033 <&rpmhcc RPMH_CXO_CLK>; 1034 clock-names = "iface", "core", "xo"; 1035 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 1036 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 1037 interconnect-names = "sdhc-ddr","cpu-sdhc"; 1038 power-domains = <&rpmhpd SC7280_CX>; 1039 operating-points-v2 = <&sdhc1_opp_table>; 1040 1041 bus-width = <8>; 1042 supports-cqe; 1043 dma-coherent; 1044 1045 qcom,dll-config = <0x0007642c>; 1046 qcom,ddr-config = <0x80040868>; 1047 1048 mmc-ddr-1_8v; 1049 mmc-hs200-1_8v; 1050 mmc-hs400-1_8v; 1051 mmc-hs400-enhanced-strobe; 1052 1053 resets = <&gcc GCC_SDCC1_BCR>; 1054 1055 sdhc1_opp_table: opp-table { 1056 compatible = "operating-points-v2"; 1057 1058 opp-100000000 { 1059 opp-hz = /bits/ 64 <100000000>; 1060 required-opps = <&rpmhpd_opp_low_svs>; 1061 opp-peak-kBps = <1800000 400000>; 1062 opp-avg-kBps = <100000 0>; 1063 }; 1064 1065 opp-384000000 { 1066 opp-hz = /bits/ 64 <384000000>; 1067 required-opps = <&rpmhpd_opp_nom>; 1068 opp-peak-kBps = <5400000 1600000>; 1069 opp-avg-kBps = <390000 0>; 1070 }; 1071 }; 1072 }; 1073 1074 gpi_dma0: dma-controller@900000 { 1075 #dma-cells = <3>; 1076 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1077 reg = <0 0x00900000 0 0x60000>; 1078 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1079 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1080 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1081 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1082 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1083 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1084 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1085 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1086 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1087 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1088 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1089 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1090 dma-channels = <12>; 1091 dma-channel-mask = <0x7f>; 1092 iommus = <&apps_smmu 0x0136 0x0>; 1093 status = "disabled"; 1094 }; 1095 1096 qupv3_id_0: geniqup@9c0000 { 1097 compatible = "qcom,geni-se-qup"; 1098 reg = <0 0x009c0000 0 0x2000>; 1099 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1100 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1101 clock-names = "m-ahb", "s-ahb"; 1102 #address-cells = <2>; 1103 #size-cells = <2>; 1104 ranges; 1105 iommus = <&apps_smmu 0x123 0x0>; 1106 status = "disabled"; 1107 1108 i2c0: i2c@980000 { 1109 compatible = "qcom,geni-i2c"; 1110 reg = <0 0x00980000 0 0x4000>; 1111 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1112 clock-names = "se"; 1113 pinctrl-names = "default"; 1114 pinctrl-0 = <&qup_i2c0_data_clk>; 1115 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1116 #address-cells = <1>; 1117 #size-cells = <0>; 1118 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1119 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1120 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1121 interconnect-names = "qup-core", "qup-config", 1122 "qup-memory"; 1123 power-domains = <&rpmhpd SC7280_CX>; 1124 required-opps = <&rpmhpd_opp_low_svs>; 1125 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1126 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1127 dma-names = "tx", "rx"; 1128 status = "disabled"; 1129 }; 1130 1131 spi0: spi@980000 { 1132 compatible = "qcom,geni-spi"; 1133 reg = <0 0x00980000 0 0x4000>; 1134 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1135 clock-names = "se"; 1136 pinctrl-names = "default"; 1137 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1138 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1139 #address-cells = <1>; 1140 #size-cells = <0>; 1141 power-domains = <&rpmhpd SC7280_CX>; 1142 operating-points-v2 = <&qup_opp_table>; 1143 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1144 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1145 interconnect-names = "qup-core", "qup-config"; 1146 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1147 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1148 dma-names = "tx", "rx"; 1149 status = "disabled"; 1150 }; 1151 1152 uart0: serial@980000 { 1153 compatible = "qcom,geni-uart"; 1154 reg = <0 0x00980000 0 0x4000>; 1155 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1156 clock-names = "se"; 1157 pinctrl-names = "default"; 1158 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1159 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1160 power-domains = <&rpmhpd SC7280_CX>; 1161 operating-points-v2 = <&qup_opp_table>; 1162 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1163 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1164 interconnect-names = "qup-core", "qup-config"; 1165 status = "disabled"; 1166 }; 1167 1168 i2c1: i2c@984000 { 1169 compatible = "qcom,geni-i2c"; 1170 reg = <0 0x00984000 0 0x4000>; 1171 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1172 clock-names = "se"; 1173 pinctrl-names = "default"; 1174 pinctrl-0 = <&qup_i2c1_data_clk>; 1175 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1176 #address-cells = <1>; 1177 #size-cells = <0>; 1178 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1179 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1180 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1181 interconnect-names = "qup-core", "qup-config", 1182 "qup-memory"; 1183 power-domains = <&rpmhpd SC7280_CX>; 1184 required-opps = <&rpmhpd_opp_low_svs>; 1185 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1186 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1187 dma-names = "tx", "rx"; 1188 status = "disabled"; 1189 }; 1190 1191 spi1: spi@984000 { 1192 compatible = "qcom,geni-spi"; 1193 reg = <0 0x00984000 0 0x4000>; 1194 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1195 clock-names = "se"; 1196 pinctrl-names = "default"; 1197 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1198 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1199 #address-cells = <1>; 1200 #size-cells = <0>; 1201 power-domains = <&rpmhpd SC7280_CX>; 1202 operating-points-v2 = <&qup_opp_table>; 1203 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1204 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1205 interconnect-names = "qup-core", "qup-config"; 1206 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1207 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1208 dma-names = "tx", "rx"; 1209 status = "disabled"; 1210 }; 1211 1212 uart1: serial@984000 { 1213 compatible = "qcom,geni-uart"; 1214 reg = <0 0x00984000 0 0x4000>; 1215 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1216 clock-names = "se"; 1217 pinctrl-names = "default"; 1218 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1219 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1220 power-domains = <&rpmhpd SC7280_CX>; 1221 operating-points-v2 = <&qup_opp_table>; 1222 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1223 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1224 interconnect-names = "qup-core", "qup-config"; 1225 status = "disabled"; 1226 }; 1227 1228 i2c2: i2c@988000 { 1229 compatible = "qcom,geni-i2c"; 1230 reg = <0 0x00988000 0 0x4000>; 1231 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1232 clock-names = "se"; 1233 pinctrl-names = "default"; 1234 pinctrl-0 = <&qup_i2c2_data_clk>; 1235 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1236 #address-cells = <1>; 1237 #size-cells = <0>; 1238 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1239 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1240 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1241 interconnect-names = "qup-core", "qup-config", 1242 "qup-memory"; 1243 power-domains = <&rpmhpd SC7280_CX>; 1244 required-opps = <&rpmhpd_opp_low_svs>; 1245 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1246 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1247 dma-names = "tx", "rx"; 1248 status = "disabled"; 1249 }; 1250 1251 spi2: spi@988000 { 1252 compatible = "qcom,geni-spi"; 1253 reg = <0 0x00988000 0 0x4000>; 1254 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1255 clock-names = "se"; 1256 pinctrl-names = "default"; 1257 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1258 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1259 #address-cells = <1>; 1260 #size-cells = <0>; 1261 power-domains = <&rpmhpd SC7280_CX>; 1262 operating-points-v2 = <&qup_opp_table>; 1263 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1264 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1265 interconnect-names = "qup-core", "qup-config"; 1266 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1267 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1268 dma-names = "tx", "rx"; 1269 status = "disabled"; 1270 }; 1271 1272 uart2: serial@988000 { 1273 compatible = "qcom,geni-uart"; 1274 reg = <0 0x00988000 0 0x4000>; 1275 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1276 clock-names = "se"; 1277 pinctrl-names = "default"; 1278 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1279 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1280 power-domains = <&rpmhpd SC7280_CX>; 1281 operating-points-v2 = <&qup_opp_table>; 1282 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1283 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1284 interconnect-names = "qup-core", "qup-config"; 1285 status = "disabled"; 1286 }; 1287 1288 i2c3: i2c@98c000 { 1289 compatible = "qcom,geni-i2c"; 1290 reg = <0 0x0098c000 0 0x4000>; 1291 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1292 clock-names = "se"; 1293 pinctrl-names = "default"; 1294 pinctrl-0 = <&qup_i2c3_data_clk>; 1295 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1296 #address-cells = <1>; 1297 #size-cells = <0>; 1298 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1299 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1300 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1301 interconnect-names = "qup-core", "qup-config", 1302 "qup-memory"; 1303 power-domains = <&rpmhpd SC7280_CX>; 1304 required-opps = <&rpmhpd_opp_low_svs>; 1305 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1306 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1307 dma-names = "tx", "rx"; 1308 status = "disabled"; 1309 }; 1310 1311 spi3: spi@98c000 { 1312 compatible = "qcom,geni-spi"; 1313 reg = <0 0x0098c000 0 0x4000>; 1314 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1315 clock-names = "se"; 1316 pinctrl-names = "default"; 1317 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1318 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1319 #address-cells = <1>; 1320 #size-cells = <0>; 1321 power-domains = <&rpmhpd SC7280_CX>; 1322 operating-points-v2 = <&qup_opp_table>; 1323 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1324 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1325 interconnect-names = "qup-core", "qup-config"; 1326 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1327 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1328 dma-names = "tx", "rx"; 1329 status = "disabled"; 1330 }; 1331 1332 uart3: serial@98c000 { 1333 compatible = "qcom,geni-uart"; 1334 reg = <0 0x0098c000 0 0x4000>; 1335 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1336 clock-names = "se"; 1337 pinctrl-names = "default"; 1338 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1339 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1340 power-domains = <&rpmhpd SC7280_CX>; 1341 operating-points-v2 = <&qup_opp_table>; 1342 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1343 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1344 interconnect-names = "qup-core", "qup-config"; 1345 status = "disabled"; 1346 }; 1347 1348 i2c4: i2c@990000 { 1349 compatible = "qcom,geni-i2c"; 1350 reg = <0 0x00990000 0 0x4000>; 1351 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1352 clock-names = "se"; 1353 pinctrl-names = "default"; 1354 pinctrl-0 = <&qup_i2c4_data_clk>; 1355 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1356 #address-cells = <1>; 1357 #size-cells = <0>; 1358 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1359 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1360 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1361 interconnect-names = "qup-core", "qup-config", 1362 "qup-memory"; 1363 power-domains = <&rpmhpd SC7280_CX>; 1364 required-opps = <&rpmhpd_opp_low_svs>; 1365 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1366 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1367 dma-names = "tx", "rx"; 1368 status = "disabled"; 1369 }; 1370 1371 spi4: spi@990000 { 1372 compatible = "qcom,geni-spi"; 1373 reg = <0 0x00990000 0 0x4000>; 1374 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1375 clock-names = "se"; 1376 pinctrl-names = "default"; 1377 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1378 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1379 #address-cells = <1>; 1380 #size-cells = <0>; 1381 power-domains = <&rpmhpd SC7280_CX>; 1382 operating-points-v2 = <&qup_opp_table>; 1383 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1384 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1385 interconnect-names = "qup-core", "qup-config"; 1386 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1387 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1388 dma-names = "tx", "rx"; 1389 status = "disabled"; 1390 }; 1391 1392 uart4: serial@990000 { 1393 compatible = "qcom,geni-uart"; 1394 reg = <0 0x00990000 0 0x4000>; 1395 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1396 clock-names = "se"; 1397 pinctrl-names = "default"; 1398 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1399 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1400 power-domains = <&rpmhpd SC7280_CX>; 1401 operating-points-v2 = <&qup_opp_table>; 1402 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1403 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1404 interconnect-names = "qup-core", "qup-config"; 1405 status = "disabled"; 1406 }; 1407 1408 i2c5: i2c@994000 { 1409 compatible = "qcom,geni-i2c"; 1410 reg = <0 0x00994000 0 0x4000>; 1411 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1412 clock-names = "se"; 1413 pinctrl-names = "default"; 1414 pinctrl-0 = <&qup_i2c5_data_clk>; 1415 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1416 #address-cells = <1>; 1417 #size-cells = <0>; 1418 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1419 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1420 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1421 interconnect-names = "qup-core", "qup-config", 1422 "qup-memory"; 1423 power-domains = <&rpmhpd SC7280_CX>; 1424 required-opps = <&rpmhpd_opp_low_svs>; 1425 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1426 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1427 dma-names = "tx", "rx"; 1428 status = "disabled"; 1429 }; 1430 1431 spi5: spi@994000 { 1432 compatible = "qcom,geni-spi"; 1433 reg = <0 0x00994000 0 0x4000>; 1434 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1435 clock-names = "se"; 1436 pinctrl-names = "default"; 1437 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1438 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1439 #address-cells = <1>; 1440 #size-cells = <0>; 1441 power-domains = <&rpmhpd SC7280_CX>; 1442 operating-points-v2 = <&qup_opp_table>; 1443 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1444 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1445 interconnect-names = "qup-core", "qup-config"; 1446 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1447 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1448 dma-names = "tx", "rx"; 1449 status = "disabled"; 1450 }; 1451 1452 uart5: serial@994000 { 1453 compatible = "qcom,geni-debug-uart"; 1454 reg = <0 0x00994000 0 0x4000>; 1455 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1456 clock-names = "se"; 1457 pinctrl-names = "default"; 1458 pinctrl-0 = <&qup_uart5_tx>, <&qup_uart5_rx>; 1459 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1460 power-domains = <&rpmhpd SC7280_CX>; 1461 operating-points-v2 = <&qup_opp_table>; 1462 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1463 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1464 interconnect-names = "qup-core", "qup-config"; 1465 status = "disabled"; 1466 }; 1467 1468 i2c6: i2c@998000 { 1469 compatible = "qcom,geni-i2c"; 1470 reg = <0 0x00998000 0 0x4000>; 1471 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1472 clock-names = "se"; 1473 pinctrl-names = "default"; 1474 pinctrl-0 = <&qup_i2c6_data_clk>; 1475 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1476 #address-cells = <1>; 1477 #size-cells = <0>; 1478 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1479 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1480 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1481 interconnect-names = "qup-core", "qup-config", 1482 "qup-memory"; 1483 power-domains = <&rpmhpd SC7280_CX>; 1484 required-opps = <&rpmhpd_opp_low_svs>; 1485 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1486 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1487 dma-names = "tx", "rx"; 1488 status = "disabled"; 1489 }; 1490 1491 spi6: spi@998000 { 1492 compatible = "qcom,geni-spi"; 1493 reg = <0 0x00998000 0 0x4000>; 1494 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1495 clock-names = "se"; 1496 pinctrl-names = "default"; 1497 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1498 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1499 #address-cells = <1>; 1500 #size-cells = <0>; 1501 power-domains = <&rpmhpd SC7280_CX>; 1502 operating-points-v2 = <&qup_opp_table>; 1503 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1504 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1505 interconnect-names = "qup-core", "qup-config"; 1506 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1507 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1508 dma-names = "tx", "rx"; 1509 status = "disabled"; 1510 }; 1511 1512 uart6: serial@998000 { 1513 compatible = "qcom,geni-uart"; 1514 reg = <0 0x00998000 0 0x4000>; 1515 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1516 clock-names = "se"; 1517 pinctrl-names = "default"; 1518 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1519 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1520 power-domains = <&rpmhpd SC7280_CX>; 1521 operating-points-v2 = <&qup_opp_table>; 1522 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1523 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1524 interconnect-names = "qup-core", "qup-config"; 1525 status = "disabled"; 1526 }; 1527 1528 i2c7: i2c@99c000 { 1529 compatible = "qcom,geni-i2c"; 1530 reg = <0 0x0099c000 0 0x4000>; 1531 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1532 clock-names = "se"; 1533 pinctrl-names = "default"; 1534 pinctrl-0 = <&qup_i2c7_data_clk>; 1535 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1536 #address-cells = <1>; 1537 #size-cells = <0>; 1538 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1539 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1540 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1541 interconnect-names = "qup-core", "qup-config", 1542 "qup-memory"; 1543 power-domains = <&rpmhpd SC7280_CX>; 1544 required-opps = <&rpmhpd_opp_low_svs>; 1545 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1546 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1547 dma-names = "tx", "rx"; 1548 status = "disabled"; 1549 }; 1550 1551 spi7: spi@99c000 { 1552 compatible = "qcom,geni-spi"; 1553 reg = <0 0x0099c000 0 0x4000>; 1554 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1555 clock-names = "se"; 1556 pinctrl-names = "default"; 1557 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1558 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1559 #address-cells = <1>; 1560 #size-cells = <0>; 1561 power-domains = <&rpmhpd SC7280_CX>; 1562 operating-points-v2 = <&qup_opp_table>; 1563 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1564 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1565 interconnect-names = "qup-core", "qup-config"; 1566 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1567 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1568 dma-names = "tx", "rx"; 1569 status = "disabled"; 1570 }; 1571 1572 uart7: serial@99c000 { 1573 compatible = "qcom,geni-uart"; 1574 reg = <0 0x0099c000 0 0x4000>; 1575 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1576 clock-names = "se"; 1577 pinctrl-names = "default"; 1578 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1579 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1580 power-domains = <&rpmhpd SC7280_CX>; 1581 operating-points-v2 = <&qup_opp_table>; 1582 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1583 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1584 interconnect-names = "qup-core", "qup-config"; 1585 status = "disabled"; 1586 }; 1587 }; 1588 1589 gpi_dma1: dma-controller@a00000 { 1590 #dma-cells = <3>; 1591 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1592 reg = <0 0x00a00000 0 0x60000>; 1593 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1595 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1596 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1598 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1600 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1601 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1602 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1603 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1604 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1605 dma-channels = <12>; 1606 dma-channel-mask = <0x1e>; 1607 iommus = <&apps_smmu 0x56 0x0>; 1608 status = "disabled"; 1609 }; 1610 1611 qupv3_id_1: geniqup@ac0000 { 1612 compatible = "qcom,geni-se-qup"; 1613 reg = <0 0x00ac0000 0 0x2000>; 1614 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1615 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1616 clock-names = "m-ahb", "s-ahb"; 1617 #address-cells = <2>; 1618 #size-cells = <2>; 1619 ranges; 1620 iommus = <&apps_smmu 0x43 0x0>; 1621 status = "disabled"; 1622 1623 i2c8: i2c@a80000 { 1624 compatible = "qcom,geni-i2c"; 1625 reg = <0 0x00a80000 0 0x4000>; 1626 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1627 clock-names = "se"; 1628 pinctrl-names = "default"; 1629 pinctrl-0 = <&qup_i2c8_data_clk>; 1630 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1631 #address-cells = <1>; 1632 #size-cells = <0>; 1633 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1634 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1635 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1636 interconnect-names = "qup-core", "qup-config", 1637 "qup-memory"; 1638 power-domains = <&rpmhpd SC7280_CX>; 1639 required-opps = <&rpmhpd_opp_low_svs>; 1640 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1641 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1642 dma-names = "tx", "rx"; 1643 status = "disabled"; 1644 }; 1645 1646 spi8: spi@a80000 { 1647 compatible = "qcom,geni-spi"; 1648 reg = <0 0x00a80000 0 0x4000>; 1649 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1650 clock-names = "se"; 1651 pinctrl-names = "default"; 1652 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1653 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1654 #address-cells = <1>; 1655 #size-cells = <0>; 1656 power-domains = <&rpmhpd SC7280_CX>; 1657 operating-points-v2 = <&qup_opp_table>; 1658 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1659 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1660 interconnect-names = "qup-core", "qup-config"; 1661 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1662 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1663 dma-names = "tx", "rx"; 1664 status = "disabled"; 1665 }; 1666 1667 uart8: serial@a80000 { 1668 compatible = "qcom,geni-uart"; 1669 reg = <0 0x00a80000 0 0x4000>; 1670 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1671 clock-names = "se"; 1672 pinctrl-names = "default"; 1673 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1674 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1675 power-domains = <&rpmhpd SC7280_CX>; 1676 operating-points-v2 = <&qup_opp_table>; 1677 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1678 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1679 interconnect-names = "qup-core", "qup-config"; 1680 status = "disabled"; 1681 }; 1682 1683 i2c9: i2c@a84000 { 1684 compatible = "qcom,geni-i2c"; 1685 reg = <0 0x00a84000 0 0x4000>; 1686 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1687 clock-names = "se"; 1688 pinctrl-names = "default"; 1689 pinctrl-0 = <&qup_i2c9_data_clk>; 1690 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1691 #address-cells = <1>; 1692 #size-cells = <0>; 1693 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1694 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1695 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1696 interconnect-names = "qup-core", "qup-config", 1697 "qup-memory"; 1698 power-domains = <&rpmhpd SC7280_CX>; 1699 required-opps = <&rpmhpd_opp_low_svs>; 1700 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1701 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1702 dma-names = "tx", "rx"; 1703 status = "disabled"; 1704 }; 1705 1706 spi9: spi@a84000 { 1707 compatible = "qcom,geni-spi"; 1708 reg = <0 0x00a84000 0 0x4000>; 1709 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1710 clock-names = "se"; 1711 pinctrl-names = "default"; 1712 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1713 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1714 #address-cells = <1>; 1715 #size-cells = <0>; 1716 power-domains = <&rpmhpd SC7280_CX>; 1717 operating-points-v2 = <&qup_opp_table>; 1718 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1719 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1720 interconnect-names = "qup-core", "qup-config"; 1721 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1722 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1723 dma-names = "tx", "rx"; 1724 status = "disabled"; 1725 }; 1726 1727 uart9: serial@a84000 { 1728 compatible = "qcom,geni-uart"; 1729 reg = <0 0x00a84000 0 0x4000>; 1730 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1731 clock-names = "se"; 1732 pinctrl-names = "default"; 1733 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1734 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1735 power-domains = <&rpmhpd SC7280_CX>; 1736 operating-points-v2 = <&qup_opp_table>; 1737 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1738 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1739 interconnect-names = "qup-core", "qup-config"; 1740 status = "disabled"; 1741 }; 1742 1743 i2c10: i2c@a88000 { 1744 compatible = "qcom,geni-i2c"; 1745 reg = <0 0x00a88000 0 0x4000>; 1746 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1747 clock-names = "se"; 1748 pinctrl-names = "default"; 1749 pinctrl-0 = <&qup_i2c10_data_clk>; 1750 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1751 #address-cells = <1>; 1752 #size-cells = <0>; 1753 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1754 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1755 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1756 interconnect-names = "qup-core", "qup-config", 1757 "qup-memory"; 1758 power-domains = <&rpmhpd SC7280_CX>; 1759 required-opps = <&rpmhpd_opp_low_svs>; 1760 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1761 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1762 dma-names = "tx", "rx"; 1763 status = "disabled"; 1764 }; 1765 1766 spi10: spi@a88000 { 1767 compatible = "qcom,geni-spi"; 1768 reg = <0 0x00a88000 0 0x4000>; 1769 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1770 clock-names = "se"; 1771 pinctrl-names = "default"; 1772 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1773 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1774 #address-cells = <1>; 1775 #size-cells = <0>; 1776 power-domains = <&rpmhpd SC7280_CX>; 1777 operating-points-v2 = <&qup_opp_table>; 1778 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1779 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1780 interconnect-names = "qup-core", "qup-config"; 1781 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1782 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1783 dma-names = "tx", "rx"; 1784 status = "disabled"; 1785 }; 1786 1787 uart10: serial@a88000 { 1788 compatible = "qcom,geni-uart"; 1789 reg = <0 0x00a88000 0 0x4000>; 1790 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1791 clock-names = "se"; 1792 pinctrl-names = "default"; 1793 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1794 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1795 power-domains = <&rpmhpd SC7280_CX>; 1796 operating-points-v2 = <&qup_opp_table>; 1797 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1798 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1799 interconnect-names = "qup-core", "qup-config"; 1800 status = "disabled"; 1801 }; 1802 1803 i2c11: i2c@a8c000 { 1804 compatible = "qcom,geni-i2c"; 1805 reg = <0 0x00a8c000 0 0x4000>; 1806 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1807 clock-names = "se"; 1808 pinctrl-names = "default"; 1809 pinctrl-0 = <&qup_i2c11_data_clk>; 1810 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1811 #address-cells = <1>; 1812 #size-cells = <0>; 1813 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1814 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1815 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1816 interconnect-names = "qup-core", "qup-config", 1817 "qup-memory"; 1818 power-domains = <&rpmhpd SC7280_CX>; 1819 required-opps = <&rpmhpd_opp_low_svs>; 1820 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1821 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1822 dma-names = "tx", "rx"; 1823 status = "disabled"; 1824 }; 1825 1826 spi11: spi@a8c000 { 1827 compatible = "qcom,geni-spi"; 1828 reg = <0 0x00a8c000 0 0x4000>; 1829 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1830 clock-names = "se"; 1831 pinctrl-names = "default"; 1832 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1833 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1834 #address-cells = <1>; 1835 #size-cells = <0>; 1836 power-domains = <&rpmhpd SC7280_CX>; 1837 operating-points-v2 = <&qup_opp_table>; 1838 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1839 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1840 interconnect-names = "qup-core", "qup-config"; 1841 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1842 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1843 dma-names = "tx", "rx"; 1844 status = "disabled"; 1845 }; 1846 1847 uart11: serial@a8c000 { 1848 compatible = "qcom,geni-uart"; 1849 reg = <0 0x00a8c000 0 0x4000>; 1850 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1851 clock-names = "se"; 1852 pinctrl-names = "default"; 1853 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1854 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1855 power-domains = <&rpmhpd SC7280_CX>; 1856 operating-points-v2 = <&qup_opp_table>; 1857 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1858 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1859 interconnect-names = "qup-core", "qup-config"; 1860 status = "disabled"; 1861 }; 1862 1863 i2c12: i2c@a90000 { 1864 compatible = "qcom,geni-i2c"; 1865 reg = <0 0x00a90000 0 0x4000>; 1866 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1867 clock-names = "se"; 1868 pinctrl-names = "default"; 1869 pinctrl-0 = <&qup_i2c12_data_clk>; 1870 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1871 #address-cells = <1>; 1872 #size-cells = <0>; 1873 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1874 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1875 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1876 interconnect-names = "qup-core", "qup-config", 1877 "qup-memory"; 1878 power-domains = <&rpmhpd SC7280_CX>; 1879 required-opps = <&rpmhpd_opp_low_svs>; 1880 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1881 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1882 dma-names = "tx", "rx"; 1883 status = "disabled"; 1884 }; 1885 1886 spi12: spi@a90000 { 1887 compatible = "qcom,geni-spi"; 1888 reg = <0 0x00a90000 0 0x4000>; 1889 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1890 clock-names = "se"; 1891 pinctrl-names = "default"; 1892 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1893 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1894 #address-cells = <1>; 1895 #size-cells = <0>; 1896 power-domains = <&rpmhpd SC7280_CX>; 1897 operating-points-v2 = <&qup_opp_table>; 1898 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1899 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1900 interconnect-names = "qup-core", "qup-config"; 1901 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1902 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1903 dma-names = "tx", "rx"; 1904 status = "disabled"; 1905 }; 1906 1907 uart12: serial@a90000 { 1908 compatible = "qcom,geni-uart"; 1909 reg = <0 0x00a90000 0 0x4000>; 1910 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1911 clock-names = "se"; 1912 pinctrl-names = "default"; 1913 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1914 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1915 power-domains = <&rpmhpd SC7280_CX>; 1916 operating-points-v2 = <&qup_opp_table>; 1917 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1918 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1919 interconnect-names = "qup-core", "qup-config"; 1920 status = "disabled"; 1921 }; 1922 1923 i2c13: i2c@a94000 { 1924 compatible = "qcom,geni-i2c"; 1925 reg = <0 0x00a94000 0 0x4000>; 1926 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1927 clock-names = "se"; 1928 pinctrl-names = "default"; 1929 pinctrl-0 = <&qup_i2c13_data_clk>; 1930 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1931 #address-cells = <1>; 1932 #size-cells = <0>; 1933 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1934 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1935 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1936 interconnect-names = "qup-core", "qup-config", 1937 "qup-memory"; 1938 power-domains = <&rpmhpd SC7280_CX>; 1939 required-opps = <&rpmhpd_opp_low_svs>; 1940 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1941 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1942 dma-names = "tx", "rx"; 1943 status = "disabled"; 1944 }; 1945 1946 spi13: spi@a94000 { 1947 compatible = "qcom,geni-spi"; 1948 reg = <0 0x00a94000 0 0x4000>; 1949 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1950 clock-names = "se"; 1951 pinctrl-names = "default"; 1952 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1953 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1954 #address-cells = <1>; 1955 #size-cells = <0>; 1956 power-domains = <&rpmhpd SC7280_CX>; 1957 operating-points-v2 = <&qup_opp_table>; 1958 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1959 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1960 interconnect-names = "qup-core", "qup-config"; 1961 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1962 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1963 dma-names = "tx", "rx"; 1964 status = "disabled"; 1965 }; 1966 1967 uart13: serial@a94000 { 1968 compatible = "qcom,geni-uart"; 1969 reg = <0 0x00a94000 0 0x4000>; 1970 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1971 clock-names = "se"; 1972 pinctrl-names = "default"; 1973 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1974 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1975 power-domains = <&rpmhpd SC7280_CX>; 1976 operating-points-v2 = <&qup_opp_table>; 1977 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1978 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1979 interconnect-names = "qup-core", "qup-config"; 1980 status = "disabled"; 1981 }; 1982 1983 i2c14: i2c@a98000 { 1984 compatible = "qcom,geni-i2c"; 1985 reg = <0 0x00a98000 0 0x4000>; 1986 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1987 clock-names = "se"; 1988 pinctrl-names = "default"; 1989 pinctrl-0 = <&qup_i2c14_data_clk>; 1990 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1991 #address-cells = <1>; 1992 #size-cells = <0>; 1993 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1994 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1995 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1996 interconnect-names = "qup-core", "qup-config", 1997 "qup-memory"; 1998 power-domains = <&rpmhpd SC7280_CX>; 1999 required-opps = <&rpmhpd_opp_low_svs>; 2000 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2001 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2002 dma-names = "tx", "rx"; 2003 status = "disabled"; 2004 }; 2005 2006 spi14: spi@a98000 { 2007 compatible = "qcom,geni-spi"; 2008 reg = <0 0x00a98000 0 0x4000>; 2009 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2010 clock-names = "se"; 2011 pinctrl-names = "default"; 2012 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 2013 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 2014 #address-cells = <1>; 2015 #size-cells = <0>; 2016 power-domains = <&rpmhpd SC7280_CX>; 2017 operating-points-v2 = <&qup_opp_table>; 2018 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2019 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2020 interconnect-names = "qup-core", "qup-config"; 2021 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2022 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2023 dma-names = "tx", "rx"; 2024 status = "disabled"; 2025 }; 2026 2027 uart14: serial@a98000 { 2028 compatible = "qcom,geni-uart"; 2029 reg = <0 0x00a98000 0 0x4000>; 2030 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2031 clock-names = "se"; 2032 pinctrl-names = "default"; 2033 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 2034 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 2035 power-domains = <&rpmhpd SC7280_CX>; 2036 operating-points-v2 = <&qup_opp_table>; 2037 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2038 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2039 interconnect-names = "qup-core", "qup-config"; 2040 status = "disabled"; 2041 }; 2042 2043 i2c15: i2c@a9c000 { 2044 compatible = "qcom,geni-i2c"; 2045 reg = <0 0x00a9c000 0 0x4000>; 2046 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2047 clock-names = "se"; 2048 pinctrl-names = "default"; 2049 pinctrl-0 = <&qup_i2c15_data_clk>; 2050 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2051 #address-cells = <1>; 2052 #size-cells = <0>; 2053 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2054 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 2055 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2056 interconnect-names = "qup-core", "qup-config", 2057 "qup-memory"; 2058 power-domains = <&rpmhpd SC7280_CX>; 2059 required-opps = <&rpmhpd_opp_low_svs>; 2060 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2061 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2062 dma-names = "tx", "rx"; 2063 status = "disabled"; 2064 }; 2065 2066 spi15: spi@a9c000 { 2067 compatible = "qcom,geni-spi"; 2068 reg = <0 0x00a9c000 0 0x4000>; 2069 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2070 clock-names = "se"; 2071 pinctrl-names = "default"; 2072 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 2073 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2074 #address-cells = <1>; 2075 #size-cells = <0>; 2076 power-domains = <&rpmhpd SC7280_CX>; 2077 operating-points-v2 = <&qup_opp_table>; 2078 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2079 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2080 interconnect-names = "qup-core", "qup-config"; 2081 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2082 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2083 dma-names = "tx", "rx"; 2084 status = "disabled"; 2085 }; 2086 2087 uart15: serial@a9c000 { 2088 compatible = "qcom,geni-uart"; 2089 reg = <0 0x00a9c000 0 0x4000>; 2090 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2091 clock-names = "se"; 2092 pinctrl-names = "default"; 2093 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 2094 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2095 power-domains = <&rpmhpd SC7280_CX>; 2096 operating-points-v2 = <&qup_opp_table>; 2097 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2098 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2099 interconnect-names = "qup-core", "qup-config"; 2100 status = "disabled"; 2101 }; 2102 }; 2103 2104 rng: rng@10d3000 { 2105 compatible = "qcom,sc7280-trng", "qcom,trng"; 2106 reg = <0 0x010d3000 0 0x1000>; 2107 }; 2108 2109 cnoc2: interconnect@1500000 { 2110 reg = <0 0x01500000 0 0x1000>; 2111 compatible = "qcom,sc7280-cnoc2"; 2112 #interconnect-cells = <2>; 2113 qcom,bcm-voters = <&apps_bcm_voter>; 2114 }; 2115 2116 cnoc3: interconnect@1502000 { 2117 reg = <0 0x01502000 0 0x1000>; 2118 compatible = "qcom,sc7280-cnoc3"; 2119 #interconnect-cells = <2>; 2120 qcom,bcm-voters = <&apps_bcm_voter>; 2121 }; 2122 2123 mc_virt: interconnect@1580000 { 2124 reg = <0 0x01580000 0 0x4>; 2125 compatible = "qcom,sc7280-mc-virt"; 2126 #interconnect-cells = <2>; 2127 qcom,bcm-voters = <&apps_bcm_voter>; 2128 }; 2129 2130 system_noc: interconnect@1680000 { 2131 reg = <0 0x01680000 0 0x15480>; 2132 compatible = "qcom,sc7280-system-noc"; 2133 #interconnect-cells = <2>; 2134 qcom,bcm-voters = <&apps_bcm_voter>; 2135 }; 2136 2137 aggre1_noc: interconnect@16e0000 { 2138 compatible = "qcom,sc7280-aggre1-noc"; 2139 reg = <0 0x016e0000 0 0x1c080>; 2140 #interconnect-cells = <2>; 2141 qcom,bcm-voters = <&apps_bcm_voter>; 2142 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2143 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 2144 }; 2145 2146 aggre2_noc: interconnect@1700000 { 2147 reg = <0 0x01700000 0 0x2b080>; 2148 compatible = "qcom,sc7280-aggre2-noc"; 2149 #interconnect-cells = <2>; 2150 qcom,bcm-voters = <&apps_bcm_voter>; 2151 clocks = <&rpmhcc RPMH_IPA_CLK>; 2152 }; 2153 2154 mmss_noc: interconnect@1740000 { 2155 reg = <0 0x01740000 0 0x1e080>; 2156 compatible = "qcom,sc7280-mmss-noc"; 2157 #interconnect-cells = <2>; 2158 qcom,bcm-voters = <&apps_bcm_voter>; 2159 }; 2160 2161 wifi: wifi@17a10040 { 2162 compatible = "qcom,wcn6750-wifi"; 2163 reg = <0 0x17a10040 0 0x0>; 2164 iommus = <&apps_smmu 0x1c00 0x1>; 2165 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 2166 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 2167 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 2168 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 2169 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 2170 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 2171 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 2172 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 2173 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 2174 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 2175 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 2176 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 2177 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 2178 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 2179 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 2180 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 2181 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 2182 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 2183 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 2184 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 2185 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 2186 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 2187 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 2188 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 2189 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 2190 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 2191 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 2192 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 2193 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2194 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2195 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2196 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2197 qcom,rproc = <&remoteproc_wpss>; 2198 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2199 status = "disabled"; 2200 qcom,smem-states = <&wlan_smp2p_out 0>; 2201 qcom,smem-state-names = "wlan-smp2p-out"; 2202 }; 2203 2204 pcie0: pcie@1c00000 { 2205 compatible = "qcom,pcie-sc7280"; 2206 reg = <0 0x01c00000 0 0x3000>, 2207 <0 0x60000000 0 0xf1d>, 2208 <0 0x60000f20 0 0xa8>, 2209 <0 0x60001000 0 0x1000>, 2210 <0 0x60100000 0 0x100000>, 2211 <0 0x01c03000 0 0x1000>; 2212 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2213 device_type = "pci"; 2214 linux,pci-domain = <0>; 2215 bus-range = <0x00 0xff>; 2216 num-lanes = <1>; 2217 2218 #address-cells = <3>; 2219 #size-cells = <2>; 2220 2221 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 2222 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 2223 2224 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2225 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2226 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2227 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2228 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2229 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2230 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2231 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2232 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2233 interrupt-names = "msi0", 2234 "msi1", 2235 "msi2", 2236 "msi3", 2237 "msi4", 2238 "msi5", 2239 "msi6", 2240 "msi7", 2241 "global"; 2242 #interrupt-cells = <1>; 2243 interrupt-map-mask = <0 0 0 0x7>; 2244 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2245 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 2246 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 2247 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 2248 2249 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 2250 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, 2251 <&pcie0_phy>, 2252 <&rpmhcc RPMH_CXO_CLK>, 2253 <&gcc GCC_PCIE_0_AUX_CLK>, 2254 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2255 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2256 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2257 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2258 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2259 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2260 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2261 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; 2262 clock-names = "pipe", 2263 "pipe_mux", 2264 "phy_pipe", 2265 "ref", 2266 "aux", 2267 "cfg", 2268 "bus_master", 2269 "bus_slave", 2270 "slave_q2a", 2271 "tbu", 2272 "ddrss_sf_tbu", 2273 "aggre0", 2274 "aggre1"; 2275 2276 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 2277 <0x100 &apps_smmu 0x1c01 0x1>; 2278 2279 resets = <&gcc GCC_PCIE_0_BCR>; 2280 reset-names = "pci"; 2281 2282 power-domains = <&gcc GCC_PCIE_0_GDSC>; 2283 2284 phys = <&pcie0_phy>; 2285 phy-names = "pciephy"; 2286 2287 pinctrl-names = "default"; 2288 pinctrl-0 = <&pcie0_clkreq_n>; 2289 dma-coherent; 2290 2291 status = "disabled"; 2292 2293 pcie0_port: pcie@0 { 2294 device_type = "pci"; 2295 reg = <0x0 0x0 0x0 0x0 0x0>; 2296 bus-range = <0x01 0xff>; 2297 2298 #address-cells = <3>; 2299 #size-cells = <2>; 2300 ranges; 2301 }; 2302 }; 2303 2304 pcie0_phy: phy@1c06000 { 2305 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; 2306 reg = <0 0x01c06000 0 0x1000>; 2307 2308 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2309 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2310 <&gcc GCC_PCIE_CLKREF_EN>, 2311 <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, 2312 <&gcc GCC_PCIE_0_PIPE_CLK>; 2313 clock-names = "aux", 2314 "cfg_ahb", 2315 "ref", 2316 "refgen", 2317 "pipe"; 2318 2319 clock-output-names = "pcie_0_pipe_clk"; 2320 #clock-cells = <0>; 2321 2322 #phy-cells = <0>; 2323 2324 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2325 reset-names = "phy"; 2326 2327 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>; 2328 assigned-clock-rates = <100000000>; 2329 2330 status = "disabled"; 2331 }; 2332 2333 pcie1: pcie@1c08000 { 2334 compatible = "qcom,pcie-sc7280"; 2335 reg = <0 0x01c08000 0 0x3000>, 2336 <0 0x40000000 0 0xf1d>, 2337 <0 0x40000f20 0 0xa8>, 2338 <0 0x40001000 0 0x1000>, 2339 <0 0x40100000 0 0x100000>; 2340 2341 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2342 device_type = "pci"; 2343 linux,pci-domain = <1>; 2344 bus-range = <0x00 0xff>; 2345 num-lanes = <2>; 2346 2347 #address-cells = <3>; 2348 #size-cells = <2>; 2349 2350 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2351 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2352 2353 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2354 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2355 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2356 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2357 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2358 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2359 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2360 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2361 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 2362 interrupt-names = "msi0", 2363 "msi1", 2364 "msi2", 2365 "msi3", 2366 "msi4", 2367 "msi5", 2368 "msi6", 2369 "msi7", 2370 "global"; 2371 #interrupt-cells = <1>; 2372 interrupt-map-mask = <0 0 0 0x7>; 2373 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 2374 <0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 2375 <0 0 0 3 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 2376 <0 0 0 4 &intc 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; 2377 2378 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2379 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2380 <&pcie1_phy>, 2381 <&rpmhcc RPMH_CXO_CLK>, 2382 <&gcc GCC_PCIE_1_AUX_CLK>, 2383 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2384 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2385 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2386 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2387 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2388 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2389 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2390 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2391 2392 clock-names = "pipe", 2393 "pipe_mux", 2394 "phy_pipe", 2395 "ref", 2396 "aux", 2397 "cfg", 2398 "bus_master", 2399 "bus_slave", 2400 "slave_q2a", 2401 "tbu", 2402 "ddrss_sf_tbu", 2403 "aggre0", 2404 "aggre1"; 2405 2406 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2407 assigned-clock-rates = <19200000>; 2408 2409 resets = <&gcc GCC_PCIE_1_BCR>; 2410 reset-names = "pci"; 2411 2412 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2413 2414 phys = <&pcie1_phy>; 2415 phy-names = "pciephy"; 2416 2417 pinctrl-names = "default"; 2418 pinctrl-0 = <&pcie1_clkreq_n>; 2419 2420 dma-coherent; 2421 2422 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2423 <0x100 &apps_smmu 0x1c81 0x1>; 2424 2425 status = "disabled"; 2426 2427 pcie@0 { 2428 device_type = "pci"; 2429 reg = <0x0 0x0 0x0 0x0 0x0>; 2430 bus-range = <0x01 0xff>; 2431 2432 #address-cells = <3>; 2433 #size-cells = <2>; 2434 ranges; 2435 }; 2436 }; 2437 2438 pcie1_phy: phy@1c0e000 { 2439 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2440 reg = <0 0x01c0e000 0 0x1000>; 2441 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2442 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2443 <&gcc GCC_PCIE_CLKREF_EN>, 2444 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, 2445 <&gcc GCC_PCIE_1_PIPE_CLK>; 2446 clock-names = "aux", 2447 "cfg_ahb", 2448 "ref", 2449 "refgen", 2450 "pipe"; 2451 2452 clock-output-names = "pcie_1_pipe_clk"; 2453 #clock-cells = <0>; 2454 2455 #phy-cells = <0>; 2456 2457 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2458 reset-names = "phy"; 2459 2460 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2461 assigned-clock-rates = <100000000>; 2462 2463 status = "disabled"; 2464 }; 2465 2466 ufs_mem_hc: ufshc@1d84000 { 2467 compatible = "qcom,sc7280-ufshc", "qcom,ufshc", 2468 "jedec,ufs-2.0"; 2469 reg = <0x0 0x01d84000 0x0 0x3000>; 2470 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2471 phys = <&ufs_mem_phy>; 2472 phy-names = "ufsphy"; 2473 lanes-per-direction = <2>; 2474 #reset-cells = <1>; 2475 resets = <&gcc GCC_UFS_PHY_BCR>; 2476 reset-names = "rst"; 2477 2478 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 2479 required-opps = <&rpmhpd_opp_nom>; 2480 2481 iommus = <&apps_smmu 0x80 0x0>; 2482 dma-coherent; 2483 2484 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2485 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2486 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2487 &cnoc2 SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 2488 interconnect-names = "ufs-ddr", "cpu-ufs"; 2489 2490 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2491 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2492 <&gcc GCC_UFS_PHY_AHB_CLK>, 2493 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2494 <&rpmhcc RPMH_CXO_CLK>, 2495 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2496 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2497 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2498 clock-names = "core_clk", 2499 "bus_aggr_clk", 2500 "iface_clk", 2501 "core_clk_unipro", 2502 "ref_clk", 2503 "tx_lane0_sync_clk", 2504 "rx_lane0_sync_clk", 2505 "rx_lane1_sync_clk"; 2506 2507 operating-points-v2 = <&ufs_opp_table>; 2508 2509 qcom,ice = <&ice>; 2510 2511 status = "disabled"; 2512 2513 ufs_opp_table: opp-table { 2514 compatible = "operating-points-v2"; 2515 2516 opp-75000000 { 2517 opp-hz = /bits/ 64 <75000000>, 2518 /bits/ 64 <0>, 2519 /bits/ 64 <0>, 2520 /bits/ 64 <75000000>, 2521 /bits/ 64 <0>, 2522 /bits/ 64 <0>, 2523 /bits/ 64 <0>, 2524 /bits/ 64 <0>; 2525 required-opps = <&rpmhpd_opp_low_svs>; 2526 }; 2527 2528 opp-150000000 { 2529 opp-hz = /bits/ 64 <150000000>, 2530 /bits/ 64 <0>, 2531 /bits/ 64 <0>, 2532 /bits/ 64 <150000000>, 2533 /bits/ 64 <0>, 2534 /bits/ 64 <0>, 2535 /bits/ 64 <0>, 2536 /bits/ 64 <0>; 2537 required-opps = <&rpmhpd_opp_svs>; 2538 }; 2539 2540 opp-300000000 { 2541 opp-hz = /bits/ 64 <300000000>, 2542 /bits/ 64 <0>, 2543 /bits/ 64 <0>, 2544 /bits/ 64 <300000000>, 2545 /bits/ 64 <0>, 2546 /bits/ 64 <0>, 2547 /bits/ 64 <0>, 2548 /bits/ 64 <0>; 2549 required-opps = <&rpmhpd_opp_nom>; 2550 }; 2551 }; 2552 }; 2553 2554 ufs_mem_phy: phy@1d87000 { 2555 compatible = "qcom,sc7280-qmp-ufs-phy"; 2556 reg = <0x0 0x01d87000 0x0 0xe00>; 2557 clocks = <&rpmhcc RPMH_CXO_CLK>, 2558 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2559 <&gcc GCC_UFS_1_CLKREF_EN>; 2560 clock-names = "ref", "ref_aux", "qref"; 2561 2562 power-domains = <&rpmhpd SC7280_MX>; 2563 2564 resets = <&ufs_mem_hc 0>; 2565 reset-names = "ufsphy"; 2566 2567 #clock-cells = <1>; 2568 #phy-cells = <0>; 2569 2570 status = "disabled"; 2571 }; 2572 2573 ice: crypto@1d88000 { 2574 compatible = "qcom,sc7280-inline-crypto-engine", 2575 "qcom,inline-crypto-engine"; 2576 reg = <0 0x01d88000 0 0x8000>; 2577 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2578 }; 2579 2580 cryptobam: dma-controller@1dc4000 { 2581 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2582 reg = <0x0 0x01dc4000 0x0 0x28000>; 2583 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2584 #dma-cells = <1>; 2585 iommus = <&apps_smmu 0x4e4 0x0011>, 2586 <&apps_smmu 0x4e6 0x0011>; 2587 qcom,ee = <0>; 2588 qcom,controlled-remotely; 2589 num-channels = <16>; 2590 qcom,num-ees = <4>; 2591 }; 2592 2593 crypto: crypto@1dfa000 { 2594 compatible = "qcom,sc7280-qce", "qcom,sm8150-qce", "qcom,qce"; 2595 reg = <0x0 0x01dfa000 0x0 0x6000>; 2596 dmas = <&cryptobam 4>, <&cryptobam 5>; 2597 dma-names = "rx", "tx"; 2598 iommus = <&apps_smmu 0x4e4 0x0011>, 2599 <&apps_smmu 0x4e4 0x0011>; 2600 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 2601 interconnect-names = "memory"; 2602 }; 2603 2604 ipa: ipa@1e40000 { 2605 compatible = "qcom,sc7280-ipa"; 2606 2607 iommus = <&apps_smmu 0x480 0x0>, 2608 <&apps_smmu 0x482 0x0>; 2609 reg = <0 0x01e40000 0 0x8000>, 2610 <0 0x01e50000 0 0x4ad0>, 2611 <0 0x01e04000 0 0x23000>; 2612 reg-names = "ipa-reg", 2613 "ipa-shared", 2614 "gsi"; 2615 2616 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2617 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2618 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2619 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2620 interrupt-names = "ipa", 2621 "gsi", 2622 "ipa-clock-query", 2623 "ipa-setup-ready"; 2624 2625 clocks = <&rpmhcc RPMH_IPA_CLK>; 2626 clock-names = "core"; 2627 2628 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2629 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2630 interconnect-names = "memory", 2631 "config"; 2632 2633 qcom,qmp = <&aoss_qmp>; 2634 2635 qcom,smem-states = <&ipa_smp2p_out 0>, 2636 <&ipa_smp2p_out 1>; 2637 qcom,smem-state-names = "ipa-clock-enabled-valid", 2638 "ipa-clock-enabled"; 2639 2640 status = "disabled"; 2641 }; 2642 2643 tcsr_mutex: hwlock@1f40000 { 2644 compatible = "qcom,tcsr-mutex"; 2645 reg = <0 0x01f40000 0 0x20000>; 2646 #hwlock-cells = <1>; 2647 }; 2648 2649 tcsr_1: syscon@1f60000 { 2650 compatible = "qcom,sc7280-tcsr", "syscon"; 2651 reg = <0 0x01f60000 0 0x20000>; 2652 }; 2653 2654 tcsr_2: syscon@1fc0000 { 2655 compatible = "qcom,sc7280-tcsr", "syscon"; 2656 reg = <0 0x01fc0000 0 0x30000>; 2657 }; 2658 2659 lpasscc: lpasscc@3000000 { 2660 compatible = "qcom,sc7280-lpasscc"; 2661 reg = <0 0x03000000 0 0x40>, 2662 <0 0x03c04000 0 0x4>; 2663 reg-names = "qdsp6ss", "top_cc"; 2664 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2665 clock-names = "iface"; 2666 #clock-cells = <1>; 2667 status = "reserved"; /* Owned by ADSP firmware */ 2668 }; 2669 2670 lpass_rx_macro: codec@3200000 { 2671 compatible = "qcom,sc7280-lpass-rx-macro"; 2672 reg = <0 0x03200000 0 0x1000>; 2673 2674 pinctrl-names = "default"; 2675 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2676 2677 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2678 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2679 <&lpass_va_macro>; 2680 clock-names = "mclk", "npl", "fsgen"; 2681 2682 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2683 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2684 power-domain-names = "macro", "dcodec"; 2685 2686 #clock-cells = <0>; 2687 #sound-dai-cells = <1>; 2688 2689 status = "disabled"; 2690 }; 2691 2692 swr0: soundwire@3210000 { 2693 compatible = "qcom,soundwire-v1.6.0"; 2694 reg = <0 0x03210000 0 0x2000>; 2695 2696 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2697 clocks = <&lpass_rx_macro>; 2698 clock-names = "iface"; 2699 2700 qcom,din-ports = <0>; 2701 qcom,dout-ports = <5>; 2702 2703 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2704 reset-names = "swr_audio_cgcr"; 2705 2706 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2707 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2708 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2709 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2710 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2711 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2712 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2713 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2714 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2715 2716 #sound-dai-cells = <1>; 2717 #address-cells = <2>; 2718 #size-cells = <0>; 2719 2720 status = "disabled"; 2721 }; 2722 2723 lpass_tx_macro: codec@3220000 { 2724 compatible = "qcom,sc7280-lpass-tx-macro"; 2725 reg = <0 0x03220000 0 0x1000>; 2726 2727 pinctrl-names = "default"; 2728 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2729 2730 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2731 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2732 <&lpass_va_macro>; 2733 clock-names = "mclk", "npl", "fsgen"; 2734 2735 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2736 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2737 power-domain-names = "macro", "dcodec"; 2738 2739 #clock-cells = <0>; 2740 #sound-dai-cells = <1>; 2741 2742 status = "disabled"; 2743 }; 2744 2745 swr1: soundwire@3230000 { 2746 compatible = "qcom,soundwire-v1.6.0"; 2747 reg = <0 0x03230000 0 0x2000>; 2748 2749 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2750 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2751 clocks = <&lpass_tx_macro>; 2752 clock-names = "iface"; 2753 2754 qcom,din-ports = <3>; 2755 qcom,dout-ports = <0>; 2756 2757 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2758 reset-names = "swr_audio_cgcr"; 2759 2760 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2761 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2762 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2763 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2764 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2765 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2766 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2767 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2768 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2769 2770 #sound-dai-cells = <1>; 2771 #address-cells = <2>; 2772 #size-cells = <0>; 2773 2774 status = "disabled"; 2775 }; 2776 2777 lpass_wsa_macro: codec@3240000 { 2778 compatible = "qcom,sc7280-lpass-wsa-macro"; 2779 reg = <0x0 0x03240000 0x0 0x1000>; 2780 2781 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2782 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2783 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2784 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2785 <&lpass_va_macro>; 2786 clock-names = "mclk", 2787 "npl", 2788 "macro", 2789 "dcodec", 2790 "fsgen"; 2791 2792 pinctrl-0 = <&lpass_wsa_swr_clk>, <&lpass_wsa_swr_data>; 2793 pinctrl-names = "default"; 2794 2795 #clock-cells = <0>; 2796 clock-output-names = "mclk"; 2797 #sound-dai-cells = <1>; 2798 2799 status = "disabled"; 2800 }; 2801 2802 swr2: soundwire@3250000 { 2803 compatible = "qcom,soundwire-v1.6.0"; 2804 reg = <0x0 0x03250000 0x0 0x2000>; 2805 2806 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2807 clocks = <&lpass_wsa_macro>; 2808 clock-names = "iface"; 2809 2810 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; 2811 reset-names = "swr_audio_cgcr"; 2812 2813 qcom,din-ports = <2>; 2814 qcom,dout-ports = <6>; 2815 2816 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 2817 0x1f 0x3f 0x0f 0x0f>; 2818 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2819 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2820 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2821 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2822 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2823 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 2824 0xff 0xff>; 2825 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 2826 0xff 0xff>; 2827 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 2828 0xff 0xff>; 2829 2830 #address-cells = <2>; 2831 #size-cells = <0>; 2832 #sound-dai-cells = <1>; 2833 2834 status = "disabled"; 2835 }; 2836 2837 lpass_audiocc: clock-controller@3300000 { 2838 compatible = "qcom,sc7280-lpassaudiocc"; 2839 reg = <0 0x03300000 0 0x30000>, 2840 <0 0x032a9000 0 0x1000>; 2841 clocks = <&rpmhcc RPMH_CXO_CLK>, 2842 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2843 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2844 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2845 #clock-cells = <1>; 2846 #power-domain-cells = <1>; 2847 #reset-cells = <1>; 2848 }; 2849 2850 lpass_va_macro: codec@3370000 { 2851 compatible = "qcom,sc7280-lpass-va-macro"; 2852 reg = <0 0x03370000 0 0x1000>; 2853 2854 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2855 clock-names = "mclk"; 2856 2857 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2858 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2859 power-domain-names = "macro", "dcodec"; 2860 2861 #clock-cells = <0>; 2862 #sound-dai-cells = <1>; 2863 2864 status = "disabled"; 2865 }; 2866 2867 lpass_aon: clock-controller@3380000 { 2868 compatible = "qcom,sc7280-lpassaoncc"; 2869 reg = <0 0x03380000 0 0x30000>; 2870 clocks = <&rpmhcc RPMH_CXO_CLK>, 2871 <&rpmhcc RPMH_CXO_CLK_A>, 2872 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2873 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2874 #clock-cells = <1>; 2875 #power-domain-cells = <1>; 2876 status = "reserved"; /* Owned by ADSP firmware */ 2877 }; 2878 2879 lpass_core: clock-controller@3900000 { 2880 compatible = "qcom,sc7280-lpasscorecc"; 2881 reg = <0 0x03900000 0 0x50000>; 2882 clocks = <&rpmhcc RPMH_CXO_CLK>; 2883 clock-names = "bi_tcxo"; 2884 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2885 #clock-cells = <1>; 2886 #power-domain-cells = <1>; 2887 status = "reserved"; /* Owned by ADSP firmware */ 2888 }; 2889 2890 lpass_cpu: audio@3987000 { 2891 compatible = "qcom,sc7280-lpass-cpu"; 2892 2893 reg = <0 0x03987000 0 0x68000>, 2894 <0 0x03b00000 0 0x29000>, 2895 <0 0x03260000 0 0xc000>, 2896 <0 0x03280000 0 0x29000>, 2897 <0 0x03340000 0 0x29000>, 2898 <0 0x0336c000 0 0x3000>; 2899 reg-names = "lpass-hdmiif", 2900 "lpass-lpaif", 2901 "lpass-rxtx-cdc-dma-lpm", 2902 "lpass-rxtx-lpaif", 2903 "lpass-va-lpaif", 2904 "lpass-va-cdc-dma-lpm"; 2905 2906 iommus = <&apps_smmu 0x1820 0>, 2907 <&apps_smmu 0x1821 0>, 2908 <&apps_smmu 0x1832 0>; 2909 2910 power-domains = <&rpmhpd SC7280_LCX>; 2911 power-domain-names = "lcx"; 2912 required-opps = <&rpmhpd_opp_nom>; 2913 2914 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2915 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2916 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2917 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2918 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2919 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2920 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2921 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2922 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2923 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2924 clock-names = "aon_cc_audio_hm_h", 2925 "audio_cc_ext_mclk0", 2926 "core_cc_sysnoc_mport_core", 2927 "core_cc_ext_if0_ibit", 2928 "core_cc_ext_if1_ibit", 2929 "audio_cc_codec_mem", 2930 "audio_cc_codec_mem0", 2931 "audio_cc_codec_mem1", 2932 "audio_cc_codec_mem2", 2933 "aon_cc_va_mem0"; 2934 2935 #sound-dai-cells = <1>; 2936 #address-cells = <1>; 2937 #size-cells = <0>; 2938 2939 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2940 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2941 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2942 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2943 interrupt-names = "lpass-irq-lpaif", 2944 "lpass-irq-hdmi", 2945 "lpass-irq-vaif", 2946 "lpass-irq-rxtxif"; 2947 2948 status = "disabled"; 2949 }; 2950 2951 slimbam: dma-controller@3a84000 { 2952 compatible = "qcom,bam-v1.7.0"; 2953 reg = <0 0x03a84000 0 0x20000>; 2954 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 2955 #dma-cells = <1>; 2956 qcom,controlled-remotely; 2957 num-channels = <31>; 2958 qcom,ee = <1>; 2959 qcom,num-ees = <2>; 2960 iommus = <&apps_smmu 0x1826 0x0>; 2961 status = "disabled"; 2962 }; 2963 2964 slim: slim-ngd@3ac0000 { 2965 compatible = "qcom,slim-ngd-v1.5.0"; 2966 reg = <0 0x03ac0000 0 0x2c000>; 2967 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 2968 dmas = <&slimbam 3>, <&slimbam 4>; 2969 dma-names = "rx", "tx"; 2970 iommus = <&apps_smmu 0x1826 0x0>; 2971 #address-cells = <1>; 2972 #size-cells = <0>; 2973 status = "disabled"; 2974 }; 2975 2976 lpass_hm: clock-controller@3c00000 { 2977 compatible = "qcom,sc7280-lpasshm"; 2978 reg = <0 0x03c00000 0 0x28>; 2979 clocks = <&rpmhcc RPMH_CXO_CLK>; 2980 clock-names = "bi_tcxo"; 2981 #clock-cells = <1>; 2982 #power-domain-cells = <1>; 2983 status = "reserved"; /* Owned by ADSP firmware */ 2984 }; 2985 2986 lpass_ag_noc: interconnect@3c40000 { 2987 reg = <0 0x03c40000 0 0xf080>; 2988 compatible = "qcom,sc7280-lpass-ag-noc"; 2989 #interconnect-cells = <2>; 2990 qcom,bcm-voters = <&apps_bcm_voter>; 2991 }; 2992 2993 lpass_tlmm: pinctrl@33c0000 { 2994 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2995 reg = <0 0x033c0000 0x0 0x20000>, 2996 <0 0x03550000 0x0 0x10000>; 2997 gpio-controller; 2998 #gpio-cells = <2>; 2999 gpio-ranges = <&lpass_tlmm 0 0 15>; 3000 3001 lpass_dmic01_clk: dmic01-clk-state { 3002 pins = "gpio6"; 3003 function = "dmic1_clk"; 3004 drive-strength = <8>; 3005 bias-disable; 3006 }; 3007 3008 lpass_dmic01_data: dmic01-data-state { 3009 pins = "gpio7"; 3010 function = "dmic1_data"; 3011 drive-strength = <8>; 3012 bias-pull-down; 3013 }; 3014 3015 lpass_dmic23_clk: dmic23-clk-state { 3016 pins = "gpio8"; 3017 function = "dmic2_clk"; 3018 drive-strength = <8>; 3019 bias-disable; 3020 }; 3021 3022 lpass_dmic23_data: dmic23-data-state { 3023 pins = "gpio9"; 3024 function = "dmic2_data"; 3025 drive-strength = <8>; 3026 bias-pull-down; 3027 }; 3028 3029 lpass_rx_swr_clk: rx-swr-clk-state { 3030 pins = "gpio3"; 3031 function = "swr_rx_clk"; 3032 drive-strength = <2>; 3033 slew-rate = <1>; 3034 bias-disable; 3035 }; 3036 3037 lpass_rx_swr_data: rx-swr-data-state { 3038 pins = "gpio4", "gpio5"; 3039 function = "swr_rx_data"; 3040 drive-strength = <2>; 3041 slew-rate = <1>; 3042 bias-bus-hold; 3043 }; 3044 3045 lpass_tx_swr_clk: tx-swr-clk-state { 3046 pins = "gpio0"; 3047 function = "swr_tx_clk"; 3048 drive-strength = <2>; 3049 slew-rate = <1>; 3050 bias-disable; 3051 }; 3052 3053 lpass_tx_swr_data: tx-swr-data-state { 3054 pins = "gpio1", "gpio2", "gpio14"; 3055 function = "swr_tx_data"; 3056 drive-strength = <2>; 3057 slew-rate = <1>; 3058 bias-bus-hold; 3059 }; 3060 3061 lpass_wsa_swr_clk: wsa-swr-clk-state { 3062 pins = "gpio10"; 3063 function = "wsa_swr_clk"; 3064 drive-strength = <2>; 3065 slew-rate = <1>; 3066 bias-disable; 3067 }; 3068 3069 lpass_wsa_swr_data: wsa-swr-data-state { 3070 pins = "gpio11"; 3071 function = "wsa_swr_data"; 3072 drive-strength = <2>; 3073 slew-rate = <1>; 3074 bias-bus-hold; 3075 }; 3076 }; 3077 3078 gpu: gpu@3d00000 { 3079 compatible = "qcom,adreno-635.0", "qcom,adreno"; 3080 reg = <0 0x03d00000 0 0x40000>, 3081 <0 0x03d9e000 0 0x1000>, 3082 <0 0x03d61000 0 0x800>; 3083 reg-names = "kgsl_3d0_reg_memory", 3084 "cx_mem", 3085 "cx_dbgc"; 3086 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 3087 iommus = <&adreno_smmu 0 0x400>, 3088 <&adreno_smmu 1 0x400>; 3089 operating-points-v2 = <&gpu_opp_table>; 3090 qcom,gmu = <&gmu>; 3091 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 3092 interconnect-names = "gfx-mem"; 3093 #cooling-cells = <2>; 3094 3095 nvmem-cells = <&gpu_speed_bin>; 3096 nvmem-cell-names = "speed_bin"; 3097 3098 status = "disabled"; 3099 3100 gpu_zap_shader: zap-shader { 3101 memory-region = <&gpu_zap_mem>; 3102 }; 3103 3104 gpu_opp_table: opp-table { 3105 compatible = "operating-points-v2"; 3106 3107 opp-315000000 { 3108 opp-hz = /bits/ 64 <315000000>; 3109 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3110 opp-peak-kBps = <1804000>; 3111 opp-supported-hw = <0x17>; 3112 }; 3113 3114 opp-450000000 { 3115 opp-hz = /bits/ 64 <450000000>; 3116 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3117 opp-peak-kBps = <4068000>; 3118 opp-supported-hw = <0x17>; 3119 }; 3120 3121 /* Only applicable for SKUs which has 550Mhz as Fmax */ 3122 opp-550000000-0 { 3123 opp-hz = /bits/ 64 <550000000>; 3124 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3125 opp-peak-kBps = <8368000>; 3126 opp-supported-hw = <0x01>; 3127 }; 3128 3129 opp-550000000-1 { 3130 opp-hz = /bits/ 64 <550000000>; 3131 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3132 opp-peak-kBps = <6832000>; 3133 opp-supported-hw = <0x16>; 3134 }; 3135 3136 opp-608000000 { 3137 opp-hz = /bits/ 64 <608000000>; 3138 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 3139 opp-peak-kBps = <8368000>; 3140 opp-supported-hw = <0x16>; 3141 }; 3142 3143 opp-700000000 { 3144 opp-hz = /bits/ 64 <700000000>; 3145 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3146 opp-peak-kBps = <8532000>; 3147 opp-supported-hw = <0x06>; 3148 }; 3149 3150 opp-812000000 { 3151 opp-hz = /bits/ 64 <812000000>; 3152 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3153 opp-peak-kBps = <8532000>; 3154 opp-supported-hw = <0x06>; 3155 }; 3156 3157 opp-840000000 { 3158 opp-hz = /bits/ 64 <840000000>; 3159 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3160 opp-peak-kBps = <8532000>; 3161 opp-supported-hw = <0x02>; 3162 }; 3163 3164 opp-900000000 { 3165 opp-hz = /bits/ 64 <900000000>; 3166 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3167 opp-peak-kBps = <8532000>; 3168 opp-supported-hw = <0x02>; 3169 }; 3170 }; 3171 }; 3172 3173 gmu: gmu@3d6a000 { 3174 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 3175 reg = <0 0x03d6a000 0 0x34000>, 3176 <0 0x3de0000 0 0x10000>, 3177 <0 0x0b290000 0 0x10000>; 3178 reg-names = "gmu", "rscc", "gmu_pdc"; 3179 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 3180 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 3181 interrupt-names = "hfi", "gmu"; 3182 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 3183 <&gpucc GPU_CC_CXO_CLK>, 3184 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 3185 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3186 <&gpucc GPU_CC_AHB_CLK>, 3187 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3188 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 3189 clock-names = "gmu", 3190 "cxo", 3191 "axi", 3192 "memnoc", 3193 "ahb", 3194 "hub", 3195 "smmu_vote"; 3196 power-domains = <&gpucc GPU_CC_CX_GDSC>, 3197 <&gpucc GPU_CC_GX_GDSC>; 3198 power-domain-names = "cx", 3199 "gx"; 3200 iommus = <&adreno_smmu 5 0x400>; 3201 operating-points-v2 = <&gmu_opp_table>; 3202 3203 gmu_opp_table: opp-table { 3204 compatible = "operating-points-v2"; 3205 3206 opp-200000000 { 3207 opp-hz = /bits/ 64 <200000000>; 3208 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3209 }; 3210 }; 3211 }; 3212 3213 gpucc: clock-controller@3d90000 { 3214 compatible = "qcom,sc7280-gpucc"; 3215 reg = <0 0x03d90000 0 0x9000>; 3216 clocks = <&rpmhcc RPMH_CXO_CLK>, 3217 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3218 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3219 clock-names = "bi_tcxo", 3220 "gcc_gpu_gpll0_clk_src", 3221 "gcc_gpu_gpll0_div_clk_src"; 3222 #clock-cells = <1>; 3223 #reset-cells = <1>; 3224 #power-domain-cells = <1>; 3225 }; 3226 3227 dma@117f000 { 3228 compatible = "qcom,sc7280-dcc", "qcom,dcc"; 3229 reg = <0x0 0x0117f000 0x0 0x1000>, 3230 <0x0 0x01112000 0x0 0x6000>; 3231 }; 3232 3233 adreno_smmu: iommu@3da0000 { 3234 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", 3235 "qcom,smmu-500", "arm,mmu-500"; 3236 reg = <0 0x03da0000 0 0x20000>; 3237 #iommu-cells = <2>; 3238 #global-interrupts = <2>; 3239 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 3240 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 3241 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 3242 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 3243 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 3244 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 3245 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 3246 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 3247 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 3248 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 3249 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 3250 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 3251 3252 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3253 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 3254 <&gpucc GPU_CC_AHB_CLK>, 3255 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 3256 <&gpucc GPU_CC_CX_GMU_CLK>, 3257 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3258 <&gpucc GPU_CC_HUB_AON_CLK>; 3259 clock-names = "gcc_gpu_memnoc_gfx_clk", 3260 "gcc_gpu_snoc_dvm_gfx_clk", 3261 "gpu_cc_ahb_clk", 3262 "gpu_cc_hlos1_vote_gpu_smmu_clk", 3263 "gpu_cc_cx_gmu_clk", 3264 "gpu_cc_hub_cx_int_clk", 3265 "gpu_cc_hub_aon_clk"; 3266 3267 power-domains = <&gpucc GPU_CC_CX_GDSC>; 3268 dma-coherent; 3269 }; 3270 3271 gfx_0_tbu: tbu@3dd9000 { 3272 compatible = "qcom,sc7280-tbu"; 3273 reg = <0x0 0x3dd9000 0x0 0x1000>; 3274 qcom,stream-id-range = <&adreno_smmu 0x0 0x400>; 3275 }; 3276 3277 gfx_1_tbu: tbu@3ddd000 { 3278 compatible = "qcom,sc7280-tbu"; 3279 reg = <0x0 0x3ddd000 0x0 0x1000>; 3280 qcom,stream-id-range = <&adreno_smmu 0x400 0x400>; 3281 }; 3282 3283 remoteproc_mpss: remoteproc@4080000 { 3284 compatible = "qcom,sc7280-mpss-pas"; 3285 reg = <0 0x04080000 0 0x10000>; 3286 3287 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 3288 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3289 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3290 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3291 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3292 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3293 interrupt-names = "wdog", "fatal", "ready", "handover", 3294 "stop-ack", "shutdown-ack"; 3295 3296 clocks = <&rpmhcc RPMH_CXO_CLK>; 3297 clock-names = "xo"; 3298 3299 power-domains = <&rpmhpd SC7280_CX>, 3300 <&rpmhpd SC7280_MSS>; 3301 power-domain-names = "cx", "mss"; 3302 3303 memory-region = <&mpss_mem>; 3304 3305 qcom,qmp = <&aoss_qmp>; 3306 3307 qcom,smem-states = <&modem_smp2p_out 0>; 3308 qcom,smem-state-names = "stop"; 3309 3310 status = "disabled"; 3311 3312 glink-edge { 3313 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 3314 IPCC_MPROC_SIGNAL_GLINK_QMP 3315 IRQ_TYPE_EDGE_RISING>; 3316 mboxes = <&ipcc IPCC_CLIENT_MPSS 3317 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3318 label = "modem"; 3319 qcom,remote-pid = <1>; 3320 }; 3321 }; 3322 3323 stm@6002000 { 3324 compatible = "arm,coresight-stm", "arm,primecell"; 3325 reg = <0 0x06002000 0 0x1000>, 3326 <0 0x16280000 0 0x180000>; 3327 reg-names = "stm-base", "stm-stimulus-base"; 3328 3329 clocks = <&aoss_qmp>; 3330 clock-names = "apb_pclk"; 3331 3332 out-ports { 3333 port { 3334 stm_out: endpoint { 3335 remote-endpoint = <&funnel0_in7>; 3336 }; 3337 }; 3338 }; 3339 }; 3340 3341 funnel@6041000 { 3342 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3343 reg = <0 0x06041000 0 0x1000>; 3344 3345 clocks = <&aoss_qmp>; 3346 clock-names = "apb_pclk"; 3347 3348 out-ports { 3349 port { 3350 funnel0_out: endpoint { 3351 remote-endpoint = <&merge_funnel_in0>; 3352 }; 3353 }; 3354 }; 3355 3356 in-ports { 3357 #address-cells = <1>; 3358 #size-cells = <0>; 3359 3360 port@7 { 3361 reg = <7>; 3362 funnel0_in7: endpoint { 3363 remote-endpoint = <&stm_out>; 3364 }; 3365 }; 3366 }; 3367 }; 3368 3369 funnel@6042000 { 3370 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3371 reg = <0 0x06042000 0 0x1000>; 3372 3373 clocks = <&aoss_qmp>; 3374 clock-names = "apb_pclk"; 3375 3376 out-ports { 3377 port { 3378 funnel1_out: endpoint { 3379 remote-endpoint = <&merge_funnel_in1>; 3380 }; 3381 }; 3382 }; 3383 3384 in-ports { 3385 #address-cells = <1>; 3386 #size-cells = <0>; 3387 3388 port@4 { 3389 reg = <4>; 3390 funnel1_in4: endpoint { 3391 remote-endpoint = <&apss_merge_funnel_out>; 3392 }; 3393 }; 3394 }; 3395 }; 3396 3397 funnel@6045000 { 3398 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3399 reg = <0 0x06045000 0 0x1000>; 3400 3401 clocks = <&aoss_qmp>; 3402 clock-names = "apb_pclk"; 3403 3404 out-ports { 3405 port { 3406 merge_funnel_out: endpoint { 3407 remote-endpoint = <&swao_funnel_in>; 3408 }; 3409 }; 3410 }; 3411 3412 in-ports { 3413 #address-cells = <1>; 3414 #size-cells = <0>; 3415 3416 port@0 { 3417 reg = <0>; 3418 merge_funnel_in0: endpoint { 3419 remote-endpoint = <&funnel0_out>; 3420 }; 3421 }; 3422 3423 port@1 { 3424 reg = <1>; 3425 merge_funnel_in1: endpoint { 3426 remote-endpoint = <&funnel1_out>; 3427 }; 3428 }; 3429 }; 3430 }; 3431 3432 replicator@6046000 { 3433 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3434 reg = <0 0x06046000 0 0x1000>; 3435 3436 clocks = <&aoss_qmp>; 3437 clock-names = "apb_pclk"; 3438 3439 out-ports { 3440 port { 3441 replicator_out: endpoint { 3442 remote-endpoint = <&etr_in>; 3443 }; 3444 }; 3445 }; 3446 3447 in-ports { 3448 port { 3449 replicator_in: endpoint { 3450 remote-endpoint = <&swao_replicator_out>; 3451 }; 3452 }; 3453 }; 3454 }; 3455 3456 etr@6048000 { 3457 compatible = "arm,coresight-tmc", "arm,primecell"; 3458 reg = <0 0x06048000 0 0x1000>; 3459 iommus = <&apps_smmu 0x04c0 0>; 3460 3461 clocks = <&aoss_qmp>; 3462 clock-names = "apb_pclk"; 3463 arm,scatter-gather; 3464 3465 in-ports { 3466 port { 3467 etr_in: endpoint { 3468 remote-endpoint = <&replicator_out>; 3469 }; 3470 }; 3471 }; 3472 }; 3473 3474 funnel@6b04000 { 3475 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3476 reg = <0 0x06b04000 0 0x1000>; 3477 3478 clocks = <&aoss_qmp>; 3479 clock-names = "apb_pclk"; 3480 3481 out-ports { 3482 port { 3483 swao_funnel_out: endpoint { 3484 remote-endpoint = <&etf_in>; 3485 }; 3486 }; 3487 }; 3488 3489 in-ports { 3490 #address-cells = <1>; 3491 #size-cells = <0>; 3492 3493 port@7 { 3494 reg = <7>; 3495 swao_funnel_in: endpoint { 3496 remote-endpoint = <&merge_funnel_out>; 3497 }; 3498 }; 3499 }; 3500 }; 3501 3502 etf@6b05000 { 3503 compatible = "arm,coresight-tmc", "arm,primecell"; 3504 reg = <0 0x06b05000 0 0x1000>; 3505 3506 clocks = <&aoss_qmp>; 3507 clock-names = "apb_pclk"; 3508 3509 out-ports { 3510 port { 3511 etf_out: endpoint { 3512 remote-endpoint = <&swao_replicator_in>; 3513 }; 3514 }; 3515 }; 3516 3517 in-ports { 3518 port { 3519 etf_in: endpoint { 3520 remote-endpoint = <&swao_funnel_out>; 3521 }; 3522 }; 3523 }; 3524 }; 3525 3526 replicator@6b06000 { 3527 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3528 reg = <0 0x06b06000 0 0x1000>; 3529 3530 clocks = <&aoss_qmp>; 3531 clock-names = "apb_pclk"; 3532 qcom,replicator-loses-context; 3533 3534 out-ports { 3535 port { 3536 swao_replicator_out: endpoint { 3537 remote-endpoint = <&replicator_in>; 3538 }; 3539 }; 3540 }; 3541 3542 in-ports { 3543 port { 3544 swao_replicator_in: endpoint { 3545 remote-endpoint = <&etf_out>; 3546 }; 3547 }; 3548 }; 3549 }; 3550 3551 etm@7040000 { 3552 compatible = "arm,coresight-etm4x", "arm,primecell"; 3553 reg = <0 0x07040000 0 0x1000>; 3554 3555 cpu = <&cpu0>; 3556 3557 clocks = <&aoss_qmp>; 3558 clock-names = "apb_pclk"; 3559 arm,coresight-loses-context-with-cpu; 3560 qcom,skip-power-up; 3561 3562 out-ports { 3563 port { 3564 etm0_out: endpoint { 3565 remote-endpoint = <&apss_funnel_in0>; 3566 }; 3567 }; 3568 }; 3569 }; 3570 3571 etm@7140000 { 3572 compatible = "arm,coresight-etm4x", "arm,primecell"; 3573 reg = <0 0x07140000 0 0x1000>; 3574 3575 cpu = <&cpu1>; 3576 3577 clocks = <&aoss_qmp>; 3578 clock-names = "apb_pclk"; 3579 arm,coresight-loses-context-with-cpu; 3580 qcom,skip-power-up; 3581 3582 out-ports { 3583 port { 3584 etm1_out: endpoint { 3585 remote-endpoint = <&apss_funnel_in1>; 3586 }; 3587 }; 3588 }; 3589 }; 3590 3591 etm@7240000 { 3592 compatible = "arm,coresight-etm4x", "arm,primecell"; 3593 reg = <0 0x07240000 0 0x1000>; 3594 3595 cpu = <&cpu2>; 3596 3597 clocks = <&aoss_qmp>; 3598 clock-names = "apb_pclk"; 3599 arm,coresight-loses-context-with-cpu; 3600 qcom,skip-power-up; 3601 3602 out-ports { 3603 port { 3604 etm2_out: endpoint { 3605 remote-endpoint = <&apss_funnel_in2>; 3606 }; 3607 }; 3608 }; 3609 }; 3610 3611 etm@7340000 { 3612 compatible = "arm,coresight-etm4x", "arm,primecell"; 3613 reg = <0 0x07340000 0 0x1000>; 3614 3615 cpu = <&cpu3>; 3616 3617 clocks = <&aoss_qmp>; 3618 clock-names = "apb_pclk"; 3619 arm,coresight-loses-context-with-cpu; 3620 qcom,skip-power-up; 3621 3622 out-ports { 3623 port { 3624 etm3_out: endpoint { 3625 remote-endpoint = <&apss_funnel_in3>; 3626 }; 3627 }; 3628 }; 3629 }; 3630 3631 etm@7440000 { 3632 compatible = "arm,coresight-etm4x", "arm,primecell"; 3633 reg = <0 0x07440000 0 0x1000>; 3634 3635 cpu = <&cpu4>; 3636 3637 clocks = <&aoss_qmp>; 3638 clock-names = "apb_pclk"; 3639 arm,coresight-loses-context-with-cpu; 3640 qcom,skip-power-up; 3641 3642 out-ports { 3643 port { 3644 etm4_out: endpoint { 3645 remote-endpoint = <&apss_funnel_in4>; 3646 }; 3647 }; 3648 }; 3649 }; 3650 3651 etm@7540000 { 3652 compatible = "arm,coresight-etm4x", "arm,primecell"; 3653 reg = <0 0x07540000 0 0x1000>; 3654 3655 cpu = <&cpu5>; 3656 3657 clocks = <&aoss_qmp>; 3658 clock-names = "apb_pclk"; 3659 arm,coresight-loses-context-with-cpu; 3660 qcom,skip-power-up; 3661 3662 out-ports { 3663 port { 3664 etm5_out: endpoint { 3665 remote-endpoint = <&apss_funnel_in5>; 3666 }; 3667 }; 3668 }; 3669 }; 3670 3671 etm@7640000 { 3672 compatible = "arm,coresight-etm4x", "arm,primecell"; 3673 reg = <0 0x07640000 0 0x1000>; 3674 3675 cpu = <&cpu6>; 3676 3677 clocks = <&aoss_qmp>; 3678 clock-names = "apb_pclk"; 3679 arm,coresight-loses-context-with-cpu; 3680 qcom,skip-power-up; 3681 3682 out-ports { 3683 port { 3684 etm6_out: endpoint { 3685 remote-endpoint = <&apss_funnel_in6>; 3686 }; 3687 }; 3688 }; 3689 }; 3690 3691 etm@7740000 { 3692 compatible = "arm,coresight-etm4x", "arm,primecell"; 3693 reg = <0 0x07740000 0 0x1000>; 3694 3695 cpu = <&cpu7>; 3696 3697 clocks = <&aoss_qmp>; 3698 clock-names = "apb_pclk"; 3699 arm,coresight-loses-context-with-cpu; 3700 qcom,skip-power-up; 3701 3702 out-ports { 3703 port { 3704 etm7_out: endpoint { 3705 remote-endpoint = <&apss_funnel_in7>; 3706 }; 3707 }; 3708 }; 3709 }; 3710 3711 funnel@7800000 { /* APSS Funnel */ 3712 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3713 reg = <0 0x07800000 0 0x1000>; 3714 3715 clocks = <&aoss_qmp>; 3716 clock-names = "apb_pclk"; 3717 3718 out-ports { 3719 port { 3720 apss_funnel_out: endpoint { 3721 remote-endpoint = <&apss_merge_funnel_in>; 3722 }; 3723 }; 3724 }; 3725 3726 in-ports { 3727 #address-cells = <1>; 3728 #size-cells = <0>; 3729 3730 port@0 { 3731 reg = <0>; 3732 apss_funnel_in0: endpoint { 3733 remote-endpoint = <&etm0_out>; 3734 }; 3735 }; 3736 3737 port@1 { 3738 reg = <1>; 3739 apss_funnel_in1: endpoint { 3740 remote-endpoint = <&etm1_out>; 3741 }; 3742 }; 3743 3744 port@2 { 3745 reg = <2>; 3746 apss_funnel_in2: endpoint { 3747 remote-endpoint = <&etm2_out>; 3748 }; 3749 }; 3750 3751 port@3 { 3752 reg = <3>; 3753 apss_funnel_in3: endpoint { 3754 remote-endpoint = <&etm3_out>; 3755 }; 3756 }; 3757 3758 port@4 { 3759 reg = <4>; 3760 apss_funnel_in4: endpoint { 3761 remote-endpoint = <&etm4_out>; 3762 }; 3763 }; 3764 3765 port@5 { 3766 reg = <5>; 3767 apss_funnel_in5: endpoint { 3768 remote-endpoint = <&etm5_out>; 3769 }; 3770 }; 3771 3772 port@6 { 3773 reg = <6>; 3774 apss_funnel_in6: endpoint { 3775 remote-endpoint = <&etm6_out>; 3776 }; 3777 }; 3778 3779 port@7 { 3780 reg = <7>; 3781 apss_funnel_in7: endpoint { 3782 remote-endpoint = <&etm7_out>; 3783 }; 3784 }; 3785 }; 3786 }; 3787 3788 funnel@7810000 { 3789 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3790 reg = <0 0x07810000 0 0x1000>; 3791 3792 clocks = <&aoss_qmp>; 3793 clock-names = "apb_pclk"; 3794 3795 out-ports { 3796 port { 3797 apss_merge_funnel_out: endpoint { 3798 remote-endpoint = <&funnel1_in4>; 3799 }; 3800 }; 3801 }; 3802 3803 in-ports { 3804 port { 3805 apss_merge_funnel_in: endpoint { 3806 remote-endpoint = <&apss_funnel_out>; 3807 }; 3808 }; 3809 }; 3810 }; 3811 3812 sdhc_2: mmc@8804000 { 3813 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3814 pinctrl-names = "default", "sleep"; 3815 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3816 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3817 status = "disabled"; 3818 3819 reg = <0 0x08804000 0 0x1000>; 3820 3821 iommus = <&apps_smmu 0x100 0x0>; 3822 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3823 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3824 interrupt-names = "hc_irq", "pwr_irq"; 3825 3826 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3827 <&gcc GCC_SDCC2_APPS_CLK>, 3828 <&rpmhcc RPMH_CXO_CLK>; 3829 clock-names = "iface", "core", "xo"; 3830 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3831 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3832 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3833 power-domains = <&rpmhpd SC7280_CX>; 3834 operating-points-v2 = <&sdhc2_opp_table>; 3835 3836 bus-width = <4>; 3837 dma-coherent; 3838 3839 qcom,dll-config = <0x0007642c>; 3840 3841 resets = <&gcc GCC_SDCC2_BCR>; 3842 3843 sdhc2_opp_table: opp-table { 3844 compatible = "operating-points-v2"; 3845 3846 opp-100000000 { 3847 opp-hz = /bits/ 64 <100000000>; 3848 required-opps = <&rpmhpd_opp_low_svs>; 3849 opp-peak-kBps = <1800000 400000>; 3850 opp-avg-kBps = <100000 0>; 3851 }; 3852 3853 opp-202000000 { 3854 opp-hz = /bits/ 64 <202000000>; 3855 required-opps = <&rpmhpd_opp_nom>; 3856 opp-peak-kBps = <5400000 1600000>; 3857 opp-avg-kBps = <200000 0>; 3858 }; 3859 }; 3860 }; 3861 3862 usb_1_hsphy: phy@88e3000 { 3863 compatible = "qcom,sc7280-usb-hs-phy", 3864 "qcom,usb-snps-hs-7nm-phy"; 3865 reg = <0 0x088e3000 0 0x400>; 3866 status = "disabled"; 3867 #phy-cells = <0>; 3868 3869 clocks = <&rpmhcc RPMH_CXO_CLK>; 3870 clock-names = "ref"; 3871 3872 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3873 }; 3874 3875 usb_2_hsphy: phy@88e4000 { 3876 compatible = "qcom,sc7280-usb-hs-phy", 3877 "qcom,usb-snps-hs-7nm-phy"; 3878 reg = <0 0x088e4000 0 0x400>; 3879 status = "disabled"; 3880 #phy-cells = <0>; 3881 3882 clocks = <&rpmhcc RPMH_CXO_CLK>; 3883 clock-names = "ref"; 3884 3885 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3886 }; 3887 3888 usb_1_qmpphy: phy@88e8000 { 3889 compatible = "qcom,sc7280-qmp-usb3-dp-phy"; 3890 reg = <0 0x088e8000 0 0x3000>; 3891 status = "disabled"; 3892 3893 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3894 <&rpmhcc RPMH_CXO_CLK>, 3895 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3896 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3897 clock-names = "aux", 3898 "ref", 3899 "com_aux", 3900 "usb3_pipe"; 3901 3902 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3903 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3904 reset-names = "phy", "common"; 3905 3906 #clock-cells = <1>; 3907 #phy-cells = <1>; 3908 3909 orientation-switch; 3910 3911 ports { 3912 #address-cells = <1>; 3913 #size-cells = <0>; 3914 3915 port@0 { 3916 reg = <0>; 3917 3918 usb_dp_qmpphy_out: endpoint { 3919 }; 3920 }; 3921 3922 port@1 { 3923 reg = <1>; 3924 3925 usb_dp_qmpphy_usb_ss_in: endpoint { 3926 remote-endpoint = <&usb_1_dwc3_ss>; 3927 }; 3928 }; 3929 3930 port@2 { 3931 reg = <2>; 3932 3933 usb_dp_qmpphy_dp_in: endpoint { 3934 remote-endpoint = <&mdss_dp_out>; 3935 }; 3936 }; 3937 }; 3938 }; 3939 3940 usb_2: usb@8c00000 { 3941 compatible = "qcom,sc7280-dwc3", "qcom,snps-dwc3"; 3942 reg = <0 0x08c00000 0 0xfc100>; 3943 status = "disabled"; 3944 3945 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3946 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3947 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3948 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3949 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3950 clock-names = "cfg_noc", 3951 "core", 3952 "iface", 3953 "sleep", 3954 "mock_utmi"; 3955 3956 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3957 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3958 assigned-clock-rates = <19200000>, <200000000>; 3959 3960 interrupts-extended = <&intc GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 3961 <&intc GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 3962 <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3963 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 3964 <&pdc 13 IRQ_TYPE_EDGE_BOTH>; 3965 interrupt-names = "dwc_usb3", 3966 "pwr_event", 3967 "hs_phy_irq", 3968 "dp_hs_phy_irq", 3969 "dm_hs_phy_irq"; 3970 3971 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3972 required-opps = <&rpmhpd_opp_nom>; 3973 3974 resets = <&gcc GCC_USB30_SEC_BCR>; 3975 3976 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3977 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3978 interconnect-names = "usb-ddr", "apps-usb"; 3979 3980 iommus = <&apps_smmu 0xa0 0x0>; 3981 snps,dis_u2_susphy_quirk; 3982 snps,dis_enblslpm_quirk; 3983 snps,dis-u1-entry-quirk; 3984 snps,dis-u2-entry-quirk; 3985 phys = <&usb_2_hsphy>; 3986 phy-names = "usb2-phy"; 3987 maximum-speed = "high-speed"; 3988 usb-role-switch; 3989 3990 port { 3991 usb2_role_switch: endpoint { 3992 remote-endpoint = <&eud_ep>; 3993 }; 3994 }; 3995 }; 3996 3997 qspi: spi@88dc000 { 3998 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3999 reg = <0 0x088dc000 0 0x1000>; 4000 iommus = <&apps_smmu 0x20 0x0>; 4001 #address-cells = <1>; 4002 #size-cells = <0>; 4003 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 4004 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 4005 <&gcc GCC_QSPI_CORE_CLK>; 4006 clock-names = "iface", "core"; 4007 interconnects = <&gem_noc MASTER_APPSS_PROC 0 4008 &cnoc2 SLAVE_QSPI_0 0>; 4009 interconnect-names = "qspi-config"; 4010 power-domains = <&rpmhpd SC7280_CX>; 4011 operating-points-v2 = <&qspi_opp_table>; 4012 status = "disabled"; 4013 }; 4014 4015 remoteproc_adsp: remoteproc@3700000 { 4016 compatible = "qcom,sc7280-adsp-pas"; 4017 reg = <0 0x03700000 0 0x100>; 4018 4019 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 4020 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4021 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 4022 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 4023 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 4024 <&adsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 4025 interrupt-names = "wdog", "fatal", "ready", "handover", 4026 "stop-ack", "shutdown-ack"; 4027 4028 clocks = <&rpmhcc RPMH_CXO_CLK>; 4029 clock-names = "xo"; 4030 4031 power-domains = <&rpmhpd SC7280_LCX>, 4032 <&rpmhpd SC7280_LMX>; 4033 power-domain-names = "lcx", "lmx"; 4034 4035 memory-region = <&adsp_mem>; 4036 4037 qcom,qmp = <&aoss_qmp>; 4038 4039 qcom,smem-states = <&adsp_smp2p_out 0>; 4040 qcom,smem-state-names = "stop"; 4041 4042 status = "disabled"; 4043 4044 remoteproc_adsp_glink: glink-edge { 4045 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 4046 IPCC_MPROC_SIGNAL_GLINK_QMP 4047 IRQ_TYPE_EDGE_RISING>; 4048 4049 mboxes = <&ipcc IPCC_CLIENT_LPASS 4050 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4051 4052 label = "lpass"; 4053 qcom,remote-pid = <2>; 4054 4055 apr { 4056 compatible = "qcom,apr-v2"; 4057 qcom,glink-channels = "apr_audio_svc"; 4058 qcom,domain = <APR_DOMAIN_ADSP>; 4059 #address-cells = <1>; 4060 #size-cells = <0>; 4061 4062 service@3 { 4063 reg = <APR_SVC_ADSP_CORE>; 4064 compatible = "qcom,q6core"; 4065 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4066 }; 4067 4068 q6afe: service@4 { 4069 compatible = "qcom,q6afe"; 4070 reg = <APR_SVC_AFE>; 4071 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4072 4073 q6afedai: dais { 4074 compatible = "qcom,q6afe-dais"; 4075 #address-cells = <1>; 4076 #size-cells = <0>; 4077 #sound-dai-cells = <1>; 4078 }; 4079 4080 q6afecc: clock-controller { 4081 compatible = "qcom,q6afe-clocks"; 4082 #clock-cells = <2>; 4083 }; 4084 4085 q6usbdai: usbd { 4086 compatible = "qcom,q6usb"; 4087 iommus = <&apps_smmu 0x180f 0x0>; 4088 #sound-dai-cells = <1>; 4089 qcom,usb-audio-intr-idx = /bits/ 16 <2>; 4090 }; 4091 }; 4092 4093 q6asm: service@7 { 4094 compatible = "qcom,q6asm"; 4095 reg = <APR_SVC_ASM>; 4096 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4097 4098 q6asmdai: dais { 4099 compatible = "qcom,q6asm-dais"; 4100 #address-cells = <1>; 4101 #size-cells = <0>; 4102 #sound-dai-cells = <1>; 4103 iommus = <&apps_smmu 0x1801 0x0>; 4104 4105 dai@0 { 4106 reg = <MSM_FRONTEND_DAI_MULTIMEDIA1>; 4107 }; 4108 4109 dai@1 { 4110 reg = <MSM_FRONTEND_DAI_MULTIMEDIA2>; 4111 }; 4112 4113 dai@2 { 4114 reg = <MSM_FRONTEND_DAI_MULTIMEDIA3>; 4115 }; 4116 }; 4117 }; 4118 4119 q6adm: service@8 { 4120 compatible = "qcom,q6adm"; 4121 reg = <APR_SVC_ADM>; 4122 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4123 4124 q6routing: routing { 4125 compatible = "qcom,q6adm-routing"; 4126 #sound-dai-cells = <0>; 4127 }; 4128 }; 4129 }; 4130 4131 fastrpc { 4132 compatible = "qcom,fastrpc"; 4133 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4134 label = "adsp"; 4135 qcom,non-secure-domain; 4136 #address-cells = <1>; 4137 #size-cells = <0>; 4138 4139 compute-cb@3 { 4140 compatible = "qcom,fastrpc-compute-cb"; 4141 reg = <3>; 4142 iommus = <&apps_smmu 0x1803 0x0>; 4143 dma-coherent; 4144 }; 4145 4146 compute-cb@4 { 4147 compatible = "qcom,fastrpc-compute-cb"; 4148 reg = <4>; 4149 iommus = <&apps_smmu 0x1804 0x0>; 4150 dma-coherent; 4151 }; 4152 4153 compute-cb@5 { 4154 compatible = "qcom,fastrpc-compute-cb"; 4155 reg = <5>; 4156 iommus = <&apps_smmu 0x1805 0x0>; 4157 dma-coherent; 4158 }; 4159 }; 4160 }; 4161 }; 4162 4163 remoteproc_wpss: remoteproc@8a00000 { 4164 compatible = "qcom,sc7280-wpss-pas"; 4165 reg = <0 0x08a00000 0 0x10000>; 4166 4167 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 4168 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4169 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 4170 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 4171 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 4172 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 4173 interrupt-names = "wdog", "fatal", "ready", "handover", 4174 "stop-ack", "shutdown-ack"; 4175 4176 clocks = <&rpmhcc RPMH_CXO_CLK>; 4177 clock-names = "xo"; 4178 4179 power-domains = <&rpmhpd SC7280_CX>, 4180 <&rpmhpd SC7280_MX>; 4181 power-domain-names = "cx", "mx"; 4182 4183 memory-region = <&wpss_mem>; 4184 4185 qcom,qmp = <&aoss_qmp>; 4186 4187 qcom,smem-states = <&wpss_smp2p_out 0>; 4188 qcom,smem-state-names = "stop"; 4189 4190 4191 status = "disabled"; 4192 4193 glink-edge { 4194 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 4195 IPCC_MPROC_SIGNAL_GLINK_QMP 4196 IRQ_TYPE_EDGE_RISING>; 4197 mboxes = <&ipcc IPCC_CLIENT_WPSS 4198 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4199 4200 label = "wpss"; 4201 qcom,remote-pid = <13>; 4202 }; 4203 }; 4204 4205 pmu@9091000 { 4206 compatible = "qcom,sc7280-llcc-bwmon"; 4207 reg = <0 0x09091000 0 0x1000>; 4208 4209 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 4210 4211 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 4212 4213 operating-points-v2 = <&llcc_bwmon_opp_table>; 4214 4215 llcc_bwmon_opp_table: opp-table { 4216 compatible = "operating-points-v2"; 4217 4218 opp-0 { 4219 opp-peak-kBps = <800000>; 4220 }; 4221 opp-1 { 4222 opp-peak-kBps = <1804000>; 4223 }; 4224 opp-2 { 4225 opp-peak-kBps = <2188000>; 4226 }; 4227 opp-3 { 4228 opp-peak-kBps = <3072000>; 4229 }; 4230 opp-4 { 4231 opp-peak-kBps = <4068000>; 4232 }; 4233 opp-5 { 4234 opp-peak-kBps = <6220000>; 4235 }; 4236 opp-6 { 4237 opp-peak-kBps = <6832000>; 4238 }; 4239 opp-7 { 4240 opp-peak-kBps = <8532000>; 4241 }; 4242 opp-8 { 4243 opp-peak-kBps = <10944000>; 4244 }; 4245 opp-9 { 4246 opp-peak-kBps = <12787200>; 4247 }; 4248 }; 4249 }; 4250 4251 pmu@90b6400 { 4252 compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon"; 4253 reg = <0 0x090b6400 0 0x600>; 4254 4255 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4256 4257 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 4258 operating-points-v2 = <&cpu_bwmon_opp_table>; 4259 4260 cpu_bwmon_opp_table: opp-table { 4261 compatible = "operating-points-v2"; 4262 4263 opp-0 { 4264 opp-peak-kBps = <2400000>; 4265 }; 4266 opp-1 { 4267 opp-peak-kBps = <4800000>; 4268 }; 4269 opp-2 { 4270 opp-peak-kBps = <7456000>; 4271 }; 4272 opp-3 { 4273 opp-peak-kBps = <9600000>; 4274 }; 4275 opp-4 { 4276 opp-peak-kBps = <12896000>; 4277 }; 4278 opp-5 { 4279 opp-peak-kBps = <14928000>; 4280 }; 4281 opp-6 { 4282 opp-peak-kBps = <17056000>; 4283 }; 4284 }; 4285 }; 4286 4287 dc_noc: interconnect@90e0000 { 4288 reg = <0 0x090e0000 0 0x5080>; 4289 compatible = "qcom,sc7280-dc-noc"; 4290 #interconnect-cells = <2>; 4291 qcom,bcm-voters = <&apps_bcm_voter>; 4292 }; 4293 4294 gem_noc: interconnect@9100000 { 4295 reg = <0 0x09100000 0 0xe2200>; 4296 compatible = "qcom,sc7280-gem-noc"; 4297 #interconnect-cells = <2>; 4298 qcom,bcm-voters = <&apps_bcm_voter>; 4299 }; 4300 4301 system-cache-controller@9200000 { 4302 compatible = "qcom,sc7280-llcc"; 4303 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 4304 <0 0x09600000 0 0x58000>; 4305 reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; 4306 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 4307 }; 4308 4309 eud: eud@88e0000 { 4310 compatible = "qcom,sc7280-eud", "qcom,eud"; 4311 reg = <0 0x88e0000 0 0x2000>, 4312 <0 0x88e2000 0 0x1000>; 4313 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 4314 4315 status = "disabled"; 4316 4317 ports { 4318 #address-cells = <1>; 4319 #size-cells = <0>; 4320 4321 port@0 { 4322 reg = <0>; 4323 eud_ep: endpoint { 4324 remote-endpoint = <&usb2_role_switch>; 4325 }; 4326 }; 4327 }; 4328 }; 4329 4330 nsp_noc: interconnect@a0c0000 { 4331 reg = <0 0x0a0c0000 0 0x10000>; 4332 compatible = "qcom,sc7280-nsp-noc"; 4333 #interconnect-cells = <2>; 4334 qcom,bcm-voters = <&apps_bcm_voter>; 4335 }; 4336 4337 remoteproc_cdsp: remoteproc@a300000 { 4338 compatible = "qcom,sc7280-cdsp-pas"; 4339 reg = <0 0x0a300000 0 0x10000>; 4340 4341 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 4342 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4343 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 4344 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 4345 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 4346 <&cdsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 4347 interrupt-names = "wdog", "fatal", "ready", "handover", 4348 "stop-ack", "shutdown-ack"; 4349 4350 clocks = <&rpmhcc RPMH_CXO_CLK>; 4351 clock-names = "xo"; 4352 4353 power-domains = <&rpmhpd SC7280_CX>, 4354 <&rpmhpd SC7280_MX>; 4355 power-domain-names = "cx", "mx"; 4356 4357 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 4358 4359 memory-region = <&cdsp_mem>; 4360 4361 qcom,qmp = <&aoss_qmp>; 4362 4363 qcom,smem-states = <&cdsp_smp2p_out 0>; 4364 qcom,smem-state-names = "stop"; 4365 4366 status = "disabled"; 4367 4368 glink-edge { 4369 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4370 IPCC_MPROC_SIGNAL_GLINK_QMP 4371 IRQ_TYPE_EDGE_RISING>; 4372 mboxes = <&ipcc IPCC_CLIENT_CDSP 4373 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4374 4375 label = "cdsp"; 4376 qcom,remote-pid = <5>; 4377 4378 fastrpc { 4379 compatible = "qcom,fastrpc"; 4380 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4381 label = "cdsp"; 4382 qcom,non-secure-domain; 4383 #address-cells = <1>; 4384 #size-cells = <0>; 4385 4386 compute-cb@1 { 4387 compatible = "qcom,fastrpc-compute-cb"; 4388 reg = <1>; 4389 iommus = <&apps_smmu 0x11a1 0x0420>, 4390 <&apps_smmu 0x1181 0x0420>; 4391 dma-coherent; 4392 }; 4393 4394 compute-cb@2 { 4395 compatible = "qcom,fastrpc-compute-cb"; 4396 reg = <2>; 4397 iommus = <&apps_smmu 0x11a2 0x0420>, 4398 <&apps_smmu 0x1182 0x0420>; 4399 dma-coherent; 4400 }; 4401 4402 compute-cb@3 { 4403 compatible = "qcom,fastrpc-compute-cb"; 4404 reg = <3>; 4405 iommus = <&apps_smmu 0x11a3 0x0420>, 4406 <&apps_smmu 0x1183 0x0420>; 4407 dma-coherent; 4408 }; 4409 4410 compute-cb@4 { 4411 compatible = "qcom,fastrpc-compute-cb"; 4412 reg = <4>; 4413 iommus = <&apps_smmu 0x11a4 0x0420>, 4414 <&apps_smmu 0x1184 0x0420>; 4415 dma-coherent; 4416 }; 4417 4418 compute-cb@5 { 4419 compatible = "qcom,fastrpc-compute-cb"; 4420 reg = <5>; 4421 iommus = <&apps_smmu 0x11a5 0x0420>, 4422 <&apps_smmu 0x1185 0x0420>; 4423 dma-coherent; 4424 }; 4425 4426 compute-cb@6 { 4427 compatible = "qcom,fastrpc-compute-cb"; 4428 reg = <6>; 4429 iommus = <&apps_smmu 0x11a6 0x0420>, 4430 <&apps_smmu 0x1186 0x0420>; 4431 dma-coherent; 4432 }; 4433 4434 compute-cb@7 { 4435 compatible = "qcom,fastrpc-compute-cb"; 4436 reg = <7>; 4437 iommus = <&apps_smmu 0x11a7 0x0420>, 4438 <&apps_smmu 0x1187 0x0420>; 4439 dma-coherent; 4440 }; 4441 4442 compute-cb@8 { 4443 compatible = "qcom,fastrpc-compute-cb"; 4444 reg = <8>; 4445 iommus = <&apps_smmu 0x11a8 0x0420>, 4446 <&apps_smmu 0x1188 0x0420>; 4447 dma-coherent; 4448 }; 4449 4450 /* note: secure cb9 in downstream */ 4451 4452 compute-cb@11 { 4453 compatible = "qcom,fastrpc-compute-cb"; 4454 reg = <11>; 4455 iommus = <&apps_smmu 0x11ab 0x0420>, 4456 <&apps_smmu 0x118b 0x0420>; 4457 dma-coherent; 4458 }; 4459 4460 compute-cb@12 { 4461 compatible = "qcom,fastrpc-compute-cb"; 4462 reg = <12>; 4463 iommus = <&apps_smmu 0x11ac 0x0420>, 4464 <&apps_smmu 0x118c 0x0420>; 4465 dma-coherent; 4466 }; 4467 4468 compute-cb@13 { 4469 compatible = "qcom,fastrpc-compute-cb"; 4470 reg = <13>; 4471 iommus = <&apps_smmu 0x11ad 0x0420>, 4472 <&apps_smmu 0x118d 0x0420>; 4473 dma-coherent; 4474 }; 4475 4476 compute-cb@14 { 4477 compatible = "qcom,fastrpc-compute-cb"; 4478 reg = <14>; 4479 iommus = <&apps_smmu 0x11ae 0x0420>, 4480 <&apps_smmu 0x118e 0x0420>; 4481 dma-coherent; 4482 }; 4483 }; 4484 }; 4485 }; 4486 4487 usb_1: usb@a600000 { 4488 compatible = "qcom,sc7280-dwc3", "qcom,snps-dwc3"; 4489 reg = <0 0x0a600000 0 0xfc100>; 4490 status = "disabled"; 4491 4492 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4493 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4494 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4495 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4496 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 4497 clock-names = "cfg_noc", 4498 "core", 4499 "iface", 4500 "sleep", 4501 "mock_utmi"; 4502 4503 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4504 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4505 assigned-clock-rates = <19200000>, <200000000>; 4506 4507 interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 4508 <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4509 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4510 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4511 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4512 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 4513 interrupt-names = "dwc_usb3", 4514 "pwr_event", 4515 "hs_phy_irq", 4516 "dp_hs_phy_irq", 4517 "dm_hs_phy_irq", 4518 "ss_phy_irq"; 4519 4520 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 4521 required-opps = <&rpmhpd_opp_nom>; 4522 4523 resets = <&gcc GCC_USB30_PRIM_BCR>; 4524 4525 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 4526 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 4527 interconnect-names = "usb-ddr", "apps-usb"; 4528 4529 wakeup-source; 4530 4531 iommus = <&apps_smmu 0xe0 0x0>; 4532 snps,dis_u2_susphy_quirk; 4533 snps,dis_enblslpm_quirk; 4534 snps,parkmode-disable-ss-quirk; 4535 snps,dis-u1-entry-quirk; 4536 snps,dis-u2-entry-quirk; 4537 num-hc-interrupters = /bits/ 16 <3>; 4538 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4539 phy-names = "usb2-phy", "usb3-phy"; 4540 maximum-speed = "super-speed"; 4541 4542 ports { 4543 #address-cells = <1>; 4544 #size-cells = <0>; 4545 4546 port@0 { 4547 reg = <0>; 4548 4549 usb_1_dwc3_hs: endpoint { 4550 }; 4551 }; 4552 4553 port@1 { 4554 reg = <1>; 4555 4556 usb_1_dwc3_ss: endpoint { 4557 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; 4558 }; 4559 }; 4560 }; 4561 }; 4562 4563 venus: video-codec@aa00000 { 4564 compatible = "qcom,sc7280-venus"; 4565 reg = <0 0x0aa00000 0 0xd0600>; 4566 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4567 4568 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 4569 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 4570 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 4571 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 4572 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 4573 clock-names = "core", "bus", "iface", 4574 "vcodec_core", "vcodec_bus"; 4575 4576 power-domains = <&videocc MVSC_GDSC>, 4577 <&videocc MVS0_GDSC>, 4578 <&rpmhpd SC7280_CX>; 4579 power-domain-names = "venus", "vcodec0", "cx"; 4580 operating-points-v2 = <&venus_opp_table>; 4581 4582 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 4583 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 4584 interconnect-names = "cpu-cfg", "video-mem"; 4585 4586 iommus = <&apps_smmu 0x2180 0x20>; 4587 memory-region = <&video_mem>; 4588 4589 status = "disabled"; 4590 4591 venus_opp_table: opp-table { 4592 compatible = "operating-points-v2"; 4593 4594 opp-133330000 { 4595 opp-hz = /bits/ 64 <133330000>; 4596 required-opps = <&rpmhpd_opp_low_svs>; 4597 }; 4598 4599 opp-240000000 { 4600 opp-hz = /bits/ 64 <240000000>; 4601 required-opps = <&rpmhpd_opp_svs>; 4602 }; 4603 4604 opp-335000000 { 4605 opp-hz = /bits/ 64 <335000000>; 4606 required-opps = <&rpmhpd_opp_svs_l1>; 4607 }; 4608 4609 opp-424000000 { 4610 opp-hz = /bits/ 64 <424000000>; 4611 required-opps = <&rpmhpd_opp_nom>; 4612 }; 4613 4614 opp-460000048 { 4615 opp-hz = /bits/ 64 <460000048>; 4616 required-opps = <&rpmhpd_opp_turbo>; 4617 }; 4618 }; 4619 }; 4620 4621 videocc: clock-controller@aaf0000 { 4622 compatible = "qcom,sc7280-videocc"; 4623 reg = <0 0x0aaf0000 0 0x10000>; 4624 clocks = <&rpmhcc RPMH_CXO_CLK>, 4625 <&rpmhcc RPMH_CXO_CLK_A>; 4626 clock-names = "bi_tcxo", "bi_tcxo_ao"; 4627 #clock-cells = <1>; 4628 #reset-cells = <1>; 4629 #power-domain-cells = <1>; 4630 }; 4631 4632 cci0: cci@ac4a000 { 4633 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci"; 4634 reg = <0 0x0ac4a000 0 0x1000>; 4635 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4636 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4637 4638 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4639 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4640 <&camcc CAM_CC_CPAS_AHB_CLK>, 4641 <&camcc CAM_CC_CCI_0_CLK>, 4642 <&camcc CAM_CC_CCI_0_CLK_SRC>; 4643 clock-names = "camnoc_axi", 4644 "slow_ahb_src", 4645 "cpas_ahb", 4646 "cci", 4647 "cci_src"; 4648 pinctrl-0 = <&cci0_default &cci1_default>; 4649 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 4650 pinctrl-names = "default", "sleep"; 4651 4652 #address-cells = <1>; 4653 #size-cells = <0>; 4654 4655 status = "disabled"; 4656 4657 cci0_i2c0: i2c-bus@0 { 4658 reg = <0>; 4659 clock-frequency = <1000000>; 4660 #address-cells = <1>; 4661 #size-cells = <0>; 4662 }; 4663 4664 cci0_i2c1: i2c-bus@1 { 4665 reg = <1>; 4666 clock-frequency = <1000000>; 4667 #address-cells = <1>; 4668 #size-cells = <0>; 4669 }; 4670 }; 4671 4672 cci1: cci@ac4b000 { 4673 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci"; 4674 reg = <0 0x0ac4b000 0 0x1000>; 4675 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 4676 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4677 4678 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4679 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4680 <&camcc CAM_CC_CPAS_AHB_CLK>, 4681 <&camcc CAM_CC_CCI_1_CLK>, 4682 <&camcc CAM_CC_CCI_1_CLK_SRC>; 4683 clock-names = "camnoc_axi", 4684 "slow_ahb_src", 4685 "cpas_ahb", 4686 "cci", 4687 "cci_src"; 4688 pinctrl-0 = <&cci2_default &cci3_default>; 4689 pinctrl-1 = <&cci2_sleep &cci3_sleep>; 4690 pinctrl-names = "default", "sleep"; 4691 4692 #address-cells = <1>; 4693 #size-cells = <0>; 4694 4695 status = "disabled"; 4696 4697 cci1_i2c0: i2c-bus@0 { 4698 reg = <0>; 4699 clock-frequency = <1000000>; 4700 #address-cells = <1>; 4701 #size-cells = <0>; 4702 }; 4703 4704 cci1_i2c1: i2c-bus@1 { 4705 reg = <1>; 4706 clock-frequency = <1000000>; 4707 #address-cells = <1>; 4708 #size-cells = <0>; 4709 }; 4710 }; 4711 4712 camss: isp@acb3000 { 4713 compatible = "qcom,sc7280-camss"; 4714 4715 reg = <0x0 0x0acb3000 0x0 0x1000>, 4716 <0x0 0x0acba000 0x0 0x1000>, 4717 <0x0 0x0acc1000 0x0 0x1000>, 4718 <0x0 0x0acc8000 0x0 0x1000>, 4719 <0x0 0x0accf000 0x0 0x1000>, 4720 <0x0 0x0ace0000 0x0 0x2000>, 4721 <0x0 0x0ace2000 0x0 0x2000>, 4722 <0x0 0x0ace4000 0x0 0x2000>, 4723 <0x0 0x0ace6000 0x0 0x2000>, 4724 <0x0 0x0ace8000 0x0 0x2000>, 4725 <0x0 0x0acaf000 0x0 0x4000>, 4726 <0x0 0x0acb6000 0x0 0x4000>, 4727 <0x0 0x0acbd000 0x0 0x4000>, 4728 <0x0 0x0acc4000 0x0 0x4000>, 4729 <0x0 0x0accb000 0x0 0x4000>; 4730 reg-names = "csid0", 4731 "csid1", 4732 "csid2", 4733 "csid_lite0", 4734 "csid_lite1", 4735 "csiphy0", 4736 "csiphy1", 4737 "csiphy2", 4738 "csiphy3", 4739 "csiphy4", 4740 "vfe0", 4741 "vfe1", 4742 "vfe2", 4743 "vfe_lite0", 4744 "vfe_lite1"; 4745 4746 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4747 <&camcc CAM_CC_CPAS_AHB_CLK>, 4748 <&camcc CAM_CC_CSIPHY0_CLK>, 4749 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 4750 <&camcc CAM_CC_CSIPHY1_CLK>, 4751 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 4752 <&camcc CAM_CC_CSIPHY2_CLK>, 4753 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 4754 <&camcc CAM_CC_CSIPHY3_CLK>, 4755 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 4756 <&camcc CAM_CC_CSIPHY4_CLK>, 4757 <&camcc CAM_CC_CSI4PHYTIMER_CLK>, 4758 <&gcc GCC_CAMERA_HF_AXI_CLK>, 4759 <&gcc GCC_CAMERA_SF_AXI_CLK>, 4760 <&camcc CAM_CC_ICP_AHB_CLK>, 4761 <&camcc CAM_CC_IFE_0_CLK>, 4762 <&camcc CAM_CC_IFE_0_AXI_CLK>, 4763 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 4764 <&camcc CAM_CC_IFE_0_CSID_CLK>, 4765 <&camcc CAM_CC_IFE_1_CLK>, 4766 <&camcc CAM_CC_IFE_1_AXI_CLK>, 4767 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 4768 <&camcc CAM_CC_IFE_1_CSID_CLK>, 4769 <&camcc CAM_CC_IFE_2_CLK>, 4770 <&camcc CAM_CC_IFE_2_AXI_CLK>, 4771 <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>, 4772 <&camcc CAM_CC_IFE_2_CSID_CLK>, 4773 <&camcc CAM_CC_IFE_LITE_0_CLK>, 4774 <&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>, 4775 <&camcc CAM_CC_IFE_LITE_0_CSID_CLK>, 4776 <&camcc CAM_CC_IFE_LITE_1_CLK>, 4777 <&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>, 4778 <&camcc CAM_CC_IFE_LITE_1_CSID_CLK>; 4779 clock-names = "camnoc_axi", 4780 "cpas_ahb", 4781 "csiphy0", 4782 "csiphy0_timer", 4783 "csiphy1", 4784 "csiphy1_timer", 4785 "csiphy2", 4786 "csiphy2_timer", 4787 "csiphy3", 4788 "csiphy3_timer", 4789 "csiphy4", 4790 "csiphy4_timer", 4791 "gcc_axi_hf", 4792 "gcc_axi_sf", 4793 "icp_ahb", 4794 "vfe0", 4795 "vfe0_axi", 4796 "vfe0_cphy_rx", 4797 "vfe0_csid", 4798 "vfe1", 4799 "vfe1_axi", 4800 "vfe1_cphy_rx", 4801 "vfe1_csid", 4802 "vfe2", 4803 "vfe2_axi", 4804 "vfe2_cphy_rx", 4805 "vfe2_csid", 4806 "vfe_lite0", 4807 "vfe_lite0_cphy_rx", 4808 "vfe_lite0_csid", 4809 "vfe_lite1", 4810 "vfe_lite1_cphy_rx", 4811 "vfe_lite1_csid"; 4812 4813 interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 4814 <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, 4815 <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>, 4816 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 4817 <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, 4818 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 4819 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 4820 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 4821 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 4822 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, 4823 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 4824 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 4825 <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>, 4826 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, 4827 <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>; 4828 interrupt-names = "csid0", 4829 "csid1", 4830 "csid2", 4831 "csid_lite0", 4832 "csid_lite1", 4833 "csiphy0", 4834 "csiphy1", 4835 "csiphy2", 4836 "csiphy3", 4837 "csiphy4", 4838 "vfe0", 4839 "vfe1", 4840 "vfe2", 4841 "vfe_lite0", 4842 "vfe_lite1"; 4843 4844 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4845 &cnoc2 SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 4846 <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS 4847 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4848 interconnect-names = "ahb", 4849 "hf_0"; 4850 4851 iommus = <&apps_smmu 0x800 0x4e0>; 4852 4853 power-domains = <&camcc CAM_CC_IFE_0_GDSC>, 4854 <&camcc CAM_CC_IFE_1_GDSC>, 4855 <&camcc CAM_CC_IFE_2_GDSC>, 4856 <&camcc CAM_CC_TITAN_TOP_GDSC>; 4857 power-domain-names = "ife0", 4858 "ife1", 4859 "ife2", 4860 "top"; 4861 4862 status = "disabled"; 4863 4864 ports { 4865 #address-cells = <1>; 4866 #size-cells = <0>; 4867 4868 port@0 { 4869 reg = <0>; 4870 }; 4871 4872 port@1 { 4873 reg = <1>; 4874 }; 4875 4876 port@2 { 4877 reg = <2>; 4878 }; 4879 4880 port@3 { 4881 reg = <3>; 4882 }; 4883 4884 port@4 { 4885 reg = <4>; 4886 }; 4887 }; 4888 }; 4889 4890 camcc: clock-controller@ad00000 { 4891 compatible = "qcom,sc7280-camcc"; 4892 reg = <0 0x0ad00000 0 0x10000>; 4893 clocks = <&rpmhcc RPMH_CXO_CLK>, 4894 <&rpmhcc RPMH_CXO_CLK_A>, 4895 <&sleep_clk>; 4896 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 4897 #clock-cells = <1>; 4898 #reset-cells = <1>; 4899 #power-domain-cells = <1>; 4900 }; 4901 4902 dispcc: clock-controller@af00000 { 4903 compatible = "qcom,sc7280-dispcc"; 4904 reg = <0 0x0af00000 0 0x20000>; 4905 clocks = <&rpmhcc RPMH_CXO_CLK>, 4906 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 4907 <&mdss_dsi_phy DSI_BYTE_PLL_CLK>, 4908 <&mdss_dsi_phy DSI_PIXEL_PLL_CLK>, 4909 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4910 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4911 <&mdss_edp_phy 0>, 4912 <&mdss_edp_phy 1>; 4913 clock-names = "bi_tcxo", 4914 "gcc_disp_gpll0_clk", 4915 "dsi0_phy_pll_out_byteclk", 4916 "dsi0_phy_pll_out_dsiclk", 4917 "dp_phy_pll_link_clk", 4918 "dp_phy_pll_vco_div_clk", 4919 "edp_phy_pll_link_clk", 4920 "edp_phy_pll_vco_div_clk"; 4921 #clock-cells = <1>; 4922 #reset-cells = <1>; 4923 #power-domain-cells = <1>; 4924 }; 4925 4926 mdss: display-subsystem@ae00000 { 4927 compatible = "qcom,sc7280-mdss"; 4928 reg = <0 0x0ae00000 0 0x1000>; 4929 reg-names = "mdss"; 4930 4931 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 4932 4933 clocks = <&gcc GCC_DISP_AHB_CLK>, 4934 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4935 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4936 clock-names = "iface", 4937 "ahb", 4938 "core"; 4939 4940 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4941 interrupt-controller; 4942 #interrupt-cells = <1>; 4943 4944 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS 4945 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4946 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4947 &cnoc2 SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>; 4948 interconnect-names = "mdp0-mem", 4949 "cpu-cfg"; 4950 4951 iommus = <&apps_smmu 0x900 0x402>; 4952 4953 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 4954 4955 #address-cells = <2>; 4956 #size-cells = <2>; 4957 ranges; 4958 4959 status = "disabled"; 4960 4961 mdss_mdp: display-controller@ae01000 { 4962 compatible = "qcom,sc7280-dpu"; 4963 reg = <0 0x0ae01000 0 0x8f030>, 4964 <0 0x0aeb0000 0 0x3000>; 4965 reg-names = "mdp", "vbif"; 4966 4967 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4968 <&gcc GCC_DISP_SF_AXI_CLK>, 4969 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4970 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 4971 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4972 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4973 clock-names = "bus", 4974 "nrt_bus", 4975 "iface", 4976 "lut", 4977 "core", 4978 "vsync"; 4979 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 4980 <&dispcc DISP_CC_MDSS_AHB_CLK>; 4981 assigned-clock-rates = <19200000>, 4982 <19200000>; 4983 operating-points-v2 = <&mdp_opp_table>; 4984 power-domains = <&rpmhpd SC7280_CX>; 4985 4986 interrupt-parent = <&mdss>; 4987 interrupts = <0>; 4988 4989 ports { 4990 #address-cells = <1>; 4991 #size-cells = <0>; 4992 4993 port@0 { 4994 reg = <0>; 4995 dpu_intf1_out: endpoint { 4996 remote-endpoint = <&mdss_dsi0_in>; 4997 }; 4998 }; 4999 5000 port@1 { 5001 reg = <1>; 5002 dpu_intf5_out: endpoint { 5003 remote-endpoint = <&edp_in>; 5004 }; 5005 }; 5006 5007 port@2 { 5008 reg = <2>; 5009 dpu_intf0_out: endpoint { 5010 remote-endpoint = <&dp_in>; 5011 }; 5012 }; 5013 }; 5014 5015 mdp_opp_table: opp-table { 5016 compatible = "operating-points-v2"; 5017 5018 opp-200000000 { 5019 opp-hz = /bits/ 64 <200000000>; 5020 required-opps = <&rpmhpd_opp_low_svs>; 5021 }; 5022 5023 opp-300000000 { 5024 opp-hz = /bits/ 64 <300000000>; 5025 required-opps = <&rpmhpd_opp_svs>; 5026 }; 5027 5028 opp-380000000 { 5029 opp-hz = /bits/ 64 <380000000>; 5030 required-opps = <&rpmhpd_opp_svs_l1>; 5031 }; 5032 5033 opp-506666667 { 5034 opp-hz = /bits/ 64 <506666667>; 5035 required-opps = <&rpmhpd_opp_nom>; 5036 }; 5037 5038 opp-608000000 { 5039 opp-hz = /bits/ 64 <608000000>; 5040 required-opps = <&rpmhpd_opp_turbo>; 5041 }; 5042 }; 5043 }; 5044 5045 mdss_dsi: dsi@ae94000 { 5046 compatible = "qcom,sc7280-dsi-ctrl", 5047 "qcom,mdss-dsi-ctrl"; 5048 reg = <0 0x0ae94000 0 0x400>; 5049 reg-names = "dsi_ctrl"; 5050 5051 interrupt-parent = <&mdss>; 5052 interrupts = <4>; 5053 5054 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 5055 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 5056 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 5057 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 5058 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5059 <&gcc GCC_DISP_HF_AXI_CLK>; 5060 clock-names = "byte", 5061 "byte_intf", 5062 "pixel", 5063 "core", 5064 "iface", 5065 "bus"; 5066 5067 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 5068 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 5069 assigned-clock-parents = <&mdss_dsi_phy DSI_BYTE_PLL_CLK>, 5070 <&mdss_dsi_phy DSI_PIXEL_PLL_CLK>; 5071 5072 operating-points-v2 = <&dsi_opp_table>; 5073 power-domains = <&rpmhpd SC7280_CX>; 5074 5075 phys = <&mdss_dsi_phy>; 5076 5077 #address-cells = <1>; 5078 #size-cells = <0>; 5079 5080 status = "disabled"; 5081 5082 ports { 5083 #address-cells = <1>; 5084 #size-cells = <0>; 5085 5086 port@0 { 5087 reg = <0>; 5088 mdss_dsi0_in: endpoint { 5089 remote-endpoint = <&dpu_intf1_out>; 5090 }; 5091 }; 5092 5093 port@1 { 5094 reg = <1>; 5095 mdss_dsi0_out: endpoint { 5096 }; 5097 }; 5098 }; 5099 5100 dsi_opp_table: opp-table { 5101 compatible = "operating-points-v2"; 5102 5103 opp-187500000 { 5104 opp-hz = /bits/ 64 <187500000>; 5105 required-opps = <&rpmhpd_opp_low_svs>; 5106 }; 5107 5108 opp-300000000 { 5109 opp-hz = /bits/ 64 <300000000>; 5110 required-opps = <&rpmhpd_opp_svs>; 5111 }; 5112 5113 opp-358000000 { 5114 opp-hz = /bits/ 64 <358000000>; 5115 required-opps = <&rpmhpd_opp_svs_l1>; 5116 }; 5117 }; 5118 }; 5119 5120 mdss_dsi_phy: phy@ae94400 { 5121 compatible = "qcom,sc7280-dsi-phy-7nm"; 5122 reg = <0 0x0ae94400 0 0x200>, 5123 <0 0x0ae94600 0 0x280>, 5124 <0 0x0ae94900 0 0x280>; 5125 reg-names = "dsi_phy", 5126 "dsi_phy_lane", 5127 "dsi_pll"; 5128 5129 #clock-cells = <1>; 5130 #phy-cells = <0>; 5131 5132 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5133 <&rpmhcc RPMH_CXO_CLK>; 5134 clock-names = "iface", "ref"; 5135 5136 status = "disabled"; 5137 }; 5138 5139 mdss_edp: edp@aea0000 { 5140 compatible = "qcom,sc7280-edp"; 5141 pinctrl-names = "default"; 5142 pinctrl-0 = <&edp_hot_plug_det>; 5143 5144 reg = <0 0x0aea0000 0 0x200>, 5145 <0 0x0aea0200 0 0x200>, 5146 <0 0x0aea0400 0 0xc00>, 5147 <0 0x0aea1000 0 0x400>, 5148 <0 0x0aea1400 0 0x400>; 5149 5150 interrupt-parent = <&mdss>; 5151 interrupts = <14>; 5152 5153 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5154 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 5155 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 5156 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 5157 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 5158 clock-names = "core_iface", 5159 "core_aux", 5160 "ctrl_link", 5161 "ctrl_link_iface", 5162 "stream_pixel"; 5163 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 5164 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 5165 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 5166 5167 phys = <&mdss_edp_phy>; 5168 phy-names = "dp"; 5169 5170 operating-points-v2 = <&edp_opp_table>; 5171 power-domains = <&rpmhpd SC7280_CX>; 5172 5173 status = "disabled"; 5174 5175 ports { 5176 #address-cells = <1>; 5177 #size-cells = <0>; 5178 5179 port@0 { 5180 reg = <0>; 5181 edp_in: endpoint { 5182 remote-endpoint = <&dpu_intf5_out>; 5183 }; 5184 }; 5185 5186 port@1 { 5187 reg = <1>; 5188 mdss_edp_out: endpoint { }; 5189 }; 5190 }; 5191 5192 edp_opp_table: opp-table { 5193 compatible = "operating-points-v2"; 5194 5195 opp-160000000 { 5196 opp-hz = /bits/ 64 <160000000>; 5197 required-opps = <&rpmhpd_opp_low_svs>; 5198 }; 5199 5200 opp-270000000 { 5201 opp-hz = /bits/ 64 <270000000>; 5202 required-opps = <&rpmhpd_opp_svs>; 5203 }; 5204 5205 opp-540000000 { 5206 opp-hz = /bits/ 64 <540000000>; 5207 required-opps = <&rpmhpd_opp_nom>; 5208 }; 5209 5210 opp-810000000 { 5211 opp-hz = /bits/ 64 <810000000>; 5212 required-opps = <&rpmhpd_opp_nom>; 5213 }; 5214 }; 5215 }; 5216 5217 mdss_edp_phy: phy@aec2a00 { 5218 compatible = "qcom,sc7280-edp-phy"; 5219 5220 reg = <0 0x0aec2a00 0 0x19c>, 5221 <0 0x0aec2200 0 0xa0>, 5222 <0 0x0aec2600 0 0xa0>, 5223 <0 0x0aec2000 0 0x1c0>; 5224 5225 clocks = <&rpmhcc RPMH_CXO_CLK>, 5226 <&gcc GCC_EDP_CLKREF_EN>; 5227 clock-names = "aux", 5228 "cfg_ahb"; 5229 5230 #clock-cells = <1>; 5231 #phy-cells = <0>; 5232 5233 status = "disabled"; 5234 }; 5235 5236 mdss_dp: displayport-controller@ae90000 { 5237 compatible = "qcom,sc7280-dp"; 5238 5239 reg = <0 0x0ae90000 0 0x200>, 5240 <0 0x0ae90200 0 0x200>, 5241 <0 0x0ae90400 0 0xc00>, 5242 <0 0x0ae91000 0 0x400>, 5243 <0 0x0ae91400 0 0x400>; 5244 5245 interrupt-parent = <&mdss>; 5246 interrupts = <12>; 5247 5248 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5249 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 5250 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 5251 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 5252 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 5253 clock-names = "core_iface", 5254 "core_aux", 5255 "ctrl_link", 5256 "ctrl_link_iface", 5257 "stream_pixel"; 5258 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 5259 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 5260 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5261 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5262 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 5263 phy-names = "dp"; 5264 5265 operating-points-v2 = <&dp_opp_table>; 5266 power-domains = <&rpmhpd SC7280_CX>; 5267 5268 #sound-dai-cells = <0>; 5269 5270 status = "disabled"; 5271 5272 ports { 5273 #address-cells = <1>; 5274 #size-cells = <0>; 5275 5276 port@0 { 5277 reg = <0>; 5278 dp_in: endpoint { 5279 remote-endpoint = <&dpu_intf0_out>; 5280 }; 5281 }; 5282 5283 port@1 { 5284 reg = <1>; 5285 mdss_dp_out: endpoint { 5286 remote-endpoint = <&usb_dp_qmpphy_dp_in>; 5287 }; 5288 }; 5289 }; 5290 5291 dp_opp_table: opp-table { 5292 compatible = "operating-points-v2"; 5293 5294 opp-160000000 { 5295 opp-hz = /bits/ 64 <160000000>; 5296 required-opps = <&rpmhpd_opp_low_svs>; 5297 }; 5298 5299 opp-270000000 { 5300 opp-hz = /bits/ 64 <270000000>; 5301 required-opps = <&rpmhpd_opp_svs>; 5302 }; 5303 5304 opp-540000000 { 5305 opp-hz = /bits/ 64 <540000000>; 5306 required-opps = <&rpmhpd_opp_svs_l1>; 5307 }; 5308 5309 opp-810000000 { 5310 opp-hz = /bits/ 64 <810000000>; 5311 required-opps = <&rpmhpd_opp_nom>; 5312 }; 5313 }; 5314 }; 5315 }; 5316 5317 pdc: interrupt-controller@b220000 { 5318 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 5319 reg = <0 0x0b220000 0 0x30000>; 5320 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 5321 <55 306 4>, <59 312 3>, <62 374 2>, 5322 <64 434 2>, <66 438 3>, <69 86 1>, 5323 <70 520 54>, <124 609 31>, <155 63 1>, 5324 <156 716 12>; 5325 #interrupt-cells = <2>; 5326 interrupt-parent = <&intc>; 5327 interrupt-controller; 5328 }; 5329 5330 pdc_reset: reset-controller@b5e0000 { 5331 compatible = "qcom,sc7280-pdc-global"; 5332 reg = <0 0x0b5e0000 0 0x20000>; 5333 #reset-cells = <1>; 5334 status = "reserved"; /* Owned by firmware */ 5335 }; 5336 5337 tsens0: thermal-sensor@c263000 { 5338 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 5339 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 5340 <0 0x0c222000 0 0x1ff>; /* SROT */ 5341 #qcom,sensors = <15>; 5342 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 5343 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 5344 interrupt-names = "uplow","critical"; 5345 #thermal-sensor-cells = <1>; 5346 }; 5347 5348 tsens1: thermal-sensor@c265000 { 5349 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 5350 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 5351 <0 0x0c223000 0 0x1ff>; /* SROT */ 5352 #qcom,sensors = <12>; 5353 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 5354 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 5355 interrupt-names = "uplow","critical"; 5356 #thermal-sensor-cells = <1>; 5357 }; 5358 5359 aoss_reset: reset-controller@c2a0000 { 5360 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 5361 reg = <0 0x0c2a0000 0 0x31000>; 5362 #reset-cells = <1>; 5363 }; 5364 5365 aoss_qmp: power-management@c300000 { 5366 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 5367 reg = <0 0x0c300000 0 0x400>; 5368 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 5369 IPCC_MPROC_SIGNAL_GLINK_QMP 5370 IRQ_TYPE_EDGE_RISING>; 5371 mboxes = <&ipcc IPCC_CLIENT_AOP 5372 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5373 5374 #clock-cells = <0>; 5375 }; 5376 5377 sram@c3f0000 { 5378 compatible = "qcom,rpmh-stats"; 5379 reg = <0 0x0c3f0000 0 0x400>; 5380 }; 5381 5382 spmi_bus: spmi@c440000 { 5383 compatible = "qcom,spmi-pmic-arb"; 5384 reg = <0 0x0c440000 0 0x1100>, 5385 <0 0x0c600000 0 0x2000000>, 5386 <0 0x0e600000 0 0x100000>, 5387 <0 0x0e700000 0 0xa0000>, 5388 <0 0x0c40a000 0 0x26000>; 5389 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 5390 interrupt-names = "periph_irq"; 5391 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5392 qcom,ee = <0>; 5393 qcom,channel = <0>; 5394 #address-cells = <2>; 5395 #size-cells = <0>; 5396 interrupt-controller; 5397 #interrupt-cells = <4>; 5398 }; 5399 5400 tlmm: pinctrl@f100000 { 5401 compatible = "qcom,sc7280-pinctrl"; 5402 reg = <0 0x0f100000 0 0x300000>; 5403 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 5404 gpio-controller; 5405 #gpio-cells = <2>; 5406 interrupt-controller; 5407 #interrupt-cells = <2>; 5408 gpio-ranges = <&tlmm 0 0 175>; 5409 wakeup-parent = <&pdc>; 5410 5411 cci0_default: cci0-default-state { 5412 pins = "gpio69", "gpio70"; 5413 function = "cci_i2c"; 5414 drive-strength = <2>; 5415 bias-pull-up; 5416 }; 5417 5418 cci0_sleep: cci0-sleep-state { 5419 pins = "gpio69", "gpio70"; 5420 function = "cci_i2c"; 5421 drive-strength = <2>; 5422 bias-pull-down; 5423 }; 5424 5425 cci1_default: cci1-default-state { 5426 pins = "gpio71", "gpio72"; 5427 function = "cci_i2c"; 5428 drive-strength = <2>; 5429 bias-pull-up; 5430 }; 5431 5432 cci1_sleep: cci1-sleep-state { 5433 pins = "gpio71", "gpio72"; 5434 function = "cci_i2c"; 5435 drive-strength = <2>; 5436 bias-pull-down; 5437 }; 5438 5439 cci2_default: cci2-default-state { 5440 pins = "gpio73", "gpio74"; 5441 function = "cci_i2c"; 5442 drive-strength = <2>; 5443 bias-pull-up; 5444 }; 5445 5446 cci2_sleep: cci2-sleep-state { 5447 pins = "gpio73", "gpio74"; 5448 function = "cci_i2c"; 5449 drive-strength = <2>; 5450 bias-pull-down; 5451 }; 5452 5453 cci3_default: cci3-default-state { 5454 pins = "gpio75", "gpio76"; 5455 function = "cci_i2c"; 5456 drive-strength = <2>; 5457 bias-pull-up; 5458 }; 5459 5460 cci3_sleep: cci3-sleep-state { 5461 pins = "gpio75", "gpio76"; 5462 function = "cci_i2c"; 5463 drive-strength = <2>; 5464 bias-pull-down; 5465 }; 5466 5467 dp_hot_plug_det: dp-hot-plug-det-state { 5468 pins = "gpio47"; 5469 function = "dp_hot"; 5470 }; 5471 5472 edp_hot_plug_det: edp-hot-plug-det-state { 5473 pins = "gpio60"; 5474 function = "edp_hot"; 5475 }; 5476 5477 mi2s0_data0: mi2s0-data0-state { 5478 pins = "gpio98"; 5479 function = "mi2s0_data0"; 5480 }; 5481 5482 mi2s0_data1: mi2s0-data1-state { 5483 pins = "gpio99"; 5484 function = "mi2s0_data1"; 5485 }; 5486 5487 mi2s0_mclk: mi2s0-mclk-state { 5488 pins = "gpio96"; 5489 function = "pri_mi2s"; 5490 }; 5491 5492 mi2s0_sclk: mi2s0-sclk-state { 5493 pins = "gpio97"; 5494 function = "mi2s0_sck"; 5495 }; 5496 5497 mi2s0_ws: mi2s0-ws-state { 5498 pins = "gpio100"; 5499 function = "mi2s0_ws"; 5500 }; 5501 5502 mi2s1_data0: mi2s1-data0-state { 5503 pins = "gpio107"; 5504 function = "mi2s1_data0"; 5505 }; 5506 5507 mi2s1_sclk: mi2s1-sclk-state { 5508 pins = "gpio106"; 5509 function = "mi2s1_sck"; 5510 }; 5511 5512 mi2s1_ws: mi2s1-ws-state { 5513 pins = "gpio108"; 5514 function = "mi2s1_ws"; 5515 }; 5516 5517 pcie0_clkreq_n: pcie0-clkreq-n-state { 5518 pins = "gpio88"; 5519 function = "pcie0_clkreqn"; 5520 }; 5521 5522 pcie1_clkreq_n: pcie1-clkreq-n-state { 5523 pins = "gpio79"; 5524 function = "pcie1_clkreqn"; 5525 }; 5526 5527 qspi_clk: qspi-clk-state { 5528 pins = "gpio14"; 5529 function = "qspi_clk"; 5530 }; 5531 5532 qspi_cs0: qspi-cs0-state { 5533 pins = "gpio15"; 5534 function = "qspi_cs"; 5535 }; 5536 5537 qspi_cs1: qspi-cs1-state { 5538 pins = "gpio19"; 5539 function = "qspi_cs"; 5540 }; 5541 5542 qspi_data0: qspi-data0-state { 5543 pins = "gpio12"; 5544 function = "qspi_data"; 5545 }; 5546 5547 qspi_data1: qspi-data1-state { 5548 pins = "gpio13"; 5549 function = "qspi_data"; 5550 }; 5551 5552 qspi_data23: qspi-data23-state { 5553 pins = "gpio16", "gpio17"; 5554 function = "qspi_data"; 5555 }; 5556 5557 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 5558 pins = "gpio0", "gpio1"; 5559 function = "qup00"; 5560 }; 5561 5562 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 5563 pins = "gpio4", "gpio5"; 5564 function = "qup01"; 5565 }; 5566 5567 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 5568 pins = "gpio8", "gpio9"; 5569 function = "qup02"; 5570 }; 5571 5572 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 5573 pins = "gpio12", "gpio13"; 5574 function = "qup03"; 5575 }; 5576 5577 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 5578 pins = "gpio16", "gpio17"; 5579 function = "qup04"; 5580 }; 5581 5582 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 5583 pins = "gpio20", "gpio21"; 5584 function = "qup05"; 5585 }; 5586 5587 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 5588 pins = "gpio24", "gpio25"; 5589 function = "qup06"; 5590 }; 5591 5592 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 5593 pins = "gpio28", "gpio29"; 5594 function = "qup07"; 5595 }; 5596 5597 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 5598 pins = "gpio32", "gpio33"; 5599 function = "qup10"; 5600 }; 5601 5602 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 5603 pins = "gpio36", "gpio37"; 5604 function = "qup11"; 5605 }; 5606 5607 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 5608 pins = "gpio40", "gpio41"; 5609 function = "qup12"; 5610 }; 5611 5612 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 5613 pins = "gpio44", "gpio45"; 5614 function = "qup13"; 5615 }; 5616 5617 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 5618 pins = "gpio48", "gpio49"; 5619 function = "qup14"; 5620 }; 5621 5622 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 5623 pins = "gpio52", "gpio53"; 5624 function = "qup15"; 5625 }; 5626 5627 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 5628 pins = "gpio56", "gpio57"; 5629 function = "qup16"; 5630 }; 5631 5632 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 5633 pins = "gpio60", "gpio61"; 5634 function = "qup17"; 5635 }; 5636 5637 qup_spi0_data_clk: qup-spi0-data-clk-state { 5638 pins = "gpio0", "gpio1", "gpio2"; 5639 function = "qup00"; 5640 }; 5641 5642 qup_spi0_cs: qup-spi0-cs-state { 5643 pins = "gpio3"; 5644 function = "qup00"; 5645 }; 5646 5647 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 5648 pins = "gpio3"; 5649 function = "gpio"; 5650 }; 5651 5652 qup_spi1_data_clk: qup-spi1-data-clk-state { 5653 pins = "gpio4", "gpio5", "gpio6"; 5654 function = "qup01"; 5655 }; 5656 5657 qup_spi1_cs: qup-spi1-cs-state { 5658 pins = "gpio7"; 5659 function = "qup01"; 5660 }; 5661 5662 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 5663 pins = "gpio7"; 5664 function = "gpio"; 5665 }; 5666 5667 qup_spi2_data_clk: qup-spi2-data-clk-state { 5668 pins = "gpio8", "gpio9", "gpio10"; 5669 function = "qup02"; 5670 }; 5671 5672 qup_spi2_cs: qup-spi2-cs-state { 5673 pins = "gpio11"; 5674 function = "qup02"; 5675 }; 5676 5677 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 5678 pins = "gpio11"; 5679 function = "gpio"; 5680 }; 5681 5682 qup_spi3_data_clk: qup-spi3-data-clk-state { 5683 pins = "gpio12", "gpio13", "gpio14"; 5684 function = "qup03"; 5685 }; 5686 5687 qup_spi3_cs: qup-spi3-cs-state { 5688 pins = "gpio15"; 5689 function = "qup03"; 5690 }; 5691 5692 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 5693 pins = "gpio15"; 5694 function = "gpio"; 5695 }; 5696 5697 qup_spi4_data_clk: qup-spi4-data-clk-state { 5698 pins = "gpio16", "gpio17", "gpio18"; 5699 function = "qup04"; 5700 }; 5701 5702 qup_spi4_cs: qup-spi4-cs-state { 5703 pins = "gpio19"; 5704 function = "qup04"; 5705 }; 5706 5707 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 5708 pins = "gpio19"; 5709 function = "gpio"; 5710 }; 5711 5712 qup_spi5_data_clk: qup-spi5-data-clk-state { 5713 pins = "gpio20", "gpio21", "gpio22"; 5714 function = "qup05"; 5715 }; 5716 5717 qup_spi5_cs: qup-spi5-cs-state { 5718 pins = "gpio23"; 5719 function = "qup05"; 5720 }; 5721 5722 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 5723 pins = "gpio23"; 5724 function = "gpio"; 5725 }; 5726 5727 qup_spi6_data_clk: qup-spi6-data-clk-state { 5728 pins = "gpio24", "gpio25", "gpio26"; 5729 function = "qup06"; 5730 }; 5731 5732 qup_spi6_cs: qup-spi6-cs-state { 5733 pins = "gpio27"; 5734 function = "qup06"; 5735 }; 5736 5737 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 5738 pins = "gpio27"; 5739 function = "gpio"; 5740 }; 5741 5742 qup_spi7_data_clk: qup-spi7-data-clk-state { 5743 pins = "gpio28", "gpio29", "gpio30"; 5744 function = "qup07"; 5745 }; 5746 5747 qup_spi7_cs: qup-spi7-cs-state { 5748 pins = "gpio31"; 5749 function = "qup07"; 5750 }; 5751 5752 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 5753 pins = "gpio31"; 5754 function = "gpio"; 5755 }; 5756 5757 qup_spi8_data_clk: qup-spi8-data-clk-state { 5758 pins = "gpio32", "gpio33", "gpio34"; 5759 function = "qup10"; 5760 }; 5761 5762 qup_spi8_cs: qup-spi8-cs-state { 5763 pins = "gpio35"; 5764 function = "qup10"; 5765 }; 5766 5767 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 5768 pins = "gpio35"; 5769 function = "gpio"; 5770 }; 5771 5772 qup_spi9_data_clk: qup-spi9-data-clk-state { 5773 pins = "gpio36", "gpio37", "gpio38"; 5774 function = "qup11"; 5775 }; 5776 5777 qup_spi9_cs: qup-spi9-cs-state { 5778 pins = "gpio39"; 5779 function = "qup11"; 5780 }; 5781 5782 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 5783 pins = "gpio39"; 5784 function = "gpio"; 5785 }; 5786 5787 qup_spi10_data_clk: qup-spi10-data-clk-state { 5788 pins = "gpio40", "gpio41", "gpio42"; 5789 function = "qup12"; 5790 }; 5791 5792 qup_spi10_cs: qup-spi10-cs-state { 5793 pins = "gpio43"; 5794 function = "qup12"; 5795 }; 5796 5797 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 5798 pins = "gpio43"; 5799 function = "gpio"; 5800 }; 5801 5802 qup_spi11_data_clk: qup-spi11-data-clk-state { 5803 pins = "gpio44", "gpio45", "gpio46"; 5804 function = "qup13"; 5805 }; 5806 5807 qup_spi11_cs: qup-spi11-cs-state { 5808 pins = "gpio47"; 5809 function = "qup13"; 5810 }; 5811 5812 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 5813 pins = "gpio47"; 5814 function = "gpio"; 5815 }; 5816 5817 qup_spi12_data_clk: qup-spi12-data-clk-state { 5818 pins = "gpio48", "gpio49", "gpio50"; 5819 function = "qup14"; 5820 }; 5821 5822 qup_spi12_cs: qup-spi12-cs-state { 5823 pins = "gpio51"; 5824 function = "qup14"; 5825 }; 5826 5827 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 5828 pins = "gpio51"; 5829 function = "gpio"; 5830 }; 5831 5832 qup_spi13_data_clk: qup-spi13-data-clk-state { 5833 pins = "gpio52", "gpio53", "gpio54"; 5834 function = "qup15"; 5835 }; 5836 5837 qup_spi13_cs: qup-spi13-cs-state { 5838 pins = "gpio55"; 5839 function = "qup15"; 5840 }; 5841 5842 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 5843 pins = "gpio55"; 5844 function = "gpio"; 5845 }; 5846 5847 qup_spi14_data_clk: qup-spi14-data-clk-state { 5848 pins = "gpio56", "gpio57", "gpio58"; 5849 function = "qup16"; 5850 }; 5851 5852 qup_spi14_cs: qup-spi14-cs-state { 5853 pins = "gpio59"; 5854 function = "qup16"; 5855 }; 5856 5857 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 5858 pins = "gpio59"; 5859 function = "gpio"; 5860 }; 5861 5862 qup_spi15_data_clk: qup-spi15-data-clk-state { 5863 pins = "gpio60", "gpio61", "gpio62"; 5864 function = "qup17"; 5865 }; 5866 5867 qup_spi15_cs: qup-spi15-cs-state { 5868 pins = "gpio63"; 5869 function = "qup17"; 5870 }; 5871 5872 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 5873 pins = "gpio63"; 5874 function = "gpio"; 5875 }; 5876 5877 qup_uart0_cts: qup-uart0-cts-state { 5878 pins = "gpio0"; 5879 function = "qup00"; 5880 }; 5881 5882 qup_uart0_rts: qup-uart0-rts-state { 5883 pins = "gpio1"; 5884 function = "qup00"; 5885 }; 5886 5887 qup_uart0_tx: qup-uart0-tx-state { 5888 pins = "gpio2"; 5889 function = "qup00"; 5890 }; 5891 5892 qup_uart0_rx: qup-uart0-rx-state { 5893 pins = "gpio3"; 5894 function = "qup00"; 5895 }; 5896 5897 qup_uart1_cts: qup-uart1-cts-state { 5898 pins = "gpio4"; 5899 function = "qup01"; 5900 }; 5901 5902 qup_uart1_rts: qup-uart1-rts-state { 5903 pins = "gpio5"; 5904 function = "qup01"; 5905 }; 5906 5907 qup_uart1_tx: qup-uart1-tx-state { 5908 pins = "gpio6"; 5909 function = "qup01"; 5910 }; 5911 5912 qup_uart1_rx: qup-uart1-rx-state { 5913 pins = "gpio7"; 5914 function = "qup01"; 5915 }; 5916 5917 qup_uart2_cts: qup-uart2-cts-state { 5918 pins = "gpio8"; 5919 function = "qup02"; 5920 }; 5921 5922 qup_uart2_rts: qup-uart2-rts-state { 5923 pins = "gpio9"; 5924 function = "qup02"; 5925 }; 5926 5927 qup_uart2_tx: qup-uart2-tx-state { 5928 pins = "gpio10"; 5929 function = "qup02"; 5930 }; 5931 5932 qup_uart2_rx: qup-uart2-rx-state { 5933 pins = "gpio11"; 5934 function = "qup02"; 5935 }; 5936 5937 qup_uart3_cts: qup-uart3-cts-state { 5938 pins = "gpio12"; 5939 function = "qup03"; 5940 }; 5941 5942 qup_uart3_rts: qup-uart3-rts-state { 5943 pins = "gpio13"; 5944 function = "qup03"; 5945 }; 5946 5947 qup_uart3_tx: qup-uart3-tx-state { 5948 pins = "gpio14"; 5949 function = "qup03"; 5950 }; 5951 5952 qup_uart3_rx: qup-uart3-rx-state { 5953 pins = "gpio15"; 5954 function = "qup03"; 5955 }; 5956 5957 qup_uart4_cts: qup-uart4-cts-state { 5958 pins = "gpio16"; 5959 function = "qup04"; 5960 }; 5961 5962 qup_uart4_rts: qup-uart4-rts-state { 5963 pins = "gpio17"; 5964 function = "qup04"; 5965 }; 5966 5967 qup_uart4_tx: qup-uart4-tx-state { 5968 pins = "gpio18"; 5969 function = "qup04"; 5970 }; 5971 5972 qup_uart4_rx: qup-uart4-rx-state { 5973 pins = "gpio19"; 5974 function = "qup04"; 5975 }; 5976 5977 qup_uart5_tx: qup-uart5-tx-state { 5978 pins = "gpio22"; 5979 function = "qup05"; 5980 }; 5981 5982 qup_uart5_rx: qup-uart5-rx-state { 5983 pins = "gpio23"; 5984 function = "qup05"; 5985 }; 5986 5987 qup_uart6_cts: qup-uart6-cts-state { 5988 pins = "gpio24"; 5989 function = "qup06"; 5990 }; 5991 5992 qup_uart6_rts: qup-uart6-rts-state { 5993 pins = "gpio25"; 5994 function = "qup06"; 5995 }; 5996 5997 qup_uart6_tx: qup-uart6-tx-state { 5998 pins = "gpio26"; 5999 function = "qup06"; 6000 }; 6001 6002 qup_uart6_rx: qup-uart6-rx-state { 6003 pins = "gpio27"; 6004 function = "qup06"; 6005 }; 6006 6007 qup_uart7_cts: qup-uart7-cts-state { 6008 pins = "gpio28"; 6009 function = "qup07"; 6010 }; 6011 6012 qup_uart7_rts: qup-uart7-rts-state { 6013 pins = "gpio29"; 6014 function = "qup07"; 6015 }; 6016 6017 qup_uart7_tx: qup-uart7-tx-state { 6018 pins = "gpio30"; 6019 function = "qup07"; 6020 }; 6021 6022 qup_uart7_rx: qup-uart7-rx-state { 6023 pins = "gpio31"; 6024 function = "qup07"; 6025 }; 6026 6027 qup_uart8_cts: qup-uart8-cts-state { 6028 pins = "gpio32"; 6029 function = "qup10"; 6030 }; 6031 6032 qup_uart8_rts: qup-uart8-rts-state { 6033 pins = "gpio33"; 6034 function = "qup10"; 6035 }; 6036 6037 qup_uart8_tx: qup-uart8-tx-state { 6038 pins = "gpio34"; 6039 function = "qup10"; 6040 }; 6041 6042 qup_uart8_rx: qup-uart8-rx-state { 6043 pins = "gpio35"; 6044 function = "qup10"; 6045 }; 6046 6047 qup_uart9_cts: qup-uart9-cts-state { 6048 pins = "gpio36"; 6049 function = "qup11"; 6050 }; 6051 6052 qup_uart9_rts: qup-uart9-rts-state { 6053 pins = "gpio37"; 6054 function = "qup11"; 6055 }; 6056 6057 qup_uart9_tx: qup-uart9-tx-state { 6058 pins = "gpio38"; 6059 function = "qup11"; 6060 }; 6061 6062 qup_uart9_rx: qup-uart9-rx-state { 6063 pins = "gpio39"; 6064 function = "qup11"; 6065 }; 6066 6067 qup_uart10_cts: qup-uart10-cts-state { 6068 pins = "gpio40"; 6069 function = "qup12"; 6070 }; 6071 6072 qup_uart10_rts: qup-uart10-rts-state { 6073 pins = "gpio41"; 6074 function = "qup12"; 6075 }; 6076 6077 qup_uart10_tx: qup-uart10-tx-state { 6078 pins = "gpio42"; 6079 function = "qup12"; 6080 }; 6081 6082 qup_uart10_rx: qup-uart10-rx-state { 6083 pins = "gpio43"; 6084 function = "qup12"; 6085 }; 6086 6087 qup_uart11_cts: qup-uart11-cts-state { 6088 pins = "gpio44"; 6089 function = "qup13"; 6090 }; 6091 6092 qup_uart11_rts: qup-uart11-rts-state { 6093 pins = "gpio45"; 6094 function = "qup13"; 6095 }; 6096 6097 qup_uart11_tx: qup-uart11-tx-state { 6098 pins = "gpio46"; 6099 function = "qup13"; 6100 }; 6101 6102 qup_uart11_rx: qup-uart11-rx-state { 6103 pins = "gpio47"; 6104 function = "qup13"; 6105 }; 6106 6107 qup_uart12_cts: qup-uart12-cts-state { 6108 pins = "gpio48"; 6109 function = "qup14"; 6110 }; 6111 6112 qup_uart12_rts: qup-uart12-rts-state { 6113 pins = "gpio49"; 6114 function = "qup14"; 6115 }; 6116 6117 qup_uart12_tx: qup-uart12-tx-state { 6118 pins = "gpio50"; 6119 function = "qup14"; 6120 }; 6121 6122 qup_uart12_rx: qup-uart12-rx-state { 6123 pins = "gpio51"; 6124 function = "qup14"; 6125 }; 6126 6127 qup_uart13_cts: qup-uart13-cts-state { 6128 pins = "gpio52"; 6129 function = "qup15"; 6130 }; 6131 6132 qup_uart13_rts: qup-uart13-rts-state { 6133 pins = "gpio53"; 6134 function = "qup15"; 6135 }; 6136 6137 qup_uart13_tx: qup-uart13-tx-state { 6138 pins = "gpio54"; 6139 function = "qup15"; 6140 }; 6141 6142 qup_uart13_rx: qup-uart13-rx-state { 6143 pins = "gpio55"; 6144 function = "qup15"; 6145 }; 6146 6147 qup_uart14_cts: qup-uart14-cts-state { 6148 pins = "gpio56"; 6149 function = "qup16"; 6150 }; 6151 6152 qup_uart14_rts: qup-uart14-rts-state { 6153 pins = "gpio57"; 6154 function = "qup16"; 6155 }; 6156 6157 qup_uart14_tx: qup-uart14-tx-state { 6158 pins = "gpio58"; 6159 function = "qup16"; 6160 }; 6161 6162 qup_uart14_rx: qup-uart14-rx-state { 6163 pins = "gpio59"; 6164 function = "qup16"; 6165 }; 6166 6167 qup_uart15_cts: qup-uart15-cts-state { 6168 pins = "gpio60"; 6169 function = "qup17"; 6170 }; 6171 6172 qup_uart15_rts: qup-uart15-rts-state { 6173 pins = "gpio61"; 6174 function = "qup17"; 6175 }; 6176 6177 qup_uart15_tx: qup-uart15-tx-state { 6178 pins = "gpio62"; 6179 function = "qup17"; 6180 }; 6181 6182 qup_uart15_rx: qup-uart15-rx-state { 6183 pins = "gpio63"; 6184 function = "qup17"; 6185 }; 6186 6187 sdc1_clk: sdc1-clk-state { 6188 pins = "sdc1_clk"; 6189 }; 6190 6191 sdc1_cmd: sdc1-cmd-state { 6192 pins = "sdc1_cmd"; 6193 }; 6194 6195 sdc1_data: sdc1-data-state { 6196 pins = "sdc1_data"; 6197 }; 6198 6199 sdc1_rclk: sdc1-rclk-state { 6200 pins = "sdc1_rclk"; 6201 }; 6202 6203 sdc1_clk_sleep: sdc1-clk-sleep-state { 6204 pins = "sdc1_clk"; 6205 drive-strength = <2>; 6206 bias-bus-hold; 6207 }; 6208 6209 sdc1_cmd_sleep: sdc1-cmd-sleep-state { 6210 pins = "sdc1_cmd"; 6211 drive-strength = <2>; 6212 bias-bus-hold; 6213 }; 6214 6215 sdc1_data_sleep: sdc1-data-sleep-state { 6216 pins = "sdc1_data"; 6217 drive-strength = <2>; 6218 bias-bus-hold; 6219 }; 6220 6221 sdc1_rclk_sleep: sdc1-rclk-sleep-state { 6222 pins = "sdc1_rclk"; 6223 drive-strength = <2>; 6224 bias-bus-hold; 6225 }; 6226 6227 sdc2_clk: sdc2-clk-state { 6228 pins = "sdc2_clk"; 6229 }; 6230 6231 sdc2_cmd: sdc2-cmd-state { 6232 pins = "sdc2_cmd"; 6233 }; 6234 6235 sdc2_data: sdc2-data-state { 6236 pins = "sdc2_data"; 6237 }; 6238 6239 sdc2_clk_sleep: sdc2-clk-sleep-state { 6240 pins = "sdc2_clk"; 6241 drive-strength = <2>; 6242 bias-bus-hold; 6243 }; 6244 6245 sdc2_cmd_sleep: sdc2-cmd-sleep-state { 6246 pins = "sdc2_cmd"; 6247 drive-strength = <2>; 6248 bias-bus-hold; 6249 }; 6250 6251 sdc2_data_sleep: sdc2-data-sleep-state { 6252 pins = "sdc2_data"; 6253 drive-strength = <2>; 6254 bias-bus-hold; 6255 }; 6256 }; 6257 6258 sram@146a5000 { 6259 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 6260 reg = <0 0x146a5000 0 0x6000>; 6261 6262 #address-cells = <1>; 6263 #size-cells = <1>; 6264 6265 ranges = <0 0 0x146a5000 0x6000>; 6266 6267 pil-reloc@594c { 6268 compatible = "qcom,pil-reloc-info"; 6269 reg = <0x594c 0xc8>; 6270 }; 6271 }; 6272 6273 apps_smmu: iommu@15000000 { 6274 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 6275 reg = <0 0x15000000 0 0x100000>; 6276 #iommu-cells = <2>; 6277 #global-interrupts = <1>; 6278 dma-coherent; 6279 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 6280 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 6281 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 6282 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 6283 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 6284 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 6285 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 6286 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 6287 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 6288 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 6289 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 6290 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 6291 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 6292 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 6293 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 6294 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 6295 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 6296 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 6297 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 6298 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 6299 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 6300 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 6301 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 6302 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 6303 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 6304 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 6305 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 6306 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 6307 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 6308 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 6309 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 6310 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 6311 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 6312 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 6313 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 6314 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 6315 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 6316 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 6317 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 6318 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 6319 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 6320 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 6321 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 6322 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 6323 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 6324 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 6325 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 6326 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 6327 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 6328 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 6329 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 6330 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 6331 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 6332 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 6333 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 6334 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 6335 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 6336 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 6337 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 6338 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 6339 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 6340 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 6341 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 6342 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 6343 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 6344 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 6345 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 6346 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 6347 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 6348 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 6349 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 6350 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 6351 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 6352 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 6353 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 6354 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 6355 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 6356 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 6357 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 6358 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 6359 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 6360 }; 6361 6362 anoc_1_tbu: tbu@151dd000 { 6363 compatible = "qcom,sc7280-tbu"; 6364 reg = <0x0 0x151dd000 0x0 0x1000>; 6365 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6366 &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>; 6367 qcom,stream-id-range = <&apps_smmu 0x0 0x400>; 6368 }; 6369 6370 anoc_2_tbu: tbu@151e1000 { 6371 compatible = "qcom,sc7280-tbu"; 6372 reg = <0x0 0x151e1000 0x0 0x1000>; 6373 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6374 &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>; 6375 qcom,stream-id-range = <&apps_smmu 0x400 0x400>; 6376 }; 6377 6378 mnoc_hf_0_tbu: tbu@151e5000 { 6379 compatible = "qcom,sc7280-tbu"; 6380 reg = <0x0 0x151e5000 0x0 0x1000>; 6381 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY 6382 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 6383 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC>; 6384 qcom,stream-id-range = <&apps_smmu 0x800 0x400>; 6385 }; 6386 6387 mnoc_hf_1_tbu: tbu@151e9000 { 6388 compatible = "qcom,sc7280-tbu"; 6389 reg = <0x0 0x151e9000 0x0 0x1000>; 6390 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY 6391 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 6392 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC>; 6393 qcom,stream-id-range = <&apps_smmu 0xc00 0x400>; 6394 }; 6395 6396 compute_dsp_1_tbu: tbu@151ed000 { 6397 compatible = "qcom,sc7280-tbu"; 6398 reg = <0x0 0x151ed000 0x0 0x1000>; 6399 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6400 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 6401 power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU1_GDSC>; 6402 qcom,stream-id-range = <&apps_smmu 0x1000 0x400>; 6403 }; 6404 6405 compute_dsp_0_tbu: tbu@151f1000 { 6406 compatible = "qcom,sc7280-tbu"; 6407 reg = <0x0 0x151f1000 0x0 0x1000>; 6408 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6409 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 6410 power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC>; 6411 qcom,stream-id-range = <&apps_smmu 0x1400 0x400>; 6412 }; 6413 6414 adsp_tbu: tbu@151f5000 { 6415 compatible = "qcom,sc7280-tbu"; 6416 reg = <0x0 0x151f5000 0x0 0x1000>; 6417 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6418 &lpass_ag_noc SLAVE_LPASS_CORE_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 6419 qcom,stream-id-range = <&apps_smmu 0x1800 0x400>; 6420 }; 6421 6422 anoc_1_pcie_tbu: tbu@151f9000 { 6423 compatible = "qcom,sc7280-tbu"; 6424 reg = <0x0 0x151f9000 0x0 0x1000>; 6425 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6426 &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>; 6427 qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>; 6428 }; 6429 6430 mnoc_sf_0_tbu: tbu@151fd000 { 6431 compatible = "qcom,sc7280-tbu"; 6432 reg = <0x0 0x151fd000 0x0 0x1000>; 6433 interconnects = <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ACTIVE_ONLY 6434 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 6435 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC>; 6436 qcom,stream-id-range = <&apps_smmu 0x2000 0x400>; 6437 }; 6438 6439 intc: interrupt-controller@17a00000 { 6440 compatible = "arm,gic-v3"; 6441 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 6442 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 6443 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 6444 #interrupt-cells = <3>; 6445 interrupt-controller; 6446 #address-cells = <2>; 6447 #size-cells = <2>; 6448 ranges; 6449 6450 msi-controller@17a40000 { 6451 compatible = "arm,gic-v3-its"; 6452 reg = <0 0x17a40000 0 0x20000>; 6453 msi-controller; 6454 #msi-cells = <1>; 6455 status = "disabled"; 6456 }; 6457 }; 6458 6459 watchdog: watchdog@17c10000 { 6460 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 6461 reg = <0 0x17c10000 0 0x1000>; 6462 clocks = <&sleep_clk>; 6463 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 6464 status = "reserved"; /* Owned by Gunyah hyp */ 6465 }; 6466 6467 timer@17c20000 { 6468 #address-cells = <1>; 6469 #size-cells = <1>; 6470 ranges = <0 0 0 0x20000000>; 6471 compatible = "arm,armv7-timer-mem"; 6472 reg = <0 0x17c20000 0 0x1000>; 6473 6474 frame@17c21000 { 6475 frame-number = <0>; 6476 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 6477 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 6478 reg = <0x17c21000 0x1000>, 6479 <0x17c22000 0x1000>; 6480 }; 6481 6482 frame@17c23000 { 6483 frame-number = <1>; 6484 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 6485 reg = <0x17c23000 0x1000>; 6486 status = "disabled"; 6487 }; 6488 6489 frame@17c25000 { 6490 frame-number = <2>; 6491 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 6492 reg = <0x17c25000 0x1000>; 6493 status = "disabled"; 6494 }; 6495 6496 frame@17c27000 { 6497 frame-number = <3>; 6498 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 6499 reg = <0x17c27000 0x1000>; 6500 status = "disabled"; 6501 }; 6502 6503 frame@17c29000 { 6504 frame-number = <4>; 6505 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 6506 reg = <0x17c29000 0x1000>; 6507 status = "disabled"; 6508 }; 6509 6510 frame@17c2b000 { 6511 frame-number = <5>; 6512 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 6513 reg = <0x17c2b000 0x1000>; 6514 status = "disabled"; 6515 }; 6516 6517 frame@17c2d000 { 6518 frame-number = <6>; 6519 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 6520 reg = <0x17c2d000 0x1000>; 6521 status = "disabled"; 6522 }; 6523 }; 6524 6525 apps_rsc: rsc@18200000 { 6526 compatible = "qcom,rpmh-rsc"; 6527 reg = <0 0x18200000 0 0x10000>, 6528 <0 0x18210000 0 0x10000>, 6529 <0 0x18220000 0 0x10000>; 6530 reg-names = "drv-0", "drv-1", "drv-2"; 6531 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 6532 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 6533 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 6534 qcom,tcs-offset = <0xd00>; 6535 qcom,drv-id = <2>; 6536 qcom,tcs-config = <ACTIVE_TCS 2>, 6537 <SLEEP_TCS 3>, 6538 <WAKE_TCS 3>, 6539 <CONTROL_TCS 1>; 6540 power-domains = <&cluster_pd>; 6541 6542 apps_bcm_voter: bcm-voter { 6543 compatible = "qcom,bcm-voter"; 6544 }; 6545 6546 rpmhpd: power-controller { 6547 compatible = "qcom,sc7280-rpmhpd"; 6548 #power-domain-cells = <1>; 6549 operating-points-v2 = <&rpmhpd_opp_table>; 6550 6551 rpmhpd_opp_table: opp-table { 6552 compatible = "operating-points-v2"; 6553 6554 rpmhpd_opp_ret: opp1 { 6555 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 6556 }; 6557 6558 rpmhpd_opp_low_svs: opp2 { 6559 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 6560 }; 6561 6562 rpmhpd_opp_svs: opp3 { 6563 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 6564 }; 6565 6566 rpmhpd_opp_svs_l1: opp4 { 6567 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 6568 }; 6569 6570 rpmhpd_opp_svs_l2: opp5 { 6571 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 6572 }; 6573 6574 rpmhpd_opp_nom: opp6 { 6575 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 6576 }; 6577 6578 rpmhpd_opp_nom_l1: opp7 { 6579 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 6580 }; 6581 6582 rpmhpd_opp_turbo: opp8 { 6583 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 6584 }; 6585 6586 rpmhpd_opp_turbo_l1: opp9 { 6587 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 6588 }; 6589 }; 6590 }; 6591 6592 rpmhcc: clock-controller { 6593 compatible = "qcom,sc7280-rpmh-clk"; 6594 clocks = <&xo_board>; 6595 clock-names = "xo"; 6596 #clock-cells = <1>; 6597 }; 6598 }; 6599 6600 epss_l3: interconnect@18590000 { 6601 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3"; 6602 reg = <0 0x18590000 0 0x1000>; 6603 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6604 clock-names = "xo", "alternate"; 6605 #interconnect-cells = <1>; 6606 }; 6607 6608 cpufreq_hw: cpufreq@18591000 { 6609 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss"; 6610 reg = <0 0x18591000 0 0x1000>, 6611 <0 0x18592000 0 0x1000>, 6612 <0 0x18593000 0 0x1000>; 6613 6614 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 6615 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 6616 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 6617 interrupt-names = "dcvsh-irq-0", 6618 "dcvsh-irq-1", 6619 "dcvsh-irq-2"; 6620 6621 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6622 clock-names = "xo", "alternate"; 6623 #freq-domain-cells = <1>; 6624 #clock-cells = <1>; 6625 }; 6626 }; 6627 6628 sound: sound { 6629 }; 6630 6631 thermal_zones: thermal-zones { 6632 cpu0-thermal { 6633 polling-delay-passive = <250>; 6634 6635 thermal-sensors = <&tsens0 1>; 6636 6637 trips { 6638 cpu0_alert0: trip-point0 { 6639 temperature = <90000>; 6640 hysteresis = <2000>; 6641 type = "passive"; 6642 }; 6643 6644 cpu0_alert1: trip-point1 { 6645 temperature = <95000>; 6646 hysteresis = <2000>; 6647 type = "passive"; 6648 }; 6649 6650 cpu0_crit: cpu-crit { 6651 temperature = <110000>; 6652 hysteresis = <0>; 6653 type = "critical"; 6654 }; 6655 }; 6656 6657 cooling-maps { 6658 map0 { 6659 trip = <&cpu0_alert0>; 6660 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6661 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6662 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6663 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6664 }; 6665 map1 { 6666 trip = <&cpu0_alert1>; 6667 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6668 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6669 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6670 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6671 }; 6672 }; 6673 }; 6674 6675 cpu1-thermal { 6676 polling-delay-passive = <250>; 6677 6678 thermal-sensors = <&tsens0 2>; 6679 6680 trips { 6681 cpu1_alert0: trip-point0 { 6682 temperature = <90000>; 6683 hysteresis = <2000>; 6684 type = "passive"; 6685 }; 6686 6687 cpu1_alert1: trip-point1 { 6688 temperature = <95000>; 6689 hysteresis = <2000>; 6690 type = "passive"; 6691 }; 6692 6693 cpu1_crit: cpu-crit { 6694 temperature = <110000>; 6695 hysteresis = <0>; 6696 type = "critical"; 6697 }; 6698 }; 6699 6700 cooling-maps { 6701 map0 { 6702 trip = <&cpu1_alert0>; 6703 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6704 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6705 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6706 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6707 }; 6708 map1 { 6709 trip = <&cpu1_alert1>; 6710 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6711 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6712 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6713 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6714 }; 6715 }; 6716 }; 6717 6718 cpu2-thermal { 6719 polling-delay-passive = <250>; 6720 6721 thermal-sensors = <&tsens0 3>; 6722 6723 trips { 6724 cpu2_alert0: trip-point0 { 6725 temperature = <90000>; 6726 hysteresis = <2000>; 6727 type = "passive"; 6728 }; 6729 6730 cpu2_alert1: trip-point1 { 6731 temperature = <95000>; 6732 hysteresis = <2000>; 6733 type = "passive"; 6734 }; 6735 6736 cpu2_crit: cpu-crit { 6737 temperature = <110000>; 6738 hysteresis = <0>; 6739 type = "critical"; 6740 }; 6741 }; 6742 6743 cooling-maps { 6744 map0 { 6745 trip = <&cpu2_alert0>; 6746 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6747 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6748 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6749 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6750 }; 6751 map1 { 6752 trip = <&cpu2_alert1>; 6753 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6754 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6755 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6756 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6757 }; 6758 }; 6759 }; 6760 6761 cpu3-thermal { 6762 polling-delay-passive = <250>; 6763 6764 thermal-sensors = <&tsens0 4>; 6765 6766 trips { 6767 cpu3_alert0: trip-point0 { 6768 temperature = <90000>; 6769 hysteresis = <2000>; 6770 type = "passive"; 6771 }; 6772 6773 cpu3_alert1: trip-point1 { 6774 temperature = <95000>; 6775 hysteresis = <2000>; 6776 type = "passive"; 6777 }; 6778 6779 cpu3_crit: cpu-crit { 6780 temperature = <110000>; 6781 hysteresis = <0>; 6782 type = "critical"; 6783 }; 6784 }; 6785 6786 cooling-maps { 6787 map0 { 6788 trip = <&cpu3_alert0>; 6789 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6790 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6791 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6792 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6793 }; 6794 map1 { 6795 trip = <&cpu3_alert1>; 6796 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6797 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6798 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6799 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6800 }; 6801 }; 6802 }; 6803 6804 cpu4-thermal { 6805 polling-delay-passive = <250>; 6806 6807 thermal-sensors = <&tsens0 7>; 6808 6809 trips { 6810 cpu4_alert0: trip-point0 { 6811 temperature = <90000>; 6812 hysteresis = <2000>; 6813 type = "passive"; 6814 }; 6815 6816 cpu4_alert1: trip-point1 { 6817 temperature = <95000>; 6818 hysteresis = <2000>; 6819 type = "passive"; 6820 }; 6821 6822 cpu4_crit: cpu-crit { 6823 temperature = <110000>; 6824 hysteresis = <0>; 6825 type = "critical"; 6826 }; 6827 }; 6828 6829 cooling-maps { 6830 map0 { 6831 trip = <&cpu4_alert0>; 6832 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6833 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6834 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6835 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6836 }; 6837 map1 { 6838 trip = <&cpu4_alert1>; 6839 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6840 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6841 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6842 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6843 }; 6844 }; 6845 }; 6846 6847 cpu5-thermal { 6848 polling-delay-passive = <250>; 6849 6850 thermal-sensors = <&tsens0 8>; 6851 6852 trips { 6853 cpu5_alert0: trip-point0 { 6854 temperature = <90000>; 6855 hysteresis = <2000>; 6856 type = "passive"; 6857 }; 6858 6859 cpu5_alert1: trip-point1 { 6860 temperature = <95000>; 6861 hysteresis = <2000>; 6862 type = "passive"; 6863 }; 6864 6865 cpu5_crit: cpu-crit { 6866 temperature = <110000>; 6867 hysteresis = <0>; 6868 type = "critical"; 6869 }; 6870 }; 6871 6872 cooling-maps { 6873 map0 { 6874 trip = <&cpu5_alert0>; 6875 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6876 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6877 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6878 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6879 }; 6880 map1 { 6881 trip = <&cpu5_alert1>; 6882 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6883 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6884 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6885 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6886 }; 6887 }; 6888 }; 6889 6890 cpu6-thermal { 6891 polling-delay-passive = <250>; 6892 6893 thermal-sensors = <&tsens0 9>; 6894 6895 trips { 6896 cpu6_alert0: trip-point0 { 6897 temperature = <90000>; 6898 hysteresis = <2000>; 6899 type = "passive"; 6900 }; 6901 6902 cpu6_alert1: trip-point1 { 6903 temperature = <95000>; 6904 hysteresis = <2000>; 6905 type = "passive"; 6906 }; 6907 6908 cpu6_crit: cpu-crit { 6909 temperature = <110000>; 6910 hysteresis = <0>; 6911 type = "critical"; 6912 }; 6913 }; 6914 6915 cooling-maps { 6916 map0 { 6917 trip = <&cpu6_alert0>; 6918 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6919 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6920 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6921 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6922 }; 6923 map1 { 6924 trip = <&cpu6_alert1>; 6925 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6926 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6927 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6928 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6929 }; 6930 }; 6931 }; 6932 6933 cpu7-thermal { 6934 polling-delay-passive = <250>; 6935 6936 thermal-sensors = <&tsens0 10>; 6937 6938 trips { 6939 cpu7_alert0: trip-point0 { 6940 temperature = <90000>; 6941 hysteresis = <2000>; 6942 type = "passive"; 6943 }; 6944 6945 cpu7_alert1: trip-point1 { 6946 temperature = <95000>; 6947 hysteresis = <2000>; 6948 type = "passive"; 6949 }; 6950 6951 cpu7_crit: cpu-crit { 6952 temperature = <110000>; 6953 hysteresis = <0>; 6954 type = "critical"; 6955 }; 6956 }; 6957 6958 cooling-maps { 6959 map0 { 6960 trip = <&cpu7_alert0>; 6961 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6962 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6963 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6964 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6965 }; 6966 map1 { 6967 trip = <&cpu7_alert1>; 6968 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6969 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6970 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6971 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6972 }; 6973 }; 6974 }; 6975 6976 cpu8-thermal { 6977 polling-delay-passive = <250>; 6978 6979 thermal-sensors = <&tsens0 11>; 6980 6981 trips { 6982 cpu8_alert0: trip-point0 { 6983 temperature = <90000>; 6984 hysteresis = <2000>; 6985 type = "passive"; 6986 }; 6987 6988 cpu8_alert1: trip-point1 { 6989 temperature = <95000>; 6990 hysteresis = <2000>; 6991 type = "passive"; 6992 }; 6993 6994 cpu8_crit: cpu-crit { 6995 temperature = <110000>; 6996 hysteresis = <0>; 6997 type = "critical"; 6998 }; 6999 }; 7000 7001 cooling-maps { 7002 map0 { 7003 trip = <&cpu8_alert0>; 7004 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7005 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7006 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7007 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7008 }; 7009 map1 { 7010 trip = <&cpu8_alert1>; 7011 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7012 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7013 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7014 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7015 }; 7016 }; 7017 }; 7018 7019 cpu9-thermal { 7020 polling-delay-passive = <250>; 7021 7022 thermal-sensors = <&tsens0 12>; 7023 7024 trips { 7025 cpu9_alert0: trip-point0 { 7026 temperature = <90000>; 7027 hysteresis = <2000>; 7028 type = "passive"; 7029 }; 7030 7031 cpu9_alert1: trip-point1 { 7032 temperature = <95000>; 7033 hysteresis = <2000>; 7034 type = "passive"; 7035 }; 7036 7037 cpu9_crit: cpu-crit { 7038 temperature = <110000>; 7039 hysteresis = <0>; 7040 type = "critical"; 7041 }; 7042 }; 7043 7044 cooling-maps { 7045 map0 { 7046 trip = <&cpu9_alert0>; 7047 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7048 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7049 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7050 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7051 }; 7052 map1 { 7053 trip = <&cpu9_alert1>; 7054 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7055 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7056 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7057 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7058 }; 7059 }; 7060 }; 7061 7062 cpu10-thermal { 7063 polling-delay-passive = <250>; 7064 7065 thermal-sensors = <&tsens0 13>; 7066 7067 trips { 7068 cpu10_alert0: trip-point0 { 7069 temperature = <90000>; 7070 hysteresis = <2000>; 7071 type = "passive"; 7072 }; 7073 7074 cpu10_alert1: trip-point1 { 7075 temperature = <95000>; 7076 hysteresis = <2000>; 7077 type = "passive"; 7078 }; 7079 7080 cpu10_crit: cpu-crit { 7081 temperature = <110000>; 7082 hysteresis = <0>; 7083 type = "critical"; 7084 }; 7085 }; 7086 7087 cooling-maps { 7088 map0 { 7089 trip = <&cpu10_alert0>; 7090 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7091 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7092 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7093 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7094 }; 7095 map1 { 7096 trip = <&cpu10_alert1>; 7097 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7098 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7099 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7100 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7101 }; 7102 }; 7103 }; 7104 7105 cpu11-thermal { 7106 polling-delay-passive = <250>; 7107 7108 thermal-sensors = <&tsens0 14>; 7109 7110 trips { 7111 cpu11_alert0: trip-point0 { 7112 temperature = <90000>; 7113 hysteresis = <2000>; 7114 type = "passive"; 7115 }; 7116 7117 cpu11_alert1: trip-point1 { 7118 temperature = <95000>; 7119 hysteresis = <2000>; 7120 type = "passive"; 7121 }; 7122 7123 cpu11_crit: cpu-crit { 7124 temperature = <110000>; 7125 hysteresis = <0>; 7126 type = "critical"; 7127 }; 7128 }; 7129 7130 cooling-maps { 7131 map0 { 7132 trip = <&cpu11_alert0>; 7133 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7134 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7135 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7136 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7137 }; 7138 map1 { 7139 trip = <&cpu11_alert1>; 7140 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7141 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7142 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7143 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7144 }; 7145 }; 7146 }; 7147 7148 aoss0-thermal { 7149 polling-delay-passive = <0>; 7150 7151 thermal-sensors = <&tsens0 0>; 7152 7153 trips { 7154 aoss0_alert0: trip-point0 { 7155 temperature = <90000>; 7156 hysteresis = <2000>; 7157 type = "hot"; 7158 }; 7159 7160 aoss0_crit: aoss0-crit { 7161 temperature = <110000>; 7162 hysteresis = <0>; 7163 type = "critical"; 7164 }; 7165 }; 7166 }; 7167 7168 aoss1-thermal { 7169 polling-delay-passive = <0>; 7170 7171 thermal-sensors = <&tsens1 0>; 7172 7173 trips { 7174 aoss1_alert0: trip-point0 { 7175 temperature = <90000>; 7176 hysteresis = <2000>; 7177 type = "hot"; 7178 }; 7179 7180 aoss1_crit: aoss1-crit { 7181 temperature = <110000>; 7182 hysteresis = <0>; 7183 type = "critical"; 7184 }; 7185 }; 7186 }; 7187 7188 cpuss0-thermal { 7189 polling-delay-passive = <0>; 7190 7191 thermal-sensors = <&tsens0 5>; 7192 7193 trips { 7194 cpuss0_alert0: trip-point0 { 7195 temperature = <90000>; 7196 hysteresis = <2000>; 7197 type = "hot"; 7198 }; 7199 cpuss0_crit: cluster0-crit { 7200 temperature = <110000>; 7201 hysteresis = <0>; 7202 type = "critical"; 7203 }; 7204 }; 7205 }; 7206 7207 cpuss1-thermal { 7208 polling-delay-passive = <0>; 7209 7210 thermal-sensors = <&tsens0 6>; 7211 7212 trips { 7213 cpuss1_alert0: trip-point0 { 7214 temperature = <90000>; 7215 hysteresis = <2000>; 7216 type = "hot"; 7217 }; 7218 cpuss1_crit: cluster0-crit { 7219 temperature = <110000>; 7220 hysteresis = <0>; 7221 type = "critical"; 7222 }; 7223 }; 7224 }; 7225 7226 gpuss0-thermal { 7227 polling-delay-passive = <100>; 7228 7229 thermal-sensors = <&tsens1 1>; 7230 7231 trips { 7232 gpuss0_alert0: trip-point0 { 7233 temperature = <95000>; 7234 hysteresis = <2000>; 7235 type = "passive"; 7236 }; 7237 7238 gpuss0_crit: gpuss0-crit { 7239 temperature = <110000>; 7240 hysteresis = <0>; 7241 type = "critical"; 7242 }; 7243 }; 7244 7245 cooling-maps { 7246 map0 { 7247 trip = <&gpuss0_alert0>; 7248 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7249 }; 7250 }; 7251 }; 7252 7253 gpuss1-thermal { 7254 polling-delay-passive = <100>; 7255 7256 thermal-sensors = <&tsens1 2>; 7257 7258 trips { 7259 gpuss1_alert0: trip-point0 { 7260 temperature = <95000>; 7261 hysteresis = <2000>; 7262 type = "passive"; 7263 }; 7264 7265 gpuss1_crit: gpuss1-crit { 7266 temperature = <110000>; 7267 hysteresis = <0>; 7268 type = "critical"; 7269 }; 7270 }; 7271 7272 cooling-maps { 7273 map0 { 7274 trip = <&gpuss1_alert0>; 7275 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7276 }; 7277 }; 7278 }; 7279 7280 nspss0-thermal { 7281 thermal-sensors = <&tsens1 3>; 7282 7283 trips { 7284 nspss0_alert0: trip-point0 { 7285 temperature = <90000>; 7286 hysteresis = <2000>; 7287 type = "hot"; 7288 }; 7289 7290 nspss0_crit: nspss0-crit { 7291 temperature = <110000>; 7292 hysteresis = <0>; 7293 type = "critical"; 7294 }; 7295 }; 7296 }; 7297 7298 nspss1-thermal { 7299 thermal-sensors = <&tsens1 4>; 7300 7301 trips { 7302 nspss1_alert0: trip-point0 { 7303 temperature = <90000>; 7304 hysteresis = <2000>; 7305 type = "hot"; 7306 }; 7307 7308 nspss1_crit: nspss1-crit { 7309 temperature = <110000>; 7310 hysteresis = <0>; 7311 type = "critical"; 7312 }; 7313 }; 7314 }; 7315 7316 video-thermal { 7317 thermal-sensors = <&tsens1 5>; 7318 7319 trips { 7320 video_alert0: trip-point0 { 7321 temperature = <90000>; 7322 hysteresis = <2000>; 7323 type = "hot"; 7324 }; 7325 7326 video_crit: video-crit { 7327 temperature = <110000>; 7328 hysteresis = <0>; 7329 type = "critical"; 7330 }; 7331 }; 7332 }; 7333 7334 ddr-thermal { 7335 thermal-sensors = <&tsens1 6>; 7336 7337 trips { 7338 ddr_alert0: trip-point0 { 7339 temperature = <90000>; 7340 hysteresis = <2000>; 7341 type = "hot"; 7342 }; 7343 7344 ddr_crit: ddr-crit { 7345 temperature = <110000>; 7346 hysteresis = <0>; 7347 type = "critical"; 7348 }; 7349 }; 7350 }; 7351 7352 mdmss0-thermal { 7353 thermal-sensors = <&tsens1 7>; 7354 7355 trips { 7356 mdmss0_alert0: trip-point0 { 7357 temperature = <90000>; 7358 hysteresis = <2000>; 7359 type = "hot"; 7360 }; 7361 7362 mdmss0_crit: mdmss0-crit { 7363 temperature = <110000>; 7364 hysteresis = <0>; 7365 type = "critical"; 7366 }; 7367 }; 7368 }; 7369 7370 mdmss1-thermal { 7371 thermal-sensors = <&tsens1 8>; 7372 7373 trips { 7374 mdmss1_alert0: trip-point0 { 7375 temperature = <90000>; 7376 hysteresis = <2000>; 7377 type = "hot"; 7378 }; 7379 7380 mdmss1_crit: mdmss1-crit { 7381 temperature = <110000>; 7382 hysteresis = <0>; 7383 type = "critical"; 7384 }; 7385 }; 7386 }; 7387 7388 mdmss2-thermal { 7389 thermal-sensors = <&tsens1 9>; 7390 7391 trips { 7392 mdmss2_alert0: trip-point0 { 7393 temperature = <90000>; 7394 hysteresis = <2000>; 7395 type = "hot"; 7396 }; 7397 7398 mdmss2_crit: mdmss2-crit { 7399 temperature = <110000>; 7400 hysteresis = <0>; 7401 type = "critical"; 7402 }; 7403 }; 7404 }; 7405 7406 mdmss3-thermal { 7407 thermal-sensors = <&tsens1 10>; 7408 7409 trips { 7410 mdmss3_alert0: trip-point0 { 7411 temperature = <90000>; 7412 hysteresis = <2000>; 7413 type = "hot"; 7414 }; 7415 7416 mdmss3_crit: mdmss3-crit { 7417 temperature = <110000>; 7418 hysteresis = <0>; 7419 type = "critical"; 7420 }; 7421 }; 7422 }; 7423 7424 camera0-thermal { 7425 thermal-sensors = <&tsens1 11>; 7426 7427 trips { 7428 camera0_alert0: trip-point0 { 7429 temperature = <90000>; 7430 hysteresis = <2000>; 7431 type = "hot"; 7432 }; 7433 7434 camera0_crit: camera0-crit { 7435 temperature = <110000>; 7436 hysteresis = <0>; 7437 type = "critical"; 7438 }; 7439 }; 7440 }; 7441 }; 7442 7443 timer { 7444 compatible = "arm,armv8-timer"; 7445 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 7446 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 7447 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 7448 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 7449 }; 7450}; 7451