1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/firmware/qcom,scm.h> 17#include <dt-bindings/gpio/gpio.h> 18#include <dt-bindings/interconnect/qcom,icc.h> 19#include <dt-bindings/interconnect/qcom,osm-l3.h> 20#include <dt-bindings/interconnect/qcom,sc7280.h> 21#include <dt-bindings/interrupt-controller/arm-gic.h> 22#include <dt-bindings/mailbox/qcom-ipcc.h> 23#include <dt-bindings/phy/phy-qcom-qmp.h> 24#include <dt-bindings/power/qcom-rpmpd.h> 25#include <dt-bindings/reset/qcom,sdm845-aoss.h> 26#include <dt-bindings/reset/qcom,sdm845-pdc.h> 27#include <dt-bindings/soc/qcom,apr.h> 28#include <dt-bindings/soc/qcom,rpmh-rsc.h> 29#include <dt-bindings/sound/qcom,lpass.h> 30#include <dt-bindings/thermal/thermal.h> 31 32/ { 33 interrupt-parent = <&intc>; 34 35 #address-cells = <2>; 36 #size-cells = <2>; 37 38 chosen { }; 39 40 aliases { 41 i2c0 = &i2c0; 42 i2c1 = &i2c1; 43 i2c2 = &i2c2; 44 i2c3 = &i2c3; 45 i2c4 = &i2c4; 46 i2c5 = &i2c5; 47 i2c6 = &i2c6; 48 i2c7 = &i2c7; 49 i2c8 = &i2c8; 50 i2c9 = &i2c9; 51 i2c10 = &i2c10; 52 i2c11 = &i2c11; 53 i2c12 = &i2c12; 54 i2c13 = &i2c13; 55 i2c14 = &i2c14; 56 i2c15 = &i2c15; 57 mmc1 = &sdhc_1; 58 mmc2 = &sdhc_2; 59 spi0 = &spi0; 60 spi1 = &spi1; 61 spi2 = &spi2; 62 spi3 = &spi3; 63 spi4 = &spi4; 64 spi5 = &spi5; 65 spi6 = &spi6; 66 spi7 = &spi7; 67 spi8 = &spi8; 68 spi9 = &spi9; 69 spi10 = &spi10; 70 spi11 = &spi11; 71 spi12 = &spi12; 72 spi13 = &spi13; 73 spi14 = &spi14; 74 spi15 = &spi15; 75 }; 76 77 clocks { 78 xo_board: xo-board { 79 compatible = "fixed-clock"; 80 clock-frequency = <76800000>; 81 #clock-cells = <0>; 82 }; 83 84 sleep_clk: sleep-clk { 85 compatible = "fixed-clock"; 86 clock-frequency = <32000>; 87 #clock-cells = <0>; 88 }; 89 }; 90 91 reserved-memory { 92 #address-cells = <2>; 93 #size-cells = <2>; 94 ranges; 95 96 wlan_ce_mem: wlan-ce@4cd000 { 97 no-map; 98 reg = <0x0 0x004cd000 0x0 0x1000>; 99 }; 100 101 hyp_mem: hyp@80000000 { 102 reg = <0x0 0x80000000 0x0 0x600000>; 103 no-map; 104 }; 105 106 xbl_mem: xbl@80600000 { 107 reg = <0x0 0x80600000 0x0 0x200000>; 108 no-map; 109 }; 110 111 aop_mem: aop@80800000 { 112 reg = <0x0 0x80800000 0x0 0x60000>; 113 no-map; 114 }; 115 116 aop_cmd_db_mem: aop-cmd-db@80860000 { 117 reg = <0x0 0x80860000 0x0 0x20000>; 118 compatible = "qcom,cmd-db"; 119 no-map; 120 }; 121 122 reserved_xbl_uefi_log: xbl-uefi-res@80880000 { 123 reg = <0x0 0x80884000 0x0 0x10000>; 124 no-map; 125 }; 126 127 sec_apps_mem: sec-apps@808ff000 { 128 reg = <0x0 0x808ff000 0x0 0x1000>; 129 no-map; 130 }; 131 132 smem_mem: smem@80900000 { 133 reg = <0x0 0x80900000 0x0 0x200000>; 134 no-map; 135 }; 136 137 cpucp_mem: cpucp@80b00000 { 138 no-map; 139 reg = <0x0 0x80b00000 0x0 0x100000>; 140 }; 141 142 wlan_fw_mem: wlan-fw@80c00000 { 143 reg = <0x0 0x80c00000 0x0 0xc00000>; 144 no-map; 145 }; 146 147 adsp_mem: adsp@86700000 { 148 reg = <0x0 0x86700000 0x0 0x2800000>; 149 no-map; 150 }; 151 152 video_mem: video@8b200000 { 153 reg = <0x0 0x8b200000 0x0 0x500000>; 154 no-map; 155 }; 156 157 cdsp_mem: cdsp@88f00000 { 158 reg = <0x0 0x88f00000 0x0 0x1e00000>; 159 no-map; 160 }; 161 162 ipa_fw_mem: ipa-fw@8b700000 { 163 reg = <0 0x8b700000 0 0x10000>; 164 no-map; 165 }; 166 167 gpu_zap_mem: zap@8b71a000 { 168 reg = <0 0x8b71a000 0 0x2000>; 169 no-map; 170 }; 171 172 mpss_mem: mpss@8b800000 { 173 reg = <0x0 0x8b800000 0x0 0xf600000>; 174 no-map; 175 }; 176 177 wpss_mem: wpss@9ae00000 { 178 reg = <0x0 0x9ae00000 0x0 0x1900000>; 179 no-map; 180 }; 181 182 rmtfs_mem: rmtfs@9c900000 { 183 compatible = "qcom,rmtfs-mem"; 184 reg = <0x0 0x9c900000 0x0 0x280000>; 185 no-map; 186 187 qcom,client-id = <1>; 188 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 189 }; 190 }; 191 192 cpus { 193 #address-cells = <2>; 194 #size-cells = <0>; 195 196 CPU0: cpu@0 { 197 device_type = "cpu"; 198 compatible = "qcom,kryo"; 199 reg = <0x0 0x0>; 200 clocks = <&cpufreq_hw 0>; 201 enable-method = "psci"; 202 power-domains = <&CPU_PD0>; 203 power-domain-names = "psci"; 204 next-level-cache = <&L2_0>; 205 operating-points-v2 = <&cpu0_opp_table>; 206 capacity-dmips-mhz = <1024>; 207 dynamic-power-coefficient = <100>; 208 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 209 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 210 qcom,freq-domain = <&cpufreq_hw 0>; 211 #cooling-cells = <2>; 212 L2_0: l2-cache { 213 compatible = "cache"; 214 cache-level = <2>; 215 cache-unified; 216 next-level-cache = <&L3_0>; 217 L3_0: l3-cache { 218 compatible = "cache"; 219 cache-level = <3>; 220 cache-unified; 221 }; 222 }; 223 }; 224 225 CPU1: cpu@100 { 226 device_type = "cpu"; 227 compatible = "qcom,kryo"; 228 reg = <0x0 0x100>; 229 clocks = <&cpufreq_hw 0>; 230 enable-method = "psci"; 231 power-domains = <&CPU_PD1>; 232 power-domain-names = "psci"; 233 next-level-cache = <&L2_100>; 234 operating-points-v2 = <&cpu0_opp_table>; 235 capacity-dmips-mhz = <1024>; 236 dynamic-power-coefficient = <100>; 237 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 238 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 239 qcom,freq-domain = <&cpufreq_hw 0>; 240 #cooling-cells = <2>; 241 L2_100: l2-cache { 242 compatible = "cache"; 243 cache-level = <2>; 244 cache-unified; 245 next-level-cache = <&L3_0>; 246 }; 247 }; 248 249 CPU2: cpu@200 { 250 device_type = "cpu"; 251 compatible = "qcom,kryo"; 252 reg = <0x0 0x200>; 253 clocks = <&cpufreq_hw 0>; 254 enable-method = "psci"; 255 power-domains = <&CPU_PD2>; 256 power-domain-names = "psci"; 257 next-level-cache = <&L2_200>; 258 operating-points-v2 = <&cpu0_opp_table>; 259 capacity-dmips-mhz = <1024>; 260 dynamic-power-coefficient = <100>; 261 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 262 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 263 qcom,freq-domain = <&cpufreq_hw 0>; 264 #cooling-cells = <2>; 265 L2_200: l2-cache { 266 compatible = "cache"; 267 cache-level = <2>; 268 cache-unified; 269 next-level-cache = <&L3_0>; 270 }; 271 }; 272 273 CPU3: cpu@300 { 274 device_type = "cpu"; 275 compatible = "qcom,kryo"; 276 reg = <0x0 0x300>; 277 clocks = <&cpufreq_hw 0>; 278 enable-method = "psci"; 279 power-domains = <&CPU_PD3>; 280 power-domain-names = "psci"; 281 next-level-cache = <&L2_300>; 282 operating-points-v2 = <&cpu0_opp_table>; 283 capacity-dmips-mhz = <1024>; 284 dynamic-power-coefficient = <100>; 285 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 286 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 287 qcom,freq-domain = <&cpufreq_hw 0>; 288 #cooling-cells = <2>; 289 L2_300: l2-cache { 290 compatible = "cache"; 291 cache-level = <2>; 292 cache-unified; 293 next-level-cache = <&L3_0>; 294 }; 295 }; 296 297 CPU4: cpu@400 { 298 device_type = "cpu"; 299 compatible = "qcom,kryo"; 300 reg = <0x0 0x400>; 301 clocks = <&cpufreq_hw 1>; 302 enable-method = "psci"; 303 power-domains = <&CPU_PD4>; 304 power-domain-names = "psci"; 305 next-level-cache = <&L2_400>; 306 operating-points-v2 = <&cpu4_opp_table>; 307 capacity-dmips-mhz = <1946>; 308 dynamic-power-coefficient = <520>; 309 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 310 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 311 qcom,freq-domain = <&cpufreq_hw 1>; 312 #cooling-cells = <2>; 313 L2_400: l2-cache { 314 compatible = "cache"; 315 cache-level = <2>; 316 cache-unified; 317 next-level-cache = <&L3_0>; 318 }; 319 }; 320 321 CPU5: cpu@500 { 322 device_type = "cpu"; 323 compatible = "qcom,kryo"; 324 reg = <0x0 0x500>; 325 clocks = <&cpufreq_hw 1>; 326 enable-method = "psci"; 327 power-domains = <&CPU_PD5>; 328 power-domain-names = "psci"; 329 next-level-cache = <&L2_500>; 330 operating-points-v2 = <&cpu4_opp_table>; 331 capacity-dmips-mhz = <1946>; 332 dynamic-power-coefficient = <520>; 333 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 334 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 335 qcom,freq-domain = <&cpufreq_hw 1>; 336 #cooling-cells = <2>; 337 L2_500: l2-cache { 338 compatible = "cache"; 339 cache-level = <2>; 340 cache-unified; 341 next-level-cache = <&L3_0>; 342 }; 343 }; 344 345 CPU6: cpu@600 { 346 device_type = "cpu"; 347 compatible = "qcom,kryo"; 348 reg = <0x0 0x600>; 349 clocks = <&cpufreq_hw 1>; 350 enable-method = "psci"; 351 power-domains = <&CPU_PD6>; 352 power-domain-names = "psci"; 353 next-level-cache = <&L2_600>; 354 operating-points-v2 = <&cpu4_opp_table>; 355 capacity-dmips-mhz = <1946>; 356 dynamic-power-coefficient = <520>; 357 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 358 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 359 qcom,freq-domain = <&cpufreq_hw 1>; 360 #cooling-cells = <2>; 361 L2_600: l2-cache { 362 compatible = "cache"; 363 cache-level = <2>; 364 cache-unified; 365 next-level-cache = <&L3_0>; 366 }; 367 }; 368 369 CPU7: cpu@700 { 370 device_type = "cpu"; 371 compatible = "qcom,kryo"; 372 reg = <0x0 0x700>; 373 clocks = <&cpufreq_hw 2>; 374 enable-method = "psci"; 375 power-domains = <&CPU_PD7>; 376 power-domain-names = "psci"; 377 next-level-cache = <&L2_700>; 378 operating-points-v2 = <&cpu7_opp_table>; 379 capacity-dmips-mhz = <1985>; 380 dynamic-power-coefficient = <552>; 381 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 382 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 383 qcom,freq-domain = <&cpufreq_hw 2>; 384 #cooling-cells = <2>; 385 L2_700: l2-cache { 386 compatible = "cache"; 387 cache-level = <2>; 388 cache-unified; 389 next-level-cache = <&L3_0>; 390 }; 391 }; 392 393 cpu-map { 394 cluster0 { 395 core0 { 396 cpu = <&CPU0>; 397 }; 398 399 core1 { 400 cpu = <&CPU1>; 401 }; 402 403 core2 { 404 cpu = <&CPU2>; 405 }; 406 407 core3 { 408 cpu = <&CPU3>; 409 }; 410 411 core4 { 412 cpu = <&CPU4>; 413 }; 414 415 core5 { 416 cpu = <&CPU5>; 417 }; 418 419 core6 { 420 cpu = <&CPU6>; 421 }; 422 423 core7 { 424 cpu = <&CPU7>; 425 }; 426 }; 427 }; 428 429 idle-states { 430 entry-method = "psci"; 431 432 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 433 compatible = "arm,idle-state"; 434 idle-state-name = "little-power-down"; 435 arm,psci-suspend-param = <0x40000003>; 436 entry-latency-us = <549>; 437 exit-latency-us = <901>; 438 min-residency-us = <1774>; 439 local-timer-stop; 440 }; 441 442 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 443 compatible = "arm,idle-state"; 444 idle-state-name = "little-rail-power-down"; 445 arm,psci-suspend-param = <0x40000004>; 446 entry-latency-us = <702>; 447 exit-latency-us = <915>; 448 min-residency-us = <4001>; 449 local-timer-stop; 450 }; 451 452 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 453 compatible = "arm,idle-state"; 454 idle-state-name = "big-power-down"; 455 arm,psci-suspend-param = <0x40000003>; 456 entry-latency-us = <523>; 457 exit-latency-us = <1244>; 458 min-residency-us = <2207>; 459 local-timer-stop; 460 }; 461 462 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 463 compatible = "arm,idle-state"; 464 idle-state-name = "big-rail-power-down"; 465 arm,psci-suspend-param = <0x40000004>; 466 entry-latency-us = <526>; 467 exit-latency-us = <1854>; 468 min-residency-us = <5555>; 469 local-timer-stop; 470 }; 471 }; 472 473 domain_idle_states: domain-idle-states { 474 CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { 475 compatible = "domain-idle-state"; 476 arm,psci-suspend-param = <0x41000044>; 477 entry-latency-us = <2752>; 478 exit-latency-us = <3048>; 479 min-residency-us = <6118>; 480 }; 481 482 CLUSTER_SLEEP_CX_RET: cluster-sleep-1 { 483 compatible = "domain-idle-state"; 484 arm,psci-suspend-param = <0x41001344>; 485 entry-latency-us = <3263>; 486 exit-latency-us = <4562>; 487 min-residency-us = <8467>; 488 }; 489 490 CLUSTER_SLEEP_LLCC_OFF: cluster-sleep-2 { 491 compatible = "domain-idle-state"; 492 arm,psci-suspend-param = <0x4100b344>; 493 entry-latency-us = <3638>; 494 exit-latency-us = <6562>; 495 min-residency-us = <9826>; 496 }; 497 }; 498 }; 499 500 cpu0_opp_table: opp-table-cpu0 { 501 compatible = "operating-points-v2"; 502 opp-shared; 503 504 cpu0_opp_300mhz: opp-300000000 { 505 opp-hz = /bits/ 64 <300000000>; 506 opp-peak-kBps = <800000 9600000>; 507 }; 508 509 cpu0_opp_691mhz: opp-691200000 { 510 opp-hz = /bits/ 64 <691200000>; 511 opp-peak-kBps = <800000 17817600>; 512 }; 513 514 cpu0_opp_806mhz: opp-806400000 { 515 opp-hz = /bits/ 64 <806400000>; 516 opp-peak-kBps = <800000 20889600>; 517 }; 518 519 cpu0_opp_941mhz: opp-940800000 { 520 opp-hz = /bits/ 64 <940800000>; 521 opp-peak-kBps = <1804000 24576000>; 522 }; 523 524 cpu0_opp_1152mhz: opp-1152000000 { 525 opp-hz = /bits/ 64 <1152000000>; 526 opp-peak-kBps = <2188000 27033600>; 527 }; 528 529 cpu0_opp_1325mhz: opp-1324800000 { 530 opp-hz = /bits/ 64 <1324800000>; 531 opp-peak-kBps = <2188000 33792000>; 532 }; 533 534 cpu0_opp_1517mhz: opp-1516800000 { 535 opp-hz = /bits/ 64 <1516800000>; 536 opp-peak-kBps = <3072000 38092800>; 537 }; 538 539 cpu0_opp_1651mhz: opp-1651200000 { 540 opp-hz = /bits/ 64 <1651200000>; 541 opp-peak-kBps = <3072000 41779200>; 542 }; 543 544 cpu0_opp_1805mhz: opp-1804800000 { 545 opp-hz = /bits/ 64 <1804800000>; 546 opp-peak-kBps = <4068000 48537600>; 547 }; 548 549 cpu0_opp_1958mhz: opp-1958400000 { 550 opp-hz = /bits/ 64 <1958400000>; 551 opp-peak-kBps = <4068000 48537600>; 552 }; 553 554 cpu0_opp_2016mhz: opp-2016000000 { 555 opp-hz = /bits/ 64 <2016000000>; 556 opp-peak-kBps = <6220000 48537600>; 557 }; 558 }; 559 560 cpu4_opp_table: opp-table-cpu4 { 561 compatible = "operating-points-v2"; 562 opp-shared; 563 564 cpu4_opp_691mhz: opp-691200000 { 565 opp-hz = /bits/ 64 <691200000>; 566 opp-peak-kBps = <1804000 9600000>; 567 }; 568 569 cpu4_opp_941mhz: opp-940800000 { 570 opp-hz = /bits/ 64 <940800000>; 571 opp-peak-kBps = <2188000 17817600>; 572 }; 573 574 cpu4_opp_1229mhz: opp-1228800000 { 575 opp-hz = /bits/ 64 <1228800000>; 576 opp-peak-kBps = <4068000 24576000>; 577 }; 578 579 cpu4_opp_1344mhz: opp-1344000000 { 580 opp-hz = /bits/ 64 <1344000000>; 581 opp-peak-kBps = <4068000 24576000>; 582 }; 583 584 cpu4_opp_1517mhz: opp-1516800000 { 585 opp-hz = /bits/ 64 <1516800000>; 586 opp-peak-kBps = <4068000 24576000>; 587 }; 588 589 cpu4_opp_1651mhz: opp-1651200000 { 590 opp-hz = /bits/ 64 <1651200000>; 591 opp-peak-kBps = <6220000 38092800>; 592 }; 593 594 cpu4_opp_1901mhz: opp-1900800000 { 595 opp-hz = /bits/ 64 <1900800000>; 596 opp-peak-kBps = <6220000 44851200>; 597 }; 598 599 cpu4_opp_2054mhz: opp-2054400000 { 600 opp-hz = /bits/ 64 <2054400000>; 601 opp-peak-kBps = <6220000 44851200>; 602 }; 603 604 cpu4_opp_2112mhz: opp-2112000000 { 605 opp-hz = /bits/ 64 <2112000000>; 606 opp-peak-kBps = <6220000 44851200>; 607 }; 608 609 cpu4_opp_2131mhz: opp-2131200000 { 610 opp-hz = /bits/ 64 <2131200000>; 611 opp-peak-kBps = <6220000 44851200>; 612 }; 613 614 cpu4_opp_2208mhz: opp-2208000000 { 615 opp-hz = /bits/ 64 <2208000000>; 616 opp-peak-kBps = <6220000 44851200>; 617 }; 618 619 cpu4_opp_2400mhz: opp-2400000000 { 620 opp-hz = /bits/ 64 <2400000000>; 621 opp-peak-kBps = <8532000 48537600>; 622 }; 623 624 cpu4_opp_2611mhz: opp-2611200000 { 625 opp-hz = /bits/ 64 <2611200000>; 626 opp-peak-kBps = <8532000 48537600>; 627 }; 628 }; 629 630 cpu7_opp_table: opp-table-cpu7 { 631 compatible = "operating-points-v2"; 632 opp-shared; 633 634 cpu7_opp_806mhz: opp-806400000 { 635 opp-hz = /bits/ 64 <806400000>; 636 opp-peak-kBps = <1804000 9600000>; 637 }; 638 639 cpu7_opp_1056mhz: opp-1056000000 { 640 opp-hz = /bits/ 64 <1056000000>; 641 opp-peak-kBps = <2188000 17817600>; 642 }; 643 644 cpu7_opp_1325mhz: opp-1324800000 { 645 opp-hz = /bits/ 64 <1324800000>; 646 opp-peak-kBps = <4068000 24576000>; 647 }; 648 649 cpu7_opp_1517mhz: opp-1516800000 { 650 opp-hz = /bits/ 64 <1516800000>; 651 opp-peak-kBps = <4068000 24576000>; 652 }; 653 654 cpu7_opp_1766mhz: opp-1766400000 { 655 opp-hz = /bits/ 64 <1766400000>; 656 opp-peak-kBps = <6220000 38092800>; 657 }; 658 659 cpu7_opp_1862mhz: opp-1862400000 { 660 opp-hz = /bits/ 64 <1862400000>; 661 opp-peak-kBps = <6220000 38092800>; 662 }; 663 664 cpu7_opp_2035mhz: opp-2035200000 { 665 opp-hz = /bits/ 64 <2035200000>; 666 opp-peak-kBps = <6220000 38092800>; 667 }; 668 669 cpu7_opp_2112mhz: opp-2112000000 { 670 opp-hz = /bits/ 64 <2112000000>; 671 opp-peak-kBps = <6220000 44851200>; 672 }; 673 674 cpu7_opp_2208mhz: opp-2208000000 { 675 opp-hz = /bits/ 64 <2208000000>; 676 opp-peak-kBps = <6220000 44851200>; 677 }; 678 679 cpu7_opp_2381mhz: opp-2380800000 { 680 opp-hz = /bits/ 64 <2380800000>; 681 opp-peak-kBps = <6832000 44851200>; 682 }; 683 684 cpu7_opp_2400mhz: opp-2400000000 { 685 opp-hz = /bits/ 64 <2400000000>; 686 opp-peak-kBps = <8532000 48537600>; 687 }; 688 689 cpu7_opp_2515mhz: opp-2515200000 { 690 opp-hz = /bits/ 64 <2515200000>; 691 opp-peak-kBps = <8532000 48537600>; 692 }; 693 694 cpu7_opp_2707mhz: opp-2707200000 { 695 opp-hz = /bits/ 64 <2707200000>; 696 opp-peak-kBps = <8532000 48537600>; 697 }; 698 699 cpu7_opp_3014mhz: opp-3014400000 { 700 opp-hz = /bits/ 64 <3014400000>; 701 opp-peak-kBps = <8532000 48537600>; 702 }; 703 }; 704 705 memory@80000000 { 706 device_type = "memory"; 707 /* We expect the bootloader to fill in the size */ 708 reg = <0 0x80000000 0 0>; 709 }; 710 711 firmware { 712 scm: scm { 713 compatible = "qcom,scm-sc7280", "qcom,scm"; 714 qcom,dload-mode = <&tcsr_2 0x13000>; 715 }; 716 }; 717 718 clk_virt: interconnect { 719 compatible = "qcom,sc7280-clk-virt"; 720 #interconnect-cells = <2>; 721 qcom,bcm-voters = <&apps_bcm_voter>; 722 }; 723 724 smem { 725 compatible = "qcom,smem"; 726 memory-region = <&smem_mem>; 727 hwlocks = <&tcsr_mutex 3>; 728 }; 729 730 smp2p-adsp { 731 compatible = "qcom,smp2p"; 732 qcom,smem = <443>, <429>; 733 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 734 IPCC_MPROC_SIGNAL_SMP2P 735 IRQ_TYPE_EDGE_RISING>; 736 mboxes = <&ipcc IPCC_CLIENT_LPASS 737 IPCC_MPROC_SIGNAL_SMP2P>; 738 739 qcom,local-pid = <0>; 740 qcom,remote-pid = <2>; 741 742 adsp_smp2p_out: master-kernel { 743 qcom,entry-name = "master-kernel"; 744 #qcom,smem-state-cells = <1>; 745 }; 746 747 adsp_smp2p_in: slave-kernel { 748 qcom,entry-name = "slave-kernel"; 749 interrupt-controller; 750 #interrupt-cells = <2>; 751 }; 752 }; 753 754 smp2p-cdsp { 755 compatible = "qcom,smp2p"; 756 qcom,smem = <94>, <432>; 757 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 758 IPCC_MPROC_SIGNAL_SMP2P 759 IRQ_TYPE_EDGE_RISING>; 760 mboxes = <&ipcc IPCC_CLIENT_CDSP 761 IPCC_MPROC_SIGNAL_SMP2P>; 762 763 qcom,local-pid = <0>; 764 qcom,remote-pid = <5>; 765 766 cdsp_smp2p_out: master-kernel { 767 qcom,entry-name = "master-kernel"; 768 #qcom,smem-state-cells = <1>; 769 }; 770 771 cdsp_smp2p_in: slave-kernel { 772 qcom,entry-name = "slave-kernel"; 773 interrupt-controller; 774 #interrupt-cells = <2>; 775 }; 776 }; 777 778 smp2p-mpss { 779 compatible = "qcom,smp2p"; 780 qcom,smem = <435>, <428>; 781 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 782 IPCC_MPROC_SIGNAL_SMP2P 783 IRQ_TYPE_EDGE_RISING>; 784 mboxes = <&ipcc IPCC_CLIENT_MPSS 785 IPCC_MPROC_SIGNAL_SMP2P>; 786 787 qcom,local-pid = <0>; 788 qcom,remote-pid = <1>; 789 790 modem_smp2p_out: master-kernel { 791 qcom,entry-name = "master-kernel"; 792 #qcom,smem-state-cells = <1>; 793 }; 794 795 modem_smp2p_in: slave-kernel { 796 qcom,entry-name = "slave-kernel"; 797 interrupt-controller; 798 #interrupt-cells = <2>; 799 }; 800 801 ipa_smp2p_out: ipa-ap-to-modem { 802 qcom,entry-name = "ipa"; 803 #qcom,smem-state-cells = <1>; 804 }; 805 806 ipa_smp2p_in: ipa-modem-to-ap { 807 qcom,entry-name = "ipa"; 808 interrupt-controller; 809 #interrupt-cells = <2>; 810 }; 811 }; 812 813 smp2p-wpss { 814 compatible = "qcom,smp2p"; 815 qcom,smem = <617>, <616>; 816 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 817 IPCC_MPROC_SIGNAL_SMP2P 818 IRQ_TYPE_EDGE_RISING>; 819 mboxes = <&ipcc IPCC_CLIENT_WPSS 820 IPCC_MPROC_SIGNAL_SMP2P>; 821 822 qcom,local-pid = <0>; 823 qcom,remote-pid = <13>; 824 825 wpss_smp2p_out: master-kernel { 826 qcom,entry-name = "master-kernel"; 827 #qcom,smem-state-cells = <1>; 828 }; 829 830 wpss_smp2p_in: slave-kernel { 831 qcom,entry-name = "slave-kernel"; 832 interrupt-controller; 833 #interrupt-cells = <2>; 834 }; 835 836 wlan_smp2p_out: wlan-ap-to-wpss { 837 qcom,entry-name = "wlan"; 838 #qcom,smem-state-cells = <1>; 839 }; 840 841 wlan_smp2p_in: wlan-wpss-to-ap { 842 qcom,entry-name = "wlan"; 843 interrupt-controller; 844 #interrupt-cells = <2>; 845 }; 846 }; 847 848 pmu { 849 compatible = "arm,armv8-pmuv3"; 850 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 851 }; 852 853 psci { 854 compatible = "arm,psci-1.0"; 855 method = "smc"; 856 857 CPU_PD0: power-domain-cpu0 { 858 #power-domain-cells = <0>; 859 power-domains = <&CLUSTER_PD>; 860 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 861 }; 862 863 CPU_PD1: power-domain-cpu1 { 864 #power-domain-cells = <0>; 865 power-domains = <&CLUSTER_PD>; 866 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 867 }; 868 869 CPU_PD2: power-domain-cpu2 { 870 #power-domain-cells = <0>; 871 power-domains = <&CLUSTER_PD>; 872 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 873 }; 874 875 CPU_PD3: power-domain-cpu3 { 876 #power-domain-cells = <0>; 877 power-domains = <&CLUSTER_PD>; 878 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 879 }; 880 881 CPU_PD4: power-domain-cpu4 { 882 #power-domain-cells = <0>; 883 power-domains = <&CLUSTER_PD>; 884 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 885 }; 886 887 CPU_PD5: power-domain-cpu5 { 888 #power-domain-cells = <0>; 889 power-domains = <&CLUSTER_PD>; 890 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 891 }; 892 893 CPU_PD6: power-domain-cpu6 { 894 #power-domain-cells = <0>; 895 power-domains = <&CLUSTER_PD>; 896 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 897 }; 898 899 CPU_PD7: power-domain-cpu7 { 900 #power-domain-cells = <0>; 901 power-domains = <&CLUSTER_PD>; 902 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 903 }; 904 905 CLUSTER_PD: power-domain-cluster { 906 #power-domain-cells = <0>; 907 domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_CX_RET &CLUSTER_SLEEP_LLCC_OFF>; 908 }; 909 }; 910 911 qspi_opp_table: opp-table-qspi { 912 compatible = "operating-points-v2"; 913 914 opp-75000000 { 915 opp-hz = /bits/ 64 <75000000>; 916 required-opps = <&rpmhpd_opp_low_svs>; 917 }; 918 919 opp-150000000 { 920 opp-hz = /bits/ 64 <150000000>; 921 required-opps = <&rpmhpd_opp_svs>; 922 }; 923 924 opp-200000000 { 925 opp-hz = /bits/ 64 <200000000>; 926 required-opps = <&rpmhpd_opp_svs_l1>; 927 }; 928 929 opp-300000000 { 930 opp-hz = /bits/ 64 <300000000>; 931 required-opps = <&rpmhpd_opp_nom>; 932 }; 933 }; 934 935 qup_opp_table: opp-table-qup { 936 compatible = "operating-points-v2"; 937 938 opp-75000000 { 939 opp-hz = /bits/ 64 <75000000>; 940 required-opps = <&rpmhpd_opp_low_svs>; 941 }; 942 943 opp-100000000 { 944 opp-hz = /bits/ 64 <100000000>; 945 required-opps = <&rpmhpd_opp_svs>; 946 }; 947 948 opp-128000000 { 949 opp-hz = /bits/ 64 <128000000>; 950 required-opps = <&rpmhpd_opp_nom>; 951 }; 952 }; 953 954 soc: soc@0 { 955 #address-cells = <2>; 956 #size-cells = <2>; 957 ranges = <0 0 0 0 0x10 0>; 958 dma-ranges = <0 0 0 0 0x10 0>; 959 compatible = "simple-bus"; 960 961 gcc: clock-controller@100000 { 962 compatible = "qcom,gcc-sc7280"; 963 reg = <0 0x00100000 0 0x1f0000>; 964 clocks = <&rpmhcc RPMH_CXO_CLK>, 965 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 966 <0>, <&pcie1_phy>, 967 <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, 968 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 969 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 970 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 971 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 972 "ufs_phy_tx_symbol_0_clk", 973 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 974 #clock-cells = <1>; 975 #reset-cells = <1>; 976 #power-domain-cells = <1>; 977 power-domains = <&rpmhpd SC7280_CX>; 978 }; 979 980 ipcc: mailbox@408000 { 981 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 982 reg = <0 0x00408000 0 0x1000>; 983 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 984 interrupt-controller; 985 #interrupt-cells = <3>; 986 #mbox-cells = <2>; 987 }; 988 989 qfprom: efuse@784000 { 990 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 991 reg = <0 0x00784000 0 0xa20>, 992 <0 0x00780000 0 0xa20>, 993 <0 0x00782000 0 0x120>, 994 <0 0x00786000 0 0x1fff>; 995 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 996 clock-names = "core"; 997 power-domains = <&rpmhpd SC7280_MX>; 998 #address-cells = <1>; 999 #size-cells = <1>; 1000 1001 gpu_speed_bin: gpu-speed-bin@1e9 { 1002 reg = <0x1e9 0x2>; 1003 bits = <5 8>; 1004 }; 1005 }; 1006 1007 sdhc_1: mmc@7c4000 { 1008 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 1009 pinctrl-names = "default", "sleep"; 1010 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 1011 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 1012 status = "disabled"; 1013 1014 reg = <0 0x007c4000 0 0x1000>, 1015 <0 0x007c5000 0 0x1000>; 1016 reg-names = "hc", "cqhci"; 1017 1018 iommus = <&apps_smmu 0xc0 0x0>; 1019 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 1020 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 1021 interrupt-names = "hc_irq", "pwr_irq"; 1022 1023 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1024 <&gcc GCC_SDCC1_APPS_CLK>, 1025 <&rpmhcc RPMH_CXO_CLK>; 1026 clock-names = "iface", "core", "xo"; 1027 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 1028 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 1029 interconnect-names = "sdhc-ddr","cpu-sdhc"; 1030 power-domains = <&rpmhpd SC7280_CX>; 1031 operating-points-v2 = <&sdhc1_opp_table>; 1032 1033 bus-width = <8>; 1034 supports-cqe; 1035 dma-coherent; 1036 1037 qcom,dll-config = <0x0007642c>; 1038 qcom,ddr-config = <0x80040868>; 1039 1040 mmc-ddr-1_8v; 1041 mmc-hs200-1_8v; 1042 mmc-hs400-1_8v; 1043 mmc-hs400-enhanced-strobe; 1044 1045 resets = <&gcc GCC_SDCC1_BCR>; 1046 1047 sdhc1_opp_table: opp-table { 1048 compatible = "operating-points-v2"; 1049 1050 opp-100000000 { 1051 opp-hz = /bits/ 64 <100000000>; 1052 required-opps = <&rpmhpd_opp_low_svs>; 1053 opp-peak-kBps = <1800000 400000>; 1054 opp-avg-kBps = <100000 0>; 1055 }; 1056 1057 opp-384000000 { 1058 opp-hz = /bits/ 64 <384000000>; 1059 required-opps = <&rpmhpd_opp_nom>; 1060 opp-peak-kBps = <5400000 1600000>; 1061 opp-avg-kBps = <390000 0>; 1062 }; 1063 }; 1064 }; 1065 1066 gpi_dma0: dma-controller@900000 { 1067 #dma-cells = <3>; 1068 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1069 reg = <0 0x00900000 0 0x60000>; 1070 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1071 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1072 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1073 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1074 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1075 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1076 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1077 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1078 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1079 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1080 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1081 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1082 dma-channels = <12>; 1083 dma-channel-mask = <0x7f>; 1084 iommus = <&apps_smmu 0x0136 0x0>; 1085 status = "disabled"; 1086 }; 1087 1088 qupv3_id_0: geniqup@9c0000 { 1089 compatible = "qcom,geni-se-qup"; 1090 reg = <0 0x009c0000 0 0x2000>; 1091 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1092 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1093 clock-names = "m-ahb", "s-ahb"; 1094 #address-cells = <2>; 1095 #size-cells = <2>; 1096 ranges; 1097 iommus = <&apps_smmu 0x123 0x0>; 1098 status = "disabled"; 1099 1100 i2c0: i2c@980000 { 1101 compatible = "qcom,geni-i2c"; 1102 reg = <0 0x00980000 0 0x4000>; 1103 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1104 clock-names = "se"; 1105 pinctrl-names = "default"; 1106 pinctrl-0 = <&qup_i2c0_data_clk>; 1107 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1111 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1112 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1113 interconnect-names = "qup-core", "qup-config", 1114 "qup-memory"; 1115 power-domains = <&rpmhpd SC7280_CX>; 1116 required-opps = <&rpmhpd_opp_low_svs>; 1117 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1118 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1119 dma-names = "tx", "rx"; 1120 status = "disabled"; 1121 }; 1122 1123 spi0: spi@980000 { 1124 compatible = "qcom,geni-spi"; 1125 reg = <0 0x00980000 0 0x4000>; 1126 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1127 clock-names = "se"; 1128 pinctrl-names = "default"; 1129 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1130 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1131 #address-cells = <1>; 1132 #size-cells = <0>; 1133 power-domains = <&rpmhpd SC7280_CX>; 1134 operating-points-v2 = <&qup_opp_table>; 1135 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1136 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1137 interconnect-names = "qup-core", "qup-config"; 1138 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1139 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1140 dma-names = "tx", "rx"; 1141 status = "disabled"; 1142 }; 1143 1144 uart0: serial@980000 { 1145 compatible = "qcom,geni-uart"; 1146 reg = <0 0x00980000 0 0x4000>; 1147 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1148 clock-names = "se"; 1149 pinctrl-names = "default"; 1150 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1151 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1152 power-domains = <&rpmhpd SC7280_CX>; 1153 operating-points-v2 = <&qup_opp_table>; 1154 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1155 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1156 interconnect-names = "qup-core", "qup-config"; 1157 status = "disabled"; 1158 }; 1159 1160 i2c1: i2c@984000 { 1161 compatible = "qcom,geni-i2c"; 1162 reg = <0 0x00984000 0 0x4000>; 1163 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1164 clock-names = "se"; 1165 pinctrl-names = "default"; 1166 pinctrl-0 = <&qup_i2c1_data_clk>; 1167 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1168 #address-cells = <1>; 1169 #size-cells = <0>; 1170 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1171 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1172 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1173 interconnect-names = "qup-core", "qup-config", 1174 "qup-memory"; 1175 power-domains = <&rpmhpd SC7280_CX>; 1176 required-opps = <&rpmhpd_opp_low_svs>; 1177 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1178 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1179 dma-names = "tx", "rx"; 1180 status = "disabled"; 1181 }; 1182 1183 spi1: spi@984000 { 1184 compatible = "qcom,geni-spi"; 1185 reg = <0 0x00984000 0 0x4000>; 1186 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1187 clock-names = "se"; 1188 pinctrl-names = "default"; 1189 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1190 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1191 #address-cells = <1>; 1192 #size-cells = <0>; 1193 power-domains = <&rpmhpd SC7280_CX>; 1194 operating-points-v2 = <&qup_opp_table>; 1195 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1196 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1197 interconnect-names = "qup-core", "qup-config"; 1198 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1199 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1200 dma-names = "tx", "rx"; 1201 status = "disabled"; 1202 }; 1203 1204 uart1: serial@984000 { 1205 compatible = "qcom,geni-uart"; 1206 reg = <0 0x00984000 0 0x4000>; 1207 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1208 clock-names = "se"; 1209 pinctrl-names = "default"; 1210 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1211 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1212 power-domains = <&rpmhpd SC7280_CX>; 1213 operating-points-v2 = <&qup_opp_table>; 1214 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1215 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1216 interconnect-names = "qup-core", "qup-config"; 1217 status = "disabled"; 1218 }; 1219 1220 i2c2: i2c@988000 { 1221 compatible = "qcom,geni-i2c"; 1222 reg = <0 0x00988000 0 0x4000>; 1223 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1224 clock-names = "se"; 1225 pinctrl-names = "default"; 1226 pinctrl-0 = <&qup_i2c2_data_clk>; 1227 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1228 #address-cells = <1>; 1229 #size-cells = <0>; 1230 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1231 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1232 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1233 interconnect-names = "qup-core", "qup-config", 1234 "qup-memory"; 1235 power-domains = <&rpmhpd SC7280_CX>; 1236 required-opps = <&rpmhpd_opp_low_svs>; 1237 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1238 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1239 dma-names = "tx", "rx"; 1240 status = "disabled"; 1241 }; 1242 1243 spi2: spi@988000 { 1244 compatible = "qcom,geni-spi"; 1245 reg = <0 0x00988000 0 0x4000>; 1246 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1247 clock-names = "se"; 1248 pinctrl-names = "default"; 1249 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1250 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1251 #address-cells = <1>; 1252 #size-cells = <0>; 1253 power-domains = <&rpmhpd SC7280_CX>; 1254 operating-points-v2 = <&qup_opp_table>; 1255 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1256 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1257 interconnect-names = "qup-core", "qup-config"; 1258 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1259 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1260 dma-names = "tx", "rx"; 1261 status = "disabled"; 1262 }; 1263 1264 uart2: serial@988000 { 1265 compatible = "qcom,geni-uart"; 1266 reg = <0 0x00988000 0 0x4000>; 1267 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1268 clock-names = "se"; 1269 pinctrl-names = "default"; 1270 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1271 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1272 power-domains = <&rpmhpd SC7280_CX>; 1273 operating-points-v2 = <&qup_opp_table>; 1274 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1275 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1276 interconnect-names = "qup-core", "qup-config"; 1277 status = "disabled"; 1278 }; 1279 1280 i2c3: i2c@98c000 { 1281 compatible = "qcom,geni-i2c"; 1282 reg = <0 0x0098c000 0 0x4000>; 1283 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1284 clock-names = "se"; 1285 pinctrl-names = "default"; 1286 pinctrl-0 = <&qup_i2c3_data_clk>; 1287 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1288 #address-cells = <1>; 1289 #size-cells = <0>; 1290 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1291 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1292 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1293 interconnect-names = "qup-core", "qup-config", 1294 "qup-memory"; 1295 power-domains = <&rpmhpd SC7280_CX>; 1296 required-opps = <&rpmhpd_opp_low_svs>; 1297 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1298 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1299 dma-names = "tx", "rx"; 1300 status = "disabled"; 1301 }; 1302 1303 spi3: spi@98c000 { 1304 compatible = "qcom,geni-spi"; 1305 reg = <0 0x0098c000 0 0x4000>; 1306 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1307 clock-names = "se"; 1308 pinctrl-names = "default"; 1309 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1310 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1311 #address-cells = <1>; 1312 #size-cells = <0>; 1313 power-domains = <&rpmhpd SC7280_CX>; 1314 operating-points-v2 = <&qup_opp_table>; 1315 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1316 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1317 interconnect-names = "qup-core", "qup-config"; 1318 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1319 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1320 dma-names = "tx", "rx"; 1321 status = "disabled"; 1322 }; 1323 1324 uart3: serial@98c000 { 1325 compatible = "qcom,geni-uart"; 1326 reg = <0 0x0098c000 0 0x4000>; 1327 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1328 clock-names = "se"; 1329 pinctrl-names = "default"; 1330 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1331 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1332 power-domains = <&rpmhpd SC7280_CX>; 1333 operating-points-v2 = <&qup_opp_table>; 1334 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1335 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1336 interconnect-names = "qup-core", "qup-config"; 1337 status = "disabled"; 1338 }; 1339 1340 i2c4: i2c@990000 { 1341 compatible = "qcom,geni-i2c"; 1342 reg = <0 0x00990000 0 0x4000>; 1343 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1344 clock-names = "se"; 1345 pinctrl-names = "default"; 1346 pinctrl-0 = <&qup_i2c4_data_clk>; 1347 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1348 #address-cells = <1>; 1349 #size-cells = <0>; 1350 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1351 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1352 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1353 interconnect-names = "qup-core", "qup-config", 1354 "qup-memory"; 1355 power-domains = <&rpmhpd SC7280_CX>; 1356 required-opps = <&rpmhpd_opp_low_svs>; 1357 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1358 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1359 dma-names = "tx", "rx"; 1360 status = "disabled"; 1361 }; 1362 1363 spi4: spi@990000 { 1364 compatible = "qcom,geni-spi"; 1365 reg = <0 0x00990000 0 0x4000>; 1366 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1367 clock-names = "se"; 1368 pinctrl-names = "default"; 1369 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1370 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1371 #address-cells = <1>; 1372 #size-cells = <0>; 1373 power-domains = <&rpmhpd SC7280_CX>; 1374 operating-points-v2 = <&qup_opp_table>; 1375 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1376 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1377 interconnect-names = "qup-core", "qup-config"; 1378 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1379 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1380 dma-names = "tx", "rx"; 1381 status = "disabled"; 1382 }; 1383 1384 uart4: serial@990000 { 1385 compatible = "qcom,geni-uart"; 1386 reg = <0 0x00990000 0 0x4000>; 1387 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1388 clock-names = "se"; 1389 pinctrl-names = "default"; 1390 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1391 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1392 power-domains = <&rpmhpd SC7280_CX>; 1393 operating-points-v2 = <&qup_opp_table>; 1394 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1395 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1396 interconnect-names = "qup-core", "qup-config"; 1397 status = "disabled"; 1398 }; 1399 1400 i2c5: i2c@994000 { 1401 compatible = "qcom,geni-i2c"; 1402 reg = <0 0x00994000 0 0x4000>; 1403 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1404 clock-names = "se"; 1405 pinctrl-names = "default"; 1406 pinctrl-0 = <&qup_i2c5_data_clk>; 1407 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1408 #address-cells = <1>; 1409 #size-cells = <0>; 1410 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1411 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1412 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1413 interconnect-names = "qup-core", "qup-config", 1414 "qup-memory"; 1415 power-domains = <&rpmhpd SC7280_CX>; 1416 required-opps = <&rpmhpd_opp_low_svs>; 1417 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1418 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1419 dma-names = "tx", "rx"; 1420 status = "disabled"; 1421 }; 1422 1423 spi5: spi@994000 { 1424 compatible = "qcom,geni-spi"; 1425 reg = <0 0x00994000 0 0x4000>; 1426 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1427 clock-names = "se"; 1428 pinctrl-names = "default"; 1429 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1430 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1431 #address-cells = <1>; 1432 #size-cells = <0>; 1433 power-domains = <&rpmhpd SC7280_CX>; 1434 operating-points-v2 = <&qup_opp_table>; 1435 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1436 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1437 interconnect-names = "qup-core", "qup-config"; 1438 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1439 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1440 dma-names = "tx", "rx"; 1441 status = "disabled"; 1442 }; 1443 1444 uart5: serial@994000 { 1445 compatible = "qcom,geni-debug-uart"; 1446 reg = <0 0x00994000 0 0x4000>; 1447 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1448 clock-names = "se"; 1449 pinctrl-names = "default"; 1450 pinctrl-0 = <&qup_uart5_tx>, <&qup_uart5_rx>; 1451 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1452 power-domains = <&rpmhpd SC7280_CX>; 1453 operating-points-v2 = <&qup_opp_table>; 1454 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1455 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1456 interconnect-names = "qup-core", "qup-config"; 1457 status = "disabled"; 1458 }; 1459 1460 i2c6: i2c@998000 { 1461 compatible = "qcom,geni-i2c"; 1462 reg = <0 0x00998000 0 0x4000>; 1463 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1464 clock-names = "se"; 1465 pinctrl-names = "default"; 1466 pinctrl-0 = <&qup_i2c6_data_clk>; 1467 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1468 #address-cells = <1>; 1469 #size-cells = <0>; 1470 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1471 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1472 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1473 interconnect-names = "qup-core", "qup-config", 1474 "qup-memory"; 1475 power-domains = <&rpmhpd SC7280_CX>; 1476 required-opps = <&rpmhpd_opp_low_svs>; 1477 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1478 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1479 dma-names = "tx", "rx"; 1480 status = "disabled"; 1481 }; 1482 1483 spi6: spi@998000 { 1484 compatible = "qcom,geni-spi"; 1485 reg = <0 0x00998000 0 0x4000>; 1486 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1487 clock-names = "se"; 1488 pinctrl-names = "default"; 1489 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1490 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1491 #address-cells = <1>; 1492 #size-cells = <0>; 1493 power-domains = <&rpmhpd SC7280_CX>; 1494 operating-points-v2 = <&qup_opp_table>; 1495 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1496 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1497 interconnect-names = "qup-core", "qup-config"; 1498 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1499 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1500 dma-names = "tx", "rx"; 1501 status = "disabled"; 1502 }; 1503 1504 uart6: serial@998000 { 1505 compatible = "qcom,geni-uart"; 1506 reg = <0 0x00998000 0 0x4000>; 1507 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1508 clock-names = "se"; 1509 pinctrl-names = "default"; 1510 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1511 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1512 power-domains = <&rpmhpd SC7280_CX>; 1513 operating-points-v2 = <&qup_opp_table>; 1514 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1515 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1516 interconnect-names = "qup-core", "qup-config"; 1517 status = "disabled"; 1518 }; 1519 1520 i2c7: i2c@99c000 { 1521 compatible = "qcom,geni-i2c"; 1522 reg = <0 0x0099c000 0 0x4000>; 1523 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1524 clock-names = "se"; 1525 pinctrl-names = "default"; 1526 pinctrl-0 = <&qup_i2c7_data_clk>; 1527 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1528 #address-cells = <1>; 1529 #size-cells = <0>; 1530 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1531 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1532 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1533 interconnect-names = "qup-core", "qup-config", 1534 "qup-memory"; 1535 power-domains = <&rpmhpd SC7280_CX>; 1536 required-opps = <&rpmhpd_opp_low_svs>; 1537 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1538 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1539 dma-names = "tx", "rx"; 1540 status = "disabled"; 1541 }; 1542 1543 spi7: spi@99c000 { 1544 compatible = "qcom,geni-spi"; 1545 reg = <0 0x0099c000 0 0x4000>; 1546 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1547 clock-names = "se"; 1548 pinctrl-names = "default"; 1549 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1550 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1551 #address-cells = <1>; 1552 #size-cells = <0>; 1553 power-domains = <&rpmhpd SC7280_CX>; 1554 operating-points-v2 = <&qup_opp_table>; 1555 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1556 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1557 interconnect-names = "qup-core", "qup-config"; 1558 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1559 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1560 dma-names = "tx", "rx"; 1561 status = "disabled"; 1562 }; 1563 1564 uart7: serial@99c000 { 1565 compatible = "qcom,geni-uart"; 1566 reg = <0 0x0099c000 0 0x4000>; 1567 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1568 clock-names = "se"; 1569 pinctrl-names = "default"; 1570 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1571 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1572 power-domains = <&rpmhpd SC7280_CX>; 1573 operating-points-v2 = <&qup_opp_table>; 1574 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1575 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1576 interconnect-names = "qup-core", "qup-config"; 1577 status = "disabled"; 1578 }; 1579 }; 1580 1581 gpi_dma1: dma-controller@a00000 { 1582 #dma-cells = <3>; 1583 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1584 reg = <0 0x00a00000 0 0x60000>; 1585 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1586 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1587 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1588 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1589 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1590 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1591 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1592 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1593 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1595 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1596 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1597 dma-channels = <12>; 1598 dma-channel-mask = <0x1e>; 1599 iommus = <&apps_smmu 0x56 0x0>; 1600 status = "disabled"; 1601 }; 1602 1603 qupv3_id_1: geniqup@ac0000 { 1604 compatible = "qcom,geni-se-qup"; 1605 reg = <0 0x00ac0000 0 0x2000>; 1606 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1607 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1608 clock-names = "m-ahb", "s-ahb"; 1609 #address-cells = <2>; 1610 #size-cells = <2>; 1611 ranges; 1612 iommus = <&apps_smmu 0x43 0x0>; 1613 status = "disabled"; 1614 1615 i2c8: i2c@a80000 { 1616 compatible = "qcom,geni-i2c"; 1617 reg = <0 0x00a80000 0 0x4000>; 1618 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1619 clock-names = "se"; 1620 pinctrl-names = "default"; 1621 pinctrl-0 = <&qup_i2c8_data_clk>; 1622 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1623 #address-cells = <1>; 1624 #size-cells = <0>; 1625 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1626 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1627 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1628 interconnect-names = "qup-core", "qup-config", 1629 "qup-memory"; 1630 power-domains = <&rpmhpd SC7280_CX>; 1631 required-opps = <&rpmhpd_opp_low_svs>; 1632 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1633 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1634 dma-names = "tx", "rx"; 1635 status = "disabled"; 1636 }; 1637 1638 spi8: spi@a80000 { 1639 compatible = "qcom,geni-spi"; 1640 reg = <0 0x00a80000 0 0x4000>; 1641 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1642 clock-names = "se"; 1643 pinctrl-names = "default"; 1644 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1645 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1646 #address-cells = <1>; 1647 #size-cells = <0>; 1648 power-domains = <&rpmhpd SC7280_CX>; 1649 operating-points-v2 = <&qup_opp_table>; 1650 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1651 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1652 interconnect-names = "qup-core", "qup-config"; 1653 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1654 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1655 dma-names = "tx", "rx"; 1656 status = "disabled"; 1657 }; 1658 1659 uart8: serial@a80000 { 1660 compatible = "qcom,geni-uart"; 1661 reg = <0 0x00a80000 0 0x4000>; 1662 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1663 clock-names = "se"; 1664 pinctrl-names = "default"; 1665 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1666 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1667 power-domains = <&rpmhpd SC7280_CX>; 1668 operating-points-v2 = <&qup_opp_table>; 1669 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1670 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1671 interconnect-names = "qup-core", "qup-config"; 1672 status = "disabled"; 1673 }; 1674 1675 i2c9: i2c@a84000 { 1676 compatible = "qcom,geni-i2c"; 1677 reg = <0 0x00a84000 0 0x4000>; 1678 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1679 clock-names = "se"; 1680 pinctrl-names = "default"; 1681 pinctrl-0 = <&qup_i2c9_data_clk>; 1682 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1683 #address-cells = <1>; 1684 #size-cells = <0>; 1685 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1686 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1687 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1688 interconnect-names = "qup-core", "qup-config", 1689 "qup-memory"; 1690 power-domains = <&rpmhpd SC7280_CX>; 1691 required-opps = <&rpmhpd_opp_low_svs>; 1692 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1693 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1694 dma-names = "tx", "rx"; 1695 status = "disabled"; 1696 }; 1697 1698 spi9: spi@a84000 { 1699 compatible = "qcom,geni-spi"; 1700 reg = <0 0x00a84000 0 0x4000>; 1701 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1702 clock-names = "se"; 1703 pinctrl-names = "default"; 1704 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1705 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1706 #address-cells = <1>; 1707 #size-cells = <0>; 1708 power-domains = <&rpmhpd SC7280_CX>; 1709 operating-points-v2 = <&qup_opp_table>; 1710 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1711 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1712 interconnect-names = "qup-core", "qup-config"; 1713 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1714 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1715 dma-names = "tx", "rx"; 1716 status = "disabled"; 1717 }; 1718 1719 uart9: serial@a84000 { 1720 compatible = "qcom,geni-uart"; 1721 reg = <0 0x00a84000 0 0x4000>; 1722 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1723 clock-names = "se"; 1724 pinctrl-names = "default"; 1725 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1726 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1727 power-domains = <&rpmhpd SC7280_CX>; 1728 operating-points-v2 = <&qup_opp_table>; 1729 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1730 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1731 interconnect-names = "qup-core", "qup-config"; 1732 status = "disabled"; 1733 }; 1734 1735 i2c10: i2c@a88000 { 1736 compatible = "qcom,geni-i2c"; 1737 reg = <0 0x00a88000 0 0x4000>; 1738 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1739 clock-names = "se"; 1740 pinctrl-names = "default"; 1741 pinctrl-0 = <&qup_i2c10_data_clk>; 1742 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1743 #address-cells = <1>; 1744 #size-cells = <0>; 1745 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1746 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1747 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1748 interconnect-names = "qup-core", "qup-config", 1749 "qup-memory"; 1750 power-domains = <&rpmhpd SC7280_CX>; 1751 required-opps = <&rpmhpd_opp_low_svs>; 1752 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1753 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1754 dma-names = "tx", "rx"; 1755 status = "disabled"; 1756 }; 1757 1758 spi10: spi@a88000 { 1759 compatible = "qcom,geni-spi"; 1760 reg = <0 0x00a88000 0 0x4000>; 1761 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1762 clock-names = "se"; 1763 pinctrl-names = "default"; 1764 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1765 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1766 #address-cells = <1>; 1767 #size-cells = <0>; 1768 power-domains = <&rpmhpd SC7280_CX>; 1769 operating-points-v2 = <&qup_opp_table>; 1770 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1771 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1772 interconnect-names = "qup-core", "qup-config"; 1773 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1774 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1775 dma-names = "tx", "rx"; 1776 status = "disabled"; 1777 }; 1778 1779 uart10: serial@a88000 { 1780 compatible = "qcom,geni-uart"; 1781 reg = <0 0x00a88000 0 0x4000>; 1782 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1783 clock-names = "se"; 1784 pinctrl-names = "default"; 1785 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1786 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1787 power-domains = <&rpmhpd SC7280_CX>; 1788 operating-points-v2 = <&qup_opp_table>; 1789 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1790 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1791 interconnect-names = "qup-core", "qup-config"; 1792 status = "disabled"; 1793 }; 1794 1795 i2c11: i2c@a8c000 { 1796 compatible = "qcom,geni-i2c"; 1797 reg = <0 0x00a8c000 0 0x4000>; 1798 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1799 clock-names = "se"; 1800 pinctrl-names = "default"; 1801 pinctrl-0 = <&qup_i2c11_data_clk>; 1802 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1803 #address-cells = <1>; 1804 #size-cells = <0>; 1805 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1806 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1807 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1808 interconnect-names = "qup-core", "qup-config", 1809 "qup-memory"; 1810 power-domains = <&rpmhpd SC7280_CX>; 1811 required-opps = <&rpmhpd_opp_low_svs>; 1812 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1813 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1814 dma-names = "tx", "rx"; 1815 status = "disabled"; 1816 }; 1817 1818 spi11: spi@a8c000 { 1819 compatible = "qcom,geni-spi"; 1820 reg = <0 0x00a8c000 0 0x4000>; 1821 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1822 clock-names = "se"; 1823 pinctrl-names = "default"; 1824 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1825 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1826 #address-cells = <1>; 1827 #size-cells = <0>; 1828 power-domains = <&rpmhpd SC7280_CX>; 1829 operating-points-v2 = <&qup_opp_table>; 1830 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1831 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1832 interconnect-names = "qup-core", "qup-config"; 1833 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1834 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1835 dma-names = "tx", "rx"; 1836 status = "disabled"; 1837 }; 1838 1839 uart11: serial@a8c000 { 1840 compatible = "qcom,geni-uart"; 1841 reg = <0 0x00a8c000 0 0x4000>; 1842 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1843 clock-names = "se"; 1844 pinctrl-names = "default"; 1845 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1846 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1847 power-domains = <&rpmhpd SC7280_CX>; 1848 operating-points-v2 = <&qup_opp_table>; 1849 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1850 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1851 interconnect-names = "qup-core", "qup-config"; 1852 status = "disabled"; 1853 }; 1854 1855 i2c12: i2c@a90000 { 1856 compatible = "qcom,geni-i2c"; 1857 reg = <0 0x00a90000 0 0x4000>; 1858 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1859 clock-names = "se"; 1860 pinctrl-names = "default"; 1861 pinctrl-0 = <&qup_i2c12_data_clk>; 1862 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1863 #address-cells = <1>; 1864 #size-cells = <0>; 1865 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1866 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1867 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1868 interconnect-names = "qup-core", "qup-config", 1869 "qup-memory"; 1870 power-domains = <&rpmhpd SC7280_CX>; 1871 required-opps = <&rpmhpd_opp_low_svs>; 1872 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1873 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1874 dma-names = "tx", "rx"; 1875 status = "disabled"; 1876 }; 1877 1878 spi12: spi@a90000 { 1879 compatible = "qcom,geni-spi"; 1880 reg = <0 0x00a90000 0 0x4000>; 1881 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1882 clock-names = "se"; 1883 pinctrl-names = "default"; 1884 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1885 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1886 #address-cells = <1>; 1887 #size-cells = <0>; 1888 power-domains = <&rpmhpd SC7280_CX>; 1889 operating-points-v2 = <&qup_opp_table>; 1890 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1891 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1892 interconnect-names = "qup-core", "qup-config"; 1893 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1894 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1895 dma-names = "tx", "rx"; 1896 status = "disabled"; 1897 }; 1898 1899 uart12: serial@a90000 { 1900 compatible = "qcom,geni-uart"; 1901 reg = <0 0x00a90000 0 0x4000>; 1902 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1903 clock-names = "se"; 1904 pinctrl-names = "default"; 1905 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1906 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1907 power-domains = <&rpmhpd SC7280_CX>; 1908 operating-points-v2 = <&qup_opp_table>; 1909 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1910 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1911 interconnect-names = "qup-core", "qup-config"; 1912 status = "disabled"; 1913 }; 1914 1915 i2c13: i2c@a94000 { 1916 compatible = "qcom,geni-i2c"; 1917 reg = <0 0x00a94000 0 0x4000>; 1918 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1919 clock-names = "se"; 1920 pinctrl-names = "default"; 1921 pinctrl-0 = <&qup_i2c13_data_clk>; 1922 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1923 #address-cells = <1>; 1924 #size-cells = <0>; 1925 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1926 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1927 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1928 interconnect-names = "qup-core", "qup-config", 1929 "qup-memory"; 1930 power-domains = <&rpmhpd SC7280_CX>; 1931 required-opps = <&rpmhpd_opp_low_svs>; 1932 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1933 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1934 dma-names = "tx", "rx"; 1935 status = "disabled"; 1936 }; 1937 1938 spi13: spi@a94000 { 1939 compatible = "qcom,geni-spi"; 1940 reg = <0 0x00a94000 0 0x4000>; 1941 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1942 clock-names = "se"; 1943 pinctrl-names = "default"; 1944 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1945 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1946 #address-cells = <1>; 1947 #size-cells = <0>; 1948 power-domains = <&rpmhpd SC7280_CX>; 1949 operating-points-v2 = <&qup_opp_table>; 1950 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1951 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1952 interconnect-names = "qup-core", "qup-config"; 1953 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1954 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1955 dma-names = "tx", "rx"; 1956 status = "disabled"; 1957 }; 1958 1959 uart13: serial@a94000 { 1960 compatible = "qcom,geni-uart"; 1961 reg = <0 0x00a94000 0 0x4000>; 1962 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1963 clock-names = "se"; 1964 pinctrl-names = "default"; 1965 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1966 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1967 power-domains = <&rpmhpd SC7280_CX>; 1968 operating-points-v2 = <&qup_opp_table>; 1969 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1970 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1971 interconnect-names = "qup-core", "qup-config"; 1972 status = "disabled"; 1973 }; 1974 1975 i2c14: i2c@a98000 { 1976 compatible = "qcom,geni-i2c"; 1977 reg = <0 0x00a98000 0 0x4000>; 1978 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1979 clock-names = "se"; 1980 pinctrl-names = "default"; 1981 pinctrl-0 = <&qup_i2c14_data_clk>; 1982 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1983 #address-cells = <1>; 1984 #size-cells = <0>; 1985 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1986 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1987 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1988 interconnect-names = "qup-core", "qup-config", 1989 "qup-memory"; 1990 power-domains = <&rpmhpd SC7280_CX>; 1991 required-opps = <&rpmhpd_opp_low_svs>; 1992 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1993 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1994 dma-names = "tx", "rx"; 1995 status = "disabled"; 1996 }; 1997 1998 spi14: spi@a98000 { 1999 compatible = "qcom,geni-spi"; 2000 reg = <0 0x00a98000 0 0x4000>; 2001 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2002 clock-names = "se"; 2003 pinctrl-names = "default"; 2004 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 2005 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 2006 #address-cells = <1>; 2007 #size-cells = <0>; 2008 power-domains = <&rpmhpd SC7280_CX>; 2009 operating-points-v2 = <&qup_opp_table>; 2010 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2011 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2012 interconnect-names = "qup-core", "qup-config"; 2013 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2014 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2015 dma-names = "tx", "rx"; 2016 status = "disabled"; 2017 }; 2018 2019 uart14: serial@a98000 { 2020 compatible = "qcom,geni-uart"; 2021 reg = <0 0x00a98000 0 0x4000>; 2022 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2023 clock-names = "se"; 2024 pinctrl-names = "default"; 2025 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 2026 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 2027 power-domains = <&rpmhpd SC7280_CX>; 2028 operating-points-v2 = <&qup_opp_table>; 2029 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2030 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2031 interconnect-names = "qup-core", "qup-config"; 2032 status = "disabled"; 2033 }; 2034 2035 i2c15: i2c@a9c000 { 2036 compatible = "qcom,geni-i2c"; 2037 reg = <0 0x00a9c000 0 0x4000>; 2038 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2039 clock-names = "se"; 2040 pinctrl-names = "default"; 2041 pinctrl-0 = <&qup_i2c15_data_clk>; 2042 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2043 #address-cells = <1>; 2044 #size-cells = <0>; 2045 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2046 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 2047 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2048 interconnect-names = "qup-core", "qup-config", 2049 "qup-memory"; 2050 power-domains = <&rpmhpd SC7280_CX>; 2051 required-opps = <&rpmhpd_opp_low_svs>; 2052 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2053 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2054 dma-names = "tx", "rx"; 2055 status = "disabled"; 2056 }; 2057 2058 spi15: spi@a9c000 { 2059 compatible = "qcom,geni-spi"; 2060 reg = <0 0x00a9c000 0 0x4000>; 2061 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2062 clock-names = "se"; 2063 pinctrl-names = "default"; 2064 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 2065 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2066 #address-cells = <1>; 2067 #size-cells = <0>; 2068 power-domains = <&rpmhpd SC7280_CX>; 2069 operating-points-v2 = <&qup_opp_table>; 2070 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2071 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2072 interconnect-names = "qup-core", "qup-config"; 2073 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2074 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2075 dma-names = "tx", "rx"; 2076 status = "disabled"; 2077 }; 2078 2079 uart15: serial@a9c000 { 2080 compatible = "qcom,geni-uart"; 2081 reg = <0 0x00a9c000 0 0x4000>; 2082 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2083 clock-names = "se"; 2084 pinctrl-names = "default"; 2085 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 2086 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2087 power-domains = <&rpmhpd SC7280_CX>; 2088 operating-points-v2 = <&qup_opp_table>; 2089 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2090 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2091 interconnect-names = "qup-core", "qup-config"; 2092 status = "disabled"; 2093 }; 2094 }; 2095 2096 rng: rng@10d3000 { 2097 compatible = "qcom,sc7280-trng", "qcom,trng"; 2098 reg = <0 0x010d3000 0 0x1000>; 2099 }; 2100 2101 cnoc2: interconnect@1500000 { 2102 reg = <0 0x01500000 0 0x1000>; 2103 compatible = "qcom,sc7280-cnoc2"; 2104 #interconnect-cells = <2>; 2105 qcom,bcm-voters = <&apps_bcm_voter>; 2106 }; 2107 2108 cnoc3: interconnect@1502000 { 2109 reg = <0 0x01502000 0 0x1000>; 2110 compatible = "qcom,sc7280-cnoc3"; 2111 #interconnect-cells = <2>; 2112 qcom,bcm-voters = <&apps_bcm_voter>; 2113 }; 2114 2115 mc_virt: interconnect@1580000 { 2116 reg = <0 0x01580000 0 0x4>; 2117 compatible = "qcom,sc7280-mc-virt"; 2118 #interconnect-cells = <2>; 2119 qcom,bcm-voters = <&apps_bcm_voter>; 2120 }; 2121 2122 system_noc: interconnect@1680000 { 2123 reg = <0 0x01680000 0 0x15480>; 2124 compatible = "qcom,sc7280-system-noc"; 2125 #interconnect-cells = <2>; 2126 qcom,bcm-voters = <&apps_bcm_voter>; 2127 }; 2128 2129 aggre1_noc: interconnect@16e0000 { 2130 compatible = "qcom,sc7280-aggre1-noc"; 2131 reg = <0 0x016e0000 0 0x1c080>; 2132 #interconnect-cells = <2>; 2133 qcom,bcm-voters = <&apps_bcm_voter>; 2134 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2135 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 2136 }; 2137 2138 aggre2_noc: interconnect@1700000 { 2139 reg = <0 0x01700000 0 0x2b080>; 2140 compatible = "qcom,sc7280-aggre2-noc"; 2141 #interconnect-cells = <2>; 2142 qcom,bcm-voters = <&apps_bcm_voter>; 2143 clocks = <&rpmhcc RPMH_IPA_CLK>; 2144 }; 2145 2146 mmss_noc: interconnect@1740000 { 2147 reg = <0 0x01740000 0 0x1e080>; 2148 compatible = "qcom,sc7280-mmss-noc"; 2149 #interconnect-cells = <2>; 2150 qcom,bcm-voters = <&apps_bcm_voter>; 2151 }; 2152 2153 wifi: wifi@17a10040 { 2154 compatible = "qcom,wcn6750-wifi"; 2155 reg = <0 0x17a10040 0 0x0>; 2156 iommus = <&apps_smmu 0x1c00 0x1>; 2157 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 2158 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 2159 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 2160 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 2161 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 2162 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 2163 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 2164 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 2165 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 2166 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 2167 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 2168 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 2169 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 2170 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 2171 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 2172 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 2173 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 2174 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 2175 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 2176 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 2177 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 2178 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 2179 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 2180 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 2181 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 2182 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 2183 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 2184 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 2185 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2186 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2187 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2188 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2189 qcom,rproc = <&remoteproc_wpss>; 2190 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2191 status = "disabled"; 2192 qcom,smem-states = <&wlan_smp2p_out 0>; 2193 qcom,smem-state-names = "wlan-smp2p-out"; 2194 }; 2195 2196 pcie1: pcie@1c08000 { 2197 compatible = "qcom,pcie-sc7280"; 2198 reg = <0 0x01c08000 0 0x3000>, 2199 <0 0x40000000 0 0xf1d>, 2200 <0 0x40000f20 0 0xa8>, 2201 <0 0x40001000 0 0x1000>, 2202 <0 0x40100000 0 0x100000>; 2203 2204 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2205 device_type = "pci"; 2206 linux,pci-domain = <1>; 2207 bus-range = <0x00 0xff>; 2208 num-lanes = <2>; 2209 2210 #address-cells = <3>; 2211 #size-cells = <2>; 2212 2213 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2214 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2215 2216 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2217 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2218 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2219 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2220 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2221 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2222 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2223 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 2224 interrupt-names = "msi0", "msi1", "msi2", "msi3", 2225 "msi4", "msi5", "msi6", "msi7"; 2226 #interrupt-cells = <1>; 2227 interrupt-map-mask = <0 0 0 0x7>; 2228 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2229 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2230 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2231 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2232 2233 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2234 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2235 <&pcie1_phy>, 2236 <&rpmhcc RPMH_CXO_CLK>, 2237 <&gcc GCC_PCIE_1_AUX_CLK>, 2238 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2239 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2240 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2241 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2242 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2243 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2244 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2245 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2246 2247 clock-names = "pipe", 2248 "pipe_mux", 2249 "phy_pipe", 2250 "ref", 2251 "aux", 2252 "cfg", 2253 "bus_master", 2254 "bus_slave", 2255 "slave_q2a", 2256 "tbu", 2257 "ddrss_sf_tbu", 2258 "aggre0", 2259 "aggre1"; 2260 2261 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2262 assigned-clock-rates = <19200000>; 2263 2264 resets = <&gcc GCC_PCIE_1_BCR>; 2265 reset-names = "pci"; 2266 2267 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2268 2269 phys = <&pcie1_phy>; 2270 phy-names = "pciephy"; 2271 2272 pinctrl-names = "default"; 2273 pinctrl-0 = <&pcie1_clkreq_n>; 2274 2275 dma-coherent; 2276 2277 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2278 <0x100 &apps_smmu 0x1c81 0x1>; 2279 2280 status = "disabled"; 2281 2282 pcie@0 { 2283 device_type = "pci"; 2284 reg = <0x0 0x0 0x0 0x0 0x0>; 2285 bus-range = <0x01 0xff>; 2286 2287 #address-cells = <3>; 2288 #size-cells = <2>; 2289 ranges; 2290 }; 2291 }; 2292 2293 pcie1_phy: phy@1c0e000 { 2294 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2295 reg = <0 0x01c0e000 0 0x1000>; 2296 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2297 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2298 <&gcc GCC_PCIE_CLKREF_EN>, 2299 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, 2300 <&gcc GCC_PCIE_1_PIPE_CLK>; 2301 clock-names = "aux", 2302 "cfg_ahb", 2303 "ref", 2304 "refgen", 2305 "pipe"; 2306 2307 clock-output-names = "pcie_1_pipe_clk"; 2308 #clock-cells = <0>; 2309 2310 #phy-cells = <0>; 2311 2312 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2313 reset-names = "phy"; 2314 2315 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2316 assigned-clock-rates = <100000000>; 2317 2318 status = "disabled"; 2319 }; 2320 2321 ufs_mem_hc: ufs@1d84000 { 2322 compatible = "qcom,sc7280-ufshc", "qcom,ufshc", 2323 "jedec,ufs-2.0"; 2324 reg = <0x0 0x01d84000 0x0 0x3000>; 2325 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2326 phys = <&ufs_mem_phy>; 2327 phy-names = "ufsphy"; 2328 lanes-per-direction = <2>; 2329 #reset-cells = <1>; 2330 resets = <&gcc GCC_UFS_PHY_BCR>; 2331 reset-names = "rst"; 2332 2333 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 2334 required-opps = <&rpmhpd_opp_nom>; 2335 2336 iommus = <&apps_smmu 0x80 0x0>; 2337 dma-coherent; 2338 2339 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2340 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2341 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2342 &cnoc2 SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 2343 interconnect-names = "ufs-ddr", "cpu-ufs"; 2344 2345 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2346 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2347 <&gcc GCC_UFS_PHY_AHB_CLK>, 2348 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2349 <&rpmhcc RPMH_CXO_CLK>, 2350 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2351 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2352 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2353 clock-names = "core_clk", 2354 "bus_aggr_clk", 2355 "iface_clk", 2356 "core_clk_unipro", 2357 "ref_clk", 2358 "tx_lane0_sync_clk", 2359 "rx_lane0_sync_clk", 2360 "rx_lane1_sync_clk"; 2361 freq-table-hz = 2362 <75000000 300000000>, 2363 <0 0>, 2364 <0 0>, 2365 <75000000 300000000>, 2366 <0 0>, 2367 <0 0>, 2368 <0 0>, 2369 <0 0>; 2370 qcom,ice = <&ice>; 2371 2372 status = "disabled"; 2373 }; 2374 2375 ufs_mem_phy: phy@1d87000 { 2376 compatible = "qcom,sc7280-qmp-ufs-phy"; 2377 reg = <0x0 0x01d87000 0x0 0xe00>; 2378 clocks = <&rpmhcc RPMH_CXO_CLK>, 2379 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2380 <&gcc GCC_UFS_1_CLKREF_EN>; 2381 clock-names = "ref", "ref_aux", "qref"; 2382 2383 power-domains = <&rpmhpd SC7280_MX>; 2384 2385 resets = <&ufs_mem_hc 0>; 2386 reset-names = "ufsphy"; 2387 2388 #clock-cells = <1>; 2389 #phy-cells = <0>; 2390 2391 status = "disabled"; 2392 }; 2393 2394 ice: crypto@1d88000 { 2395 compatible = "qcom,sc7280-inline-crypto-engine", 2396 "qcom,inline-crypto-engine"; 2397 reg = <0 0x01d88000 0 0x8000>; 2398 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2399 }; 2400 2401 cryptobam: dma-controller@1dc4000 { 2402 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2403 reg = <0x0 0x01dc4000 0x0 0x28000>; 2404 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2405 #dma-cells = <1>; 2406 iommus = <&apps_smmu 0x4e4 0x0011>, 2407 <&apps_smmu 0x4e6 0x0011>; 2408 qcom,ee = <0>; 2409 qcom,controlled-remotely; 2410 num-channels = <16>; 2411 qcom,num-ees = <4>; 2412 }; 2413 2414 crypto: crypto@1dfa000 { 2415 compatible = "qcom,sc7280-qce", "qcom,sm8150-qce", "qcom,qce"; 2416 reg = <0x0 0x01dfa000 0x0 0x6000>; 2417 dmas = <&cryptobam 4>, <&cryptobam 5>; 2418 dma-names = "rx", "tx"; 2419 iommus = <&apps_smmu 0x4e4 0x0011>, 2420 <&apps_smmu 0x4e4 0x0011>; 2421 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 2422 interconnect-names = "memory"; 2423 }; 2424 2425 ipa: ipa@1e40000 { 2426 compatible = "qcom,sc7280-ipa"; 2427 2428 iommus = <&apps_smmu 0x480 0x0>, 2429 <&apps_smmu 0x482 0x0>; 2430 reg = <0 0x01e40000 0 0x8000>, 2431 <0 0x01e50000 0 0x4ad0>, 2432 <0 0x01e04000 0 0x23000>; 2433 reg-names = "ipa-reg", 2434 "ipa-shared", 2435 "gsi"; 2436 2437 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2438 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2439 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2440 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2441 interrupt-names = "ipa", 2442 "gsi", 2443 "ipa-clock-query", 2444 "ipa-setup-ready"; 2445 2446 clocks = <&rpmhcc RPMH_IPA_CLK>; 2447 clock-names = "core"; 2448 2449 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2450 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2451 interconnect-names = "memory", 2452 "config"; 2453 2454 qcom,qmp = <&aoss_qmp>; 2455 2456 qcom,smem-states = <&ipa_smp2p_out 0>, 2457 <&ipa_smp2p_out 1>; 2458 qcom,smem-state-names = "ipa-clock-enabled-valid", 2459 "ipa-clock-enabled"; 2460 2461 status = "disabled"; 2462 }; 2463 2464 tcsr_mutex: hwlock@1f40000 { 2465 compatible = "qcom,tcsr-mutex"; 2466 reg = <0 0x01f40000 0 0x20000>; 2467 #hwlock-cells = <1>; 2468 }; 2469 2470 tcsr_1: syscon@1f60000 { 2471 compatible = "qcom,sc7280-tcsr", "syscon"; 2472 reg = <0 0x01f60000 0 0x20000>; 2473 }; 2474 2475 tcsr_2: syscon@1fc0000 { 2476 compatible = "qcom,sc7280-tcsr", "syscon"; 2477 reg = <0 0x01fc0000 0 0x30000>; 2478 }; 2479 2480 lpasscc: lpasscc@3000000 { 2481 compatible = "qcom,sc7280-lpasscc"; 2482 reg = <0 0x03000000 0 0x40>, 2483 <0 0x03c04000 0 0x4>; 2484 reg-names = "qdsp6ss", "top_cc"; 2485 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2486 clock-names = "iface"; 2487 #clock-cells = <1>; 2488 status = "reserved"; /* Owned by ADSP firmware */ 2489 }; 2490 2491 lpass_rx_macro: codec@3200000 { 2492 compatible = "qcom,sc7280-lpass-rx-macro"; 2493 reg = <0 0x03200000 0 0x1000>; 2494 2495 pinctrl-names = "default"; 2496 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2497 2498 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2499 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2500 <&lpass_va_macro>; 2501 clock-names = "mclk", "npl", "fsgen"; 2502 2503 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2504 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2505 power-domain-names = "macro", "dcodec"; 2506 2507 #clock-cells = <0>; 2508 #sound-dai-cells = <1>; 2509 2510 status = "disabled"; 2511 }; 2512 2513 swr0: soundwire@3210000 { 2514 compatible = "qcom,soundwire-v1.6.0"; 2515 reg = <0 0x03210000 0 0x2000>; 2516 2517 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2518 clocks = <&lpass_rx_macro>; 2519 clock-names = "iface"; 2520 2521 qcom,din-ports = <0>; 2522 qcom,dout-ports = <5>; 2523 2524 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2525 reset-names = "swr_audio_cgcr"; 2526 2527 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2528 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2529 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2530 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2531 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2532 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2533 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2534 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2535 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2536 2537 #sound-dai-cells = <1>; 2538 #address-cells = <2>; 2539 #size-cells = <0>; 2540 2541 status = "disabled"; 2542 }; 2543 2544 lpass_tx_macro: codec@3220000 { 2545 compatible = "qcom,sc7280-lpass-tx-macro"; 2546 reg = <0 0x03220000 0 0x1000>; 2547 2548 pinctrl-names = "default"; 2549 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2550 2551 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2552 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2553 <&lpass_va_macro>; 2554 clock-names = "mclk", "npl", "fsgen"; 2555 2556 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2557 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2558 power-domain-names = "macro", "dcodec"; 2559 2560 #clock-cells = <0>; 2561 #sound-dai-cells = <1>; 2562 2563 status = "disabled"; 2564 }; 2565 2566 swr1: soundwire@3230000 { 2567 compatible = "qcom,soundwire-v1.6.0"; 2568 reg = <0 0x03230000 0 0x2000>; 2569 2570 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2571 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2572 clocks = <&lpass_tx_macro>; 2573 clock-names = "iface"; 2574 2575 qcom,din-ports = <3>; 2576 qcom,dout-ports = <0>; 2577 2578 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2579 reset-names = "swr_audio_cgcr"; 2580 2581 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2582 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2583 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2584 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2585 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2586 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2587 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2588 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2589 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2590 2591 #sound-dai-cells = <1>; 2592 #address-cells = <2>; 2593 #size-cells = <0>; 2594 2595 status = "disabled"; 2596 }; 2597 2598 lpass_audiocc: clock-controller@3300000 { 2599 compatible = "qcom,sc7280-lpassaudiocc"; 2600 reg = <0 0x03300000 0 0x30000>, 2601 <0 0x032a9000 0 0x1000>; 2602 clocks = <&rpmhcc RPMH_CXO_CLK>, 2603 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2604 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2605 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2606 #clock-cells = <1>; 2607 #power-domain-cells = <1>; 2608 #reset-cells = <1>; 2609 }; 2610 2611 lpass_va_macro: codec@3370000 { 2612 compatible = "qcom,sc7280-lpass-va-macro"; 2613 reg = <0 0x03370000 0 0x1000>; 2614 2615 pinctrl-names = "default"; 2616 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; 2617 2618 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2619 clock-names = "mclk"; 2620 2621 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2622 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2623 power-domain-names = "macro", "dcodec"; 2624 2625 #clock-cells = <0>; 2626 #sound-dai-cells = <1>; 2627 2628 status = "disabled"; 2629 }; 2630 2631 lpass_aon: clock-controller@3380000 { 2632 compatible = "qcom,sc7280-lpassaoncc"; 2633 reg = <0 0x03380000 0 0x30000>; 2634 clocks = <&rpmhcc RPMH_CXO_CLK>, 2635 <&rpmhcc RPMH_CXO_CLK_A>, 2636 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2637 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2638 #clock-cells = <1>; 2639 #power-domain-cells = <1>; 2640 status = "reserved"; /* Owned by ADSP firmware */ 2641 }; 2642 2643 lpass_core: clock-controller@3900000 { 2644 compatible = "qcom,sc7280-lpasscorecc"; 2645 reg = <0 0x03900000 0 0x50000>; 2646 clocks = <&rpmhcc RPMH_CXO_CLK>; 2647 clock-names = "bi_tcxo"; 2648 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2649 #clock-cells = <1>; 2650 #power-domain-cells = <1>; 2651 status = "reserved"; /* Owned by ADSP firmware */ 2652 }; 2653 2654 lpass_cpu: audio@3987000 { 2655 compatible = "qcom,sc7280-lpass-cpu"; 2656 2657 reg = <0 0x03987000 0 0x68000>, 2658 <0 0x03b00000 0 0x29000>, 2659 <0 0x03260000 0 0xc000>, 2660 <0 0x03280000 0 0x29000>, 2661 <0 0x03340000 0 0x29000>, 2662 <0 0x0336c000 0 0x3000>; 2663 reg-names = "lpass-hdmiif", 2664 "lpass-lpaif", 2665 "lpass-rxtx-cdc-dma-lpm", 2666 "lpass-rxtx-lpaif", 2667 "lpass-va-lpaif", 2668 "lpass-va-cdc-dma-lpm"; 2669 2670 iommus = <&apps_smmu 0x1820 0>, 2671 <&apps_smmu 0x1821 0>, 2672 <&apps_smmu 0x1832 0>; 2673 2674 power-domains = <&rpmhpd SC7280_LCX>; 2675 power-domain-names = "lcx"; 2676 required-opps = <&rpmhpd_opp_nom>; 2677 2678 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2679 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2680 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2681 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2682 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2683 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2684 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2685 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2686 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2687 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2688 clock-names = "aon_cc_audio_hm_h", 2689 "audio_cc_ext_mclk0", 2690 "core_cc_sysnoc_mport_core", 2691 "core_cc_ext_if0_ibit", 2692 "core_cc_ext_if1_ibit", 2693 "audio_cc_codec_mem", 2694 "audio_cc_codec_mem0", 2695 "audio_cc_codec_mem1", 2696 "audio_cc_codec_mem2", 2697 "aon_cc_va_mem0"; 2698 2699 #sound-dai-cells = <1>; 2700 #address-cells = <1>; 2701 #size-cells = <0>; 2702 2703 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2704 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2705 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2706 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2707 interrupt-names = "lpass-irq-lpaif", 2708 "lpass-irq-hdmi", 2709 "lpass-irq-vaif", 2710 "lpass-irq-rxtxif"; 2711 2712 status = "disabled"; 2713 }; 2714 2715 slimbam: dma-controller@3a84000 { 2716 compatible = "qcom,bam-v1.7.0"; 2717 reg = <0 0x03a84000 0 0x20000>; 2718 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 2719 #dma-cells = <1>; 2720 qcom,controlled-remotely; 2721 num-channels = <31>; 2722 qcom,ee = <1>; 2723 qcom,num-ees = <2>; 2724 iommus = <&apps_smmu 0x1826 0x0>; 2725 status = "disabled"; 2726 }; 2727 2728 slim: slim-ngd@3ac0000 { 2729 compatible = "qcom,slim-ngd-v1.5.0"; 2730 reg = <0 0x03ac0000 0 0x2c000>; 2731 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 2732 dmas = <&slimbam 3>, <&slimbam 4>; 2733 dma-names = "rx", "tx"; 2734 iommus = <&apps_smmu 0x1826 0x0>; 2735 #address-cells = <1>; 2736 #size-cells = <0>; 2737 status = "disabled"; 2738 }; 2739 2740 lpass_hm: clock-controller@3c00000 { 2741 compatible = "qcom,sc7280-lpasshm"; 2742 reg = <0 0x03c00000 0 0x28>; 2743 clocks = <&rpmhcc RPMH_CXO_CLK>; 2744 clock-names = "bi_tcxo"; 2745 #clock-cells = <1>; 2746 #power-domain-cells = <1>; 2747 status = "reserved"; /* Owned by ADSP firmware */ 2748 }; 2749 2750 lpass_ag_noc: interconnect@3c40000 { 2751 reg = <0 0x03c40000 0 0xf080>; 2752 compatible = "qcom,sc7280-lpass-ag-noc"; 2753 #interconnect-cells = <2>; 2754 qcom,bcm-voters = <&apps_bcm_voter>; 2755 }; 2756 2757 lpass_tlmm: pinctrl@33c0000 { 2758 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2759 reg = <0 0x033c0000 0x0 0x20000>, 2760 <0 0x03550000 0x0 0x10000>; 2761 gpio-controller; 2762 #gpio-cells = <2>; 2763 gpio-ranges = <&lpass_tlmm 0 0 15>; 2764 2765 lpass_dmic01_clk: dmic01-clk-state { 2766 pins = "gpio6"; 2767 function = "dmic1_clk"; 2768 }; 2769 2770 lpass_dmic01_data: dmic01-data-state { 2771 pins = "gpio7"; 2772 function = "dmic1_data"; 2773 }; 2774 2775 lpass_dmic23_clk: dmic23-clk-state { 2776 pins = "gpio8"; 2777 function = "dmic2_clk"; 2778 }; 2779 2780 lpass_dmic23_data: dmic23-data-state { 2781 pins = "gpio9"; 2782 function = "dmic2_data"; 2783 }; 2784 2785 lpass_rx_swr_clk: rx-swr-clk-state { 2786 pins = "gpio3"; 2787 function = "swr_rx_clk"; 2788 }; 2789 2790 lpass_rx_swr_data: rx-swr-data-state { 2791 pins = "gpio4", "gpio5"; 2792 function = "swr_rx_data"; 2793 }; 2794 2795 lpass_tx_swr_clk: tx-swr-clk-state { 2796 pins = "gpio0"; 2797 function = "swr_tx_clk"; 2798 }; 2799 2800 lpass_tx_swr_data: tx-swr-data-state { 2801 pins = "gpio1", "gpio2", "gpio14"; 2802 function = "swr_tx_data"; 2803 }; 2804 }; 2805 2806 gpu: gpu@3d00000 { 2807 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2808 reg = <0 0x03d00000 0 0x40000>, 2809 <0 0x03d9e000 0 0x1000>, 2810 <0 0x03d61000 0 0x800>; 2811 reg-names = "kgsl_3d0_reg_memory", 2812 "cx_mem", 2813 "cx_dbgc"; 2814 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2815 iommus = <&adreno_smmu 0 0x400>, 2816 <&adreno_smmu 1 0x400>; 2817 operating-points-v2 = <&gpu_opp_table>; 2818 qcom,gmu = <&gmu>; 2819 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2820 interconnect-names = "gfx-mem"; 2821 #cooling-cells = <2>; 2822 2823 nvmem-cells = <&gpu_speed_bin>; 2824 nvmem-cell-names = "speed_bin"; 2825 2826 gpu_zap_shader: zap-shader { 2827 memory-region = <&gpu_zap_mem>; 2828 }; 2829 2830 gpu_opp_table: opp-table { 2831 compatible = "operating-points-v2"; 2832 2833 opp-315000000 { 2834 opp-hz = /bits/ 64 <315000000>; 2835 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2836 opp-peak-kBps = <1804000>; 2837 opp-supported-hw = <0x07>; 2838 }; 2839 2840 opp-450000000 { 2841 opp-hz = /bits/ 64 <450000000>; 2842 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2843 opp-peak-kBps = <4068000>; 2844 opp-supported-hw = <0x07>; 2845 }; 2846 2847 /* Only applicable for SKUs which has 550Mhz as Fmax */ 2848 opp-550000000-0 { 2849 opp-hz = /bits/ 64 <550000000>; 2850 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2851 opp-peak-kBps = <8368000>; 2852 opp-supported-hw = <0x01>; 2853 }; 2854 2855 opp-550000000-1 { 2856 opp-hz = /bits/ 64 <550000000>; 2857 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2858 opp-peak-kBps = <6832000>; 2859 opp-supported-hw = <0x06>; 2860 }; 2861 2862 opp-608000000 { 2863 opp-hz = /bits/ 64 <608000000>; 2864 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2865 opp-peak-kBps = <8368000>; 2866 opp-supported-hw = <0x06>; 2867 }; 2868 2869 opp-700000000 { 2870 opp-hz = /bits/ 64 <700000000>; 2871 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2872 opp-peak-kBps = <8532000>; 2873 opp-supported-hw = <0x06>; 2874 }; 2875 2876 opp-812000000 { 2877 opp-hz = /bits/ 64 <812000000>; 2878 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2879 opp-peak-kBps = <8532000>; 2880 opp-supported-hw = <0x06>; 2881 }; 2882 2883 opp-840000000 { 2884 opp-hz = /bits/ 64 <840000000>; 2885 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2886 opp-peak-kBps = <8532000>; 2887 opp-supported-hw = <0x02>; 2888 }; 2889 2890 opp-900000000 { 2891 opp-hz = /bits/ 64 <900000000>; 2892 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2893 opp-peak-kBps = <8532000>; 2894 opp-supported-hw = <0x02>; 2895 }; 2896 }; 2897 }; 2898 2899 gmu: gmu@3d6a000 { 2900 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2901 reg = <0 0x03d6a000 0 0x34000>, 2902 <0 0x3de0000 0 0x10000>, 2903 <0 0x0b290000 0 0x10000>; 2904 reg-names = "gmu", "rscc", "gmu_pdc"; 2905 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2906 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2907 interrupt-names = "hfi", "gmu"; 2908 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2909 <&gpucc GPU_CC_CXO_CLK>, 2910 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2911 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2912 <&gpucc GPU_CC_AHB_CLK>, 2913 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2914 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2915 clock-names = "gmu", 2916 "cxo", 2917 "axi", 2918 "memnoc", 2919 "ahb", 2920 "hub", 2921 "smmu_vote"; 2922 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2923 <&gpucc GPU_CC_GX_GDSC>; 2924 power-domain-names = "cx", 2925 "gx"; 2926 iommus = <&adreno_smmu 5 0x400>; 2927 operating-points-v2 = <&gmu_opp_table>; 2928 2929 gmu_opp_table: opp-table { 2930 compatible = "operating-points-v2"; 2931 2932 opp-200000000 { 2933 opp-hz = /bits/ 64 <200000000>; 2934 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2935 }; 2936 }; 2937 }; 2938 2939 gpucc: clock-controller@3d90000 { 2940 compatible = "qcom,sc7280-gpucc"; 2941 reg = <0 0x03d90000 0 0x9000>; 2942 clocks = <&rpmhcc RPMH_CXO_CLK>, 2943 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2944 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2945 clock-names = "bi_tcxo", 2946 "gcc_gpu_gpll0_clk_src", 2947 "gcc_gpu_gpll0_div_clk_src"; 2948 #clock-cells = <1>; 2949 #reset-cells = <1>; 2950 #power-domain-cells = <1>; 2951 }; 2952 2953 dma@117f000 { 2954 compatible = "qcom,sc7280-dcc", "qcom,dcc"; 2955 reg = <0x0 0x0117f000 0x0 0x1000>, 2956 <0x0 0x01112000 0x0 0x6000>; 2957 }; 2958 2959 adreno_smmu: iommu@3da0000 { 2960 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", 2961 "qcom,smmu-500", "arm,mmu-500"; 2962 reg = <0 0x03da0000 0 0x20000>; 2963 #iommu-cells = <2>; 2964 #global-interrupts = <2>; 2965 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2966 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2967 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2968 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2969 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2970 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2971 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2972 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2973 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2974 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2975 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2976 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2977 2978 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2979 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2980 <&gpucc GPU_CC_AHB_CLK>, 2981 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2982 <&gpucc GPU_CC_CX_GMU_CLK>, 2983 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2984 <&gpucc GPU_CC_HUB_AON_CLK>; 2985 clock-names = "gcc_gpu_memnoc_gfx_clk", 2986 "gcc_gpu_snoc_dvm_gfx_clk", 2987 "gpu_cc_ahb_clk", 2988 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2989 "gpu_cc_cx_gmu_clk", 2990 "gpu_cc_hub_cx_int_clk", 2991 "gpu_cc_hub_aon_clk"; 2992 2993 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2994 dma-coherent; 2995 }; 2996 2997 gfx_0_tbu: tbu@3dd9000 { 2998 compatible = "qcom,sc7280-tbu"; 2999 reg = <0x0 0x3dd9000 0x0 0x1000>; 3000 qcom,stream-id-range = <&adreno_smmu 0x0 0x400>; 3001 }; 3002 3003 gfx_1_tbu: tbu@3ddd000 { 3004 compatible = "qcom,sc7280-tbu"; 3005 reg = <0x0 0x3ddd000 0x0 0x1000>; 3006 qcom,stream-id-range = <&adreno_smmu 0x400 0x400>; 3007 }; 3008 3009 remoteproc_mpss: remoteproc@4080000 { 3010 compatible = "qcom,sc7280-mpss-pas"; 3011 reg = <0 0x04080000 0 0x10000>; 3012 3013 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 3014 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3015 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3016 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3017 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3018 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3019 interrupt-names = "wdog", "fatal", "ready", "handover", 3020 "stop-ack", "shutdown-ack"; 3021 3022 clocks = <&rpmhcc RPMH_CXO_CLK>; 3023 clock-names = "xo"; 3024 3025 power-domains = <&rpmhpd SC7280_CX>, 3026 <&rpmhpd SC7280_MSS>; 3027 power-domain-names = "cx", "mss"; 3028 3029 memory-region = <&mpss_mem>; 3030 3031 qcom,qmp = <&aoss_qmp>; 3032 3033 qcom,smem-states = <&modem_smp2p_out 0>; 3034 qcom,smem-state-names = "stop"; 3035 3036 status = "disabled"; 3037 3038 glink-edge { 3039 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 3040 IPCC_MPROC_SIGNAL_GLINK_QMP 3041 IRQ_TYPE_EDGE_RISING>; 3042 mboxes = <&ipcc IPCC_CLIENT_MPSS 3043 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3044 label = "modem"; 3045 qcom,remote-pid = <1>; 3046 }; 3047 }; 3048 3049 stm@6002000 { 3050 compatible = "arm,coresight-stm", "arm,primecell"; 3051 reg = <0 0x06002000 0 0x1000>, 3052 <0 0x16280000 0 0x180000>; 3053 reg-names = "stm-base", "stm-stimulus-base"; 3054 3055 clocks = <&aoss_qmp>; 3056 clock-names = "apb_pclk"; 3057 3058 out-ports { 3059 port { 3060 stm_out: endpoint { 3061 remote-endpoint = <&funnel0_in7>; 3062 }; 3063 }; 3064 }; 3065 }; 3066 3067 funnel@6041000 { 3068 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3069 reg = <0 0x06041000 0 0x1000>; 3070 3071 clocks = <&aoss_qmp>; 3072 clock-names = "apb_pclk"; 3073 3074 out-ports { 3075 port { 3076 funnel0_out: endpoint { 3077 remote-endpoint = <&merge_funnel_in0>; 3078 }; 3079 }; 3080 }; 3081 3082 in-ports { 3083 #address-cells = <1>; 3084 #size-cells = <0>; 3085 3086 port@7 { 3087 reg = <7>; 3088 funnel0_in7: endpoint { 3089 remote-endpoint = <&stm_out>; 3090 }; 3091 }; 3092 }; 3093 }; 3094 3095 funnel@6042000 { 3096 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3097 reg = <0 0x06042000 0 0x1000>; 3098 3099 clocks = <&aoss_qmp>; 3100 clock-names = "apb_pclk"; 3101 3102 out-ports { 3103 port { 3104 funnel1_out: endpoint { 3105 remote-endpoint = <&merge_funnel_in1>; 3106 }; 3107 }; 3108 }; 3109 3110 in-ports { 3111 #address-cells = <1>; 3112 #size-cells = <0>; 3113 3114 port@4 { 3115 reg = <4>; 3116 funnel1_in4: endpoint { 3117 remote-endpoint = <&apss_merge_funnel_out>; 3118 }; 3119 }; 3120 }; 3121 }; 3122 3123 funnel@6045000 { 3124 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3125 reg = <0 0x06045000 0 0x1000>; 3126 3127 clocks = <&aoss_qmp>; 3128 clock-names = "apb_pclk"; 3129 3130 out-ports { 3131 port { 3132 merge_funnel_out: endpoint { 3133 remote-endpoint = <&swao_funnel_in>; 3134 }; 3135 }; 3136 }; 3137 3138 in-ports { 3139 #address-cells = <1>; 3140 #size-cells = <0>; 3141 3142 port@0 { 3143 reg = <0>; 3144 merge_funnel_in0: endpoint { 3145 remote-endpoint = <&funnel0_out>; 3146 }; 3147 }; 3148 3149 port@1 { 3150 reg = <1>; 3151 merge_funnel_in1: endpoint { 3152 remote-endpoint = <&funnel1_out>; 3153 }; 3154 }; 3155 }; 3156 }; 3157 3158 replicator@6046000 { 3159 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3160 reg = <0 0x06046000 0 0x1000>; 3161 3162 clocks = <&aoss_qmp>; 3163 clock-names = "apb_pclk"; 3164 3165 out-ports { 3166 port { 3167 replicator_out: endpoint { 3168 remote-endpoint = <&etr_in>; 3169 }; 3170 }; 3171 }; 3172 3173 in-ports { 3174 port { 3175 replicator_in: endpoint { 3176 remote-endpoint = <&swao_replicator_out>; 3177 }; 3178 }; 3179 }; 3180 }; 3181 3182 etr@6048000 { 3183 compatible = "arm,coresight-tmc", "arm,primecell"; 3184 reg = <0 0x06048000 0 0x1000>; 3185 iommus = <&apps_smmu 0x04c0 0>; 3186 3187 clocks = <&aoss_qmp>; 3188 clock-names = "apb_pclk"; 3189 arm,scatter-gather; 3190 3191 in-ports { 3192 port { 3193 etr_in: endpoint { 3194 remote-endpoint = <&replicator_out>; 3195 }; 3196 }; 3197 }; 3198 }; 3199 3200 funnel@6b04000 { 3201 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3202 reg = <0 0x06b04000 0 0x1000>; 3203 3204 clocks = <&aoss_qmp>; 3205 clock-names = "apb_pclk"; 3206 3207 out-ports { 3208 port { 3209 swao_funnel_out: endpoint { 3210 remote-endpoint = <&etf_in>; 3211 }; 3212 }; 3213 }; 3214 3215 in-ports { 3216 #address-cells = <1>; 3217 #size-cells = <0>; 3218 3219 port@7 { 3220 reg = <7>; 3221 swao_funnel_in: endpoint { 3222 remote-endpoint = <&merge_funnel_out>; 3223 }; 3224 }; 3225 }; 3226 }; 3227 3228 etf@6b05000 { 3229 compatible = "arm,coresight-tmc", "arm,primecell"; 3230 reg = <0 0x06b05000 0 0x1000>; 3231 3232 clocks = <&aoss_qmp>; 3233 clock-names = "apb_pclk"; 3234 3235 out-ports { 3236 port { 3237 etf_out: endpoint { 3238 remote-endpoint = <&swao_replicator_in>; 3239 }; 3240 }; 3241 }; 3242 3243 in-ports { 3244 port { 3245 etf_in: endpoint { 3246 remote-endpoint = <&swao_funnel_out>; 3247 }; 3248 }; 3249 }; 3250 }; 3251 3252 replicator@6b06000 { 3253 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3254 reg = <0 0x06b06000 0 0x1000>; 3255 3256 clocks = <&aoss_qmp>; 3257 clock-names = "apb_pclk"; 3258 qcom,replicator-loses-context; 3259 3260 out-ports { 3261 port { 3262 swao_replicator_out: endpoint { 3263 remote-endpoint = <&replicator_in>; 3264 }; 3265 }; 3266 }; 3267 3268 in-ports { 3269 port { 3270 swao_replicator_in: endpoint { 3271 remote-endpoint = <&etf_out>; 3272 }; 3273 }; 3274 }; 3275 }; 3276 3277 etm@7040000 { 3278 compatible = "arm,coresight-etm4x", "arm,primecell"; 3279 reg = <0 0x07040000 0 0x1000>; 3280 3281 cpu = <&CPU0>; 3282 3283 clocks = <&aoss_qmp>; 3284 clock-names = "apb_pclk"; 3285 arm,coresight-loses-context-with-cpu; 3286 qcom,skip-power-up; 3287 3288 out-ports { 3289 port { 3290 etm0_out: endpoint { 3291 remote-endpoint = <&apss_funnel_in0>; 3292 }; 3293 }; 3294 }; 3295 }; 3296 3297 etm@7140000 { 3298 compatible = "arm,coresight-etm4x", "arm,primecell"; 3299 reg = <0 0x07140000 0 0x1000>; 3300 3301 cpu = <&CPU1>; 3302 3303 clocks = <&aoss_qmp>; 3304 clock-names = "apb_pclk"; 3305 arm,coresight-loses-context-with-cpu; 3306 qcom,skip-power-up; 3307 3308 out-ports { 3309 port { 3310 etm1_out: endpoint { 3311 remote-endpoint = <&apss_funnel_in1>; 3312 }; 3313 }; 3314 }; 3315 }; 3316 3317 etm@7240000 { 3318 compatible = "arm,coresight-etm4x", "arm,primecell"; 3319 reg = <0 0x07240000 0 0x1000>; 3320 3321 cpu = <&CPU2>; 3322 3323 clocks = <&aoss_qmp>; 3324 clock-names = "apb_pclk"; 3325 arm,coresight-loses-context-with-cpu; 3326 qcom,skip-power-up; 3327 3328 out-ports { 3329 port { 3330 etm2_out: endpoint { 3331 remote-endpoint = <&apss_funnel_in2>; 3332 }; 3333 }; 3334 }; 3335 }; 3336 3337 etm@7340000 { 3338 compatible = "arm,coresight-etm4x", "arm,primecell"; 3339 reg = <0 0x07340000 0 0x1000>; 3340 3341 cpu = <&CPU3>; 3342 3343 clocks = <&aoss_qmp>; 3344 clock-names = "apb_pclk"; 3345 arm,coresight-loses-context-with-cpu; 3346 qcom,skip-power-up; 3347 3348 out-ports { 3349 port { 3350 etm3_out: endpoint { 3351 remote-endpoint = <&apss_funnel_in3>; 3352 }; 3353 }; 3354 }; 3355 }; 3356 3357 etm@7440000 { 3358 compatible = "arm,coresight-etm4x", "arm,primecell"; 3359 reg = <0 0x07440000 0 0x1000>; 3360 3361 cpu = <&CPU4>; 3362 3363 clocks = <&aoss_qmp>; 3364 clock-names = "apb_pclk"; 3365 arm,coresight-loses-context-with-cpu; 3366 qcom,skip-power-up; 3367 3368 out-ports { 3369 port { 3370 etm4_out: endpoint { 3371 remote-endpoint = <&apss_funnel_in4>; 3372 }; 3373 }; 3374 }; 3375 }; 3376 3377 etm@7540000 { 3378 compatible = "arm,coresight-etm4x", "arm,primecell"; 3379 reg = <0 0x07540000 0 0x1000>; 3380 3381 cpu = <&CPU5>; 3382 3383 clocks = <&aoss_qmp>; 3384 clock-names = "apb_pclk"; 3385 arm,coresight-loses-context-with-cpu; 3386 qcom,skip-power-up; 3387 3388 out-ports { 3389 port { 3390 etm5_out: endpoint { 3391 remote-endpoint = <&apss_funnel_in5>; 3392 }; 3393 }; 3394 }; 3395 }; 3396 3397 etm@7640000 { 3398 compatible = "arm,coresight-etm4x", "arm,primecell"; 3399 reg = <0 0x07640000 0 0x1000>; 3400 3401 cpu = <&CPU6>; 3402 3403 clocks = <&aoss_qmp>; 3404 clock-names = "apb_pclk"; 3405 arm,coresight-loses-context-with-cpu; 3406 qcom,skip-power-up; 3407 3408 out-ports { 3409 port { 3410 etm6_out: endpoint { 3411 remote-endpoint = <&apss_funnel_in6>; 3412 }; 3413 }; 3414 }; 3415 }; 3416 3417 etm@7740000 { 3418 compatible = "arm,coresight-etm4x", "arm,primecell"; 3419 reg = <0 0x07740000 0 0x1000>; 3420 3421 cpu = <&CPU7>; 3422 3423 clocks = <&aoss_qmp>; 3424 clock-names = "apb_pclk"; 3425 arm,coresight-loses-context-with-cpu; 3426 qcom,skip-power-up; 3427 3428 out-ports { 3429 port { 3430 etm7_out: endpoint { 3431 remote-endpoint = <&apss_funnel_in7>; 3432 }; 3433 }; 3434 }; 3435 }; 3436 3437 funnel@7800000 { /* APSS Funnel */ 3438 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3439 reg = <0 0x07800000 0 0x1000>; 3440 3441 clocks = <&aoss_qmp>; 3442 clock-names = "apb_pclk"; 3443 3444 out-ports { 3445 port { 3446 apss_funnel_out: endpoint { 3447 remote-endpoint = <&apss_merge_funnel_in>; 3448 }; 3449 }; 3450 }; 3451 3452 in-ports { 3453 #address-cells = <1>; 3454 #size-cells = <0>; 3455 3456 port@0 { 3457 reg = <0>; 3458 apss_funnel_in0: endpoint { 3459 remote-endpoint = <&etm0_out>; 3460 }; 3461 }; 3462 3463 port@1 { 3464 reg = <1>; 3465 apss_funnel_in1: endpoint { 3466 remote-endpoint = <&etm1_out>; 3467 }; 3468 }; 3469 3470 port@2 { 3471 reg = <2>; 3472 apss_funnel_in2: endpoint { 3473 remote-endpoint = <&etm2_out>; 3474 }; 3475 }; 3476 3477 port@3 { 3478 reg = <3>; 3479 apss_funnel_in3: endpoint { 3480 remote-endpoint = <&etm3_out>; 3481 }; 3482 }; 3483 3484 port@4 { 3485 reg = <4>; 3486 apss_funnel_in4: endpoint { 3487 remote-endpoint = <&etm4_out>; 3488 }; 3489 }; 3490 3491 port@5 { 3492 reg = <5>; 3493 apss_funnel_in5: endpoint { 3494 remote-endpoint = <&etm5_out>; 3495 }; 3496 }; 3497 3498 port@6 { 3499 reg = <6>; 3500 apss_funnel_in6: endpoint { 3501 remote-endpoint = <&etm6_out>; 3502 }; 3503 }; 3504 3505 port@7 { 3506 reg = <7>; 3507 apss_funnel_in7: endpoint { 3508 remote-endpoint = <&etm7_out>; 3509 }; 3510 }; 3511 }; 3512 }; 3513 3514 funnel@7810000 { 3515 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3516 reg = <0 0x07810000 0 0x1000>; 3517 3518 clocks = <&aoss_qmp>; 3519 clock-names = "apb_pclk"; 3520 3521 out-ports { 3522 port { 3523 apss_merge_funnel_out: endpoint { 3524 remote-endpoint = <&funnel1_in4>; 3525 }; 3526 }; 3527 }; 3528 3529 in-ports { 3530 port { 3531 apss_merge_funnel_in: endpoint { 3532 remote-endpoint = <&apss_funnel_out>; 3533 }; 3534 }; 3535 }; 3536 }; 3537 3538 sdhc_2: mmc@8804000 { 3539 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3540 pinctrl-names = "default", "sleep"; 3541 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3542 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3543 status = "disabled"; 3544 3545 reg = <0 0x08804000 0 0x1000>; 3546 3547 iommus = <&apps_smmu 0x100 0x0>; 3548 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3549 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3550 interrupt-names = "hc_irq", "pwr_irq"; 3551 3552 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3553 <&gcc GCC_SDCC2_APPS_CLK>, 3554 <&rpmhcc RPMH_CXO_CLK>; 3555 clock-names = "iface", "core", "xo"; 3556 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3557 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3558 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3559 power-domains = <&rpmhpd SC7280_CX>; 3560 operating-points-v2 = <&sdhc2_opp_table>; 3561 3562 bus-width = <4>; 3563 dma-coherent; 3564 3565 qcom,dll-config = <0x0007642c>; 3566 3567 resets = <&gcc GCC_SDCC2_BCR>; 3568 3569 sdhc2_opp_table: opp-table { 3570 compatible = "operating-points-v2"; 3571 3572 opp-100000000 { 3573 opp-hz = /bits/ 64 <100000000>; 3574 required-opps = <&rpmhpd_opp_low_svs>; 3575 opp-peak-kBps = <1800000 400000>; 3576 opp-avg-kBps = <100000 0>; 3577 }; 3578 3579 opp-202000000 { 3580 opp-hz = /bits/ 64 <202000000>; 3581 required-opps = <&rpmhpd_opp_nom>; 3582 opp-peak-kBps = <5400000 1600000>; 3583 opp-avg-kBps = <200000 0>; 3584 }; 3585 }; 3586 }; 3587 3588 usb_1_hsphy: phy@88e3000 { 3589 compatible = "qcom,sc7280-usb-hs-phy", 3590 "qcom,usb-snps-hs-7nm-phy"; 3591 reg = <0 0x088e3000 0 0x400>; 3592 status = "disabled"; 3593 #phy-cells = <0>; 3594 3595 clocks = <&rpmhcc RPMH_CXO_CLK>; 3596 clock-names = "ref"; 3597 3598 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3599 }; 3600 3601 usb_2_hsphy: phy@88e4000 { 3602 compatible = "qcom,sc7280-usb-hs-phy", 3603 "qcom,usb-snps-hs-7nm-phy"; 3604 reg = <0 0x088e4000 0 0x400>; 3605 status = "disabled"; 3606 #phy-cells = <0>; 3607 3608 clocks = <&rpmhcc RPMH_CXO_CLK>; 3609 clock-names = "ref"; 3610 3611 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3612 }; 3613 3614 usb_1_qmpphy: phy@88e8000 { 3615 compatible = "qcom,sc7280-qmp-usb3-dp-phy"; 3616 reg = <0 0x088e8000 0 0x3000>; 3617 status = "disabled"; 3618 3619 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3620 <&rpmhcc RPMH_CXO_CLK>, 3621 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3622 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3623 clock-names = "aux", 3624 "ref", 3625 "com_aux", 3626 "usb3_pipe"; 3627 3628 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3629 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3630 reset-names = "phy", "common"; 3631 3632 #clock-cells = <1>; 3633 #phy-cells = <1>; 3634 3635 ports { 3636 #address-cells = <1>; 3637 #size-cells = <0>; 3638 3639 port@0 { 3640 reg = <0>; 3641 3642 usb_dp_qmpphy_out: endpoint { 3643 }; 3644 }; 3645 3646 port@1 { 3647 reg = <1>; 3648 3649 usb_dp_qmpphy_usb_ss_in: endpoint { 3650 }; 3651 }; 3652 3653 port@2 { 3654 reg = <2>; 3655 3656 usb_dp_qmpphy_dp_in: endpoint { 3657 }; 3658 }; 3659 }; 3660 }; 3661 3662 usb_2: usb@8cf8800 { 3663 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3664 reg = <0 0x08cf8800 0 0x400>; 3665 status = "disabled"; 3666 #address-cells = <2>; 3667 #size-cells = <2>; 3668 ranges; 3669 dma-ranges; 3670 3671 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3672 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3673 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3674 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3675 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3676 clock-names = "cfg_noc", 3677 "core", 3678 "iface", 3679 "sleep", 3680 "mock_utmi"; 3681 3682 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3683 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3684 assigned-clock-rates = <19200000>, <200000000>; 3685 3686 interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 3687 <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3688 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 3689 <&pdc 13 IRQ_TYPE_EDGE_BOTH>; 3690 interrupt-names = "pwr_event", 3691 "hs_phy_irq", 3692 "dp_hs_phy_irq", 3693 "dm_hs_phy_irq"; 3694 3695 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3696 required-opps = <&rpmhpd_opp_nom>; 3697 3698 resets = <&gcc GCC_USB30_SEC_BCR>; 3699 3700 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3701 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3702 interconnect-names = "usb-ddr", "apps-usb"; 3703 3704 usb_2_dwc3: usb@8c00000 { 3705 compatible = "snps,dwc3"; 3706 reg = <0 0x08c00000 0 0xe000>; 3707 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3708 iommus = <&apps_smmu 0xa0 0x0>; 3709 snps,dis_u2_susphy_quirk; 3710 snps,dis_enblslpm_quirk; 3711 phys = <&usb_2_hsphy>; 3712 phy-names = "usb2-phy"; 3713 maximum-speed = "high-speed"; 3714 usb-role-switch; 3715 3716 port { 3717 usb2_role_switch: endpoint { 3718 remote-endpoint = <&eud_ep>; 3719 }; 3720 }; 3721 }; 3722 }; 3723 3724 qspi: spi@88dc000 { 3725 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3726 reg = <0 0x088dc000 0 0x1000>; 3727 iommus = <&apps_smmu 0x20 0x0>; 3728 #address-cells = <1>; 3729 #size-cells = <0>; 3730 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3731 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3732 <&gcc GCC_QSPI_CORE_CLK>; 3733 clock-names = "iface", "core"; 3734 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3735 &cnoc2 SLAVE_QSPI_0 0>; 3736 interconnect-names = "qspi-config"; 3737 power-domains = <&rpmhpd SC7280_CX>; 3738 operating-points-v2 = <&qspi_opp_table>; 3739 status = "disabled"; 3740 }; 3741 3742 remoteproc_adsp: remoteproc@3700000 { 3743 compatible = "qcom,sc7280-adsp-pas"; 3744 reg = <0 0x03700000 0 0x100>; 3745 3746 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 3747 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3748 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3749 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3750 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3751 <&adsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3752 interrupt-names = "wdog", "fatal", "ready", "handover", 3753 "stop-ack", "shutdown-ack"; 3754 3755 clocks = <&rpmhcc RPMH_CXO_CLK>; 3756 clock-names = "xo"; 3757 3758 power-domains = <&rpmhpd SC7280_LCX>, 3759 <&rpmhpd SC7280_LMX>; 3760 power-domain-names = "lcx", "lmx"; 3761 3762 memory-region = <&adsp_mem>; 3763 3764 qcom,qmp = <&aoss_qmp>; 3765 3766 qcom,smem-states = <&adsp_smp2p_out 0>; 3767 qcom,smem-state-names = "stop"; 3768 3769 status = "disabled"; 3770 3771 glink-edge { 3772 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3773 IPCC_MPROC_SIGNAL_GLINK_QMP 3774 IRQ_TYPE_EDGE_RISING>; 3775 3776 mboxes = <&ipcc IPCC_CLIENT_LPASS 3777 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3778 3779 label = "lpass"; 3780 qcom,remote-pid = <2>; 3781 3782 apr { 3783 compatible = "qcom,apr-v2"; 3784 qcom,glink-channels = "apr_audio_svc"; 3785 qcom,domain = <APR_DOMAIN_ADSP>; 3786 #address-cells = <1>; 3787 #size-cells = <0>; 3788 3789 service@3 { 3790 reg = <APR_SVC_ADSP_CORE>; 3791 compatible = "qcom,q6core"; 3792 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3793 }; 3794 3795 q6afe: service@4 { 3796 compatible = "qcom,q6afe"; 3797 reg = <APR_SVC_AFE>; 3798 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3799 3800 q6afedai: dais { 3801 compatible = "qcom,q6afe-dais"; 3802 #address-cells = <1>; 3803 #size-cells = <0>; 3804 #sound-dai-cells = <1>; 3805 }; 3806 3807 q6afecc: clock-controller { 3808 compatible = "qcom,q6afe-clocks"; 3809 #clock-cells = <2>; 3810 }; 3811 }; 3812 3813 q6asm: service@7 { 3814 compatible = "qcom,q6asm"; 3815 reg = <APR_SVC_ASM>; 3816 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3817 3818 q6asmdai: dais { 3819 compatible = "qcom,q6asm-dais"; 3820 #address-cells = <1>; 3821 #size-cells = <0>; 3822 #sound-dai-cells = <1>; 3823 iommus = <&apps_smmu 0x1801 0x0>; 3824 3825 dai@0 { 3826 reg = <0>; 3827 }; 3828 3829 dai@1 { 3830 reg = <1>; 3831 }; 3832 3833 dai@2 { 3834 reg = <2>; 3835 }; 3836 }; 3837 }; 3838 3839 q6adm: service@8 { 3840 compatible = "qcom,q6adm"; 3841 reg = <APR_SVC_ADM>; 3842 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 3843 3844 q6routing: routing { 3845 compatible = "qcom,q6adm-routing"; 3846 #sound-dai-cells = <0>; 3847 }; 3848 }; 3849 }; 3850 3851 fastrpc { 3852 compatible = "qcom,fastrpc"; 3853 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3854 label = "adsp"; 3855 qcom,non-secure-domain; 3856 #address-cells = <1>; 3857 #size-cells = <0>; 3858 3859 compute-cb@3 { 3860 compatible = "qcom,fastrpc-compute-cb"; 3861 reg = <3>; 3862 iommus = <&apps_smmu 0x1803 0x0>; 3863 }; 3864 3865 compute-cb@4 { 3866 compatible = "qcom,fastrpc-compute-cb"; 3867 reg = <4>; 3868 iommus = <&apps_smmu 0x1804 0x0>; 3869 }; 3870 3871 compute-cb@5 { 3872 compatible = "qcom,fastrpc-compute-cb"; 3873 reg = <5>; 3874 iommus = <&apps_smmu 0x1805 0x0>; 3875 }; 3876 }; 3877 }; 3878 }; 3879 3880 remoteproc_wpss: remoteproc@8a00000 { 3881 compatible = "qcom,sc7280-wpss-pas"; 3882 reg = <0 0x08a00000 0 0x10000>; 3883 3884 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3885 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3886 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3887 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3888 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3889 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3890 interrupt-names = "wdog", "fatal", "ready", "handover", 3891 "stop-ack", "shutdown-ack"; 3892 3893 clocks = <&rpmhcc RPMH_CXO_CLK>; 3894 clock-names = "xo"; 3895 3896 power-domains = <&rpmhpd SC7280_CX>, 3897 <&rpmhpd SC7280_MX>; 3898 power-domain-names = "cx", "mx"; 3899 3900 memory-region = <&wpss_mem>; 3901 3902 qcom,qmp = <&aoss_qmp>; 3903 3904 qcom,smem-states = <&wpss_smp2p_out 0>; 3905 qcom,smem-state-names = "stop"; 3906 3907 3908 status = "disabled"; 3909 3910 glink-edge { 3911 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3912 IPCC_MPROC_SIGNAL_GLINK_QMP 3913 IRQ_TYPE_EDGE_RISING>; 3914 mboxes = <&ipcc IPCC_CLIENT_WPSS 3915 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3916 3917 label = "wpss"; 3918 qcom,remote-pid = <13>; 3919 }; 3920 }; 3921 3922 pmu@9091000 { 3923 compatible = "qcom,sc7280-llcc-bwmon"; 3924 reg = <0 0x09091000 0 0x1000>; 3925 3926 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3927 3928 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3929 3930 operating-points-v2 = <&llcc_bwmon_opp_table>; 3931 3932 llcc_bwmon_opp_table: opp-table { 3933 compatible = "operating-points-v2"; 3934 3935 opp-0 { 3936 opp-peak-kBps = <800000>; 3937 }; 3938 opp-1 { 3939 opp-peak-kBps = <1804000>; 3940 }; 3941 opp-2 { 3942 opp-peak-kBps = <2188000>; 3943 }; 3944 opp-3 { 3945 opp-peak-kBps = <3072000>; 3946 }; 3947 opp-4 { 3948 opp-peak-kBps = <4068000>; 3949 }; 3950 opp-5 { 3951 opp-peak-kBps = <6220000>; 3952 }; 3953 opp-6 { 3954 opp-peak-kBps = <6832000>; 3955 }; 3956 opp-7 { 3957 opp-peak-kBps = <8532000>; 3958 }; 3959 }; 3960 }; 3961 3962 pmu@90b6400 { 3963 compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon"; 3964 reg = <0 0x090b6400 0 0x600>; 3965 3966 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3967 3968 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3969 operating-points-v2 = <&cpu_bwmon_opp_table>; 3970 3971 cpu_bwmon_opp_table: opp-table { 3972 compatible = "operating-points-v2"; 3973 3974 opp-0 { 3975 opp-peak-kBps = <2400000>; 3976 }; 3977 opp-1 { 3978 opp-peak-kBps = <4800000>; 3979 }; 3980 opp-2 { 3981 opp-peak-kBps = <7456000>; 3982 }; 3983 opp-3 { 3984 opp-peak-kBps = <9600000>; 3985 }; 3986 opp-4 { 3987 opp-peak-kBps = <12896000>; 3988 }; 3989 opp-5 { 3990 opp-peak-kBps = <14928000>; 3991 }; 3992 opp-6 { 3993 opp-peak-kBps = <17056000>; 3994 }; 3995 }; 3996 }; 3997 3998 dc_noc: interconnect@90e0000 { 3999 reg = <0 0x090e0000 0 0x5080>; 4000 compatible = "qcom,sc7280-dc-noc"; 4001 #interconnect-cells = <2>; 4002 qcom,bcm-voters = <&apps_bcm_voter>; 4003 }; 4004 4005 gem_noc: interconnect@9100000 { 4006 reg = <0 0x09100000 0 0xe2200>; 4007 compatible = "qcom,sc7280-gem-noc"; 4008 #interconnect-cells = <2>; 4009 qcom,bcm-voters = <&apps_bcm_voter>; 4010 }; 4011 4012 system-cache-controller@9200000 { 4013 compatible = "qcom,sc7280-llcc"; 4014 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 4015 <0 0x09600000 0 0x58000>; 4016 reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; 4017 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 4018 }; 4019 4020 eud: eud@88e0000 { 4021 compatible = "qcom,sc7280-eud", "qcom,eud"; 4022 reg = <0 0x88e0000 0 0x2000>, 4023 <0 0x88e2000 0 0x1000>; 4024 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 4025 4026 status = "disabled"; 4027 4028 ports { 4029 #address-cells = <1>; 4030 #size-cells = <0>; 4031 4032 port@0 { 4033 reg = <0>; 4034 eud_ep: endpoint { 4035 remote-endpoint = <&usb2_role_switch>; 4036 }; 4037 }; 4038 }; 4039 }; 4040 4041 nsp_noc: interconnect@a0c0000 { 4042 reg = <0 0x0a0c0000 0 0x10000>; 4043 compatible = "qcom,sc7280-nsp-noc"; 4044 #interconnect-cells = <2>; 4045 qcom,bcm-voters = <&apps_bcm_voter>; 4046 }; 4047 4048 remoteproc_cdsp: remoteproc@a300000 { 4049 compatible = "qcom,sc7280-cdsp-pas"; 4050 reg = <0 0x0a300000 0 0x10000>; 4051 4052 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 4053 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4054 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 4055 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 4056 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 4057 <&cdsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 4058 interrupt-names = "wdog", "fatal", "ready", "handover", 4059 "stop-ack", "shutdown-ack"; 4060 4061 clocks = <&rpmhcc RPMH_CXO_CLK>; 4062 clock-names = "xo"; 4063 4064 power-domains = <&rpmhpd SC7280_CX>, 4065 <&rpmhpd SC7280_MX>; 4066 power-domain-names = "cx", "mx"; 4067 4068 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 4069 4070 memory-region = <&cdsp_mem>; 4071 4072 qcom,qmp = <&aoss_qmp>; 4073 4074 qcom,smem-states = <&cdsp_smp2p_out 0>; 4075 qcom,smem-state-names = "stop"; 4076 4077 status = "disabled"; 4078 4079 glink-edge { 4080 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4081 IPCC_MPROC_SIGNAL_GLINK_QMP 4082 IRQ_TYPE_EDGE_RISING>; 4083 mboxes = <&ipcc IPCC_CLIENT_CDSP 4084 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4085 4086 label = "cdsp"; 4087 qcom,remote-pid = <5>; 4088 4089 fastrpc { 4090 compatible = "qcom,fastrpc"; 4091 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4092 label = "cdsp"; 4093 qcom,non-secure-domain; 4094 #address-cells = <1>; 4095 #size-cells = <0>; 4096 4097 compute-cb@1 { 4098 compatible = "qcom,fastrpc-compute-cb"; 4099 reg = <1>; 4100 iommus = <&apps_smmu 0x11a1 0x0420>, 4101 <&apps_smmu 0x1181 0x0420>; 4102 }; 4103 4104 compute-cb@2 { 4105 compatible = "qcom,fastrpc-compute-cb"; 4106 reg = <2>; 4107 iommus = <&apps_smmu 0x11a2 0x0420>, 4108 <&apps_smmu 0x1182 0x0420>; 4109 }; 4110 4111 compute-cb@3 { 4112 compatible = "qcom,fastrpc-compute-cb"; 4113 reg = <3>; 4114 iommus = <&apps_smmu 0x11a3 0x0420>, 4115 <&apps_smmu 0x1183 0x0420>; 4116 }; 4117 4118 compute-cb@4 { 4119 compatible = "qcom,fastrpc-compute-cb"; 4120 reg = <4>; 4121 iommus = <&apps_smmu 0x11a4 0x0420>, 4122 <&apps_smmu 0x1184 0x0420>; 4123 }; 4124 4125 compute-cb@5 { 4126 compatible = "qcom,fastrpc-compute-cb"; 4127 reg = <5>; 4128 iommus = <&apps_smmu 0x11a5 0x0420>, 4129 <&apps_smmu 0x1185 0x0420>; 4130 }; 4131 4132 compute-cb@6 { 4133 compatible = "qcom,fastrpc-compute-cb"; 4134 reg = <6>; 4135 iommus = <&apps_smmu 0x11a6 0x0420>, 4136 <&apps_smmu 0x1186 0x0420>; 4137 }; 4138 4139 compute-cb@7 { 4140 compatible = "qcom,fastrpc-compute-cb"; 4141 reg = <7>; 4142 iommus = <&apps_smmu 0x11a7 0x0420>, 4143 <&apps_smmu 0x1187 0x0420>; 4144 }; 4145 4146 compute-cb@8 { 4147 compatible = "qcom,fastrpc-compute-cb"; 4148 reg = <8>; 4149 iommus = <&apps_smmu 0x11a8 0x0420>, 4150 <&apps_smmu 0x1188 0x0420>; 4151 }; 4152 4153 /* note: secure cb9 in downstream */ 4154 4155 compute-cb@11 { 4156 compatible = "qcom,fastrpc-compute-cb"; 4157 reg = <11>; 4158 iommus = <&apps_smmu 0x11ab 0x0420>, 4159 <&apps_smmu 0x118b 0x0420>; 4160 }; 4161 4162 compute-cb@12 { 4163 compatible = "qcom,fastrpc-compute-cb"; 4164 reg = <12>; 4165 iommus = <&apps_smmu 0x11ac 0x0420>, 4166 <&apps_smmu 0x118c 0x0420>; 4167 }; 4168 4169 compute-cb@13 { 4170 compatible = "qcom,fastrpc-compute-cb"; 4171 reg = <13>; 4172 iommus = <&apps_smmu 0x11ad 0x0420>, 4173 <&apps_smmu 0x118d 0x0420>; 4174 }; 4175 4176 compute-cb@14 { 4177 compatible = "qcom,fastrpc-compute-cb"; 4178 reg = <14>; 4179 iommus = <&apps_smmu 0x11ae 0x0420>, 4180 <&apps_smmu 0x118e 0x0420>; 4181 }; 4182 }; 4183 }; 4184 }; 4185 4186 usb_1: usb@a6f8800 { 4187 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 4188 reg = <0 0x0a6f8800 0 0x400>; 4189 status = "disabled"; 4190 #address-cells = <2>; 4191 #size-cells = <2>; 4192 ranges; 4193 dma-ranges; 4194 4195 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4196 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4197 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4198 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4199 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 4200 clock-names = "cfg_noc", 4201 "core", 4202 "iface", 4203 "sleep", 4204 "mock_utmi"; 4205 4206 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4207 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4208 assigned-clock-rates = <19200000>, <200000000>; 4209 4210 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4211 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4212 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4213 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4214 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 4215 interrupt-names = "pwr_event", 4216 "hs_phy_irq", 4217 "dp_hs_phy_irq", 4218 "dm_hs_phy_irq", 4219 "ss_phy_irq"; 4220 4221 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 4222 required-opps = <&rpmhpd_opp_nom>; 4223 4224 resets = <&gcc GCC_USB30_PRIM_BCR>; 4225 4226 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 4227 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 4228 interconnect-names = "usb-ddr", "apps-usb"; 4229 4230 wakeup-source; 4231 4232 usb_1_dwc3: usb@a600000 { 4233 compatible = "snps,dwc3"; 4234 reg = <0 0x0a600000 0 0xe000>; 4235 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4236 iommus = <&apps_smmu 0xe0 0x0>; 4237 snps,dis_u2_susphy_quirk; 4238 snps,dis_enblslpm_quirk; 4239 snps,parkmode-disable-ss-quirk; 4240 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4241 phy-names = "usb2-phy", "usb3-phy"; 4242 maximum-speed = "super-speed"; 4243 4244 ports { 4245 #address-cells = <1>; 4246 #size-cells = <0>; 4247 4248 port@0 { 4249 reg = <0>; 4250 4251 usb_1_dwc3_hs: endpoint { 4252 }; 4253 }; 4254 4255 port@1 { 4256 reg = <1>; 4257 4258 usb_1_dwc3_ss: endpoint { 4259 }; 4260 }; 4261 }; 4262 }; 4263 }; 4264 4265 venus: video-codec@aa00000 { 4266 compatible = "qcom,sc7280-venus"; 4267 reg = <0 0x0aa00000 0 0xd0600>; 4268 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4269 4270 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 4271 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 4272 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 4273 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 4274 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 4275 clock-names = "core", "bus", "iface", 4276 "vcodec_core", "vcodec_bus"; 4277 4278 power-domains = <&videocc MVSC_GDSC>, 4279 <&videocc MVS0_GDSC>, 4280 <&rpmhpd SC7280_CX>; 4281 power-domain-names = "venus", "vcodec0", "cx"; 4282 operating-points-v2 = <&venus_opp_table>; 4283 4284 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 4285 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 4286 interconnect-names = "cpu-cfg", "video-mem"; 4287 4288 iommus = <&apps_smmu 0x2180 0x20>; 4289 memory-region = <&video_mem>; 4290 4291 status = "disabled"; 4292 4293 video-decoder { 4294 compatible = "venus-decoder"; 4295 }; 4296 4297 video-encoder { 4298 compatible = "venus-encoder"; 4299 }; 4300 4301 venus_opp_table: opp-table { 4302 compatible = "operating-points-v2"; 4303 4304 opp-133330000 { 4305 opp-hz = /bits/ 64 <133330000>; 4306 required-opps = <&rpmhpd_opp_low_svs>; 4307 }; 4308 4309 opp-240000000 { 4310 opp-hz = /bits/ 64 <240000000>; 4311 required-opps = <&rpmhpd_opp_svs>; 4312 }; 4313 4314 opp-335000000 { 4315 opp-hz = /bits/ 64 <335000000>; 4316 required-opps = <&rpmhpd_opp_svs_l1>; 4317 }; 4318 4319 opp-424000000 { 4320 opp-hz = /bits/ 64 <424000000>; 4321 required-opps = <&rpmhpd_opp_nom>; 4322 }; 4323 4324 opp-460000048 { 4325 opp-hz = /bits/ 64 <460000048>; 4326 required-opps = <&rpmhpd_opp_turbo>; 4327 }; 4328 }; 4329 }; 4330 4331 videocc: clock-controller@aaf0000 { 4332 compatible = "qcom,sc7280-videocc"; 4333 reg = <0 0x0aaf0000 0 0x10000>; 4334 clocks = <&rpmhcc RPMH_CXO_CLK>, 4335 <&rpmhcc RPMH_CXO_CLK_A>; 4336 clock-names = "bi_tcxo", "bi_tcxo_ao"; 4337 #clock-cells = <1>; 4338 #reset-cells = <1>; 4339 #power-domain-cells = <1>; 4340 }; 4341 4342 cci0: cci@ac4a000 { 4343 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci"; 4344 reg = <0 0x0ac4a000 0 0x1000>; 4345 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4346 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4347 4348 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4349 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4350 <&camcc CAM_CC_CPAS_AHB_CLK>, 4351 <&camcc CAM_CC_CCI_0_CLK>, 4352 <&camcc CAM_CC_CCI_0_CLK_SRC>; 4353 clock-names = "camnoc_axi", 4354 "slow_ahb_src", 4355 "cpas_ahb", 4356 "cci", 4357 "cci_src"; 4358 pinctrl-0 = <&cci0_default &cci1_default>; 4359 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 4360 pinctrl-names = "default", "sleep"; 4361 4362 #address-cells = <1>; 4363 #size-cells = <0>; 4364 4365 status = "disabled"; 4366 4367 cci0_i2c0: i2c-bus@0 { 4368 reg = <0>; 4369 clock-frequency = <1000000>; 4370 #address-cells = <1>; 4371 #size-cells = <0>; 4372 }; 4373 4374 cci0_i2c1: i2c-bus@1 { 4375 reg = <1>; 4376 clock-frequency = <1000000>; 4377 #address-cells = <1>; 4378 #size-cells = <0>; 4379 }; 4380 }; 4381 4382 cci1: cci@ac4b000 { 4383 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci"; 4384 reg = <0 0x0ac4b000 0 0x1000>; 4385 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 4386 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4387 4388 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4389 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4390 <&camcc CAM_CC_CPAS_AHB_CLK>, 4391 <&camcc CAM_CC_CCI_1_CLK>, 4392 <&camcc CAM_CC_CCI_1_CLK_SRC>; 4393 clock-names = "camnoc_axi", 4394 "slow_ahb_src", 4395 "cpas_ahb", 4396 "cci", 4397 "cci_src"; 4398 pinctrl-0 = <&cci2_default &cci3_default>; 4399 pinctrl-1 = <&cci2_sleep &cci3_sleep>; 4400 pinctrl-names = "default", "sleep"; 4401 4402 #address-cells = <1>; 4403 #size-cells = <0>; 4404 4405 status = "disabled"; 4406 4407 cci1_i2c0: i2c-bus@0 { 4408 reg = <0>; 4409 clock-frequency = <1000000>; 4410 #address-cells = <1>; 4411 #size-cells = <0>; 4412 }; 4413 4414 cci1_i2c1: i2c-bus@1 { 4415 reg = <1>; 4416 clock-frequency = <1000000>; 4417 #address-cells = <1>; 4418 #size-cells = <0>; 4419 }; 4420 }; 4421 4422 camcc: clock-controller@ad00000 { 4423 compatible = "qcom,sc7280-camcc"; 4424 reg = <0 0x0ad00000 0 0x10000>; 4425 clocks = <&rpmhcc RPMH_CXO_CLK>, 4426 <&rpmhcc RPMH_CXO_CLK_A>, 4427 <&sleep_clk>; 4428 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 4429 #clock-cells = <1>; 4430 #reset-cells = <1>; 4431 #power-domain-cells = <1>; 4432 }; 4433 4434 dispcc: clock-controller@af00000 { 4435 compatible = "qcom,sc7280-dispcc"; 4436 reg = <0 0x0af00000 0 0x20000>; 4437 clocks = <&rpmhcc RPMH_CXO_CLK>, 4438 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 4439 <&mdss_dsi_phy 0>, 4440 <&mdss_dsi_phy 1>, 4441 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4442 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4443 <&mdss_edp_phy 0>, 4444 <&mdss_edp_phy 1>; 4445 clock-names = "bi_tcxo", 4446 "gcc_disp_gpll0_clk", 4447 "dsi0_phy_pll_out_byteclk", 4448 "dsi0_phy_pll_out_dsiclk", 4449 "dp_phy_pll_link_clk", 4450 "dp_phy_pll_vco_div_clk", 4451 "edp_phy_pll_link_clk", 4452 "edp_phy_pll_vco_div_clk"; 4453 #clock-cells = <1>; 4454 #reset-cells = <1>; 4455 #power-domain-cells = <1>; 4456 }; 4457 4458 mdss: display-subsystem@ae00000 { 4459 compatible = "qcom,sc7280-mdss"; 4460 reg = <0 0x0ae00000 0 0x1000>; 4461 reg-names = "mdss"; 4462 4463 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 4464 4465 clocks = <&gcc GCC_DISP_AHB_CLK>, 4466 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4467 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4468 clock-names = "iface", 4469 "ahb", 4470 "core"; 4471 4472 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4473 interrupt-controller; 4474 #interrupt-cells = <1>; 4475 4476 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS 4477 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4478 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4479 &cnoc2 SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>; 4480 interconnect-names = "mdp0-mem", 4481 "cpu-cfg"; 4482 4483 iommus = <&apps_smmu 0x900 0x402>; 4484 4485 #address-cells = <2>; 4486 #size-cells = <2>; 4487 ranges; 4488 4489 status = "disabled"; 4490 4491 mdss_mdp: display-controller@ae01000 { 4492 compatible = "qcom,sc7280-dpu"; 4493 reg = <0 0x0ae01000 0 0x8f030>, 4494 <0 0x0aeb0000 0 0x2008>; 4495 reg-names = "mdp", "vbif"; 4496 4497 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4498 <&gcc GCC_DISP_SF_AXI_CLK>, 4499 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4500 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 4501 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4502 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4503 clock-names = "bus", 4504 "nrt_bus", 4505 "iface", 4506 "lut", 4507 "core", 4508 "vsync"; 4509 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 4510 <&dispcc DISP_CC_MDSS_AHB_CLK>; 4511 assigned-clock-rates = <19200000>, 4512 <19200000>; 4513 operating-points-v2 = <&mdp_opp_table>; 4514 power-domains = <&rpmhpd SC7280_CX>; 4515 4516 interrupt-parent = <&mdss>; 4517 interrupts = <0>; 4518 4519 ports { 4520 #address-cells = <1>; 4521 #size-cells = <0>; 4522 4523 port@0 { 4524 reg = <0>; 4525 dpu_intf1_out: endpoint { 4526 remote-endpoint = <&mdss_dsi0_in>; 4527 }; 4528 }; 4529 4530 port@1 { 4531 reg = <1>; 4532 dpu_intf5_out: endpoint { 4533 remote-endpoint = <&edp_in>; 4534 }; 4535 }; 4536 4537 port@2 { 4538 reg = <2>; 4539 dpu_intf0_out: endpoint { 4540 remote-endpoint = <&dp_in>; 4541 }; 4542 }; 4543 }; 4544 4545 mdp_opp_table: opp-table { 4546 compatible = "operating-points-v2"; 4547 4548 opp-200000000 { 4549 opp-hz = /bits/ 64 <200000000>; 4550 required-opps = <&rpmhpd_opp_low_svs>; 4551 }; 4552 4553 opp-300000000 { 4554 opp-hz = /bits/ 64 <300000000>; 4555 required-opps = <&rpmhpd_opp_svs>; 4556 }; 4557 4558 opp-380000000 { 4559 opp-hz = /bits/ 64 <380000000>; 4560 required-opps = <&rpmhpd_opp_svs_l1>; 4561 }; 4562 4563 opp-506666667 { 4564 opp-hz = /bits/ 64 <506666667>; 4565 required-opps = <&rpmhpd_opp_nom>; 4566 }; 4567 4568 opp-608000000 { 4569 opp-hz = /bits/ 64 <608000000>; 4570 required-opps = <&rpmhpd_opp_turbo>; 4571 }; 4572 }; 4573 }; 4574 4575 mdss_dsi: dsi@ae94000 { 4576 compatible = "qcom,sc7280-dsi-ctrl", 4577 "qcom,mdss-dsi-ctrl"; 4578 reg = <0 0x0ae94000 0 0x400>; 4579 reg-names = "dsi_ctrl"; 4580 4581 interrupt-parent = <&mdss>; 4582 interrupts = <4>; 4583 4584 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4585 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4586 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4587 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4588 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4589 <&gcc GCC_DISP_HF_AXI_CLK>; 4590 clock-names = "byte", 4591 "byte_intf", 4592 "pixel", 4593 "core", 4594 "iface", 4595 "bus"; 4596 4597 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4598 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>; 4599 4600 operating-points-v2 = <&dsi_opp_table>; 4601 power-domains = <&rpmhpd SC7280_CX>; 4602 4603 phys = <&mdss_dsi_phy>; 4604 4605 #address-cells = <1>; 4606 #size-cells = <0>; 4607 4608 status = "disabled"; 4609 4610 ports { 4611 #address-cells = <1>; 4612 #size-cells = <0>; 4613 4614 port@0 { 4615 reg = <0>; 4616 mdss_dsi0_in: endpoint { 4617 remote-endpoint = <&dpu_intf1_out>; 4618 }; 4619 }; 4620 4621 port@1 { 4622 reg = <1>; 4623 mdss_dsi0_out: endpoint { 4624 }; 4625 }; 4626 }; 4627 4628 dsi_opp_table: opp-table { 4629 compatible = "operating-points-v2"; 4630 4631 opp-187500000 { 4632 opp-hz = /bits/ 64 <187500000>; 4633 required-opps = <&rpmhpd_opp_low_svs>; 4634 }; 4635 4636 opp-300000000 { 4637 opp-hz = /bits/ 64 <300000000>; 4638 required-opps = <&rpmhpd_opp_svs>; 4639 }; 4640 4641 opp-358000000 { 4642 opp-hz = /bits/ 64 <358000000>; 4643 required-opps = <&rpmhpd_opp_svs_l1>; 4644 }; 4645 }; 4646 }; 4647 4648 mdss_dsi_phy: phy@ae94400 { 4649 compatible = "qcom,sc7280-dsi-phy-7nm"; 4650 reg = <0 0x0ae94400 0 0x200>, 4651 <0 0x0ae94600 0 0x280>, 4652 <0 0x0ae94900 0 0x280>; 4653 reg-names = "dsi_phy", 4654 "dsi_phy_lane", 4655 "dsi_pll"; 4656 4657 #clock-cells = <1>; 4658 #phy-cells = <0>; 4659 4660 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4661 <&rpmhcc RPMH_CXO_CLK>; 4662 clock-names = "iface", "ref"; 4663 4664 status = "disabled"; 4665 }; 4666 4667 mdss_edp: edp@aea0000 { 4668 compatible = "qcom,sc7280-edp"; 4669 pinctrl-names = "default"; 4670 pinctrl-0 = <&edp_hot_plug_det>; 4671 4672 reg = <0 0x0aea0000 0 0x200>, 4673 <0 0x0aea0200 0 0x200>, 4674 <0 0x0aea0400 0 0xc00>, 4675 <0 0x0aea1000 0 0x400>; 4676 4677 interrupt-parent = <&mdss>; 4678 interrupts = <14>; 4679 4680 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4681 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 4682 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 4683 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 4684 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 4685 clock-names = "core_iface", 4686 "core_aux", 4687 "ctrl_link", 4688 "ctrl_link_iface", 4689 "stream_pixel"; 4690 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 4691 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 4692 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 4693 4694 phys = <&mdss_edp_phy>; 4695 phy-names = "dp"; 4696 4697 operating-points-v2 = <&edp_opp_table>; 4698 power-domains = <&rpmhpd SC7280_CX>; 4699 4700 status = "disabled"; 4701 4702 ports { 4703 #address-cells = <1>; 4704 #size-cells = <0>; 4705 4706 port@0 { 4707 reg = <0>; 4708 edp_in: endpoint { 4709 remote-endpoint = <&dpu_intf5_out>; 4710 }; 4711 }; 4712 4713 port@1 { 4714 reg = <1>; 4715 mdss_edp_out: endpoint { }; 4716 }; 4717 }; 4718 4719 edp_opp_table: opp-table { 4720 compatible = "operating-points-v2"; 4721 4722 opp-160000000 { 4723 opp-hz = /bits/ 64 <160000000>; 4724 required-opps = <&rpmhpd_opp_low_svs>; 4725 }; 4726 4727 opp-270000000 { 4728 opp-hz = /bits/ 64 <270000000>; 4729 required-opps = <&rpmhpd_opp_svs>; 4730 }; 4731 4732 opp-540000000 { 4733 opp-hz = /bits/ 64 <540000000>; 4734 required-opps = <&rpmhpd_opp_nom>; 4735 }; 4736 4737 opp-810000000 { 4738 opp-hz = /bits/ 64 <810000000>; 4739 required-opps = <&rpmhpd_opp_nom>; 4740 }; 4741 }; 4742 }; 4743 4744 mdss_edp_phy: phy@aec2a00 { 4745 compatible = "qcom,sc7280-edp-phy"; 4746 4747 reg = <0 0x0aec2a00 0 0x19c>, 4748 <0 0x0aec2200 0 0xa0>, 4749 <0 0x0aec2600 0 0xa0>, 4750 <0 0x0aec2000 0 0x1c0>; 4751 4752 clocks = <&rpmhcc RPMH_CXO_CLK>, 4753 <&gcc GCC_EDP_CLKREF_EN>; 4754 clock-names = "aux", 4755 "cfg_ahb"; 4756 4757 #clock-cells = <1>; 4758 #phy-cells = <0>; 4759 4760 status = "disabled"; 4761 }; 4762 4763 mdss_dp: displayport-controller@ae90000 { 4764 compatible = "qcom,sc7280-dp"; 4765 4766 reg = <0 0x0ae90000 0 0x200>, 4767 <0 0x0ae90200 0 0x200>, 4768 <0 0x0ae90400 0 0xc00>, 4769 <0 0x0ae91000 0 0x400>, 4770 <0 0x0ae91400 0 0x400>; 4771 4772 interrupt-parent = <&mdss>; 4773 interrupts = <12>; 4774 4775 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4776 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4777 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4778 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4779 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4780 clock-names = "core_iface", 4781 "core_aux", 4782 "ctrl_link", 4783 "ctrl_link_iface", 4784 "stream_pixel"; 4785 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4786 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4787 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4788 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4789 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 4790 phy-names = "dp"; 4791 4792 operating-points-v2 = <&dp_opp_table>; 4793 power-domains = <&rpmhpd SC7280_CX>; 4794 4795 #sound-dai-cells = <0>; 4796 4797 status = "disabled"; 4798 4799 ports { 4800 #address-cells = <1>; 4801 #size-cells = <0>; 4802 4803 port@0 { 4804 reg = <0>; 4805 dp_in: endpoint { 4806 remote-endpoint = <&dpu_intf0_out>; 4807 }; 4808 }; 4809 4810 port@1 { 4811 reg = <1>; 4812 mdss_dp_out: endpoint { }; 4813 }; 4814 }; 4815 4816 dp_opp_table: opp-table { 4817 compatible = "operating-points-v2"; 4818 4819 opp-160000000 { 4820 opp-hz = /bits/ 64 <160000000>; 4821 required-opps = <&rpmhpd_opp_low_svs>; 4822 }; 4823 4824 opp-270000000 { 4825 opp-hz = /bits/ 64 <270000000>; 4826 required-opps = <&rpmhpd_opp_svs>; 4827 }; 4828 4829 opp-540000000 { 4830 opp-hz = /bits/ 64 <540000000>; 4831 required-opps = <&rpmhpd_opp_svs_l1>; 4832 }; 4833 4834 opp-810000000 { 4835 opp-hz = /bits/ 64 <810000000>; 4836 required-opps = <&rpmhpd_opp_nom>; 4837 }; 4838 }; 4839 }; 4840 }; 4841 4842 pdc: interrupt-controller@b220000 { 4843 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 4844 reg = <0 0x0b220000 0 0x30000>; 4845 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 4846 <55 306 4>, <59 312 3>, <62 374 2>, 4847 <64 434 2>, <66 438 3>, <69 86 1>, 4848 <70 520 54>, <124 609 31>, <155 63 1>, 4849 <156 716 12>; 4850 #interrupt-cells = <2>; 4851 interrupt-parent = <&intc>; 4852 interrupt-controller; 4853 }; 4854 4855 pdc_reset: reset-controller@b5e0000 { 4856 compatible = "qcom,sc7280-pdc-global"; 4857 reg = <0 0x0b5e0000 0 0x20000>; 4858 #reset-cells = <1>; 4859 status = "reserved"; /* Owned by firmware */ 4860 }; 4861 4862 tsens0: thermal-sensor@c263000 { 4863 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4864 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4865 <0 0x0c222000 0 0x1ff>; /* SROT */ 4866 #qcom,sensors = <15>; 4867 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4868 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4869 interrupt-names = "uplow","critical"; 4870 #thermal-sensor-cells = <1>; 4871 }; 4872 4873 tsens1: thermal-sensor@c265000 { 4874 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4875 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4876 <0 0x0c223000 0 0x1ff>; /* SROT */ 4877 #qcom,sensors = <12>; 4878 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4879 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4880 interrupt-names = "uplow","critical"; 4881 #thermal-sensor-cells = <1>; 4882 }; 4883 4884 aoss_reset: reset-controller@c2a0000 { 4885 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 4886 reg = <0 0x0c2a0000 0 0x31000>; 4887 #reset-cells = <1>; 4888 }; 4889 4890 aoss_qmp: power-management@c300000 { 4891 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 4892 reg = <0 0x0c300000 0 0x400>; 4893 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4894 IPCC_MPROC_SIGNAL_GLINK_QMP 4895 IRQ_TYPE_EDGE_RISING>; 4896 mboxes = <&ipcc IPCC_CLIENT_AOP 4897 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4898 4899 #clock-cells = <0>; 4900 }; 4901 4902 sram@c3f0000 { 4903 compatible = "qcom,rpmh-stats"; 4904 reg = <0 0x0c3f0000 0 0x400>; 4905 }; 4906 4907 spmi_bus: spmi@c440000 { 4908 compatible = "qcom,spmi-pmic-arb"; 4909 reg = <0 0x0c440000 0 0x1100>, 4910 <0 0x0c600000 0 0x2000000>, 4911 <0 0x0e600000 0 0x100000>, 4912 <0 0x0e700000 0 0xa0000>, 4913 <0 0x0c40a000 0 0x26000>; 4914 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4915 interrupt-names = "periph_irq"; 4916 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4917 qcom,ee = <0>; 4918 qcom,channel = <0>; 4919 #address-cells = <2>; 4920 #size-cells = <0>; 4921 interrupt-controller; 4922 #interrupt-cells = <4>; 4923 }; 4924 4925 tlmm: pinctrl@f100000 { 4926 compatible = "qcom,sc7280-pinctrl"; 4927 reg = <0 0x0f100000 0 0x300000>; 4928 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4929 gpio-controller; 4930 #gpio-cells = <2>; 4931 interrupt-controller; 4932 #interrupt-cells = <2>; 4933 gpio-ranges = <&tlmm 0 0 175>; 4934 wakeup-parent = <&pdc>; 4935 4936 cci0_default: cci0-default-state { 4937 pins = "gpio69", "gpio70"; 4938 function = "cci_i2c"; 4939 drive-strength = <2>; 4940 bias-pull-up; 4941 }; 4942 4943 cci0_sleep: cci0-sleep-state { 4944 pins = "gpio69", "gpio70"; 4945 function = "cci_i2c"; 4946 drive-strength = <2>; 4947 bias-pull-down; 4948 }; 4949 4950 cci1_default: cci1-default-state { 4951 pins = "gpio71", "gpio72"; 4952 function = "cci_i2c"; 4953 drive-strength = <2>; 4954 bias-pull-up; 4955 }; 4956 4957 cci1_sleep: cci1-sleep-state { 4958 pins = "gpio71", "gpio72"; 4959 function = "cci_i2c"; 4960 drive-strength = <2>; 4961 bias-pull-down; 4962 }; 4963 4964 cci2_default: cci2-default-state { 4965 pins = "gpio73", "gpio74"; 4966 function = "cci_i2c"; 4967 drive-strength = <2>; 4968 bias-pull-up; 4969 }; 4970 4971 cci2_sleep: cci2-sleep-state { 4972 pins = "gpio73", "gpio74"; 4973 function = "cci_i2c"; 4974 drive-strength = <2>; 4975 bias-pull-down; 4976 }; 4977 4978 cci3_default: cci3-default-state { 4979 pins = "gpio75", "gpio76"; 4980 function = "cci_i2c"; 4981 drive-strength = <2>; 4982 bias-pull-up; 4983 }; 4984 4985 cci3_sleep: cci3-sleep-state { 4986 pins = "gpio75", "gpio76"; 4987 function = "cci_i2c"; 4988 drive-strength = <2>; 4989 bias-pull-down; 4990 }; 4991 4992 dp_hot_plug_det: dp-hot-plug-det-state { 4993 pins = "gpio47"; 4994 function = "dp_hot"; 4995 }; 4996 4997 edp_hot_plug_det: edp-hot-plug-det-state { 4998 pins = "gpio60"; 4999 function = "edp_hot"; 5000 }; 5001 5002 mi2s0_data0: mi2s0-data0-state { 5003 pins = "gpio98"; 5004 function = "mi2s0_data0"; 5005 }; 5006 5007 mi2s0_data1: mi2s0-data1-state { 5008 pins = "gpio99"; 5009 function = "mi2s0_data1"; 5010 }; 5011 5012 mi2s0_mclk: mi2s0-mclk-state { 5013 pins = "gpio96"; 5014 function = "pri_mi2s"; 5015 }; 5016 5017 mi2s0_sclk: mi2s0-sclk-state { 5018 pins = "gpio97"; 5019 function = "mi2s0_sck"; 5020 }; 5021 5022 mi2s0_ws: mi2s0-ws-state { 5023 pins = "gpio100"; 5024 function = "mi2s0_ws"; 5025 }; 5026 5027 mi2s1_data0: mi2s1-data0-state { 5028 pins = "gpio107"; 5029 function = "mi2s1_data0"; 5030 }; 5031 5032 mi2s1_sclk: mi2s1-sclk-state { 5033 pins = "gpio106"; 5034 function = "mi2s1_sck"; 5035 }; 5036 5037 mi2s1_ws: mi2s1-ws-state { 5038 pins = "gpio108"; 5039 function = "mi2s1_ws"; 5040 }; 5041 5042 pcie1_clkreq_n: pcie1-clkreq-n-state { 5043 pins = "gpio79"; 5044 function = "pcie1_clkreqn"; 5045 }; 5046 5047 qspi_clk: qspi-clk-state { 5048 pins = "gpio14"; 5049 function = "qspi_clk"; 5050 }; 5051 5052 qspi_cs0: qspi-cs0-state { 5053 pins = "gpio15"; 5054 function = "qspi_cs"; 5055 }; 5056 5057 qspi_cs1: qspi-cs1-state { 5058 pins = "gpio19"; 5059 function = "qspi_cs"; 5060 }; 5061 5062 qspi_data0: qspi-data0-state { 5063 pins = "gpio12"; 5064 function = "qspi_data"; 5065 }; 5066 5067 qspi_data1: qspi-data1-state { 5068 pins = "gpio13"; 5069 function = "qspi_data"; 5070 }; 5071 5072 qspi_data23: qspi-data23-state { 5073 pins = "gpio16", "gpio17"; 5074 function = "qspi_data"; 5075 }; 5076 5077 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 5078 pins = "gpio0", "gpio1"; 5079 function = "qup00"; 5080 }; 5081 5082 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 5083 pins = "gpio4", "gpio5"; 5084 function = "qup01"; 5085 }; 5086 5087 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 5088 pins = "gpio8", "gpio9"; 5089 function = "qup02"; 5090 }; 5091 5092 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 5093 pins = "gpio12", "gpio13"; 5094 function = "qup03"; 5095 }; 5096 5097 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 5098 pins = "gpio16", "gpio17"; 5099 function = "qup04"; 5100 }; 5101 5102 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 5103 pins = "gpio20", "gpio21"; 5104 function = "qup05"; 5105 }; 5106 5107 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 5108 pins = "gpio24", "gpio25"; 5109 function = "qup06"; 5110 }; 5111 5112 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 5113 pins = "gpio28", "gpio29"; 5114 function = "qup07"; 5115 }; 5116 5117 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 5118 pins = "gpio32", "gpio33"; 5119 function = "qup10"; 5120 }; 5121 5122 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 5123 pins = "gpio36", "gpio37"; 5124 function = "qup11"; 5125 }; 5126 5127 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 5128 pins = "gpio40", "gpio41"; 5129 function = "qup12"; 5130 }; 5131 5132 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 5133 pins = "gpio44", "gpio45"; 5134 function = "qup13"; 5135 }; 5136 5137 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 5138 pins = "gpio48", "gpio49"; 5139 function = "qup14"; 5140 }; 5141 5142 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 5143 pins = "gpio52", "gpio53"; 5144 function = "qup15"; 5145 }; 5146 5147 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 5148 pins = "gpio56", "gpio57"; 5149 function = "qup16"; 5150 }; 5151 5152 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 5153 pins = "gpio60", "gpio61"; 5154 function = "qup17"; 5155 }; 5156 5157 qup_spi0_data_clk: qup-spi0-data-clk-state { 5158 pins = "gpio0", "gpio1", "gpio2"; 5159 function = "qup00"; 5160 }; 5161 5162 qup_spi0_cs: qup-spi0-cs-state { 5163 pins = "gpio3"; 5164 function = "qup00"; 5165 }; 5166 5167 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 5168 pins = "gpio3"; 5169 function = "gpio"; 5170 }; 5171 5172 qup_spi1_data_clk: qup-spi1-data-clk-state { 5173 pins = "gpio4", "gpio5", "gpio6"; 5174 function = "qup01"; 5175 }; 5176 5177 qup_spi1_cs: qup-spi1-cs-state { 5178 pins = "gpio7"; 5179 function = "qup01"; 5180 }; 5181 5182 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 5183 pins = "gpio7"; 5184 function = "gpio"; 5185 }; 5186 5187 qup_spi2_data_clk: qup-spi2-data-clk-state { 5188 pins = "gpio8", "gpio9", "gpio10"; 5189 function = "qup02"; 5190 }; 5191 5192 qup_spi2_cs: qup-spi2-cs-state { 5193 pins = "gpio11"; 5194 function = "qup02"; 5195 }; 5196 5197 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 5198 pins = "gpio11"; 5199 function = "gpio"; 5200 }; 5201 5202 qup_spi3_data_clk: qup-spi3-data-clk-state { 5203 pins = "gpio12", "gpio13", "gpio14"; 5204 function = "qup03"; 5205 }; 5206 5207 qup_spi3_cs: qup-spi3-cs-state { 5208 pins = "gpio15"; 5209 function = "qup03"; 5210 }; 5211 5212 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 5213 pins = "gpio15"; 5214 function = "gpio"; 5215 }; 5216 5217 qup_spi4_data_clk: qup-spi4-data-clk-state { 5218 pins = "gpio16", "gpio17", "gpio18"; 5219 function = "qup04"; 5220 }; 5221 5222 qup_spi4_cs: qup-spi4-cs-state { 5223 pins = "gpio19"; 5224 function = "qup04"; 5225 }; 5226 5227 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 5228 pins = "gpio19"; 5229 function = "gpio"; 5230 }; 5231 5232 qup_spi5_data_clk: qup-spi5-data-clk-state { 5233 pins = "gpio20", "gpio21", "gpio22"; 5234 function = "qup05"; 5235 }; 5236 5237 qup_spi5_cs: qup-spi5-cs-state { 5238 pins = "gpio23"; 5239 function = "qup05"; 5240 }; 5241 5242 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 5243 pins = "gpio23"; 5244 function = "gpio"; 5245 }; 5246 5247 qup_spi6_data_clk: qup-spi6-data-clk-state { 5248 pins = "gpio24", "gpio25", "gpio26"; 5249 function = "qup06"; 5250 }; 5251 5252 qup_spi6_cs: qup-spi6-cs-state { 5253 pins = "gpio27"; 5254 function = "qup06"; 5255 }; 5256 5257 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 5258 pins = "gpio27"; 5259 function = "gpio"; 5260 }; 5261 5262 qup_spi7_data_clk: qup-spi7-data-clk-state { 5263 pins = "gpio28", "gpio29", "gpio30"; 5264 function = "qup07"; 5265 }; 5266 5267 qup_spi7_cs: qup-spi7-cs-state { 5268 pins = "gpio31"; 5269 function = "qup07"; 5270 }; 5271 5272 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 5273 pins = "gpio31"; 5274 function = "gpio"; 5275 }; 5276 5277 qup_spi8_data_clk: qup-spi8-data-clk-state { 5278 pins = "gpio32", "gpio33", "gpio34"; 5279 function = "qup10"; 5280 }; 5281 5282 qup_spi8_cs: qup-spi8-cs-state { 5283 pins = "gpio35"; 5284 function = "qup10"; 5285 }; 5286 5287 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 5288 pins = "gpio35"; 5289 function = "gpio"; 5290 }; 5291 5292 qup_spi9_data_clk: qup-spi9-data-clk-state { 5293 pins = "gpio36", "gpio37", "gpio38"; 5294 function = "qup11"; 5295 }; 5296 5297 qup_spi9_cs: qup-spi9-cs-state { 5298 pins = "gpio39"; 5299 function = "qup11"; 5300 }; 5301 5302 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 5303 pins = "gpio39"; 5304 function = "gpio"; 5305 }; 5306 5307 qup_spi10_data_clk: qup-spi10-data-clk-state { 5308 pins = "gpio40", "gpio41", "gpio42"; 5309 function = "qup12"; 5310 }; 5311 5312 qup_spi10_cs: qup-spi10-cs-state { 5313 pins = "gpio43"; 5314 function = "qup12"; 5315 }; 5316 5317 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 5318 pins = "gpio43"; 5319 function = "gpio"; 5320 }; 5321 5322 qup_spi11_data_clk: qup-spi11-data-clk-state { 5323 pins = "gpio44", "gpio45", "gpio46"; 5324 function = "qup13"; 5325 }; 5326 5327 qup_spi11_cs: qup-spi11-cs-state { 5328 pins = "gpio47"; 5329 function = "qup13"; 5330 }; 5331 5332 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 5333 pins = "gpio47"; 5334 function = "gpio"; 5335 }; 5336 5337 qup_spi12_data_clk: qup-spi12-data-clk-state { 5338 pins = "gpio48", "gpio49", "gpio50"; 5339 function = "qup14"; 5340 }; 5341 5342 qup_spi12_cs: qup-spi12-cs-state { 5343 pins = "gpio51"; 5344 function = "qup14"; 5345 }; 5346 5347 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 5348 pins = "gpio51"; 5349 function = "gpio"; 5350 }; 5351 5352 qup_spi13_data_clk: qup-spi13-data-clk-state { 5353 pins = "gpio52", "gpio53", "gpio54"; 5354 function = "qup15"; 5355 }; 5356 5357 qup_spi13_cs: qup-spi13-cs-state { 5358 pins = "gpio55"; 5359 function = "qup15"; 5360 }; 5361 5362 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 5363 pins = "gpio55"; 5364 function = "gpio"; 5365 }; 5366 5367 qup_spi14_data_clk: qup-spi14-data-clk-state { 5368 pins = "gpio56", "gpio57", "gpio58"; 5369 function = "qup16"; 5370 }; 5371 5372 qup_spi14_cs: qup-spi14-cs-state { 5373 pins = "gpio59"; 5374 function = "qup16"; 5375 }; 5376 5377 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 5378 pins = "gpio59"; 5379 function = "gpio"; 5380 }; 5381 5382 qup_spi15_data_clk: qup-spi15-data-clk-state { 5383 pins = "gpio60", "gpio61", "gpio62"; 5384 function = "qup17"; 5385 }; 5386 5387 qup_spi15_cs: qup-spi15-cs-state { 5388 pins = "gpio63"; 5389 function = "qup17"; 5390 }; 5391 5392 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 5393 pins = "gpio63"; 5394 function = "gpio"; 5395 }; 5396 5397 qup_uart0_cts: qup-uart0-cts-state { 5398 pins = "gpio0"; 5399 function = "qup00"; 5400 }; 5401 5402 qup_uart0_rts: qup-uart0-rts-state { 5403 pins = "gpio1"; 5404 function = "qup00"; 5405 }; 5406 5407 qup_uart0_tx: qup-uart0-tx-state { 5408 pins = "gpio2"; 5409 function = "qup00"; 5410 }; 5411 5412 qup_uart0_rx: qup-uart0-rx-state { 5413 pins = "gpio3"; 5414 function = "qup00"; 5415 }; 5416 5417 qup_uart1_cts: qup-uart1-cts-state { 5418 pins = "gpio4"; 5419 function = "qup01"; 5420 }; 5421 5422 qup_uart1_rts: qup-uart1-rts-state { 5423 pins = "gpio5"; 5424 function = "qup01"; 5425 }; 5426 5427 qup_uart1_tx: qup-uart1-tx-state { 5428 pins = "gpio6"; 5429 function = "qup01"; 5430 }; 5431 5432 qup_uart1_rx: qup-uart1-rx-state { 5433 pins = "gpio7"; 5434 function = "qup01"; 5435 }; 5436 5437 qup_uart2_cts: qup-uart2-cts-state { 5438 pins = "gpio8"; 5439 function = "qup02"; 5440 }; 5441 5442 qup_uart2_rts: qup-uart2-rts-state { 5443 pins = "gpio9"; 5444 function = "qup02"; 5445 }; 5446 5447 qup_uart2_tx: qup-uart2-tx-state { 5448 pins = "gpio10"; 5449 function = "qup02"; 5450 }; 5451 5452 qup_uart2_rx: qup-uart2-rx-state { 5453 pins = "gpio11"; 5454 function = "qup02"; 5455 }; 5456 5457 qup_uart3_cts: qup-uart3-cts-state { 5458 pins = "gpio12"; 5459 function = "qup03"; 5460 }; 5461 5462 qup_uart3_rts: qup-uart3-rts-state { 5463 pins = "gpio13"; 5464 function = "qup03"; 5465 }; 5466 5467 qup_uart3_tx: qup-uart3-tx-state { 5468 pins = "gpio14"; 5469 function = "qup03"; 5470 }; 5471 5472 qup_uart3_rx: qup-uart3-rx-state { 5473 pins = "gpio15"; 5474 function = "qup03"; 5475 }; 5476 5477 qup_uart4_cts: qup-uart4-cts-state { 5478 pins = "gpio16"; 5479 function = "qup04"; 5480 }; 5481 5482 qup_uart4_rts: qup-uart4-rts-state { 5483 pins = "gpio17"; 5484 function = "qup04"; 5485 }; 5486 5487 qup_uart4_tx: qup-uart4-tx-state { 5488 pins = "gpio18"; 5489 function = "qup04"; 5490 }; 5491 5492 qup_uart4_rx: qup-uart4-rx-state { 5493 pins = "gpio19"; 5494 function = "qup04"; 5495 }; 5496 5497 qup_uart5_tx: qup-uart5-tx-state { 5498 pins = "gpio22"; 5499 function = "qup05"; 5500 }; 5501 5502 qup_uart5_rx: qup-uart5-rx-state { 5503 pins = "gpio23"; 5504 function = "qup05"; 5505 }; 5506 5507 qup_uart6_cts: qup-uart6-cts-state { 5508 pins = "gpio24"; 5509 function = "qup06"; 5510 }; 5511 5512 qup_uart6_rts: qup-uart6-rts-state { 5513 pins = "gpio25"; 5514 function = "qup06"; 5515 }; 5516 5517 qup_uart6_tx: qup-uart6-tx-state { 5518 pins = "gpio26"; 5519 function = "qup06"; 5520 }; 5521 5522 qup_uart6_rx: qup-uart6-rx-state { 5523 pins = "gpio27"; 5524 function = "qup06"; 5525 }; 5526 5527 qup_uart7_cts: qup-uart7-cts-state { 5528 pins = "gpio28"; 5529 function = "qup07"; 5530 }; 5531 5532 qup_uart7_rts: qup-uart7-rts-state { 5533 pins = "gpio29"; 5534 function = "qup07"; 5535 }; 5536 5537 qup_uart7_tx: qup-uart7-tx-state { 5538 pins = "gpio30"; 5539 function = "qup07"; 5540 }; 5541 5542 qup_uart7_rx: qup-uart7-rx-state { 5543 pins = "gpio31"; 5544 function = "qup07"; 5545 }; 5546 5547 qup_uart8_cts: qup-uart8-cts-state { 5548 pins = "gpio32"; 5549 function = "qup10"; 5550 }; 5551 5552 qup_uart8_rts: qup-uart8-rts-state { 5553 pins = "gpio33"; 5554 function = "qup10"; 5555 }; 5556 5557 qup_uart8_tx: qup-uart8-tx-state { 5558 pins = "gpio34"; 5559 function = "qup10"; 5560 }; 5561 5562 qup_uart8_rx: qup-uart8-rx-state { 5563 pins = "gpio35"; 5564 function = "qup10"; 5565 }; 5566 5567 qup_uart9_cts: qup-uart9-cts-state { 5568 pins = "gpio36"; 5569 function = "qup11"; 5570 }; 5571 5572 qup_uart9_rts: qup-uart9-rts-state { 5573 pins = "gpio37"; 5574 function = "qup11"; 5575 }; 5576 5577 qup_uart9_tx: qup-uart9-tx-state { 5578 pins = "gpio38"; 5579 function = "qup11"; 5580 }; 5581 5582 qup_uart9_rx: qup-uart9-rx-state { 5583 pins = "gpio39"; 5584 function = "qup11"; 5585 }; 5586 5587 qup_uart10_cts: qup-uart10-cts-state { 5588 pins = "gpio40"; 5589 function = "qup12"; 5590 }; 5591 5592 qup_uart10_rts: qup-uart10-rts-state { 5593 pins = "gpio41"; 5594 function = "qup12"; 5595 }; 5596 5597 qup_uart10_tx: qup-uart10-tx-state { 5598 pins = "gpio42"; 5599 function = "qup12"; 5600 }; 5601 5602 qup_uart10_rx: qup-uart10-rx-state { 5603 pins = "gpio43"; 5604 function = "qup12"; 5605 }; 5606 5607 qup_uart11_cts: qup-uart11-cts-state { 5608 pins = "gpio44"; 5609 function = "qup13"; 5610 }; 5611 5612 qup_uart11_rts: qup-uart11-rts-state { 5613 pins = "gpio45"; 5614 function = "qup13"; 5615 }; 5616 5617 qup_uart11_tx: qup-uart11-tx-state { 5618 pins = "gpio46"; 5619 function = "qup13"; 5620 }; 5621 5622 qup_uart11_rx: qup-uart11-rx-state { 5623 pins = "gpio47"; 5624 function = "qup13"; 5625 }; 5626 5627 qup_uart12_cts: qup-uart12-cts-state { 5628 pins = "gpio48"; 5629 function = "qup14"; 5630 }; 5631 5632 qup_uart12_rts: qup-uart12-rts-state { 5633 pins = "gpio49"; 5634 function = "qup14"; 5635 }; 5636 5637 qup_uart12_tx: qup-uart12-tx-state { 5638 pins = "gpio50"; 5639 function = "qup14"; 5640 }; 5641 5642 qup_uart12_rx: qup-uart12-rx-state { 5643 pins = "gpio51"; 5644 function = "qup14"; 5645 }; 5646 5647 qup_uart13_cts: qup-uart13-cts-state { 5648 pins = "gpio52"; 5649 function = "qup15"; 5650 }; 5651 5652 qup_uart13_rts: qup-uart13-rts-state { 5653 pins = "gpio53"; 5654 function = "qup15"; 5655 }; 5656 5657 qup_uart13_tx: qup-uart13-tx-state { 5658 pins = "gpio54"; 5659 function = "qup15"; 5660 }; 5661 5662 qup_uart13_rx: qup-uart13-rx-state { 5663 pins = "gpio55"; 5664 function = "qup15"; 5665 }; 5666 5667 qup_uart14_cts: qup-uart14-cts-state { 5668 pins = "gpio56"; 5669 function = "qup16"; 5670 }; 5671 5672 qup_uart14_rts: qup-uart14-rts-state { 5673 pins = "gpio57"; 5674 function = "qup16"; 5675 }; 5676 5677 qup_uart14_tx: qup-uart14-tx-state { 5678 pins = "gpio58"; 5679 function = "qup16"; 5680 }; 5681 5682 qup_uart14_rx: qup-uart14-rx-state { 5683 pins = "gpio59"; 5684 function = "qup16"; 5685 }; 5686 5687 qup_uart15_cts: qup-uart15-cts-state { 5688 pins = "gpio60"; 5689 function = "qup17"; 5690 }; 5691 5692 qup_uart15_rts: qup-uart15-rts-state { 5693 pins = "gpio61"; 5694 function = "qup17"; 5695 }; 5696 5697 qup_uart15_tx: qup-uart15-tx-state { 5698 pins = "gpio62"; 5699 function = "qup17"; 5700 }; 5701 5702 qup_uart15_rx: qup-uart15-rx-state { 5703 pins = "gpio63"; 5704 function = "qup17"; 5705 }; 5706 5707 sdc1_clk: sdc1-clk-state { 5708 pins = "sdc1_clk"; 5709 }; 5710 5711 sdc1_cmd: sdc1-cmd-state { 5712 pins = "sdc1_cmd"; 5713 }; 5714 5715 sdc1_data: sdc1-data-state { 5716 pins = "sdc1_data"; 5717 }; 5718 5719 sdc1_rclk: sdc1-rclk-state { 5720 pins = "sdc1_rclk"; 5721 }; 5722 5723 sdc1_clk_sleep: sdc1-clk-sleep-state { 5724 pins = "sdc1_clk"; 5725 drive-strength = <2>; 5726 bias-bus-hold; 5727 }; 5728 5729 sdc1_cmd_sleep: sdc1-cmd-sleep-state { 5730 pins = "sdc1_cmd"; 5731 drive-strength = <2>; 5732 bias-bus-hold; 5733 }; 5734 5735 sdc1_data_sleep: sdc1-data-sleep-state { 5736 pins = "sdc1_data"; 5737 drive-strength = <2>; 5738 bias-bus-hold; 5739 }; 5740 5741 sdc1_rclk_sleep: sdc1-rclk-sleep-state { 5742 pins = "sdc1_rclk"; 5743 drive-strength = <2>; 5744 bias-bus-hold; 5745 }; 5746 5747 sdc2_clk: sdc2-clk-state { 5748 pins = "sdc2_clk"; 5749 }; 5750 5751 sdc2_cmd: sdc2-cmd-state { 5752 pins = "sdc2_cmd"; 5753 }; 5754 5755 sdc2_data: sdc2-data-state { 5756 pins = "sdc2_data"; 5757 }; 5758 5759 sdc2_clk_sleep: sdc2-clk-sleep-state { 5760 pins = "sdc2_clk"; 5761 drive-strength = <2>; 5762 bias-bus-hold; 5763 }; 5764 5765 sdc2_cmd_sleep: sdc2-cmd-sleep-state { 5766 pins = "sdc2_cmd"; 5767 drive-strength = <2>; 5768 bias-bus-hold; 5769 }; 5770 5771 sdc2_data_sleep: sdc2-data-sleep-state { 5772 pins = "sdc2_data"; 5773 drive-strength = <2>; 5774 bias-bus-hold; 5775 }; 5776 }; 5777 5778 sram@146a5000 { 5779 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 5780 reg = <0 0x146a5000 0 0x6000>; 5781 5782 #address-cells = <1>; 5783 #size-cells = <1>; 5784 5785 ranges = <0 0 0x146a5000 0x6000>; 5786 5787 pil-reloc@594c { 5788 compatible = "qcom,pil-reloc-info"; 5789 reg = <0x594c 0xc8>; 5790 }; 5791 }; 5792 5793 apps_smmu: iommu@15000000 { 5794 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 5795 reg = <0 0x15000000 0 0x100000>; 5796 #iommu-cells = <2>; 5797 #global-interrupts = <1>; 5798 dma-coherent; 5799 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5800 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5801 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5802 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5803 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5804 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5805 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5806 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5807 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5808 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5809 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5810 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5811 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5812 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5813 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5814 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5815 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5816 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5817 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5818 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5819 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5820 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5821 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5822 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5823 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5824 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5825 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5826 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5827 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5828 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5829 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5830 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5831 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5832 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5833 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5834 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5835 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5836 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5837 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5838 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5839 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5840 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5841 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5842 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5843 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5844 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5845 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5846 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5847 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5848 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5849 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5850 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5851 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5852 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5853 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5854 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5855 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5856 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5857 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5858 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5859 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5860 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5861 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5862 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5863 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5864 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5865 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5866 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5867 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5868 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5869 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5870 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5871 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5872 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5873 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5874 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5875 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5876 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5877 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5878 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5879 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 5880 }; 5881 5882 anoc_1_tbu: tbu@151dd000 { 5883 compatible = "qcom,sc7280-tbu"; 5884 reg = <0x0 0x151dd000 0x0 0x1000>; 5885 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5886 &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>; 5887 qcom,stream-id-range = <&apps_smmu 0x0 0x400>; 5888 }; 5889 5890 anoc_2_tbu: tbu@151e1000 { 5891 compatible = "qcom,sc7280-tbu"; 5892 reg = <0x0 0x151e1000 0x0 0x1000>; 5893 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5894 &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>; 5895 qcom,stream-id-range = <&apps_smmu 0x400 0x400>; 5896 }; 5897 5898 mnoc_hf_0_tbu: tbu@151e5000 { 5899 compatible = "qcom,sc7280-tbu"; 5900 reg = <0x0 0x151e5000 0x0 0x1000>; 5901 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY 5902 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5903 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC>; 5904 qcom,stream-id-range = <&apps_smmu 0x800 0x400>; 5905 }; 5906 5907 mnoc_hf_1_tbu: tbu@151e9000 { 5908 compatible = "qcom,sc7280-tbu"; 5909 reg = <0x0 0x151e9000 0x0 0x1000>; 5910 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY 5911 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5912 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC>; 5913 qcom,stream-id-range = <&apps_smmu 0xc00 0x400>; 5914 }; 5915 5916 compute_dsp_1_tbu: tbu@151ed000 { 5917 compatible = "qcom,sc7280-tbu"; 5918 reg = <0x0 0x151ed000 0x0 0x1000>; 5919 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5920 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5921 power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU1_GDSC>; 5922 qcom,stream-id-range = <&apps_smmu 0x1000 0x400>; 5923 }; 5924 5925 compute_dsp_0_tbu: tbu@151f1000 { 5926 compatible = "qcom,sc7280-tbu"; 5927 reg = <0x0 0x151f1000 0x0 0x1000>; 5928 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5929 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5930 power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC>; 5931 qcom,stream-id-range = <&apps_smmu 0x1400 0x400>; 5932 }; 5933 5934 adsp_tbu: tbu@151f5000 { 5935 compatible = "qcom,sc7280-tbu"; 5936 reg = <0x0 0x151f5000 0x0 0x1000>; 5937 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5938 &lpass_ag_noc SLAVE_LPASS_CORE_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5939 qcom,stream-id-range = <&apps_smmu 0x1800 0x400>; 5940 }; 5941 5942 anoc_1_pcie_tbu: tbu@151f9000 { 5943 compatible = "qcom,sc7280-tbu"; 5944 reg = <0x0 0x151f9000 0x0 0x1000>; 5945 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5946 &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>; 5947 qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>; 5948 }; 5949 5950 mnoc_sf_0_tbu: tbu@151fd000 { 5951 compatible = "qcom,sc7280-tbu"; 5952 reg = <0x0 0x151fd000 0x0 0x1000>; 5953 interconnects = <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ACTIVE_ONLY 5954 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5955 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC>; 5956 qcom,stream-id-range = <&apps_smmu 0x2000 0x400>; 5957 }; 5958 5959 intc: interrupt-controller@17a00000 { 5960 compatible = "arm,gic-v3"; 5961 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5962 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5963 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 5964 #interrupt-cells = <3>; 5965 interrupt-controller; 5966 #address-cells = <2>; 5967 #size-cells = <2>; 5968 ranges; 5969 5970 msi-controller@17a40000 { 5971 compatible = "arm,gic-v3-its"; 5972 reg = <0 0x17a40000 0 0x20000>; 5973 msi-controller; 5974 #msi-cells = <1>; 5975 status = "disabled"; 5976 }; 5977 }; 5978 5979 watchdog: watchdog@17c10000 { 5980 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 5981 reg = <0 0x17c10000 0 0x1000>; 5982 clocks = <&sleep_clk>; 5983 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 5984 status = "reserved"; /* Owned by Gunyah hyp */ 5985 }; 5986 5987 timer@17c20000 { 5988 #address-cells = <1>; 5989 #size-cells = <1>; 5990 ranges = <0 0 0 0x20000000>; 5991 compatible = "arm,armv7-timer-mem"; 5992 reg = <0 0x17c20000 0 0x1000>; 5993 5994 frame@17c21000 { 5995 frame-number = <0>; 5996 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5997 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5998 reg = <0x17c21000 0x1000>, 5999 <0x17c22000 0x1000>; 6000 }; 6001 6002 frame@17c23000 { 6003 frame-number = <1>; 6004 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 6005 reg = <0x17c23000 0x1000>; 6006 status = "disabled"; 6007 }; 6008 6009 frame@17c25000 { 6010 frame-number = <2>; 6011 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 6012 reg = <0x17c25000 0x1000>; 6013 status = "disabled"; 6014 }; 6015 6016 frame@17c27000 { 6017 frame-number = <3>; 6018 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 6019 reg = <0x17c27000 0x1000>; 6020 status = "disabled"; 6021 }; 6022 6023 frame@17c29000 { 6024 frame-number = <4>; 6025 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 6026 reg = <0x17c29000 0x1000>; 6027 status = "disabled"; 6028 }; 6029 6030 frame@17c2b000 { 6031 frame-number = <5>; 6032 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 6033 reg = <0x17c2b000 0x1000>; 6034 status = "disabled"; 6035 }; 6036 6037 frame@17c2d000 { 6038 frame-number = <6>; 6039 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 6040 reg = <0x17c2d000 0x1000>; 6041 status = "disabled"; 6042 }; 6043 }; 6044 6045 apps_rsc: rsc@18200000 { 6046 compatible = "qcom,rpmh-rsc"; 6047 reg = <0 0x18200000 0 0x10000>, 6048 <0 0x18210000 0 0x10000>, 6049 <0 0x18220000 0 0x10000>; 6050 reg-names = "drv-0", "drv-1", "drv-2"; 6051 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 6052 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 6053 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 6054 qcom,tcs-offset = <0xd00>; 6055 qcom,drv-id = <2>; 6056 qcom,tcs-config = <ACTIVE_TCS 2>, 6057 <SLEEP_TCS 3>, 6058 <WAKE_TCS 3>, 6059 <CONTROL_TCS 1>; 6060 power-domains = <&CLUSTER_PD>; 6061 6062 apps_bcm_voter: bcm-voter { 6063 compatible = "qcom,bcm-voter"; 6064 }; 6065 6066 rpmhpd: power-controller { 6067 compatible = "qcom,sc7280-rpmhpd"; 6068 #power-domain-cells = <1>; 6069 operating-points-v2 = <&rpmhpd_opp_table>; 6070 6071 rpmhpd_opp_table: opp-table { 6072 compatible = "operating-points-v2"; 6073 6074 rpmhpd_opp_ret: opp1 { 6075 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 6076 }; 6077 6078 rpmhpd_opp_low_svs: opp2 { 6079 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 6080 }; 6081 6082 rpmhpd_opp_svs: opp3 { 6083 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 6084 }; 6085 6086 rpmhpd_opp_svs_l1: opp4 { 6087 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 6088 }; 6089 6090 rpmhpd_opp_svs_l2: opp5 { 6091 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 6092 }; 6093 6094 rpmhpd_opp_nom: opp6 { 6095 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 6096 }; 6097 6098 rpmhpd_opp_nom_l1: opp7 { 6099 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 6100 }; 6101 6102 rpmhpd_opp_turbo: opp8 { 6103 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 6104 }; 6105 6106 rpmhpd_opp_turbo_l1: opp9 { 6107 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 6108 }; 6109 }; 6110 }; 6111 6112 rpmhcc: clock-controller { 6113 compatible = "qcom,sc7280-rpmh-clk"; 6114 clocks = <&xo_board>; 6115 clock-names = "xo"; 6116 #clock-cells = <1>; 6117 }; 6118 }; 6119 6120 epss_l3: interconnect@18590000 { 6121 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3"; 6122 reg = <0 0x18590000 0 0x1000>; 6123 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6124 clock-names = "xo", "alternate"; 6125 #interconnect-cells = <1>; 6126 }; 6127 6128 cpufreq_hw: cpufreq@18591000 { 6129 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss"; 6130 reg = <0 0x18591000 0 0x1000>, 6131 <0 0x18592000 0 0x1000>, 6132 <0 0x18593000 0 0x1000>; 6133 6134 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 6135 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 6136 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 6137 interrupt-names = "dcvsh-irq-0", 6138 "dcvsh-irq-1", 6139 "dcvsh-irq-2"; 6140 6141 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6142 clock-names = "xo", "alternate"; 6143 #freq-domain-cells = <1>; 6144 #clock-cells = <1>; 6145 }; 6146 }; 6147 6148 sound: sound { 6149 }; 6150 6151 thermal_zones: thermal-zones { 6152 cpu0-thermal { 6153 polling-delay-passive = <250>; 6154 6155 thermal-sensors = <&tsens0 1>; 6156 6157 trips { 6158 cpu0_alert0: trip-point0 { 6159 temperature = <90000>; 6160 hysteresis = <2000>; 6161 type = "passive"; 6162 }; 6163 6164 cpu0_alert1: trip-point1 { 6165 temperature = <95000>; 6166 hysteresis = <2000>; 6167 type = "passive"; 6168 }; 6169 6170 cpu0_crit: cpu-crit { 6171 temperature = <110000>; 6172 hysteresis = <0>; 6173 type = "critical"; 6174 }; 6175 }; 6176 6177 cooling-maps { 6178 map0 { 6179 trip = <&cpu0_alert0>; 6180 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6181 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6182 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6183 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6184 }; 6185 map1 { 6186 trip = <&cpu0_alert1>; 6187 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6188 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6189 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6190 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6191 }; 6192 }; 6193 }; 6194 6195 cpu1-thermal { 6196 polling-delay-passive = <250>; 6197 6198 thermal-sensors = <&tsens0 2>; 6199 6200 trips { 6201 cpu1_alert0: trip-point0 { 6202 temperature = <90000>; 6203 hysteresis = <2000>; 6204 type = "passive"; 6205 }; 6206 6207 cpu1_alert1: trip-point1 { 6208 temperature = <95000>; 6209 hysteresis = <2000>; 6210 type = "passive"; 6211 }; 6212 6213 cpu1_crit: cpu-crit { 6214 temperature = <110000>; 6215 hysteresis = <0>; 6216 type = "critical"; 6217 }; 6218 }; 6219 6220 cooling-maps { 6221 map0 { 6222 trip = <&cpu1_alert0>; 6223 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6224 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6225 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6226 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6227 }; 6228 map1 { 6229 trip = <&cpu1_alert1>; 6230 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6231 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6232 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6233 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6234 }; 6235 }; 6236 }; 6237 6238 cpu2-thermal { 6239 polling-delay-passive = <250>; 6240 6241 thermal-sensors = <&tsens0 3>; 6242 6243 trips { 6244 cpu2_alert0: trip-point0 { 6245 temperature = <90000>; 6246 hysteresis = <2000>; 6247 type = "passive"; 6248 }; 6249 6250 cpu2_alert1: trip-point1 { 6251 temperature = <95000>; 6252 hysteresis = <2000>; 6253 type = "passive"; 6254 }; 6255 6256 cpu2_crit: cpu-crit { 6257 temperature = <110000>; 6258 hysteresis = <0>; 6259 type = "critical"; 6260 }; 6261 }; 6262 6263 cooling-maps { 6264 map0 { 6265 trip = <&cpu2_alert0>; 6266 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6267 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6268 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6269 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6270 }; 6271 map1 { 6272 trip = <&cpu2_alert1>; 6273 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6274 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6275 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6276 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6277 }; 6278 }; 6279 }; 6280 6281 cpu3-thermal { 6282 polling-delay-passive = <250>; 6283 6284 thermal-sensors = <&tsens0 4>; 6285 6286 trips { 6287 cpu3_alert0: trip-point0 { 6288 temperature = <90000>; 6289 hysteresis = <2000>; 6290 type = "passive"; 6291 }; 6292 6293 cpu3_alert1: trip-point1 { 6294 temperature = <95000>; 6295 hysteresis = <2000>; 6296 type = "passive"; 6297 }; 6298 6299 cpu3_crit: cpu-crit { 6300 temperature = <110000>; 6301 hysteresis = <0>; 6302 type = "critical"; 6303 }; 6304 }; 6305 6306 cooling-maps { 6307 map0 { 6308 trip = <&cpu3_alert0>; 6309 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6310 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6311 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6312 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6313 }; 6314 map1 { 6315 trip = <&cpu3_alert1>; 6316 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6317 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6318 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6319 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6320 }; 6321 }; 6322 }; 6323 6324 cpu4-thermal { 6325 polling-delay-passive = <250>; 6326 6327 thermal-sensors = <&tsens0 7>; 6328 6329 trips { 6330 cpu4_alert0: trip-point0 { 6331 temperature = <90000>; 6332 hysteresis = <2000>; 6333 type = "passive"; 6334 }; 6335 6336 cpu4_alert1: trip-point1 { 6337 temperature = <95000>; 6338 hysteresis = <2000>; 6339 type = "passive"; 6340 }; 6341 6342 cpu4_crit: cpu-crit { 6343 temperature = <110000>; 6344 hysteresis = <0>; 6345 type = "critical"; 6346 }; 6347 }; 6348 6349 cooling-maps { 6350 map0 { 6351 trip = <&cpu4_alert0>; 6352 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6353 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6354 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6355 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6356 }; 6357 map1 { 6358 trip = <&cpu4_alert1>; 6359 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6360 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6361 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6362 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6363 }; 6364 }; 6365 }; 6366 6367 cpu5-thermal { 6368 polling-delay-passive = <250>; 6369 6370 thermal-sensors = <&tsens0 8>; 6371 6372 trips { 6373 cpu5_alert0: trip-point0 { 6374 temperature = <90000>; 6375 hysteresis = <2000>; 6376 type = "passive"; 6377 }; 6378 6379 cpu5_alert1: trip-point1 { 6380 temperature = <95000>; 6381 hysteresis = <2000>; 6382 type = "passive"; 6383 }; 6384 6385 cpu5_crit: cpu-crit { 6386 temperature = <110000>; 6387 hysteresis = <0>; 6388 type = "critical"; 6389 }; 6390 }; 6391 6392 cooling-maps { 6393 map0 { 6394 trip = <&cpu5_alert0>; 6395 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6396 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6397 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6398 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6399 }; 6400 map1 { 6401 trip = <&cpu5_alert1>; 6402 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6403 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6404 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6405 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6406 }; 6407 }; 6408 }; 6409 6410 cpu6-thermal { 6411 polling-delay-passive = <250>; 6412 6413 thermal-sensors = <&tsens0 9>; 6414 6415 trips { 6416 cpu6_alert0: trip-point0 { 6417 temperature = <90000>; 6418 hysteresis = <2000>; 6419 type = "passive"; 6420 }; 6421 6422 cpu6_alert1: trip-point1 { 6423 temperature = <95000>; 6424 hysteresis = <2000>; 6425 type = "passive"; 6426 }; 6427 6428 cpu6_crit: cpu-crit { 6429 temperature = <110000>; 6430 hysteresis = <0>; 6431 type = "critical"; 6432 }; 6433 }; 6434 6435 cooling-maps { 6436 map0 { 6437 trip = <&cpu6_alert0>; 6438 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6439 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6440 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6441 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6442 }; 6443 map1 { 6444 trip = <&cpu6_alert1>; 6445 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6446 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6447 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6448 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6449 }; 6450 }; 6451 }; 6452 6453 cpu7-thermal { 6454 polling-delay-passive = <250>; 6455 6456 thermal-sensors = <&tsens0 10>; 6457 6458 trips { 6459 cpu7_alert0: trip-point0 { 6460 temperature = <90000>; 6461 hysteresis = <2000>; 6462 type = "passive"; 6463 }; 6464 6465 cpu7_alert1: trip-point1 { 6466 temperature = <95000>; 6467 hysteresis = <2000>; 6468 type = "passive"; 6469 }; 6470 6471 cpu7_crit: cpu-crit { 6472 temperature = <110000>; 6473 hysteresis = <0>; 6474 type = "critical"; 6475 }; 6476 }; 6477 6478 cooling-maps { 6479 map0 { 6480 trip = <&cpu7_alert0>; 6481 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6482 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6483 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6484 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6485 }; 6486 map1 { 6487 trip = <&cpu7_alert1>; 6488 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6489 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6490 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6491 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6492 }; 6493 }; 6494 }; 6495 6496 cpu8-thermal { 6497 polling-delay-passive = <250>; 6498 6499 thermal-sensors = <&tsens0 11>; 6500 6501 trips { 6502 cpu8_alert0: trip-point0 { 6503 temperature = <90000>; 6504 hysteresis = <2000>; 6505 type = "passive"; 6506 }; 6507 6508 cpu8_alert1: trip-point1 { 6509 temperature = <95000>; 6510 hysteresis = <2000>; 6511 type = "passive"; 6512 }; 6513 6514 cpu8_crit: cpu-crit { 6515 temperature = <110000>; 6516 hysteresis = <0>; 6517 type = "critical"; 6518 }; 6519 }; 6520 6521 cooling-maps { 6522 map0 { 6523 trip = <&cpu8_alert0>; 6524 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6525 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6526 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6527 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6528 }; 6529 map1 { 6530 trip = <&cpu8_alert1>; 6531 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6532 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6533 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6534 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6535 }; 6536 }; 6537 }; 6538 6539 cpu9-thermal { 6540 polling-delay-passive = <250>; 6541 6542 thermal-sensors = <&tsens0 12>; 6543 6544 trips { 6545 cpu9_alert0: trip-point0 { 6546 temperature = <90000>; 6547 hysteresis = <2000>; 6548 type = "passive"; 6549 }; 6550 6551 cpu9_alert1: trip-point1 { 6552 temperature = <95000>; 6553 hysteresis = <2000>; 6554 type = "passive"; 6555 }; 6556 6557 cpu9_crit: cpu-crit { 6558 temperature = <110000>; 6559 hysteresis = <0>; 6560 type = "critical"; 6561 }; 6562 }; 6563 6564 cooling-maps { 6565 map0 { 6566 trip = <&cpu9_alert0>; 6567 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6568 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6569 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6570 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6571 }; 6572 map1 { 6573 trip = <&cpu9_alert1>; 6574 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6575 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6576 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6577 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6578 }; 6579 }; 6580 }; 6581 6582 cpu10-thermal { 6583 polling-delay-passive = <250>; 6584 6585 thermal-sensors = <&tsens0 13>; 6586 6587 trips { 6588 cpu10_alert0: trip-point0 { 6589 temperature = <90000>; 6590 hysteresis = <2000>; 6591 type = "passive"; 6592 }; 6593 6594 cpu10_alert1: trip-point1 { 6595 temperature = <95000>; 6596 hysteresis = <2000>; 6597 type = "passive"; 6598 }; 6599 6600 cpu10_crit: cpu-crit { 6601 temperature = <110000>; 6602 hysteresis = <0>; 6603 type = "critical"; 6604 }; 6605 }; 6606 6607 cooling-maps { 6608 map0 { 6609 trip = <&cpu10_alert0>; 6610 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6611 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6612 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6613 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6614 }; 6615 map1 { 6616 trip = <&cpu10_alert1>; 6617 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6618 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6619 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6620 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6621 }; 6622 }; 6623 }; 6624 6625 cpu11-thermal { 6626 polling-delay-passive = <250>; 6627 6628 thermal-sensors = <&tsens0 14>; 6629 6630 trips { 6631 cpu11_alert0: trip-point0 { 6632 temperature = <90000>; 6633 hysteresis = <2000>; 6634 type = "passive"; 6635 }; 6636 6637 cpu11_alert1: trip-point1 { 6638 temperature = <95000>; 6639 hysteresis = <2000>; 6640 type = "passive"; 6641 }; 6642 6643 cpu11_crit: cpu-crit { 6644 temperature = <110000>; 6645 hysteresis = <0>; 6646 type = "critical"; 6647 }; 6648 }; 6649 6650 cooling-maps { 6651 map0 { 6652 trip = <&cpu11_alert0>; 6653 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6654 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6655 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6656 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6657 }; 6658 map1 { 6659 trip = <&cpu11_alert1>; 6660 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6661 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6662 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6663 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6664 }; 6665 }; 6666 }; 6667 6668 aoss0-thermal { 6669 polling-delay-passive = <0>; 6670 6671 thermal-sensors = <&tsens0 0>; 6672 6673 trips { 6674 aoss0_alert0: trip-point0 { 6675 temperature = <90000>; 6676 hysteresis = <2000>; 6677 type = "hot"; 6678 }; 6679 6680 aoss0_crit: aoss0-crit { 6681 temperature = <110000>; 6682 hysteresis = <0>; 6683 type = "critical"; 6684 }; 6685 }; 6686 }; 6687 6688 aoss1-thermal { 6689 polling-delay-passive = <0>; 6690 6691 thermal-sensors = <&tsens1 0>; 6692 6693 trips { 6694 aoss1_alert0: trip-point0 { 6695 temperature = <90000>; 6696 hysteresis = <2000>; 6697 type = "hot"; 6698 }; 6699 6700 aoss1_crit: aoss1-crit { 6701 temperature = <110000>; 6702 hysteresis = <0>; 6703 type = "critical"; 6704 }; 6705 }; 6706 }; 6707 6708 cpuss0-thermal { 6709 polling-delay-passive = <0>; 6710 6711 thermal-sensors = <&tsens0 5>; 6712 6713 trips { 6714 cpuss0_alert0: trip-point0 { 6715 temperature = <90000>; 6716 hysteresis = <2000>; 6717 type = "hot"; 6718 }; 6719 cpuss0_crit: cluster0-crit { 6720 temperature = <110000>; 6721 hysteresis = <0>; 6722 type = "critical"; 6723 }; 6724 }; 6725 }; 6726 6727 cpuss1-thermal { 6728 polling-delay-passive = <0>; 6729 6730 thermal-sensors = <&tsens0 6>; 6731 6732 trips { 6733 cpuss1_alert0: trip-point0 { 6734 temperature = <90000>; 6735 hysteresis = <2000>; 6736 type = "hot"; 6737 }; 6738 cpuss1_crit: cluster0-crit { 6739 temperature = <110000>; 6740 hysteresis = <0>; 6741 type = "critical"; 6742 }; 6743 }; 6744 }; 6745 6746 gpuss0-thermal { 6747 polling-delay-passive = <100>; 6748 6749 thermal-sensors = <&tsens1 1>; 6750 6751 trips { 6752 gpuss0_alert0: trip-point0 { 6753 temperature = <95000>; 6754 hysteresis = <2000>; 6755 type = "passive"; 6756 }; 6757 6758 gpuss0_crit: gpuss0-crit { 6759 temperature = <110000>; 6760 hysteresis = <0>; 6761 type = "critical"; 6762 }; 6763 }; 6764 6765 cooling-maps { 6766 map0 { 6767 trip = <&gpuss0_alert0>; 6768 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6769 }; 6770 }; 6771 }; 6772 6773 gpuss1-thermal { 6774 polling-delay-passive = <100>; 6775 6776 thermal-sensors = <&tsens1 2>; 6777 6778 trips { 6779 gpuss1_alert0: trip-point0 { 6780 temperature = <95000>; 6781 hysteresis = <2000>; 6782 type = "passive"; 6783 }; 6784 6785 gpuss1_crit: gpuss1-crit { 6786 temperature = <110000>; 6787 hysteresis = <0>; 6788 type = "critical"; 6789 }; 6790 }; 6791 6792 cooling-maps { 6793 map0 { 6794 trip = <&gpuss1_alert0>; 6795 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6796 }; 6797 }; 6798 }; 6799 6800 nspss0-thermal { 6801 thermal-sensors = <&tsens1 3>; 6802 6803 trips { 6804 nspss0_alert0: trip-point0 { 6805 temperature = <90000>; 6806 hysteresis = <2000>; 6807 type = "hot"; 6808 }; 6809 6810 nspss0_crit: nspss0-crit { 6811 temperature = <110000>; 6812 hysteresis = <0>; 6813 type = "critical"; 6814 }; 6815 }; 6816 }; 6817 6818 nspss1-thermal { 6819 thermal-sensors = <&tsens1 4>; 6820 6821 trips { 6822 nspss1_alert0: trip-point0 { 6823 temperature = <90000>; 6824 hysteresis = <2000>; 6825 type = "hot"; 6826 }; 6827 6828 nspss1_crit: nspss1-crit { 6829 temperature = <110000>; 6830 hysteresis = <0>; 6831 type = "critical"; 6832 }; 6833 }; 6834 }; 6835 6836 video-thermal { 6837 thermal-sensors = <&tsens1 5>; 6838 6839 trips { 6840 video_alert0: trip-point0 { 6841 temperature = <90000>; 6842 hysteresis = <2000>; 6843 type = "hot"; 6844 }; 6845 6846 video_crit: video-crit { 6847 temperature = <110000>; 6848 hysteresis = <0>; 6849 type = "critical"; 6850 }; 6851 }; 6852 }; 6853 6854 ddr-thermal { 6855 thermal-sensors = <&tsens1 6>; 6856 6857 trips { 6858 ddr_alert0: trip-point0 { 6859 temperature = <90000>; 6860 hysteresis = <2000>; 6861 type = "hot"; 6862 }; 6863 6864 ddr_crit: ddr-crit { 6865 temperature = <110000>; 6866 hysteresis = <0>; 6867 type = "critical"; 6868 }; 6869 }; 6870 }; 6871 6872 mdmss0-thermal { 6873 thermal-sensors = <&tsens1 7>; 6874 6875 trips { 6876 mdmss0_alert0: trip-point0 { 6877 temperature = <90000>; 6878 hysteresis = <2000>; 6879 type = "hot"; 6880 }; 6881 6882 mdmss0_crit: mdmss0-crit { 6883 temperature = <110000>; 6884 hysteresis = <0>; 6885 type = "critical"; 6886 }; 6887 }; 6888 }; 6889 6890 mdmss1-thermal { 6891 thermal-sensors = <&tsens1 8>; 6892 6893 trips { 6894 mdmss1_alert0: trip-point0 { 6895 temperature = <90000>; 6896 hysteresis = <2000>; 6897 type = "hot"; 6898 }; 6899 6900 mdmss1_crit: mdmss1-crit { 6901 temperature = <110000>; 6902 hysteresis = <0>; 6903 type = "critical"; 6904 }; 6905 }; 6906 }; 6907 6908 mdmss2-thermal { 6909 thermal-sensors = <&tsens1 9>; 6910 6911 trips { 6912 mdmss2_alert0: trip-point0 { 6913 temperature = <90000>; 6914 hysteresis = <2000>; 6915 type = "hot"; 6916 }; 6917 6918 mdmss2_crit: mdmss2-crit { 6919 temperature = <110000>; 6920 hysteresis = <0>; 6921 type = "critical"; 6922 }; 6923 }; 6924 }; 6925 6926 mdmss3-thermal { 6927 thermal-sensors = <&tsens1 10>; 6928 6929 trips { 6930 mdmss3_alert0: trip-point0 { 6931 temperature = <90000>; 6932 hysteresis = <2000>; 6933 type = "hot"; 6934 }; 6935 6936 mdmss3_crit: mdmss3-crit { 6937 temperature = <110000>; 6938 hysteresis = <0>; 6939 type = "critical"; 6940 }; 6941 }; 6942 }; 6943 6944 camera0-thermal { 6945 thermal-sensors = <&tsens1 11>; 6946 6947 trips { 6948 camera0_alert0: trip-point0 { 6949 temperature = <90000>; 6950 hysteresis = <2000>; 6951 type = "hot"; 6952 }; 6953 6954 camera0_crit: camera0-crit { 6955 temperature = <110000>; 6956 hysteresis = <0>; 6957 type = "critical"; 6958 }; 6959 }; 6960 }; 6961 }; 6962 6963 timer { 6964 compatible = "arm,armv8-timer"; 6965 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6966 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6967 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6968 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6969 }; 6970}; 6971