1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/firmware/qcom,scm.h> 17#include <dt-bindings/gpio/gpio.h> 18#include <dt-bindings/interconnect/qcom,osm-l3.h> 19#include <dt-bindings/interconnect/qcom,sc7280.h> 20#include <dt-bindings/interrupt-controller/arm-gic.h> 21#include <dt-bindings/mailbox/qcom-ipcc.h> 22#include <dt-bindings/phy/phy-qcom-qmp.h> 23#include <dt-bindings/power/qcom-rpmpd.h> 24#include <dt-bindings/reset/qcom,sdm845-aoss.h> 25#include <dt-bindings/reset/qcom,sdm845-pdc.h> 26#include <dt-bindings/soc/qcom,rpmh-rsc.h> 27#include <dt-bindings/sound/qcom,lpass.h> 28#include <dt-bindings/thermal/thermal.h> 29 30/ { 31 interrupt-parent = <&intc>; 32 33 #address-cells = <2>; 34 #size-cells = <2>; 35 36 chosen { }; 37 38 aliases { 39 i2c0 = &i2c0; 40 i2c1 = &i2c1; 41 i2c2 = &i2c2; 42 i2c3 = &i2c3; 43 i2c4 = &i2c4; 44 i2c5 = &i2c5; 45 i2c6 = &i2c6; 46 i2c7 = &i2c7; 47 i2c8 = &i2c8; 48 i2c9 = &i2c9; 49 i2c10 = &i2c10; 50 i2c11 = &i2c11; 51 i2c12 = &i2c12; 52 i2c13 = &i2c13; 53 i2c14 = &i2c14; 54 i2c15 = &i2c15; 55 mmc1 = &sdhc_1; 56 mmc2 = &sdhc_2; 57 spi0 = &spi0; 58 spi1 = &spi1; 59 spi2 = &spi2; 60 spi3 = &spi3; 61 spi4 = &spi4; 62 spi5 = &spi5; 63 spi6 = &spi6; 64 spi7 = &spi7; 65 spi8 = &spi8; 66 spi9 = &spi9; 67 spi10 = &spi10; 68 spi11 = &spi11; 69 spi12 = &spi12; 70 spi13 = &spi13; 71 spi14 = &spi14; 72 spi15 = &spi15; 73 }; 74 75 clocks { 76 xo_board: xo-board { 77 compatible = "fixed-clock"; 78 clock-frequency = <76800000>; 79 #clock-cells = <0>; 80 }; 81 82 sleep_clk: sleep-clk { 83 compatible = "fixed-clock"; 84 clock-frequency = <32000>; 85 #clock-cells = <0>; 86 }; 87 }; 88 89 reserved-memory { 90 #address-cells = <2>; 91 #size-cells = <2>; 92 ranges; 93 94 wlan_ce_mem: memory@4cd000 { 95 no-map; 96 reg = <0x0 0x004cd000 0x0 0x1000>; 97 }; 98 99 hyp_mem: memory@80000000 { 100 reg = <0x0 0x80000000 0x0 0x600000>; 101 no-map; 102 }; 103 104 xbl_mem: memory@80600000 { 105 reg = <0x0 0x80600000 0x0 0x200000>; 106 no-map; 107 }; 108 109 aop_mem: memory@80800000 { 110 reg = <0x0 0x80800000 0x0 0x60000>; 111 no-map; 112 }; 113 114 aop_cmd_db_mem: memory@80860000 { 115 reg = <0x0 0x80860000 0x0 0x20000>; 116 compatible = "qcom,cmd-db"; 117 no-map; 118 }; 119 120 reserved_xbl_uefi_log: memory@80880000 { 121 reg = <0x0 0x80884000 0x0 0x10000>; 122 no-map; 123 }; 124 125 sec_apps_mem: memory@808ff000 { 126 reg = <0x0 0x808ff000 0x0 0x1000>; 127 no-map; 128 }; 129 130 smem_mem: memory@80900000 { 131 reg = <0x0 0x80900000 0x0 0x200000>; 132 no-map; 133 }; 134 135 cpucp_mem: memory@80b00000 { 136 no-map; 137 reg = <0x0 0x80b00000 0x0 0x100000>; 138 }; 139 140 wlan_fw_mem: memory@80c00000 { 141 reg = <0x0 0x80c00000 0x0 0xc00000>; 142 no-map; 143 }; 144 145 video_mem: memory@8b200000 { 146 reg = <0x0 0x8b200000 0x0 0x500000>; 147 no-map; 148 }; 149 150 ipa_fw_mem: memory@8b700000 { 151 reg = <0 0x8b700000 0 0x10000>; 152 no-map; 153 }; 154 155 rmtfs_mem: memory@9c900000 { 156 compatible = "qcom,rmtfs-mem"; 157 reg = <0x0 0x9c900000 0x0 0x280000>; 158 no-map; 159 160 qcom,client-id = <1>; 161 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 162 }; 163 }; 164 165 cpus { 166 #address-cells = <2>; 167 #size-cells = <0>; 168 169 CPU0: cpu@0 { 170 device_type = "cpu"; 171 compatible = "qcom,kryo"; 172 reg = <0x0 0x0>; 173 clocks = <&cpufreq_hw 0>; 174 enable-method = "psci"; 175 power-domains = <&CPU_PD0>; 176 power-domain-names = "psci"; 177 next-level-cache = <&L2_0>; 178 operating-points-v2 = <&cpu0_opp_table>; 179 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 180 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 181 qcom,freq-domain = <&cpufreq_hw 0>; 182 #cooling-cells = <2>; 183 L2_0: l2-cache { 184 compatible = "cache"; 185 cache-level = <2>; 186 cache-unified; 187 next-level-cache = <&L3_0>; 188 L3_0: l3-cache { 189 compatible = "cache"; 190 cache-level = <3>; 191 cache-unified; 192 }; 193 }; 194 }; 195 196 CPU1: cpu@100 { 197 device_type = "cpu"; 198 compatible = "qcom,kryo"; 199 reg = <0x0 0x100>; 200 clocks = <&cpufreq_hw 0>; 201 enable-method = "psci"; 202 power-domains = <&CPU_PD1>; 203 power-domain-names = "psci"; 204 next-level-cache = <&L2_100>; 205 operating-points-v2 = <&cpu0_opp_table>; 206 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 207 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 208 qcom,freq-domain = <&cpufreq_hw 0>; 209 #cooling-cells = <2>; 210 L2_100: l2-cache { 211 compatible = "cache"; 212 cache-level = <2>; 213 cache-unified; 214 next-level-cache = <&L3_0>; 215 }; 216 }; 217 218 CPU2: cpu@200 { 219 device_type = "cpu"; 220 compatible = "qcom,kryo"; 221 reg = <0x0 0x200>; 222 clocks = <&cpufreq_hw 0>; 223 enable-method = "psci"; 224 power-domains = <&CPU_PD2>; 225 power-domain-names = "psci"; 226 next-level-cache = <&L2_200>; 227 operating-points-v2 = <&cpu0_opp_table>; 228 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 229 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 230 qcom,freq-domain = <&cpufreq_hw 0>; 231 #cooling-cells = <2>; 232 L2_200: l2-cache { 233 compatible = "cache"; 234 cache-level = <2>; 235 cache-unified; 236 next-level-cache = <&L3_0>; 237 }; 238 }; 239 240 CPU3: cpu@300 { 241 device_type = "cpu"; 242 compatible = "qcom,kryo"; 243 reg = <0x0 0x300>; 244 clocks = <&cpufreq_hw 0>; 245 enable-method = "psci"; 246 power-domains = <&CPU_PD3>; 247 power-domain-names = "psci"; 248 next-level-cache = <&L2_300>; 249 operating-points-v2 = <&cpu0_opp_table>; 250 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 251 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 252 qcom,freq-domain = <&cpufreq_hw 0>; 253 #cooling-cells = <2>; 254 L2_300: l2-cache { 255 compatible = "cache"; 256 cache-level = <2>; 257 cache-unified; 258 next-level-cache = <&L3_0>; 259 }; 260 }; 261 262 CPU4: cpu@400 { 263 device_type = "cpu"; 264 compatible = "qcom,kryo"; 265 reg = <0x0 0x400>; 266 clocks = <&cpufreq_hw 1>; 267 enable-method = "psci"; 268 power-domains = <&CPU_PD4>; 269 power-domain-names = "psci"; 270 next-level-cache = <&L2_400>; 271 operating-points-v2 = <&cpu4_opp_table>; 272 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 273 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 274 qcom,freq-domain = <&cpufreq_hw 1>; 275 #cooling-cells = <2>; 276 L2_400: l2-cache { 277 compatible = "cache"; 278 cache-level = <2>; 279 cache-unified; 280 next-level-cache = <&L3_0>; 281 }; 282 }; 283 284 CPU5: cpu@500 { 285 device_type = "cpu"; 286 compatible = "qcom,kryo"; 287 reg = <0x0 0x500>; 288 clocks = <&cpufreq_hw 1>; 289 enable-method = "psci"; 290 power-domains = <&CPU_PD5>; 291 power-domain-names = "psci"; 292 next-level-cache = <&L2_500>; 293 operating-points-v2 = <&cpu4_opp_table>; 294 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 295 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 296 qcom,freq-domain = <&cpufreq_hw 1>; 297 #cooling-cells = <2>; 298 L2_500: l2-cache { 299 compatible = "cache"; 300 cache-level = <2>; 301 cache-unified; 302 next-level-cache = <&L3_0>; 303 }; 304 }; 305 306 CPU6: cpu@600 { 307 device_type = "cpu"; 308 compatible = "qcom,kryo"; 309 reg = <0x0 0x600>; 310 clocks = <&cpufreq_hw 1>; 311 enable-method = "psci"; 312 power-domains = <&CPU_PD6>; 313 power-domain-names = "psci"; 314 next-level-cache = <&L2_600>; 315 operating-points-v2 = <&cpu4_opp_table>; 316 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 317 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 318 qcom,freq-domain = <&cpufreq_hw 1>; 319 #cooling-cells = <2>; 320 L2_600: l2-cache { 321 compatible = "cache"; 322 cache-level = <2>; 323 cache-unified; 324 next-level-cache = <&L3_0>; 325 }; 326 }; 327 328 CPU7: cpu@700 { 329 device_type = "cpu"; 330 compatible = "qcom,kryo"; 331 reg = <0x0 0x700>; 332 clocks = <&cpufreq_hw 2>; 333 enable-method = "psci"; 334 power-domains = <&CPU_PD7>; 335 power-domain-names = "psci"; 336 next-level-cache = <&L2_700>; 337 operating-points-v2 = <&cpu7_opp_table>; 338 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 339 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 340 qcom,freq-domain = <&cpufreq_hw 2>; 341 #cooling-cells = <2>; 342 L2_700: l2-cache { 343 compatible = "cache"; 344 cache-level = <2>; 345 cache-unified; 346 next-level-cache = <&L3_0>; 347 }; 348 }; 349 350 cpu-map { 351 cluster0 { 352 core0 { 353 cpu = <&CPU0>; 354 }; 355 356 core1 { 357 cpu = <&CPU1>; 358 }; 359 360 core2 { 361 cpu = <&CPU2>; 362 }; 363 364 core3 { 365 cpu = <&CPU3>; 366 }; 367 368 core4 { 369 cpu = <&CPU4>; 370 }; 371 372 core5 { 373 cpu = <&CPU5>; 374 }; 375 376 core6 { 377 cpu = <&CPU6>; 378 }; 379 380 core7 { 381 cpu = <&CPU7>; 382 }; 383 }; 384 }; 385 386 idle-states { 387 entry-method = "psci"; 388 389 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 390 compatible = "arm,idle-state"; 391 idle-state-name = "little-power-down"; 392 arm,psci-suspend-param = <0x40000003>; 393 entry-latency-us = <549>; 394 exit-latency-us = <901>; 395 min-residency-us = <1774>; 396 local-timer-stop; 397 }; 398 399 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 400 compatible = "arm,idle-state"; 401 idle-state-name = "little-rail-power-down"; 402 arm,psci-suspend-param = <0x40000004>; 403 entry-latency-us = <702>; 404 exit-latency-us = <915>; 405 min-residency-us = <4001>; 406 local-timer-stop; 407 }; 408 409 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 410 compatible = "arm,idle-state"; 411 idle-state-name = "big-power-down"; 412 arm,psci-suspend-param = <0x40000003>; 413 entry-latency-us = <523>; 414 exit-latency-us = <1244>; 415 min-residency-us = <2207>; 416 local-timer-stop; 417 }; 418 419 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 420 compatible = "arm,idle-state"; 421 idle-state-name = "big-rail-power-down"; 422 arm,psci-suspend-param = <0x40000004>; 423 entry-latency-us = <526>; 424 exit-latency-us = <1854>; 425 min-residency-us = <5555>; 426 local-timer-stop; 427 }; 428 }; 429 430 domain-idle-states { 431 CLUSTER_SLEEP_0: cluster-sleep-0 { 432 compatible = "domain-idle-state"; 433 idle-state-name = "cluster-power-down"; 434 arm,psci-suspend-param = <0x40003444>; 435 entry-latency-us = <3263>; 436 exit-latency-us = <6562>; 437 min-residency-us = <9926>; 438 local-timer-stop; 439 }; 440 }; 441 }; 442 443 cpu0_opp_table: opp-table-cpu0 { 444 compatible = "operating-points-v2"; 445 opp-shared; 446 447 cpu0_opp_300mhz: opp-300000000 { 448 opp-hz = /bits/ 64 <300000000>; 449 opp-peak-kBps = <800000 9600000>; 450 }; 451 452 cpu0_opp_691mhz: opp-691200000 { 453 opp-hz = /bits/ 64 <691200000>; 454 opp-peak-kBps = <800000 17817600>; 455 }; 456 457 cpu0_opp_806mhz: opp-806400000 { 458 opp-hz = /bits/ 64 <806400000>; 459 opp-peak-kBps = <800000 20889600>; 460 }; 461 462 cpu0_opp_941mhz: opp-940800000 { 463 opp-hz = /bits/ 64 <940800000>; 464 opp-peak-kBps = <1804000 24576000>; 465 }; 466 467 cpu0_opp_1152mhz: opp-1152000000 { 468 opp-hz = /bits/ 64 <1152000000>; 469 opp-peak-kBps = <2188000 27033600>; 470 }; 471 472 cpu0_opp_1325mhz: opp-1324800000 { 473 opp-hz = /bits/ 64 <1324800000>; 474 opp-peak-kBps = <2188000 33792000>; 475 }; 476 477 cpu0_opp_1517mhz: opp-1516800000 { 478 opp-hz = /bits/ 64 <1516800000>; 479 opp-peak-kBps = <3072000 38092800>; 480 }; 481 482 cpu0_opp_1651mhz: opp-1651200000 { 483 opp-hz = /bits/ 64 <1651200000>; 484 opp-peak-kBps = <3072000 41779200>; 485 }; 486 487 cpu0_opp_1805mhz: opp-1804800000 { 488 opp-hz = /bits/ 64 <1804800000>; 489 opp-peak-kBps = <4068000 48537600>; 490 }; 491 492 cpu0_opp_1958mhz: opp-1958400000 { 493 opp-hz = /bits/ 64 <1958400000>; 494 opp-peak-kBps = <4068000 48537600>; 495 }; 496 497 cpu0_opp_2016mhz: opp-2016000000 { 498 opp-hz = /bits/ 64 <2016000000>; 499 opp-peak-kBps = <6220000 48537600>; 500 }; 501 }; 502 503 cpu4_opp_table: opp-table-cpu4 { 504 compatible = "operating-points-v2"; 505 opp-shared; 506 507 cpu4_opp_691mhz: opp-691200000 { 508 opp-hz = /bits/ 64 <691200000>; 509 opp-peak-kBps = <1804000 9600000>; 510 }; 511 512 cpu4_opp_941mhz: opp-940800000 { 513 opp-hz = /bits/ 64 <940800000>; 514 opp-peak-kBps = <2188000 17817600>; 515 }; 516 517 cpu4_opp_1229mhz: opp-1228800000 { 518 opp-hz = /bits/ 64 <1228800000>; 519 opp-peak-kBps = <4068000 24576000>; 520 }; 521 522 cpu4_opp_1344mhz: opp-1344000000 { 523 opp-hz = /bits/ 64 <1344000000>; 524 opp-peak-kBps = <4068000 24576000>; 525 }; 526 527 cpu4_opp_1517mhz: opp-1516800000 { 528 opp-hz = /bits/ 64 <1516800000>; 529 opp-peak-kBps = <4068000 24576000>; 530 }; 531 532 cpu4_opp_1651mhz: opp-1651200000 { 533 opp-hz = /bits/ 64 <1651200000>; 534 opp-peak-kBps = <6220000 38092800>; 535 }; 536 537 cpu4_opp_1901mhz: opp-1900800000 { 538 opp-hz = /bits/ 64 <1900800000>; 539 opp-peak-kBps = <6220000 44851200>; 540 }; 541 542 cpu4_opp_2054mhz: opp-2054400000 { 543 opp-hz = /bits/ 64 <2054400000>; 544 opp-peak-kBps = <6220000 44851200>; 545 }; 546 547 cpu4_opp_2112mhz: opp-2112000000 { 548 opp-hz = /bits/ 64 <2112000000>; 549 opp-peak-kBps = <6220000 44851200>; 550 }; 551 552 cpu4_opp_2131mhz: opp-2131200000 { 553 opp-hz = /bits/ 64 <2131200000>; 554 opp-peak-kBps = <6220000 44851200>; 555 }; 556 557 cpu4_opp_2208mhz: opp-2208000000 { 558 opp-hz = /bits/ 64 <2208000000>; 559 opp-peak-kBps = <6220000 44851200>; 560 }; 561 562 cpu4_opp_2400mhz: opp-2400000000 { 563 opp-hz = /bits/ 64 <2400000000>; 564 opp-peak-kBps = <8532000 48537600>; 565 }; 566 567 cpu4_opp_2611mhz: opp-2611200000 { 568 opp-hz = /bits/ 64 <2611200000>; 569 opp-peak-kBps = <8532000 48537600>; 570 }; 571 }; 572 573 cpu7_opp_table: opp-table-cpu7 { 574 compatible = "operating-points-v2"; 575 opp-shared; 576 577 cpu7_opp_806mhz: opp-806400000 { 578 opp-hz = /bits/ 64 <806400000>; 579 opp-peak-kBps = <1804000 9600000>; 580 }; 581 582 cpu7_opp_1056mhz: opp-1056000000 { 583 opp-hz = /bits/ 64 <1056000000>; 584 opp-peak-kBps = <2188000 17817600>; 585 }; 586 587 cpu7_opp_1325mhz: opp-1324800000 { 588 opp-hz = /bits/ 64 <1324800000>; 589 opp-peak-kBps = <4068000 24576000>; 590 }; 591 592 cpu7_opp_1517mhz: opp-1516800000 { 593 opp-hz = /bits/ 64 <1516800000>; 594 opp-peak-kBps = <4068000 24576000>; 595 }; 596 597 cpu7_opp_1766mhz: opp-1766400000 { 598 opp-hz = /bits/ 64 <1766400000>; 599 opp-peak-kBps = <6220000 38092800>; 600 }; 601 602 cpu7_opp_1862mhz: opp-1862400000 { 603 opp-hz = /bits/ 64 <1862400000>; 604 opp-peak-kBps = <6220000 38092800>; 605 }; 606 607 cpu7_opp_2035mhz: opp-2035200000 { 608 opp-hz = /bits/ 64 <2035200000>; 609 opp-peak-kBps = <6220000 38092800>; 610 }; 611 612 cpu7_opp_2112mhz: opp-2112000000 { 613 opp-hz = /bits/ 64 <2112000000>; 614 opp-peak-kBps = <6220000 44851200>; 615 }; 616 617 cpu7_opp_2208mhz: opp-2208000000 { 618 opp-hz = /bits/ 64 <2208000000>; 619 opp-peak-kBps = <6220000 44851200>; 620 }; 621 622 cpu7_opp_2381mhz: opp-2380800000 { 623 opp-hz = /bits/ 64 <2380800000>; 624 opp-peak-kBps = <6832000 44851200>; 625 }; 626 627 cpu7_opp_2400mhz: opp-2400000000 { 628 opp-hz = /bits/ 64 <2400000000>; 629 opp-peak-kBps = <8532000 48537600>; 630 }; 631 632 cpu7_opp_2515mhz: opp-2515200000 { 633 opp-hz = /bits/ 64 <2515200000>; 634 opp-peak-kBps = <8532000 48537600>; 635 }; 636 637 cpu7_opp_2707mhz: opp-2707200000 { 638 opp-hz = /bits/ 64 <2707200000>; 639 opp-peak-kBps = <8532000 48537600>; 640 }; 641 642 cpu7_opp_3014mhz: opp-3014400000 { 643 opp-hz = /bits/ 64 <3014400000>; 644 opp-peak-kBps = <8532000 48537600>; 645 }; 646 }; 647 648 memory@80000000 { 649 device_type = "memory"; 650 /* We expect the bootloader to fill in the size */ 651 reg = <0 0x80000000 0 0>; 652 }; 653 654 firmware { 655 scm: scm { 656 compatible = "qcom,scm-sc7280", "qcom,scm"; 657 }; 658 }; 659 660 clk_virt: interconnect { 661 compatible = "qcom,sc7280-clk-virt"; 662 #interconnect-cells = <2>; 663 qcom,bcm-voters = <&apps_bcm_voter>; 664 }; 665 666 smem { 667 compatible = "qcom,smem"; 668 memory-region = <&smem_mem>; 669 hwlocks = <&tcsr_mutex 3>; 670 }; 671 672 smp2p-adsp { 673 compatible = "qcom,smp2p"; 674 qcom,smem = <443>, <429>; 675 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 676 IPCC_MPROC_SIGNAL_SMP2P 677 IRQ_TYPE_EDGE_RISING>; 678 mboxes = <&ipcc IPCC_CLIENT_LPASS 679 IPCC_MPROC_SIGNAL_SMP2P>; 680 681 qcom,local-pid = <0>; 682 qcom,remote-pid = <2>; 683 684 adsp_smp2p_out: master-kernel { 685 qcom,entry-name = "master-kernel"; 686 #qcom,smem-state-cells = <1>; 687 }; 688 689 adsp_smp2p_in: slave-kernel { 690 qcom,entry-name = "slave-kernel"; 691 interrupt-controller; 692 #interrupt-cells = <2>; 693 }; 694 }; 695 696 smp2p-cdsp { 697 compatible = "qcom,smp2p"; 698 qcom,smem = <94>, <432>; 699 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 700 IPCC_MPROC_SIGNAL_SMP2P 701 IRQ_TYPE_EDGE_RISING>; 702 mboxes = <&ipcc IPCC_CLIENT_CDSP 703 IPCC_MPROC_SIGNAL_SMP2P>; 704 705 qcom,local-pid = <0>; 706 qcom,remote-pid = <5>; 707 708 cdsp_smp2p_out: master-kernel { 709 qcom,entry-name = "master-kernel"; 710 #qcom,smem-state-cells = <1>; 711 }; 712 713 cdsp_smp2p_in: slave-kernel { 714 qcom,entry-name = "slave-kernel"; 715 interrupt-controller; 716 #interrupt-cells = <2>; 717 }; 718 }; 719 720 smp2p-mpss { 721 compatible = "qcom,smp2p"; 722 qcom,smem = <435>, <428>; 723 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 724 IPCC_MPROC_SIGNAL_SMP2P 725 IRQ_TYPE_EDGE_RISING>; 726 mboxes = <&ipcc IPCC_CLIENT_MPSS 727 IPCC_MPROC_SIGNAL_SMP2P>; 728 729 qcom,local-pid = <0>; 730 qcom,remote-pid = <1>; 731 732 modem_smp2p_out: master-kernel { 733 qcom,entry-name = "master-kernel"; 734 #qcom,smem-state-cells = <1>; 735 }; 736 737 modem_smp2p_in: slave-kernel { 738 qcom,entry-name = "slave-kernel"; 739 interrupt-controller; 740 #interrupt-cells = <2>; 741 }; 742 743 ipa_smp2p_out: ipa-ap-to-modem { 744 qcom,entry-name = "ipa"; 745 #qcom,smem-state-cells = <1>; 746 }; 747 748 ipa_smp2p_in: ipa-modem-to-ap { 749 qcom,entry-name = "ipa"; 750 interrupt-controller; 751 #interrupt-cells = <2>; 752 }; 753 }; 754 755 smp2p-wpss { 756 compatible = "qcom,smp2p"; 757 qcom,smem = <617>, <616>; 758 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 759 IPCC_MPROC_SIGNAL_SMP2P 760 IRQ_TYPE_EDGE_RISING>; 761 mboxes = <&ipcc IPCC_CLIENT_WPSS 762 IPCC_MPROC_SIGNAL_SMP2P>; 763 764 qcom,local-pid = <0>; 765 qcom,remote-pid = <13>; 766 767 wpss_smp2p_out: master-kernel { 768 qcom,entry-name = "master-kernel"; 769 #qcom,smem-state-cells = <1>; 770 }; 771 772 wpss_smp2p_in: slave-kernel { 773 qcom,entry-name = "slave-kernel"; 774 interrupt-controller; 775 #interrupt-cells = <2>; 776 }; 777 778 wlan_smp2p_out: wlan-ap-to-wpss { 779 qcom,entry-name = "wlan"; 780 #qcom,smem-state-cells = <1>; 781 }; 782 783 wlan_smp2p_in: wlan-wpss-to-ap { 784 qcom,entry-name = "wlan"; 785 interrupt-controller; 786 #interrupt-cells = <2>; 787 }; 788 }; 789 790 pmu { 791 compatible = "arm,armv8-pmuv3"; 792 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 793 }; 794 795 psci { 796 compatible = "arm,psci-1.0"; 797 method = "smc"; 798 799 CPU_PD0: power-domain-cpu0 { 800 #power-domain-cells = <0>; 801 power-domains = <&CLUSTER_PD>; 802 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 803 }; 804 805 CPU_PD1: power-domain-cpu1 { 806 #power-domain-cells = <0>; 807 power-domains = <&CLUSTER_PD>; 808 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 809 }; 810 811 CPU_PD2: power-domain-cpu2 { 812 #power-domain-cells = <0>; 813 power-domains = <&CLUSTER_PD>; 814 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 815 }; 816 817 CPU_PD3: power-domain-cpu3 { 818 #power-domain-cells = <0>; 819 power-domains = <&CLUSTER_PD>; 820 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 821 }; 822 823 CPU_PD4: power-domain-cpu4 { 824 #power-domain-cells = <0>; 825 power-domains = <&CLUSTER_PD>; 826 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 827 }; 828 829 CPU_PD5: power-domain-cpu5 { 830 #power-domain-cells = <0>; 831 power-domains = <&CLUSTER_PD>; 832 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 833 }; 834 835 CPU_PD6: power-domain-cpu6 { 836 #power-domain-cells = <0>; 837 power-domains = <&CLUSTER_PD>; 838 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 839 }; 840 841 CPU_PD7: power-domain-cpu7 { 842 #power-domain-cells = <0>; 843 power-domains = <&CLUSTER_PD>; 844 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 845 }; 846 847 CLUSTER_PD: power-domain-cluster { 848 #power-domain-cells = <0>; 849 domain-idle-states = <&CLUSTER_SLEEP_0>; 850 }; 851 }; 852 853 qspi_opp_table: opp-table-qspi { 854 compatible = "operating-points-v2"; 855 856 opp-75000000 { 857 opp-hz = /bits/ 64 <75000000>; 858 required-opps = <&rpmhpd_opp_low_svs>; 859 }; 860 861 opp-150000000 { 862 opp-hz = /bits/ 64 <150000000>; 863 required-opps = <&rpmhpd_opp_svs>; 864 }; 865 866 opp-200000000 { 867 opp-hz = /bits/ 64 <200000000>; 868 required-opps = <&rpmhpd_opp_svs_l1>; 869 }; 870 871 opp-300000000 { 872 opp-hz = /bits/ 64 <300000000>; 873 required-opps = <&rpmhpd_opp_nom>; 874 }; 875 }; 876 877 qup_opp_table: opp-table-qup { 878 compatible = "operating-points-v2"; 879 880 opp-75000000 { 881 opp-hz = /bits/ 64 <75000000>; 882 required-opps = <&rpmhpd_opp_low_svs>; 883 }; 884 885 opp-100000000 { 886 opp-hz = /bits/ 64 <100000000>; 887 required-opps = <&rpmhpd_opp_svs>; 888 }; 889 890 opp-128000000 { 891 opp-hz = /bits/ 64 <128000000>; 892 required-opps = <&rpmhpd_opp_nom>; 893 }; 894 }; 895 896 soc: soc@0 { 897 #address-cells = <2>; 898 #size-cells = <2>; 899 ranges = <0 0 0 0 0x10 0>; 900 dma-ranges = <0 0 0 0 0x10 0>; 901 compatible = "simple-bus"; 902 903 gcc: clock-controller@100000 { 904 compatible = "qcom,gcc-sc7280"; 905 reg = <0 0x00100000 0 0x1f0000>; 906 clocks = <&rpmhcc RPMH_CXO_CLK>, 907 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 908 <0>, <&pcie1_phy>, 909 <0>, <0>, <0>, 910 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 911 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 912 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 913 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 914 "ufs_phy_tx_symbol_0_clk", 915 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 916 #clock-cells = <1>; 917 #reset-cells = <1>; 918 #power-domain-cells = <1>; 919 power-domains = <&rpmhpd SC7280_CX>; 920 }; 921 922 ipcc: mailbox@408000 { 923 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 924 reg = <0 0x00408000 0 0x1000>; 925 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 926 interrupt-controller; 927 #interrupt-cells = <3>; 928 #mbox-cells = <2>; 929 }; 930 931 qfprom: efuse@784000 { 932 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 933 reg = <0 0x00784000 0 0xa20>, 934 <0 0x00780000 0 0xa20>, 935 <0 0x00782000 0 0x120>, 936 <0 0x00786000 0 0x1fff>; 937 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 938 clock-names = "core"; 939 power-domains = <&rpmhpd SC7280_MX>; 940 #address-cells = <1>; 941 #size-cells = <1>; 942 943 gpu_speed_bin: gpu_speed_bin@1e9 { 944 reg = <0x1e9 0x2>; 945 bits = <5 8>; 946 }; 947 }; 948 949 sdhc_1: mmc@7c4000 { 950 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 951 pinctrl-names = "default", "sleep"; 952 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 953 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 954 status = "disabled"; 955 956 reg = <0 0x007c4000 0 0x1000>, 957 <0 0x007c5000 0 0x1000>; 958 reg-names = "hc", "cqhci"; 959 960 iommus = <&apps_smmu 0xc0 0x0>; 961 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 962 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 963 interrupt-names = "hc_irq", "pwr_irq"; 964 965 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 966 <&gcc GCC_SDCC1_APPS_CLK>, 967 <&rpmhcc RPMH_CXO_CLK>; 968 clock-names = "iface", "core", "xo"; 969 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 970 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 971 interconnect-names = "sdhc-ddr","cpu-sdhc"; 972 power-domains = <&rpmhpd SC7280_CX>; 973 operating-points-v2 = <&sdhc1_opp_table>; 974 975 bus-width = <8>; 976 supports-cqe; 977 978 qcom,dll-config = <0x0007642c>; 979 qcom,ddr-config = <0x80040868>; 980 981 mmc-ddr-1_8v; 982 mmc-hs200-1_8v; 983 mmc-hs400-1_8v; 984 mmc-hs400-enhanced-strobe; 985 986 resets = <&gcc GCC_SDCC1_BCR>; 987 988 sdhc1_opp_table: opp-table { 989 compatible = "operating-points-v2"; 990 991 opp-100000000 { 992 opp-hz = /bits/ 64 <100000000>; 993 required-opps = <&rpmhpd_opp_low_svs>; 994 opp-peak-kBps = <1800000 400000>; 995 opp-avg-kBps = <100000 0>; 996 }; 997 998 opp-384000000 { 999 opp-hz = /bits/ 64 <384000000>; 1000 required-opps = <&rpmhpd_opp_nom>; 1001 opp-peak-kBps = <5400000 1600000>; 1002 opp-avg-kBps = <390000 0>; 1003 }; 1004 }; 1005 }; 1006 1007 gpi_dma0: dma-controller@900000 { 1008 #dma-cells = <3>; 1009 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1010 reg = <0 0x00900000 0 0x60000>; 1011 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1012 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1013 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1014 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1015 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1016 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1017 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1018 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1019 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1020 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1021 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1022 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1023 dma-channels = <12>; 1024 dma-channel-mask = <0x7f>; 1025 iommus = <&apps_smmu 0x0136 0x0>; 1026 status = "disabled"; 1027 }; 1028 1029 qupv3_id_0: geniqup@9c0000 { 1030 compatible = "qcom,geni-se-qup"; 1031 reg = <0 0x009c0000 0 0x2000>; 1032 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1033 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1034 clock-names = "m-ahb", "s-ahb"; 1035 #address-cells = <2>; 1036 #size-cells = <2>; 1037 ranges; 1038 iommus = <&apps_smmu 0x123 0x0>; 1039 status = "disabled"; 1040 1041 i2c0: i2c@980000 { 1042 compatible = "qcom,geni-i2c"; 1043 reg = <0 0x00980000 0 0x4000>; 1044 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1045 clock-names = "se"; 1046 pinctrl-names = "default"; 1047 pinctrl-0 = <&qup_i2c0_data_clk>; 1048 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1049 #address-cells = <1>; 1050 #size-cells = <0>; 1051 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1052 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1053 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1054 interconnect-names = "qup-core", "qup-config", 1055 "qup-memory"; 1056 power-domains = <&rpmhpd SC7280_CX>; 1057 required-opps = <&rpmhpd_opp_low_svs>; 1058 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1059 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1060 dma-names = "tx", "rx"; 1061 status = "disabled"; 1062 }; 1063 1064 spi0: spi@980000 { 1065 compatible = "qcom,geni-spi"; 1066 reg = <0 0x00980000 0 0x4000>; 1067 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1068 clock-names = "se"; 1069 pinctrl-names = "default"; 1070 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1071 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1072 #address-cells = <1>; 1073 #size-cells = <0>; 1074 power-domains = <&rpmhpd SC7280_CX>; 1075 operating-points-v2 = <&qup_opp_table>; 1076 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1077 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1078 interconnect-names = "qup-core", "qup-config"; 1079 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1080 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1081 dma-names = "tx", "rx"; 1082 status = "disabled"; 1083 }; 1084 1085 uart0: serial@980000 { 1086 compatible = "qcom,geni-uart"; 1087 reg = <0 0x00980000 0 0x4000>; 1088 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1089 clock-names = "se"; 1090 pinctrl-names = "default"; 1091 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1092 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1093 power-domains = <&rpmhpd SC7280_CX>; 1094 operating-points-v2 = <&qup_opp_table>; 1095 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1096 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1097 interconnect-names = "qup-core", "qup-config"; 1098 status = "disabled"; 1099 }; 1100 1101 i2c1: i2c@984000 { 1102 compatible = "qcom,geni-i2c"; 1103 reg = <0 0x00984000 0 0x4000>; 1104 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1105 clock-names = "se"; 1106 pinctrl-names = "default"; 1107 pinctrl-0 = <&qup_i2c1_data_clk>; 1108 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1109 #address-cells = <1>; 1110 #size-cells = <0>; 1111 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1112 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1113 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1114 interconnect-names = "qup-core", "qup-config", 1115 "qup-memory"; 1116 power-domains = <&rpmhpd SC7280_CX>; 1117 required-opps = <&rpmhpd_opp_low_svs>; 1118 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1119 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1120 dma-names = "tx", "rx"; 1121 status = "disabled"; 1122 }; 1123 1124 spi1: spi@984000 { 1125 compatible = "qcom,geni-spi"; 1126 reg = <0 0x00984000 0 0x4000>; 1127 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1128 clock-names = "se"; 1129 pinctrl-names = "default"; 1130 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1131 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1132 #address-cells = <1>; 1133 #size-cells = <0>; 1134 power-domains = <&rpmhpd SC7280_CX>; 1135 operating-points-v2 = <&qup_opp_table>; 1136 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1137 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1138 interconnect-names = "qup-core", "qup-config"; 1139 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1140 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1141 dma-names = "tx", "rx"; 1142 status = "disabled"; 1143 }; 1144 1145 uart1: serial@984000 { 1146 compatible = "qcom,geni-uart"; 1147 reg = <0 0x00984000 0 0x4000>; 1148 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1149 clock-names = "se"; 1150 pinctrl-names = "default"; 1151 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1152 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1153 power-domains = <&rpmhpd SC7280_CX>; 1154 operating-points-v2 = <&qup_opp_table>; 1155 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1156 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1157 interconnect-names = "qup-core", "qup-config"; 1158 status = "disabled"; 1159 }; 1160 1161 i2c2: i2c@988000 { 1162 compatible = "qcom,geni-i2c"; 1163 reg = <0 0x00988000 0 0x4000>; 1164 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1165 clock-names = "se"; 1166 pinctrl-names = "default"; 1167 pinctrl-0 = <&qup_i2c2_data_clk>; 1168 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1169 #address-cells = <1>; 1170 #size-cells = <0>; 1171 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1172 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1173 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1174 interconnect-names = "qup-core", "qup-config", 1175 "qup-memory"; 1176 power-domains = <&rpmhpd SC7280_CX>; 1177 required-opps = <&rpmhpd_opp_low_svs>; 1178 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1179 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1180 dma-names = "tx", "rx"; 1181 status = "disabled"; 1182 }; 1183 1184 spi2: spi@988000 { 1185 compatible = "qcom,geni-spi"; 1186 reg = <0 0x00988000 0 0x4000>; 1187 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1188 clock-names = "se"; 1189 pinctrl-names = "default"; 1190 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1191 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1192 #address-cells = <1>; 1193 #size-cells = <0>; 1194 power-domains = <&rpmhpd SC7280_CX>; 1195 operating-points-v2 = <&qup_opp_table>; 1196 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1197 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1198 interconnect-names = "qup-core", "qup-config"; 1199 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1200 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1201 dma-names = "tx", "rx"; 1202 status = "disabled"; 1203 }; 1204 1205 uart2: serial@988000 { 1206 compatible = "qcom,geni-uart"; 1207 reg = <0 0x00988000 0 0x4000>; 1208 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1209 clock-names = "se"; 1210 pinctrl-names = "default"; 1211 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1212 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1213 power-domains = <&rpmhpd SC7280_CX>; 1214 operating-points-v2 = <&qup_opp_table>; 1215 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1216 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1217 interconnect-names = "qup-core", "qup-config"; 1218 status = "disabled"; 1219 }; 1220 1221 i2c3: i2c@98c000 { 1222 compatible = "qcom,geni-i2c"; 1223 reg = <0 0x0098c000 0 0x4000>; 1224 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1225 clock-names = "se"; 1226 pinctrl-names = "default"; 1227 pinctrl-0 = <&qup_i2c3_data_clk>; 1228 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1229 #address-cells = <1>; 1230 #size-cells = <0>; 1231 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1232 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1233 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1234 interconnect-names = "qup-core", "qup-config", 1235 "qup-memory"; 1236 power-domains = <&rpmhpd SC7280_CX>; 1237 required-opps = <&rpmhpd_opp_low_svs>; 1238 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1239 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1240 dma-names = "tx", "rx"; 1241 status = "disabled"; 1242 }; 1243 1244 spi3: spi@98c000 { 1245 compatible = "qcom,geni-spi"; 1246 reg = <0 0x0098c000 0 0x4000>; 1247 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1248 clock-names = "se"; 1249 pinctrl-names = "default"; 1250 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1251 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1252 #address-cells = <1>; 1253 #size-cells = <0>; 1254 power-domains = <&rpmhpd SC7280_CX>; 1255 operating-points-v2 = <&qup_opp_table>; 1256 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1257 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1258 interconnect-names = "qup-core", "qup-config"; 1259 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1260 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1261 dma-names = "tx", "rx"; 1262 status = "disabled"; 1263 }; 1264 1265 uart3: serial@98c000 { 1266 compatible = "qcom,geni-uart"; 1267 reg = <0 0x0098c000 0 0x4000>; 1268 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1269 clock-names = "se"; 1270 pinctrl-names = "default"; 1271 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1272 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1273 power-domains = <&rpmhpd SC7280_CX>; 1274 operating-points-v2 = <&qup_opp_table>; 1275 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1276 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1277 interconnect-names = "qup-core", "qup-config"; 1278 status = "disabled"; 1279 }; 1280 1281 i2c4: i2c@990000 { 1282 compatible = "qcom,geni-i2c"; 1283 reg = <0 0x00990000 0 0x4000>; 1284 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1285 clock-names = "se"; 1286 pinctrl-names = "default"; 1287 pinctrl-0 = <&qup_i2c4_data_clk>; 1288 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1289 #address-cells = <1>; 1290 #size-cells = <0>; 1291 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1292 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1293 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1294 interconnect-names = "qup-core", "qup-config", 1295 "qup-memory"; 1296 power-domains = <&rpmhpd SC7280_CX>; 1297 required-opps = <&rpmhpd_opp_low_svs>; 1298 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1299 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1300 dma-names = "tx", "rx"; 1301 status = "disabled"; 1302 }; 1303 1304 spi4: spi@990000 { 1305 compatible = "qcom,geni-spi"; 1306 reg = <0 0x00990000 0 0x4000>; 1307 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1308 clock-names = "se"; 1309 pinctrl-names = "default"; 1310 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1311 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1312 #address-cells = <1>; 1313 #size-cells = <0>; 1314 power-domains = <&rpmhpd SC7280_CX>; 1315 operating-points-v2 = <&qup_opp_table>; 1316 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1317 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1318 interconnect-names = "qup-core", "qup-config"; 1319 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1320 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1321 dma-names = "tx", "rx"; 1322 status = "disabled"; 1323 }; 1324 1325 uart4: serial@990000 { 1326 compatible = "qcom,geni-uart"; 1327 reg = <0 0x00990000 0 0x4000>; 1328 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1329 clock-names = "se"; 1330 pinctrl-names = "default"; 1331 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1332 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1333 power-domains = <&rpmhpd SC7280_CX>; 1334 operating-points-v2 = <&qup_opp_table>; 1335 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1336 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1337 interconnect-names = "qup-core", "qup-config"; 1338 status = "disabled"; 1339 }; 1340 1341 i2c5: i2c@994000 { 1342 compatible = "qcom,geni-i2c"; 1343 reg = <0 0x00994000 0 0x4000>; 1344 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1345 clock-names = "se"; 1346 pinctrl-names = "default"; 1347 pinctrl-0 = <&qup_i2c5_data_clk>; 1348 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1349 #address-cells = <1>; 1350 #size-cells = <0>; 1351 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1352 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1353 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1354 interconnect-names = "qup-core", "qup-config", 1355 "qup-memory"; 1356 power-domains = <&rpmhpd SC7280_CX>; 1357 required-opps = <&rpmhpd_opp_low_svs>; 1358 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1359 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1360 dma-names = "tx", "rx"; 1361 status = "disabled"; 1362 }; 1363 1364 spi5: spi@994000 { 1365 compatible = "qcom,geni-spi"; 1366 reg = <0 0x00994000 0 0x4000>; 1367 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1368 clock-names = "se"; 1369 pinctrl-names = "default"; 1370 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1371 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1372 #address-cells = <1>; 1373 #size-cells = <0>; 1374 power-domains = <&rpmhpd SC7280_CX>; 1375 operating-points-v2 = <&qup_opp_table>; 1376 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1377 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1378 interconnect-names = "qup-core", "qup-config"; 1379 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1380 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1381 dma-names = "tx", "rx"; 1382 status = "disabled"; 1383 }; 1384 1385 uart5: serial@994000 { 1386 compatible = "qcom,geni-uart"; 1387 reg = <0 0x00994000 0 0x4000>; 1388 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1389 clock-names = "se"; 1390 pinctrl-names = "default"; 1391 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1392 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1393 power-domains = <&rpmhpd SC7280_CX>; 1394 operating-points-v2 = <&qup_opp_table>; 1395 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1396 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1397 interconnect-names = "qup-core", "qup-config"; 1398 status = "disabled"; 1399 }; 1400 1401 i2c6: i2c@998000 { 1402 compatible = "qcom,geni-i2c"; 1403 reg = <0 0x00998000 0 0x4000>; 1404 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1405 clock-names = "se"; 1406 pinctrl-names = "default"; 1407 pinctrl-0 = <&qup_i2c6_data_clk>; 1408 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1409 #address-cells = <1>; 1410 #size-cells = <0>; 1411 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1412 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1413 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1414 interconnect-names = "qup-core", "qup-config", 1415 "qup-memory"; 1416 power-domains = <&rpmhpd SC7280_CX>; 1417 required-opps = <&rpmhpd_opp_low_svs>; 1418 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1419 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1420 dma-names = "tx", "rx"; 1421 status = "disabled"; 1422 }; 1423 1424 spi6: spi@998000 { 1425 compatible = "qcom,geni-spi"; 1426 reg = <0 0x00998000 0 0x4000>; 1427 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1428 clock-names = "se"; 1429 pinctrl-names = "default"; 1430 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1431 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1432 #address-cells = <1>; 1433 #size-cells = <0>; 1434 power-domains = <&rpmhpd SC7280_CX>; 1435 operating-points-v2 = <&qup_opp_table>; 1436 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1437 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1438 interconnect-names = "qup-core", "qup-config"; 1439 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1440 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1441 dma-names = "tx", "rx"; 1442 status = "disabled"; 1443 }; 1444 1445 uart6: serial@998000 { 1446 compatible = "qcom,geni-uart"; 1447 reg = <0 0x00998000 0 0x4000>; 1448 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1449 clock-names = "se"; 1450 pinctrl-names = "default"; 1451 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1452 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1453 power-domains = <&rpmhpd SC7280_CX>; 1454 operating-points-v2 = <&qup_opp_table>; 1455 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1456 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1457 interconnect-names = "qup-core", "qup-config"; 1458 status = "disabled"; 1459 }; 1460 1461 i2c7: i2c@99c000 { 1462 compatible = "qcom,geni-i2c"; 1463 reg = <0 0x0099c000 0 0x4000>; 1464 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1465 clock-names = "se"; 1466 pinctrl-names = "default"; 1467 pinctrl-0 = <&qup_i2c7_data_clk>; 1468 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1469 #address-cells = <1>; 1470 #size-cells = <0>; 1471 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1472 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1473 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1474 interconnect-names = "qup-core", "qup-config", 1475 "qup-memory"; 1476 power-domains = <&rpmhpd SC7280_CX>; 1477 required-opps = <&rpmhpd_opp_low_svs>; 1478 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1479 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1480 dma-names = "tx", "rx"; 1481 status = "disabled"; 1482 }; 1483 1484 spi7: spi@99c000 { 1485 compatible = "qcom,geni-spi"; 1486 reg = <0 0x0099c000 0 0x4000>; 1487 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1488 clock-names = "se"; 1489 pinctrl-names = "default"; 1490 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1491 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1492 #address-cells = <1>; 1493 #size-cells = <0>; 1494 power-domains = <&rpmhpd SC7280_CX>; 1495 operating-points-v2 = <&qup_opp_table>; 1496 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1497 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1498 interconnect-names = "qup-core", "qup-config"; 1499 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1500 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1501 dma-names = "tx", "rx"; 1502 status = "disabled"; 1503 }; 1504 1505 uart7: serial@99c000 { 1506 compatible = "qcom,geni-uart"; 1507 reg = <0 0x0099c000 0 0x4000>; 1508 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1509 clock-names = "se"; 1510 pinctrl-names = "default"; 1511 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1512 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1513 power-domains = <&rpmhpd SC7280_CX>; 1514 operating-points-v2 = <&qup_opp_table>; 1515 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1516 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1517 interconnect-names = "qup-core", "qup-config"; 1518 status = "disabled"; 1519 }; 1520 }; 1521 1522 gpi_dma1: dma-controller@a00000 { 1523 #dma-cells = <3>; 1524 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1525 reg = <0 0x00a00000 0 0x60000>; 1526 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1538 dma-channels = <12>; 1539 dma-channel-mask = <0x1e>; 1540 iommus = <&apps_smmu 0x56 0x0>; 1541 status = "disabled"; 1542 }; 1543 1544 qupv3_id_1: geniqup@ac0000 { 1545 compatible = "qcom,geni-se-qup"; 1546 reg = <0 0x00ac0000 0 0x2000>; 1547 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1548 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1549 clock-names = "m-ahb", "s-ahb"; 1550 #address-cells = <2>; 1551 #size-cells = <2>; 1552 ranges; 1553 iommus = <&apps_smmu 0x43 0x0>; 1554 status = "disabled"; 1555 1556 i2c8: i2c@a80000 { 1557 compatible = "qcom,geni-i2c"; 1558 reg = <0 0x00a80000 0 0x4000>; 1559 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1560 clock-names = "se"; 1561 pinctrl-names = "default"; 1562 pinctrl-0 = <&qup_i2c8_data_clk>; 1563 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1564 #address-cells = <1>; 1565 #size-cells = <0>; 1566 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1567 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1568 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1569 interconnect-names = "qup-core", "qup-config", 1570 "qup-memory"; 1571 power-domains = <&rpmhpd SC7280_CX>; 1572 required-opps = <&rpmhpd_opp_low_svs>; 1573 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1574 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1575 dma-names = "tx", "rx"; 1576 status = "disabled"; 1577 }; 1578 1579 spi8: spi@a80000 { 1580 compatible = "qcom,geni-spi"; 1581 reg = <0 0x00a80000 0 0x4000>; 1582 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1583 clock-names = "se"; 1584 pinctrl-names = "default"; 1585 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1586 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1587 #address-cells = <1>; 1588 #size-cells = <0>; 1589 power-domains = <&rpmhpd SC7280_CX>; 1590 operating-points-v2 = <&qup_opp_table>; 1591 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1592 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1593 interconnect-names = "qup-core", "qup-config"; 1594 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1595 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1596 dma-names = "tx", "rx"; 1597 status = "disabled"; 1598 }; 1599 1600 uart8: serial@a80000 { 1601 compatible = "qcom,geni-uart"; 1602 reg = <0 0x00a80000 0 0x4000>; 1603 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1604 clock-names = "se"; 1605 pinctrl-names = "default"; 1606 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1607 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1608 power-domains = <&rpmhpd SC7280_CX>; 1609 operating-points-v2 = <&qup_opp_table>; 1610 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1611 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1612 interconnect-names = "qup-core", "qup-config"; 1613 status = "disabled"; 1614 }; 1615 1616 i2c9: i2c@a84000 { 1617 compatible = "qcom,geni-i2c"; 1618 reg = <0 0x00a84000 0 0x4000>; 1619 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1620 clock-names = "se"; 1621 pinctrl-names = "default"; 1622 pinctrl-0 = <&qup_i2c9_data_clk>; 1623 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1624 #address-cells = <1>; 1625 #size-cells = <0>; 1626 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1627 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1628 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1629 interconnect-names = "qup-core", "qup-config", 1630 "qup-memory"; 1631 power-domains = <&rpmhpd SC7280_CX>; 1632 required-opps = <&rpmhpd_opp_low_svs>; 1633 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1634 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1635 dma-names = "tx", "rx"; 1636 status = "disabled"; 1637 }; 1638 1639 spi9: spi@a84000 { 1640 compatible = "qcom,geni-spi"; 1641 reg = <0 0x00a84000 0 0x4000>; 1642 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1643 clock-names = "se"; 1644 pinctrl-names = "default"; 1645 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1646 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1647 #address-cells = <1>; 1648 #size-cells = <0>; 1649 power-domains = <&rpmhpd SC7280_CX>; 1650 operating-points-v2 = <&qup_opp_table>; 1651 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1652 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1653 interconnect-names = "qup-core", "qup-config"; 1654 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1655 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1656 dma-names = "tx", "rx"; 1657 status = "disabled"; 1658 }; 1659 1660 uart9: serial@a84000 { 1661 compatible = "qcom,geni-uart"; 1662 reg = <0 0x00a84000 0 0x4000>; 1663 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1664 clock-names = "se"; 1665 pinctrl-names = "default"; 1666 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1667 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1668 power-domains = <&rpmhpd SC7280_CX>; 1669 operating-points-v2 = <&qup_opp_table>; 1670 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1671 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1672 interconnect-names = "qup-core", "qup-config"; 1673 status = "disabled"; 1674 }; 1675 1676 i2c10: i2c@a88000 { 1677 compatible = "qcom,geni-i2c"; 1678 reg = <0 0x00a88000 0 0x4000>; 1679 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1680 clock-names = "se"; 1681 pinctrl-names = "default"; 1682 pinctrl-0 = <&qup_i2c10_data_clk>; 1683 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1684 #address-cells = <1>; 1685 #size-cells = <0>; 1686 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1687 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1688 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1689 interconnect-names = "qup-core", "qup-config", 1690 "qup-memory"; 1691 power-domains = <&rpmhpd SC7280_CX>; 1692 required-opps = <&rpmhpd_opp_low_svs>; 1693 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1694 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1695 dma-names = "tx", "rx"; 1696 status = "disabled"; 1697 }; 1698 1699 spi10: spi@a88000 { 1700 compatible = "qcom,geni-spi"; 1701 reg = <0 0x00a88000 0 0x4000>; 1702 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1703 clock-names = "se"; 1704 pinctrl-names = "default"; 1705 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1706 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1707 #address-cells = <1>; 1708 #size-cells = <0>; 1709 power-domains = <&rpmhpd SC7280_CX>; 1710 operating-points-v2 = <&qup_opp_table>; 1711 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1712 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1713 interconnect-names = "qup-core", "qup-config"; 1714 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1715 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1716 dma-names = "tx", "rx"; 1717 status = "disabled"; 1718 }; 1719 1720 uart10: serial@a88000 { 1721 compatible = "qcom,geni-uart"; 1722 reg = <0 0x00a88000 0 0x4000>; 1723 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1724 clock-names = "se"; 1725 pinctrl-names = "default"; 1726 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1727 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1728 power-domains = <&rpmhpd SC7280_CX>; 1729 operating-points-v2 = <&qup_opp_table>; 1730 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1731 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1732 interconnect-names = "qup-core", "qup-config"; 1733 status = "disabled"; 1734 }; 1735 1736 i2c11: i2c@a8c000 { 1737 compatible = "qcom,geni-i2c"; 1738 reg = <0 0x00a8c000 0 0x4000>; 1739 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1740 clock-names = "se"; 1741 pinctrl-names = "default"; 1742 pinctrl-0 = <&qup_i2c11_data_clk>; 1743 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1744 #address-cells = <1>; 1745 #size-cells = <0>; 1746 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1747 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1748 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1749 interconnect-names = "qup-core", "qup-config", 1750 "qup-memory"; 1751 power-domains = <&rpmhpd SC7280_CX>; 1752 required-opps = <&rpmhpd_opp_low_svs>; 1753 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1754 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1755 dma-names = "tx", "rx"; 1756 status = "disabled"; 1757 }; 1758 1759 spi11: spi@a8c000 { 1760 compatible = "qcom,geni-spi"; 1761 reg = <0 0x00a8c000 0 0x4000>; 1762 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1763 clock-names = "se"; 1764 pinctrl-names = "default"; 1765 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1766 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1767 #address-cells = <1>; 1768 #size-cells = <0>; 1769 power-domains = <&rpmhpd SC7280_CX>; 1770 operating-points-v2 = <&qup_opp_table>; 1771 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1772 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1773 interconnect-names = "qup-core", "qup-config"; 1774 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1775 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1776 dma-names = "tx", "rx"; 1777 status = "disabled"; 1778 }; 1779 1780 uart11: serial@a8c000 { 1781 compatible = "qcom,geni-uart"; 1782 reg = <0 0x00a8c000 0 0x4000>; 1783 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1784 clock-names = "se"; 1785 pinctrl-names = "default"; 1786 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1787 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1788 power-domains = <&rpmhpd SC7280_CX>; 1789 operating-points-v2 = <&qup_opp_table>; 1790 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1791 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1792 interconnect-names = "qup-core", "qup-config"; 1793 status = "disabled"; 1794 }; 1795 1796 i2c12: i2c@a90000 { 1797 compatible = "qcom,geni-i2c"; 1798 reg = <0 0x00a90000 0 0x4000>; 1799 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1800 clock-names = "se"; 1801 pinctrl-names = "default"; 1802 pinctrl-0 = <&qup_i2c12_data_clk>; 1803 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1804 #address-cells = <1>; 1805 #size-cells = <0>; 1806 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1807 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1808 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1809 interconnect-names = "qup-core", "qup-config", 1810 "qup-memory"; 1811 power-domains = <&rpmhpd SC7280_CX>; 1812 required-opps = <&rpmhpd_opp_low_svs>; 1813 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1814 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1815 dma-names = "tx", "rx"; 1816 status = "disabled"; 1817 }; 1818 1819 spi12: spi@a90000 { 1820 compatible = "qcom,geni-spi"; 1821 reg = <0 0x00a90000 0 0x4000>; 1822 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1823 clock-names = "se"; 1824 pinctrl-names = "default"; 1825 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1826 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1827 #address-cells = <1>; 1828 #size-cells = <0>; 1829 power-domains = <&rpmhpd SC7280_CX>; 1830 operating-points-v2 = <&qup_opp_table>; 1831 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1832 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1833 interconnect-names = "qup-core", "qup-config"; 1834 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1835 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1836 dma-names = "tx", "rx"; 1837 status = "disabled"; 1838 }; 1839 1840 uart12: serial@a90000 { 1841 compatible = "qcom,geni-uart"; 1842 reg = <0 0x00a90000 0 0x4000>; 1843 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1844 clock-names = "se"; 1845 pinctrl-names = "default"; 1846 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1847 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1848 power-domains = <&rpmhpd SC7280_CX>; 1849 operating-points-v2 = <&qup_opp_table>; 1850 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1851 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1852 interconnect-names = "qup-core", "qup-config"; 1853 status = "disabled"; 1854 }; 1855 1856 i2c13: i2c@a94000 { 1857 compatible = "qcom,geni-i2c"; 1858 reg = <0 0x00a94000 0 0x4000>; 1859 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1860 clock-names = "se"; 1861 pinctrl-names = "default"; 1862 pinctrl-0 = <&qup_i2c13_data_clk>; 1863 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1864 #address-cells = <1>; 1865 #size-cells = <0>; 1866 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1867 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1868 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1869 interconnect-names = "qup-core", "qup-config", 1870 "qup-memory"; 1871 power-domains = <&rpmhpd SC7280_CX>; 1872 required-opps = <&rpmhpd_opp_low_svs>; 1873 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1874 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1875 dma-names = "tx", "rx"; 1876 status = "disabled"; 1877 }; 1878 1879 spi13: spi@a94000 { 1880 compatible = "qcom,geni-spi"; 1881 reg = <0 0x00a94000 0 0x4000>; 1882 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1883 clock-names = "se"; 1884 pinctrl-names = "default"; 1885 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1886 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1887 #address-cells = <1>; 1888 #size-cells = <0>; 1889 power-domains = <&rpmhpd SC7280_CX>; 1890 operating-points-v2 = <&qup_opp_table>; 1891 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1892 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1893 interconnect-names = "qup-core", "qup-config"; 1894 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1895 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1896 dma-names = "tx", "rx"; 1897 status = "disabled"; 1898 }; 1899 1900 uart13: serial@a94000 { 1901 compatible = "qcom,geni-uart"; 1902 reg = <0 0x00a94000 0 0x4000>; 1903 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1904 clock-names = "se"; 1905 pinctrl-names = "default"; 1906 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1907 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1908 power-domains = <&rpmhpd SC7280_CX>; 1909 operating-points-v2 = <&qup_opp_table>; 1910 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1911 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1912 interconnect-names = "qup-core", "qup-config"; 1913 status = "disabled"; 1914 }; 1915 1916 i2c14: i2c@a98000 { 1917 compatible = "qcom,geni-i2c"; 1918 reg = <0 0x00a98000 0 0x4000>; 1919 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1920 clock-names = "se"; 1921 pinctrl-names = "default"; 1922 pinctrl-0 = <&qup_i2c14_data_clk>; 1923 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1924 #address-cells = <1>; 1925 #size-cells = <0>; 1926 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1927 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1928 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1929 interconnect-names = "qup-core", "qup-config", 1930 "qup-memory"; 1931 power-domains = <&rpmhpd SC7280_CX>; 1932 required-opps = <&rpmhpd_opp_low_svs>; 1933 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1934 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1935 dma-names = "tx", "rx"; 1936 status = "disabled"; 1937 }; 1938 1939 spi14: spi@a98000 { 1940 compatible = "qcom,geni-spi"; 1941 reg = <0 0x00a98000 0 0x4000>; 1942 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1943 clock-names = "se"; 1944 pinctrl-names = "default"; 1945 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1946 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1947 #address-cells = <1>; 1948 #size-cells = <0>; 1949 power-domains = <&rpmhpd SC7280_CX>; 1950 operating-points-v2 = <&qup_opp_table>; 1951 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1952 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1953 interconnect-names = "qup-core", "qup-config"; 1954 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1955 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1956 dma-names = "tx", "rx"; 1957 status = "disabled"; 1958 }; 1959 1960 uart14: serial@a98000 { 1961 compatible = "qcom,geni-uart"; 1962 reg = <0 0x00a98000 0 0x4000>; 1963 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1964 clock-names = "se"; 1965 pinctrl-names = "default"; 1966 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 1967 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1968 power-domains = <&rpmhpd SC7280_CX>; 1969 operating-points-v2 = <&qup_opp_table>; 1970 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1971 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1972 interconnect-names = "qup-core", "qup-config"; 1973 status = "disabled"; 1974 }; 1975 1976 i2c15: i2c@a9c000 { 1977 compatible = "qcom,geni-i2c"; 1978 reg = <0 0x00a9c000 0 0x4000>; 1979 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1980 clock-names = "se"; 1981 pinctrl-names = "default"; 1982 pinctrl-0 = <&qup_i2c15_data_clk>; 1983 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 1984 #address-cells = <1>; 1985 #size-cells = <0>; 1986 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1987 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1988 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1989 interconnect-names = "qup-core", "qup-config", 1990 "qup-memory"; 1991 power-domains = <&rpmhpd SC7280_CX>; 1992 required-opps = <&rpmhpd_opp_low_svs>; 1993 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1994 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1995 dma-names = "tx", "rx"; 1996 status = "disabled"; 1997 }; 1998 1999 spi15: spi@a9c000 { 2000 compatible = "qcom,geni-spi"; 2001 reg = <0 0x00a9c000 0 0x4000>; 2002 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2003 clock-names = "se"; 2004 pinctrl-names = "default"; 2005 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 2006 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2007 #address-cells = <1>; 2008 #size-cells = <0>; 2009 power-domains = <&rpmhpd SC7280_CX>; 2010 operating-points-v2 = <&qup_opp_table>; 2011 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2012 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2013 interconnect-names = "qup-core", "qup-config"; 2014 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2015 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2016 dma-names = "tx", "rx"; 2017 status = "disabled"; 2018 }; 2019 2020 uart15: serial@a9c000 { 2021 compatible = "qcom,geni-uart"; 2022 reg = <0 0x00a9c000 0 0x4000>; 2023 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2024 clock-names = "se"; 2025 pinctrl-names = "default"; 2026 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 2027 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2028 power-domains = <&rpmhpd SC7280_CX>; 2029 operating-points-v2 = <&qup_opp_table>; 2030 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2031 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2032 interconnect-names = "qup-core", "qup-config"; 2033 status = "disabled"; 2034 }; 2035 }; 2036 2037 cnoc2: interconnect@1500000 { 2038 reg = <0 0x01500000 0 0x1000>; 2039 compatible = "qcom,sc7280-cnoc2"; 2040 #interconnect-cells = <2>; 2041 qcom,bcm-voters = <&apps_bcm_voter>; 2042 }; 2043 2044 cnoc3: interconnect@1502000 { 2045 reg = <0 0x01502000 0 0x1000>; 2046 compatible = "qcom,sc7280-cnoc3"; 2047 #interconnect-cells = <2>; 2048 qcom,bcm-voters = <&apps_bcm_voter>; 2049 }; 2050 2051 mc_virt: interconnect@1580000 { 2052 reg = <0 0x01580000 0 0x4>; 2053 compatible = "qcom,sc7280-mc-virt"; 2054 #interconnect-cells = <2>; 2055 qcom,bcm-voters = <&apps_bcm_voter>; 2056 }; 2057 2058 system_noc: interconnect@1680000 { 2059 reg = <0 0x01680000 0 0x15480>; 2060 compatible = "qcom,sc7280-system-noc"; 2061 #interconnect-cells = <2>; 2062 qcom,bcm-voters = <&apps_bcm_voter>; 2063 }; 2064 2065 aggre1_noc: interconnect@16e0000 { 2066 compatible = "qcom,sc7280-aggre1-noc"; 2067 reg = <0 0x016e0000 0 0x1c080>; 2068 #interconnect-cells = <2>; 2069 qcom,bcm-voters = <&apps_bcm_voter>; 2070 }; 2071 2072 aggre2_noc: interconnect@1700000 { 2073 reg = <0 0x01700000 0 0x2b080>; 2074 compatible = "qcom,sc7280-aggre2-noc"; 2075 #interconnect-cells = <2>; 2076 qcom,bcm-voters = <&apps_bcm_voter>; 2077 }; 2078 2079 mmss_noc: interconnect@1740000 { 2080 reg = <0 0x01740000 0 0x1e080>; 2081 compatible = "qcom,sc7280-mmss-noc"; 2082 #interconnect-cells = <2>; 2083 qcom,bcm-voters = <&apps_bcm_voter>; 2084 }; 2085 2086 wifi: wifi@17a10040 { 2087 compatible = "qcom,wcn6750-wifi"; 2088 reg = <0 0x17a10040 0 0x0>; 2089 iommus = <&apps_smmu 0x1c00 0x1>; 2090 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 2091 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 2092 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 2093 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 2094 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 2095 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 2096 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 2097 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 2098 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 2099 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 2100 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 2101 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 2102 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 2103 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 2104 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 2105 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 2106 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 2107 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 2108 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 2109 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 2110 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 2111 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 2112 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 2113 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 2114 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 2115 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 2116 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 2117 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 2118 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2119 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2120 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2121 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2122 qcom,rproc = <&remoteproc_wpss>; 2123 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2124 status = "disabled"; 2125 qcom,smem-states = <&wlan_smp2p_out 0>; 2126 qcom,smem-state-names = "wlan-smp2p-out"; 2127 }; 2128 2129 pcie1: pci@1c08000 { 2130 compatible = "qcom,pcie-sc7280"; 2131 reg = <0 0x01c08000 0 0x3000>, 2132 <0 0x40000000 0 0xf1d>, 2133 <0 0x40000f20 0 0xa8>, 2134 <0 0x40001000 0 0x1000>, 2135 <0 0x40100000 0 0x100000>; 2136 2137 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2138 device_type = "pci"; 2139 linux,pci-domain = <1>; 2140 bus-range = <0x00 0xff>; 2141 num-lanes = <2>; 2142 2143 #address-cells = <3>; 2144 #size-cells = <2>; 2145 2146 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2147 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2148 2149 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 2150 interrupt-names = "msi"; 2151 #interrupt-cells = <1>; 2152 interrupt-map-mask = <0 0 0 0x7>; 2153 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2154 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2155 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2156 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2157 2158 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2159 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2160 <&pcie1_phy>, 2161 <&rpmhcc RPMH_CXO_CLK>, 2162 <&gcc GCC_PCIE_1_AUX_CLK>, 2163 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2164 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2165 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2166 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2167 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2168 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2169 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2170 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2171 2172 clock-names = "pipe", 2173 "pipe_mux", 2174 "phy_pipe", 2175 "ref", 2176 "aux", 2177 "cfg", 2178 "bus_master", 2179 "bus_slave", 2180 "slave_q2a", 2181 "tbu", 2182 "ddrss_sf_tbu", 2183 "aggre0", 2184 "aggre1"; 2185 2186 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2187 assigned-clock-rates = <19200000>; 2188 2189 resets = <&gcc GCC_PCIE_1_BCR>; 2190 reset-names = "pci"; 2191 2192 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2193 2194 phys = <&pcie1_phy>; 2195 phy-names = "pciephy"; 2196 2197 pinctrl-names = "default"; 2198 pinctrl-0 = <&pcie1_clkreq_n>; 2199 2200 dma-coherent; 2201 2202 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2203 <0x100 &apps_smmu 0x1c81 0x1>; 2204 2205 status = "disabled"; 2206 }; 2207 2208 pcie1_phy: phy@1c0e000 { 2209 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2210 reg = <0 0x01c0e000 0 0x1000>; 2211 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2212 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2213 <&gcc GCC_PCIE_CLKREF_EN>, 2214 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, 2215 <&gcc GCC_PCIE_1_PIPE_CLK>; 2216 clock-names = "aux", 2217 "cfg_ahb", 2218 "ref", 2219 "refgen", 2220 "pipe"; 2221 2222 clock-output-names = "pcie_1_pipe_clk"; 2223 #clock-cells = <0>; 2224 2225 #phy-cells = <0>; 2226 2227 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2228 reset-names = "phy"; 2229 2230 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2231 assigned-clock-rates = <100000000>; 2232 2233 status = "disabled"; 2234 }; 2235 2236 ipa: ipa@1e40000 { 2237 compatible = "qcom,sc7280-ipa"; 2238 2239 iommus = <&apps_smmu 0x480 0x0>, 2240 <&apps_smmu 0x482 0x0>; 2241 reg = <0 0x01e40000 0 0x8000>, 2242 <0 0x01e50000 0 0x4ad0>, 2243 <0 0x01e04000 0 0x23000>; 2244 reg-names = "ipa-reg", 2245 "ipa-shared", 2246 "gsi"; 2247 2248 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2249 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2250 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2251 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2252 interrupt-names = "ipa", 2253 "gsi", 2254 "ipa-clock-query", 2255 "ipa-setup-ready"; 2256 2257 clocks = <&rpmhcc RPMH_IPA_CLK>; 2258 clock-names = "core"; 2259 2260 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2261 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2262 interconnect-names = "memory", 2263 "config"; 2264 2265 qcom,qmp = <&aoss_qmp>; 2266 2267 qcom,smem-states = <&ipa_smp2p_out 0>, 2268 <&ipa_smp2p_out 1>; 2269 qcom,smem-state-names = "ipa-clock-enabled-valid", 2270 "ipa-clock-enabled"; 2271 2272 status = "disabled"; 2273 }; 2274 2275 tcsr_mutex: hwlock@1f40000 { 2276 compatible = "qcom,tcsr-mutex"; 2277 reg = <0 0x01f40000 0 0x20000>; 2278 #hwlock-cells = <1>; 2279 }; 2280 2281 tcsr_1: syscon@1f60000 { 2282 compatible = "qcom,sc7280-tcsr", "syscon"; 2283 reg = <0 0x01f60000 0 0x20000>; 2284 }; 2285 2286 tcsr_2: syscon@1fc0000 { 2287 compatible = "qcom,sc7280-tcsr", "syscon"; 2288 reg = <0 0x01fc0000 0 0x30000>; 2289 }; 2290 2291 lpasscc: lpasscc@3000000 { 2292 compatible = "qcom,sc7280-lpasscc"; 2293 reg = <0 0x03000000 0 0x40>, 2294 <0 0x03c04000 0 0x4>; 2295 reg-names = "qdsp6ss", "top_cc"; 2296 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2297 clock-names = "iface"; 2298 #clock-cells = <1>; 2299 status = "reserved"; /* Owned by ADSP firmware */ 2300 }; 2301 2302 lpass_rx_macro: codec@3200000 { 2303 compatible = "qcom,sc7280-lpass-rx-macro"; 2304 reg = <0 0x03200000 0 0x1000>; 2305 2306 pinctrl-names = "default"; 2307 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2308 2309 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2310 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2311 <&lpass_va_macro>; 2312 clock-names = "mclk", "npl", "fsgen"; 2313 2314 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2315 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2316 power-domain-names = "macro", "dcodec"; 2317 2318 #clock-cells = <0>; 2319 #sound-dai-cells = <1>; 2320 2321 status = "disabled"; 2322 }; 2323 2324 swr0: soundwire@3210000 { 2325 compatible = "qcom,soundwire-v1.6.0"; 2326 reg = <0 0x03210000 0 0x2000>; 2327 2328 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2329 clocks = <&lpass_rx_macro>; 2330 clock-names = "iface"; 2331 2332 qcom,din-ports = <0>; 2333 qcom,dout-ports = <5>; 2334 2335 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2336 reset-names = "swr_audio_cgcr"; 2337 2338 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2339 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2340 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2341 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2342 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2343 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2344 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2345 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2346 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2347 2348 #sound-dai-cells = <1>; 2349 #address-cells = <2>; 2350 #size-cells = <0>; 2351 2352 status = "disabled"; 2353 }; 2354 2355 lpass_tx_macro: codec@3220000 { 2356 compatible = "qcom,sc7280-lpass-tx-macro"; 2357 reg = <0 0x03220000 0 0x1000>; 2358 2359 pinctrl-names = "default"; 2360 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2361 2362 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2363 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2364 <&lpass_va_macro>; 2365 clock-names = "mclk", "npl", "fsgen"; 2366 2367 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2368 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2369 power-domain-names = "macro", "dcodec"; 2370 2371 #clock-cells = <0>; 2372 #sound-dai-cells = <1>; 2373 2374 status = "disabled"; 2375 }; 2376 2377 swr1: soundwire@3230000 { 2378 compatible = "qcom,soundwire-v1.6.0"; 2379 reg = <0 0x03230000 0 0x2000>; 2380 2381 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2382 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2383 clocks = <&lpass_tx_macro>; 2384 clock-names = "iface"; 2385 2386 qcom,din-ports = <3>; 2387 qcom,dout-ports = <0>; 2388 2389 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2390 reset-names = "swr_audio_cgcr"; 2391 2392 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2393 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2394 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2395 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2396 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2397 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2398 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2399 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2400 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2401 2402 #sound-dai-cells = <1>; 2403 #address-cells = <2>; 2404 #size-cells = <0>; 2405 2406 status = "disabled"; 2407 }; 2408 2409 lpass_audiocc: clock-controller@3300000 { 2410 compatible = "qcom,sc7280-lpassaudiocc"; 2411 reg = <0 0x03300000 0 0x30000>, 2412 <0 0x032a9000 0 0x1000>; 2413 clocks = <&rpmhcc RPMH_CXO_CLK>, 2414 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2415 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2416 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2417 #clock-cells = <1>; 2418 #power-domain-cells = <1>; 2419 #reset-cells = <1>; 2420 }; 2421 2422 lpass_va_macro: codec@3370000 { 2423 compatible = "qcom,sc7280-lpass-va-macro"; 2424 reg = <0 0x03370000 0 0x1000>; 2425 2426 pinctrl-names = "default"; 2427 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; 2428 2429 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2430 clock-names = "mclk"; 2431 2432 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2433 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2434 power-domain-names = "macro", "dcodec"; 2435 2436 #clock-cells = <0>; 2437 #sound-dai-cells = <1>; 2438 2439 status = "disabled"; 2440 }; 2441 2442 lpass_aon: clock-controller@3380000 { 2443 compatible = "qcom,sc7280-lpassaoncc"; 2444 reg = <0 0x03380000 0 0x30000>; 2445 clocks = <&rpmhcc RPMH_CXO_CLK>, 2446 <&rpmhcc RPMH_CXO_CLK_A>, 2447 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2448 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2449 #clock-cells = <1>; 2450 #power-domain-cells = <1>; 2451 status = "reserved"; /* Owned by ADSP firmware */ 2452 }; 2453 2454 lpass_core: clock-controller@3900000 { 2455 compatible = "qcom,sc7280-lpasscorecc"; 2456 reg = <0 0x03900000 0 0x50000>; 2457 clocks = <&rpmhcc RPMH_CXO_CLK>; 2458 clock-names = "bi_tcxo"; 2459 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2460 #clock-cells = <1>; 2461 #power-domain-cells = <1>; 2462 status = "reserved"; /* Owned by ADSP firmware */ 2463 }; 2464 2465 lpass_cpu: audio@3987000 { 2466 compatible = "qcom,sc7280-lpass-cpu"; 2467 2468 reg = <0 0x03987000 0 0x68000>, 2469 <0 0x03b00000 0 0x29000>, 2470 <0 0x03260000 0 0xc000>, 2471 <0 0x03280000 0 0x29000>, 2472 <0 0x03340000 0 0x29000>, 2473 <0 0x0336c000 0 0x3000>; 2474 reg-names = "lpass-hdmiif", 2475 "lpass-lpaif", 2476 "lpass-rxtx-cdc-dma-lpm", 2477 "lpass-rxtx-lpaif", 2478 "lpass-va-lpaif", 2479 "lpass-va-cdc-dma-lpm"; 2480 2481 iommus = <&apps_smmu 0x1820 0>, 2482 <&apps_smmu 0x1821 0>, 2483 <&apps_smmu 0x1832 0>; 2484 2485 power-domains = <&rpmhpd SC7280_LCX>; 2486 power-domain-names = "lcx"; 2487 required-opps = <&rpmhpd_opp_nom>; 2488 2489 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2490 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2491 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2492 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2493 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2494 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2495 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2496 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2497 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2498 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2499 clock-names = "aon_cc_audio_hm_h", 2500 "audio_cc_ext_mclk0", 2501 "core_cc_sysnoc_mport_core", 2502 "core_cc_ext_if0_ibit", 2503 "core_cc_ext_if1_ibit", 2504 "audio_cc_codec_mem", 2505 "audio_cc_codec_mem0", 2506 "audio_cc_codec_mem1", 2507 "audio_cc_codec_mem2", 2508 "aon_cc_va_mem0"; 2509 2510 #sound-dai-cells = <1>; 2511 #address-cells = <1>; 2512 #size-cells = <0>; 2513 2514 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2515 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2516 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2517 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2518 interrupt-names = "lpass-irq-lpaif", 2519 "lpass-irq-hdmi", 2520 "lpass-irq-vaif", 2521 "lpass-irq-rxtxif"; 2522 2523 status = "disabled"; 2524 }; 2525 2526 lpass_hm: clock-controller@3c00000 { 2527 compatible = "qcom,sc7280-lpasshm"; 2528 reg = <0 0x03c00000 0 0x28>; 2529 clocks = <&rpmhcc RPMH_CXO_CLK>; 2530 clock-names = "bi_tcxo"; 2531 #clock-cells = <1>; 2532 #power-domain-cells = <1>; 2533 status = "reserved"; /* Owned by ADSP firmware */ 2534 }; 2535 2536 lpass_ag_noc: interconnect@3c40000 { 2537 reg = <0 0x03c40000 0 0xf080>; 2538 compatible = "qcom,sc7280-lpass-ag-noc"; 2539 #interconnect-cells = <2>; 2540 qcom,bcm-voters = <&apps_bcm_voter>; 2541 }; 2542 2543 lpass_tlmm: pinctrl@33c0000 { 2544 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2545 reg = <0 0x033c0000 0x0 0x20000>, 2546 <0 0x03550000 0x0 0x10000>; 2547 gpio-controller; 2548 #gpio-cells = <2>; 2549 gpio-ranges = <&lpass_tlmm 0 0 15>; 2550 2551 lpass_dmic01_clk: dmic01-clk-state { 2552 pins = "gpio6"; 2553 function = "dmic1_clk"; 2554 }; 2555 2556 lpass_dmic01_data: dmic01-data-state { 2557 pins = "gpio7"; 2558 function = "dmic1_data"; 2559 }; 2560 2561 lpass_dmic23_clk: dmic23-clk-state { 2562 pins = "gpio8"; 2563 function = "dmic2_clk"; 2564 }; 2565 2566 lpass_dmic23_data: dmic23-data-state { 2567 pins = "gpio9"; 2568 function = "dmic2_data"; 2569 }; 2570 2571 lpass_rx_swr_clk: rx-swr-clk-state { 2572 pins = "gpio3"; 2573 function = "swr_rx_clk"; 2574 }; 2575 2576 lpass_rx_swr_data: rx-swr-data-state { 2577 pins = "gpio4", "gpio5"; 2578 function = "swr_rx_data"; 2579 }; 2580 2581 lpass_tx_swr_clk: tx-swr-clk-state { 2582 pins = "gpio0"; 2583 function = "swr_tx_clk"; 2584 }; 2585 2586 lpass_tx_swr_data: tx-swr-data-state { 2587 pins = "gpio1", "gpio2", "gpio14"; 2588 function = "swr_tx_data"; 2589 }; 2590 }; 2591 2592 gpu: gpu@3d00000 { 2593 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2594 reg = <0 0x03d00000 0 0x40000>, 2595 <0 0x03d9e000 0 0x1000>, 2596 <0 0x03d61000 0 0x800>; 2597 reg-names = "kgsl_3d0_reg_memory", 2598 "cx_mem", 2599 "cx_dbgc"; 2600 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2601 iommus = <&adreno_smmu 0 0x401>; 2602 operating-points-v2 = <&gpu_opp_table>; 2603 qcom,gmu = <&gmu>; 2604 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2605 interconnect-names = "gfx-mem"; 2606 #cooling-cells = <2>; 2607 2608 nvmem-cells = <&gpu_speed_bin>; 2609 nvmem-cell-names = "speed_bin"; 2610 2611 gpu_opp_table: opp-table { 2612 compatible = "operating-points-v2"; 2613 2614 opp-315000000 { 2615 opp-hz = /bits/ 64 <315000000>; 2616 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2617 opp-peak-kBps = <1804000>; 2618 opp-supported-hw = <0x03>; 2619 }; 2620 2621 opp-450000000 { 2622 opp-hz = /bits/ 64 <450000000>; 2623 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2624 opp-peak-kBps = <4068000>; 2625 opp-supported-hw = <0x03>; 2626 }; 2627 2628 /* Only applicable for SKUs which has 550Mhz as Fmax */ 2629 opp-550000000-0 { 2630 opp-hz = /bits/ 64 <550000000>; 2631 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2632 opp-peak-kBps = <8368000>; 2633 opp-supported-hw = <0x01>; 2634 }; 2635 2636 opp-550000000-1 { 2637 opp-hz = /bits/ 64 <550000000>; 2638 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2639 opp-peak-kBps = <6832000>; 2640 opp-supported-hw = <0x02>; 2641 }; 2642 2643 opp-608000000 { 2644 opp-hz = /bits/ 64 <608000000>; 2645 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2646 opp-peak-kBps = <8368000>; 2647 opp-supported-hw = <0x02>; 2648 }; 2649 2650 opp-700000000 { 2651 opp-hz = /bits/ 64 <700000000>; 2652 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2653 opp-peak-kBps = <8532000>; 2654 opp-supported-hw = <0x02>; 2655 }; 2656 2657 opp-812000000 { 2658 opp-hz = /bits/ 64 <812000000>; 2659 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2660 opp-peak-kBps = <8532000>; 2661 opp-supported-hw = <0x02>; 2662 }; 2663 2664 opp-840000000 { 2665 opp-hz = /bits/ 64 <840000000>; 2666 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2667 opp-peak-kBps = <8532000>; 2668 opp-supported-hw = <0x02>; 2669 }; 2670 2671 opp-900000000 { 2672 opp-hz = /bits/ 64 <900000000>; 2673 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2674 opp-peak-kBps = <8532000>; 2675 opp-supported-hw = <0x02>; 2676 }; 2677 }; 2678 }; 2679 2680 gmu: gmu@3d6a000 { 2681 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2682 reg = <0 0x03d6a000 0 0x34000>, 2683 <0 0x3de0000 0 0x10000>, 2684 <0 0x0b290000 0 0x10000>; 2685 reg-names = "gmu", "rscc", "gmu_pdc"; 2686 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2687 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2688 interrupt-names = "hfi", "gmu"; 2689 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2690 <&gpucc GPU_CC_CXO_CLK>, 2691 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2692 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2693 <&gpucc GPU_CC_AHB_CLK>, 2694 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2695 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2696 clock-names = "gmu", 2697 "cxo", 2698 "axi", 2699 "memnoc", 2700 "ahb", 2701 "hub", 2702 "smmu_vote"; 2703 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2704 <&gpucc GPU_CC_GX_GDSC>; 2705 power-domain-names = "cx", 2706 "gx"; 2707 iommus = <&adreno_smmu 5 0x400>; 2708 operating-points-v2 = <&gmu_opp_table>; 2709 2710 gmu_opp_table: opp-table { 2711 compatible = "operating-points-v2"; 2712 2713 opp-200000000 { 2714 opp-hz = /bits/ 64 <200000000>; 2715 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2716 }; 2717 }; 2718 }; 2719 2720 gpucc: clock-controller@3d90000 { 2721 compatible = "qcom,sc7280-gpucc"; 2722 reg = <0 0x03d90000 0 0x9000>; 2723 clocks = <&rpmhcc RPMH_CXO_CLK>, 2724 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2725 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2726 clock-names = "bi_tcxo", 2727 "gcc_gpu_gpll0_clk_src", 2728 "gcc_gpu_gpll0_div_clk_src"; 2729 #clock-cells = <1>; 2730 #reset-cells = <1>; 2731 #power-domain-cells = <1>; 2732 }; 2733 2734 dma@117f000 { 2735 compatible = "qcom,sc7280-dcc", "qcom,dcc"; 2736 reg = <0x0 0x0117f000 0x0 0x1000>, 2737 <0x0 0x01112000 0x0 0x6000>; 2738 }; 2739 2740 adreno_smmu: iommu@3da0000 { 2741 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", 2742 "qcom,smmu-500", "arm,mmu-500"; 2743 reg = <0 0x03da0000 0 0x20000>; 2744 #iommu-cells = <2>; 2745 #global-interrupts = <2>; 2746 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2747 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2748 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2749 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2750 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2751 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2752 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2753 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2754 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2755 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2756 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2757 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2758 2759 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2760 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2761 <&gpucc GPU_CC_AHB_CLK>, 2762 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2763 <&gpucc GPU_CC_CX_GMU_CLK>, 2764 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2765 <&gpucc GPU_CC_HUB_AON_CLK>; 2766 clock-names = "gcc_gpu_memnoc_gfx_clk", 2767 "gcc_gpu_snoc_dvm_gfx_clk", 2768 "gpu_cc_ahb_clk", 2769 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2770 "gpu_cc_cx_gmu_clk", 2771 "gpu_cc_hub_cx_int_clk", 2772 "gpu_cc_hub_aon_clk"; 2773 2774 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2775 }; 2776 2777 remoteproc_mpss: remoteproc@4080000 { 2778 compatible = "qcom,sc7280-mpss-pas"; 2779 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; 2780 reg-names = "qdsp6", "rmb"; 2781 2782 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2783 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2784 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2785 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2786 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2787 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2788 interrupt-names = "wdog", "fatal", "ready", "handover", 2789 "stop-ack", "shutdown-ack"; 2790 2791 clocks = <&rpmhcc RPMH_CXO_CLK>; 2792 clock-names = "xo"; 2793 2794 power-domains = <&rpmhpd SC7280_CX>, 2795 <&rpmhpd SC7280_MSS>; 2796 power-domain-names = "cx", "mss"; 2797 2798 memory-region = <&mpss_mem>; 2799 2800 qcom,qmp = <&aoss_qmp>; 2801 2802 qcom,smem-states = <&modem_smp2p_out 0>; 2803 qcom,smem-state-names = "stop"; 2804 2805 status = "disabled"; 2806 2807 glink-edge { 2808 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2809 IPCC_MPROC_SIGNAL_GLINK_QMP 2810 IRQ_TYPE_EDGE_RISING>; 2811 mboxes = <&ipcc IPCC_CLIENT_MPSS 2812 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2813 label = "modem"; 2814 qcom,remote-pid = <1>; 2815 }; 2816 }; 2817 2818 stm@6002000 { 2819 compatible = "arm,coresight-stm", "arm,primecell"; 2820 reg = <0 0x06002000 0 0x1000>, 2821 <0 0x16280000 0 0x180000>; 2822 reg-names = "stm-base", "stm-stimulus-base"; 2823 2824 clocks = <&aoss_qmp>; 2825 clock-names = "apb_pclk"; 2826 2827 out-ports { 2828 port { 2829 stm_out: endpoint { 2830 remote-endpoint = <&funnel0_in7>; 2831 }; 2832 }; 2833 }; 2834 }; 2835 2836 funnel@6041000 { 2837 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2838 reg = <0 0x06041000 0 0x1000>; 2839 2840 clocks = <&aoss_qmp>; 2841 clock-names = "apb_pclk"; 2842 2843 out-ports { 2844 port { 2845 funnel0_out: endpoint { 2846 remote-endpoint = <&merge_funnel_in0>; 2847 }; 2848 }; 2849 }; 2850 2851 in-ports { 2852 #address-cells = <1>; 2853 #size-cells = <0>; 2854 2855 port@7 { 2856 reg = <7>; 2857 funnel0_in7: endpoint { 2858 remote-endpoint = <&stm_out>; 2859 }; 2860 }; 2861 }; 2862 }; 2863 2864 funnel@6042000 { 2865 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2866 reg = <0 0x06042000 0 0x1000>; 2867 2868 clocks = <&aoss_qmp>; 2869 clock-names = "apb_pclk"; 2870 2871 out-ports { 2872 port { 2873 funnel1_out: endpoint { 2874 remote-endpoint = <&merge_funnel_in1>; 2875 }; 2876 }; 2877 }; 2878 2879 in-ports { 2880 #address-cells = <1>; 2881 #size-cells = <0>; 2882 2883 port@4 { 2884 reg = <4>; 2885 funnel1_in4: endpoint { 2886 remote-endpoint = <&apss_merge_funnel_out>; 2887 }; 2888 }; 2889 }; 2890 }; 2891 2892 funnel@6045000 { 2893 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2894 reg = <0 0x06045000 0 0x1000>; 2895 2896 clocks = <&aoss_qmp>; 2897 clock-names = "apb_pclk"; 2898 2899 out-ports { 2900 port { 2901 merge_funnel_out: endpoint { 2902 remote-endpoint = <&swao_funnel_in>; 2903 }; 2904 }; 2905 }; 2906 2907 in-ports { 2908 #address-cells = <1>; 2909 #size-cells = <0>; 2910 2911 port@0 { 2912 reg = <0>; 2913 merge_funnel_in0: endpoint { 2914 remote-endpoint = <&funnel0_out>; 2915 }; 2916 }; 2917 2918 port@1 { 2919 reg = <1>; 2920 merge_funnel_in1: endpoint { 2921 remote-endpoint = <&funnel1_out>; 2922 }; 2923 }; 2924 }; 2925 }; 2926 2927 replicator@6046000 { 2928 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2929 reg = <0 0x06046000 0 0x1000>; 2930 2931 clocks = <&aoss_qmp>; 2932 clock-names = "apb_pclk"; 2933 2934 out-ports { 2935 port { 2936 replicator_out: endpoint { 2937 remote-endpoint = <&etr_in>; 2938 }; 2939 }; 2940 }; 2941 2942 in-ports { 2943 port { 2944 replicator_in: endpoint { 2945 remote-endpoint = <&swao_replicator_out>; 2946 }; 2947 }; 2948 }; 2949 }; 2950 2951 etr@6048000 { 2952 compatible = "arm,coresight-tmc", "arm,primecell"; 2953 reg = <0 0x06048000 0 0x1000>; 2954 iommus = <&apps_smmu 0x04c0 0>; 2955 2956 clocks = <&aoss_qmp>; 2957 clock-names = "apb_pclk"; 2958 arm,scatter-gather; 2959 2960 in-ports { 2961 port { 2962 etr_in: endpoint { 2963 remote-endpoint = <&replicator_out>; 2964 }; 2965 }; 2966 }; 2967 }; 2968 2969 funnel@6b04000 { 2970 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2971 reg = <0 0x06b04000 0 0x1000>; 2972 2973 clocks = <&aoss_qmp>; 2974 clock-names = "apb_pclk"; 2975 2976 out-ports { 2977 port { 2978 swao_funnel_out: endpoint { 2979 remote-endpoint = <&etf_in>; 2980 }; 2981 }; 2982 }; 2983 2984 in-ports { 2985 #address-cells = <1>; 2986 #size-cells = <0>; 2987 2988 port@7 { 2989 reg = <7>; 2990 swao_funnel_in: endpoint { 2991 remote-endpoint = <&merge_funnel_out>; 2992 }; 2993 }; 2994 }; 2995 }; 2996 2997 etf@6b05000 { 2998 compatible = "arm,coresight-tmc", "arm,primecell"; 2999 reg = <0 0x06b05000 0 0x1000>; 3000 3001 clocks = <&aoss_qmp>; 3002 clock-names = "apb_pclk"; 3003 3004 out-ports { 3005 port { 3006 etf_out: endpoint { 3007 remote-endpoint = <&swao_replicator_in>; 3008 }; 3009 }; 3010 }; 3011 3012 in-ports { 3013 port { 3014 etf_in: endpoint { 3015 remote-endpoint = <&swao_funnel_out>; 3016 }; 3017 }; 3018 }; 3019 }; 3020 3021 replicator@6b06000 { 3022 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3023 reg = <0 0x06b06000 0 0x1000>; 3024 3025 clocks = <&aoss_qmp>; 3026 clock-names = "apb_pclk"; 3027 qcom,replicator-loses-context; 3028 3029 out-ports { 3030 port { 3031 swao_replicator_out: endpoint { 3032 remote-endpoint = <&replicator_in>; 3033 }; 3034 }; 3035 }; 3036 3037 in-ports { 3038 port { 3039 swao_replicator_in: endpoint { 3040 remote-endpoint = <&etf_out>; 3041 }; 3042 }; 3043 }; 3044 }; 3045 3046 etm@7040000 { 3047 compatible = "arm,coresight-etm4x", "arm,primecell"; 3048 reg = <0 0x07040000 0 0x1000>; 3049 3050 cpu = <&CPU0>; 3051 3052 clocks = <&aoss_qmp>; 3053 clock-names = "apb_pclk"; 3054 arm,coresight-loses-context-with-cpu; 3055 qcom,skip-power-up; 3056 3057 out-ports { 3058 port { 3059 etm0_out: endpoint { 3060 remote-endpoint = <&apss_funnel_in0>; 3061 }; 3062 }; 3063 }; 3064 }; 3065 3066 etm@7140000 { 3067 compatible = "arm,coresight-etm4x", "arm,primecell"; 3068 reg = <0 0x07140000 0 0x1000>; 3069 3070 cpu = <&CPU1>; 3071 3072 clocks = <&aoss_qmp>; 3073 clock-names = "apb_pclk"; 3074 arm,coresight-loses-context-with-cpu; 3075 qcom,skip-power-up; 3076 3077 out-ports { 3078 port { 3079 etm1_out: endpoint { 3080 remote-endpoint = <&apss_funnel_in1>; 3081 }; 3082 }; 3083 }; 3084 }; 3085 3086 etm@7240000 { 3087 compatible = "arm,coresight-etm4x", "arm,primecell"; 3088 reg = <0 0x07240000 0 0x1000>; 3089 3090 cpu = <&CPU2>; 3091 3092 clocks = <&aoss_qmp>; 3093 clock-names = "apb_pclk"; 3094 arm,coresight-loses-context-with-cpu; 3095 qcom,skip-power-up; 3096 3097 out-ports { 3098 port { 3099 etm2_out: endpoint { 3100 remote-endpoint = <&apss_funnel_in2>; 3101 }; 3102 }; 3103 }; 3104 }; 3105 3106 etm@7340000 { 3107 compatible = "arm,coresight-etm4x", "arm,primecell"; 3108 reg = <0 0x07340000 0 0x1000>; 3109 3110 cpu = <&CPU3>; 3111 3112 clocks = <&aoss_qmp>; 3113 clock-names = "apb_pclk"; 3114 arm,coresight-loses-context-with-cpu; 3115 qcom,skip-power-up; 3116 3117 out-ports { 3118 port { 3119 etm3_out: endpoint { 3120 remote-endpoint = <&apss_funnel_in3>; 3121 }; 3122 }; 3123 }; 3124 }; 3125 3126 etm@7440000 { 3127 compatible = "arm,coresight-etm4x", "arm,primecell"; 3128 reg = <0 0x07440000 0 0x1000>; 3129 3130 cpu = <&CPU4>; 3131 3132 clocks = <&aoss_qmp>; 3133 clock-names = "apb_pclk"; 3134 arm,coresight-loses-context-with-cpu; 3135 qcom,skip-power-up; 3136 3137 out-ports { 3138 port { 3139 etm4_out: endpoint { 3140 remote-endpoint = <&apss_funnel_in4>; 3141 }; 3142 }; 3143 }; 3144 }; 3145 3146 etm@7540000 { 3147 compatible = "arm,coresight-etm4x", "arm,primecell"; 3148 reg = <0 0x07540000 0 0x1000>; 3149 3150 cpu = <&CPU5>; 3151 3152 clocks = <&aoss_qmp>; 3153 clock-names = "apb_pclk"; 3154 arm,coresight-loses-context-with-cpu; 3155 qcom,skip-power-up; 3156 3157 out-ports { 3158 port { 3159 etm5_out: endpoint { 3160 remote-endpoint = <&apss_funnel_in5>; 3161 }; 3162 }; 3163 }; 3164 }; 3165 3166 etm@7640000 { 3167 compatible = "arm,coresight-etm4x", "arm,primecell"; 3168 reg = <0 0x07640000 0 0x1000>; 3169 3170 cpu = <&CPU6>; 3171 3172 clocks = <&aoss_qmp>; 3173 clock-names = "apb_pclk"; 3174 arm,coresight-loses-context-with-cpu; 3175 qcom,skip-power-up; 3176 3177 out-ports { 3178 port { 3179 etm6_out: endpoint { 3180 remote-endpoint = <&apss_funnel_in6>; 3181 }; 3182 }; 3183 }; 3184 }; 3185 3186 etm@7740000 { 3187 compatible = "arm,coresight-etm4x", "arm,primecell"; 3188 reg = <0 0x07740000 0 0x1000>; 3189 3190 cpu = <&CPU7>; 3191 3192 clocks = <&aoss_qmp>; 3193 clock-names = "apb_pclk"; 3194 arm,coresight-loses-context-with-cpu; 3195 qcom,skip-power-up; 3196 3197 out-ports { 3198 port { 3199 etm7_out: endpoint { 3200 remote-endpoint = <&apss_funnel_in7>; 3201 }; 3202 }; 3203 }; 3204 }; 3205 3206 funnel@7800000 { /* APSS Funnel */ 3207 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3208 reg = <0 0x07800000 0 0x1000>; 3209 3210 clocks = <&aoss_qmp>; 3211 clock-names = "apb_pclk"; 3212 3213 out-ports { 3214 port { 3215 apss_funnel_out: endpoint { 3216 remote-endpoint = <&apss_merge_funnel_in>; 3217 }; 3218 }; 3219 }; 3220 3221 in-ports { 3222 #address-cells = <1>; 3223 #size-cells = <0>; 3224 3225 port@0 { 3226 reg = <0>; 3227 apss_funnel_in0: endpoint { 3228 remote-endpoint = <&etm0_out>; 3229 }; 3230 }; 3231 3232 port@1 { 3233 reg = <1>; 3234 apss_funnel_in1: endpoint { 3235 remote-endpoint = <&etm1_out>; 3236 }; 3237 }; 3238 3239 port@2 { 3240 reg = <2>; 3241 apss_funnel_in2: endpoint { 3242 remote-endpoint = <&etm2_out>; 3243 }; 3244 }; 3245 3246 port@3 { 3247 reg = <3>; 3248 apss_funnel_in3: endpoint { 3249 remote-endpoint = <&etm3_out>; 3250 }; 3251 }; 3252 3253 port@4 { 3254 reg = <4>; 3255 apss_funnel_in4: endpoint { 3256 remote-endpoint = <&etm4_out>; 3257 }; 3258 }; 3259 3260 port@5 { 3261 reg = <5>; 3262 apss_funnel_in5: endpoint { 3263 remote-endpoint = <&etm5_out>; 3264 }; 3265 }; 3266 3267 port@6 { 3268 reg = <6>; 3269 apss_funnel_in6: endpoint { 3270 remote-endpoint = <&etm6_out>; 3271 }; 3272 }; 3273 3274 port@7 { 3275 reg = <7>; 3276 apss_funnel_in7: endpoint { 3277 remote-endpoint = <&etm7_out>; 3278 }; 3279 }; 3280 }; 3281 }; 3282 3283 funnel@7810000 { 3284 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3285 reg = <0 0x07810000 0 0x1000>; 3286 3287 clocks = <&aoss_qmp>; 3288 clock-names = "apb_pclk"; 3289 3290 out-ports { 3291 port { 3292 apss_merge_funnel_out: endpoint { 3293 remote-endpoint = <&funnel1_in4>; 3294 }; 3295 }; 3296 }; 3297 3298 in-ports { 3299 port { 3300 apss_merge_funnel_in: endpoint { 3301 remote-endpoint = <&apss_funnel_out>; 3302 }; 3303 }; 3304 }; 3305 }; 3306 3307 sdhc_2: mmc@8804000 { 3308 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3309 pinctrl-names = "default", "sleep"; 3310 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3311 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3312 status = "disabled"; 3313 3314 reg = <0 0x08804000 0 0x1000>; 3315 3316 iommus = <&apps_smmu 0x100 0x0>; 3317 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3318 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3319 interrupt-names = "hc_irq", "pwr_irq"; 3320 3321 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3322 <&gcc GCC_SDCC2_APPS_CLK>, 3323 <&rpmhcc RPMH_CXO_CLK>; 3324 clock-names = "iface", "core", "xo"; 3325 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3326 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3327 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3328 power-domains = <&rpmhpd SC7280_CX>; 3329 operating-points-v2 = <&sdhc2_opp_table>; 3330 3331 bus-width = <4>; 3332 3333 qcom,dll-config = <0x0007642c>; 3334 3335 resets = <&gcc GCC_SDCC2_BCR>; 3336 3337 sdhc2_opp_table: opp-table { 3338 compatible = "operating-points-v2"; 3339 3340 opp-100000000 { 3341 opp-hz = /bits/ 64 <100000000>; 3342 required-opps = <&rpmhpd_opp_low_svs>; 3343 opp-peak-kBps = <1800000 400000>; 3344 opp-avg-kBps = <100000 0>; 3345 }; 3346 3347 opp-202000000 { 3348 opp-hz = /bits/ 64 <202000000>; 3349 required-opps = <&rpmhpd_opp_nom>; 3350 opp-peak-kBps = <5400000 1600000>; 3351 opp-avg-kBps = <200000 0>; 3352 }; 3353 }; 3354 }; 3355 3356 usb_1_hsphy: phy@88e3000 { 3357 compatible = "qcom,sc7280-usb-hs-phy", 3358 "qcom,usb-snps-hs-7nm-phy"; 3359 reg = <0 0x088e3000 0 0x400>; 3360 status = "disabled"; 3361 #phy-cells = <0>; 3362 3363 clocks = <&rpmhcc RPMH_CXO_CLK>; 3364 clock-names = "ref"; 3365 3366 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3367 }; 3368 3369 usb_2_hsphy: phy@88e4000 { 3370 compatible = "qcom,sc7280-usb-hs-phy", 3371 "qcom,usb-snps-hs-7nm-phy"; 3372 reg = <0 0x088e4000 0 0x400>; 3373 status = "disabled"; 3374 #phy-cells = <0>; 3375 3376 clocks = <&rpmhcc RPMH_CXO_CLK>; 3377 clock-names = "ref"; 3378 3379 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3380 }; 3381 3382 usb_1_qmpphy: phy@88e8000 { 3383 compatible = "qcom,sc7280-qmp-usb3-dp-phy"; 3384 reg = <0 0x088e8000 0 0x3000>; 3385 status = "disabled"; 3386 3387 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3388 <&rpmhcc RPMH_CXO_CLK>, 3389 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3390 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3391 clock-names = "aux", 3392 "ref", 3393 "com_aux", 3394 "usb3_pipe"; 3395 3396 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3397 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3398 reset-names = "phy", "common"; 3399 3400 #clock-cells = <1>; 3401 #phy-cells = <1>; 3402 }; 3403 3404 usb_2: usb@8cf8800 { 3405 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3406 reg = <0 0x08cf8800 0 0x400>; 3407 status = "disabled"; 3408 #address-cells = <2>; 3409 #size-cells = <2>; 3410 ranges; 3411 dma-ranges; 3412 3413 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3414 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3415 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3416 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3417 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3418 clock-names = "cfg_noc", 3419 "core", 3420 "iface", 3421 "sleep", 3422 "mock_utmi"; 3423 3424 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3425 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3426 assigned-clock-rates = <19200000>, <200000000>; 3427 3428 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3429 <&pdc 12 IRQ_TYPE_EDGE_RISING>, 3430 <&pdc 13 IRQ_TYPE_EDGE_RISING>; 3431 interrupt-names = "hs_phy_irq", 3432 "dp_hs_phy_irq", 3433 "dm_hs_phy_irq"; 3434 3435 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3436 required-opps = <&rpmhpd_opp_nom>; 3437 3438 resets = <&gcc GCC_USB30_SEC_BCR>; 3439 3440 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3441 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3442 interconnect-names = "usb-ddr", "apps-usb"; 3443 3444 usb_2_dwc3: usb@8c00000 { 3445 compatible = "snps,dwc3"; 3446 reg = <0 0x08c00000 0 0xe000>; 3447 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3448 iommus = <&apps_smmu 0xa0 0x0>; 3449 snps,dis_u2_susphy_quirk; 3450 snps,dis_enblslpm_quirk; 3451 phys = <&usb_2_hsphy>; 3452 phy-names = "usb2-phy"; 3453 maximum-speed = "high-speed"; 3454 usb-role-switch; 3455 3456 port { 3457 usb2_role_switch: endpoint { 3458 remote-endpoint = <&eud_ep>; 3459 }; 3460 }; 3461 }; 3462 }; 3463 3464 qspi: spi@88dc000 { 3465 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3466 reg = <0 0x088dc000 0 0x1000>; 3467 iommus = <&apps_smmu 0x20 0x0>; 3468 #address-cells = <1>; 3469 #size-cells = <0>; 3470 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3471 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3472 <&gcc GCC_QSPI_CORE_CLK>; 3473 clock-names = "iface", "core"; 3474 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3475 &cnoc2 SLAVE_QSPI_0 0>; 3476 interconnect-names = "qspi-config"; 3477 power-domains = <&rpmhpd SC7280_CX>; 3478 operating-points-v2 = <&qspi_opp_table>; 3479 status = "disabled"; 3480 }; 3481 3482 remoteproc_wpss: remoteproc@8a00000 { 3483 compatible = "qcom,sc7280-wpss-pil"; 3484 reg = <0 0x08a00000 0 0x10000>; 3485 3486 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3487 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3488 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3489 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3490 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3491 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3492 interrupt-names = "wdog", "fatal", "ready", "handover", 3493 "stop-ack", "shutdown-ack"; 3494 3495 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 3496 <&gcc GCC_WPSS_AHB_CLK>, 3497 <&gcc GCC_WPSS_RSCP_CLK>, 3498 <&rpmhcc RPMH_CXO_CLK>; 3499 clock-names = "ahb_bdg", "ahb", 3500 "rscp", "xo"; 3501 3502 power-domains = <&rpmhpd SC7280_CX>, 3503 <&rpmhpd SC7280_MX>; 3504 power-domain-names = "cx", "mx"; 3505 3506 memory-region = <&wpss_mem>; 3507 3508 qcom,qmp = <&aoss_qmp>; 3509 3510 qcom,smem-states = <&wpss_smp2p_out 0>; 3511 qcom,smem-state-names = "stop"; 3512 3513 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 3514 <&pdc_reset PDC_WPSS_SYNC_RESET>; 3515 reset-names = "restart", "pdc_sync"; 3516 3517 qcom,halt-regs = <&tcsr_1 0x17000>; 3518 3519 status = "disabled"; 3520 3521 glink-edge { 3522 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3523 IPCC_MPROC_SIGNAL_GLINK_QMP 3524 IRQ_TYPE_EDGE_RISING>; 3525 mboxes = <&ipcc IPCC_CLIENT_WPSS 3526 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3527 3528 label = "wpss"; 3529 qcom,remote-pid = <13>; 3530 }; 3531 }; 3532 3533 pmu@9091000 { 3534 compatible = "qcom,sc7280-llcc-bwmon"; 3535 reg = <0 0x09091000 0 0x1000>; 3536 3537 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3538 3539 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3540 3541 operating-points-v2 = <&llcc_bwmon_opp_table>; 3542 3543 llcc_bwmon_opp_table: opp-table { 3544 compatible = "operating-points-v2"; 3545 3546 opp-0 { 3547 opp-peak-kBps = <800000>; 3548 }; 3549 opp-1 { 3550 opp-peak-kBps = <1804000>; 3551 }; 3552 opp-2 { 3553 opp-peak-kBps = <2188000>; 3554 }; 3555 opp-3 { 3556 opp-peak-kBps = <3072000>; 3557 }; 3558 opp-4 { 3559 opp-peak-kBps = <4068000>; 3560 }; 3561 opp-5 { 3562 opp-peak-kBps = <6220000>; 3563 }; 3564 opp-6 { 3565 opp-peak-kBps = <6832000>; 3566 }; 3567 opp-7 { 3568 opp-peak-kBps = <8532000>; 3569 }; 3570 }; 3571 }; 3572 3573 pmu@90b6400 { 3574 compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon"; 3575 reg = <0 0x090b6400 0 0x600>; 3576 3577 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3578 3579 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3580 operating-points-v2 = <&cpu_bwmon_opp_table>; 3581 3582 cpu_bwmon_opp_table: opp-table { 3583 compatible = "operating-points-v2"; 3584 3585 opp-0 { 3586 opp-peak-kBps = <2400000>; 3587 }; 3588 opp-1 { 3589 opp-peak-kBps = <4800000>; 3590 }; 3591 opp-2 { 3592 opp-peak-kBps = <7456000>; 3593 }; 3594 opp-3 { 3595 opp-peak-kBps = <9600000>; 3596 }; 3597 opp-4 { 3598 opp-peak-kBps = <12896000>; 3599 }; 3600 opp-5 { 3601 opp-peak-kBps = <14928000>; 3602 }; 3603 opp-6 { 3604 opp-peak-kBps = <17056000>; 3605 }; 3606 }; 3607 }; 3608 3609 dc_noc: interconnect@90e0000 { 3610 reg = <0 0x090e0000 0 0x5080>; 3611 compatible = "qcom,sc7280-dc-noc"; 3612 #interconnect-cells = <2>; 3613 qcom,bcm-voters = <&apps_bcm_voter>; 3614 }; 3615 3616 gem_noc: interconnect@9100000 { 3617 reg = <0 0x09100000 0 0xe2200>; 3618 compatible = "qcom,sc7280-gem-noc"; 3619 #interconnect-cells = <2>; 3620 qcom,bcm-voters = <&apps_bcm_voter>; 3621 }; 3622 3623 system-cache-controller@9200000 { 3624 compatible = "qcom,sc7280-llcc"; 3625 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 3626 <0 0x09600000 0 0x58000>; 3627 reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; 3628 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3629 }; 3630 3631 eud: eud@88e0000 { 3632 compatible = "qcom,sc7280-eud", "qcom,eud"; 3633 reg = <0 0x88e0000 0 0x2000>, 3634 <0 0x88e2000 0 0x1000>; 3635 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 3636 3637 status = "disabled"; 3638 3639 ports { 3640 #address-cells = <1>; 3641 #size-cells = <0>; 3642 3643 port@0 { 3644 reg = <0>; 3645 eud_ep: endpoint { 3646 remote-endpoint = <&usb2_role_switch>; 3647 }; 3648 }; 3649 }; 3650 }; 3651 3652 nsp_noc: interconnect@a0c0000 { 3653 reg = <0 0x0a0c0000 0 0x10000>; 3654 compatible = "qcom,sc7280-nsp-noc"; 3655 #interconnect-cells = <2>; 3656 qcom,bcm-voters = <&apps_bcm_voter>; 3657 }; 3658 3659 usb_1: usb@a6f8800 { 3660 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3661 reg = <0 0x0a6f8800 0 0x400>; 3662 status = "disabled"; 3663 #address-cells = <2>; 3664 #size-cells = <2>; 3665 ranges; 3666 dma-ranges; 3667 3668 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3669 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3670 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3671 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3672 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 3673 clock-names = "cfg_noc", 3674 "core", 3675 "iface", 3676 "sleep", 3677 "mock_utmi"; 3678 3679 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3680 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3681 assigned-clock-rates = <19200000>, <200000000>; 3682 3683 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3684 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, 3685 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3686 <&pdc 17 IRQ_TYPE_EDGE_BOTH>; 3687 interrupt-names = "hs_phy_irq", 3688 "dp_hs_phy_irq", 3689 "dm_hs_phy_irq", 3690 "ss_phy_irq"; 3691 3692 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3693 required-opps = <&rpmhpd_opp_nom>; 3694 3695 resets = <&gcc GCC_USB30_PRIM_BCR>; 3696 3697 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3698 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 3699 interconnect-names = "usb-ddr", "apps-usb"; 3700 3701 wakeup-source; 3702 3703 usb_1_dwc3: usb@a600000 { 3704 compatible = "snps,dwc3"; 3705 reg = <0 0x0a600000 0 0xe000>; 3706 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3707 iommus = <&apps_smmu 0xe0 0x0>; 3708 snps,dis_u2_susphy_quirk; 3709 snps,dis_enblslpm_quirk; 3710 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 3711 phy-names = "usb2-phy", "usb3-phy"; 3712 maximum-speed = "super-speed"; 3713 }; 3714 }; 3715 3716 venus: video-codec@aa00000 { 3717 compatible = "qcom,sc7280-venus"; 3718 reg = <0 0x0aa00000 0 0xd0600>; 3719 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3720 3721 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 3722 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 3723 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3724 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 3725 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 3726 clock-names = "core", "bus", "iface", 3727 "vcodec_core", "vcodec_bus"; 3728 3729 power-domains = <&videocc MVSC_GDSC>, 3730 <&videocc MVS0_GDSC>, 3731 <&rpmhpd SC7280_CX>; 3732 power-domain-names = "venus", "vcodec0", "cx"; 3733 operating-points-v2 = <&venus_opp_table>; 3734 3735 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 3736 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 3737 interconnect-names = "cpu-cfg", "video-mem"; 3738 3739 iommus = <&apps_smmu 0x2180 0x20>, 3740 <&apps_smmu 0x2184 0x20>; 3741 memory-region = <&video_mem>; 3742 3743 video-decoder { 3744 compatible = "venus-decoder"; 3745 }; 3746 3747 video-encoder { 3748 compatible = "venus-encoder"; 3749 }; 3750 3751 video-firmware { 3752 iommus = <&apps_smmu 0x21a2 0x0>; 3753 }; 3754 3755 venus_opp_table: opp-table { 3756 compatible = "operating-points-v2"; 3757 3758 opp-133330000 { 3759 opp-hz = /bits/ 64 <133330000>; 3760 required-opps = <&rpmhpd_opp_low_svs>; 3761 }; 3762 3763 opp-240000000 { 3764 opp-hz = /bits/ 64 <240000000>; 3765 required-opps = <&rpmhpd_opp_svs>; 3766 }; 3767 3768 opp-335000000 { 3769 opp-hz = /bits/ 64 <335000000>; 3770 required-opps = <&rpmhpd_opp_svs_l1>; 3771 }; 3772 3773 opp-424000000 { 3774 opp-hz = /bits/ 64 <424000000>; 3775 required-opps = <&rpmhpd_opp_nom>; 3776 }; 3777 3778 opp-460000048 { 3779 opp-hz = /bits/ 64 <460000048>; 3780 required-opps = <&rpmhpd_opp_turbo>; 3781 }; 3782 }; 3783 }; 3784 3785 videocc: clock-controller@aaf0000 { 3786 compatible = "qcom,sc7280-videocc"; 3787 reg = <0 0x0aaf0000 0 0x10000>; 3788 clocks = <&rpmhcc RPMH_CXO_CLK>, 3789 <&rpmhcc RPMH_CXO_CLK_A>; 3790 clock-names = "bi_tcxo", "bi_tcxo_ao"; 3791 #clock-cells = <1>; 3792 #reset-cells = <1>; 3793 #power-domain-cells = <1>; 3794 }; 3795 3796 camcc: clock-controller@ad00000 { 3797 compatible = "qcom,sc7280-camcc"; 3798 reg = <0 0x0ad00000 0 0x10000>; 3799 clocks = <&rpmhcc RPMH_CXO_CLK>, 3800 <&rpmhcc RPMH_CXO_CLK_A>, 3801 <&sleep_clk>; 3802 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 3803 #clock-cells = <1>; 3804 #reset-cells = <1>; 3805 #power-domain-cells = <1>; 3806 }; 3807 3808 dispcc: clock-controller@af00000 { 3809 compatible = "qcom,sc7280-dispcc"; 3810 reg = <0 0x0af00000 0 0x20000>; 3811 clocks = <&rpmhcc RPMH_CXO_CLK>, 3812 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 3813 <&mdss_dsi_phy 0>, 3814 <&mdss_dsi_phy 1>, 3815 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3816 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3817 <&mdss_edp_phy 0>, 3818 <&mdss_edp_phy 1>; 3819 clock-names = "bi_tcxo", 3820 "gcc_disp_gpll0_clk", 3821 "dsi0_phy_pll_out_byteclk", 3822 "dsi0_phy_pll_out_dsiclk", 3823 "dp_phy_pll_link_clk", 3824 "dp_phy_pll_vco_div_clk", 3825 "edp_phy_pll_link_clk", 3826 "edp_phy_pll_vco_div_clk"; 3827 #clock-cells = <1>; 3828 #reset-cells = <1>; 3829 #power-domain-cells = <1>; 3830 }; 3831 3832 mdss: display-subsystem@ae00000 { 3833 compatible = "qcom,sc7280-mdss"; 3834 reg = <0 0x0ae00000 0 0x1000>; 3835 reg-names = "mdss"; 3836 3837 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3838 3839 clocks = <&gcc GCC_DISP_AHB_CLK>, 3840 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3841 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3842 clock-names = "iface", 3843 "ahb", 3844 "core"; 3845 3846 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3847 interrupt-controller; 3848 #interrupt-cells = <1>; 3849 3850 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>; 3851 interconnect-names = "mdp0-mem"; 3852 3853 iommus = <&apps_smmu 0x900 0x402>; 3854 3855 #address-cells = <2>; 3856 #size-cells = <2>; 3857 ranges; 3858 3859 status = "disabled"; 3860 3861 mdss_mdp: display-controller@ae01000 { 3862 compatible = "qcom,sc7280-dpu"; 3863 reg = <0 0x0ae01000 0 0x8f030>, 3864 <0 0x0aeb0000 0 0x2008>; 3865 reg-names = "mdp", "vbif"; 3866 3867 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3868 <&gcc GCC_DISP_SF_AXI_CLK>, 3869 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3870 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3871 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3872 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3873 clock-names = "bus", 3874 "nrt_bus", 3875 "iface", 3876 "lut", 3877 "core", 3878 "vsync"; 3879 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 3880 <&dispcc DISP_CC_MDSS_AHB_CLK>; 3881 assigned-clock-rates = <19200000>, 3882 <19200000>; 3883 operating-points-v2 = <&mdp_opp_table>; 3884 power-domains = <&rpmhpd SC7280_CX>; 3885 3886 interrupt-parent = <&mdss>; 3887 interrupts = <0>; 3888 3889 ports { 3890 #address-cells = <1>; 3891 #size-cells = <0>; 3892 3893 port@0 { 3894 reg = <0>; 3895 dpu_intf1_out: endpoint { 3896 remote-endpoint = <&mdss_dsi0_in>; 3897 }; 3898 }; 3899 3900 port@1 { 3901 reg = <1>; 3902 dpu_intf5_out: endpoint { 3903 remote-endpoint = <&edp_in>; 3904 }; 3905 }; 3906 3907 port@2 { 3908 reg = <2>; 3909 dpu_intf0_out: endpoint { 3910 remote-endpoint = <&dp_in>; 3911 }; 3912 }; 3913 }; 3914 3915 mdp_opp_table: opp-table { 3916 compatible = "operating-points-v2"; 3917 3918 opp-200000000 { 3919 opp-hz = /bits/ 64 <200000000>; 3920 required-opps = <&rpmhpd_opp_low_svs>; 3921 }; 3922 3923 opp-300000000 { 3924 opp-hz = /bits/ 64 <300000000>; 3925 required-opps = <&rpmhpd_opp_svs>; 3926 }; 3927 3928 opp-380000000 { 3929 opp-hz = /bits/ 64 <380000000>; 3930 required-opps = <&rpmhpd_opp_svs_l1>; 3931 }; 3932 3933 opp-506666667 { 3934 opp-hz = /bits/ 64 <506666667>; 3935 required-opps = <&rpmhpd_opp_nom>; 3936 }; 3937 }; 3938 }; 3939 3940 mdss_dsi: dsi@ae94000 { 3941 compatible = "qcom,sc7280-dsi-ctrl", 3942 "qcom,mdss-dsi-ctrl"; 3943 reg = <0 0x0ae94000 0 0x400>; 3944 reg-names = "dsi_ctrl"; 3945 3946 interrupt-parent = <&mdss>; 3947 interrupts = <4>; 3948 3949 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3950 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3951 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3952 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3953 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3954 <&gcc GCC_DISP_HF_AXI_CLK>; 3955 clock-names = "byte", 3956 "byte_intf", 3957 "pixel", 3958 "core", 3959 "iface", 3960 "bus"; 3961 3962 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3963 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>; 3964 3965 operating-points-v2 = <&dsi_opp_table>; 3966 power-domains = <&rpmhpd SC7280_CX>; 3967 3968 phys = <&mdss_dsi_phy>; 3969 3970 #address-cells = <1>; 3971 #size-cells = <0>; 3972 3973 status = "disabled"; 3974 3975 ports { 3976 #address-cells = <1>; 3977 #size-cells = <0>; 3978 3979 port@0 { 3980 reg = <0>; 3981 mdss_dsi0_in: endpoint { 3982 remote-endpoint = <&dpu_intf1_out>; 3983 }; 3984 }; 3985 3986 port@1 { 3987 reg = <1>; 3988 mdss_dsi0_out: endpoint { 3989 }; 3990 }; 3991 }; 3992 3993 dsi_opp_table: opp-table { 3994 compatible = "operating-points-v2"; 3995 3996 opp-187500000 { 3997 opp-hz = /bits/ 64 <187500000>; 3998 required-opps = <&rpmhpd_opp_low_svs>; 3999 }; 4000 4001 opp-300000000 { 4002 opp-hz = /bits/ 64 <300000000>; 4003 required-opps = <&rpmhpd_opp_svs>; 4004 }; 4005 4006 opp-358000000 { 4007 opp-hz = /bits/ 64 <358000000>; 4008 required-opps = <&rpmhpd_opp_svs_l1>; 4009 }; 4010 }; 4011 }; 4012 4013 mdss_dsi_phy: phy@ae94400 { 4014 compatible = "qcom,sc7280-dsi-phy-7nm"; 4015 reg = <0 0x0ae94400 0 0x200>, 4016 <0 0x0ae94600 0 0x280>, 4017 <0 0x0ae94900 0 0x280>; 4018 reg-names = "dsi_phy", 4019 "dsi_phy_lane", 4020 "dsi_pll"; 4021 4022 #clock-cells = <1>; 4023 #phy-cells = <0>; 4024 4025 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4026 <&rpmhcc RPMH_CXO_CLK>; 4027 clock-names = "iface", "ref"; 4028 4029 status = "disabled"; 4030 }; 4031 4032 mdss_edp: edp@aea0000 { 4033 compatible = "qcom,sc7280-edp"; 4034 pinctrl-names = "default"; 4035 pinctrl-0 = <&edp_hot_plug_det>; 4036 4037 reg = <0 0x0aea0000 0 0x200>, 4038 <0 0x0aea0200 0 0x200>, 4039 <0 0x0aea0400 0 0xc00>, 4040 <0 0x0aea1000 0 0x400>; 4041 4042 interrupt-parent = <&mdss>; 4043 interrupts = <14>; 4044 4045 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4046 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 4047 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 4048 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 4049 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 4050 clock-names = "core_iface", 4051 "core_aux", 4052 "ctrl_link", 4053 "ctrl_link_iface", 4054 "stream_pixel"; 4055 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 4056 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 4057 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 4058 4059 phys = <&mdss_edp_phy>; 4060 phy-names = "dp"; 4061 4062 operating-points-v2 = <&edp_opp_table>; 4063 power-domains = <&rpmhpd SC7280_CX>; 4064 4065 status = "disabled"; 4066 4067 ports { 4068 #address-cells = <1>; 4069 #size-cells = <0>; 4070 4071 port@0 { 4072 reg = <0>; 4073 edp_in: endpoint { 4074 remote-endpoint = <&dpu_intf5_out>; 4075 }; 4076 }; 4077 4078 port@1 { 4079 reg = <1>; 4080 mdss_edp_out: endpoint { }; 4081 }; 4082 }; 4083 4084 edp_opp_table: opp-table { 4085 compatible = "operating-points-v2"; 4086 4087 opp-160000000 { 4088 opp-hz = /bits/ 64 <160000000>; 4089 required-opps = <&rpmhpd_opp_low_svs>; 4090 }; 4091 4092 opp-270000000 { 4093 opp-hz = /bits/ 64 <270000000>; 4094 required-opps = <&rpmhpd_opp_svs>; 4095 }; 4096 4097 opp-540000000 { 4098 opp-hz = /bits/ 64 <540000000>; 4099 required-opps = <&rpmhpd_opp_nom>; 4100 }; 4101 4102 opp-810000000 { 4103 opp-hz = /bits/ 64 <810000000>; 4104 required-opps = <&rpmhpd_opp_nom>; 4105 }; 4106 }; 4107 }; 4108 4109 mdss_edp_phy: phy@aec2a00 { 4110 compatible = "qcom,sc7280-edp-phy"; 4111 4112 reg = <0 0x0aec2a00 0 0x19c>, 4113 <0 0x0aec2200 0 0xa0>, 4114 <0 0x0aec2600 0 0xa0>, 4115 <0 0x0aec2000 0 0x1c0>; 4116 4117 clocks = <&rpmhcc RPMH_CXO_CLK>, 4118 <&gcc GCC_EDP_CLKREF_EN>; 4119 clock-names = "aux", 4120 "cfg_ahb"; 4121 4122 #clock-cells = <1>; 4123 #phy-cells = <0>; 4124 4125 status = "disabled"; 4126 }; 4127 4128 mdss_dp: displayport-controller@ae90000 { 4129 compatible = "qcom,sc7280-dp"; 4130 4131 reg = <0 0x0ae90000 0 0x200>, 4132 <0 0x0ae90200 0 0x200>, 4133 <0 0x0ae90400 0 0xc00>, 4134 <0 0x0ae91000 0 0x400>, 4135 <0 0x0ae91400 0 0x400>; 4136 4137 interrupt-parent = <&mdss>; 4138 interrupts = <12>; 4139 4140 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4141 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4142 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4143 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4144 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4145 clock-names = "core_iface", 4146 "core_aux", 4147 "ctrl_link", 4148 "ctrl_link_iface", 4149 "stream_pixel"; 4150 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4151 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4152 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4153 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4154 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 4155 phy-names = "dp"; 4156 4157 operating-points-v2 = <&dp_opp_table>; 4158 power-domains = <&rpmhpd SC7280_CX>; 4159 4160 #sound-dai-cells = <0>; 4161 4162 status = "disabled"; 4163 4164 ports { 4165 #address-cells = <1>; 4166 #size-cells = <0>; 4167 4168 port@0 { 4169 reg = <0>; 4170 dp_in: endpoint { 4171 remote-endpoint = <&dpu_intf0_out>; 4172 }; 4173 }; 4174 4175 port@1 { 4176 reg = <1>; 4177 mdss_dp_out: endpoint { }; 4178 }; 4179 }; 4180 4181 dp_opp_table: opp-table { 4182 compatible = "operating-points-v2"; 4183 4184 opp-160000000 { 4185 opp-hz = /bits/ 64 <160000000>; 4186 required-opps = <&rpmhpd_opp_low_svs>; 4187 }; 4188 4189 opp-270000000 { 4190 opp-hz = /bits/ 64 <270000000>; 4191 required-opps = <&rpmhpd_opp_svs>; 4192 }; 4193 4194 opp-540000000 { 4195 opp-hz = /bits/ 64 <540000000>; 4196 required-opps = <&rpmhpd_opp_svs_l1>; 4197 }; 4198 4199 opp-810000000 { 4200 opp-hz = /bits/ 64 <810000000>; 4201 required-opps = <&rpmhpd_opp_nom>; 4202 }; 4203 }; 4204 }; 4205 }; 4206 4207 pdc: interrupt-controller@b220000 { 4208 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 4209 reg = <0 0x0b220000 0 0x30000>; 4210 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 4211 <55 306 4>, <59 312 3>, <62 374 2>, 4212 <64 434 2>, <66 438 3>, <69 86 1>, 4213 <70 520 54>, <124 609 31>, <155 63 1>, 4214 <156 716 12>; 4215 #interrupt-cells = <2>; 4216 interrupt-parent = <&intc>; 4217 interrupt-controller; 4218 }; 4219 4220 pdc_reset: reset-controller@b5e0000 { 4221 compatible = "qcom,sc7280-pdc-global"; 4222 reg = <0 0x0b5e0000 0 0x20000>; 4223 #reset-cells = <1>; 4224 status = "reserved"; /* Owned by firmware */ 4225 }; 4226 4227 tsens0: thermal-sensor@c263000 { 4228 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4229 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4230 <0 0x0c222000 0 0x1ff>; /* SROT */ 4231 #qcom,sensors = <15>; 4232 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4233 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4234 interrupt-names = "uplow","critical"; 4235 #thermal-sensor-cells = <1>; 4236 }; 4237 4238 tsens1: thermal-sensor@c265000 { 4239 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4240 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4241 <0 0x0c223000 0 0x1ff>; /* SROT */ 4242 #qcom,sensors = <12>; 4243 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4244 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4245 interrupt-names = "uplow","critical"; 4246 #thermal-sensor-cells = <1>; 4247 }; 4248 4249 aoss_reset: reset-controller@c2a0000 { 4250 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 4251 reg = <0 0x0c2a0000 0 0x31000>; 4252 #reset-cells = <1>; 4253 }; 4254 4255 aoss_qmp: power-management@c300000 { 4256 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 4257 reg = <0 0x0c300000 0 0x400>; 4258 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4259 IPCC_MPROC_SIGNAL_GLINK_QMP 4260 IRQ_TYPE_EDGE_RISING>; 4261 mboxes = <&ipcc IPCC_CLIENT_AOP 4262 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4263 4264 #clock-cells = <0>; 4265 }; 4266 4267 sram@c3f0000 { 4268 compatible = "qcom,rpmh-stats"; 4269 reg = <0 0x0c3f0000 0 0x400>; 4270 }; 4271 4272 spmi_bus: spmi@c440000 { 4273 compatible = "qcom,spmi-pmic-arb"; 4274 reg = <0 0x0c440000 0 0x1100>, 4275 <0 0x0c600000 0 0x2000000>, 4276 <0 0x0e600000 0 0x100000>, 4277 <0 0x0e700000 0 0xa0000>, 4278 <0 0x0c40a000 0 0x26000>; 4279 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4280 interrupt-names = "periph_irq"; 4281 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4282 qcom,ee = <0>; 4283 qcom,channel = <0>; 4284 #address-cells = <2>; 4285 #size-cells = <0>; 4286 interrupt-controller; 4287 #interrupt-cells = <4>; 4288 }; 4289 4290 tlmm: pinctrl@f100000 { 4291 compatible = "qcom,sc7280-pinctrl"; 4292 reg = <0 0x0f100000 0 0x300000>; 4293 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4294 gpio-controller; 4295 #gpio-cells = <2>; 4296 interrupt-controller; 4297 #interrupt-cells = <2>; 4298 gpio-ranges = <&tlmm 0 0 175>; 4299 wakeup-parent = <&pdc>; 4300 4301 dp_hot_plug_det: dp-hot-plug-det-state { 4302 pins = "gpio47"; 4303 function = "dp_hot"; 4304 }; 4305 4306 edp_hot_plug_det: edp-hot-plug-det-state { 4307 pins = "gpio60"; 4308 function = "edp_hot"; 4309 }; 4310 4311 mi2s0_data0: mi2s0-data0-state { 4312 pins = "gpio98"; 4313 function = "mi2s0_data0"; 4314 }; 4315 4316 mi2s0_data1: mi2s0-data1-state { 4317 pins = "gpio99"; 4318 function = "mi2s0_data1"; 4319 }; 4320 4321 mi2s0_mclk: mi2s0-mclk-state { 4322 pins = "gpio96"; 4323 function = "pri_mi2s"; 4324 }; 4325 4326 mi2s0_sclk: mi2s0-sclk-state { 4327 pins = "gpio97"; 4328 function = "mi2s0_sck"; 4329 }; 4330 4331 mi2s0_ws: mi2s0-ws-state { 4332 pins = "gpio100"; 4333 function = "mi2s0_ws"; 4334 }; 4335 4336 mi2s1_data0: mi2s1-data0-state { 4337 pins = "gpio107"; 4338 function = "mi2s1_data0"; 4339 }; 4340 4341 mi2s1_sclk: mi2s1-sclk-state { 4342 pins = "gpio106"; 4343 function = "mi2s1_sck"; 4344 }; 4345 4346 mi2s1_ws: mi2s1-ws-state { 4347 pins = "gpio108"; 4348 function = "mi2s1_ws"; 4349 }; 4350 4351 pcie1_clkreq_n: pcie1-clkreq-n-state { 4352 pins = "gpio79"; 4353 function = "pcie1_clkreqn"; 4354 }; 4355 4356 qspi_clk: qspi-clk-state { 4357 pins = "gpio14"; 4358 function = "qspi_clk"; 4359 }; 4360 4361 qspi_cs0: qspi-cs0-state { 4362 pins = "gpio15"; 4363 function = "qspi_cs"; 4364 }; 4365 4366 qspi_cs1: qspi-cs1-state { 4367 pins = "gpio19"; 4368 function = "qspi_cs"; 4369 }; 4370 4371 qspi_data0: qspi-data0-state { 4372 pins = "gpio12"; 4373 function = "qspi_data"; 4374 }; 4375 4376 qspi_data1: qspi-data1-state { 4377 pins = "gpio13"; 4378 function = "qspi_data"; 4379 }; 4380 4381 qspi_data23: qspi-data23-state { 4382 pins = "gpio16", "gpio17"; 4383 function = "qspi_data"; 4384 }; 4385 4386 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4387 pins = "gpio0", "gpio1"; 4388 function = "qup00"; 4389 }; 4390 4391 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4392 pins = "gpio4", "gpio5"; 4393 function = "qup01"; 4394 }; 4395 4396 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4397 pins = "gpio8", "gpio9"; 4398 function = "qup02"; 4399 }; 4400 4401 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4402 pins = "gpio12", "gpio13"; 4403 function = "qup03"; 4404 }; 4405 4406 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4407 pins = "gpio16", "gpio17"; 4408 function = "qup04"; 4409 }; 4410 4411 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4412 pins = "gpio20", "gpio21"; 4413 function = "qup05"; 4414 }; 4415 4416 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4417 pins = "gpio24", "gpio25"; 4418 function = "qup06"; 4419 }; 4420 4421 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 4422 pins = "gpio28", "gpio29"; 4423 function = "qup07"; 4424 }; 4425 4426 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4427 pins = "gpio32", "gpio33"; 4428 function = "qup10"; 4429 }; 4430 4431 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4432 pins = "gpio36", "gpio37"; 4433 function = "qup11"; 4434 }; 4435 4436 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4437 pins = "gpio40", "gpio41"; 4438 function = "qup12"; 4439 }; 4440 4441 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4442 pins = "gpio44", "gpio45"; 4443 function = "qup13"; 4444 }; 4445 4446 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4447 pins = "gpio48", "gpio49"; 4448 function = "qup14"; 4449 }; 4450 4451 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4452 pins = "gpio52", "gpio53"; 4453 function = "qup15"; 4454 }; 4455 4456 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 4457 pins = "gpio56", "gpio57"; 4458 function = "qup16"; 4459 }; 4460 4461 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4462 pins = "gpio60", "gpio61"; 4463 function = "qup17"; 4464 }; 4465 4466 qup_spi0_data_clk: qup-spi0-data-clk-state { 4467 pins = "gpio0", "gpio1", "gpio2"; 4468 function = "qup00"; 4469 }; 4470 4471 qup_spi0_cs: qup-spi0-cs-state { 4472 pins = "gpio3"; 4473 function = "qup00"; 4474 }; 4475 4476 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 4477 pins = "gpio3"; 4478 function = "gpio"; 4479 }; 4480 4481 qup_spi1_data_clk: qup-spi1-data-clk-state { 4482 pins = "gpio4", "gpio5", "gpio6"; 4483 function = "qup01"; 4484 }; 4485 4486 qup_spi1_cs: qup-spi1-cs-state { 4487 pins = "gpio7"; 4488 function = "qup01"; 4489 }; 4490 4491 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 4492 pins = "gpio7"; 4493 function = "gpio"; 4494 }; 4495 4496 qup_spi2_data_clk: qup-spi2-data-clk-state { 4497 pins = "gpio8", "gpio9", "gpio10"; 4498 function = "qup02"; 4499 }; 4500 4501 qup_spi2_cs: qup-spi2-cs-state { 4502 pins = "gpio11"; 4503 function = "qup02"; 4504 }; 4505 4506 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 4507 pins = "gpio11"; 4508 function = "gpio"; 4509 }; 4510 4511 qup_spi3_data_clk: qup-spi3-data-clk-state { 4512 pins = "gpio12", "gpio13", "gpio14"; 4513 function = "qup03"; 4514 }; 4515 4516 qup_spi3_cs: qup-spi3-cs-state { 4517 pins = "gpio15"; 4518 function = "qup03"; 4519 }; 4520 4521 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 4522 pins = "gpio15"; 4523 function = "gpio"; 4524 }; 4525 4526 qup_spi4_data_clk: qup-spi4-data-clk-state { 4527 pins = "gpio16", "gpio17", "gpio18"; 4528 function = "qup04"; 4529 }; 4530 4531 qup_spi4_cs: qup-spi4-cs-state { 4532 pins = "gpio19"; 4533 function = "qup04"; 4534 }; 4535 4536 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 4537 pins = "gpio19"; 4538 function = "gpio"; 4539 }; 4540 4541 qup_spi5_data_clk: qup-spi5-data-clk-state { 4542 pins = "gpio20", "gpio21", "gpio22"; 4543 function = "qup05"; 4544 }; 4545 4546 qup_spi5_cs: qup-spi5-cs-state { 4547 pins = "gpio23"; 4548 function = "qup05"; 4549 }; 4550 4551 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 4552 pins = "gpio23"; 4553 function = "gpio"; 4554 }; 4555 4556 qup_spi6_data_clk: qup-spi6-data-clk-state { 4557 pins = "gpio24", "gpio25", "gpio26"; 4558 function = "qup06"; 4559 }; 4560 4561 qup_spi6_cs: qup-spi6-cs-state { 4562 pins = "gpio27"; 4563 function = "qup06"; 4564 }; 4565 4566 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 4567 pins = "gpio27"; 4568 function = "gpio"; 4569 }; 4570 4571 qup_spi7_data_clk: qup-spi7-data-clk-state { 4572 pins = "gpio28", "gpio29", "gpio30"; 4573 function = "qup07"; 4574 }; 4575 4576 qup_spi7_cs: qup-spi7-cs-state { 4577 pins = "gpio31"; 4578 function = "qup07"; 4579 }; 4580 4581 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 4582 pins = "gpio31"; 4583 function = "gpio"; 4584 }; 4585 4586 qup_spi8_data_clk: qup-spi8-data-clk-state { 4587 pins = "gpio32", "gpio33", "gpio34"; 4588 function = "qup10"; 4589 }; 4590 4591 qup_spi8_cs: qup-spi8-cs-state { 4592 pins = "gpio35"; 4593 function = "qup10"; 4594 }; 4595 4596 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 4597 pins = "gpio35"; 4598 function = "gpio"; 4599 }; 4600 4601 qup_spi9_data_clk: qup-spi9-data-clk-state { 4602 pins = "gpio36", "gpio37", "gpio38"; 4603 function = "qup11"; 4604 }; 4605 4606 qup_spi9_cs: qup-spi9-cs-state { 4607 pins = "gpio39"; 4608 function = "qup11"; 4609 }; 4610 4611 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 4612 pins = "gpio39"; 4613 function = "gpio"; 4614 }; 4615 4616 qup_spi10_data_clk: qup-spi10-data-clk-state { 4617 pins = "gpio40", "gpio41", "gpio42"; 4618 function = "qup12"; 4619 }; 4620 4621 qup_spi10_cs: qup-spi10-cs-state { 4622 pins = "gpio43"; 4623 function = "qup12"; 4624 }; 4625 4626 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 4627 pins = "gpio43"; 4628 function = "gpio"; 4629 }; 4630 4631 qup_spi11_data_clk: qup-spi11-data-clk-state { 4632 pins = "gpio44", "gpio45", "gpio46"; 4633 function = "qup13"; 4634 }; 4635 4636 qup_spi11_cs: qup-spi11-cs-state { 4637 pins = "gpio47"; 4638 function = "qup13"; 4639 }; 4640 4641 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 4642 pins = "gpio47"; 4643 function = "gpio"; 4644 }; 4645 4646 qup_spi12_data_clk: qup-spi12-data-clk-state { 4647 pins = "gpio48", "gpio49", "gpio50"; 4648 function = "qup14"; 4649 }; 4650 4651 qup_spi12_cs: qup-spi12-cs-state { 4652 pins = "gpio51"; 4653 function = "qup14"; 4654 }; 4655 4656 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 4657 pins = "gpio51"; 4658 function = "gpio"; 4659 }; 4660 4661 qup_spi13_data_clk: qup-spi13-data-clk-state { 4662 pins = "gpio52", "gpio53", "gpio54"; 4663 function = "qup15"; 4664 }; 4665 4666 qup_spi13_cs: qup-spi13-cs-state { 4667 pins = "gpio55"; 4668 function = "qup15"; 4669 }; 4670 4671 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 4672 pins = "gpio55"; 4673 function = "gpio"; 4674 }; 4675 4676 qup_spi14_data_clk: qup-spi14-data-clk-state { 4677 pins = "gpio56", "gpio57", "gpio58"; 4678 function = "qup16"; 4679 }; 4680 4681 qup_spi14_cs: qup-spi14-cs-state { 4682 pins = "gpio59"; 4683 function = "qup16"; 4684 }; 4685 4686 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 4687 pins = "gpio59"; 4688 function = "gpio"; 4689 }; 4690 4691 qup_spi15_data_clk: qup-spi15-data-clk-state { 4692 pins = "gpio60", "gpio61", "gpio62"; 4693 function = "qup17"; 4694 }; 4695 4696 qup_spi15_cs: qup-spi15-cs-state { 4697 pins = "gpio63"; 4698 function = "qup17"; 4699 }; 4700 4701 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 4702 pins = "gpio63"; 4703 function = "gpio"; 4704 }; 4705 4706 qup_uart0_cts: qup-uart0-cts-state { 4707 pins = "gpio0"; 4708 function = "qup00"; 4709 }; 4710 4711 qup_uart0_rts: qup-uart0-rts-state { 4712 pins = "gpio1"; 4713 function = "qup00"; 4714 }; 4715 4716 qup_uart0_tx: qup-uart0-tx-state { 4717 pins = "gpio2"; 4718 function = "qup00"; 4719 }; 4720 4721 qup_uart0_rx: qup-uart0-rx-state { 4722 pins = "gpio3"; 4723 function = "qup00"; 4724 }; 4725 4726 qup_uart1_cts: qup-uart1-cts-state { 4727 pins = "gpio4"; 4728 function = "qup01"; 4729 }; 4730 4731 qup_uart1_rts: qup-uart1-rts-state { 4732 pins = "gpio5"; 4733 function = "qup01"; 4734 }; 4735 4736 qup_uart1_tx: qup-uart1-tx-state { 4737 pins = "gpio6"; 4738 function = "qup01"; 4739 }; 4740 4741 qup_uart1_rx: qup-uart1-rx-state { 4742 pins = "gpio7"; 4743 function = "qup01"; 4744 }; 4745 4746 qup_uart2_cts: qup-uart2-cts-state { 4747 pins = "gpio8"; 4748 function = "qup02"; 4749 }; 4750 4751 qup_uart2_rts: qup-uart2-rts-state { 4752 pins = "gpio9"; 4753 function = "qup02"; 4754 }; 4755 4756 qup_uart2_tx: qup-uart2-tx-state { 4757 pins = "gpio10"; 4758 function = "qup02"; 4759 }; 4760 4761 qup_uart2_rx: qup-uart2-rx-state { 4762 pins = "gpio11"; 4763 function = "qup02"; 4764 }; 4765 4766 qup_uart3_cts: qup-uart3-cts-state { 4767 pins = "gpio12"; 4768 function = "qup03"; 4769 }; 4770 4771 qup_uart3_rts: qup-uart3-rts-state { 4772 pins = "gpio13"; 4773 function = "qup03"; 4774 }; 4775 4776 qup_uart3_tx: qup-uart3-tx-state { 4777 pins = "gpio14"; 4778 function = "qup03"; 4779 }; 4780 4781 qup_uart3_rx: qup-uart3-rx-state { 4782 pins = "gpio15"; 4783 function = "qup03"; 4784 }; 4785 4786 qup_uart4_cts: qup-uart4-cts-state { 4787 pins = "gpio16"; 4788 function = "qup04"; 4789 }; 4790 4791 qup_uart4_rts: qup-uart4-rts-state { 4792 pins = "gpio17"; 4793 function = "qup04"; 4794 }; 4795 4796 qup_uart4_tx: qup-uart4-tx-state { 4797 pins = "gpio18"; 4798 function = "qup04"; 4799 }; 4800 4801 qup_uart4_rx: qup-uart4-rx-state { 4802 pins = "gpio19"; 4803 function = "qup04"; 4804 }; 4805 4806 qup_uart5_cts: qup-uart5-cts-state { 4807 pins = "gpio20"; 4808 function = "qup05"; 4809 }; 4810 4811 qup_uart5_rts: qup-uart5-rts-state { 4812 pins = "gpio21"; 4813 function = "qup05"; 4814 }; 4815 4816 qup_uart5_tx: qup-uart5-tx-state { 4817 pins = "gpio22"; 4818 function = "qup05"; 4819 }; 4820 4821 qup_uart5_rx: qup-uart5-rx-state { 4822 pins = "gpio23"; 4823 function = "qup05"; 4824 }; 4825 4826 qup_uart6_cts: qup-uart6-cts-state { 4827 pins = "gpio24"; 4828 function = "qup06"; 4829 }; 4830 4831 qup_uart6_rts: qup-uart6-rts-state { 4832 pins = "gpio25"; 4833 function = "qup06"; 4834 }; 4835 4836 qup_uart6_tx: qup-uart6-tx-state { 4837 pins = "gpio26"; 4838 function = "qup06"; 4839 }; 4840 4841 qup_uart6_rx: qup-uart6-rx-state { 4842 pins = "gpio27"; 4843 function = "qup06"; 4844 }; 4845 4846 qup_uart7_cts: qup-uart7-cts-state { 4847 pins = "gpio28"; 4848 function = "qup07"; 4849 }; 4850 4851 qup_uart7_rts: qup-uart7-rts-state { 4852 pins = "gpio29"; 4853 function = "qup07"; 4854 }; 4855 4856 qup_uart7_tx: qup-uart7-tx-state { 4857 pins = "gpio30"; 4858 function = "qup07"; 4859 }; 4860 4861 qup_uart7_rx: qup-uart7-rx-state { 4862 pins = "gpio31"; 4863 function = "qup07"; 4864 }; 4865 4866 qup_uart8_cts: qup-uart8-cts-state { 4867 pins = "gpio32"; 4868 function = "qup10"; 4869 }; 4870 4871 qup_uart8_rts: qup-uart8-rts-state { 4872 pins = "gpio33"; 4873 function = "qup10"; 4874 }; 4875 4876 qup_uart8_tx: qup-uart8-tx-state { 4877 pins = "gpio34"; 4878 function = "qup10"; 4879 }; 4880 4881 qup_uart8_rx: qup-uart8-rx-state { 4882 pins = "gpio35"; 4883 function = "qup10"; 4884 }; 4885 4886 qup_uart9_cts: qup-uart9-cts-state { 4887 pins = "gpio36"; 4888 function = "qup11"; 4889 }; 4890 4891 qup_uart9_rts: qup-uart9-rts-state { 4892 pins = "gpio37"; 4893 function = "qup11"; 4894 }; 4895 4896 qup_uart9_tx: qup-uart9-tx-state { 4897 pins = "gpio38"; 4898 function = "qup11"; 4899 }; 4900 4901 qup_uart9_rx: qup-uart9-rx-state { 4902 pins = "gpio39"; 4903 function = "qup11"; 4904 }; 4905 4906 qup_uart10_cts: qup-uart10-cts-state { 4907 pins = "gpio40"; 4908 function = "qup12"; 4909 }; 4910 4911 qup_uart10_rts: qup-uart10-rts-state { 4912 pins = "gpio41"; 4913 function = "qup12"; 4914 }; 4915 4916 qup_uart10_tx: qup-uart10-tx-state { 4917 pins = "gpio42"; 4918 function = "qup12"; 4919 }; 4920 4921 qup_uart10_rx: qup-uart10-rx-state { 4922 pins = "gpio43"; 4923 function = "qup12"; 4924 }; 4925 4926 qup_uart11_cts: qup-uart11-cts-state { 4927 pins = "gpio44"; 4928 function = "qup13"; 4929 }; 4930 4931 qup_uart11_rts: qup-uart11-rts-state { 4932 pins = "gpio45"; 4933 function = "qup13"; 4934 }; 4935 4936 qup_uart11_tx: qup-uart11-tx-state { 4937 pins = "gpio46"; 4938 function = "qup13"; 4939 }; 4940 4941 qup_uart11_rx: qup-uart11-rx-state { 4942 pins = "gpio47"; 4943 function = "qup13"; 4944 }; 4945 4946 qup_uart12_cts: qup-uart12-cts-state { 4947 pins = "gpio48"; 4948 function = "qup14"; 4949 }; 4950 4951 qup_uart12_rts: qup-uart12-rts-state { 4952 pins = "gpio49"; 4953 function = "qup14"; 4954 }; 4955 4956 qup_uart12_tx: qup-uart12-tx-state { 4957 pins = "gpio50"; 4958 function = "qup14"; 4959 }; 4960 4961 qup_uart12_rx: qup-uart12-rx-state { 4962 pins = "gpio51"; 4963 function = "qup14"; 4964 }; 4965 4966 qup_uart13_cts: qup-uart13-cts-state { 4967 pins = "gpio52"; 4968 function = "qup15"; 4969 }; 4970 4971 qup_uart13_rts: qup-uart13-rts-state { 4972 pins = "gpio53"; 4973 function = "qup15"; 4974 }; 4975 4976 qup_uart13_tx: qup-uart13-tx-state { 4977 pins = "gpio54"; 4978 function = "qup15"; 4979 }; 4980 4981 qup_uart13_rx: qup-uart13-rx-state { 4982 pins = "gpio55"; 4983 function = "qup15"; 4984 }; 4985 4986 qup_uart14_cts: qup-uart14-cts-state { 4987 pins = "gpio56"; 4988 function = "qup16"; 4989 }; 4990 4991 qup_uart14_rts: qup-uart14-rts-state { 4992 pins = "gpio57"; 4993 function = "qup16"; 4994 }; 4995 4996 qup_uart14_tx: qup-uart14-tx-state { 4997 pins = "gpio58"; 4998 function = "qup16"; 4999 }; 5000 5001 qup_uart14_rx: qup-uart14-rx-state { 5002 pins = "gpio59"; 5003 function = "qup16"; 5004 }; 5005 5006 qup_uart15_cts: qup-uart15-cts-state { 5007 pins = "gpio60"; 5008 function = "qup17"; 5009 }; 5010 5011 qup_uart15_rts: qup-uart15-rts-state { 5012 pins = "gpio61"; 5013 function = "qup17"; 5014 }; 5015 5016 qup_uart15_tx: qup-uart15-tx-state { 5017 pins = "gpio62"; 5018 function = "qup17"; 5019 }; 5020 5021 qup_uart15_rx: qup-uart15-rx-state { 5022 pins = "gpio63"; 5023 function = "qup17"; 5024 }; 5025 5026 sdc1_clk: sdc1-clk-state { 5027 pins = "sdc1_clk"; 5028 }; 5029 5030 sdc1_cmd: sdc1-cmd-state { 5031 pins = "sdc1_cmd"; 5032 }; 5033 5034 sdc1_data: sdc1-data-state { 5035 pins = "sdc1_data"; 5036 }; 5037 5038 sdc1_rclk: sdc1-rclk-state { 5039 pins = "sdc1_rclk"; 5040 }; 5041 5042 sdc1_clk_sleep: sdc1-clk-sleep-state { 5043 pins = "sdc1_clk"; 5044 drive-strength = <2>; 5045 bias-bus-hold; 5046 }; 5047 5048 sdc1_cmd_sleep: sdc1-cmd-sleep-state { 5049 pins = "sdc1_cmd"; 5050 drive-strength = <2>; 5051 bias-bus-hold; 5052 }; 5053 5054 sdc1_data_sleep: sdc1-data-sleep-state { 5055 pins = "sdc1_data"; 5056 drive-strength = <2>; 5057 bias-bus-hold; 5058 }; 5059 5060 sdc1_rclk_sleep: sdc1-rclk-sleep-state { 5061 pins = "sdc1_rclk"; 5062 drive-strength = <2>; 5063 bias-bus-hold; 5064 }; 5065 5066 sdc2_clk: sdc2-clk-state { 5067 pins = "sdc2_clk"; 5068 }; 5069 5070 sdc2_cmd: sdc2-cmd-state { 5071 pins = "sdc2_cmd"; 5072 }; 5073 5074 sdc2_data: sdc2-data-state { 5075 pins = "sdc2_data"; 5076 }; 5077 5078 sdc2_clk_sleep: sdc2-clk-sleep-state { 5079 pins = "sdc2_clk"; 5080 drive-strength = <2>; 5081 bias-bus-hold; 5082 }; 5083 5084 sdc2_cmd_sleep: sdc2-cmd-sleep-state { 5085 pins = "sdc2_cmd"; 5086 drive-strength = <2>; 5087 bias-bus-hold; 5088 }; 5089 5090 sdc2_data_sleep: sdc2-data-sleep-state { 5091 pins = "sdc2_data"; 5092 drive-strength = <2>; 5093 bias-bus-hold; 5094 }; 5095 }; 5096 5097 sram@146a5000 { 5098 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 5099 reg = <0 0x146a5000 0 0x6000>; 5100 5101 #address-cells = <1>; 5102 #size-cells = <1>; 5103 5104 ranges = <0 0 0x146a5000 0x6000>; 5105 5106 pil-reloc@594c { 5107 compatible = "qcom,pil-reloc-info"; 5108 reg = <0x594c 0xc8>; 5109 }; 5110 }; 5111 5112 apps_smmu: iommu@15000000 { 5113 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 5114 reg = <0 0x15000000 0 0x100000>; 5115 #iommu-cells = <2>; 5116 #global-interrupts = <1>; 5117 dma-coherent; 5118 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5119 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5120 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5121 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5122 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5123 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5124 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5125 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5126 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5127 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5128 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5129 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5130 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5131 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5132 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5133 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5134 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5135 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5136 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5137 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5138 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5139 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5140 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5141 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5142 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5143 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5144 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5145 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5146 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5147 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5148 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5149 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5150 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5151 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5152 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5153 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5154 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5155 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5156 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5157 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5158 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5159 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5160 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5161 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5162 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5163 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5164 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5165 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5166 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5167 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5168 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5169 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5170 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5171 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5172 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5173 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5174 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5175 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5176 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5177 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5178 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5179 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5180 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5181 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5182 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5183 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5184 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5185 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5186 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5187 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5188 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5189 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5190 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5191 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5192 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5193 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5194 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5195 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5196 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5197 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5198 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 5199 }; 5200 5201 intc: interrupt-controller@17a00000 { 5202 compatible = "arm,gic-v3"; 5203 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5204 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5205 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 5206 #interrupt-cells = <3>; 5207 interrupt-controller; 5208 #address-cells = <2>; 5209 #size-cells = <2>; 5210 ranges; 5211 5212 msi-controller@17a40000 { 5213 compatible = "arm,gic-v3-its"; 5214 reg = <0 0x17a40000 0 0x20000>; 5215 msi-controller; 5216 #msi-cells = <1>; 5217 status = "disabled"; 5218 }; 5219 }; 5220 5221 watchdog: watchdog@17c10000 { 5222 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 5223 reg = <0 0x17c10000 0 0x1000>; 5224 clocks = <&sleep_clk>; 5225 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 5226 status = "reserved"; /* Owned by Gunyah hyp */ 5227 }; 5228 5229 timer@17c20000 { 5230 #address-cells = <1>; 5231 #size-cells = <1>; 5232 ranges = <0 0 0 0x20000000>; 5233 compatible = "arm,armv7-timer-mem"; 5234 reg = <0 0x17c20000 0 0x1000>; 5235 5236 frame@17c21000 { 5237 frame-number = <0>; 5238 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5239 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5240 reg = <0x17c21000 0x1000>, 5241 <0x17c22000 0x1000>; 5242 }; 5243 5244 frame@17c23000 { 5245 frame-number = <1>; 5246 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5247 reg = <0x17c23000 0x1000>; 5248 status = "disabled"; 5249 }; 5250 5251 frame@17c25000 { 5252 frame-number = <2>; 5253 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5254 reg = <0x17c25000 0x1000>; 5255 status = "disabled"; 5256 }; 5257 5258 frame@17c27000 { 5259 frame-number = <3>; 5260 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5261 reg = <0x17c27000 0x1000>; 5262 status = "disabled"; 5263 }; 5264 5265 frame@17c29000 { 5266 frame-number = <4>; 5267 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5268 reg = <0x17c29000 0x1000>; 5269 status = "disabled"; 5270 }; 5271 5272 frame@17c2b000 { 5273 frame-number = <5>; 5274 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5275 reg = <0x17c2b000 0x1000>; 5276 status = "disabled"; 5277 }; 5278 5279 frame@17c2d000 { 5280 frame-number = <6>; 5281 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5282 reg = <0x17c2d000 0x1000>; 5283 status = "disabled"; 5284 }; 5285 }; 5286 5287 apps_rsc: rsc@18200000 { 5288 compatible = "qcom,rpmh-rsc"; 5289 reg = <0 0x18200000 0 0x10000>, 5290 <0 0x18210000 0 0x10000>, 5291 <0 0x18220000 0 0x10000>; 5292 reg-names = "drv-0", "drv-1", "drv-2"; 5293 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5294 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5295 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5296 qcom,tcs-offset = <0xd00>; 5297 qcom,drv-id = <2>; 5298 qcom,tcs-config = <ACTIVE_TCS 2>, 5299 <SLEEP_TCS 3>, 5300 <WAKE_TCS 3>, 5301 <CONTROL_TCS 1>; 5302 power-domains = <&CLUSTER_PD>; 5303 5304 apps_bcm_voter: bcm-voter { 5305 compatible = "qcom,bcm-voter"; 5306 }; 5307 5308 rpmhpd: power-controller { 5309 compatible = "qcom,sc7280-rpmhpd"; 5310 #power-domain-cells = <1>; 5311 operating-points-v2 = <&rpmhpd_opp_table>; 5312 5313 rpmhpd_opp_table: opp-table { 5314 compatible = "operating-points-v2"; 5315 5316 rpmhpd_opp_ret: opp1 { 5317 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5318 }; 5319 5320 rpmhpd_opp_low_svs: opp2 { 5321 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5322 }; 5323 5324 rpmhpd_opp_svs: opp3 { 5325 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5326 }; 5327 5328 rpmhpd_opp_svs_l1: opp4 { 5329 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5330 }; 5331 5332 rpmhpd_opp_svs_l2: opp5 { 5333 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5334 }; 5335 5336 rpmhpd_opp_nom: opp6 { 5337 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5338 }; 5339 5340 rpmhpd_opp_nom_l1: opp7 { 5341 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5342 }; 5343 5344 rpmhpd_opp_turbo: opp8 { 5345 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5346 }; 5347 5348 rpmhpd_opp_turbo_l1: opp9 { 5349 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5350 }; 5351 }; 5352 }; 5353 5354 rpmhcc: clock-controller { 5355 compatible = "qcom,sc7280-rpmh-clk"; 5356 clocks = <&xo_board>; 5357 clock-names = "xo"; 5358 #clock-cells = <1>; 5359 }; 5360 }; 5361 5362 epss_l3: interconnect@18590000 { 5363 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3"; 5364 reg = <0 0x18590000 0 0x1000>; 5365 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5366 clock-names = "xo", "alternate"; 5367 #interconnect-cells = <1>; 5368 }; 5369 5370 cpufreq_hw: cpufreq@18591000 { 5371 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss"; 5372 reg = <0 0x18591000 0 0x1000>, 5373 <0 0x18592000 0 0x1000>, 5374 <0 0x18593000 0 0x1000>; 5375 5376 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 5377 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5378 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 5379 interrupt-names = "dcvsh-irq-0", 5380 "dcvsh-irq-1", 5381 "dcvsh-irq-2"; 5382 5383 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5384 clock-names = "xo", "alternate"; 5385 #freq-domain-cells = <1>; 5386 #clock-cells = <1>; 5387 }; 5388 }; 5389 5390 thermal_zones: thermal-zones { 5391 cpu0-thermal { 5392 polling-delay-passive = <250>; 5393 polling-delay = <0>; 5394 5395 thermal-sensors = <&tsens0 1>; 5396 5397 trips { 5398 cpu0_alert0: trip-point0 { 5399 temperature = <90000>; 5400 hysteresis = <2000>; 5401 type = "passive"; 5402 }; 5403 5404 cpu0_alert1: trip-point1 { 5405 temperature = <95000>; 5406 hysteresis = <2000>; 5407 type = "passive"; 5408 }; 5409 5410 cpu0_crit: cpu-crit { 5411 temperature = <110000>; 5412 hysteresis = <0>; 5413 type = "critical"; 5414 }; 5415 }; 5416 5417 cooling-maps { 5418 map0 { 5419 trip = <&cpu0_alert0>; 5420 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5421 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5422 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5423 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5424 }; 5425 map1 { 5426 trip = <&cpu0_alert1>; 5427 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5428 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5429 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5430 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5431 }; 5432 }; 5433 }; 5434 5435 cpu1-thermal { 5436 polling-delay-passive = <250>; 5437 polling-delay = <0>; 5438 5439 thermal-sensors = <&tsens0 2>; 5440 5441 trips { 5442 cpu1_alert0: trip-point0 { 5443 temperature = <90000>; 5444 hysteresis = <2000>; 5445 type = "passive"; 5446 }; 5447 5448 cpu1_alert1: trip-point1 { 5449 temperature = <95000>; 5450 hysteresis = <2000>; 5451 type = "passive"; 5452 }; 5453 5454 cpu1_crit: cpu-crit { 5455 temperature = <110000>; 5456 hysteresis = <0>; 5457 type = "critical"; 5458 }; 5459 }; 5460 5461 cooling-maps { 5462 map0 { 5463 trip = <&cpu1_alert0>; 5464 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5465 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5466 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5467 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5468 }; 5469 map1 { 5470 trip = <&cpu1_alert1>; 5471 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5472 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5473 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5474 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5475 }; 5476 }; 5477 }; 5478 5479 cpu2-thermal { 5480 polling-delay-passive = <250>; 5481 polling-delay = <0>; 5482 5483 thermal-sensors = <&tsens0 3>; 5484 5485 trips { 5486 cpu2_alert0: trip-point0 { 5487 temperature = <90000>; 5488 hysteresis = <2000>; 5489 type = "passive"; 5490 }; 5491 5492 cpu2_alert1: trip-point1 { 5493 temperature = <95000>; 5494 hysteresis = <2000>; 5495 type = "passive"; 5496 }; 5497 5498 cpu2_crit: cpu-crit { 5499 temperature = <110000>; 5500 hysteresis = <0>; 5501 type = "critical"; 5502 }; 5503 }; 5504 5505 cooling-maps { 5506 map0 { 5507 trip = <&cpu2_alert0>; 5508 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5509 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5510 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5511 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5512 }; 5513 map1 { 5514 trip = <&cpu2_alert1>; 5515 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5516 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5517 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5518 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5519 }; 5520 }; 5521 }; 5522 5523 cpu3-thermal { 5524 polling-delay-passive = <250>; 5525 polling-delay = <0>; 5526 5527 thermal-sensors = <&tsens0 4>; 5528 5529 trips { 5530 cpu3_alert0: trip-point0 { 5531 temperature = <90000>; 5532 hysteresis = <2000>; 5533 type = "passive"; 5534 }; 5535 5536 cpu3_alert1: trip-point1 { 5537 temperature = <95000>; 5538 hysteresis = <2000>; 5539 type = "passive"; 5540 }; 5541 5542 cpu3_crit: cpu-crit { 5543 temperature = <110000>; 5544 hysteresis = <0>; 5545 type = "critical"; 5546 }; 5547 }; 5548 5549 cooling-maps { 5550 map0 { 5551 trip = <&cpu3_alert0>; 5552 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5553 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5554 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5555 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5556 }; 5557 map1 { 5558 trip = <&cpu3_alert1>; 5559 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5560 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5561 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5562 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5563 }; 5564 }; 5565 }; 5566 5567 cpu4-thermal { 5568 polling-delay-passive = <250>; 5569 polling-delay = <0>; 5570 5571 thermal-sensors = <&tsens0 7>; 5572 5573 trips { 5574 cpu4_alert0: trip-point0 { 5575 temperature = <90000>; 5576 hysteresis = <2000>; 5577 type = "passive"; 5578 }; 5579 5580 cpu4_alert1: trip-point1 { 5581 temperature = <95000>; 5582 hysteresis = <2000>; 5583 type = "passive"; 5584 }; 5585 5586 cpu4_crit: cpu-crit { 5587 temperature = <110000>; 5588 hysteresis = <0>; 5589 type = "critical"; 5590 }; 5591 }; 5592 5593 cooling-maps { 5594 map0 { 5595 trip = <&cpu4_alert0>; 5596 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5597 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5598 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5599 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5600 }; 5601 map1 { 5602 trip = <&cpu4_alert1>; 5603 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5604 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5605 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5606 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5607 }; 5608 }; 5609 }; 5610 5611 cpu5-thermal { 5612 polling-delay-passive = <250>; 5613 polling-delay = <0>; 5614 5615 thermal-sensors = <&tsens0 8>; 5616 5617 trips { 5618 cpu5_alert0: trip-point0 { 5619 temperature = <90000>; 5620 hysteresis = <2000>; 5621 type = "passive"; 5622 }; 5623 5624 cpu5_alert1: trip-point1 { 5625 temperature = <95000>; 5626 hysteresis = <2000>; 5627 type = "passive"; 5628 }; 5629 5630 cpu5_crit: cpu-crit { 5631 temperature = <110000>; 5632 hysteresis = <0>; 5633 type = "critical"; 5634 }; 5635 }; 5636 5637 cooling-maps { 5638 map0 { 5639 trip = <&cpu5_alert0>; 5640 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5641 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5642 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5643 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5644 }; 5645 map1 { 5646 trip = <&cpu5_alert1>; 5647 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5648 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5649 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5650 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5651 }; 5652 }; 5653 }; 5654 5655 cpu6-thermal { 5656 polling-delay-passive = <250>; 5657 polling-delay = <0>; 5658 5659 thermal-sensors = <&tsens0 9>; 5660 5661 trips { 5662 cpu6_alert0: trip-point0 { 5663 temperature = <90000>; 5664 hysteresis = <2000>; 5665 type = "passive"; 5666 }; 5667 5668 cpu6_alert1: trip-point1 { 5669 temperature = <95000>; 5670 hysteresis = <2000>; 5671 type = "passive"; 5672 }; 5673 5674 cpu6_crit: cpu-crit { 5675 temperature = <110000>; 5676 hysteresis = <0>; 5677 type = "critical"; 5678 }; 5679 }; 5680 5681 cooling-maps { 5682 map0 { 5683 trip = <&cpu6_alert0>; 5684 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5685 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5686 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5687 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5688 }; 5689 map1 { 5690 trip = <&cpu6_alert1>; 5691 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5692 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5693 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5694 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5695 }; 5696 }; 5697 }; 5698 5699 cpu7-thermal { 5700 polling-delay-passive = <250>; 5701 polling-delay = <0>; 5702 5703 thermal-sensors = <&tsens0 10>; 5704 5705 trips { 5706 cpu7_alert0: trip-point0 { 5707 temperature = <90000>; 5708 hysteresis = <2000>; 5709 type = "passive"; 5710 }; 5711 5712 cpu7_alert1: trip-point1 { 5713 temperature = <95000>; 5714 hysteresis = <2000>; 5715 type = "passive"; 5716 }; 5717 5718 cpu7_crit: cpu-crit { 5719 temperature = <110000>; 5720 hysteresis = <0>; 5721 type = "critical"; 5722 }; 5723 }; 5724 5725 cooling-maps { 5726 map0 { 5727 trip = <&cpu7_alert0>; 5728 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5729 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5730 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5731 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5732 }; 5733 map1 { 5734 trip = <&cpu7_alert1>; 5735 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5736 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5737 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5738 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5739 }; 5740 }; 5741 }; 5742 5743 cpu8-thermal { 5744 polling-delay-passive = <250>; 5745 polling-delay = <0>; 5746 5747 thermal-sensors = <&tsens0 11>; 5748 5749 trips { 5750 cpu8_alert0: trip-point0 { 5751 temperature = <90000>; 5752 hysteresis = <2000>; 5753 type = "passive"; 5754 }; 5755 5756 cpu8_alert1: trip-point1 { 5757 temperature = <95000>; 5758 hysteresis = <2000>; 5759 type = "passive"; 5760 }; 5761 5762 cpu8_crit: cpu-crit { 5763 temperature = <110000>; 5764 hysteresis = <0>; 5765 type = "critical"; 5766 }; 5767 }; 5768 5769 cooling-maps { 5770 map0 { 5771 trip = <&cpu8_alert0>; 5772 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5773 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5774 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5775 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5776 }; 5777 map1 { 5778 trip = <&cpu8_alert1>; 5779 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5780 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5781 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5782 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5783 }; 5784 }; 5785 }; 5786 5787 cpu9-thermal { 5788 polling-delay-passive = <250>; 5789 polling-delay = <0>; 5790 5791 thermal-sensors = <&tsens0 12>; 5792 5793 trips { 5794 cpu9_alert0: trip-point0 { 5795 temperature = <90000>; 5796 hysteresis = <2000>; 5797 type = "passive"; 5798 }; 5799 5800 cpu9_alert1: trip-point1 { 5801 temperature = <95000>; 5802 hysteresis = <2000>; 5803 type = "passive"; 5804 }; 5805 5806 cpu9_crit: cpu-crit { 5807 temperature = <110000>; 5808 hysteresis = <0>; 5809 type = "critical"; 5810 }; 5811 }; 5812 5813 cooling-maps { 5814 map0 { 5815 trip = <&cpu9_alert0>; 5816 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5817 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5818 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5819 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5820 }; 5821 map1 { 5822 trip = <&cpu9_alert1>; 5823 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5824 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5825 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5826 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5827 }; 5828 }; 5829 }; 5830 5831 cpu10-thermal { 5832 polling-delay-passive = <250>; 5833 polling-delay = <0>; 5834 5835 thermal-sensors = <&tsens0 13>; 5836 5837 trips { 5838 cpu10_alert0: trip-point0 { 5839 temperature = <90000>; 5840 hysteresis = <2000>; 5841 type = "passive"; 5842 }; 5843 5844 cpu10_alert1: trip-point1 { 5845 temperature = <95000>; 5846 hysteresis = <2000>; 5847 type = "passive"; 5848 }; 5849 5850 cpu10_crit: cpu-crit { 5851 temperature = <110000>; 5852 hysteresis = <0>; 5853 type = "critical"; 5854 }; 5855 }; 5856 5857 cooling-maps { 5858 map0 { 5859 trip = <&cpu10_alert0>; 5860 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5861 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5862 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5863 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5864 }; 5865 map1 { 5866 trip = <&cpu10_alert1>; 5867 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5868 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5869 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5870 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5871 }; 5872 }; 5873 }; 5874 5875 cpu11-thermal { 5876 polling-delay-passive = <250>; 5877 polling-delay = <0>; 5878 5879 thermal-sensors = <&tsens0 14>; 5880 5881 trips { 5882 cpu11_alert0: trip-point0 { 5883 temperature = <90000>; 5884 hysteresis = <2000>; 5885 type = "passive"; 5886 }; 5887 5888 cpu11_alert1: trip-point1 { 5889 temperature = <95000>; 5890 hysteresis = <2000>; 5891 type = "passive"; 5892 }; 5893 5894 cpu11_crit: cpu-crit { 5895 temperature = <110000>; 5896 hysteresis = <0>; 5897 type = "critical"; 5898 }; 5899 }; 5900 5901 cooling-maps { 5902 map0 { 5903 trip = <&cpu11_alert0>; 5904 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5905 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5906 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5907 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5908 }; 5909 map1 { 5910 trip = <&cpu11_alert1>; 5911 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5912 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5913 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 5914 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5915 }; 5916 }; 5917 }; 5918 5919 aoss0-thermal { 5920 polling-delay-passive = <0>; 5921 polling-delay = <0>; 5922 5923 thermal-sensors = <&tsens0 0>; 5924 5925 trips { 5926 aoss0_alert0: trip-point0 { 5927 temperature = <90000>; 5928 hysteresis = <2000>; 5929 type = "hot"; 5930 }; 5931 5932 aoss0_crit: aoss0-crit { 5933 temperature = <110000>; 5934 hysteresis = <0>; 5935 type = "critical"; 5936 }; 5937 }; 5938 }; 5939 5940 aoss1-thermal { 5941 polling-delay-passive = <0>; 5942 polling-delay = <0>; 5943 5944 thermal-sensors = <&tsens1 0>; 5945 5946 trips { 5947 aoss1_alert0: trip-point0 { 5948 temperature = <90000>; 5949 hysteresis = <2000>; 5950 type = "hot"; 5951 }; 5952 5953 aoss1_crit: aoss1-crit { 5954 temperature = <110000>; 5955 hysteresis = <0>; 5956 type = "critical"; 5957 }; 5958 }; 5959 }; 5960 5961 cpuss0-thermal { 5962 polling-delay-passive = <0>; 5963 polling-delay = <0>; 5964 5965 thermal-sensors = <&tsens0 5>; 5966 5967 trips { 5968 cpuss0_alert0: trip-point0 { 5969 temperature = <90000>; 5970 hysteresis = <2000>; 5971 type = "hot"; 5972 }; 5973 cpuss0_crit: cluster0-crit { 5974 temperature = <110000>; 5975 hysteresis = <0>; 5976 type = "critical"; 5977 }; 5978 }; 5979 }; 5980 5981 cpuss1-thermal { 5982 polling-delay-passive = <0>; 5983 polling-delay = <0>; 5984 5985 thermal-sensors = <&tsens0 6>; 5986 5987 trips { 5988 cpuss1_alert0: trip-point0 { 5989 temperature = <90000>; 5990 hysteresis = <2000>; 5991 type = "hot"; 5992 }; 5993 cpuss1_crit: cluster0-crit { 5994 temperature = <110000>; 5995 hysteresis = <0>; 5996 type = "critical"; 5997 }; 5998 }; 5999 }; 6000 6001 gpuss0-thermal { 6002 polling-delay-passive = <100>; 6003 polling-delay = <0>; 6004 6005 thermal-sensors = <&tsens1 1>; 6006 6007 trips { 6008 gpuss0_alert0: trip-point0 { 6009 temperature = <95000>; 6010 hysteresis = <2000>; 6011 type = "passive"; 6012 }; 6013 6014 gpuss0_crit: gpuss0-crit { 6015 temperature = <110000>; 6016 hysteresis = <0>; 6017 type = "critical"; 6018 }; 6019 }; 6020 6021 cooling-maps { 6022 map0 { 6023 trip = <&gpuss0_alert0>; 6024 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6025 }; 6026 }; 6027 }; 6028 6029 gpuss1-thermal { 6030 polling-delay-passive = <100>; 6031 polling-delay = <0>; 6032 6033 thermal-sensors = <&tsens1 2>; 6034 6035 trips { 6036 gpuss1_alert0: trip-point0 { 6037 temperature = <95000>; 6038 hysteresis = <2000>; 6039 type = "passive"; 6040 }; 6041 6042 gpuss1_crit: gpuss1-crit { 6043 temperature = <110000>; 6044 hysteresis = <0>; 6045 type = "critical"; 6046 }; 6047 }; 6048 6049 cooling-maps { 6050 map0 { 6051 trip = <&gpuss1_alert0>; 6052 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6053 }; 6054 }; 6055 }; 6056 6057 nspss0-thermal { 6058 polling-delay-passive = <0>; 6059 polling-delay = <0>; 6060 6061 thermal-sensors = <&tsens1 3>; 6062 6063 trips { 6064 nspss0_alert0: trip-point0 { 6065 temperature = <90000>; 6066 hysteresis = <2000>; 6067 type = "hot"; 6068 }; 6069 6070 nspss0_crit: nspss0-crit { 6071 temperature = <110000>; 6072 hysteresis = <0>; 6073 type = "critical"; 6074 }; 6075 }; 6076 }; 6077 6078 nspss1-thermal { 6079 polling-delay-passive = <0>; 6080 polling-delay = <0>; 6081 6082 thermal-sensors = <&tsens1 4>; 6083 6084 trips { 6085 nspss1_alert0: trip-point0 { 6086 temperature = <90000>; 6087 hysteresis = <2000>; 6088 type = "hot"; 6089 }; 6090 6091 nspss1_crit: nspss1-crit { 6092 temperature = <110000>; 6093 hysteresis = <0>; 6094 type = "critical"; 6095 }; 6096 }; 6097 }; 6098 6099 video-thermal { 6100 polling-delay-passive = <0>; 6101 polling-delay = <0>; 6102 6103 thermal-sensors = <&tsens1 5>; 6104 6105 trips { 6106 video_alert0: trip-point0 { 6107 temperature = <90000>; 6108 hysteresis = <2000>; 6109 type = "hot"; 6110 }; 6111 6112 video_crit: video-crit { 6113 temperature = <110000>; 6114 hysteresis = <0>; 6115 type = "critical"; 6116 }; 6117 }; 6118 }; 6119 6120 ddr-thermal { 6121 polling-delay-passive = <0>; 6122 polling-delay = <0>; 6123 6124 thermal-sensors = <&tsens1 6>; 6125 6126 trips { 6127 ddr_alert0: trip-point0 { 6128 temperature = <90000>; 6129 hysteresis = <2000>; 6130 type = "hot"; 6131 }; 6132 6133 ddr_crit: ddr-crit { 6134 temperature = <110000>; 6135 hysteresis = <0>; 6136 type = "critical"; 6137 }; 6138 }; 6139 }; 6140 6141 mdmss0-thermal { 6142 polling-delay-passive = <0>; 6143 polling-delay = <0>; 6144 6145 thermal-sensors = <&tsens1 7>; 6146 6147 trips { 6148 mdmss0_alert0: trip-point0 { 6149 temperature = <90000>; 6150 hysteresis = <2000>; 6151 type = "hot"; 6152 }; 6153 6154 mdmss0_crit: mdmss0-crit { 6155 temperature = <110000>; 6156 hysteresis = <0>; 6157 type = "critical"; 6158 }; 6159 }; 6160 }; 6161 6162 mdmss1-thermal { 6163 polling-delay-passive = <0>; 6164 polling-delay = <0>; 6165 6166 thermal-sensors = <&tsens1 8>; 6167 6168 trips { 6169 mdmss1_alert0: trip-point0 { 6170 temperature = <90000>; 6171 hysteresis = <2000>; 6172 type = "hot"; 6173 }; 6174 6175 mdmss1_crit: mdmss1-crit { 6176 temperature = <110000>; 6177 hysteresis = <0>; 6178 type = "critical"; 6179 }; 6180 }; 6181 }; 6182 6183 mdmss2-thermal { 6184 polling-delay-passive = <0>; 6185 polling-delay = <0>; 6186 6187 thermal-sensors = <&tsens1 9>; 6188 6189 trips { 6190 mdmss2_alert0: trip-point0 { 6191 temperature = <90000>; 6192 hysteresis = <2000>; 6193 type = "hot"; 6194 }; 6195 6196 mdmss2_crit: mdmss2-crit { 6197 temperature = <110000>; 6198 hysteresis = <0>; 6199 type = "critical"; 6200 }; 6201 }; 6202 }; 6203 6204 mdmss3-thermal { 6205 polling-delay-passive = <0>; 6206 polling-delay = <0>; 6207 6208 thermal-sensors = <&tsens1 10>; 6209 6210 trips { 6211 mdmss3_alert0: trip-point0 { 6212 temperature = <90000>; 6213 hysteresis = <2000>; 6214 type = "hot"; 6215 }; 6216 6217 mdmss3_crit: mdmss3-crit { 6218 temperature = <110000>; 6219 hysteresis = <0>; 6220 type = "critical"; 6221 }; 6222 }; 6223 }; 6224 6225 camera0-thermal { 6226 polling-delay-passive = <0>; 6227 polling-delay = <0>; 6228 6229 thermal-sensors = <&tsens1 11>; 6230 6231 trips { 6232 camera0_alert0: trip-point0 { 6233 temperature = <90000>; 6234 hysteresis = <2000>; 6235 type = "hot"; 6236 }; 6237 6238 camera0_crit: camera0-crit { 6239 temperature = <110000>; 6240 hysteresis = <0>; 6241 type = "critical"; 6242 }; 6243 }; 6244 }; 6245 }; 6246 6247 timer { 6248 compatible = "arm,armv8-timer"; 6249 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6250 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6251 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6252 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6253 }; 6254}; 6255