1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/firmware/qcom,scm.h> 17#include <dt-bindings/gpio/gpio.h> 18#include <dt-bindings/interconnect/qcom,icc.h> 19#include <dt-bindings/interconnect/qcom,osm-l3.h> 20#include <dt-bindings/interconnect/qcom,sc7280.h> 21#include <dt-bindings/interrupt-controller/arm-gic.h> 22#include <dt-bindings/mailbox/qcom-ipcc.h> 23#include <dt-bindings/phy/phy-qcom-qmp.h> 24#include <dt-bindings/power/qcom-rpmpd.h> 25#include <dt-bindings/reset/qcom,sdm845-aoss.h> 26#include <dt-bindings/reset/qcom,sdm845-pdc.h> 27#include <dt-bindings/soc/qcom,rpmh-rsc.h> 28#include <dt-bindings/sound/qcom,lpass.h> 29#include <dt-bindings/thermal/thermal.h> 30 31/ { 32 interrupt-parent = <&intc>; 33 34 #address-cells = <2>; 35 #size-cells = <2>; 36 37 chosen { }; 38 39 aliases { 40 i2c0 = &i2c0; 41 i2c1 = &i2c1; 42 i2c2 = &i2c2; 43 i2c3 = &i2c3; 44 i2c4 = &i2c4; 45 i2c5 = &i2c5; 46 i2c6 = &i2c6; 47 i2c7 = &i2c7; 48 i2c8 = &i2c8; 49 i2c9 = &i2c9; 50 i2c10 = &i2c10; 51 i2c11 = &i2c11; 52 i2c12 = &i2c12; 53 i2c13 = &i2c13; 54 i2c14 = &i2c14; 55 i2c15 = &i2c15; 56 mmc1 = &sdhc_1; 57 mmc2 = &sdhc_2; 58 spi0 = &spi0; 59 spi1 = &spi1; 60 spi2 = &spi2; 61 spi3 = &spi3; 62 spi4 = &spi4; 63 spi5 = &spi5; 64 spi6 = &spi6; 65 spi7 = &spi7; 66 spi8 = &spi8; 67 spi9 = &spi9; 68 spi10 = &spi10; 69 spi11 = &spi11; 70 spi12 = &spi12; 71 spi13 = &spi13; 72 spi14 = &spi14; 73 spi15 = &spi15; 74 }; 75 76 clocks { 77 xo_board: xo-board { 78 compatible = "fixed-clock"; 79 clock-frequency = <76800000>; 80 #clock-cells = <0>; 81 }; 82 83 sleep_clk: sleep-clk { 84 compatible = "fixed-clock"; 85 clock-frequency = <32000>; 86 #clock-cells = <0>; 87 }; 88 }; 89 90 reserved-memory { 91 #address-cells = <2>; 92 #size-cells = <2>; 93 ranges; 94 95 wlan_ce_mem: wlan-ce@4cd000 { 96 no-map; 97 reg = <0x0 0x004cd000 0x0 0x1000>; 98 }; 99 100 hyp_mem: hyp@80000000 { 101 reg = <0x0 0x80000000 0x0 0x600000>; 102 no-map; 103 }; 104 105 xbl_mem: xbl@80600000 { 106 reg = <0x0 0x80600000 0x0 0x200000>; 107 no-map; 108 }; 109 110 aop_mem: aop@80800000 { 111 reg = <0x0 0x80800000 0x0 0x60000>; 112 no-map; 113 }; 114 115 aop_cmd_db_mem: aop-cmd-db@80860000 { 116 reg = <0x0 0x80860000 0x0 0x20000>; 117 compatible = "qcom,cmd-db"; 118 no-map; 119 }; 120 121 reserved_xbl_uefi_log: xbl-uefi-res@80880000 { 122 reg = <0x0 0x80884000 0x0 0x10000>; 123 no-map; 124 }; 125 126 sec_apps_mem: sec-apps@808ff000 { 127 reg = <0x0 0x808ff000 0x0 0x1000>; 128 no-map; 129 }; 130 131 smem_mem: smem@80900000 { 132 reg = <0x0 0x80900000 0x0 0x200000>; 133 no-map; 134 }; 135 136 cpucp_mem: cpucp@80b00000 { 137 no-map; 138 reg = <0x0 0x80b00000 0x0 0x100000>; 139 }; 140 141 wlan_fw_mem: wlan-fw@80c00000 { 142 reg = <0x0 0x80c00000 0x0 0xc00000>; 143 no-map; 144 }; 145 146 adsp_mem: adsp@86700000 { 147 reg = <0x0 0x86700000 0x0 0x2800000>; 148 no-map; 149 }; 150 151 video_mem: video@8b200000 { 152 reg = <0x0 0x8b200000 0x0 0x500000>; 153 no-map; 154 }; 155 156 cdsp_mem: cdsp@88f00000 { 157 reg = <0x0 0x88f00000 0x0 0x1e00000>; 158 no-map; 159 }; 160 161 ipa_fw_mem: ipa-fw@8b700000 { 162 reg = <0 0x8b700000 0 0x10000>; 163 no-map; 164 }; 165 166 gpu_zap_mem: zap@8b71a000 { 167 reg = <0 0x8b71a000 0 0x2000>; 168 no-map; 169 }; 170 171 mpss_mem: mpss@8b800000 { 172 reg = <0x0 0x8b800000 0x0 0xf600000>; 173 no-map; 174 }; 175 176 wpss_mem: wpss@9ae00000 { 177 reg = <0x0 0x9ae00000 0x0 0x1900000>; 178 no-map; 179 }; 180 181 rmtfs_mem: rmtfs@9c900000 { 182 compatible = "qcom,rmtfs-mem"; 183 reg = <0x0 0x9c900000 0x0 0x280000>; 184 no-map; 185 186 qcom,client-id = <1>; 187 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 188 }; 189 }; 190 191 cpus { 192 #address-cells = <2>; 193 #size-cells = <0>; 194 195 CPU0: cpu@0 { 196 device_type = "cpu"; 197 compatible = "qcom,kryo"; 198 reg = <0x0 0x0>; 199 clocks = <&cpufreq_hw 0>; 200 enable-method = "psci"; 201 power-domains = <&CPU_PD0>; 202 power-domain-names = "psci"; 203 next-level-cache = <&L2_0>; 204 operating-points-v2 = <&cpu0_opp_table>; 205 capacity-dmips-mhz = <1024>; 206 dynamic-power-coefficient = <100>; 207 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 208 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 209 qcom,freq-domain = <&cpufreq_hw 0>; 210 #cooling-cells = <2>; 211 L2_0: l2-cache { 212 compatible = "cache"; 213 cache-level = <2>; 214 cache-unified; 215 next-level-cache = <&L3_0>; 216 L3_0: l3-cache { 217 compatible = "cache"; 218 cache-level = <3>; 219 cache-unified; 220 }; 221 }; 222 }; 223 224 CPU1: cpu@100 { 225 device_type = "cpu"; 226 compatible = "qcom,kryo"; 227 reg = <0x0 0x100>; 228 clocks = <&cpufreq_hw 0>; 229 enable-method = "psci"; 230 power-domains = <&CPU_PD1>; 231 power-domain-names = "psci"; 232 next-level-cache = <&L2_100>; 233 operating-points-v2 = <&cpu0_opp_table>; 234 capacity-dmips-mhz = <1024>; 235 dynamic-power-coefficient = <100>; 236 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 237 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 238 qcom,freq-domain = <&cpufreq_hw 0>; 239 #cooling-cells = <2>; 240 L2_100: l2-cache { 241 compatible = "cache"; 242 cache-level = <2>; 243 cache-unified; 244 next-level-cache = <&L3_0>; 245 }; 246 }; 247 248 CPU2: cpu@200 { 249 device_type = "cpu"; 250 compatible = "qcom,kryo"; 251 reg = <0x0 0x200>; 252 clocks = <&cpufreq_hw 0>; 253 enable-method = "psci"; 254 power-domains = <&CPU_PD2>; 255 power-domain-names = "psci"; 256 next-level-cache = <&L2_200>; 257 operating-points-v2 = <&cpu0_opp_table>; 258 capacity-dmips-mhz = <1024>; 259 dynamic-power-coefficient = <100>; 260 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 261 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 262 qcom,freq-domain = <&cpufreq_hw 0>; 263 #cooling-cells = <2>; 264 L2_200: l2-cache { 265 compatible = "cache"; 266 cache-level = <2>; 267 cache-unified; 268 next-level-cache = <&L3_0>; 269 }; 270 }; 271 272 CPU3: cpu@300 { 273 device_type = "cpu"; 274 compatible = "qcom,kryo"; 275 reg = <0x0 0x300>; 276 clocks = <&cpufreq_hw 0>; 277 enable-method = "psci"; 278 power-domains = <&CPU_PD3>; 279 power-domain-names = "psci"; 280 next-level-cache = <&L2_300>; 281 operating-points-v2 = <&cpu0_opp_table>; 282 capacity-dmips-mhz = <1024>; 283 dynamic-power-coefficient = <100>; 284 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 285 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 286 qcom,freq-domain = <&cpufreq_hw 0>; 287 #cooling-cells = <2>; 288 L2_300: l2-cache { 289 compatible = "cache"; 290 cache-level = <2>; 291 cache-unified; 292 next-level-cache = <&L3_0>; 293 }; 294 }; 295 296 CPU4: cpu@400 { 297 device_type = "cpu"; 298 compatible = "qcom,kryo"; 299 reg = <0x0 0x400>; 300 clocks = <&cpufreq_hw 1>; 301 enable-method = "psci"; 302 power-domains = <&CPU_PD4>; 303 power-domain-names = "psci"; 304 next-level-cache = <&L2_400>; 305 operating-points-v2 = <&cpu4_opp_table>; 306 capacity-dmips-mhz = <1946>; 307 dynamic-power-coefficient = <520>; 308 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 309 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 310 qcom,freq-domain = <&cpufreq_hw 1>; 311 #cooling-cells = <2>; 312 L2_400: l2-cache { 313 compatible = "cache"; 314 cache-level = <2>; 315 cache-unified; 316 next-level-cache = <&L3_0>; 317 }; 318 }; 319 320 CPU5: cpu@500 { 321 device_type = "cpu"; 322 compatible = "qcom,kryo"; 323 reg = <0x0 0x500>; 324 clocks = <&cpufreq_hw 1>; 325 enable-method = "psci"; 326 power-domains = <&CPU_PD5>; 327 power-domain-names = "psci"; 328 next-level-cache = <&L2_500>; 329 operating-points-v2 = <&cpu4_opp_table>; 330 capacity-dmips-mhz = <1946>; 331 dynamic-power-coefficient = <520>; 332 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 333 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 334 qcom,freq-domain = <&cpufreq_hw 1>; 335 #cooling-cells = <2>; 336 L2_500: l2-cache { 337 compatible = "cache"; 338 cache-level = <2>; 339 cache-unified; 340 next-level-cache = <&L3_0>; 341 }; 342 }; 343 344 CPU6: cpu@600 { 345 device_type = "cpu"; 346 compatible = "qcom,kryo"; 347 reg = <0x0 0x600>; 348 clocks = <&cpufreq_hw 1>; 349 enable-method = "psci"; 350 power-domains = <&CPU_PD6>; 351 power-domain-names = "psci"; 352 next-level-cache = <&L2_600>; 353 operating-points-v2 = <&cpu4_opp_table>; 354 capacity-dmips-mhz = <1946>; 355 dynamic-power-coefficient = <520>; 356 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 357 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 358 qcom,freq-domain = <&cpufreq_hw 1>; 359 #cooling-cells = <2>; 360 L2_600: l2-cache { 361 compatible = "cache"; 362 cache-level = <2>; 363 cache-unified; 364 next-level-cache = <&L3_0>; 365 }; 366 }; 367 368 CPU7: cpu@700 { 369 device_type = "cpu"; 370 compatible = "qcom,kryo"; 371 reg = <0x0 0x700>; 372 clocks = <&cpufreq_hw 2>; 373 enable-method = "psci"; 374 power-domains = <&CPU_PD7>; 375 power-domain-names = "psci"; 376 next-level-cache = <&L2_700>; 377 operating-points-v2 = <&cpu7_opp_table>; 378 capacity-dmips-mhz = <1985>; 379 dynamic-power-coefficient = <552>; 380 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 381 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 382 qcom,freq-domain = <&cpufreq_hw 2>; 383 #cooling-cells = <2>; 384 L2_700: l2-cache { 385 compatible = "cache"; 386 cache-level = <2>; 387 cache-unified; 388 next-level-cache = <&L3_0>; 389 }; 390 }; 391 392 cpu-map { 393 cluster0 { 394 core0 { 395 cpu = <&CPU0>; 396 }; 397 398 core1 { 399 cpu = <&CPU1>; 400 }; 401 402 core2 { 403 cpu = <&CPU2>; 404 }; 405 406 core3 { 407 cpu = <&CPU3>; 408 }; 409 410 core4 { 411 cpu = <&CPU4>; 412 }; 413 414 core5 { 415 cpu = <&CPU5>; 416 }; 417 418 core6 { 419 cpu = <&CPU6>; 420 }; 421 422 core7 { 423 cpu = <&CPU7>; 424 }; 425 }; 426 }; 427 428 idle-states { 429 entry-method = "psci"; 430 431 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 432 compatible = "arm,idle-state"; 433 idle-state-name = "little-power-down"; 434 arm,psci-suspend-param = <0x40000003>; 435 entry-latency-us = <549>; 436 exit-latency-us = <901>; 437 min-residency-us = <1774>; 438 local-timer-stop; 439 }; 440 441 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 442 compatible = "arm,idle-state"; 443 idle-state-name = "little-rail-power-down"; 444 arm,psci-suspend-param = <0x40000004>; 445 entry-latency-us = <702>; 446 exit-latency-us = <915>; 447 min-residency-us = <4001>; 448 local-timer-stop; 449 }; 450 451 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 452 compatible = "arm,idle-state"; 453 idle-state-name = "big-power-down"; 454 arm,psci-suspend-param = <0x40000003>; 455 entry-latency-us = <523>; 456 exit-latency-us = <1244>; 457 min-residency-us = <2207>; 458 local-timer-stop; 459 }; 460 461 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 462 compatible = "arm,idle-state"; 463 idle-state-name = "big-rail-power-down"; 464 arm,psci-suspend-param = <0x40000004>; 465 entry-latency-us = <526>; 466 exit-latency-us = <1854>; 467 min-residency-us = <5555>; 468 local-timer-stop; 469 }; 470 }; 471 472 domain_idle_states: domain-idle-states { 473 CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { 474 compatible = "domain-idle-state"; 475 arm,psci-suspend-param = <0x41000044>; 476 entry-latency-us = <2752>; 477 exit-latency-us = <3048>; 478 min-residency-us = <6118>; 479 }; 480 481 CLUSTER_SLEEP_CX_RET: cluster-sleep-1 { 482 compatible = "domain-idle-state"; 483 arm,psci-suspend-param = <0x41001344>; 484 entry-latency-us = <3263>; 485 exit-latency-us = <4562>; 486 min-residency-us = <8467>; 487 }; 488 489 CLUSTER_SLEEP_LLCC_OFF: cluster-sleep-2 { 490 compatible = "domain-idle-state"; 491 arm,psci-suspend-param = <0x4100b344>; 492 entry-latency-us = <3638>; 493 exit-latency-us = <6562>; 494 min-residency-us = <9826>; 495 }; 496 }; 497 }; 498 499 cpu0_opp_table: opp-table-cpu0 { 500 compatible = "operating-points-v2"; 501 opp-shared; 502 503 cpu0_opp_300mhz: opp-300000000 { 504 opp-hz = /bits/ 64 <300000000>; 505 opp-peak-kBps = <800000 9600000>; 506 }; 507 508 cpu0_opp_691mhz: opp-691200000 { 509 opp-hz = /bits/ 64 <691200000>; 510 opp-peak-kBps = <800000 17817600>; 511 }; 512 513 cpu0_opp_806mhz: opp-806400000 { 514 opp-hz = /bits/ 64 <806400000>; 515 opp-peak-kBps = <800000 20889600>; 516 }; 517 518 cpu0_opp_941mhz: opp-940800000 { 519 opp-hz = /bits/ 64 <940800000>; 520 opp-peak-kBps = <1804000 24576000>; 521 }; 522 523 cpu0_opp_1152mhz: opp-1152000000 { 524 opp-hz = /bits/ 64 <1152000000>; 525 opp-peak-kBps = <2188000 27033600>; 526 }; 527 528 cpu0_opp_1325mhz: opp-1324800000 { 529 opp-hz = /bits/ 64 <1324800000>; 530 opp-peak-kBps = <2188000 33792000>; 531 }; 532 533 cpu0_opp_1517mhz: opp-1516800000 { 534 opp-hz = /bits/ 64 <1516800000>; 535 opp-peak-kBps = <3072000 38092800>; 536 }; 537 538 cpu0_opp_1651mhz: opp-1651200000 { 539 opp-hz = /bits/ 64 <1651200000>; 540 opp-peak-kBps = <3072000 41779200>; 541 }; 542 543 cpu0_opp_1805mhz: opp-1804800000 { 544 opp-hz = /bits/ 64 <1804800000>; 545 opp-peak-kBps = <4068000 48537600>; 546 }; 547 548 cpu0_opp_1958mhz: opp-1958400000 { 549 opp-hz = /bits/ 64 <1958400000>; 550 opp-peak-kBps = <4068000 48537600>; 551 }; 552 553 cpu0_opp_2016mhz: opp-2016000000 { 554 opp-hz = /bits/ 64 <2016000000>; 555 opp-peak-kBps = <6220000 48537600>; 556 }; 557 }; 558 559 cpu4_opp_table: opp-table-cpu4 { 560 compatible = "operating-points-v2"; 561 opp-shared; 562 563 cpu4_opp_691mhz: opp-691200000 { 564 opp-hz = /bits/ 64 <691200000>; 565 opp-peak-kBps = <1804000 9600000>; 566 }; 567 568 cpu4_opp_941mhz: opp-940800000 { 569 opp-hz = /bits/ 64 <940800000>; 570 opp-peak-kBps = <2188000 17817600>; 571 }; 572 573 cpu4_opp_1229mhz: opp-1228800000 { 574 opp-hz = /bits/ 64 <1228800000>; 575 opp-peak-kBps = <4068000 24576000>; 576 }; 577 578 cpu4_opp_1344mhz: opp-1344000000 { 579 opp-hz = /bits/ 64 <1344000000>; 580 opp-peak-kBps = <4068000 24576000>; 581 }; 582 583 cpu4_opp_1517mhz: opp-1516800000 { 584 opp-hz = /bits/ 64 <1516800000>; 585 opp-peak-kBps = <4068000 24576000>; 586 }; 587 588 cpu4_opp_1651mhz: opp-1651200000 { 589 opp-hz = /bits/ 64 <1651200000>; 590 opp-peak-kBps = <6220000 38092800>; 591 }; 592 593 cpu4_opp_1901mhz: opp-1900800000 { 594 opp-hz = /bits/ 64 <1900800000>; 595 opp-peak-kBps = <6220000 44851200>; 596 }; 597 598 cpu4_opp_2054mhz: opp-2054400000 { 599 opp-hz = /bits/ 64 <2054400000>; 600 opp-peak-kBps = <6220000 44851200>; 601 }; 602 603 cpu4_opp_2112mhz: opp-2112000000 { 604 opp-hz = /bits/ 64 <2112000000>; 605 opp-peak-kBps = <6220000 44851200>; 606 }; 607 608 cpu4_opp_2131mhz: opp-2131200000 { 609 opp-hz = /bits/ 64 <2131200000>; 610 opp-peak-kBps = <6220000 44851200>; 611 }; 612 613 cpu4_opp_2208mhz: opp-2208000000 { 614 opp-hz = /bits/ 64 <2208000000>; 615 opp-peak-kBps = <6220000 44851200>; 616 }; 617 618 cpu4_opp_2400mhz: opp-2400000000 { 619 opp-hz = /bits/ 64 <2400000000>; 620 opp-peak-kBps = <8532000 48537600>; 621 }; 622 623 cpu4_opp_2611mhz: opp-2611200000 { 624 opp-hz = /bits/ 64 <2611200000>; 625 opp-peak-kBps = <8532000 48537600>; 626 }; 627 }; 628 629 cpu7_opp_table: opp-table-cpu7 { 630 compatible = "operating-points-v2"; 631 opp-shared; 632 633 cpu7_opp_806mhz: opp-806400000 { 634 opp-hz = /bits/ 64 <806400000>; 635 opp-peak-kBps = <1804000 9600000>; 636 }; 637 638 cpu7_opp_1056mhz: opp-1056000000 { 639 opp-hz = /bits/ 64 <1056000000>; 640 opp-peak-kBps = <2188000 17817600>; 641 }; 642 643 cpu7_opp_1325mhz: opp-1324800000 { 644 opp-hz = /bits/ 64 <1324800000>; 645 opp-peak-kBps = <4068000 24576000>; 646 }; 647 648 cpu7_opp_1517mhz: opp-1516800000 { 649 opp-hz = /bits/ 64 <1516800000>; 650 opp-peak-kBps = <4068000 24576000>; 651 }; 652 653 cpu7_opp_1766mhz: opp-1766400000 { 654 opp-hz = /bits/ 64 <1766400000>; 655 opp-peak-kBps = <6220000 38092800>; 656 }; 657 658 cpu7_opp_1862mhz: opp-1862400000 { 659 opp-hz = /bits/ 64 <1862400000>; 660 opp-peak-kBps = <6220000 38092800>; 661 }; 662 663 cpu7_opp_2035mhz: opp-2035200000 { 664 opp-hz = /bits/ 64 <2035200000>; 665 opp-peak-kBps = <6220000 38092800>; 666 }; 667 668 cpu7_opp_2112mhz: opp-2112000000 { 669 opp-hz = /bits/ 64 <2112000000>; 670 opp-peak-kBps = <6220000 44851200>; 671 }; 672 673 cpu7_opp_2208mhz: opp-2208000000 { 674 opp-hz = /bits/ 64 <2208000000>; 675 opp-peak-kBps = <6220000 44851200>; 676 }; 677 678 cpu7_opp_2381mhz: opp-2380800000 { 679 opp-hz = /bits/ 64 <2380800000>; 680 opp-peak-kBps = <6832000 44851200>; 681 }; 682 683 cpu7_opp_2400mhz: opp-2400000000 { 684 opp-hz = /bits/ 64 <2400000000>; 685 opp-peak-kBps = <8532000 48537600>; 686 }; 687 688 cpu7_opp_2515mhz: opp-2515200000 { 689 opp-hz = /bits/ 64 <2515200000>; 690 opp-peak-kBps = <8532000 48537600>; 691 }; 692 693 cpu7_opp_2707mhz: opp-2707200000 { 694 opp-hz = /bits/ 64 <2707200000>; 695 opp-peak-kBps = <8532000 48537600>; 696 }; 697 698 cpu7_opp_3014mhz: opp-3014400000 { 699 opp-hz = /bits/ 64 <3014400000>; 700 opp-peak-kBps = <8532000 48537600>; 701 }; 702 }; 703 704 memory@80000000 { 705 device_type = "memory"; 706 /* We expect the bootloader to fill in the size */ 707 reg = <0 0x80000000 0 0>; 708 }; 709 710 firmware { 711 scm: scm { 712 compatible = "qcom,scm-sc7280", "qcom,scm"; 713 }; 714 }; 715 716 clk_virt: interconnect { 717 compatible = "qcom,sc7280-clk-virt"; 718 #interconnect-cells = <2>; 719 qcom,bcm-voters = <&apps_bcm_voter>; 720 }; 721 722 smem { 723 compatible = "qcom,smem"; 724 memory-region = <&smem_mem>; 725 hwlocks = <&tcsr_mutex 3>; 726 }; 727 728 smp2p-adsp { 729 compatible = "qcom,smp2p"; 730 qcom,smem = <443>, <429>; 731 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 732 IPCC_MPROC_SIGNAL_SMP2P 733 IRQ_TYPE_EDGE_RISING>; 734 mboxes = <&ipcc IPCC_CLIENT_LPASS 735 IPCC_MPROC_SIGNAL_SMP2P>; 736 737 qcom,local-pid = <0>; 738 qcom,remote-pid = <2>; 739 740 adsp_smp2p_out: master-kernel { 741 qcom,entry-name = "master-kernel"; 742 #qcom,smem-state-cells = <1>; 743 }; 744 745 adsp_smp2p_in: slave-kernel { 746 qcom,entry-name = "slave-kernel"; 747 interrupt-controller; 748 #interrupt-cells = <2>; 749 }; 750 }; 751 752 smp2p-cdsp { 753 compatible = "qcom,smp2p"; 754 qcom,smem = <94>, <432>; 755 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 756 IPCC_MPROC_SIGNAL_SMP2P 757 IRQ_TYPE_EDGE_RISING>; 758 mboxes = <&ipcc IPCC_CLIENT_CDSP 759 IPCC_MPROC_SIGNAL_SMP2P>; 760 761 qcom,local-pid = <0>; 762 qcom,remote-pid = <5>; 763 764 cdsp_smp2p_out: master-kernel { 765 qcom,entry-name = "master-kernel"; 766 #qcom,smem-state-cells = <1>; 767 }; 768 769 cdsp_smp2p_in: slave-kernel { 770 qcom,entry-name = "slave-kernel"; 771 interrupt-controller; 772 #interrupt-cells = <2>; 773 }; 774 }; 775 776 smp2p-mpss { 777 compatible = "qcom,smp2p"; 778 qcom,smem = <435>, <428>; 779 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 780 IPCC_MPROC_SIGNAL_SMP2P 781 IRQ_TYPE_EDGE_RISING>; 782 mboxes = <&ipcc IPCC_CLIENT_MPSS 783 IPCC_MPROC_SIGNAL_SMP2P>; 784 785 qcom,local-pid = <0>; 786 qcom,remote-pid = <1>; 787 788 modem_smp2p_out: master-kernel { 789 qcom,entry-name = "master-kernel"; 790 #qcom,smem-state-cells = <1>; 791 }; 792 793 modem_smp2p_in: slave-kernel { 794 qcom,entry-name = "slave-kernel"; 795 interrupt-controller; 796 #interrupt-cells = <2>; 797 }; 798 799 ipa_smp2p_out: ipa-ap-to-modem { 800 qcom,entry-name = "ipa"; 801 #qcom,smem-state-cells = <1>; 802 }; 803 804 ipa_smp2p_in: ipa-modem-to-ap { 805 qcom,entry-name = "ipa"; 806 interrupt-controller; 807 #interrupt-cells = <2>; 808 }; 809 }; 810 811 smp2p-wpss { 812 compatible = "qcom,smp2p"; 813 qcom,smem = <617>, <616>; 814 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 815 IPCC_MPROC_SIGNAL_SMP2P 816 IRQ_TYPE_EDGE_RISING>; 817 mboxes = <&ipcc IPCC_CLIENT_WPSS 818 IPCC_MPROC_SIGNAL_SMP2P>; 819 820 qcom,local-pid = <0>; 821 qcom,remote-pid = <13>; 822 823 wpss_smp2p_out: master-kernel { 824 qcom,entry-name = "master-kernel"; 825 #qcom,smem-state-cells = <1>; 826 }; 827 828 wpss_smp2p_in: slave-kernel { 829 qcom,entry-name = "slave-kernel"; 830 interrupt-controller; 831 #interrupt-cells = <2>; 832 }; 833 834 wlan_smp2p_out: wlan-ap-to-wpss { 835 qcom,entry-name = "wlan"; 836 #qcom,smem-state-cells = <1>; 837 }; 838 839 wlan_smp2p_in: wlan-wpss-to-ap { 840 qcom,entry-name = "wlan"; 841 interrupt-controller; 842 #interrupt-cells = <2>; 843 }; 844 }; 845 846 pmu { 847 compatible = "arm,armv8-pmuv3"; 848 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 849 }; 850 851 psci { 852 compatible = "arm,psci-1.0"; 853 method = "smc"; 854 855 CPU_PD0: power-domain-cpu0 { 856 #power-domain-cells = <0>; 857 power-domains = <&CLUSTER_PD>; 858 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 859 }; 860 861 CPU_PD1: power-domain-cpu1 { 862 #power-domain-cells = <0>; 863 power-domains = <&CLUSTER_PD>; 864 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 865 }; 866 867 CPU_PD2: power-domain-cpu2 { 868 #power-domain-cells = <0>; 869 power-domains = <&CLUSTER_PD>; 870 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 871 }; 872 873 CPU_PD3: power-domain-cpu3 { 874 #power-domain-cells = <0>; 875 power-domains = <&CLUSTER_PD>; 876 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 877 }; 878 879 CPU_PD4: power-domain-cpu4 { 880 #power-domain-cells = <0>; 881 power-domains = <&CLUSTER_PD>; 882 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 883 }; 884 885 CPU_PD5: power-domain-cpu5 { 886 #power-domain-cells = <0>; 887 power-domains = <&CLUSTER_PD>; 888 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 889 }; 890 891 CPU_PD6: power-domain-cpu6 { 892 #power-domain-cells = <0>; 893 power-domains = <&CLUSTER_PD>; 894 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 895 }; 896 897 CPU_PD7: power-domain-cpu7 { 898 #power-domain-cells = <0>; 899 power-domains = <&CLUSTER_PD>; 900 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 901 }; 902 903 CLUSTER_PD: power-domain-cluster { 904 #power-domain-cells = <0>; 905 domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_CX_RET &CLUSTER_SLEEP_LLCC_OFF>; 906 }; 907 }; 908 909 qspi_opp_table: opp-table-qspi { 910 compatible = "operating-points-v2"; 911 912 opp-75000000 { 913 opp-hz = /bits/ 64 <75000000>; 914 required-opps = <&rpmhpd_opp_low_svs>; 915 }; 916 917 opp-150000000 { 918 opp-hz = /bits/ 64 <150000000>; 919 required-opps = <&rpmhpd_opp_svs>; 920 }; 921 922 opp-200000000 { 923 opp-hz = /bits/ 64 <200000000>; 924 required-opps = <&rpmhpd_opp_svs_l1>; 925 }; 926 927 opp-300000000 { 928 opp-hz = /bits/ 64 <300000000>; 929 required-opps = <&rpmhpd_opp_nom>; 930 }; 931 }; 932 933 qup_opp_table: opp-table-qup { 934 compatible = "operating-points-v2"; 935 936 opp-75000000 { 937 opp-hz = /bits/ 64 <75000000>; 938 required-opps = <&rpmhpd_opp_low_svs>; 939 }; 940 941 opp-100000000 { 942 opp-hz = /bits/ 64 <100000000>; 943 required-opps = <&rpmhpd_opp_svs>; 944 }; 945 946 opp-128000000 { 947 opp-hz = /bits/ 64 <128000000>; 948 required-opps = <&rpmhpd_opp_nom>; 949 }; 950 }; 951 952 soc: soc@0 { 953 #address-cells = <2>; 954 #size-cells = <2>; 955 ranges = <0 0 0 0 0x10 0>; 956 dma-ranges = <0 0 0 0 0x10 0>; 957 compatible = "simple-bus"; 958 959 gcc: clock-controller@100000 { 960 compatible = "qcom,gcc-sc7280"; 961 reg = <0 0x00100000 0 0x1f0000>; 962 clocks = <&rpmhcc RPMH_CXO_CLK>, 963 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 964 <0>, <&pcie1_phy>, 965 <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, 966 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 967 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 968 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 969 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 970 "ufs_phy_tx_symbol_0_clk", 971 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 972 #clock-cells = <1>; 973 #reset-cells = <1>; 974 #power-domain-cells = <1>; 975 power-domains = <&rpmhpd SC7280_CX>; 976 }; 977 978 ipcc: mailbox@408000 { 979 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 980 reg = <0 0x00408000 0 0x1000>; 981 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 982 interrupt-controller; 983 #interrupt-cells = <3>; 984 #mbox-cells = <2>; 985 }; 986 987 qfprom: efuse@784000 { 988 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 989 reg = <0 0x00784000 0 0xa20>, 990 <0 0x00780000 0 0xa20>, 991 <0 0x00782000 0 0x120>, 992 <0 0x00786000 0 0x1fff>; 993 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 994 clock-names = "core"; 995 power-domains = <&rpmhpd SC7280_MX>; 996 #address-cells = <1>; 997 #size-cells = <1>; 998 999 gpu_speed_bin: gpu-speed-bin@1e9 { 1000 reg = <0x1e9 0x2>; 1001 bits = <5 8>; 1002 }; 1003 }; 1004 1005 sdhc_1: mmc@7c4000 { 1006 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 1007 pinctrl-names = "default", "sleep"; 1008 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 1009 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 1010 status = "disabled"; 1011 1012 reg = <0 0x007c4000 0 0x1000>, 1013 <0 0x007c5000 0 0x1000>; 1014 reg-names = "hc", "cqhci"; 1015 1016 iommus = <&apps_smmu 0xc0 0x0>; 1017 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 1018 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 1019 interrupt-names = "hc_irq", "pwr_irq"; 1020 1021 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1022 <&gcc GCC_SDCC1_APPS_CLK>, 1023 <&rpmhcc RPMH_CXO_CLK>; 1024 clock-names = "iface", "core", "xo"; 1025 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 1026 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 1027 interconnect-names = "sdhc-ddr","cpu-sdhc"; 1028 power-domains = <&rpmhpd SC7280_CX>; 1029 operating-points-v2 = <&sdhc1_opp_table>; 1030 1031 bus-width = <8>; 1032 supports-cqe; 1033 dma-coherent; 1034 1035 qcom,dll-config = <0x0007642c>; 1036 qcom,ddr-config = <0x80040868>; 1037 1038 mmc-ddr-1_8v; 1039 mmc-hs200-1_8v; 1040 mmc-hs400-1_8v; 1041 mmc-hs400-enhanced-strobe; 1042 1043 resets = <&gcc GCC_SDCC1_BCR>; 1044 1045 sdhc1_opp_table: opp-table { 1046 compatible = "operating-points-v2"; 1047 1048 opp-100000000 { 1049 opp-hz = /bits/ 64 <100000000>; 1050 required-opps = <&rpmhpd_opp_low_svs>; 1051 opp-peak-kBps = <1800000 400000>; 1052 opp-avg-kBps = <100000 0>; 1053 }; 1054 1055 opp-384000000 { 1056 opp-hz = /bits/ 64 <384000000>; 1057 required-opps = <&rpmhpd_opp_nom>; 1058 opp-peak-kBps = <5400000 1600000>; 1059 opp-avg-kBps = <390000 0>; 1060 }; 1061 }; 1062 }; 1063 1064 gpi_dma0: dma-controller@900000 { 1065 #dma-cells = <3>; 1066 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1067 reg = <0 0x00900000 0 0x60000>; 1068 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1070 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1071 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1072 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1073 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1074 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1075 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1076 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1077 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1078 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1079 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1080 dma-channels = <12>; 1081 dma-channel-mask = <0x7f>; 1082 iommus = <&apps_smmu 0x0136 0x0>; 1083 status = "disabled"; 1084 }; 1085 1086 qupv3_id_0: geniqup@9c0000 { 1087 compatible = "qcom,geni-se-qup"; 1088 reg = <0 0x009c0000 0 0x2000>; 1089 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1090 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1091 clock-names = "m-ahb", "s-ahb"; 1092 #address-cells = <2>; 1093 #size-cells = <2>; 1094 ranges; 1095 iommus = <&apps_smmu 0x123 0x0>; 1096 status = "disabled"; 1097 1098 i2c0: i2c@980000 { 1099 compatible = "qcom,geni-i2c"; 1100 reg = <0 0x00980000 0 0x4000>; 1101 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1102 clock-names = "se"; 1103 pinctrl-names = "default"; 1104 pinctrl-0 = <&qup_i2c0_data_clk>; 1105 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1106 #address-cells = <1>; 1107 #size-cells = <0>; 1108 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1109 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1110 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1111 interconnect-names = "qup-core", "qup-config", 1112 "qup-memory"; 1113 power-domains = <&rpmhpd SC7280_CX>; 1114 required-opps = <&rpmhpd_opp_low_svs>; 1115 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1116 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1117 dma-names = "tx", "rx"; 1118 status = "disabled"; 1119 }; 1120 1121 spi0: spi@980000 { 1122 compatible = "qcom,geni-spi"; 1123 reg = <0 0x00980000 0 0x4000>; 1124 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1125 clock-names = "se"; 1126 pinctrl-names = "default"; 1127 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1128 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1129 #address-cells = <1>; 1130 #size-cells = <0>; 1131 power-domains = <&rpmhpd SC7280_CX>; 1132 operating-points-v2 = <&qup_opp_table>; 1133 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1134 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1135 interconnect-names = "qup-core", "qup-config"; 1136 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1137 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1138 dma-names = "tx", "rx"; 1139 status = "disabled"; 1140 }; 1141 1142 uart0: serial@980000 { 1143 compatible = "qcom,geni-uart"; 1144 reg = <0 0x00980000 0 0x4000>; 1145 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1146 clock-names = "se"; 1147 pinctrl-names = "default"; 1148 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1149 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1150 power-domains = <&rpmhpd SC7280_CX>; 1151 operating-points-v2 = <&qup_opp_table>; 1152 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1153 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1154 interconnect-names = "qup-core", "qup-config"; 1155 status = "disabled"; 1156 }; 1157 1158 i2c1: i2c@984000 { 1159 compatible = "qcom,geni-i2c"; 1160 reg = <0 0x00984000 0 0x4000>; 1161 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1162 clock-names = "se"; 1163 pinctrl-names = "default"; 1164 pinctrl-0 = <&qup_i2c1_data_clk>; 1165 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1166 #address-cells = <1>; 1167 #size-cells = <0>; 1168 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1169 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1170 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1171 interconnect-names = "qup-core", "qup-config", 1172 "qup-memory"; 1173 power-domains = <&rpmhpd SC7280_CX>; 1174 required-opps = <&rpmhpd_opp_low_svs>; 1175 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1176 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1177 dma-names = "tx", "rx"; 1178 status = "disabled"; 1179 }; 1180 1181 spi1: spi@984000 { 1182 compatible = "qcom,geni-spi"; 1183 reg = <0 0x00984000 0 0x4000>; 1184 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1185 clock-names = "se"; 1186 pinctrl-names = "default"; 1187 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1188 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1189 #address-cells = <1>; 1190 #size-cells = <0>; 1191 power-domains = <&rpmhpd SC7280_CX>; 1192 operating-points-v2 = <&qup_opp_table>; 1193 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1194 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1195 interconnect-names = "qup-core", "qup-config"; 1196 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1197 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1198 dma-names = "tx", "rx"; 1199 status = "disabled"; 1200 }; 1201 1202 uart1: serial@984000 { 1203 compatible = "qcom,geni-uart"; 1204 reg = <0 0x00984000 0 0x4000>; 1205 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1206 clock-names = "se"; 1207 pinctrl-names = "default"; 1208 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1209 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1210 power-domains = <&rpmhpd SC7280_CX>; 1211 operating-points-v2 = <&qup_opp_table>; 1212 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1213 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1214 interconnect-names = "qup-core", "qup-config"; 1215 status = "disabled"; 1216 }; 1217 1218 i2c2: i2c@988000 { 1219 compatible = "qcom,geni-i2c"; 1220 reg = <0 0x00988000 0 0x4000>; 1221 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1222 clock-names = "se"; 1223 pinctrl-names = "default"; 1224 pinctrl-0 = <&qup_i2c2_data_clk>; 1225 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1226 #address-cells = <1>; 1227 #size-cells = <0>; 1228 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1229 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1230 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1231 interconnect-names = "qup-core", "qup-config", 1232 "qup-memory"; 1233 power-domains = <&rpmhpd SC7280_CX>; 1234 required-opps = <&rpmhpd_opp_low_svs>; 1235 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1236 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1237 dma-names = "tx", "rx"; 1238 status = "disabled"; 1239 }; 1240 1241 spi2: spi@988000 { 1242 compatible = "qcom,geni-spi"; 1243 reg = <0 0x00988000 0 0x4000>; 1244 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1245 clock-names = "se"; 1246 pinctrl-names = "default"; 1247 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1248 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1249 #address-cells = <1>; 1250 #size-cells = <0>; 1251 power-domains = <&rpmhpd SC7280_CX>; 1252 operating-points-v2 = <&qup_opp_table>; 1253 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1254 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1255 interconnect-names = "qup-core", "qup-config"; 1256 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1257 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1258 dma-names = "tx", "rx"; 1259 status = "disabled"; 1260 }; 1261 1262 uart2: serial@988000 { 1263 compatible = "qcom,geni-uart"; 1264 reg = <0 0x00988000 0 0x4000>; 1265 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1266 clock-names = "se"; 1267 pinctrl-names = "default"; 1268 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1269 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1270 power-domains = <&rpmhpd SC7280_CX>; 1271 operating-points-v2 = <&qup_opp_table>; 1272 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1273 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1274 interconnect-names = "qup-core", "qup-config"; 1275 status = "disabled"; 1276 }; 1277 1278 i2c3: i2c@98c000 { 1279 compatible = "qcom,geni-i2c"; 1280 reg = <0 0x0098c000 0 0x4000>; 1281 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1282 clock-names = "se"; 1283 pinctrl-names = "default"; 1284 pinctrl-0 = <&qup_i2c3_data_clk>; 1285 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1286 #address-cells = <1>; 1287 #size-cells = <0>; 1288 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1289 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1290 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1291 interconnect-names = "qup-core", "qup-config", 1292 "qup-memory"; 1293 power-domains = <&rpmhpd SC7280_CX>; 1294 required-opps = <&rpmhpd_opp_low_svs>; 1295 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1296 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1297 dma-names = "tx", "rx"; 1298 status = "disabled"; 1299 }; 1300 1301 spi3: spi@98c000 { 1302 compatible = "qcom,geni-spi"; 1303 reg = <0 0x0098c000 0 0x4000>; 1304 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1305 clock-names = "se"; 1306 pinctrl-names = "default"; 1307 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1308 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1309 #address-cells = <1>; 1310 #size-cells = <0>; 1311 power-domains = <&rpmhpd SC7280_CX>; 1312 operating-points-v2 = <&qup_opp_table>; 1313 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1314 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1315 interconnect-names = "qup-core", "qup-config"; 1316 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1317 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1318 dma-names = "tx", "rx"; 1319 status = "disabled"; 1320 }; 1321 1322 uart3: serial@98c000 { 1323 compatible = "qcom,geni-uart"; 1324 reg = <0 0x0098c000 0 0x4000>; 1325 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1326 clock-names = "se"; 1327 pinctrl-names = "default"; 1328 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1329 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1330 power-domains = <&rpmhpd SC7280_CX>; 1331 operating-points-v2 = <&qup_opp_table>; 1332 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1333 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1334 interconnect-names = "qup-core", "qup-config"; 1335 status = "disabled"; 1336 }; 1337 1338 i2c4: i2c@990000 { 1339 compatible = "qcom,geni-i2c"; 1340 reg = <0 0x00990000 0 0x4000>; 1341 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1342 clock-names = "se"; 1343 pinctrl-names = "default"; 1344 pinctrl-0 = <&qup_i2c4_data_clk>; 1345 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1346 #address-cells = <1>; 1347 #size-cells = <0>; 1348 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1349 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1350 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1351 interconnect-names = "qup-core", "qup-config", 1352 "qup-memory"; 1353 power-domains = <&rpmhpd SC7280_CX>; 1354 required-opps = <&rpmhpd_opp_low_svs>; 1355 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1356 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1357 dma-names = "tx", "rx"; 1358 status = "disabled"; 1359 }; 1360 1361 spi4: spi@990000 { 1362 compatible = "qcom,geni-spi"; 1363 reg = <0 0x00990000 0 0x4000>; 1364 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1365 clock-names = "se"; 1366 pinctrl-names = "default"; 1367 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1368 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1369 #address-cells = <1>; 1370 #size-cells = <0>; 1371 power-domains = <&rpmhpd SC7280_CX>; 1372 operating-points-v2 = <&qup_opp_table>; 1373 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1374 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1375 interconnect-names = "qup-core", "qup-config"; 1376 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1377 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1378 dma-names = "tx", "rx"; 1379 status = "disabled"; 1380 }; 1381 1382 uart4: serial@990000 { 1383 compatible = "qcom,geni-uart"; 1384 reg = <0 0x00990000 0 0x4000>; 1385 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1386 clock-names = "se"; 1387 pinctrl-names = "default"; 1388 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1389 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1390 power-domains = <&rpmhpd SC7280_CX>; 1391 operating-points-v2 = <&qup_opp_table>; 1392 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1393 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1394 interconnect-names = "qup-core", "qup-config"; 1395 status = "disabled"; 1396 }; 1397 1398 i2c5: i2c@994000 { 1399 compatible = "qcom,geni-i2c"; 1400 reg = <0 0x00994000 0 0x4000>; 1401 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1402 clock-names = "se"; 1403 pinctrl-names = "default"; 1404 pinctrl-0 = <&qup_i2c5_data_clk>; 1405 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1406 #address-cells = <1>; 1407 #size-cells = <0>; 1408 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1409 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1410 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1411 interconnect-names = "qup-core", "qup-config", 1412 "qup-memory"; 1413 power-domains = <&rpmhpd SC7280_CX>; 1414 required-opps = <&rpmhpd_opp_low_svs>; 1415 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1416 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1417 dma-names = "tx", "rx"; 1418 status = "disabled"; 1419 }; 1420 1421 spi5: spi@994000 { 1422 compatible = "qcom,geni-spi"; 1423 reg = <0 0x00994000 0 0x4000>; 1424 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1425 clock-names = "se"; 1426 pinctrl-names = "default"; 1427 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1428 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1429 #address-cells = <1>; 1430 #size-cells = <0>; 1431 power-domains = <&rpmhpd SC7280_CX>; 1432 operating-points-v2 = <&qup_opp_table>; 1433 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1434 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1435 interconnect-names = "qup-core", "qup-config"; 1436 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1437 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1438 dma-names = "tx", "rx"; 1439 status = "disabled"; 1440 }; 1441 1442 uart5: serial@994000 { 1443 compatible = "qcom,geni-uart"; 1444 reg = <0 0x00994000 0 0x4000>; 1445 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1446 clock-names = "se"; 1447 pinctrl-names = "default"; 1448 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1449 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1450 power-domains = <&rpmhpd SC7280_CX>; 1451 operating-points-v2 = <&qup_opp_table>; 1452 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1453 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1454 interconnect-names = "qup-core", "qup-config"; 1455 status = "disabled"; 1456 }; 1457 1458 i2c6: i2c@998000 { 1459 compatible = "qcom,geni-i2c"; 1460 reg = <0 0x00998000 0 0x4000>; 1461 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1462 clock-names = "se"; 1463 pinctrl-names = "default"; 1464 pinctrl-0 = <&qup_i2c6_data_clk>; 1465 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1466 #address-cells = <1>; 1467 #size-cells = <0>; 1468 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1469 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1470 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1471 interconnect-names = "qup-core", "qup-config", 1472 "qup-memory"; 1473 power-domains = <&rpmhpd SC7280_CX>; 1474 required-opps = <&rpmhpd_opp_low_svs>; 1475 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1476 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1477 dma-names = "tx", "rx"; 1478 status = "disabled"; 1479 }; 1480 1481 spi6: spi@998000 { 1482 compatible = "qcom,geni-spi"; 1483 reg = <0 0x00998000 0 0x4000>; 1484 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1485 clock-names = "se"; 1486 pinctrl-names = "default"; 1487 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1488 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1489 #address-cells = <1>; 1490 #size-cells = <0>; 1491 power-domains = <&rpmhpd SC7280_CX>; 1492 operating-points-v2 = <&qup_opp_table>; 1493 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1494 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1495 interconnect-names = "qup-core", "qup-config"; 1496 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1497 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1498 dma-names = "tx", "rx"; 1499 status = "disabled"; 1500 }; 1501 1502 uart6: serial@998000 { 1503 compatible = "qcom,geni-uart"; 1504 reg = <0 0x00998000 0 0x4000>; 1505 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1506 clock-names = "se"; 1507 pinctrl-names = "default"; 1508 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1509 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1510 power-domains = <&rpmhpd SC7280_CX>; 1511 operating-points-v2 = <&qup_opp_table>; 1512 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1513 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1514 interconnect-names = "qup-core", "qup-config"; 1515 status = "disabled"; 1516 }; 1517 1518 i2c7: i2c@99c000 { 1519 compatible = "qcom,geni-i2c"; 1520 reg = <0 0x0099c000 0 0x4000>; 1521 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1522 clock-names = "se"; 1523 pinctrl-names = "default"; 1524 pinctrl-0 = <&qup_i2c7_data_clk>; 1525 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1526 #address-cells = <1>; 1527 #size-cells = <0>; 1528 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1529 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1530 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1531 interconnect-names = "qup-core", "qup-config", 1532 "qup-memory"; 1533 power-domains = <&rpmhpd SC7280_CX>; 1534 required-opps = <&rpmhpd_opp_low_svs>; 1535 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1536 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1537 dma-names = "tx", "rx"; 1538 status = "disabled"; 1539 }; 1540 1541 spi7: spi@99c000 { 1542 compatible = "qcom,geni-spi"; 1543 reg = <0 0x0099c000 0 0x4000>; 1544 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1545 clock-names = "se"; 1546 pinctrl-names = "default"; 1547 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1548 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1549 #address-cells = <1>; 1550 #size-cells = <0>; 1551 power-domains = <&rpmhpd SC7280_CX>; 1552 operating-points-v2 = <&qup_opp_table>; 1553 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1554 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1555 interconnect-names = "qup-core", "qup-config"; 1556 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1557 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1558 dma-names = "tx", "rx"; 1559 status = "disabled"; 1560 }; 1561 1562 uart7: serial@99c000 { 1563 compatible = "qcom,geni-uart"; 1564 reg = <0 0x0099c000 0 0x4000>; 1565 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1566 clock-names = "se"; 1567 pinctrl-names = "default"; 1568 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1569 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1570 power-domains = <&rpmhpd SC7280_CX>; 1571 operating-points-v2 = <&qup_opp_table>; 1572 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1573 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1574 interconnect-names = "qup-core", "qup-config"; 1575 status = "disabled"; 1576 }; 1577 }; 1578 1579 gpi_dma1: dma-controller@a00000 { 1580 #dma-cells = <3>; 1581 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1582 reg = <0 0x00a00000 0 0x60000>; 1583 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1584 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1585 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1586 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1587 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1588 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1589 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1590 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1591 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1592 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1593 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1595 dma-channels = <12>; 1596 dma-channel-mask = <0x1e>; 1597 iommus = <&apps_smmu 0x56 0x0>; 1598 status = "disabled"; 1599 }; 1600 1601 qupv3_id_1: geniqup@ac0000 { 1602 compatible = "qcom,geni-se-qup"; 1603 reg = <0 0x00ac0000 0 0x2000>; 1604 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1605 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1606 clock-names = "m-ahb", "s-ahb"; 1607 #address-cells = <2>; 1608 #size-cells = <2>; 1609 ranges; 1610 iommus = <&apps_smmu 0x43 0x0>; 1611 status = "disabled"; 1612 1613 i2c8: i2c@a80000 { 1614 compatible = "qcom,geni-i2c"; 1615 reg = <0 0x00a80000 0 0x4000>; 1616 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1617 clock-names = "se"; 1618 pinctrl-names = "default"; 1619 pinctrl-0 = <&qup_i2c8_data_clk>; 1620 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1621 #address-cells = <1>; 1622 #size-cells = <0>; 1623 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1624 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1625 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1626 interconnect-names = "qup-core", "qup-config", 1627 "qup-memory"; 1628 power-domains = <&rpmhpd SC7280_CX>; 1629 required-opps = <&rpmhpd_opp_low_svs>; 1630 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1631 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1632 dma-names = "tx", "rx"; 1633 status = "disabled"; 1634 }; 1635 1636 spi8: spi@a80000 { 1637 compatible = "qcom,geni-spi"; 1638 reg = <0 0x00a80000 0 0x4000>; 1639 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1640 clock-names = "se"; 1641 pinctrl-names = "default"; 1642 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1643 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1644 #address-cells = <1>; 1645 #size-cells = <0>; 1646 power-domains = <&rpmhpd SC7280_CX>; 1647 operating-points-v2 = <&qup_opp_table>; 1648 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1649 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1650 interconnect-names = "qup-core", "qup-config"; 1651 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1652 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1653 dma-names = "tx", "rx"; 1654 status = "disabled"; 1655 }; 1656 1657 uart8: serial@a80000 { 1658 compatible = "qcom,geni-uart"; 1659 reg = <0 0x00a80000 0 0x4000>; 1660 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1661 clock-names = "se"; 1662 pinctrl-names = "default"; 1663 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1664 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1665 power-domains = <&rpmhpd SC7280_CX>; 1666 operating-points-v2 = <&qup_opp_table>; 1667 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1668 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1669 interconnect-names = "qup-core", "qup-config"; 1670 status = "disabled"; 1671 }; 1672 1673 i2c9: i2c@a84000 { 1674 compatible = "qcom,geni-i2c"; 1675 reg = <0 0x00a84000 0 0x4000>; 1676 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1677 clock-names = "se"; 1678 pinctrl-names = "default"; 1679 pinctrl-0 = <&qup_i2c9_data_clk>; 1680 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1681 #address-cells = <1>; 1682 #size-cells = <0>; 1683 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1684 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1685 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1686 interconnect-names = "qup-core", "qup-config", 1687 "qup-memory"; 1688 power-domains = <&rpmhpd SC7280_CX>; 1689 required-opps = <&rpmhpd_opp_low_svs>; 1690 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1691 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1692 dma-names = "tx", "rx"; 1693 status = "disabled"; 1694 }; 1695 1696 spi9: spi@a84000 { 1697 compatible = "qcom,geni-spi"; 1698 reg = <0 0x00a84000 0 0x4000>; 1699 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1700 clock-names = "se"; 1701 pinctrl-names = "default"; 1702 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1703 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1704 #address-cells = <1>; 1705 #size-cells = <0>; 1706 power-domains = <&rpmhpd SC7280_CX>; 1707 operating-points-v2 = <&qup_opp_table>; 1708 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1709 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1710 interconnect-names = "qup-core", "qup-config"; 1711 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1712 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1713 dma-names = "tx", "rx"; 1714 status = "disabled"; 1715 }; 1716 1717 uart9: serial@a84000 { 1718 compatible = "qcom,geni-uart"; 1719 reg = <0 0x00a84000 0 0x4000>; 1720 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1721 clock-names = "se"; 1722 pinctrl-names = "default"; 1723 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1724 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1725 power-domains = <&rpmhpd SC7280_CX>; 1726 operating-points-v2 = <&qup_opp_table>; 1727 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1728 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1729 interconnect-names = "qup-core", "qup-config"; 1730 status = "disabled"; 1731 }; 1732 1733 i2c10: i2c@a88000 { 1734 compatible = "qcom,geni-i2c"; 1735 reg = <0 0x00a88000 0 0x4000>; 1736 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1737 clock-names = "se"; 1738 pinctrl-names = "default"; 1739 pinctrl-0 = <&qup_i2c10_data_clk>; 1740 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1741 #address-cells = <1>; 1742 #size-cells = <0>; 1743 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1744 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1745 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1746 interconnect-names = "qup-core", "qup-config", 1747 "qup-memory"; 1748 power-domains = <&rpmhpd SC7280_CX>; 1749 required-opps = <&rpmhpd_opp_low_svs>; 1750 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1751 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1752 dma-names = "tx", "rx"; 1753 status = "disabled"; 1754 }; 1755 1756 spi10: spi@a88000 { 1757 compatible = "qcom,geni-spi"; 1758 reg = <0 0x00a88000 0 0x4000>; 1759 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1760 clock-names = "se"; 1761 pinctrl-names = "default"; 1762 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1763 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1764 #address-cells = <1>; 1765 #size-cells = <0>; 1766 power-domains = <&rpmhpd SC7280_CX>; 1767 operating-points-v2 = <&qup_opp_table>; 1768 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1769 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1770 interconnect-names = "qup-core", "qup-config"; 1771 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1772 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1773 dma-names = "tx", "rx"; 1774 status = "disabled"; 1775 }; 1776 1777 uart10: serial@a88000 { 1778 compatible = "qcom,geni-uart"; 1779 reg = <0 0x00a88000 0 0x4000>; 1780 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1781 clock-names = "se"; 1782 pinctrl-names = "default"; 1783 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1784 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1785 power-domains = <&rpmhpd SC7280_CX>; 1786 operating-points-v2 = <&qup_opp_table>; 1787 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1788 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1789 interconnect-names = "qup-core", "qup-config"; 1790 status = "disabled"; 1791 }; 1792 1793 i2c11: i2c@a8c000 { 1794 compatible = "qcom,geni-i2c"; 1795 reg = <0 0x00a8c000 0 0x4000>; 1796 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1797 clock-names = "se"; 1798 pinctrl-names = "default"; 1799 pinctrl-0 = <&qup_i2c11_data_clk>; 1800 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1801 #address-cells = <1>; 1802 #size-cells = <0>; 1803 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1804 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1805 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1806 interconnect-names = "qup-core", "qup-config", 1807 "qup-memory"; 1808 power-domains = <&rpmhpd SC7280_CX>; 1809 required-opps = <&rpmhpd_opp_low_svs>; 1810 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1811 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1812 dma-names = "tx", "rx"; 1813 status = "disabled"; 1814 }; 1815 1816 spi11: spi@a8c000 { 1817 compatible = "qcom,geni-spi"; 1818 reg = <0 0x00a8c000 0 0x4000>; 1819 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1820 clock-names = "se"; 1821 pinctrl-names = "default"; 1822 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1823 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1824 #address-cells = <1>; 1825 #size-cells = <0>; 1826 power-domains = <&rpmhpd SC7280_CX>; 1827 operating-points-v2 = <&qup_opp_table>; 1828 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1829 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1830 interconnect-names = "qup-core", "qup-config"; 1831 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1832 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1833 dma-names = "tx", "rx"; 1834 status = "disabled"; 1835 }; 1836 1837 uart11: serial@a8c000 { 1838 compatible = "qcom,geni-uart"; 1839 reg = <0 0x00a8c000 0 0x4000>; 1840 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1841 clock-names = "se"; 1842 pinctrl-names = "default"; 1843 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1844 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1845 power-domains = <&rpmhpd SC7280_CX>; 1846 operating-points-v2 = <&qup_opp_table>; 1847 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1848 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1849 interconnect-names = "qup-core", "qup-config"; 1850 status = "disabled"; 1851 }; 1852 1853 i2c12: i2c@a90000 { 1854 compatible = "qcom,geni-i2c"; 1855 reg = <0 0x00a90000 0 0x4000>; 1856 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1857 clock-names = "se"; 1858 pinctrl-names = "default"; 1859 pinctrl-0 = <&qup_i2c12_data_clk>; 1860 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1861 #address-cells = <1>; 1862 #size-cells = <0>; 1863 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1864 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1865 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1866 interconnect-names = "qup-core", "qup-config", 1867 "qup-memory"; 1868 power-domains = <&rpmhpd SC7280_CX>; 1869 required-opps = <&rpmhpd_opp_low_svs>; 1870 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1871 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1872 dma-names = "tx", "rx"; 1873 status = "disabled"; 1874 }; 1875 1876 spi12: spi@a90000 { 1877 compatible = "qcom,geni-spi"; 1878 reg = <0 0x00a90000 0 0x4000>; 1879 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1880 clock-names = "se"; 1881 pinctrl-names = "default"; 1882 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1883 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1884 #address-cells = <1>; 1885 #size-cells = <0>; 1886 power-domains = <&rpmhpd SC7280_CX>; 1887 operating-points-v2 = <&qup_opp_table>; 1888 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1889 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1890 interconnect-names = "qup-core", "qup-config"; 1891 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1892 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1893 dma-names = "tx", "rx"; 1894 status = "disabled"; 1895 }; 1896 1897 uart12: serial@a90000 { 1898 compatible = "qcom,geni-uart"; 1899 reg = <0 0x00a90000 0 0x4000>; 1900 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1901 clock-names = "se"; 1902 pinctrl-names = "default"; 1903 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1904 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1905 power-domains = <&rpmhpd SC7280_CX>; 1906 operating-points-v2 = <&qup_opp_table>; 1907 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1908 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1909 interconnect-names = "qup-core", "qup-config"; 1910 status = "disabled"; 1911 }; 1912 1913 i2c13: i2c@a94000 { 1914 compatible = "qcom,geni-i2c"; 1915 reg = <0 0x00a94000 0 0x4000>; 1916 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1917 clock-names = "se"; 1918 pinctrl-names = "default"; 1919 pinctrl-0 = <&qup_i2c13_data_clk>; 1920 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1921 #address-cells = <1>; 1922 #size-cells = <0>; 1923 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1924 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1925 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1926 interconnect-names = "qup-core", "qup-config", 1927 "qup-memory"; 1928 power-domains = <&rpmhpd SC7280_CX>; 1929 required-opps = <&rpmhpd_opp_low_svs>; 1930 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1931 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1932 dma-names = "tx", "rx"; 1933 status = "disabled"; 1934 }; 1935 1936 spi13: spi@a94000 { 1937 compatible = "qcom,geni-spi"; 1938 reg = <0 0x00a94000 0 0x4000>; 1939 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1940 clock-names = "se"; 1941 pinctrl-names = "default"; 1942 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1943 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1944 #address-cells = <1>; 1945 #size-cells = <0>; 1946 power-domains = <&rpmhpd SC7280_CX>; 1947 operating-points-v2 = <&qup_opp_table>; 1948 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1949 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1950 interconnect-names = "qup-core", "qup-config"; 1951 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1952 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1953 dma-names = "tx", "rx"; 1954 status = "disabled"; 1955 }; 1956 1957 uart13: serial@a94000 { 1958 compatible = "qcom,geni-uart"; 1959 reg = <0 0x00a94000 0 0x4000>; 1960 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1961 clock-names = "se"; 1962 pinctrl-names = "default"; 1963 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1964 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1965 power-domains = <&rpmhpd SC7280_CX>; 1966 operating-points-v2 = <&qup_opp_table>; 1967 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1968 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1969 interconnect-names = "qup-core", "qup-config"; 1970 status = "disabled"; 1971 }; 1972 1973 i2c14: i2c@a98000 { 1974 compatible = "qcom,geni-i2c"; 1975 reg = <0 0x00a98000 0 0x4000>; 1976 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1977 clock-names = "se"; 1978 pinctrl-names = "default"; 1979 pinctrl-0 = <&qup_i2c14_data_clk>; 1980 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1981 #address-cells = <1>; 1982 #size-cells = <0>; 1983 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1984 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1985 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1986 interconnect-names = "qup-core", "qup-config", 1987 "qup-memory"; 1988 power-domains = <&rpmhpd SC7280_CX>; 1989 required-opps = <&rpmhpd_opp_low_svs>; 1990 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1991 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1992 dma-names = "tx", "rx"; 1993 status = "disabled"; 1994 }; 1995 1996 spi14: spi@a98000 { 1997 compatible = "qcom,geni-spi"; 1998 reg = <0 0x00a98000 0 0x4000>; 1999 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2000 clock-names = "se"; 2001 pinctrl-names = "default"; 2002 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 2003 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 2004 #address-cells = <1>; 2005 #size-cells = <0>; 2006 power-domains = <&rpmhpd SC7280_CX>; 2007 operating-points-v2 = <&qup_opp_table>; 2008 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2009 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2010 interconnect-names = "qup-core", "qup-config"; 2011 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2012 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2013 dma-names = "tx", "rx"; 2014 status = "disabled"; 2015 }; 2016 2017 uart14: serial@a98000 { 2018 compatible = "qcom,geni-uart"; 2019 reg = <0 0x00a98000 0 0x4000>; 2020 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2021 clock-names = "se"; 2022 pinctrl-names = "default"; 2023 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 2024 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 2025 power-domains = <&rpmhpd SC7280_CX>; 2026 operating-points-v2 = <&qup_opp_table>; 2027 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2028 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2029 interconnect-names = "qup-core", "qup-config"; 2030 status = "disabled"; 2031 }; 2032 2033 i2c15: i2c@a9c000 { 2034 compatible = "qcom,geni-i2c"; 2035 reg = <0 0x00a9c000 0 0x4000>; 2036 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2037 clock-names = "se"; 2038 pinctrl-names = "default"; 2039 pinctrl-0 = <&qup_i2c15_data_clk>; 2040 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2041 #address-cells = <1>; 2042 #size-cells = <0>; 2043 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2044 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 2045 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2046 interconnect-names = "qup-core", "qup-config", 2047 "qup-memory"; 2048 power-domains = <&rpmhpd SC7280_CX>; 2049 required-opps = <&rpmhpd_opp_low_svs>; 2050 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2051 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2052 dma-names = "tx", "rx"; 2053 status = "disabled"; 2054 }; 2055 2056 spi15: spi@a9c000 { 2057 compatible = "qcom,geni-spi"; 2058 reg = <0 0x00a9c000 0 0x4000>; 2059 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2060 clock-names = "se"; 2061 pinctrl-names = "default"; 2062 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 2063 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2064 #address-cells = <1>; 2065 #size-cells = <0>; 2066 power-domains = <&rpmhpd SC7280_CX>; 2067 operating-points-v2 = <&qup_opp_table>; 2068 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2069 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2070 interconnect-names = "qup-core", "qup-config"; 2071 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2072 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2073 dma-names = "tx", "rx"; 2074 status = "disabled"; 2075 }; 2076 2077 uart15: serial@a9c000 { 2078 compatible = "qcom,geni-uart"; 2079 reg = <0 0x00a9c000 0 0x4000>; 2080 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2081 clock-names = "se"; 2082 pinctrl-names = "default"; 2083 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 2084 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2085 power-domains = <&rpmhpd SC7280_CX>; 2086 operating-points-v2 = <&qup_opp_table>; 2087 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2088 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2089 interconnect-names = "qup-core", "qup-config"; 2090 status = "disabled"; 2091 }; 2092 }; 2093 2094 rng: rng@10d3000 { 2095 compatible = "qcom,sc7280-trng", "qcom,trng"; 2096 reg = <0 0x010d3000 0 0x1000>; 2097 }; 2098 2099 cnoc2: interconnect@1500000 { 2100 reg = <0 0x01500000 0 0x1000>; 2101 compatible = "qcom,sc7280-cnoc2"; 2102 #interconnect-cells = <2>; 2103 qcom,bcm-voters = <&apps_bcm_voter>; 2104 }; 2105 2106 cnoc3: interconnect@1502000 { 2107 reg = <0 0x01502000 0 0x1000>; 2108 compatible = "qcom,sc7280-cnoc3"; 2109 #interconnect-cells = <2>; 2110 qcom,bcm-voters = <&apps_bcm_voter>; 2111 }; 2112 2113 mc_virt: interconnect@1580000 { 2114 reg = <0 0x01580000 0 0x4>; 2115 compatible = "qcom,sc7280-mc-virt"; 2116 #interconnect-cells = <2>; 2117 qcom,bcm-voters = <&apps_bcm_voter>; 2118 }; 2119 2120 system_noc: interconnect@1680000 { 2121 reg = <0 0x01680000 0 0x15480>; 2122 compatible = "qcom,sc7280-system-noc"; 2123 #interconnect-cells = <2>; 2124 qcom,bcm-voters = <&apps_bcm_voter>; 2125 }; 2126 2127 aggre1_noc: interconnect@16e0000 { 2128 compatible = "qcom,sc7280-aggre1-noc"; 2129 reg = <0 0x016e0000 0 0x1c080>; 2130 #interconnect-cells = <2>; 2131 qcom,bcm-voters = <&apps_bcm_voter>; 2132 }; 2133 2134 aggre2_noc: interconnect@1700000 { 2135 reg = <0 0x01700000 0 0x2b080>; 2136 compatible = "qcom,sc7280-aggre2-noc"; 2137 #interconnect-cells = <2>; 2138 qcom,bcm-voters = <&apps_bcm_voter>; 2139 }; 2140 2141 mmss_noc: interconnect@1740000 { 2142 reg = <0 0x01740000 0 0x1e080>; 2143 compatible = "qcom,sc7280-mmss-noc"; 2144 #interconnect-cells = <2>; 2145 qcom,bcm-voters = <&apps_bcm_voter>; 2146 }; 2147 2148 wifi: wifi@17a10040 { 2149 compatible = "qcom,wcn6750-wifi"; 2150 reg = <0 0x17a10040 0 0x0>; 2151 iommus = <&apps_smmu 0x1c00 0x1>; 2152 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 2153 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 2154 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 2155 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 2156 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 2157 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 2158 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 2159 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 2160 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 2161 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 2162 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 2163 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 2164 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 2165 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 2166 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 2167 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 2168 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 2169 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 2170 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 2171 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 2172 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 2173 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 2174 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 2175 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 2176 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 2177 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 2178 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 2179 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 2180 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2181 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2182 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2183 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2184 qcom,rproc = <&remoteproc_wpss>; 2185 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2186 status = "disabled"; 2187 qcom,smem-states = <&wlan_smp2p_out 0>; 2188 qcom,smem-state-names = "wlan-smp2p-out"; 2189 }; 2190 2191 pcie1: pcie@1c08000 { 2192 compatible = "qcom,pcie-sc7280"; 2193 reg = <0 0x01c08000 0 0x3000>, 2194 <0 0x40000000 0 0xf1d>, 2195 <0 0x40000f20 0 0xa8>, 2196 <0 0x40001000 0 0x1000>, 2197 <0 0x40100000 0 0x100000>; 2198 2199 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2200 device_type = "pci"; 2201 linux,pci-domain = <1>; 2202 bus-range = <0x00 0xff>; 2203 num-lanes = <2>; 2204 2205 #address-cells = <3>; 2206 #size-cells = <2>; 2207 2208 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2209 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2210 2211 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2212 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2213 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2214 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2215 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2216 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2217 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2218 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 2219 interrupt-names = "msi0", "msi1", "msi2", "msi3", 2220 "msi4", "msi5", "msi6", "msi7"; 2221 #interrupt-cells = <1>; 2222 interrupt-map-mask = <0 0 0 0x7>; 2223 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2224 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2225 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2226 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2227 2228 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2229 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2230 <&pcie1_phy>, 2231 <&rpmhcc RPMH_CXO_CLK>, 2232 <&gcc GCC_PCIE_1_AUX_CLK>, 2233 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2234 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2235 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2236 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2237 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2238 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2239 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2240 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2241 2242 clock-names = "pipe", 2243 "pipe_mux", 2244 "phy_pipe", 2245 "ref", 2246 "aux", 2247 "cfg", 2248 "bus_master", 2249 "bus_slave", 2250 "slave_q2a", 2251 "tbu", 2252 "ddrss_sf_tbu", 2253 "aggre0", 2254 "aggre1"; 2255 2256 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2257 assigned-clock-rates = <19200000>; 2258 2259 resets = <&gcc GCC_PCIE_1_BCR>; 2260 reset-names = "pci"; 2261 2262 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2263 2264 phys = <&pcie1_phy>; 2265 phy-names = "pciephy"; 2266 2267 pinctrl-names = "default"; 2268 pinctrl-0 = <&pcie1_clkreq_n>; 2269 2270 dma-coherent; 2271 2272 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2273 <0x100 &apps_smmu 0x1c81 0x1>; 2274 2275 status = "disabled"; 2276 }; 2277 2278 pcie1_phy: phy@1c0e000 { 2279 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2280 reg = <0 0x01c0e000 0 0x1000>; 2281 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2282 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2283 <&gcc GCC_PCIE_CLKREF_EN>, 2284 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, 2285 <&gcc GCC_PCIE_1_PIPE_CLK>; 2286 clock-names = "aux", 2287 "cfg_ahb", 2288 "ref", 2289 "refgen", 2290 "pipe"; 2291 2292 clock-output-names = "pcie_1_pipe_clk"; 2293 #clock-cells = <0>; 2294 2295 #phy-cells = <0>; 2296 2297 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2298 reset-names = "phy"; 2299 2300 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2301 assigned-clock-rates = <100000000>; 2302 2303 status = "disabled"; 2304 }; 2305 2306 ufs_mem_hc: ufs@1d84000 { 2307 compatible = "qcom,sc7280-ufshc", "qcom,ufshc", 2308 "jedec,ufs-2.0"; 2309 reg = <0x0 0x01d84000 0x0 0x3000>; 2310 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2311 phys = <&ufs_mem_phy>; 2312 phy-names = "ufsphy"; 2313 lanes-per-direction = <2>; 2314 #reset-cells = <1>; 2315 resets = <&gcc GCC_UFS_PHY_BCR>; 2316 reset-names = "rst"; 2317 2318 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 2319 required-opps = <&rpmhpd_opp_nom>; 2320 2321 iommus = <&apps_smmu 0x80 0x0>; 2322 dma-coherent; 2323 2324 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2325 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2326 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2327 &cnoc2 SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 2328 interconnect-names = "ufs-ddr", "cpu-ufs"; 2329 2330 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2331 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2332 <&gcc GCC_UFS_PHY_AHB_CLK>, 2333 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2334 <&rpmhcc RPMH_CXO_CLK>, 2335 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2336 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2337 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2338 clock-names = "core_clk", 2339 "bus_aggr_clk", 2340 "iface_clk", 2341 "core_clk_unipro", 2342 "ref_clk", 2343 "tx_lane0_sync_clk", 2344 "rx_lane0_sync_clk", 2345 "rx_lane1_sync_clk"; 2346 freq-table-hz = 2347 <75000000 300000000>, 2348 <0 0>, 2349 <0 0>, 2350 <75000000 300000000>, 2351 <0 0>, 2352 <0 0>, 2353 <0 0>, 2354 <0 0>; 2355 status = "disabled"; 2356 }; 2357 2358 ufs_mem_phy: phy@1d87000 { 2359 compatible = "qcom,sc7280-qmp-ufs-phy"; 2360 reg = <0x0 0x01d87000 0x0 0xe00>; 2361 clocks = <&rpmhcc RPMH_CXO_CLK>, 2362 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2363 <&gcc GCC_UFS_1_CLKREF_EN>; 2364 clock-names = "ref", "ref_aux", "qref"; 2365 2366 power-domains = <&rpmhpd SC7280_MX>; 2367 2368 resets = <&ufs_mem_hc 0>; 2369 reset-names = "ufsphy"; 2370 2371 #clock-cells = <1>; 2372 #phy-cells = <0>; 2373 2374 status = "disabled"; 2375 }; 2376 2377 cryptobam: dma-controller@1dc4000 { 2378 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2379 reg = <0x0 0x01dc4000 0x0 0x28000>; 2380 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2381 #dma-cells = <1>; 2382 iommus = <&apps_smmu 0x4e4 0x0011>, 2383 <&apps_smmu 0x4e6 0x0011>; 2384 qcom,ee = <0>; 2385 qcom,controlled-remotely; 2386 num-channels = <16>; 2387 qcom,num-ees = <4>; 2388 }; 2389 2390 crypto: crypto@1dfa000 { 2391 compatible = "qcom,sc7280-qce", "qcom,sm8150-qce", "qcom,qce"; 2392 reg = <0x0 0x01dfa000 0x0 0x6000>; 2393 dmas = <&cryptobam 4>, <&cryptobam 5>; 2394 dma-names = "rx", "tx"; 2395 iommus = <&apps_smmu 0x4e4 0x0011>, 2396 <&apps_smmu 0x4e4 0x0011>; 2397 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 2398 interconnect-names = "memory"; 2399 }; 2400 2401 ipa: ipa@1e40000 { 2402 compatible = "qcom,sc7280-ipa"; 2403 2404 iommus = <&apps_smmu 0x480 0x0>, 2405 <&apps_smmu 0x482 0x0>; 2406 reg = <0 0x01e40000 0 0x8000>, 2407 <0 0x01e50000 0 0x4ad0>, 2408 <0 0x01e04000 0 0x23000>; 2409 reg-names = "ipa-reg", 2410 "ipa-shared", 2411 "gsi"; 2412 2413 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2414 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2415 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2416 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2417 interrupt-names = "ipa", 2418 "gsi", 2419 "ipa-clock-query", 2420 "ipa-setup-ready"; 2421 2422 clocks = <&rpmhcc RPMH_IPA_CLK>; 2423 clock-names = "core"; 2424 2425 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2426 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2427 interconnect-names = "memory", 2428 "config"; 2429 2430 qcom,qmp = <&aoss_qmp>; 2431 2432 qcom,smem-states = <&ipa_smp2p_out 0>, 2433 <&ipa_smp2p_out 1>; 2434 qcom,smem-state-names = "ipa-clock-enabled-valid", 2435 "ipa-clock-enabled"; 2436 2437 status = "disabled"; 2438 }; 2439 2440 tcsr_mutex: hwlock@1f40000 { 2441 compatible = "qcom,tcsr-mutex"; 2442 reg = <0 0x01f40000 0 0x20000>; 2443 #hwlock-cells = <1>; 2444 }; 2445 2446 tcsr_1: syscon@1f60000 { 2447 compatible = "qcom,sc7280-tcsr", "syscon"; 2448 reg = <0 0x01f60000 0 0x20000>; 2449 }; 2450 2451 tcsr_2: syscon@1fc0000 { 2452 compatible = "qcom,sc7280-tcsr", "syscon"; 2453 reg = <0 0x01fc0000 0 0x30000>; 2454 }; 2455 2456 lpasscc: lpasscc@3000000 { 2457 compatible = "qcom,sc7280-lpasscc"; 2458 reg = <0 0x03000000 0 0x40>, 2459 <0 0x03c04000 0 0x4>; 2460 reg-names = "qdsp6ss", "top_cc"; 2461 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2462 clock-names = "iface"; 2463 #clock-cells = <1>; 2464 status = "reserved"; /* Owned by ADSP firmware */ 2465 }; 2466 2467 lpass_rx_macro: codec@3200000 { 2468 compatible = "qcom,sc7280-lpass-rx-macro"; 2469 reg = <0 0x03200000 0 0x1000>; 2470 2471 pinctrl-names = "default"; 2472 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2473 2474 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2475 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2476 <&lpass_va_macro>; 2477 clock-names = "mclk", "npl", "fsgen"; 2478 2479 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2480 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2481 power-domain-names = "macro", "dcodec"; 2482 2483 #clock-cells = <0>; 2484 #sound-dai-cells = <1>; 2485 2486 status = "disabled"; 2487 }; 2488 2489 swr0: soundwire@3210000 { 2490 compatible = "qcom,soundwire-v1.6.0"; 2491 reg = <0 0x03210000 0 0x2000>; 2492 2493 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2494 clocks = <&lpass_rx_macro>; 2495 clock-names = "iface"; 2496 2497 qcom,din-ports = <0>; 2498 qcom,dout-ports = <5>; 2499 2500 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2501 reset-names = "swr_audio_cgcr"; 2502 2503 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2504 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2505 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2506 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2507 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2508 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2509 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2510 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2511 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2512 2513 #sound-dai-cells = <1>; 2514 #address-cells = <2>; 2515 #size-cells = <0>; 2516 2517 status = "disabled"; 2518 }; 2519 2520 lpass_tx_macro: codec@3220000 { 2521 compatible = "qcom,sc7280-lpass-tx-macro"; 2522 reg = <0 0x03220000 0 0x1000>; 2523 2524 pinctrl-names = "default"; 2525 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2526 2527 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2528 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2529 <&lpass_va_macro>; 2530 clock-names = "mclk", "npl", "fsgen"; 2531 2532 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2533 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2534 power-domain-names = "macro", "dcodec"; 2535 2536 #clock-cells = <0>; 2537 #sound-dai-cells = <1>; 2538 2539 status = "disabled"; 2540 }; 2541 2542 swr1: soundwire@3230000 { 2543 compatible = "qcom,soundwire-v1.6.0"; 2544 reg = <0 0x03230000 0 0x2000>; 2545 2546 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2547 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2548 clocks = <&lpass_tx_macro>; 2549 clock-names = "iface"; 2550 2551 qcom,din-ports = <3>; 2552 qcom,dout-ports = <0>; 2553 2554 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2555 reset-names = "swr_audio_cgcr"; 2556 2557 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2558 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2559 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2560 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2561 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2562 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2563 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2564 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2565 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2566 2567 #sound-dai-cells = <1>; 2568 #address-cells = <2>; 2569 #size-cells = <0>; 2570 2571 status = "disabled"; 2572 }; 2573 2574 lpass_audiocc: clock-controller@3300000 { 2575 compatible = "qcom,sc7280-lpassaudiocc"; 2576 reg = <0 0x03300000 0 0x30000>, 2577 <0 0x032a9000 0 0x1000>; 2578 clocks = <&rpmhcc RPMH_CXO_CLK>, 2579 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2580 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2581 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2582 #clock-cells = <1>; 2583 #power-domain-cells = <1>; 2584 #reset-cells = <1>; 2585 }; 2586 2587 lpass_va_macro: codec@3370000 { 2588 compatible = "qcom,sc7280-lpass-va-macro"; 2589 reg = <0 0x03370000 0 0x1000>; 2590 2591 pinctrl-names = "default"; 2592 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; 2593 2594 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2595 clock-names = "mclk"; 2596 2597 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2598 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2599 power-domain-names = "macro", "dcodec"; 2600 2601 #clock-cells = <0>; 2602 #sound-dai-cells = <1>; 2603 2604 status = "disabled"; 2605 }; 2606 2607 lpass_aon: clock-controller@3380000 { 2608 compatible = "qcom,sc7280-lpassaoncc"; 2609 reg = <0 0x03380000 0 0x30000>; 2610 clocks = <&rpmhcc RPMH_CXO_CLK>, 2611 <&rpmhcc RPMH_CXO_CLK_A>, 2612 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2613 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2614 #clock-cells = <1>; 2615 #power-domain-cells = <1>; 2616 status = "reserved"; /* Owned by ADSP firmware */ 2617 }; 2618 2619 lpass_core: clock-controller@3900000 { 2620 compatible = "qcom,sc7280-lpasscorecc"; 2621 reg = <0 0x03900000 0 0x50000>; 2622 clocks = <&rpmhcc RPMH_CXO_CLK>; 2623 clock-names = "bi_tcxo"; 2624 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2625 #clock-cells = <1>; 2626 #power-domain-cells = <1>; 2627 status = "reserved"; /* Owned by ADSP firmware */ 2628 }; 2629 2630 lpass_cpu: audio@3987000 { 2631 compatible = "qcom,sc7280-lpass-cpu"; 2632 2633 reg = <0 0x03987000 0 0x68000>, 2634 <0 0x03b00000 0 0x29000>, 2635 <0 0x03260000 0 0xc000>, 2636 <0 0x03280000 0 0x29000>, 2637 <0 0x03340000 0 0x29000>, 2638 <0 0x0336c000 0 0x3000>; 2639 reg-names = "lpass-hdmiif", 2640 "lpass-lpaif", 2641 "lpass-rxtx-cdc-dma-lpm", 2642 "lpass-rxtx-lpaif", 2643 "lpass-va-lpaif", 2644 "lpass-va-cdc-dma-lpm"; 2645 2646 iommus = <&apps_smmu 0x1820 0>, 2647 <&apps_smmu 0x1821 0>, 2648 <&apps_smmu 0x1832 0>; 2649 2650 power-domains = <&rpmhpd SC7280_LCX>; 2651 power-domain-names = "lcx"; 2652 required-opps = <&rpmhpd_opp_nom>; 2653 2654 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2655 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2656 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2657 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2658 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2659 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2660 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2661 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2662 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2663 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2664 clock-names = "aon_cc_audio_hm_h", 2665 "audio_cc_ext_mclk0", 2666 "core_cc_sysnoc_mport_core", 2667 "core_cc_ext_if0_ibit", 2668 "core_cc_ext_if1_ibit", 2669 "audio_cc_codec_mem", 2670 "audio_cc_codec_mem0", 2671 "audio_cc_codec_mem1", 2672 "audio_cc_codec_mem2", 2673 "aon_cc_va_mem0"; 2674 2675 #sound-dai-cells = <1>; 2676 #address-cells = <1>; 2677 #size-cells = <0>; 2678 2679 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2680 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2681 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2682 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2683 interrupt-names = "lpass-irq-lpaif", 2684 "lpass-irq-hdmi", 2685 "lpass-irq-vaif", 2686 "lpass-irq-rxtxif"; 2687 2688 status = "disabled"; 2689 }; 2690 2691 slimbam: dma-controller@3a84000 { 2692 compatible = "qcom,bam-v1.7.0"; 2693 reg = <0 0x03a84000 0 0x20000>; 2694 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 2695 #dma-cells = <1>; 2696 qcom,controlled-remotely; 2697 num-channels = <31>; 2698 qcom,ee = <1>; 2699 qcom,num-ees = <2>; 2700 iommus = <&apps_smmu 0x1826 0x0>; 2701 status = "disabled"; 2702 }; 2703 2704 slim: slim-ngd@3ac0000 { 2705 compatible = "qcom,slim-ngd-v1.5.0"; 2706 reg = <0 0x03ac0000 0 0x2c000>; 2707 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 2708 dmas = <&slimbam 3>, <&slimbam 4>; 2709 dma-names = "rx", "tx"; 2710 iommus = <&apps_smmu 0x1826 0x0>; 2711 #address-cells = <1>; 2712 #size-cells = <0>; 2713 status = "disabled"; 2714 }; 2715 2716 lpass_hm: clock-controller@3c00000 { 2717 compatible = "qcom,sc7280-lpasshm"; 2718 reg = <0 0x03c00000 0 0x28>; 2719 clocks = <&rpmhcc RPMH_CXO_CLK>; 2720 clock-names = "bi_tcxo"; 2721 #clock-cells = <1>; 2722 #power-domain-cells = <1>; 2723 status = "reserved"; /* Owned by ADSP firmware */ 2724 }; 2725 2726 lpass_ag_noc: interconnect@3c40000 { 2727 reg = <0 0x03c40000 0 0xf080>; 2728 compatible = "qcom,sc7280-lpass-ag-noc"; 2729 #interconnect-cells = <2>; 2730 qcom,bcm-voters = <&apps_bcm_voter>; 2731 }; 2732 2733 lpass_tlmm: pinctrl@33c0000 { 2734 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2735 reg = <0 0x033c0000 0x0 0x20000>, 2736 <0 0x03550000 0x0 0x10000>; 2737 gpio-controller; 2738 #gpio-cells = <2>; 2739 gpio-ranges = <&lpass_tlmm 0 0 15>; 2740 2741 lpass_dmic01_clk: dmic01-clk-state { 2742 pins = "gpio6"; 2743 function = "dmic1_clk"; 2744 }; 2745 2746 lpass_dmic01_data: dmic01-data-state { 2747 pins = "gpio7"; 2748 function = "dmic1_data"; 2749 }; 2750 2751 lpass_dmic23_clk: dmic23-clk-state { 2752 pins = "gpio8"; 2753 function = "dmic2_clk"; 2754 }; 2755 2756 lpass_dmic23_data: dmic23-data-state { 2757 pins = "gpio9"; 2758 function = "dmic2_data"; 2759 }; 2760 2761 lpass_rx_swr_clk: rx-swr-clk-state { 2762 pins = "gpio3"; 2763 function = "swr_rx_clk"; 2764 }; 2765 2766 lpass_rx_swr_data: rx-swr-data-state { 2767 pins = "gpio4", "gpio5"; 2768 function = "swr_rx_data"; 2769 }; 2770 2771 lpass_tx_swr_clk: tx-swr-clk-state { 2772 pins = "gpio0"; 2773 function = "swr_tx_clk"; 2774 }; 2775 2776 lpass_tx_swr_data: tx-swr-data-state { 2777 pins = "gpio1", "gpio2", "gpio14"; 2778 function = "swr_tx_data"; 2779 }; 2780 }; 2781 2782 gpu: gpu@3d00000 { 2783 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2784 reg = <0 0x03d00000 0 0x40000>, 2785 <0 0x03d9e000 0 0x1000>, 2786 <0 0x03d61000 0 0x800>; 2787 reg-names = "kgsl_3d0_reg_memory", 2788 "cx_mem", 2789 "cx_dbgc"; 2790 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2791 iommus = <&adreno_smmu 0 0x400>, 2792 <&adreno_smmu 1 0x400>; 2793 operating-points-v2 = <&gpu_opp_table>; 2794 qcom,gmu = <&gmu>; 2795 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2796 interconnect-names = "gfx-mem"; 2797 #cooling-cells = <2>; 2798 2799 nvmem-cells = <&gpu_speed_bin>; 2800 nvmem-cell-names = "speed_bin"; 2801 2802 gpu_zap_shader: zap-shader { 2803 memory-region = <&gpu_zap_mem>; 2804 }; 2805 2806 gpu_opp_table: opp-table { 2807 compatible = "operating-points-v2"; 2808 2809 opp-315000000 { 2810 opp-hz = /bits/ 64 <315000000>; 2811 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2812 opp-peak-kBps = <1804000>; 2813 opp-supported-hw = <0x07>; 2814 }; 2815 2816 opp-450000000 { 2817 opp-hz = /bits/ 64 <450000000>; 2818 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2819 opp-peak-kBps = <4068000>; 2820 opp-supported-hw = <0x07>; 2821 }; 2822 2823 /* Only applicable for SKUs which has 550Mhz as Fmax */ 2824 opp-550000000-0 { 2825 opp-hz = /bits/ 64 <550000000>; 2826 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2827 opp-peak-kBps = <8368000>; 2828 opp-supported-hw = <0x01>; 2829 }; 2830 2831 opp-550000000-1 { 2832 opp-hz = /bits/ 64 <550000000>; 2833 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2834 opp-peak-kBps = <6832000>; 2835 opp-supported-hw = <0x06>; 2836 }; 2837 2838 opp-608000000 { 2839 opp-hz = /bits/ 64 <608000000>; 2840 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2841 opp-peak-kBps = <8368000>; 2842 opp-supported-hw = <0x06>; 2843 }; 2844 2845 opp-700000000 { 2846 opp-hz = /bits/ 64 <700000000>; 2847 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2848 opp-peak-kBps = <8532000>; 2849 opp-supported-hw = <0x06>; 2850 }; 2851 2852 opp-812000000 { 2853 opp-hz = /bits/ 64 <812000000>; 2854 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2855 opp-peak-kBps = <8532000>; 2856 opp-supported-hw = <0x06>; 2857 }; 2858 2859 opp-840000000 { 2860 opp-hz = /bits/ 64 <840000000>; 2861 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2862 opp-peak-kBps = <8532000>; 2863 opp-supported-hw = <0x02>; 2864 }; 2865 2866 opp-900000000 { 2867 opp-hz = /bits/ 64 <900000000>; 2868 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2869 opp-peak-kBps = <8532000>; 2870 opp-supported-hw = <0x02>; 2871 }; 2872 }; 2873 }; 2874 2875 gmu: gmu@3d6a000 { 2876 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2877 reg = <0 0x03d6a000 0 0x34000>, 2878 <0 0x3de0000 0 0x10000>, 2879 <0 0x0b290000 0 0x10000>; 2880 reg-names = "gmu", "rscc", "gmu_pdc"; 2881 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2882 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2883 interrupt-names = "hfi", "gmu"; 2884 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2885 <&gpucc GPU_CC_CXO_CLK>, 2886 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2887 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2888 <&gpucc GPU_CC_AHB_CLK>, 2889 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2890 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2891 clock-names = "gmu", 2892 "cxo", 2893 "axi", 2894 "memnoc", 2895 "ahb", 2896 "hub", 2897 "smmu_vote"; 2898 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2899 <&gpucc GPU_CC_GX_GDSC>; 2900 power-domain-names = "cx", 2901 "gx"; 2902 iommus = <&adreno_smmu 5 0x400>; 2903 operating-points-v2 = <&gmu_opp_table>; 2904 2905 gmu_opp_table: opp-table { 2906 compatible = "operating-points-v2"; 2907 2908 opp-200000000 { 2909 opp-hz = /bits/ 64 <200000000>; 2910 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2911 }; 2912 }; 2913 }; 2914 2915 gpucc: clock-controller@3d90000 { 2916 compatible = "qcom,sc7280-gpucc"; 2917 reg = <0 0x03d90000 0 0x9000>; 2918 clocks = <&rpmhcc RPMH_CXO_CLK>, 2919 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2920 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2921 clock-names = "bi_tcxo", 2922 "gcc_gpu_gpll0_clk_src", 2923 "gcc_gpu_gpll0_div_clk_src"; 2924 #clock-cells = <1>; 2925 #reset-cells = <1>; 2926 #power-domain-cells = <1>; 2927 }; 2928 2929 dma@117f000 { 2930 compatible = "qcom,sc7280-dcc", "qcom,dcc"; 2931 reg = <0x0 0x0117f000 0x0 0x1000>, 2932 <0x0 0x01112000 0x0 0x6000>; 2933 }; 2934 2935 adreno_smmu: iommu@3da0000 { 2936 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", 2937 "qcom,smmu-500", "arm,mmu-500"; 2938 reg = <0 0x03da0000 0 0x20000>; 2939 #iommu-cells = <2>; 2940 #global-interrupts = <2>; 2941 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2942 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2943 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2944 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2945 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2946 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2947 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2948 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2949 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2950 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2951 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2952 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2953 2954 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2955 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2956 <&gpucc GPU_CC_AHB_CLK>, 2957 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2958 <&gpucc GPU_CC_CX_GMU_CLK>, 2959 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2960 <&gpucc GPU_CC_HUB_AON_CLK>; 2961 clock-names = "gcc_gpu_memnoc_gfx_clk", 2962 "gcc_gpu_snoc_dvm_gfx_clk", 2963 "gpu_cc_ahb_clk", 2964 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2965 "gpu_cc_cx_gmu_clk", 2966 "gpu_cc_hub_cx_int_clk", 2967 "gpu_cc_hub_aon_clk"; 2968 2969 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2970 dma-coherent; 2971 }; 2972 2973 remoteproc_mpss: remoteproc@4080000 { 2974 compatible = "qcom,sc7280-mpss-pas"; 2975 reg = <0 0x04080000 0 0x10000>; 2976 2977 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2978 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2979 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2980 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2981 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2982 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2983 interrupt-names = "wdog", "fatal", "ready", "handover", 2984 "stop-ack", "shutdown-ack"; 2985 2986 clocks = <&rpmhcc RPMH_CXO_CLK>; 2987 clock-names = "xo"; 2988 2989 power-domains = <&rpmhpd SC7280_CX>, 2990 <&rpmhpd SC7280_MSS>; 2991 power-domain-names = "cx", "mss"; 2992 2993 memory-region = <&mpss_mem>; 2994 2995 qcom,qmp = <&aoss_qmp>; 2996 2997 qcom,smem-states = <&modem_smp2p_out 0>; 2998 qcom,smem-state-names = "stop"; 2999 3000 status = "disabled"; 3001 3002 glink-edge { 3003 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 3004 IPCC_MPROC_SIGNAL_GLINK_QMP 3005 IRQ_TYPE_EDGE_RISING>; 3006 mboxes = <&ipcc IPCC_CLIENT_MPSS 3007 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3008 label = "modem"; 3009 qcom,remote-pid = <1>; 3010 }; 3011 }; 3012 3013 stm@6002000 { 3014 compatible = "arm,coresight-stm", "arm,primecell"; 3015 reg = <0 0x06002000 0 0x1000>, 3016 <0 0x16280000 0 0x180000>; 3017 reg-names = "stm-base", "stm-stimulus-base"; 3018 3019 clocks = <&aoss_qmp>; 3020 clock-names = "apb_pclk"; 3021 3022 out-ports { 3023 port { 3024 stm_out: endpoint { 3025 remote-endpoint = <&funnel0_in7>; 3026 }; 3027 }; 3028 }; 3029 }; 3030 3031 funnel@6041000 { 3032 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3033 reg = <0 0x06041000 0 0x1000>; 3034 3035 clocks = <&aoss_qmp>; 3036 clock-names = "apb_pclk"; 3037 3038 out-ports { 3039 port { 3040 funnel0_out: endpoint { 3041 remote-endpoint = <&merge_funnel_in0>; 3042 }; 3043 }; 3044 }; 3045 3046 in-ports { 3047 #address-cells = <1>; 3048 #size-cells = <0>; 3049 3050 port@7 { 3051 reg = <7>; 3052 funnel0_in7: endpoint { 3053 remote-endpoint = <&stm_out>; 3054 }; 3055 }; 3056 }; 3057 }; 3058 3059 funnel@6042000 { 3060 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3061 reg = <0 0x06042000 0 0x1000>; 3062 3063 clocks = <&aoss_qmp>; 3064 clock-names = "apb_pclk"; 3065 3066 out-ports { 3067 port { 3068 funnel1_out: endpoint { 3069 remote-endpoint = <&merge_funnel_in1>; 3070 }; 3071 }; 3072 }; 3073 3074 in-ports { 3075 #address-cells = <1>; 3076 #size-cells = <0>; 3077 3078 port@4 { 3079 reg = <4>; 3080 funnel1_in4: endpoint { 3081 remote-endpoint = <&apss_merge_funnel_out>; 3082 }; 3083 }; 3084 }; 3085 }; 3086 3087 funnel@6045000 { 3088 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3089 reg = <0 0x06045000 0 0x1000>; 3090 3091 clocks = <&aoss_qmp>; 3092 clock-names = "apb_pclk"; 3093 3094 out-ports { 3095 port { 3096 merge_funnel_out: endpoint { 3097 remote-endpoint = <&swao_funnel_in>; 3098 }; 3099 }; 3100 }; 3101 3102 in-ports { 3103 #address-cells = <1>; 3104 #size-cells = <0>; 3105 3106 port@0 { 3107 reg = <0>; 3108 merge_funnel_in0: endpoint { 3109 remote-endpoint = <&funnel0_out>; 3110 }; 3111 }; 3112 3113 port@1 { 3114 reg = <1>; 3115 merge_funnel_in1: endpoint { 3116 remote-endpoint = <&funnel1_out>; 3117 }; 3118 }; 3119 }; 3120 }; 3121 3122 replicator@6046000 { 3123 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3124 reg = <0 0x06046000 0 0x1000>; 3125 3126 clocks = <&aoss_qmp>; 3127 clock-names = "apb_pclk"; 3128 3129 out-ports { 3130 port { 3131 replicator_out: endpoint { 3132 remote-endpoint = <&etr_in>; 3133 }; 3134 }; 3135 }; 3136 3137 in-ports { 3138 port { 3139 replicator_in: endpoint { 3140 remote-endpoint = <&swao_replicator_out>; 3141 }; 3142 }; 3143 }; 3144 }; 3145 3146 etr@6048000 { 3147 compatible = "arm,coresight-tmc", "arm,primecell"; 3148 reg = <0 0x06048000 0 0x1000>; 3149 iommus = <&apps_smmu 0x04c0 0>; 3150 3151 clocks = <&aoss_qmp>; 3152 clock-names = "apb_pclk"; 3153 arm,scatter-gather; 3154 3155 in-ports { 3156 port { 3157 etr_in: endpoint { 3158 remote-endpoint = <&replicator_out>; 3159 }; 3160 }; 3161 }; 3162 }; 3163 3164 funnel@6b04000 { 3165 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3166 reg = <0 0x06b04000 0 0x1000>; 3167 3168 clocks = <&aoss_qmp>; 3169 clock-names = "apb_pclk"; 3170 3171 out-ports { 3172 port { 3173 swao_funnel_out: endpoint { 3174 remote-endpoint = <&etf_in>; 3175 }; 3176 }; 3177 }; 3178 3179 in-ports { 3180 #address-cells = <1>; 3181 #size-cells = <0>; 3182 3183 port@7 { 3184 reg = <7>; 3185 swao_funnel_in: endpoint { 3186 remote-endpoint = <&merge_funnel_out>; 3187 }; 3188 }; 3189 }; 3190 }; 3191 3192 etf@6b05000 { 3193 compatible = "arm,coresight-tmc", "arm,primecell"; 3194 reg = <0 0x06b05000 0 0x1000>; 3195 3196 clocks = <&aoss_qmp>; 3197 clock-names = "apb_pclk"; 3198 3199 out-ports { 3200 port { 3201 etf_out: endpoint { 3202 remote-endpoint = <&swao_replicator_in>; 3203 }; 3204 }; 3205 }; 3206 3207 in-ports { 3208 port { 3209 etf_in: endpoint { 3210 remote-endpoint = <&swao_funnel_out>; 3211 }; 3212 }; 3213 }; 3214 }; 3215 3216 replicator@6b06000 { 3217 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3218 reg = <0 0x06b06000 0 0x1000>; 3219 3220 clocks = <&aoss_qmp>; 3221 clock-names = "apb_pclk"; 3222 qcom,replicator-loses-context; 3223 3224 out-ports { 3225 port { 3226 swao_replicator_out: endpoint { 3227 remote-endpoint = <&replicator_in>; 3228 }; 3229 }; 3230 }; 3231 3232 in-ports { 3233 port { 3234 swao_replicator_in: endpoint { 3235 remote-endpoint = <&etf_out>; 3236 }; 3237 }; 3238 }; 3239 }; 3240 3241 etm@7040000 { 3242 compatible = "arm,coresight-etm4x", "arm,primecell"; 3243 reg = <0 0x07040000 0 0x1000>; 3244 3245 cpu = <&CPU0>; 3246 3247 clocks = <&aoss_qmp>; 3248 clock-names = "apb_pclk"; 3249 arm,coresight-loses-context-with-cpu; 3250 qcom,skip-power-up; 3251 3252 out-ports { 3253 port { 3254 etm0_out: endpoint { 3255 remote-endpoint = <&apss_funnel_in0>; 3256 }; 3257 }; 3258 }; 3259 }; 3260 3261 etm@7140000 { 3262 compatible = "arm,coresight-etm4x", "arm,primecell"; 3263 reg = <0 0x07140000 0 0x1000>; 3264 3265 cpu = <&CPU1>; 3266 3267 clocks = <&aoss_qmp>; 3268 clock-names = "apb_pclk"; 3269 arm,coresight-loses-context-with-cpu; 3270 qcom,skip-power-up; 3271 3272 out-ports { 3273 port { 3274 etm1_out: endpoint { 3275 remote-endpoint = <&apss_funnel_in1>; 3276 }; 3277 }; 3278 }; 3279 }; 3280 3281 etm@7240000 { 3282 compatible = "arm,coresight-etm4x", "arm,primecell"; 3283 reg = <0 0x07240000 0 0x1000>; 3284 3285 cpu = <&CPU2>; 3286 3287 clocks = <&aoss_qmp>; 3288 clock-names = "apb_pclk"; 3289 arm,coresight-loses-context-with-cpu; 3290 qcom,skip-power-up; 3291 3292 out-ports { 3293 port { 3294 etm2_out: endpoint { 3295 remote-endpoint = <&apss_funnel_in2>; 3296 }; 3297 }; 3298 }; 3299 }; 3300 3301 etm@7340000 { 3302 compatible = "arm,coresight-etm4x", "arm,primecell"; 3303 reg = <0 0x07340000 0 0x1000>; 3304 3305 cpu = <&CPU3>; 3306 3307 clocks = <&aoss_qmp>; 3308 clock-names = "apb_pclk"; 3309 arm,coresight-loses-context-with-cpu; 3310 qcom,skip-power-up; 3311 3312 out-ports { 3313 port { 3314 etm3_out: endpoint { 3315 remote-endpoint = <&apss_funnel_in3>; 3316 }; 3317 }; 3318 }; 3319 }; 3320 3321 etm@7440000 { 3322 compatible = "arm,coresight-etm4x", "arm,primecell"; 3323 reg = <0 0x07440000 0 0x1000>; 3324 3325 cpu = <&CPU4>; 3326 3327 clocks = <&aoss_qmp>; 3328 clock-names = "apb_pclk"; 3329 arm,coresight-loses-context-with-cpu; 3330 qcom,skip-power-up; 3331 3332 out-ports { 3333 port { 3334 etm4_out: endpoint { 3335 remote-endpoint = <&apss_funnel_in4>; 3336 }; 3337 }; 3338 }; 3339 }; 3340 3341 etm@7540000 { 3342 compatible = "arm,coresight-etm4x", "arm,primecell"; 3343 reg = <0 0x07540000 0 0x1000>; 3344 3345 cpu = <&CPU5>; 3346 3347 clocks = <&aoss_qmp>; 3348 clock-names = "apb_pclk"; 3349 arm,coresight-loses-context-with-cpu; 3350 qcom,skip-power-up; 3351 3352 out-ports { 3353 port { 3354 etm5_out: endpoint { 3355 remote-endpoint = <&apss_funnel_in5>; 3356 }; 3357 }; 3358 }; 3359 }; 3360 3361 etm@7640000 { 3362 compatible = "arm,coresight-etm4x", "arm,primecell"; 3363 reg = <0 0x07640000 0 0x1000>; 3364 3365 cpu = <&CPU6>; 3366 3367 clocks = <&aoss_qmp>; 3368 clock-names = "apb_pclk"; 3369 arm,coresight-loses-context-with-cpu; 3370 qcom,skip-power-up; 3371 3372 out-ports { 3373 port { 3374 etm6_out: endpoint { 3375 remote-endpoint = <&apss_funnel_in6>; 3376 }; 3377 }; 3378 }; 3379 }; 3380 3381 etm@7740000 { 3382 compatible = "arm,coresight-etm4x", "arm,primecell"; 3383 reg = <0 0x07740000 0 0x1000>; 3384 3385 cpu = <&CPU7>; 3386 3387 clocks = <&aoss_qmp>; 3388 clock-names = "apb_pclk"; 3389 arm,coresight-loses-context-with-cpu; 3390 qcom,skip-power-up; 3391 3392 out-ports { 3393 port { 3394 etm7_out: endpoint { 3395 remote-endpoint = <&apss_funnel_in7>; 3396 }; 3397 }; 3398 }; 3399 }; 3400 3401 funnel@7800000 { /* APSS Funnel */ 3402 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3403 reg = <0 0x07800000 0 0x1000>; 3404 3405 clocks = <&aoss_qmp>; 3406 clock-names = "apb_pclk"; 3407 3408 out-ports { 3409 port { 3410 apss_funnel_out: endpoint { 3411 remote-endpoint = <&apss_merge_funnel_in>; 3412 }; 3413 }; 3414 }; 3415 3416 in-ports { 3417 #address-cells = <1>; 3418 #size-cells = <0>; 3419 3420 port@0 { 3421 reg = <0>; 3422 apss_funnel_in0: endpoint { 3423 remote-endpoint = <&etm0_out>; 3424 }; 3425 }; 3426 3427 port@1 { 3428 reg = <1>; 3429 apss_funnel_in1: endpoint { 3430 remote-endpoint = <&etm1_out>; 3431 }; 3432 }; 3433 3434 port@2 { 3435 reg = <2>; 3436 apss_funnel_in2: endpoint { 3437 remote-endpoint = <&etm2_out>; 3438 }; 3439 }; 3440 3441 port@3 { 3442 reg = <3>; 3443 apss_funnel_in3: endpoint { 3444 remote-endpoint = <&etm3_out>; 3445 }; 3446 }; 3447 3448 port@4 { 3449 reg = <4>; 3450 apss_funnel_in4: endpoint { 3451 remote-endpoint = <&etm4_out>; 3452 }; 3453 }; 3454 3455 port@5 { 3456 reg = <5>; 3457 apss_funnel_in5: endpoint { 3458 remote-endpoint = <&etm5_out>; 3459 }; 3460 }; 3461 3462 port@6 { 3463 reg = <6>; 3464 apss_funnel_in6: endpoint { 3465 remote-endpoint = <&etm6_out>; 3466 }; 3467 }; 3468 3469 port@7 { 3470 reg = <7>; 3471 apss_funnel_in7: endpoint { 3472 remote-endpoint = <&etm7_out>; 3473 }; 3474 }; 3475 }; 3476 }; 3477 3478 funnel@7810000 { 3479 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3480 reg = <0 0x07810000 0 0x1000>; 3481 3482 clocks = <&aoss_qmp>; 3483 clock-names = "apb_pclk"; 3484 3485 out-ports { 3486 port { 3487 apss_merge_funnel_out: endpoint { 3488 remote-endpoint = <&funnel1_in4>; 3489 }; 3490 }; 3491 }; 3492 3493 in-ports { 3494 port { 3495 apss_merge_funnel_in: endpoint { 3496 remote-endpoint = <&apss_funnel_out>; 3497 }; 3498 }; 3499 }; 3500 }; 3501 3502 sdhc_2: mmc@8804000 { 3503 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3504 pinctrl-names = "default", "sleep"; 3505 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3506 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3507 status = "disabled"; 3508 3509 reg = <0 0x08804000 0 0x1000>; 3510 3511 iommus = <&apps_smmu 0x100 0x0>; 3512 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3513 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3514 interrupt-names = "hc_irq", "pwr_irq"; 3515 3516 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3517 <&gcc GCC_SDCC2_APPS_CLK>, 3518 <&rpmhcc RPMH_CXO_CLK>; 3519 clock-names = "iface", "core", "xo"; 3520 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3521 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3522 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3523 power-domains = <&rpmhpd SC7280_CX>; 3524 operating-points-v2 = <&sdhc2_opp_table>; 3525 3526 bus-width = <4>; 3527 dma-coherent; 3528 3529 qcom,dll-config = <0x0007642c>; 3530 3531 resets = <&gcc GCC_SDCC2_BCR>; 3532 3533 sdhc2_opp_table: opp-table { 3534 compatible = "operating-points-v2"; 3535 3536 opp-100000000 { 3537 opp-hz = /bits/ 64 <100000000>; 3538 required-opps = <&rpmhpd_opp_low_svs>; 3539 opp-peak-kBps = <1800000 400000>; 3540 opp-avg-kBps = <100000 0>; 3541 }; 3542 3543 opp-202000000 { 3544 opp-hz = /bits/ 64 <202000000>; 3545 required-opps = <&rpmhpd_opp_nom>; 3546 opp-peak-kBps = <5400000 1600000>; 3547 opp-avg-kBps = <200000 0>; 3548 }; 3549 }; 3550 }; 3551 3552 usb_1_hsphy: phy@88e3000 { 3553 compatible = "qcom,sc7280-usb-hs-phy", 3554 "qcom,usb-snps-hs-7nm-phy"; 3555 reg = <0 0x088e3000 0 0x400>; 3556 status = "disabled"; 3557 #phy-cells = <0>; 3558 3559 clocks = <&rpmhcc RPMH_CXO_CLK>; 3560 clock-names = "ref"; 3561 3562 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3563 }; 3564 3565 usb_2_hsphy: phy@88e4000 { 3566 compatible = "qcom,sc7280-usb-hs-phy", 3567 "qcom,usb-snps-hs-7nm-phy"; 3568 reg = <0 0x088e4000 0 0x400>; 3569 status = "disabled"; 3570 #phy-cells = <0>; 3571 3572 clocks = <&rpmhcc RPMH_CXO_CLK>; 3573 clock-names = "ref"; 3574 3575 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3576 }; 3577 3578 usb_1_qmpphy: phy@88e8000 { 3579 compatible = "qcom,sc7280-qmp-usb3-dp-phy"; 3580 reg = <0 0x088e8000 0 0x3000>; 3581 status = "disabled"; 3582 3583 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3584 <&rpmhcc RPMH_CXO_CLK>, 3585 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3586 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3587 clock-names = "aux", 3588 "ref", 3589 "com_aux", 3590 "usb3_pipe"; 3591 3592 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3593 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3594 reset-names = "phy", "common"; 3595 3596 #clock-cells = <1>; 3597 #phy-cells = <1>; 3598 3599 ports { 3600 #address-cells = <1>; 3601 #size-cells = <0>; 3602 3603 port@0 { 3604 reg = <0>; 3605 3606 usb_dp_qmpphy_out: endpoint { 3607 }; 3608 }; 3609 3610 port@1 { 3611 reg = <1>; 3612 3613 usb_dp_qmpphy_usb_ss_in: endpoint { 3614 }; 3615 }; 3616 3617 port@2 { 3618 reg = <2>; 3619 3620 usb_dp_qmpphy_dp_in: endpoint { 3621 }; 3622 }; 3623 }; 3624 }; 3625 3626 usb_2: usb@8cf8800 { 3627 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3628 reg = <0 0x08cf8800 0 0x400>; 3629 status = "disabled"; 3630 #address-cells = <2>; 3631 #size-cells = <2>; 3632 ranges; 3633 dma-ranges; 3634 3635 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3636 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3637 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3638 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3639 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3640 clock-names = "cfg_noc", 3641 "core", 3642 "iface", 3643 "sleep", 3644 "mock_utmi"; 3645 3646 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3647 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3648 assigned-clock-rates = <19200000>, <200000000>; 3649 3650 interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 3651 <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3652 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 3653 <&pdc 13 IRQ_TYPE_EDGE_BOTH>; 3654 interrupt-names = "pwr_event", 3655 "hs_phy_irq", 3656 "dp_hs_phy_irq", 3657 "dm_hs_phy_irq"; 3658 3659 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3660 required-opps = <&rpmhpd_opp_nom>; 3661 3662 resets = <&gcc GCC_USB30_SEC_BCR>; 3663 3664 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3665 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3666 interconnect-names = "usb-ddr", "apps-usb"; 3667 3668 usb_2_dwc3: usb@8c00000 { 3669 compatible = "snps,dwc3"; 3670 reg = <0 0x08c00000 0 0xe000>; 3671 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3672 iommus = <&apps_smmu 0xa0 0x0>; 3673 snps,dis_u2_susphy_quirk; 3674 snps,dis_enblslpm_quirk; 3675 phys = <&usb_2_hsphy>; 3676 phy-names = "usb2-phy"; 3677 maximum-speed = "high-speed"; 3678 usb-role-switch; 3679 3680 port { 3681 usb2_role_switch: endpoint { 3682 remote-endpoint = <&eud_ep>; 3683 }; 3684 }; 3685 }; 3686 }; 3687 3688 qspi: spi@88dc000 { 3689 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3690 reg = <0 0x088dc000 0 0x1000>; 3691 iommus = <&apps_smmu 0x20 0x0>; 3692 #address-cells = <1>; 3693 #size-cells = <0>; 3694 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3695 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3696 <&gcc GCC_QSPI_CORE_CLK>; 3697 clock-names = "iface", "core"; 3698 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3699 &cnoc2 SLAVE_QSPI_0 0>; 3700 interconnect-names = "qspi-config"; 3701 power-domains = <&rpmhpd SC7280_CX>; 3702 operating-points-v2 = <&qspi_opp_table>; 3703 status = "disabled"; 3704 }; 3705 3706 remoteproc_adsp: remoteproc@3700000 { 3707 compatible = "qcom,sc7280-adsp-pas"; 3708 reg = <0 0x03700000 0 0x100>; 3709 3710 interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>, 3711 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3712 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3713 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3714 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3715 <&adsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3716 interrupt-names = "wdog", "fatal", "ready", "handover", 3717 "stop-ack", "shutdown-ack"; 3718 3719 clocks = <&rpmhcc RPMH_CXO_CLK>; 3720 clock-names = "xo"; 3721 3722 power-domains = <&rpmhpd SC7280_LCX>, 3723 <&rpmhpd SC7280_LMX>; 3724 power-domain-names = "lcx", "lmx"; 3725 3726 memory-region = <&adsp_mem>; 3727 3728 qcom,qmp = <&aoss_qmp>; 3729 3730 qcom,smem-states = <&adsp_smp2p_out 0>; 3731 qcom,smem-state-names = "stop"; 3732 3733 status = "disabled"; 3734 3735 glink-edge { 3736 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3737 IPCC_MPROC_SIGNAL_GLINK_QMP 3738 IRQ_TYPE_EDGE_RISING>; 3739 3740 mboxes = <&ipcc IPCC_CLIENT_LPASS 3741 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3742 3743 label = "lpass"; 3744 qcom,remote-pid = <2>; 3745 3746 fastrpc { 3747 compatible = "qcom,fastrpc"; 3748 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3749 label = "adsp"; 3750 qcom,non-secure-domain; 3751 #address-cells = <1>; 3752 #size-cells = <0>; 3753 3754 compute-cb@3 { 3755 compatible = "qcom,fastrpc-compute-cb"; 3756 reg = <3>; 3757 iommus = <&apps_smmu 0x1803 0x0>; 3758 }; 3759 3760 compute-cb@4 { 3761 compatible = "qcom,fastrpc-compute-cb"; 3762 reg = <4>; 3763 iommus = <&apps_smmu 0x1804 0x0>; 3764 }; 3765 3766 compute-cb@5 { 3767 compatible = "qcom,fastrpc-compute-cb"; 3768 reg = <5>; 3769 iommus = <&apps_smmu 0x1805 0x0>; 3770 }; 3771 }; 3772 }; 3773 }; 3774 3775 remoteproc_wpss: remoteproc@8a00000 { 3776 compatible = "qcom,sc7280-wpss-pas"; 3777 reg = <0 0x08a00000 0 0x10000>; 3778 3779 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3780 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3781 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3782 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3783 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3784 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3785 interrupt-names = "wdog", "fatal", "ready", "handover", 3786 "stop-ack", "shutdown-ack"; 3787 3788 clocks = <&rpmhcc RPMH_CXO_CLK>; 3789 clock-names = "xo"; 3790 3791 power-domains = <&rpmhpd SC7280_CX>, 3792 <&rpmhpd SC7280_MX>; 3793 power-domain-names = "cx", "mx"; 3794 3795 memory-region = <&wpss_mem>; 3796 3797 qcom,qmp = <&aoss_qmp>; 3798 3799 qcom,smem-states = <&wpss_smp2p_out 0>; 3800 qcom,smem-state-names = "stop"; 3801 3802 3803 status = "disabled"; 3804 3805 glink-edge { 3806 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3807 IPCC_MPROC_SIGNAL_GLINK_QMP 3808 IRQ_TYPE_EDGE_RISING>; 3809 mboxes = <&ipcc IPCC_CLIENT_WPSS 3810 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3811 3812 label = "wpss"; 3813 qcom,remote-pid = <13>; 3814 }; 3815 }; 3816 3817 pmu@9091000 { 3818 compatible = "qcom,sc7280-llcc-bwmon"; 3819 reg = <0 0x09091000 0 0x1000>; 3820 3821 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3822 3823 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3824 3825 operating-points-v2 = <&llcc_bwmon_opp_table>; 3826 3827 llcc_bwmon_opp_table: opp-table { 3828 compatible = "operating-points-v2"; 3829 3830 opp-0 { 3831 opp-peak-kBps = <800000>; 3832 }; 3833 opp-1 { 3834 opp-peak-kBps = <1804000>; 3835 }; 3836 opp-2 { 3837 opp-peak-kBps = <2188000>; 3838 }; 3839 opp-3 { 3840 opp-peak-kBps = <3072000>; 3841 }; 3842 opp-4 { 3843 opp-peak-kBps = <4068000>; 3844 }; 3845 opp-5 { 3846 opp-peak-kBps = <6220000>; 3847 }; 3848 opp-6 { 3849 opp-peak-kBps = <6832000>; 3850 }; 3851 opp-7 { 3852 opp-peak-kBps = <8532000>; 3853 }; 3854 }; 3855 }; 3856 3857 pmu@90b6400 { 3858 compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon"; 3859 reg = <0 0x090b6400 0 0x600>; 3860 3861 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3862 3863 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3864 operating-points-v2 = <&cpu_bwmon_opp_table>; 3865 3866 cpu_bwmon_opp_table: opp-table { 3867 compatible = "operating-points-v2"; 3868 3869 opp-0 { 3870 opp-peak-kBps = <2400000>; 3871 }; 3872 opp-1 { 3873 opp-peak-kBps = <4800000>; 3874 }; 3875 opp-2 { 3876 opp-peak-kBps = <7456000>; 3877 }; 3878 opp-3 { 3879 opp-peak-kBps = <9600000>; 3880 }; 3881 opp-4 { 3882 opp-peak-kBps = <12896000>; 3883 }; 3884 opp-5 { 3885 opp-peak-kBps = <14928000>; 3886 }; 3887 opp-6 { 3888 opp-peak-kBps = <17056000>; 3889 }; 3890 }; 3891 }; 3892 3893 dc_noc: interconnect@90e0000 { 3894 reg = <0 0x090e0000 0 0x5080>; 3895 compatible = "qcom,sc7280-dc-noc"; 3896 #interconnect-cells = <2>; 3897 qcom,bcm-voters = <&apps_bcm_voter>; 3898 }; 3899 3900 gem_noc: interconnect@9100000 { 3901 reg = <0 0x09100000 0 0xe2200>; 3902 compatible = "qcom,sc7280-gem-noc"; 3903 #interconnect-cells = <2>; 3904 qcom,bcm-voters = <&apps_bcm_voter>; 3905 }; 3906 3907 system-cache-controller@9200000 { 3908 compatible = "qcom,sc7280-llcc"; 3909 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 3910 <0 0x09600000 0 0x58000>; 3911 reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; 3912 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3913 }; 3914 3915 eud: eud@88e0000 { 3916 compatible = "qcom,sc7280-eud", "qcom,eud"; 3917 reg = <0 0x88e0000 0 0x2000>, 3918 <0 0x88e2000 0 0x1000>; 3919 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 3920 3921 status = "disabled"; 3922 3923 ports { 3924 #address-cells = <1>; 3925 #size-cells = <0>; 3926 3927 port@0 { 3928 reg = <0>; 3929 eud_ep: endpoint { 3930 remote-endpoint = <&usb2_role_switch>; 3931 }; 3932 }; 3933 }; 3934 }; 3935 3936 nsp_noc: interconnect@a0c0000 { 3937 reg = <0 0x0a0c0000 0 0x10000>; 3938 compatible = "qcom,sc7280-nsp-noc"; 3939 #interconnect-cells = <2>; 3940 qcom,bcm-voters = <&apps_bcm_voter>; 3941 }; 3942 3943 remoteproc_cdsp: remoteproc@a300000 { 3944 compatible = "qcom,sc7280-cdsp-pas"; 3945 reg = <0 0x0a300000 0 0x10000>; 3946 3947 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>, 3948 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3949 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3950 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3951 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3952 <&cdsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3953 interrupt-names = "wdog", "fatal", "ready", "handover", 3954 "stop-ack", "shutdown-ack"; 3955 3956 clocks = <&rpmhcc RPMH_CXO_CLK>; 3957 clock-names = "xo"; 3958 3959 power-domains = <&rpmhpd SC7280_CX>, 3960 <&rpmhpd SC7280_MX>; 3961 power-domain-names = "cx", "mx"; 3962 3963 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 3964 3965 memory-region = <&cdsp_mem>; 3966 3967 qcom,qmp = <&aoss_qmp>; 3968 3969 qcom,smem-states = <&cdsp_smp2p_out 0>; 3970 qcom,smem-state-names = "stop"; 3971 3972 status = "disabled"; 3973 3974 glink-edge { 3975 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3976 IPCC_MPROC_SIGNAL_GLINK_QMP 3977 IRQ_TYPE_EDGE_RISING>; 3978 mboxes = <&ipcc IPCC_CLIENT_CDSP 3979 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3980 3981 label = "cdsp"; 3982 qcom,remote-pid = <5>; 3983 3984 fastrpc { 3985 compatible = "qcom,fastrpc"; 3986 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3987 label = "cdsp"; 3988 qcom,non-secure-domain; 3989 #address-cells = <1>; 3990 #size-cells = <0>; 3991 3992 compute-cb@1 { 3993 compatible = "qcom,fastrpc-compute-cb"; 3994 reg = <1>; 3995 iommus = <&apps_smmu 0x11a1 0x0420>, 3996 <&apps_smmu 0x1181 0x0420>; 3997 }; 3998 3999 compute-cb@2 { 4000 compatible = "qcom,fastrpc-compute-cb"; 4001 reg = <2>; 4002 iommus = <&apps_smmu 0x11a2 0x0420>, 4003 <&apps_smmu 0x1182 0x0420>; 4004 }; 4005 4006 compute-cb@3 { 4007 compatible = "qcom,fastrpc-compute-cb"; 4008 reg = <3>; 4009 iommus = <&apps_smmu 0x11a3 0x0420>, 4010 <&apps_smmu 0x1183 0x0420>; 4011 }; 4012 4013 compute-cb@4 { 4014 compatible = "qcom,fastrpc-compute-cb"; 4015 reg = <4>; 4016 iommus = <&apps_smmu 0x11a4 0x0420>, 4017 <&apps_smmu 0x1184 0x0420>; 4018 }; 4019 4020 compute-cb@5 { 4021 compatible = "qcom,fastrpc-compute-cb"; 4022 reg = <5>; 4023 iommus = <&apps_smmu 0x11a5 0x0420>, 4024 <&apps_smmu 0x1185 0x0420>; 4025 }; 4026 4027 compute-cb@6 { 4028 compatible = "qcom,fastrpc-compute-cb"; 4029 reg = <6>; 4030 iommus = <&apps_smmu 0x11a6 0x0420>, 4031 <&apps_smmu 0x1186 0x0420>; 4032 }; 4033 4034 compute-cb@7 { 4035 compatible = "qcom,fastrpc-compute-cb"; 4036 reg = <7>; 4037 iommus = <&apps_smmu 0x11a7 0x0420>, 4038 <&apps_smmu 0x1187 0x0420>; 4039 }; 4040 4041 compute-cb@8 { 4042 compatible = "qcom,fastrpc-compute-cb"; 4043 reg = <8>; 4044 iommus = <&apps_smmu 0x11a8 0x0420>, 4045 <&apps_smmu 0x1188 0x0420>; 4046 }; 4047 4048 /* note: secure cb9 in downstream */ 4049 4050 compute-cb@11 { 4051 compatible = "qcom,fastrpc-compute-cb"; 4052 reg = <11>; 4053 iommus = <&apps_smmu 0x11ab 0x0420>, 4054 <&apps_smmu 0x118b 0x0420>; 4055 }; 4056 4057 compute-cb@12 { 4058 compatible = "qcom,fastrpc-compute-cb"; 4059 reg = <12>; 4060 iommus = <&apps_smmu 0x11ac 0x0420>, 4061 <&apps_smmu 0x118c 0x0420>; 4062 }; 4063 4064 compute-cb@13 { 4065 compatible = "qcom,fastrpc-compute-cb"; 4066 reg = <13>; 4067 iommus = <&apps_smmu 0x11ad 0x0420>, 4068 <&apps_smmu 0x118d 0x0420>; 4069 }; 4070 4071 compute-cb@14 { 4072 compatible = "qcom,fastrpc-compute-cb"; 4073 reg = <14>; 4074 iommus = <&apps_smmu 0x11ae 0x0420>, 4075 <&apps_smmu 0x118e 0x0420>; 4076 }; 4077 }; 4078 }; 4079 }; 4080 4081 usb_1: usb@a6f8800 { 4082 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 4083 reg = <0 0x0a6f8800 0 0x400>; 4084 status = "disabled"; 4085 #address-cells = <2>; 4086 #size-cells = <2>; 4087 ranges; 4088 dma-ranges; 4089 4090 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4091 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4092 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4093 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4094 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 4095 clock-names = "cfg_noc", 4096 "core", 4097 "iface", 4098 "sleep", 4099 "mock_utmi"; 4100 4101 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4102 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4103 assigned-clock-rates = <19200000>, <200000000>; 4104 4105 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4106 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4107 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4108 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4109 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 4110 interrupt-names = "pwr_event", 4111 "hs_phy_irq", 4112 "dp_hs_phy_irq", 4113 "dm_hs_phy_irq", 4114 "ss_phy_irq"; 4115 4116 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 4117 required-opps = <&rpmhpd_opp_nom>; 4118 4119 resets = <&gcc GCC_USB30_PRIM_BCR>; 4120 4121 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 4122 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 4123 interconnect-names = "usb-ddr", "apps-usb"; 4124 4125 wakeup-source; 4126 4127 usb_1_dwc3: usb@a600000 { 4128 compatible = "snps,dwc3"; 4129 reg = <0 0x0a600000 0 0xe000>; 4130 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4131 iommus = <&apps_smmu 0xe0 0x0>; 4132 snps,dis_u2_susphy_quirk; 4133 snps,dis_enblslpm_quirk; 4134 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4135 phy-names = "usb2-phy", "usb3-phy"; 4136 maximum-speed = "super-speed"; 4137 4138 ports { 4139 #address-cells = <1>; 4140 #size-cells = <0>; 4141 4142 port@0 { 4143 reg = <0>; 4144 4145 usb_1_dwc3_hs: endpoint { 4146 }; 4147 }; 4148 4149 port@1 { 4150 reg = <1>; 4151 4152 usb_1_dwc3_ss: endpoint { 4153 }; 4154 }; 4155 }; 4156 }; 4157 }; 4158 4159 venus: video-codec@aa00000 { 4160 compatible = "qcom,sc7280-venus"; 4161 reg = <0 0x0aa00000 0 0xd0600>; 4162 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4163 4164 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 4165 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 4166 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 4167 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 4168 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 4169 clock-names = "core", "bus", "iface", 4170 "vcodec_core", "vcodec_bus"; 4171 4172 power-domains = <&videocc MVSC_GDSC>, 4173 <&videocc MVS0_GDSC>, 4174 <&rpmhpd SC7280_CX>; 4175 power-domain-names = "venus", "vcodec0", "cx"; 4176 operating-points-v2 = <&venus_opp_table>; 4177 4178 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 4179 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 4180 interconnect-names = "cpu-cfg", "video-mem"; 4181 4182 iommus = <&apps_smmu 0x2180 0x20>; 4183 memory-region = <&video_mem>; 4184 4185 status = "disabled"; 4186 4187 video-decoder { 4188 compatible = "venus-decoder"; 4189 }; 4190 4191 video-encoder { 4192 compatible = "venus-encoder"; 4193 }; 4194 4195 venus_opp_table: opp-table { 4196 compatible = "operating-points-v2"; 4197 4198 opp-133330000 { 4199 opp-hz = /bits/ 64 <133330000>; 4200 required-opps = <&rpmhpd_opp_low_svs>; 4201 }; 4202 4203 opp-240000000 { 4204 opp-hz = /bits/ 64 <240000000>; 4205 required-opps = <&rpmhpd_opp_svs>; 4206 }; 4207 4208 opp-335000000 { 4209 opp-hz = /bits/ 64 <335000000>; 4210 required-opps = <&rpmhpd_opp_svs_l1>; 4211 }; 4212 4213 opp-424000000 { 4214 opp-hz = /bits/ 64 <424000000>; 4215 required-opps = <&rpmhpd_opp_nom>; 4216 }; 4217 4218 opp-460000048 { 4219 opp-hz = /bits/ 64 <460000048>; 4220 required-opps = <&rpmhpd_opp_turbo>; 4221 }; 4222 }; 4223 }; 4224 4225 videocc: clock-controller@aaf0000 { 4226 compatible = "qcom,sc7280-videocc"; 4227 reg = <0 0x0aaf0000 0 0x10000>; 4228 clocks = <&rpmhcc RPMH_CXO_CLK>, 4229 <&rpmhcc RPMH_CXO_CLK_A>; 4230 clock-names = "bi_tcxo", "bi_tcxo_ao"; 4231 #clock-cells = <1>; 4232 #reset-cells = <1>; 4233 #power-domain-cells = <1>; 4234 }; 4235 4236 cci0: cci@ac4a000 { 4237 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci"; 4238 reg = <0 0x0ac4a000 0 0x1000>; 4239 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4240 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4241 4242 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4243 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4244 <&camcc CAM_CC_CPAS_AHB_CLK>, 4245 <&camcc CAM_CC_CCI_0_CLK>, 4246 <&camcc CAM_CC_CCI_0_CLK_SRC>; 4247 clock-names = "camnoc_axi", 4248 "slow_ahb_src", 4249 "cpas_ahb", 4250 "cci", 4251 "cci_src"; 4252 pinctrl-0 = <&cci0_default &cci1_default>; 4253 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 4254 pinctrl-names = "default", "sleep"; 4255 4256 #address-cells = <1>; 4257 #size-cells = <0>; 4258 4259 status = "disabled"; 4260 4261 cci0_i2c0: i2c-bus@0 { 4262 reg = <0>; 4263 clock-frequency = <1000000>; 4264 #address-cells = <1>; 4265 #size-cells = <0>; 4266 }; 4267 4268 cci0_i2c1: i2c-bus@1 { 4269 reg = <1>; 4270 clock-frequency = <1000000>; 4271 #address-cells = <1>; 4272 #size-cells = <0>; 4273 }; 4274 }; 4275 4276 cci1: cci@ac4b000 { 4277 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci"; 4278 reg = <0 0x0ac4b000 0 0x1000>; 4279 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 4280 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4281 4282 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4283 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4284 <&camcc CAM_CC_CPAS_AHB_CLK>, 4285 <&camcc CAM_CC_CCI_1_CLK>, 4286 <&camcc CAM_CC_CCI_1_CLK_SRC>; 4287 clock-names = "camnoc_axi", 4288 "slow_ahb_src", 4289 "cpas_ahb", 4290 "cci", 4291 "cci_src"; 4292 pinctrl-0 = <&cci2_default &cci3_default>; 4293 pinctrl-1 = <&cci2_sleep &cci3_sleep>; 4294 pinctrl-names = "default", "sleep"; 4295 4296 #address-cells = <1>; 4297 #size-cells = <0>; 4298 4299 status = "disabled"; 4300 4301 cci1_i2c0: i2c-bus@0 { 4302 reg = <0>; 4303 clock-frequency = <1000000>; 4304 #address-cells = <1>; 4305 #size-cells = <0>; 4306 }; 4307 4308 cci1_i2c1: i2c-bus@1 { 4309 reg = <1>; 4310 clock-frequency = <1000000>; 4311 #address-cells = <1>; 4312 #size-cells = <0>; 4313 }; 4314 }; 4315 4316 camcc: clock-controller@ad00000 { 4317 compatible = "qcom,sc7280-camcc"; 4318 reg = <0 0x0ad00000 0 0x10000>; 4319 clocks = <&rpmhcc RPMH_CXO_CLK>, 4320 <&rpmhcc RPMH_CXO_CLK_A>, 4321 <&sleep_clk>; 4322 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 4323 #clock-cells = <1>; 4324 #reset-cells = <1>; 4325 #power-domain-cells = <1>; 4326 }; 4327 4328 dispcc: clock-controller@af00000 { 4329 compatible = "qcom,sc7280-dispcc"; 4330 reg = <0 0x0af00000 0 0x20000>; 4331 clocks = <&rpmhcc RPMH_CXO_CLK>, 4332 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 4333 <&mdss_dsi_phy 0>, 4334 <&mdss_dsi_phy 1>, 4335 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4336 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4337 <&mdss_edp_phy 0>, 4338 <&mdss_edp_phy 1>; 4339 clock-names = "bi_tcxo", 4340 "gcc_disp_gpll0_clk", 4341 "dsi0_phy_pll_out_byteclk", 4342 "dsi0_phy_pll_out_dsiclk", 4343 "dp_phy_pll_link_clk", 4344 "dp_phy_pll_vco_div_clk", 4345 "edp_phy_pll_link_clk", 4346 "edp_phy_pll_vco_div_clk"; 4347 #clock-cells = <1>; 4348 #reset-cells = <1>; 4349 #power-domain-cells = <1>; 4350 }; 4351 4352 mdss: display-subsystem@ae00000 { 4353 compatible = "qcom,sc7280-mdss"; 4354 reg = <0 0x0ae00000 0 0x1000>; 4355 reg-names = "mdss"; 4356 4357 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 4358 4359 clocks = <&gcc GCC_DISP_AHB_CLK>, 4360 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4361 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4362 clock-names = "iface", 4363 "ahb", 4364 "core"; 4365 4366 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4367 interrupt-controller; 4368 #interrupt-cells = <1>; 4369 4370 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS 4371 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4372 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4373 &cnoc2 SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>; 4374 interconnect-names = "mdp0-mem", 4375 "cpu-cfg"; 4376 4377 iommus = <&apps_smmu 0x900 0x402>; 4378 4379 #address-cells = <2>; 4380 #size-cells = <2>; 4381 ranges; 4382 4383 status = "disabled"; 4384 4385 mdss_mdp: display-controller@ae01000 { 4386 compatible = "qcom,sc7280-dpu"; 4387 reg = <0 0x0ae01000 0 0x8f030>, 4388 <0 0x0aeb0000 0 0x2008>; 4389 reg-names = "mdp", "vbif"; 4390 4391 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4392 <&gcc GCC_DISP_SF_AXI_CLK>, 4393 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4394 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 4395 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4396 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4397 clock-names = "bus", 4398 "nrt_bus", 4399 "iface", 4400 "lut", 4401 "core", 4402 "vsync"; 4403 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 4404 <&dispcc DISP_CC_MDSS_AHB_CLK>; 4405 assigned-clock-rates = <19200000>, 4406 <19200000>; 4407 operating-points-v2 = <&mdp_opp_table>; 4408 power-domains = <&rpmhpd SC7280_CX>; 4409 4410 interrupt-parent = <&mdss>; 4411 interrupts = <0>; 4412 4413 ports { 4414 #address-cells = <1>; 4415 #size-cells = <0>; 4416 4417 port@0 { 4418 reg = <0>; 4419 dpu_intf1_out: endpoint { 4420 remote-endpoint = <&mdss_dsi0_in>; 4421 }; 4422 }; 4423 4424 port@1 { 4425 reg = <1>; 4426 dpu_intf5_out: endpoint { 4427 remote-endpoint = <&edp_in>; 4428 }; 4429 }; 4430 4431 port@2 { 4432 reg = <2>; 4433 dpu_intf0_out: endpoint { 4434 remote-endpoint = <&dp_in>; 4435 }; 4436 }; 4437 }; 4438 4439 mdp_opp_table: opp-table { 4440 compatible = "operating-points-v2"; 4441 4442 opp-200000000 { 4443 opp-hz = /bits/ 64 <200000000>; 4444 required-opps = <&rpmhpd_opp_low_svs>; 4445 }; 4446 4447 opp-300000000 { 4448 opp-hz = /bits/ 64 <300000000>; 4449 required-opps = <&rpmhpd_opp_svs>; 4450 }; 4451 4452 opp-380000000 { 4453 opp-hz = /bits/ 64 <380000000>; 4454 required-opps = <&rpmhpd_opp_svs_l1>; 4455 }; 4456 4457 opp-506666667 { 4458 opp-hz = /bits/ 64 <506666667>; 4459 required-opps = <&rpmhpd_opp_nom>; 4460 }; 4461 }; 4462 }; 4463 4464 mdss_dsi: dsi@ae94000 { 4465 compatible = "qcom,sc7280-dsi-ctrl", 4466 "qcom,mdss-dsi-ctrl"; 4467 reg = <0 0x0ae94000 0 0x400>; 4468 reg-names = "dsi_ctrl"; 4469 4470 interrupt-parent = <&mdss>; 4471 interrupts = <4>; 4472 4473 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4474 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4475 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4476 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4477 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4478 <&gcc GCC_DISP_HF_AXI_CLK>; 4479 clock-names = "byte", 4480 "byte_intf", 4481 "pixel", 4482 "core", 4483 "iface", 4484 "bus"; 4485 4486 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4487 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>; 4488 4489 operating-points-v2 = <&dsi_opp_table>; 4490 power-domains = <&rpmhpd SC7280_CX>; 4491 4492 phys = <&mdss_dsi_phy>; 4493 4494 #address-cells = <1>; 4495 #size-cells = <0>; 4496 4497 status = "disabled"; 4498 4499 ports { 4500 #address-cells = <1>; 4501 #size-cells = <0>; 4502 4503 port@0 { 4504 reg = <0>; 4505 mdss_dsi0_in: endpoint { 4506 remote-endpoint = <&dpu_intf1_out>; 4507 }; 4508 }; 4509 4510 port@1 { 4511 reg = <1>; 4512 mdss_dsi0_out: endpoint { 4513 }; 4514 }; 4515 }; 4516 4517 dsi_opp_table: opp-table { 4518 compatible = "operating-points-v2"; 4519 4520 opp-187500000 { 4521 opp-hz = /bits/ 64 <187500000>; 4522 required-opps = <&rpmhpd_opp_low_svs>; 4523 }; 4524 4525 opp-300000000 { 4526 opp-hz = /bits/ 64 <300000000>; 4527 required-opps = <&rpmhpd_opp_svs>; 4528 }; 4529 4530 opp-358000000 { 4531 opp-hz = /bits/ 64 <358000000>; 4532 required-opps = <&rpmhpd_opp_svs_l1>; 4533 }; 4534 }; 4535 }; 4536 4537 mdss_dsi_phy: phy@ae94400 { 4538 compatible = "qcom,sc7280-dsi-phy-7nm"; 4539 reg = <0 0x0ae94400 0 0x200>, 4540 <0 0x0ae94600 0 0x280>, 4541 <0 0x0ae94900 0 0x280>; 4542 reg-names = "dsi_phy", 4543 "dsi_phy_lane", 4544 "dsi_pll"; 4545 4546 #clock-cells = <1>; 4547 #phy-cells = <0>; 4548 4549 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4550 <&rpmhcc RPMH_CXO_CLK>; 4551 clock-names = "iface", "ref"; 4552 4553 status = "disabled"; 4554 }; 4555 4556 mdss_edp: edp@aea0000 { 4557 compatible = "qcom,sc7280-edp"; 4558 pinctrl-names = "default"; 4559 pinctrl-0 = <&edp_hot_plug_det>; 4560 4561 reg = <0 0x0aea0000 0 0x200>, 4562 <0 0x0aea0200 0 0x200>, 4563 <0 0x0aea0400 0 0xc00>, 4564 <0 0x0aea1000 0 0x400>; 4565 4566 interrupt-parent = <&mdss>; 4567 interrupts = <14>; 4568 4569 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4570 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 4571 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 4572 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 4573 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 4574 clock-names = "core_iface", 4575 "core_aux", 4576 "ctrl_link", 4577 "ctrl_link_iface", 4578 "stream_pixel"; 4579 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 4580 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 4581 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 4582 4583 phys = <&mdss_edp_phy>; 4584 phy-names = "dp"; 4585 4586 operating-points-v2 = <&edp_opp_table>; 4587 power-domains = <&rpmhpd SC7280_CX>; 4588 4589 status = "disabled"; 4590 4591 ports { 4592 #address-cells = <1>; 4593 #size-cells = <0>; 4594 4595 port@0 { 4596 reg = <0>; 4597 edp_in: endpoint { 4598 remote-endpoint = <&dpu_intf5_out>; 4599 }; 4600 }; 4601 4602 port@1 { 4603 reg = <1>; 4604 mdss_edp_out: endpoint { }; 4605 }; 4606 }; 4607 4608 edp_opp_table: opp-table { 4609 compatible = "operating-points-v2"; 4610 4611 opp-160000000 { 4612 opp-hz = /bits/ 64 <160000000>; 4613 required-opps = <&rpmhpd_opp_low_svs>; 4614 }; 4615 4616 opp-270000000 { 4617 opp-hz = /bits/ 64 <270000000>; 4618 required-opps = <&rpmhpd_opp_svs>; 4619 }; 4620 4621 opp-540000000 { 4622 opp-hz = /bits/ 64 <540000000>; 4623 required-opps = <&rpmhpd_opp_nom>; 4624 }; 4625 4626 opp-810000000 { 4627 opp-hz = /bits/ 64 <810000000>; 4628 required-opps = <&rpmhpd_opp_nom>; 4629 }; 4630 }; 4631 }; 4632 4633 mdss_edp_phy: phy@aec2a00 { 4634 compatible = "qcom,sc7280-edp-phy"; 4635 4636 reg = <0 0x0aec2a00 0 0x19c>, 4637 <0 0x0aec2200 0 0xa0>, 4638 <0 0x0aec2600 0 0xa0>, 4639 <0 0x0aec2000 0 0x1c0>; 4640 4641 clocks = <&rpmhcc RPMH_CXO_CLK>, 4642 <&gcc GCC_EDP_CLKREF_EN>; 4643 clock-names = "aux", 4644 "cfg_ahb"; 4645 4646 #clock-cells = <1>; 4647 #phy-cells = <0>; 4648 4649 status = "disabled"; 4650 }; 4651 4652 mdss_dp: displayport-controller@ae90000 { 4653 compatible = "qcom,sc7280-dp"; 4654 4655 reg = <0 0x0ae90000 0 0x200>, 4656 <0 0x0ae90200 0 0x200>, 4657 <0 0x0ae90400 0 0xc00>, 4658 <0 0x0ae91000 0 0x400>, 4659 <0 0x0ae91400 0 0x400>; 4660 4661 interrupt-parent = <&mdss>; 4662 interrupts = <12>; 4663 4664 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4665 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4666 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4667 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4668 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4669 clock-names = "core_iface", 4670 "core_aux", 4671 "ctrl_link", 4672 "ctrl_link_iface", 4673 "stream_pixel"; 4674 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4675 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4676 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4677 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4678 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 4679 phy-names = "dp"; 4680 4681 operating-points-v2 = <&dp_opp_table>; 4682 power-domains = <&rpmhpd SC7280_CX>; 4683 4684 #sound-dai-cells = <0>; 4685 4686 status = "disabled"; 4687 4688 ports { 4689 #address-cells = <1>; 4690 #size-cells = <0>; 4691 4692 port@0 { 4693 reg = <0>; 4694 dp_in: endpoint { 4695 remote-endpoint = <&dpu_intf0_out>; 4696 }; 4697 }; 4698 4699 port@1 { 4700 reg = <1>; 4701 mdss_dp_out: endpoint { }; 4702 }; 4703 }; 4704 4705 dp_opp_table: opp-table { 4706 compatible = "operating-points-v2"; 4707 4708 opp-160000000 { 4709 opp-hz = /bits/ 64 <160000000>; 4710 required-opps = <&rpmhpd_opp_low_svs>; 4711 }; 4712 4713 opp-270000000 { 4714 opp-hz = /bits/ 64 <270000000>; 4715 required-opps = <&rpmhpd_opp_svs>; 4716 }; 4717 4718 opp-540000000 { 4719 opp-hz = /bits/ 64 <540000000>; 4720 required-opps = <&rpmhpd_opp_svs_l1>; 4721 }; 4722 4723 opp-810000000 { 4724 opp-hz = /bits/ 64 <810000000>; 4725 required-opps = <&rpmhpd_opp_nom>; 4726 }; 4727 }; 4728 }; 4729 }; 4730 4731 pdc: interrupt-controller@b220000 { 4732 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 4733 reg = <0 0x0b220000 0 0x30000>; 4734 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 4735 <55 306 4>, <59 312 3>, <62 374 2>, 4736 <64 434 2>, <66 438 3>, <69 86 1>, 4737 <70 520 54>, <124 609 31>, <155 63 1>, 4738 <156 716 12>; 4739 #interrupt-cells = <2>; 4740 interrupt-parent = <&intc>; 4741 interrupt-controller; 4742 }; 4743 4744 pdc_reset: reset-controller@b5e0000 { 4745 compatible = "qcom,sc7280-pdc-global"; 4746 reg = <0 0x0b5e0000 0 0x20000>; 4747 #reset-cells = <1>; 4748 status = "reserved"; /* Owned by firmware */ 4749 }; 4750 4751 tsens0: thermal-sensor@c263000 { 4752 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4753 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4754 <0 0x0c222000 0 0x1ff>; /* SROT */ 4755 #qcom,sensors = <15>; 4756 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4757 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4758 interrupt-names = "uplow","critical"; 4759 #thermal-sensor-cells = <1>; 4760 }; 4761 4762 tsens1: thermal-sensor@c265000 { 4763 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4764 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4765 <0 0x0c223000 0 0x1ff>; /* SROT */ 4766 #qcom,sensors = <12>; 4767 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4768 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4769 interrupt-names = "uplow","critical"; 4770 #thermal-sensor-cells = <1>; 4771 }; 4772 4773 aoss_reset: reset-controller@c2a0000 { 4774 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 4775 reg = <0 0x0c2a0000 0 0x31000>; 4776 #reset-cells = <1>; 4777 }; 4778 4779 aoss_qmp: power-management@c300000 { 4780 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 4781 reg = <0 0x0c300000 0 0x400>; 4782 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4783 IPCC_MPROC_SIGNAL_GLINK_QMP 4784 IRQ_TYPE_EDGE_RISING>; 4785 mboxes = <&ipcc IPCC_CLIENT_AOP 4786 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4787 4788 #clock-cells = <0>; 4789 }; 4790 4791 sram@c3f0000 { 4792 compatible = "qcom,rpmh-stats"; 4793 reg = <0 0x0c3f0000 0 0x400>; 4794 }; 4795 4796 spmi_bus: spmi@c440000 { 4797 compatible = "qcom,spmi-pmic-arb"; 4798 reg = <0 0x0c440000 0 0x1100>, 4799 <0 0x0c600000 0 0x2000000>, 4800 <0 0x0e600000 0 0x100000>, 4801 <0 0x0e700000 0 0xa0000>, 4802 <0 0x0c40a000 0 0x26000>; 4803 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4804 interrupt-names = "periph_irq"; 4805 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4806 qcom,ee = <0>; 4807 qcom,channel = <0>; 4808 #address-cells = <2>; 4809 #size-cells = <0>; 4810 interrupt-controller; 4811 #interrupt-cells = <4>; 4812 }; 4813 4814 tlmm: pinctrl@f100000 { 4815 compatible = "qcom,sc7280-pinctrl"; 4816 reg = <0 0x0f100000 0 0x300000>; 4817 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4818 gpio-controller; 4819 #gpio-cells = <2>; 4820 interrupt-controller; 4821 #interrupt-cells = <2>; 4822 gpio-ranges = <&tlmm 0 0 175>; 4823 wakeup-parent = <&pdc>; 4824 4825 cci0_default: cci0-default-state { 4826 pins = "gpio69", "gpio70"; 4827 function = "cci_i2c"; 4828 drive-strength = <2>; 4829 bias-pull-up; 4830 }; 4831 4832 cci0_sleep: cci0-sleep-state { 4833 pins = "gpio69", "gpio70"; 4834 function = "cci_i2c"; 4835 drive-strength = <2>; 4836 bias-pull-down; 4837 }; 4838 4839 cci1_default: cci1-default-state { 4840 pins = "gpio71", "gpio72"; 4841 function = "cci_i2c"; 4842 drive-strength = <2>; 4843 bias-pull-up; 4844 }; 4845 4846 cci1_sleep: cci1-sleep-state { 4847 pins = "gpio71", "gpio72"; 4848 function = "cci_i2c"; 4849 drive-strength = <2>; 4850 bias-pull-down; 4851 }; 4852 4853 cci2_default: cci2-default-state { 4854 pins = "gpio73", "gpio74"; 4855 function = "cci_i2c"; 4856 drive-strength = <2>; 4857 bias-pull-up; 4858 }; 4859 4860 cci2_sleep: cci2-sleep-state { 4861 pins = "gpio73", "gpio74"; 4862 function = "cci_i2c"; 4863 drive-strength = <2>; 4864 bias-pull-down; 4865 }; 4866 4867 cci3_default: cci3-default-state { 4868 pins = "gpio75", "gpio76"; 4869 function = "cci_i2c"; 4870 drive-strength = <2>; 4871 bias-pull-up; 4872 }; 4873 4874 cci3_sleep: cci3-sleep-state { 4875 pins = "gpio75", "gpio76"; 4876 function = "cci_i2c"; 4877 drive-strength = <2>; 4878 bias-pull-down; 4879 }; 4880 4881 dp_hot_plug_det: dp-hot-plug-det-state { 4882 pins = "gpio47"; 4883 function = "dp_hot"; 4884 }; 4885 4886 edp_hot_plug_det: edp-hot-plug-det-state { 4887 pins = "gpio60"; 4888 function = "edp_hot"; 4889 }; 4890 4891 mi2s0_data0: mi2s0-data0-state { 4892 pins = "gpio98"; 4893 function = "mi2s0_data0"; 4894 }; 4895 4896 mi2s0_data1: mi2s0-data1-state { 4897 pins = "gpio99"; 4898 function = "mi2s0_data1"; 4899 }; 4900 4901 mi2s0_mclk: mi2s0-mclk-state { 4902 pins = "gpio96"; 4903 function = "pri_mi2s"; 4904 }; 4905 4906 mi2s0_sclk: mi2s0-sclk-state { 4907 pins = "gpio97"; 4908 function = "mi2s0_sck"; 4909 }; 4910 4911 mi2s0_ws: mi2s0-ws-state { 4912 pins = "gpio100"; 4913 function = "mi2s0_ws"; 4914 }; 4915 4916 mi2s1_data0: mi2s1-data0-state { 4917 pins = "gpio107"; 4918 function = "mi2s1_data0"; 4919 }; 4920 4921 mi2s1_sclk: mi2s1-sclk-state { 4922 pins = "gpio106"; 4923 function = "mi2s1_sck"; 4924 }; 4925 4926 mi2s1_ws: mi2s1-ws-state { 4927 pins = "gpio108"; 4928 function = "mi2s1_ws"; 4929 }; 4930 4931 pcie1_clkreq_n: pcie1-clkreq-n-state { 4932 pins = "gpio79"; 4933 function = "pcie1_clkreqn"; 4934 }; 4935 4936 qspi_clk: qspi-clk-state { 4937 pins = "gpio14"; 4938 function = "qspi_clk"; 4939 }; 4940 4941 qspi_cs0: qspi-cs0-state { 4942 pins = "gpio15"; 4943 function = "qspi_cs"; 4944 }; 4945 4946 qspi_cs1: qspi-cs1-state { 4947 pins = "gpio19"; 4948 function = "qspi_cs"; 4949 }; 4950 4951 qspi_data0: qspi-data0-state { 4952 pins = "gpio12"; 4953 function = "qspi_data"; 4954 }; 4955 4956 qspi_data1: qspi-data1-state { 4957 pins = "gpio13"; 4958 function = "qspi_data"; 4959 }; 4960 4961 qspi_data23: qspi-data23-state { 4962 pins = "gpio16", "gpio17"; 4963 function = "qspi_data"; 4964 }; 4965 4966 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4967 pins = "gpio0", "gpio1"; 4968 function = "qup00"; 4969 }; 4970 4971 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4972 pins = "gpio4", "gpio5"; 4973 function = "qup01"; 4974 }; 4975 4976 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4977 pins = "gpio8", "gpio9"; 4978 function = "qup02"; 4979 }; 4980 4981 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4982 pins = "gpio12", "gpio13"; 4983 function = "qup03"; 4984 }; 4985 4986 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4987 pins = "gpio16", "gpio17"; 4988 function = "qup04"; 4989 }; 4990 4991 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4992 pins = "gpio20", "gpio21"; 4993 function = "qup05"; 4994 }; 4995 4996 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4997 pins = "gpio24", "gpio25"; 4998 function = "qup06"; 4999 }; 5000 5001 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 5002 pins = "gpio28", "gpio29"; 5003 function = "qup07"; 5004 }; 5005 5006 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 5007 pins = "gpio32", "gpio33"; 5008 function = "qup10"; 5009 }; 5010 5011 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 5012 pins = "gpio36", "gpio37"; 5013 function = "qup11"; 5014 }; 5015 5016 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 5017 pins = "gpio40", "gpio41"; 5018 function = "qup12"; 5019 }; 5020 5021 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 5022 pins = "gpio44", "gpio45"; 5023 function = "qup13"; 5024 }; 5025 5026 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 5027 pins = "gpio48", "gpio49"; 5028 function = "qup14"; 5029 }; 5030 5031 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 5032 pins = "gpio52", "gpio53"; 5033 function = "qup15"; 5034 }; 5035 5036 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 5037 pins = "gpio56", "gpio57"; 5038 function = "qup16"; 5039 }; 5040 5041 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 5042 pins = "gpio60", "gpio61"; 5043 function = "qup17"; 5044 }; 5045 5046 qup_spi0_data_clk: qup-spi0-data-clk-state { 5047 pins = "gpio0", "gpio1", "gpio2"; 5048 function = "qup00"; 5049 }; 5050 5051 qup_spi0_cs: qup-spi0-cs-state { 5052 pins = "gpio3"; 5053 function = "qup00"; 5054 }; 5055 5056 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 5057 pins = "gpio3"; 5058 function = "gpio"; 5059 }; 5060 5061 qup_spi1_data_clk: qup-spi1-data-clk-state { 5062 pins = "gpio4", "gpio5", "gpio6"; 5063 function = "qup01"; 5064 }; 5065 5066 qup_spi1_cs: qup-spi1-cs-state { 5067 pins = "gpio7"; 5068 function = "qup01"; 5069 }; 5070 5071 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 5072 pins = "gpio7"; 5073 function = "gpio"; 5074 }; 5075 5076 qup_spi2_data_clk: qup-spi2-data-clk-state { 5077 pins = "gpio8", "gpio9", "gpio10"; 5078 function = "qup02"; 5079 }; 5080 5081 qup_spi2_cs: qup-spi2-cs-state { 5082 pins = "gpio11"; 5083 function = "qup02"; 5084 }; 5085 5086 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 5087 pins = "gpio11"; 5088 function = "gpio"; 5089 }; 5090 5091 qup_spi3_data_clk: qup-spi3-data-clk-state { 5092 pins = "gpio12", "gpio13", "gpio14"; 5093 function = "qup03"; 5094 }; 5095 5096 qup_spi3_cs: qup-spi3-cs-state { 5097 pins = "gpio15"; 5098 function = "qup03"; 5099 }; 5100 5101 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 5102 pins = "gpio15"; 5103 function = "gpio"; 5104 }; 5105 5106 qup_spi4_data_clk: qup-spi4-data-clk-state { 5107 pins = "gpio16", "gpio17", "gpio18"; 5108 function = "qup04"; 5109 }; 5110 5111 qup_spi4_cs: qup-spi4-cs-state { 5112 pins = "gpio19"; 5113 function = "qup04"; 5114 }; 5115 5116 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 5117 pins = "gpio19"; 5118 function = "gpio"; 5119 }; 5120 5121 qup_spi5_data_clk: qup-spi5-data-clk-state { 5122 pins = "gpio20", "gpio21", "gpio22"; 5123 function = "qup05"; 5124 }; 5125 5126 qup_spi5_cs: qup-spi5-cs-state { 5127 pins = "gpio23"; 5128 function = "qup05"; 5129 }; 5130 5131 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 5132 pins = "gpio23"; 5133 function = "gpio"; 5134 }; 5135 5136 qup_spi6_data_clk: qup-spi6-data-clk-state { 5137 pins = "gpio24", "gpio25", "gpio26"; 5138 function = "qup06"; 5139 }; 5140 5141 qup_spi6_cs: qup-spi6-cs-state { 5142 pins = "gpio27"; 5143 function = "qup06"; 5144 }; 5145 5146 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 5147 pins = "gpio27"; 5148 function = "gpio"; 5149 }; 5150 5151 qup_spi7_data_clk: qup-spi7-data-clk-state { 5152 pins = "gpio28", "gpio29", "gpio30"; 5153 function = "qup07"; 5154 }; 5155 5156 qup_spi7_cs: qup-spi7-cs-state { 5157 pins = "gpio31"; 5158 function = "qup07"; 5159 }; 5160 5161 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 5162 pins = "gpio31"; 5163 function = "gpio"; 5164 }; 5165 5166 qup_spi8_data_clk: qup-spi8-data-clk-state { 5167 pins = "gpio32", "gpio33", "gpio34"; 5168 function = "qup10"; 5169 }; 5170 5171 qup_spi8_cs: qup-spi8-cs-state { 5172 pins = "gpio35"; 5173 function = "qup10"; 5174 }; 5175 5176 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 5177 pins = "gpio35"; 5178 function = "gpio"; 5179 }; 5180 5181 qup_spi9_data_clk: qup-spi9-data-clk-state { 5182 pins = "gpio36", "gpio37", "gpio38"; 5183 function = "qup11"; 5184 }; 5185 5186 qup_spi9_cs: qup-spi9-cs-state { 5187 pins = "gpio39"; 5188 function = "qup11"; 5189 }; 5190 5191 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 5192 pins = "gpio39"; 5193 function = "gpio"; 5194 }; 5195 5196 qup_spi10_data_clk: qup-spi10-data-clk-state { 5197 pins = "gpio40", "gpio41", "gpio42"; 5198 function = "qup12"; 5199 }; 5200 5201 qup_spi10_cs: qup-spi10-cs-state { 5202 pins = "gpio43"; 5203 function = "qup12"; 5204 }; 5205 5206 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 5207 pins = "gpio43"; 5208 function = "gpio"; 5209 }; 5210 5211 qup_spi11_data_clk: qup-spi11-data-clk-state { 5212 pins = "gpio44", "gpio45", "gpio46"; 5213 function = "qup13"; 5214 }; 5215 5216 qup_spi11_cs: qup-spi11-cs-state { 5217 pins = "gpio47"; 5218 function = "qup13"; 5219 }; 5220 5221 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 5222 pins = "gpio47"; 5223 function = "gpio"; 5224 }; 5225 5226 qup_spi12_data_clk: qup-spi12-data-clk-state { 5227 pins = "gpio48", "gpio49", "gpio50"; 5228 function = "qup14"; 5229 }; 5230 5231 qup_spi12_cs: qup-spi12-cs-state { 5232 pins = "gpio51"; 5233 function = "qup14"; 5234 }; 5235 5236 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 5237 pins = "gpio51"; 5238 function = "gpio"; 5239 }; 5240 5241 qup_spi13_data_clk: qup-spi13-data-clk-state { 5242 pins = "gpio52", "gpio53", "gpio54"; 5243 function = "qup15"; 5244 }; 5245 5246 qup_spi13_cs: qup-spi13-cs-state { 5247 pins = "gpio55"; 5248 function = "qup15"; 5249 }; 5250 5251 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 5252 pins = "gpio55"; 5253 function = "gpio"; 5254 }; 5255 5256 qup_spi14_data_clk: qup-spi14-data-clk-state { 5257 pins = "gpio56", "gpio57", "gpio58"; 5258 function = "qup16"; 5259 }; 5260 5261 qup_spi14_cs: qup-spi14-cs-state { 5262 pins = "gpio59"; 5263 function = "qup16"; 5264 }; 5265 5266 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 5267 pins = "gpio59"; 5268 function = "gpio"; 5269 }; 5270 5271 qup_spi15_data_clk: qup-spi15-data-clk-state { 5272 pins = "gpio60", "gpio61", "gpio62"; 5273 function = "qup17"; 5274 }; 5275 5276 qup_spi15_cs: qup-spi15-cs-state { 5277 pins = "gpio63"; 5278 function = "qup17"; 5279 }; 5280 5281 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 5282 pins = "gpio63"; 5283 function = "gpio"; 5284 }; 5285 5286 qup_uart0_cts: qup-uart0-cts-state { 5287 pins = "gpio0"; 5288 function = "qup00"; 5289 }; 5290 5291 qup_uart0_rts: qup-uart0-rts-state { 5292 pins = "gpio1"; 5293 function = "qup00"; 5294 }; 5295 5296 qup_uart0_tx: qup-uart0-tx-state { 5297 pins = "gpio2"; 5298 function = "qup00"; 5299 }; 5300 5301 qup_uart0_rx: qup-uart0-rx-state { 5302 pins = "gpio3"; 5303 function = "qup00"; 5304 }; 5305 5306 qup_uart1_cts: qup-uart1-cts-state { 5307 pins = "gpio4"; 5308 function = "qup01"; 5309 }; 5310 5311 qup_uart1_rts: qup-uart1-rts-state { 5312 pins = "gpio5"; 5313 function = "qup01"; 5314 }; 5315 5316 qup_uart1_tx: qup-uart1-tx-state { 5317 pins = "gpio6"; 5318 function = "qup01"; 5319 }; 5320 5321 qup_uart1_rx: qup-uart1-rx-state { 5322 pins = "gpio7"; 5323 function = "qup01"; 5324 }; 5325 5326 qup_uart2_cts: qup-uart2-cts-state { 5327 pins = "gpio8"; 5328 function = "qup02"; 5329 }; 5330 5331 qup_uart2_rts: qup-uart2-rts-state { 5332 pins = "gpio9"; 5333 function = "qup02"; 5334 }; 5335 5336 qup_uart2_tx: qup-uart2-tx-state { 5337 pins = "gpio10"; 5338 function = "qup02"; 5339 }; 5340 5341 qup_uart2_rx: qup-uart2-rx-state { 5342 pins = "gpio11"; 5343 function = "qup02"; 5344 }; 5345 5346 qup_uart3_cts: qup-uart3-cts-state { 5347 pins = "gpio12"; 5348 function = "qup03"; 5349 }; 5350 5351 qup_uart3_rts: qup-uart3-rts-state { 5352 pins = "gpio13"; 5353 function = "qup03"; 5354 }; 5355 5356 qup_uart3_tx: qup-uart3-tx-state { 5357 pins = "gpio14"; 5358 function = "qup03"; 5359 }; 5360 5361 qup_uart3_rx: qup-uart3-rx-state { 5362 pins = "gpio15"; 5363 function = "qup03"; 5364 }; 5365 5366 qup_uart4_cts: qup-uart4-cts-state { 5367 pins = "gpio16"; 5368 function = "qup04"; 5369 }; 5370 5371 qup_uart4_rts: qup-uart4-rts-state { 5372 pins = "gpio17"; 5373 function = "qup04"; 5374 }; 5375 5376 qup_uart4_tx: qup-uart4-tx-state { 5377 pins = "gpio18"; 5378 function = "qup04"; 5379 }; 5380 5381 qup_uart4_rx: qup-uart4-rx-state { 5382 pins = "gpio19"; 5383 function = "qup04"; 5384 }; 5385 5386 qup_uart5_cts: qup-uart5-cts-state { 5387 pins = "gpio20"; 5388 function = "qup05"; 5389 }; 5390 5391 qup_uart5_rts: qup-uart5-rts-state { 5392 pins = "gpio21"; 5393 function = "qup05"; 5394 }; 5395 5396 qup_uart5_tx: qup-uart5-tx-state { 5397 pins = "gpio22"; 5398 function = "qup05"; 5399 }; 5400 5401 qup_uart5_rx: qup-uart5-rx-state { 5402 pins = "gpio23"; 5403 function = "qup05"; 5404 }; 5405 5406 qup_uart6_cts: qup-uart6-cts-state { 5407 pins = "gpio24"; 5408 function = "qup06"; 5409 }; 5410 5411 qup_uart6_rts: qup-uart6-rts-state { 5412 pins = "gpio25"; 5413 function = "qup06"; 5414 }; 5415 5416 qup_uart6_tx: qup-uart6-tx-state { 5417 pins = "gpio26"; 5418 function = "qup06"; 5419 }; 5420 5421 qup_uart6_rx: qup-uart6-rx-state { 5422 pins = "gpio27"; 5423 function = "qup06"; 5424 }; 5425 5426 qup_uart7_cts: qup-uart7-cts-state { 5427 pins = "gpio28"; 5428 function = "qup07"; 5429 }; 5430 5431 qup_uart7_rts: qup-uart7-rts-state { 5432 pins = "gpio29"; 5433 function = "qup07"; 5434 }; 5435 5436 qup_uart7_tx: qup-uart7-tx-state { 5437 pins = "gpio30"; 5438 function = "qup07"; 5439 }; 5440 5441 qup_uart7_rx: qup-uart7-rx-state { 5442 pins = "gpio31"; 5443 function = "qup07"; 5444 }; 5445 5446 qup_uart8_cts: qup-uart8-cts-state { 5447 pins = "gpio32"; 5448 function = "qup10"; 5449 }; 5450 5451 qup_uart8_rts: qup-uart8-rts-state { 5452 pins = "gpio33"; 5453 function = "qup10"; 5454 }; 5455 5456 qup_uart8_tx: qup-uart8-tx-state { 5457 pins = "gpio34"; 5458 function = "qup10"; 5459 }; 5460 5461 qup_uart8_rx: qup-uart8-rx-state { 5462 pins = "gpio35"; 5463 function = "qup10"; 5464 }; 5465 5466 qup_uart9_cts: qup-uart9-cts-state { 5467 pins = "gpio36"; 5468 function = "qup11"; 5469 }; 5470 5471 qup_uart9_rts: qup-uart9-rts-state { 5472 pins = "gpio37"; 5473 function = "qup11"; 5474 }; 5475 5476 qup_uart9_tx: qup-uart9-tx-state { 5477 pins = "gpio38"; 5478 function = "qup11"; 5479 }; 5480 5481 qup_uart9_rx: qup-uart9-rx-state { 5482 pins = "gpio39"; 5483 function = "qup11"; 5484 }; 5485 5486 qup_uart10_cts: qup-uart10-cts-state { 5487 pins = "gpio40"; 5488 function = "qup12"; 5489 }; 5490 5491 qup_uart10_rts: qup-uart10-rts-state { 5492 pins = "gpio41"; 5493 function = "qup12"; 5494 }; 5495 5496 qup_uart10_tx: qup-uart10-tx-state { 5497 pins = "gpio42"; 5498 function = "qup12"; 5499 }; 5500 5501 qup_uart10_rx: qup-uart10-rx-state { 5502 pins = "gpio43"; 5503 function = "qup12"; 5504 }; 5505 5506 qup_uart11_cts: qup-uart11-cts-state { 5507 pins = "gpio44"; 5508 function = "qup13"; 5509 }; 5510 5511 qup_uart11_rts: qup-uart11-rts-state { 5512 pins = "gpio45"; 5513 function = "qup13"; 5514 }; 5515 5516 qup_uart11_tx: qup-uart11-tx-state { 5517 pins = "gpio46"; 5518 function = "qup13"; 5519 }; 5520 5521 qup_uart11_rx: qup-uart11-rx-state { 5522 pins = "gpio47"; 5523 function = "qup13"; 5524 }; 5525 5526 qup_uart12_cts: qup-uart12-cts-state { 5527 pins = "gpio48"; 5528 function = "qup14"; 5529 }; 5530 5531 qup_uart12_rts: qup-uart12-rts-state { 5532 pins = "gpio49"; 5533 function = "qup14"; 5534 }; 5535 5536 qup_uart12_tx: qup-uart12-tx-state { 5537 pins = "gpio50"; 5538 function = "qup14"; 5539 }; 5540 5541 qup_uart12_rx: qup-uart12-rx-state { 5542 pins = "gpio51"; 5543 function = "qup14"; 5544 }; 5545 5546 qup_uart13_cts: qup-uart13-cts-state { 5547 pins = "gpio52"; 5548 function = "qup15"; 5549 }; 5550 5551 qup_uart13_rts: qup-uart13-rts-state { 5552 pins = "gpio53"; 5553 function = "qup15"; 5554 }; 5555 5556 qup_uart13_tx: qup-uart13-tx-state { 5557 pins = "gpio54"; 5558 function = "qup15"; 5559 }; 5560 5561 qup_uart13_rx: qup-uart13-rx-state { 5562 pins = "gpio55"; 5563 function = "qup15"; 5564 }; 5565 5566 qup_uart14_cts: qup-uart14-cts-state { 5567 pins = "gpio56"; 5568 function = "qup16"; 5569 }; 5570 5571 qup_uart14_rts: qup-uart14-rts-state { 5572 pins = "gpio57"; 5573 function = "qup16"; 5574 }; 5575 5576 qup_uart14_tx: qup-uart14-tx-state { 5577 pins = "gpio58"; 5578 function = "qup16"; 5579 }; 5580 5581 qup_uart14_rx: qup-uart14-rx-state { 5582 pins = "gpio59"; 5583 function = "qup16"; 5584 }; 5585 5586 qup_uart15_cts: qup-uart15-cts-state { 5587 pins = "gpio60"; 5588 function = "qup17"; 5589 }; 5590 5591 qup_uart15_rts: qup-uart15-rts-state { 5592 pins = "gpio61"; 5593 function = "qup17"; 5594 }; 5595 5596 qup_uart15_tx: qup-uart15-tx-state { 5597 pins = "gpio62"; 5598 function = "qup17"; 5599 }; 5600 5601 qup_uart15_rx: qup-uart15-rx-state { 5602 pins = "gpio63"; 5603 function = "qup17"; 5604 }; 5605 5606 sdc1_clk: sdc1-clk-state { 5607 pins = "sdc1_clk"; 5608 }; 5609 5610 sdc1_cmd: sdc1-cmd-state { 5611 pins = "sdc1_cmd"; 5612 }; 5613 5614 sdc1_data: sdc1-data-state { 5615 pins = "sdc1_data"; 5616 }; 5617 5618 sdc1_rclk: sdc1-rclk-state { 5619 pins = "sdc1_rclk"; 5620 }; 5621 5622 sdc1_clk_sleep: sdc1-clk-sleep-state { 5623 pins = "sdc1_clk"; 5624 drive-strength = <2>; 5625 bias-bus-hold; 5626 }; 5627 5628 sdc1_cmd_sleep: sdc1-cmd-sleep-state { 5629 pins = "sdc1_cmd"; 5630 drive-strength = <2>; 5631 bias-bus-hold; 5632 }; 5633 5634 sdc1_data_sleep: sdc1-data-sleep-state { 5635 pins = "sdc1_data"; 5636 drive-strength = <2>; 5637 bias-bus-hold; 5638 }; 5639 5640 sdc1_rclk_sleep: sdc1-rclk-sleep-state { 5641 pins = "sdc1_rclk"; 5642 drive-strength = <2>; 5643 bias-bus-hold; 5644 }; 5645 5646 sdc2_clk: sdc2-clk-state { 5647 pins = "sdc2_clk"; 5648 }; 5649 5650 sdc2_cmd: sdc2-cmd-state { 5651 pins = "sdc2_cmd"; 5652 }; 5653 5654 sdc2_data: sdc2-data-state { 5655 pins = "sdc2_data"; 5656 }; 5657 5658 sdc2_clk_sleep: sdc2-clk-sleep-state { 5659 pins = "sdc2_clk"; 5660 drive-strength = <2>; 5661 bias-bus-hold; 5662 }; 5663 5664 sdc2_cmd_sleep: sdc2-cmd-sleep-state { 5665 pins = "sdc2_cmd"; 5666 drive-strength = <2>; 5667 bias-bus-hold; 5668 }; 5669 5670 sdc2_data_sleep: sdc2-data-sleep-state { 5671 pins = "sdc2_data"; 5672 drive-strength = <2>; 5673 bias-bus-hold; 5674 }; 5675 }; 5676 5677 sram@146a5000 { 5678 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 5679 reg = <0 0x146a5000 0 0x6000>; 5680 5681 #address-cells = <1>; 5682 #size-cells = <1>; 5683 5684 ranges = <0 0 0x146a5000 0x6000>; 5685 5686 pil-reloc@594c { 5687 compatible = "qcom,pil-reloc-info"; 5688 reg = <0x594c 0xc8>; 5689 }; 5690 }; 5691 5692 apps_smmu: iommu@15000000 { 5693 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 5694 reg = <0 0x15000000 0 0x100000>; 5695 #iommu-cells = <2>; 5696 #global-interrupts = <1>; 5697 dma-coherent; 5698 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5699 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5700 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5701 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5702 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5703 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5704 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5705 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5706 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5707 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5708 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5709 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5710 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5711 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5712 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5713 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5714 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5715 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5716 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5717 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5718 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5719 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5720 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5721 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5722 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5723 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5724 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5725 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5726 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5727 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5728 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5729 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5730 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5731 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5732 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5733 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5734 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5735 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5736 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5737 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5738 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5739 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5740 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5741 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5742 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5743 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5744 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5745 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5746 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5747 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5748 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5749 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5750 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5751 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5752 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5753 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5754 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5755 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5756 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5757 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5758 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5759 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5760 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5761 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5762 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5763 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5764 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5765 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5766 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5767 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5768 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5769 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5770 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5771 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5772 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5773 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5774 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5775 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5776 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5777 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5778 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 5779 }; 5780 5781 intc: interrupt-controller@17a00000 { 5782 compatible = "arm,gic-v3"; 5783 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5784 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5785 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 5786 #interrupt-cells = <3>; 5787 interrupt-controller; 5788 #address-cells = <2>; 5789 #size-cells = <2>; 5790 ranges; 5791 5792 msi-controller@17a40000 { 5793 compatible = "arm,gic-v3-its"; 5794 reg = <0 0x17a40000 0 0x20000>; 5795 msi-controller; 5796 #msi-cells = <1>; 5797 status = "disabled"; 5798 }; 5799 }; 5800 5801 watchdog: watchdog@17c10000 { 5802 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 5803 reg = <0 0x17c10000 0 0x1000>; 5804 clocks = <&sleep_clk>; 5805 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 5806 status = "reserved"; /* Owned by Gunyah hyp */ 5807 }; 5808 5809 timer@17c20000 { 5810 #address-cells = <1>; 5811 #size-cells = <1>; 5812 ranges = <0 0 0 0x20000000>; 5813 compatible = "arm,armv7-timer-mem"; 5814 reg = <0 0x17c20000 0 0x1000>; 5815 5816 frame@17c21000 { 5817 frame-number = <0>; 5818 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5819 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5820 reg = <0x17c21000 0x1000>, 5821 <0x17c22000 0x1000>; 5822 }; 5823 5824 frame@17c23000 { 5825 frame-number = <1>; 5826 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5827 reg = <0x17c23000 0x1000>; 5828 status = "disabled"; 5829 }; 5830 5831 frame@17c25000 { 5832 frame-number = <2>; 5833 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5834 reg = <0x17c25000 0x1000>; 5835 status = "disabled"; 5836 }; 5837 5838 frame@17c27000 { 5839 frame-number = <3>; 5840 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5841 reg = <0x17c27000 0x1000>; 5842 status = "disabled"; 5843 }; 5844 5845 frame@17c29000 { 5846 frame-number = <4>; 5847 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5848 reg = <0x17c29000 0x1000>; 5849 status = "disabled"; 5850 }; 5851 5852 frame@17c2b000 { 5853 frame-number = <5>; 5854 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5855 reg = <0x17c2b000 0x1000>; 5856 status = "disabled"; 5857 }; 5858 5859 frame@17c2d000 { 5860 frame-number = <6>; 5861 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5862 reg = <0x17c2d000 0x1000>; 5863 status = "disabled"; 5864 }; 5865 }; 5866 5867 apps_rsc: rsc@18200000 { 5868 compatible = "qcom,rpmh-rsc"; 5869 reg = <0 0x18200000 0 0x10000>, 5870 <0 0x18210000 0 0x10000>, 5871 <0 0x18220000 0 0x10000>; 5872 reg-names = "drv-0", "drv-1", "drv-2"; 5873 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5874 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5875 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5876 qcom,tcs-offset = <0xd00>; 5877 qcom,drv-id = <2>; 5878 qcom,tcs-config = <ACTIVE_TCS 2>, 5879 <SLEEP_TCS 3>, 5880 <WAKE_TCS 3>, 5881 <CONTROL_TCS 1>; 5882 power-domains = <&CLUSTER_PD>; 5883 5884 apps_bcm_voter: bcm-voter { 5885 compatible = "qcom,bcm-voter"; 5886 }; 5887 5888 rpmhpd: power-controller { 5889 compatible = "qcom,sc7280-rpmhpd"; 5890 #power-domain-cells = <1>; 5891 operating-points-v2 = <&rpmhpd_opp_table>; 5892 5893 rpmhpd_opp_table: opp-table { 5894 compatible = "operating-points-v2"; 5895 5896 rpmhpd_opp_ret: opp1 { 5897 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5898 }; 5899 5900 rpmhpd_opp_low_svs: opp2 { 5901 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5902 }; 5903 5904 rpmhpd_opp_svs: opp3 { 5905 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5906 }; 5907 5908 rpmhpd_opp_svs_l1: opp4 { 5909 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5910 }; 5911 5912 rpmhpd_opp_svs_l2: opp5 { 5913 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5914 }; 5915 5916 rpmhpd_opp_nom: opp6 { 5917 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5918 }; 5919 5920 rpmhpd_opp_nom_l1: opp7 { 5921 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5922 }; 5923 5924 rpmhpd_opp_turbo: opp8 { 5925 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5926 }; 5927 5928 rpmhpd_opp_turbo_l1: opp9 { 5929 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5930 }; 5931 }; 5932 }; 5933 5934 rpmhcc: clock-controller { 5935 compatible = "qcom,sc7280-rpmh-clk"; 5936 clocks = <&xo_board>; 5937 clock-names = "xo"; 5938 #clock-cells = <1>; 5939 }; 5940 }; 5941 5942 epss_l3: interconnect@18590000 { 5943 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3"; 5944 reg = <0 0x18590000 0 0x1000>; 5945 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5946 clock-names = "xo", "alternate"; 5947 #interconnect-cells = <1>; 5948 }; 5949 5950 cpufreq_hw: cpufreq@18591000 { 5951 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss"; 5952 reg = <0 0x18591000 0 0x1000>, 5953 <0 0x18592000 0 0x1000>, 5954 <0 0x18593000 0 0x1000>; 5955 5956 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 5957 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5958 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 5959 interrupt-names = "dcvsh-irq-0", 5960 "dcvsh-irq-1", 5961 "dcvsh-irq-2"; 5962 5963 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5964 clock-names = "xo", "alternate"; 5965 #freq-domain-cells = <1>; 5966 #clock-cells = <1>; 5967 }; 5968 }; 5969 5970 thermal_zones: thermal-zones { 5971 cpu0-thermal { 5972 polling-delay-passive = <250>; 5973 polling-delay = <0>; 5974 5975 thermal-sensors = <&tsens0 1>; 5976 5977 trips { 5978 cpu0_alert0: trip-point0 { 5979 temperature = <90000>; 5980 hysteresis = <2000>; 5981 type = "passive"; 5982 }; 5983 5984 cpu0_alert1: trip-point1 { 5985 temperature = <95000>; 5986 hysteresis = <2000>; 5987 type = "passive"; 5988 }; 5989 5990 cpu0_crit: cpu-crit { 5991 temperature = <110000>; 5992 hysteresis = <0>; 5993 type = "critical"; 5994 }; 5995 }; 5996 5997 cooling-maps { 5998 map0 { 5999 trip = <&cpu0_alert0>; 6000 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6001 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6002 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6003 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6004 }; 6005 map1 { 6006 trip = <&cpu0_alert1>; 6007 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6008 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6009 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6010 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6011 }; 6012 }; 6013 }; 6014 6015 cpu1-thermal { 6016 polling-delay-passive = <250>; 6017 polling-delay = <0>; 6018 6019 thermal-sensors = <&tsens0 2>; 6020 6021 trips { 6022 cpu1_alert0: trip-point0 { 6023 temperature = <90000>; 6024 hysteresis = <2000>; 6025 type = "passive"; 6026 }; 6027 6028 cpu1_alert1: trip-point1 { 6029 temperature = <95000>; 6030 hysteresis = <2000>; 6031 type = "passive"; 6032 }; 6033 6034 cpu1_crit: cpu-crit { 6035 temperature = <110000>; 6036 hysteresis = <0>; 6037 type = "critical"; 6038 }; 6039 }; 6040 6041 cooling-maps { 6042 map0 { 6043 trip = <&cpu1_alert0>; 6044 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6045 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6046 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6047 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6048 }; 6049 map1 { 6050 trip = <&cpu1_alert1>; 6051 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6052 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6053 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6054 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6055 }; 6056 }; 6057 }; 6058 6059 cpu2-thermal { 6060 polling-delay-passive = <250>; 6061 polling-delay = <0>; 6062 6063 thermal-sensors = <&tsens0 3>; 6064 6065 trips { 6066 cpu2_alert0: trip-point0 { 6067 temperature = <90000>; 6068 hysteresis = <2000>; 6069 type = "passive"; 6070 }; 6071 6072 cpu2_alert1: trip-point1 { 6073 temperature = <95000>; 6074 hysteresis = <2000>; 6075 type = "passive"; 6076 }; 6077 6078 cpu2_crit: cpu-crit { 6079 temperature = <110000>; 6080 hysteresis = <0>; 6081 type = "critical"; 6082 }; 6083 }; 6084 6085 cooling-maps { 6086 map0 { 6087 trip = <&cpu2_alert0>; 6088 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6089 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6090 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6091 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6092 }; 6093 map1 { 6094 trip = <&cpu2_alert1>; 6095 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6096 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6097 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6098 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6099 }; 6100 }; 6101 }; 6102 6103 cpu3-thermal { 6104 polling-delay-passive = <250>; 6105 polling-delay = <0>; 6106 6107 thermal-sensors = <&tsens0 4>; 6108 6109 trips { 6110 cpu3_alert0: trip-point0 { 6111 temperature = <90000>; 6112 hysteresis = <2000>; 6113 type = "passive"; 6114 }; 6115 6116 cpu3_alert1: trip-point1 { 6117 temperature = <95000>; 6118 hysteresis = <2000>; 6119 type = "passive"; 6120 }; 6121 6122 cpu3_crit: cpu-crit { 6123 temperature = <110000>; 6124 hysteresis = <0>; 6125 type = "critical"; 6126 }; 6127 }; 6128 6129 cooling-maps { 6130 map0 { 6131 trip = <&cpu3_alert0>; 6132 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6133 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6134 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6135 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6136 }; 6137 map1 { 6138 trip = <&cpu3_alert1>; 6139 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6140 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6141 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6142 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6143 }; 6144 }; 6145 }; 6146 6147 cpu4-thermal { 6148 polling-delay-passive = <250>; 6149 polling-delay = <0>; 6150 6151 thermal-sensors = <&tsens0 7>; 6152 6153 trips { 6154 cpu4_alert0: trip-point0 { 6155 temperature = <90000>; 6156 hysteresis = <2000>; 6157 type = "passive"; 6158 }; 6159 6160 cpu4_alert1: trip-point1 { 6161 temperature = <95000>; 6162 hysteresis = <2000>; 6163 type = "passive"; 6164 }; 6165 6166 cpu4_crit: cpu-crit { 6167 temperature = <110000>; 6168 hysteresis = <0>; 6169 type = "critical"; 6170 }; 6171 }; 6172 6173 cooling-maps { 6174 map0 { 6175 trip = <&cpu4_alert0>; 6176 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6177 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6178 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6179 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6180 }; 6181 map1 { 6182 trip = <&cpu4_alert1>; 6183 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6184 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6185 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6186 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6187 }; 6188 }; 6189 }; 6190 6191 cpu5-thermal { 6192 polling-delay-passive = <250>; 6193 polling-delay = <0>; 6194 6195 thermal-sensors = <&tsens0 8>; 6196 6197 trips { 6198 cpu5_alert0: trip-point0 { 6199 temperature = <90000>; 6200 hysteresis = <2000>; 6201 type = "passive"; 6202 }; 6203 6204 cpu5_alert1: trip-point1 { 6205 temperature = <95000>; 6206 hysteresis = <2000>; 6207 type = "passive"; 6208 }; 6209 6210 cpu5_crit: cpu-crit { 6211 temperature = <110000>; 6212 hysteresis = <0>; 6213 type = "critical"; 6214 }; 6215 }; 6216 6217 cooling-maps { 6218 map0 { 6219 trip = <&cpu5_alert0>; 6220 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6221 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6222 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6223 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6224 }; 6225 map1 { 6226 trip = <&cpu5_alert1>; 6227 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6228 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6229 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6230 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6231 }; 6232 }; 6233 }; 6234 6235 cpu6-thermal { 6236 polling-delay-passive = <250>; 6237 polling-delay = <0>; 6238 6239 thermal-sensors = <&tsens0 9>; 6240 6241 trips { 6242 cpu6_alert0: trip-point0 { 6243 temperature = <90000>; 6244 hysteresis = <2000>; 6245 type = "passive"; 6246 }; 6247 6248 cpu6_alert1: trip-point1 { 6249 temperature = <95000>; 6250 hysteresis = <2000>; 6251 type = "passive"; 6252 }; 6253 6254 cpu6_crit: cpu-crit { 6255 temperature = <110000>; 6256 hysteresis = <0>; 6257 type = "critical"; 6258 }; 6259 }; 6260 6261 cooling-maps { 6262 map0 { 6263 trip = <&cpu6_alert0>; 6264 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6265 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6266 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6267 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6268 }; 6269 map1 { 6270 trip = <&cpu6_alert1>; 6271 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6272 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6273 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6274 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6275 }; 6276 }; 6277 }; 6278 6279 cpu7-thermal { 6280 polling-delay-passive = <250>; 6281 polling-delay = <0>; 6282 6283 thermal-sensors = <&tsens0 10>; 6284 6285 trips { 6286 cpu7_alert0: trip-point0 { 6287 temperature = <90000>; 6288 hysteresis = <2000>; 6289 type = "passive"; 6290 }; 6291 6292 cpu7_alert1: trip-point1 { 6293 temperature = <95000>; 6294 hysteresis = <2000>; 6295 type = "passive"; 6296 }; 6297 6298 cpu7_crit: cpu-crit { 6299 temperature = <110000>; 6300 hysteresis = <0>; 6301 type = "critical"; 6302 }; 6303 }; 6304 6305 cooling-maps { 6306 map0 { 6307 trip = <&cpu7_alert0>; 6308 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6309 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6310 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6311 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6312 }; 6313 map1 { 6314 trip = <&cpu7_alert1>; 6315 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6316 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6317 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6318 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6319 }; 6320 }; 6321 }; 6322 6323 cpu8-thermal { 6324 polling-delay-passive = <250>; 6325 polling-delay = <0>; 6326 6327 thermal-sensors = <&tsens0 11>; 6328 6329 trips { 6330 cpu8_alert0: trip-point0 { 6331 temperature = <90000>; 6332 hysteresis = <2000>; 6333 type = "passive"; 6334 }; 6335 6336 cpu8_alert1: trip-point1 { 6337 temperature = <95000>; 6338 hysteresis = <2000>; 6339 type = "passive"; 6340 }; 6341 6342 cpu8_crit: cpu-crit { 6343 temperature = <110000>; 6344 hysteresis = <0>; 6345 type = "critical"; 6346 }; 6347 }; 6348 6349 cooling-maps { 6350 map0 { 6351 trip = <&cpu8_alert0>; 6352 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6353 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6354 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6355 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6356 }; 6357 map1 { 6358 trip = <&cpu8_alert1>; 6359 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6360 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6361 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6362 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6363 }; 6364 }; 6365 }; 6366 6367 cpu9-thermal { 6368 polling-delay-passive = <250>; 6369 polling-delay = <0>; 6370 6371 thermal-sensors = <&tsens0 12>; 6372 6373 trips { 6374 cpu9_alert0: trip-point0 { 6375 temperature = <90000>; 6376 hysteresis = <2000>; 6377 type = "passive"; 6378 }; 6379 6380 cpu9_alert1: trip-point1 { 6381 temperature = <95000>; 6382 hysteresis = <2000>; 6383 type = "passive"; 6384 }; 6385 6386 cpu9_crit: cpu-crit { 6387 temperature = <110000>; 6388 hysteresis = <0>; 6389 type = "critical"; 6390 }; 6391 }; 6392 6393 cooling-maps { 6394 map0 { 6395 trip = <&cpu9_alert0>; 6396 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6397 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6398 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6399 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6400 }; 6401 map1 { 6402 trip = <&cpu9_alert1>; 6403 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6404 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6405 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6406 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6407 }; 6408 }; 6409 }; 6410 6411 cpu10-thermal { 6412 polling-delay-passive = <250>; 6413 polling-delay = <0>; 6414 6415 thermal-sensors = <&tsens0 13>; 6416 6417 trips { 6418 cpu10_alert0: trip-point0 { 6419 temperature = <90000>; 6420 hysteresis = <2000>; 6421 type = "passive"; 6422 }; 6423 6424 cpu10_alert1: trip-point1 { 6425 temperature = <95000>; 6426 hysteresis = <2000>; 6427 type = "passive"; 6428 }; 6429 6430 cpu10_crit: cpu-crit { 6431 temperature = <110000>; 6432 hysteresis = <0>; 6433 type = "critical"; 6434 }; 6435 }; 6436 6437 cooling-maps { 6438 map0 { 6439 trip = <&cpu10_alert0>; 6440 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6441 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6442 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6443 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6444 }; 6445 map1 { 6446 trip = <&cpu10_alert1>; 6447 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6448 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6449 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6450 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6451 }; 6452 }; 6453 }; 6454 6455 cpu11-thermal { 6456 polling-delay-passive = <250>; 6457 polling-delay = <0>; 6458 6459 thermal-sensors = <&tsens0 14>; 6460 6461 trips { 6462 cpu11_alert0: trip-point0 { 6463 temperature = <90000>; 6464 hysteresis = <2000>; 6465 type = "passive"; 6466 }; 6467 6468 cpu11_alert1: trip-point1 { 6469 temperature = <95000>; 6470 hysteresis = <2000>; 6471 type = "passive"; 6472 }; 6473 6474 cpu11_crit: cpu-crit { 6475 temperature = <110000>; 6476 hysteresis = <0>; 6477 type = "critical"; 6478 }; 6479 }; 6480 6481 cooling-maps { 6482 map0 { 6483 trip = <&cpu11_alert0>; 6484 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6485 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6486 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6487 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6488 }; 6489 map1 { 6490 trip = <&cpu11_alert1>; 6491 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6492 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6493 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6494 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6495 }; 6496 }; 6497 }; 6498 6499 aoss0-thermal { 6500 polling-delay-passive = <0>; 6501 polling-delay = <0>; 6502 6503 thermal-sensors = <&tsens0 0>; 6504 6505 trips { 6506 aoss0_alert0: trip-point0 { 6507 temperature = <90000>; 6508 hysteresis = <2000>; 6509 type = "hot"; 6510 }; 6511 6512 aoss0_crit: aoss0-crit { 6513 temperature = <110000>; 6514 hysteresis = <0>; 6515 type = "critical"; 6516 }; 6517 }; 6518 }; 6519 6520 aoss1-thermal { 6521 polling-delay-passive = <0>; 6522 polling-delay = <0>; 6523 6524 thermal-sensors = <&tsens1 0>; 6525 6526 trips { 6527 aoss1_alert0: trip-point0 { 6528 temperature = <90000>; 6529 hysteresis = <2000>; 6530 type = "hot"; 6531 }; 6532 6533 aoss1_crit: aoss1-crit { 6534 temperature = <110000>; 6535 hysteresis = <0>; 6536 type = "critical"; 6537 }; 6538 }; 6539 }; 6540 6541 cpuss0-thermal { 6542 polling-delay-passive = <0>; 6543 polling-delay = <0>; 6544 6545 thermal-sensors = <&tsens0 5>; 6546 6547 trips { 6548 cpuss0_alert0: trip-point0 { 6549 temperature = <90000>; 6550 hysteresis = <2000>; 6551 type = "hot"; 6552 }; 6553 cpuss0_crit: cluster0-crit { 6554 temperature = <110000>; 6555 hysteresis = <0>; 6556 type = "critical"; 6557 }; 6558 }; 6559 }; 6560 6561 cpuss1-thermal { 6562 polling-delay-passive = <0>; 6563 polling-delay = <0>; 6564 6565 thermal-sensors = <&tsens0 6>; 6566 6567 trips { 6568 cpuss1_alert0: trip-point0 { 6569 temperature = <90000>; 6570 hysteresis = <2000>; 6571 type = "hot"; 6572 }; 6573 cpuss1_crit: cluster0-crit { 6574 temperature = <110000>; 6575 hysteresis = <0>; 6576 type = "critical"; 6577 }; 6578 }; 6579 }; 6580 6581 gpuss0-thermal { 6582 polling-delay-passive = <100>; 6583 polling-delay = <0>; 6584 6585 thermal-sensors = <&tsens1 1>; 6586 6587 trips { 6588 gpuss0_alert0: trip-point0 { 6589 temperature = <95000>; 6590 hysteresis = <2000>; 6591 type = "passive"; 6592 }; 6593 6594 gpuss0_crit: gpuss0-crit { 6595 temperature = <110000>; 6596 hysteresis = <0>; 6597 type = "critical"; 6598 }; 6599 }; 6600 6601 cooling-maps { 6602 map0 { 6603 trip = <&gpuss0_alert0>; 6604 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6605 }; 6606 }; 6607 }; 6608 6609 gpuss1-thermal { 6610 polling-delay-passive = <100>; 6611 polling-delay = <0>; 6612 6613 thermal-sensors = <&tsens1 2>; 6614 6615 trips { 6616 gpuss1_alert0: trip-point0 { 6617 temperature = <95000>; 6618 hysteresis = <2000>; 6619 type = "passive"; 6620 }; 6621 6622 gpuss1_crit: gpuss1-crit { 6623 temperature = <110000>; 6624 hysteresis = <0>; 6625 type = "critical"; 6626 }; 6627 }; 6628 6629 cooling-maps { 6630 map0 { 6631 trip = <&gpuss1_alert0>; 6632 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6633 }; 6634 }; 6635 }; 6636 6637 nspss0-thermal { 6638 polling-delay-passive = <0>; 6639 polling-delay = <0>; 6640 6641 thermal-sensors = <&tsens1 3>; 6642 6643 trips { 6644 nspss0_alert0: trip-point0 { 6645 temperature = <90000>; 6646 hysteresis = <2000>; 6647 type = "hot"; 6648 }; 6649 6650 nspss0_crit: nspss0-crit { 6651 temperature = <110000>; 6652 hysteresis = <0>; 6653 type = "critical"; 6654 }; 6655 }; 6656 }; 6657 6658 nspss1-thermal { 6659 polling-delay-passive = <0>; 6660 polling-delay = <0>; 6661 6662 thermal-sensors = <&tsens1 4>; 6663 6664 trips { 6665 nspss1_alert0: trip-point0 { 6666 temperature = <90000>; 6667 hysteresis = <2000>; 6668 type = "hot"; 6669 }; 6670 6671 nspss1_crit: nspss1-crit { 6672 temperature = <110000>; 6673 hysteresis = <0>; 6674 type = "critical"; 6675 }; 6676 }; 6677 }; 6678 6679 video-thermal { 6680 polling-delay-passive = <0>; 6681 polling-delay = <0>; 6682 6683 thermal-sensors = <&tsens1 5>; 6684 6685 trips { 6686 video_alert0: trip-point0 { 6687 temperature = <90000>; 6688 hysteresis = <2000>; 6689 type = "hot"; 6690 }; 6691 6692 video_crit: video-crit { 6693 temperature = <110000>; 6694 hysteresis = <0>; 6695 type = "critical"; 6696 }; 6697 }; 6698 }; 6699 6700 ddr-thermal { 6701 polling-delay-passive = <0>; 6702 polling-delay = <0>; 6703 6704 thermal-sensors = <&tsens1 6>; 6705 6706 trips { 6707 ddr_alert0: trip-point0 { 6708 temperature = <90000>; 6709 hysteresis = <2000>; 6710 type = "hot"; 6711 }; 6712 6713 ddr_crit: ddr-crit { 6714 temperature = <110000>; 6715 hysteresis = <0>; 6716 type = "critical"; 6717 }; 6718 }; 6719 }; 6720 6721 mdmss0-thermal { 6722 polling-delay-passive = <0>; 6723 polling-delay = <0>; 6724 6725 thermal-sensors = <&tsens1 7>; 6726 6727 trips { 6728 mdmss0_alert0: trip-point0 { 6729 temperature = <90000>; 6730 hysteresis = <2000>; 6731 type = "hot"; 6732 }; 6733 6734 mdmss0_crit: mdmss0-crit { 6735 temperature = <110000>; 6736 hysteresis = <0>; 6737 type = "critical"; 6738 }; 6739 }; 6740 }; 6741 6742 mdmss1-thermal { 6743 polling-delay-passive = <0>; 6744 polling-delay = <0>; 6745 6746 thermal-sensors = <&tsens1 8>; 6747 6748 trips { 6749 mdmss1_alert0: trip-point0 { 6750 temperature = <90000>; 6751 hysteresis = <2000>; 6752 type = "hot"; 6753 }; 6754 6755 mdmss1_crit: mdmss1-crit { 6756 temperature = <110000>; 6757 hysteresis = <0>; 6758 type = "critical"; 6759 }; 6760 }; 6761 }; 6762 6763 mdmss2-thermal { 6764 polling-delay-passive = <0>; 6765 polling-delay = <0>; 6766 6767 thermal-sensors = <&tsens1 9>; 6768 6769 trips { 6770 mdmss2_alert0: trip-point0 { 6771 temperature = <90000>; 6772 hysteresis = <2000>; 6773 type = "hot"; 6774 }; 6775 6776 mdmss2_crit: mdmss2-crit { 6777 temperature = <110000>; 6778 hysteresis = <0>; 6779 type = "critical"; 6780 }; 6781 }; 6782 }; 6783 6784 mdmss3-thermal { 6785 polling-delay-passive = <0>; 6786 polling-delay = <0>; 6787 6788 thermal-sensors = <&tsens1 10>; 6789 6790 trips { 6791 mdmss3_alert0: trip-point0 { 6792 temperature = <90000>; 6793 hysteresis = <2000>; 6794 type = "hot"; 6795 }; 6796 6797 mdmss3_crit: mdmss3-crit { 6798 temperature = <110000>; 6799 hysteresis = <0>; 6800 type = "critical"; 6801 }; 6802 }; 6803 }; 6804 6805 camera0-thermal { 6806 polling-delay-passive = <0>; 6807 polling-delay = <0>; 6808 6809 thermal-sensors = <&tsens1 11>; 6810 6811 trips { 6812 camera0_alert0: trip-point0 { 6813 temperature = <90000>; 6814 hysteresis = <2000>; 6815 type = "hot"; 6816 }; 6817 6818 camera0_crit: camera0-crit { 6819 temperature = <110000>; 6820 hysteresis = <0>; 6821 type = "critical"; 6822 }; 6823 }; 6824 }; 6825 }; 6826 6827 timer { 6828 compatible = "arm,armv8-timer"; 6829 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6830 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6831 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6832 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6833 }; 6834}; 6835