1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,gcc-sc7280.h> 10#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 11#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 13#include <dt-bindings/clock/qcom,rpmh.h> 14#include <dt-bindings/clock/qcom,videocc-sc7280.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/firmware/qcom,scm.h> 17#include <dt-bindings/gpio/gpio.h> 18#include <dt-bindings/interconnect/qcom,icc.h> 19#include <dt-bindings/interconnect/qcom,osm-l3.h> 20#include <dt-bindings/interconnect/qcom,sc7280.h> 21#include <dt-bindings/interrupt-controller/arm-gic.h> 22#include <dt-bindings/mailbox/qcom-ipcc.h> 23#include <dt-bindings/phy/phy-qcom-qmp.h> 24#include <dt-bindings/power/qcom-rpmpd.h> 25#include <dt-bindings/reset/qcom,sdm845-aoss.h> 26#include <dt-bindings/reset/qcom,sdm845-pdc.h> 27#include <dt-bindings/soc/qcom,rpmh-rsc.h> 28#include <dt-bindings/sound/qcom,lpass.h> 29#include <dt-bindings/thermal/thermal.h> 30 31/ { 32 interrupt-parent = <&intc>; 33 34 #address-cells = <2>; 35 #size-cells = <2>; 36 37 chosen { }; 38 39 aliases { 40 i2c0 = &i2c0; 41 i2c1 = &i2c1; 42 i2c2 = &i2c2; 43 i2c3 = &i2c3; 44 i2c4 = &i2c4; 45 i2c5 = &i2c5; 46 i2c6 = &i2c6; 47 i2c7 = &i2c7; 48 i2c8 = &i2c8; 49 i2c9 = &i2c9; 50 i2c10 = &i2c10; 51 i2c11 = &i2c11; 52 i2c12 = &i2c12; 53 i2c13 = &i2c13; 54 i2c14 = &i2c14; 55 i2c15 = &i2c15; 56 mmc1 = &sdhc_1; 57 mmc2 = &sdhc_2; 58 spi0 = &spi0; 59 spi1 = &spi1; 60 spi2 = &spi2; 61 spi3 = &spi3; 62 spi4 = &spi4; 63 spi5 = &spi5; 64 spi6 = &spi6; 65 spi7 = &spi7; 66 spi8 = &spi8; 67 spi9 = &spi9; 68 spi10 = &spi10; 69 spi11 = &spi11; 70 spi12 = &spi12; 71 spi13 = &spi13; 72 spi14 = &spi14; 73 spi15 = &spi15; 74 }; 75 76 clocks { 77 xo_board: xo-board { 78 compatible = "fixed-clock"; 79 clock-frequency = <76800000>; 80 #clock-cells = <0>; 81 }; 82 83 sleep_clk: sleep-clk { 84 compatible = "fixed-clock"; 85 clock-frequency = <32000>; 86 #clock-cells = <0>; 87 }; 88 }; 89 90 reserved-memory { 91 #address-cells = <2>; 92 #size-cells = <2>; 93 ranges; 94 95 wlan_ce_mem: wlan-ce@4cd000 { 96 no-map; 97 reg = <0x0 0x004cd000 0x0 0x1000>; 98 }; 99 100 hyp_mem: hyp@80000000 { 101 reg = <0x0 0x80000000 0x0 0x600000>; 102 no-map; 103 }; 104 105 xbl_mem: xbl@80600000 { 106 reg = <0x0 0x80600000 0x0 0x200000>; 107 no-map; 108 }; 109 110 aop_mem: aop@80800000 { 111 reg = <0x0 0x80800000 0x0 0x60000>; 112 no-map; 113 }; 114 115 aop_cmd_db_mem: aop-cmd-db@80860000 { 116 reg = <0x0 0x80860000 0x0 0x20000>; 117 compatible = "qcom,cmd-db"; 118 no-map; 119 }; 120 121 reserved_xbl_uefi_log: xbl-uefi-res@80880000 { 122 reg = <0x0 0x80884000 0x0 0x10000>; 123 no-map; 124 }; 125 126 sec_apps_mem: sec-apps@808ff000 { 127 reg = <0x0 0x808ff000 0x0 0x1000>; 128 no-map; 129 }; 130 131 smem_mem: smem@80900000 { 132 reg = <0x0 0x80900000 0x0 0x200000>; 133 no-map; 134 }; 135 136 cpucp_mem: cpucp@80b00000 { 137 no-map; 138 reg = <0x0 0x80b00000 0x0 0x100000>; 139 }; 140 141 wlan_fw_mem: wlan-fw@80c00000 { 142 reg = <0x0 0x80c00000 0x0 0xc00000>; 143 no-map; 144 }; 145 146 adsp_mem: adsp@86700000 { 147 reg = <0x0 0x86700000 0x0 0x2800000>; 148 no-map; 149 }; 150 151 video_mem: video@8b200000 { 152 reg = <0x0 0x8b200000 0x0 0x500000>; 153 no-map; 154 }; 155 156 cdsp_mem: cdsp@88f00000 { 157 reg = <0x0 0x88f00000 0x0 0x1e00000>; 158 no-map; 159 }; 160 161 ipa_fw_mem: ipa-fw@8b700000 { 162 reg = <0 0x8b700000 0 0x10000>; 163 no-map; 164 }; 165 166 gpu_zap_mem: zap@8b71a000 { 167 reg = <0 0x8b71a000 0 0x2000>; 168 no-map; 169 }; 170 171 mpss_mem: mpss@8b800000 { 172 reg = <0x0 0x8b800000 0x0 0xf600000>; 173 no-map; 174 }; 175 176 wpss_mem: wpss@9ae00000 { 177 reg = <0x0 0x9ae00000 0x0 0x1900000>; 178 no-map; 179 }; 180 181 rmtfs_mem: rmtfs@9c900000 { 182 compatible = "qcom,rmtfs-mem"; 183 reg = <0x0 0x9c900000 0x0 0x280000>; 184 no-map; 185 186 qcom,client-id = <1>; 187 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 188 }; 189 }; 190 191 cpus { 192 #address-cells = <2>; 193 #size-cells = <0>; 194 195 CPU0: cpu@0 { 196 device_type = "cpu"; 197 compatible = "qcom,kryo"; 198 reg = <0x0 0x0>; 199 clocks = <&cpufreq_hw 0>; 200 enable-method = "psci"; 201 power-domains = <&CPU_PD0>; 202 power-domain-names = "psci"; 203 next-level-cache = <&L2_0>; 204 operating-points-v2 = <&cpu0_opp_table>; 205 capacity-dmips-mhz = <1024>; 206 dynamic-power-coefficient = <100>; 207 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 208 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 209 qcom,freq-domain = <&cpufreq_hw 0>; 210 #cooling-cells = <2>; 211 L2_0: l2-cache { 212 compatible = "cache"; 213 cache-level = <2>; 214 cache-unified; 215 next-level-cache = <&L3_0>; 216 L3_0: l3-cache { 217 compatible = "cache"; 218 cache-level = <3>; 219 cache-unified; 220 }; 221 }; 222 }; 223 224 CPU1: cpu@100 { 225 device_type = "cpu"; 226 compatible = "qcom,kryo"; 227 reg = <0x0 0x100>; 228 clocks = <&cpufreq_hw 0>; 229 enable-method = "psci"; 230 power-domains = <&CPU_PD1>; 231 power-domain-names = "psci"; 232 next-level-cache = <&L2_100>; 233 operating-points-v2 = <&cpu0_opp_table>; 234 capacity-dmips-mhz = <1024>; 235 dynamic-power-coefficient = <100>; 236 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 237 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 238 qcom,freq-domain = <&cpufreq_hw 0>; 239 #cooling-cells = <2>; 240 L2_100: l2-cache { 241 compatible = "cache"; 242 cache-level = <2>; 243 cache-unified; 244 next-level-cache = <&L3_0>; 245 }; 246 }; 247 248 CPU2: cpu@200 { 249 device_type = "cpu"; 250 compatible = "qcom,kryo"; 251 reg = <0x0 0x200>; 252 clocks = <&cpufreq_hw 0>; 253 enable-method = "psci"; 254 power-domains = <&CPU_PD2>; 255 power-domain-names = "psci"; 256 next-level-cache = <&L2_200>; 257 operating-points-v2 = <&cpu0_opp_table>; 258 capacity-dmips-mhz = <1024>; 259 dynamic-power-coefficient = <100>; 260 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 261 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 262 qcom,freq-domain = <&cpufreq_hw 0>; 263 #cooling-cells = <2>; 264 L2_200: l2-cache { 265 compatible = "cache"; 266 cache-level = <2>; 267 cache-unified; 268 next-level-cache = <&L3_0>; 269 }; 270 }; 271 272 CPU3: cpu@300 { 273 device_type = "cpu"; 274 compatible = "qcom,kryo"; 275 reg = <0x0 0x300>; 276 clocks = <&cpufreq_hw 0>; 277 enable-method = "psci"; 278 power-domains = <&CPU_PD3>; 279 power-domain-names = "psci"; 280 next-level-cache = <&L2_300>; 281 operating-points-v2 = <&cpu0_opp_table>; 282 capacity-dmips-mhz = <1024>; 283 dynamic-power-coefficient = <100>; 284 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 285 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 286 qcom,freq-domain = <&cpufreq_hw 0>; 287 #cooling-cells = <2>; 288 L2_300: l2-cache { 289 compatible = "cache"; 290 cache-level = <2>; 291 cache-unified; 292 next-level-cache = <&L3_0>; 293 }; 294 }; 295 296 CPU4: cpu@400 { 297 device_type = "cpu"; 298 compatible = "qcom,kryo"; 299 reg = <0x0 0x400>; 300 clocks = <&cpufreq_hw 1>; 301 enable-method = "psci"; 302 power-domains = <&CPU_PD4>; 303 power-domain-names = "psci"; 304 next-level-cache = <&L2_400>; 305 operating-points-v2 = <&cpu4_opp_table>; 306 capacity-dmips-mhz = <1946>; 307 dynamic-power-coefficient = <520>; 308 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 309 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 310 qcom,freq-domain = <&cpufreq_hw 1>; 311 #cooling-cells = <2>; 312 L2_400: l2-cache { 313 compatible = "cache"; 314 cache-level = <2>; 315 cache-unified; 316 next-level-cache = <&L3_0>; 317 }; 318 }; 319 320 CPU5: cpu@500 { 321 device_type = "cpu"; 322 compatible = "qcom,kryo"; 323 reg = <0x0 0x500>; 324 clocks = <&cpufreq_hw 1>; 325 enable-method = "psci"; 326 power-domains = <&CPU_PD5>; 327 power-domain-names = "psci"; 328 next-level-cache = <&L2_500>; 329 operating-points-v2 = <&cpu4_opp_table>; 330 capacity-dmips-mhz = <1946>; 331 dynamic-power-coefficient = <520>; 332 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 333 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 334 qcom,freq-domain = <&cpufreq_hw 1>; 335 #cooling-cells = <2>; 336 L2_500: l2-cache { 337 compatible = "cache"; 338 cache-level = <2>; 339 cache-unified; 340 next-level-cache = <&L3_0>; 341 }; 342 }; 343 344 CPU6: cpu@600 { 345 device_type = "cpu"; 346 compatible = "qcom,kryo"; 347 reg = <0x0 0x600>; 348 clocks = <&cpufreq_hw 1>; 349 enable-method = "psci"; 350 power-domains = <&CPU_PD6>; 351 power-domain-names = "psci"; 352 next-level-cache = <&L2_600>; 353 operating-points-v2 = <&cpu4_opp_table>; 354 capacity-dmips-mhz = <1946>; 355 dynamic-power-coefficient = <520>; 356 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 357 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 358 qcom,freq-domain = <&cpufreq_hw 1>; 359 #cooling-cells = <2>; 360 L2_600: l2-cache { 361 compatible = "cache"; 362 cache-level = <2>; 363 cache-unified; 364 next-level-cache = <&L3_0>; 365 }; 366 }; 367 368 CPU7: cpu@700 { 369 device_type = "cpu"; 370 compatible = "qcom,kryo"; 371 reg = <0x0 0x700>; 372 clocks = <&cpufreq_hw 2>; 373 enable-method = "psci"; 374 power-domains = <&CPU_PD7>; 375 power-domain-names = "psci"; 376 next-level-cache = <&L2_700>; 377 operating-points-v2 = <&cpu7_opp_table>; 378 capacity-dmips-mhz = <1985>; 379 dynamic-power-coefficient = <552>; 380 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 381 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 382 qcom,freq-domain = <&cpufreq_hw 2>; 383 #cooling-cells = <2>; 384 L2_700: l2-cache { 385 compatible = "cache"; 386 cache-level = <2>; 387 cache-unified; 388 next-level-cache = <&L3_0>; 389 }; 390 }; 391 392 cpu-map { 393 cluster0 { 394 core0 { 395 cpu = <&CPU0>; 396 }; 397 398 core1 { 399 cpu = <&CPU1>; 400 }; 401 402 core2 { 403 cpu = <&CPU2>; 404 }; 405 406 core3 { 407 cpu = <&CPU3>; 408 }; 409 410 core4 { 411 cpu = <&CPU4>; 412 }; 413 414 core5 { 415 cpu = <&CPU5>; 416 }; 417 418 core6 { 419 cpu = <&CPU6>; 420 }; 421 422 core7 { 423 cpu = <&CPU7>; 424 }; 425 }; 426 }; 427 428 idle-states { 429 entry-method = "psci"; 430 431 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 432 compatible = "arm,idle-state"; 433 idle-state-name = "little-power-down"; 434 arm,psci-suspend-param = <0x40000003>; 435 entry-latency-us = <549>; 436 exit-latency-us = <901>; 437 min-residency-us = <1774>; 438 local-timer-stop; 439 }; 440 441 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 442 compatible = "arm,idle-state"; 443 idle-state-name = "little-rail-power-down"; 444 arm,psci-suspend-param = <0x40000004>; 445 entry-latency-us = <702>; 446 exit-latency-us = <915>; 447 min-residency-us = <4001>; 448 local-timer-stop; 449 }; 450 451 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 452 compatible = "arm,idle-state"; 453 idle-state-name = "big-power-down"; 454 arm,psci-suspend-param = <0x40000003>; 455 entry-latency-us = <523>; 456 exit-latency-us = <1244>; 457 min-residency-us = <2207>; 458 local-timer-stop; 459 }; 460 461 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 462 compatible = "arm,idle-state"; 463 idle-state-name = "big-rail-power-down"; 464 arm,psci-suspend-param = <0x40000004>; 465 entry-latency-us = <526>; 466 exit-latency-us = <1854>; 467 min-residency-us = <5555>; 468 local-timer-stop; 469 }; 470 }; 471 472 domain_idle_states: domain-idle-states { 473 CLUSTER_SLEEP_APSS_OFF: cluster-sleep-0 { 474 compatible = "domain-idle-state"; 475 arm,psci-suspend-param = <0x41000044>; 476 entry-latency-us = <2752>; 477 exit-latency-us = <3048>; 478 min-residency-us = <6118>; 479 }; 480 481 CLUSTER_SLEEP_CX_RET: cluster-sleep-1 { 482 compatible = "domain-idle-state"; 483 arm,psci-suspend-param = <0x41001344>; 484 entry-latency-us = <3263>; 485 exit-latency-us = <4562>; 486 min-residency-us = <8467>; 487 }; 488 489 CLUSTER_SLEEP_LLCC_OFF: cluster-sleep-2 { 490 compatible = "domain-idle-state"; 491 arm,psci-suspend-param = <0x4100b344>; 492 entry-latency-us = <3638>; 493 exit-latency-us = <6562>; 494 min-residency-us = <9826>; 495 }; 496 }; 497 }; 498 499 cpu0_opp_table: opp-table-cpu0 { 500 compatible = "operating-points-v2"; 501 opp-shared; 502 503 cpu0_opp_300mhz: opp-300000000 { 504 opp-hz = /bits/ 64 <300000000>; 505 opp-peak-kBps = <800000 9600000>; 506 }; 507 508 cpu0_opp_691mhz: opp-691200000 { 509 opp-hz = /bits/ 64 <691200000>; 510 opp-peak-kBps = <800000 17817600>; 511 }; 512 513 cpu0_opp_806mhz: opp-806400000 { 514 opp-hz = /bits/ 64 <806400000>; 515 opp-peak-kBps = <800000 20889600>; 516 }; 517 518 cpu0_opp_941mhz: opp-940800000 { 519 opp-hz = /bits/ 64 <940800000>; 520 opp-peak-kBps = <1804000 24576000>; 521 }; 522 523 cpu0_opp_1152mhz: opp-1152000000 { 524 opp-hz = /bits/ 64 <1152000000>; 525 opp-peak-kBps = <2188000 27033600>; 526 }; 527 528 cpu0_opp_1325mhz: opp-1324800000 { 529 opp-hz = /bits/ 64 <1324800000>; 530 opp-peak-kBps = <2188000 33792000>; 531 }; 532 533 cpu0_opp_1517mhz: opp-1516800000 { 534 opp-hz = /bits/ 64 <1516800000>; 535 opp-peak-kBps = <3072000 38092800>; 536 }; 537 538 cpu0_opp_1651mhz: opp-1651200000 { 539 opp-hz = /bits/ 64 <1651200000>; 540 opp-peak-kBps = <3072000 41779200>; 541 }; 542 543 cpu0_opp_1805mhz: opp-1804800000 { 544 opp-hz = /bits/ 64 <1804800000>; 545 opp-peak-kBps = <4068000 48537600>; 546 }; 547 548 cpu0_opp_1958mhz: opp-1958400000 { 549 opp-hz = /bits/ 64 <1958400000>; 550 opp-peak-kBps = <4068000 48537600>; 551 }; 552 553 cpu0_opp_2016mhz: opp-2016000000 { 554 opp-hz = /bits/ 64 <2016000000>; 555 opp-peak-kBps = <6220000 48537600>; 556 }; 557 }; 558 559 cpu4_opp_table: opp-table-cpu4 { 560 compatible = "operating-points-v2"; 561 opp-shared; 562 563 cpu4_opp_691mhz: opp-691200000 { 564 opp-hz = /bits/ 64 <691200000>; 565 opp-peak-kBps = <1804000 9600000>; 566 }; 567 568 cpu4_opp_941mhz: opp-940800000 { 569 opp-hz = /bits/ 64 <940800000>; 570 opp-peak-kBps = <2188000 17817600>; 571 }; 572 573 cpu4_opp_1229mhz: opp-1228800000 { 574 opp-hz = /bits/ 64 <1228800000>; 575 opp-peak-kBps = <4068000 24576000>; 576 }; 577 578 cpu4_opp_1344mhz: opp-1344000000 { 579 opp-hz = /bits/ 64 <1344000000>; 580 opp-peak-kBps = <4068000 24576000>; 581 }; 582 583 cpu4_opp_1517mhz: opp-1516800000 { 584 opp-hz = /bits/ 64 <1516800000>; 585 opp-peak-kBps = <4068000 24576000>; 586 }; 587 588 cpu4_opp_1651mhz: opp-1651200000 { 589 opp-hz = /bits/ 64 <1651200000>; 590 opp-peak-kBps = <6220000 38092800>; 591 }; 592 593 cpu4_opp_1901mhz: opp-1900800000 { 594 opp-hz = /bits/ 64 <1900800000>; 595 opp-peak-kBps = <6220000 44851200>; 596 }; 597 598 cpu4_opp_2054mhz: opp-2054400000 { 599 opp-hz = /bits/ 64 <2054400000>; 600 opp-peak-kBps = <6220000 44851200>; 601 }; 602 603 cpu4_opp_2112mhz: opp-2112000000 { 604 opp-hz = /bits/ 64 <2112000000>; 605 opp-peak-kBps = <6220000 44851200>; 606 }; 607 608 cpu4_opp_2131mhz: opp-2131200000 { 609 opp-hz = /bits/ 64 <2131200000>; 610 opp-peak-kBps = <6220000 44851200>; 611 }; 612 613 cpu4_opp_2208mhz: opp-2208000000 { 614 opp-hz = /bits/ 64 <2208000000>; 615 opp-peak-kBps = <6220000 44851200>; 616 }; 617 618 cpu4_opp_2400mhz: opp-2400000000 { 619 opp-hz = /bits/ 64 <2400000000>; 620 opp-peak-kBps = <8532000 48537600>; 621 }; 622 623 cpu4_opp_2611mhz: opp-2611200000 { 624 opp-hz = /bits/ 64 <2611200000>; 625 opp-peak-kBps = <8532000 48537600>; 626 }; 627 }; 628 629 cpu7_opp_table: opp-table-cpu7 { 630 compatible = "operating-points-v2"; 631 opp-shared; 632 633 cpu7_opp_806mhz: opp-806400000 { 634 opp-hz = /bits/ 64 <806400000>; 635 opp-peak-kBps = <1804000 9600000>; 636 }; 637 638 cpu7_opp_1056mhz: opp-1056000000 { 639 opp-hz = /bits/ 64 <1056000000>; 640 opp-peak-kBps = <2188000 17817600>; 641 }; 642 643 cpu7_opp_1325mhz: opp-1324800000 { 644 opp-hz = /bits/ 64 <1324800000>; 645 opp-peak-kBps = <4068000 24576000>; 646 }; 647 648 cpu7_opp_1517mhz: opp-1516800000 { 649 opp-hz = /bits/ 64 <1516800000>; 650 opp-peak-kBps = <4068000 24576000>; 651 }; 652 653 cpu7_opp_1766mhz: opp-1766400000 { 654 opp-hz = /bits/ 64 <1766400000>; 655 opp-peak-kBps = <6220000 38092800>; 656 }; 657 658 cpu7_opp_1862mhz: opp-1862400000 { 659 opp-hz = /bits/ 64 <1862400000>; 660 opp-peak-kBps = <6220000 38092800>; 661 }; 662 663 cpu7_opp_2035mhz: opp-2035200000 { 664 opp-hz = /bits/ 64 <2035200000>; 665 opp-peak-kBps = <6220000 38092800>; 666 }; 667 668 cpu7_opp_2112mhz: opp-2112000000 { 669 opp-hz = /bits/ 64 <2112000000>; 670 opp-peak-kBps = <6220000 44851200>; 671 }; 672 673 cpu7_opp_2208mhz: opp-2208000000 { 674 opp-hz = /bits/ 64 <2208000000>; 675 opp-peak-kBps = <6220000 44851200>; 676 }; 677 678 cpu7_opp_2381mhz: opp-2380800000 { 679 opp-hz = /bits/ 64 <2380800000>; 680 opp-peak-kBps = <6832000 44851200>; 681 }; 682 683 cpu7_opp_2400mhz: opp-2400000000 { 684 opp-hz = /bits/ 64 <2400000000>; 685 opp-peak-kBps = <8532000 48537600>; 686 }; 687 688 cpu7_opp_2515mhz: opp-2515200000 { 689 opp-hz = /bits/ 64 <2515200000>; 690 opp-peak-kBps = <8532000 48537600>; 691 }; 692 693 cpu7_opp_2707mhz: opp-2707200000 { 694 opp-hz = /bits/ 64 <2707200000>; 695 opp-peak-kBps = <8532000 48537600>; 696 }; 697 698 cpu7_opp_3014mhz: opp-3014400000 { 699 opp-hz = /bits/ 64 <3014400000>; 700 opp-peak-kBps = <8532000 48537600>; 701 }; 702 }; 703 704 memory@80000000 { 705 device_type = "memory"; 706 /* We expect the bootloader to fill in the size */ 707 reg = <0 0x80000000 0 0>; 708 }; 709 710 firmware { 711 scm: scm { 712 compatible = "qcom,scm-sc7280", "qcom,scm"; 713 }; 714 }; 715 716 clk_virt: interconnect { 717 compatible = "qcom,sc7280-clk-virt"; 718 #interconnect-cells = <2>; 719 qcom,bcm-voters = <&apps_bcm_voter>; 720 }; 721 722 smem { 723 compatible = "qcom,smem"; 724 memory-region = <&smem_mem>; 725 hwlocks = <&tcsr_mutex 3>; 726 }; 727 728 smp2p-adsp { 729 compatible = "qcom,smp2p"; 730 qcom,smem = <443>, <429>; 731 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 732 IPCC_MPROC_SIGNAL_SMP2P 733 IRQ_TYPE_EDGE_RISING>; 734 mboxes = <&ipcc IPCC_CLIENT_LPASS 735 IPCC_MPROC_SIGNAL_SMP2P>; 736 737 qcom,local-pid = <0>; 738 qcom,remote-pid = <2>; 739 740 adsp_smp2p_out: master-kernel { 741 qcom,entry-name = "master-kernel"; 742 #qcom,smem-state-cells = <1>; 743 }; 744 745 adsp_smp2p_in: slave-kernel { 746 qcom,entry-name = "slave-kernel"; 747 interrupt-controller; 748 #interrupt-cells = <2>; 749 }; 750 }; 751 752 smp2p-cdsp { 753 compatible = "qcom,smp2p"; 754 qcom,smem = <94>, <432>; 755 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 756 IPCC_MPROC_SIGNAL_SMP2P 757 IRQ_TYPE_EDGE_RISING>; 758 mboxes = <&ipcc IPCC_CLIENT_CDSP 759 IPCC_MPROC_SIGNAL_SMP2P>; 760 761 qcom,local-pid = <0>; 762 qcom,remote-pid = <5>; 763 764 cdsp_smp2p_out: master-kernel { 765 qcom,entry-name = "master-kernel"; 766 #qcom,smem-state-cells = <1>; 767 }; 768 769 cdsp_smp2p_in: slave-kernel { 770 qcom,entry-name = "slave-kernel"; 771 interrupt-controller; 772 #interrupt-cells = <2>; 773 }; 774 }; 775 776 smp2p-mpss { 777 compatible = "qcom,smp2p"; 778 qcom,smem = <435>, <428>; 779 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 780 IPCC_MPROC_SIGNAL_SMP2P 781 IRQ_TYPE_EDGE_RISING>; 782 mboxes = <&ipcc IPCC_CLIENT_MPSS 783 IPCC_MPROC_SIGNAL_SMP2P>; 784 785 qcom,local-pid = <0>; 786 qcom,remote-pid = <1>; 787 788 modem_smp2p_out: master-kernel { 789 qcom,entry-name = "master-kernel"; 790 #qcom,smem-state-cells = <1>; 791 }; 792 793 modem_smp2p_in: slave-kernel { 794 qcom,entry-name = "slave-kernel"; 795 interrupt-controller; 796 #interrupt-cells = <2>; 797 }; 798 799 ipa_smp2p_out: ipa-ap-to-modem { 800 qcom,entry-name = "ipa"; 801 #qcom,smem-state-cells = <1>; 802 }; 803 804 ipa_smp2p_in: ipa-modem-to-ap { 805 qcom,entry-name = "ipa"; 806 interrupt-controller; 807 #interrupt-cells = <2>; 808 }; 809 }; 810 811 smp2p-wpss { 812 compatible = "qcom,smp2p"; 813 qcom,smem = <617>, <616>; 814 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 815 IPCC_MPROC_SIGNAL_SMP2P 816 IRQ_TYPE_EDGE_RISING>; 817 mboxes = <&ipcc IPCC_CLIENT_WPSS 818 IPCC_MPROC_SIGNAL_SMP2P>; 819 820 qcom,local-pid = <0>; 821 qcom,remote-pid = <13>; 822 823 wpss_smp2p_out: master-kernel { 824 qcom,entry-name = "master-kernel"; 825 #qcom,smem-state-cells = <1>; 826 }; 827 828 wpss_smp2p_in: slave-kernel { 829 qcom,entry-name = "slave-kernel"; 830 interrupt-controller; 831 #interrupt-cells = <2>; 832 }; 833 834 wlan_smp2p_out: wlan-ap-to-wpss { 835 qcom,entry-name = "wlan"; 836 #qcom,smem-state-cells = <1>; 837 }; 838 839 wlan_smp2p_in: wlan-wpss-to-ap { 840 qcom,entry-name = "wlan"; 841 interrupt-controller; 842 #interrupt-cells = <2>; 843 }; 844 }; 845 846 pmu { 847 compatible = "arm,armv8-pmuv3"; 848 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 849 }; 850 851 psci { 852 compatible = "arm,psci-1.0"; 853 method = "smc"; 854 855 CPU_PD0: power-domain-cpu0 { 856 #power-domain-cells = <0>; 857 power-domains = <&CLUSTER_PD>; 858 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 859 }; 860 861 CPU_PD1: power-domain-cpu1 { 862 #power-domain-cells = <0>; 863 power-domains = <&CLUSTER_PD>; 864 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 865 }; 866 867 CPU_PD2: power-domain-cpu2 { 868 #power-domain-cells = <0>; 869 power-domains = <&CLUSTER_PD>; 870 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 871 }; 872 873 CPU_PD3: power-domain-cpu3 { 874 #power-domain-cells = <0>; 875 power-domains = <&CLUSTER_PD>; 876 domain-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; 877 }; 878 879 CPU_PD4: power-domain-cpu4 { 880 #power-domain-cells = <0>; 881 power-domains = <&CLUSTER_PD>; 882 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 883 }; 884 885 CPU_PD5: power-domain-cpu5 { 886 #power-domain-cells = <0>; 887 power-domains = <&CLUSTER_PD>; 888 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 889 }; 890 891 CPU_PD6: power-domain-cpu6 { 892 #power-domain-cells = <0>; 893 power-domains = <&CLUSTER_PD>; 894 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 895 }; 896 897 CPU_PD7: power-domain-cpu7 { 898 #power-domain-cells = <0>; 899 power-domains = <&CLUSTER_PD>; 900 domain-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; 901 }; 902 903 CLUSTER_PD: power-domain-cluster { 904 #power-domain-cells = <0>; 905 domain-idle-states = <&CLUSTER_SLEEP_APSS_OFF &CLUSTER_SLEEP_CX_RET &CLUSTER_SLEEP_LLCC_OFF>; 906 }; 907 }; 908 909 qspi_opp_table: opp-table-qspi { 910 compatible = "operating-points-v2"; 911 912 opp-75000000 { 913 opp-hz = /bits/ 64 <75000000>; 914 required-opps = <&rpmhpd_opp_low_svs>; 915 }; 916 917 opp-150000000 { 918 opp-hz = /bits/ 64 <150000000>; 919 required-opps = <&rpmhpd_opp_svs>; 920 }; 921 922 opp-200000000 { 923 opp-hz = /bits/ 64 <200000000>; 924 required-opps = <&rpmhpd_opp_svs_l1>; 925 }; 926 927 opp-300000000 { 928 opp-hz = /bits/ 64 <300000000>; 929 required-opps = <&rpmhpd_opp_nom>; 930 }; 931 }; 932 933 qup_opp_table: opp-table-qup { 934 compatible = "operating-points-v2"; 935 936 opp-75000000 { 937 opp-hz = /bits/ 64 <75000000>; 938 required-opps = <&rpmhpd_opp_low_svs>; 939 }; 940 941 opp-100000000 { 942 opp-hz = /bits/ 64 <100000000>; 943 required-opps = <&rpmhpd_opp_svs>; 944 }; 945 946 opp-128000000 { 947 opp-hz = /bits/ 64 <128000000>; 948 required-opps = <&rpmhpd_opp_nom>; 949 }; 950 }; 951 952 soc: soc@0 { 953 #address-cells = <2>; 954 #size-cells = <2>; 955 ranges = <0 0 0 0 0x10 0>; 956 dma-ranges = <0 0 0 0 0x10 0>; 957 compatible = "simple-bus"; 958 959 gcc: clock-controller@100000 { 960 compatible = "qcom,gcc-sc7280"; 961 reg = <0 0x00100000 0 0x1f0000>; 962 clocks = <&rpmhcc RPMH_CXO_CLK>, 963 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 964 <0>, <&pcie1_phy>, 965 <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, 966 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 967 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 968 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 969 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 970 "ufs_phy_tx_symbol_0_clk", 971 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 972 #clock-cells = <1>; 973 #reset-cells = <1>; 974 #power-domain-cells = <1>; 975 power-domains = <&rpmhpd SC7280_CX>; 976 }; 977 978 ipcc: mailbox@408000 { 979 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 980 reg = <0 0x00408000 0 0x1000>; 981 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 982 interrupt-controller; 983 #interrupt-cells = <3>; 984 #mbox-cells = <2>; 985 }; 986 987 qfprom: efuse@784000 { 988 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 989 reg = <0 0x00784000 0 0xa20>, 990 <0 0x00780000 0 0xa20>, 991 <0 0x00782000 0 0x120>, 992 <0 0x00786000 0 0x1fff>; 993 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 994 clock-names = "core"; 995 power-domains = <&rpmhpd SC7280_MX>; 996 #address-cells = <1>; 997 #size-cells = <1>; 998 999 gpu_speed_bin: gpu-speed-bin@1e9 { 1000 reg = <0x1e9 0x2>; 1001 bits = <5 8>; 1002 }; 1003 }; 1004 1005 sdhc_1: mmc@7c4000 { 1006 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 1007 pinctrl-names = "default", "sleep"; 1008 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 1009 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 1010 status = "disabled"; 1011 1012 reg = <0 0x007c4000 0 0x1000>, 1013 <0 0x007c5000 0 0x1000>; 1014 reg-names = "hc", "cqhci"; 1015 1016 iommus = <&apps_smmu 0xc0 0x0>; 1017 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 1018 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 1019 interrupt-names = "hc_irq", "pwr_irq"; 1020 1021 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1022 <&gcc GCC_SDCC1_APPS_CLK>, 1023 <&rpmhcc RPMH_CXO_CLK>; 1024 clock-names = "iface", "core", "xo"; 1025 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 1026 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 1027 interconnect-names = "sdhc-ddr","cpu-sdhc"; 1028 power-domains = <&rpmhpd SC7280_CX>; 1029 operating-points-v2 = <&sdhc1_opp_table>; 1030 1031 bus-width = <8>; 1032 supports-cqe; 1033 dma-coherent; 1034 1035 qcom,dll-config = <0x0007642c>; 1036 qcom,ddr-config = <0x80040868>; 1037 1038 mmc-ddr-1_8v; 1039 mmc-hs200-1_8v; 1040 mmc-hs400-1_8v; 1041 mmc-hs400-enhanced-strobe; 1042 1043 resets = <&gcc GCC_SDCC1_BCR>; 1044 1045 sdhc1_opp_table: opp-table { 1046 compatible = "operating-points-v2"; 1047 1048 opp-100000000 { 1049 opp-hz = /bits/ 64 <100000000>; 1050 required-opps = <&rpmhpd_opp_low_svs>; 1051 opp-peak-kBps = <1800000 400000>; 1052 opp-avg-kBps = <100000 0>; 1053 }; 1054 1055 opp-384000000 { 1056 opp-hz = /bits/ 64 <384000000>; 1057 required-opps = <&rpmhpd_opp_nom>; 1058 opp-peak-kBps = <5400000 1600000>; 1059 opp-avg-kBps = <390000 0>; 1060 }; 1061 }; 1062 }; 1063 1064 gpi_dma0: dma-controller@900000 { 1065 #dma-cells = <3>; 1066 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1067 reg = <0 0x00900000 0 0x60000>; 1068 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1070 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1071 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1072 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1073 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1074 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1075 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1076 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1077 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1078 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1079 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1080 dma-channels = <12>; 1081 dma-channel-mask = <0x7f>; 1082 iommus = <&apps_smmu 0x0136 0x0>; 1083 status = "disabled"; 1084 }; 1085 1086 qupv3_id_0: geniqup@9c0000 { 1087 compatible = "qcom,geni-se-qup"; 1088 reg = <0 0x009c0000 0 0x2000>; 1089 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1090 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1091 clock-names = "m-ahb", "s-ahb"; 1092 #address-cells = <2>; 1093 #size-cells = <2>; 1094 ranges; 1095 iommus = <&apps_smmu 0x123 0x0>; 1096 status = "disabled"; 1097 1098 i2c0: i2c@980000 { 1099 compatible = "qcom,geni-i2c"; 1100 reg = <0 0x00980000 0 0x4000>; 1101 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1102 clock-names = "se"; 1103 pinctrl-names = "default"; 1104 pinctrl-0 = <&qup_i2c0_data_clk>; 1105 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1106 #address-cells = <1>; 1107 #size-cells = <0>; 1108 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1109 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1110 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1111 interconnect-names = "qup-core", "qup-config", 1112 "qup-memory"; 1113 power-domains = <&rpmhpd SC7280_CX>; 1114 required-opps = <&rpmhpd_opp_low_svs>; 1115 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1116 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1117 dma-names = "tx", "rx"; 1118 status = "disabled"; 1119 }; 1120 1121 spi0: spi@980000 { 1122 compatible = "qcom,geni-spi"; 1123 reg = <0 0x00980000 0 0x4000>; 1124 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1125 clock-names = "se"; 1126 pinctrl-names = "default"; 1127 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1128 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1129 #address-cells = <1>; 1130 #size-cells = <0>; 1131 power-domains = <&rpmhpd SC7280_CX>; 1132 operating-points-v2 = <&qup_opp_table>; 1133 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1134 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1135 interconnect-names = "qup-core", "qup-config"; 1136 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1137 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1138 dma-names = "tx", "rx"; 1139 status = "disabled"; 1140 }; 1141 1142 uart0: serial@980000 { 1143 compatible = "qcom,geni-uart"; 1144 reg = <0 0x00980000 0 0x4000>; 1145 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1146 clock-names = "se"; 1147 pinctrl-names = "default"; 1148 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1149 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1150 power-domains = <&rpmhpd SC7280_CX>; 1151 operating-points-v2 = <&qup_opp_table>; 1152 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1153 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1154 interconnect-names = "qup-core", "qup-config"; 1155 status = "disabled"; 1156 }; 1157 1158 i2c1: i2c@984000 { 1159 compatible = "qcom,geni-i2c"; 1160 reg = <0 0x00984000 0 0x4000>; 1161 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1162 clock-names = "se"; 1163 pinctrl-names = "default"; 1164 pinctrl-0 = <&qup_i2c1_data_clk>; 1165 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1166 #address-cells = <1>; 1167 #size-cells = <0>; 1168 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1169 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1170 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1171 interconnect-names = "qup-core", "qup-config", 1172 "qup-memory"; 1173 power-domains = <&rpmhpd SC7280_CX>; 1174 required-opps = <&rpmhpd_opp_low_svs>; 1175 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1176 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1177 dma-names = "tx", "rx"; 1178 status = "disabled"; 1179 }; 1180 1181 spi1: spi@984000 { 1182 compatible = "qcom,geni-spi"; 1183 reg = <0 0x00984000 0 0x4000>; 1184 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1185 clock-names = "se"; 1186 pinctrl-names = "default"; 1187 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1188 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1189 #address-cells = <1>; 1190 #size-cells = <0>; 1191 power-domains = <&rpmhpd SC7280_CX>; 1192 operating-points-v2 = <&qup_opp_table>; 1193 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1194 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1195 interconnect-names = "qup-core", "qup-config"; 1196 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1197 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1198 dma-names = "tx", "rx"; 1199 status = "disabled"; 1200 }; 1201 1202 uart1: serial@984000 { 1203 compatible = "qcom,geni-uart"; 1204 reg = <0 0x00984000 0 0x4000>; 1205 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1206 clock-names = "se"; 1207 pinctrl-names = "default"; 1208 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1209 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1210 power-domains = <&rpmhpd SC7280_CX>; 1211 operating-points-v2 = <&qup_opp_table>; 1212 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1213 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1214 interconnect-names = "qup-core", "qup-config"; 1215 status = "disabled"; 1216 }; 1217 1218 i2c2: i2c@988000 { 1219 compatible = "qcom,geni-i2c"; 1220 reg = <0 0x00988000 0 0x4000>; 1221 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1222 clock-names = "se"; 1223 pinctrl-names = "default"; 1224 pinctrl-0 = <&qup_i2c2_data_clk>; 1225 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1226 #address-cells = <1>; 1227 #size-cells = <0>; 1228 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1229 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1230 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1231 interconnect-names = "qup-core", "qup-config", 1232 "qup-memory"; 1233 power-domains = <&rpmhpd SC7280_CX>; 1234 required-opps = <&rpmhpd_opp_low_svs>; 1235 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1236 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1237 dma-names = "tx", "rx"; 1238 status = "disabled"; 1239 }; 1240 1241 spi2: spi@988000 { 1242 compatible = "qcom,geni-spi"; 1243 reg = <0 0x00988000 0 0x4000>; 1244 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1245 clock-names = "se"; 1246 pinctrl-names = "default"; 1247 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1248 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1249 #address-cells = <1>; 1250 #size-cells = <0>; 1251 power-domains = <&rpmhpd SC7280_CX>; 1252 operating-points-v2 = <&qup_opp_table>; 1253 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1254 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1255 interconnect-names = "qup-core", "qup-config"; 1256 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1257 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1258 dma-names = "tx", "rx"; 1259 status = "disabled"; 1260 }; 1261 1262 uart2: serial@988000 { 1263 compatible = "qcom,geni-uart"; 1264 reg = <0 0x00988000 0 0x4000>; 1265 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1266 clock-names = "se"; 1267 pinctrl-names = "default"; 1268 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1269 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1270 power-domains = <&rpmhpd SC7280_CX>; 1271 operating-points-v2 = <&qup_opp_table>; 1272 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1273 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1274 interconnect-names = "qup-core", "qup-config"; 1275 status = "disabled"; 1276 }; 1277 1278 i2c3: i2c@98c000 { 1279 compatible = "qcom,geni-i2c"; 1280 reg = <0 0x0098c000 0 0x4000>; 1281 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1282 clock-names = "se"; 1283 pinctrl-names = "default"; 1284 pinctrl-0 = <&qup_i2c3_data_clk>; 1285 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1286 #address-cells = <1>; 1287 #size-cells = <0>; 1288 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1289 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1290 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1291 interconnect-names = "qup-core", "qup-config", 1292 "qup-memory"; 1293 power-domains = <&rpmhpd SC7280_CX>; 1294 required-opps = <&rpmhpd_opp_low_svs>; 1295 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1296 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1297 dma-names = "tx", "rx"; 1298 status = "disabled"; 1299 }; 1300 1301 spi3: spi@98c000 { 1302 compatible = "qcom,geni-spi"; 1303 reg = <0 0x0098c000 0 0x4000>; 1304 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1305 clock-names = "se"; 1306 pinctrl-names = "default"; 1307 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1308 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1309 #address-cells = <1>; 1310 #size-cells = <0>; 1311 power-domains = <&rpmhpd SC7280_CX>; 1312 operating-points-v2 = <&qup_opp_table>; 1313 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1314 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1315 interconnect-names = "qup-core", "qup-config"; 1316 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1317 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1318 dma-names = "tx", "rx"; 1319 status = "disabled"; 1320 }; 1321 1322 uart3: serial@98c000 { 1323 compatible = "qcom,geni-uart"; 1324 reg = <0 0x0098c000 0 0x4000>; 1325 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1326 clock-names = "se"; 1327 pinctrl-names = "default"; 1328 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1329 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1330 power-domains = <&rpmhpd SC7280_CX>; 1331 operating-points-v2 = <&qup_opp_table>; 1332 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1333 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1334 interconnect-names = "qup-core", "qup-config"; 1335 status = "disabled"; 1336 }; 1337 1338 i2c4: i2c@990000 { 1339 compatible = "qcom,geni-i2c"; 1340 reg = <0 0x00990000 0 0x4000>; 1341 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1342 clock-names = "se"; 1343 pinctrl-names = "default"; 1344 pinctrl-0 = <&qup_i2c4_data_clk>; 1345 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1346 #address-cells = <1>; 1347 #size-cells = <0>; 1348 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1349 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1350 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1351 interconnect-names = "qup-core", "qup-config", 1352 "qup-memory"; 1353 power-domains = <&rpmhpd SC7280_CX>; 1354 required-opps = <&rpmhpd_opp_low_svs>; 1355 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1356 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1357 dma-names = "tx", "rx"; 1358 status = "disabled"; 1359 }; 1360 1361 spi4: spi@990000 { 1362 compatible = "qcom,geni-spi"; 1363 reg = <0 0x00990000 0 0x4000>; 1364 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1365 clock-names = "se"; 1366 pinctrl-names = "default"; 1367 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1368 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1369 #address-cells = <1>; 1370 #size-cells = <0>; 1371 power-domains = <&rpmhpd SC7280_CX>; 1372 operating-points-v2 = <&qup_opp_table>; 1373 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1374 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1375 interconnect-names = "qup-core", "qup-config"; 1376 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1377 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1378 dma-names = "tx", "rx"; 1379 status = "disabled"; 1380 }; 1381 1382 uart4: serial@990000 { 1383 compatible = "qcom,geni-uart"; 1384 reg = <0 0x00990000 0 0x4000>; 1385 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1386 clock-names = "se"; 1387 pinctrl-names = "default"; 1388 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1389 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1390 power-domains = <&rpmhpd SC7280_CX>; 1391 operating-points-v2 = <&qup_opp_table>; 1392 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1393 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1394 interconnect-names = "qup-core", "qup-config"; 1395 status = "disabled"; 1396 }; 1397 1398 i2c5: i2c@994000 { 1399 compatible = "qcom,geni-i2c"; 1400 reg = <0 0x00994000 0 0x4000>; 1401 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1402 clock-names = "se"; 1403 pinctrl-names = "default"; 1404 pinctrl-0 = <&qup_i2c5_data_clk>; 1405 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1406 #address-cells = <1>; 1407 #size-cells = <0>; 1408 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1409 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1410 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1411 interconnect-names = "qup-core", "qup-config", 1412 "qup-memory"; 1413 power-domains = <&rpmhpd SC7280_CX>; 1414 required-opps = <&rpmhpd_opp_low_svs>; 1415 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1416 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1417 dma-names = "tx", "rx"; 1418 status = "disabled"; 1419 }; 1420 1421 spi5: spi@994000 { 1422 compatible = "qcom,geni-spi"; 1423 reg = <0 0x00994000 0 0x4000>; 1424 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1425 clock-names = "se"; 1426 pinctrl-names = "default"; 1427 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1428 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1429 #address-cells = <1>; 1430 #size-cells = <0>; 1431 power-domains = <&rpmhpd SC7280_CX>; 1432 operating-points-v2 = <&qup_opp_table>; 1433 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1434 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1435 interconnect-names = "qup-core", "qup-config"; 1436 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1437 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1438 dma-names = "tx", "rx"; 1439 status = "disabled"; 1440 }; 1441 1442 uart5: serial@994000 { 1443 compatible = "qcom,geni-uart"; 1444 reg = <0 0x00994000 0 0x4000>; 1445 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1446 clock-names = "se"; 1447 pinctrl-names = "default"; 1448 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; 1449 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1450 power-domains = <&rpmhpd SC7280_CX>; 1451 operating-points-v2 = <&qup_opp_table>; 1452 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1453 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1454 interconnect-names = "qup-core", "qup-config"; 1455 status = "disabled"; 1456 }; 1457 1458 i2c6: i2c@998000 { 1459 compatible = "qcom,geni-i2c"; 1460 reg = <0 0x00998000 0 0x4000>; 1461 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1462 clock-names = "se"; 1463 pinctrl-names = "default"; 1464 pinctrl-0 = <&qup_i2c6_data_clk>; 1465 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1466 #address-cells = <1>; 1467 #size-cells = <0>; 1468 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1469 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1470 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1471 interconnect-names = "qup-core", "qup-config", 1472 "qup-memory"; 1473 power-domains = <&rpmhpd SC7280_CX>; 1474 required-opps = <&rpmhpd_opp_low_svs>; 1475 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1476 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1477 dma-names = "tx", "rx"; 1478 status = "disabled"; 1479 }; 1480 1481 spi6: spi@998000 { 1482 compatible = "qcom,geni-spi"; 1483 reg = <0 0x00998000 0 0x4000>; 1484 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1485 clock-names = "se"; 1486 pinctrl-names = "default"; 1487 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1488 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1489 #address-cells = <1>; 1490 #size-cells = <0>; 1491 power-domains = <&rpmhpd SC7280_CX>; 1492 operating-points-v2 = <&qup_opp_table>; 1493 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1494 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1495 interconnect-names = "qup-core", "qup-config"; 1496 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1497 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1498 dma-names = "tx", "rx"; 1499 status = "disabled"; 1500 }; 1501 1502 uart6: serial@998000 { 1503 compatible = "qcom,geni-uart"; 1504 reg = <0 0x00998000 0 0x4000>; 1505 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1506 clock-names = "se"; 1507 pinctrl-names = "default"; 1508 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1509 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1510 power-domains = <&rpmhpd SC7280_CX>; 1511 operating-points-v2 = <&qup_opp_table>; 1512 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1513 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1514 interconnect-names = "qup-core", "qup-config"; 1515 status = "disabled"; 1516 }; 1517 1518 i2c7: i2c@99c000 { 1519 compatible = "qcom,geni-i2c"; 1520 reg = <0 0x0099c000 0 0x4000>; 1521 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1522 clock-names = "se"; 1523 pinctrl-names = "default"; 1524 pinctrl-0 = <&qup_i2c7_data_clk>; 1525 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1526 #address-cells = <1>; 1527 #size-cells = <0>; 1528 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1529 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1530 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1531 interconnect-names = "qup-core", "qup-config", 1532 "qup-memory"; 1533 power-domains = <&rpmhpd SC7280_CX>; 1534 required-opps = <&rpmhpd_opp_low_svs>; 1535 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1536 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1537 dma-names = "tx", "rx"; 1538 status = "disabled"; 1539 }; 1540 1541 spi7: spi@99c000 { 1542 compatible = "qcom,geni-spi"; 1543 reg = <0 0x0099c000 0 0x4000>; 1544 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1545 clock-names = "se"; 1546 pinctrl-names = "default"; 1547 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1548 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1549 #address-cells = <1>; 1550 #size-cells = <0>; 1551 power-domains = <&rpmhpd SC7280_CX>; 1552 operating-points-v2 = <&qup_opp_table>; 1553 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1554 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1555 interconnect-names = "qup-core", "qup-config"; 1556 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1557 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1558 dma-names = "tx", "rx"; 1559 status = "disabled"; 1560 }; 1561 1562 uart7: serial@99c000 { 1563 compatible = "qcom,geni-uart"; 1564 reg = <0 0x0099c000 0 0x4000>; 1565 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1566 clock-names = "se"; 1567 pinctrl-names = "default"; 1568 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1569 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1570 power-domains = <&rpmhpd SC7280_CX>; 1571 operating-points-v2 = <&qup_opp_table>; 1572 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1573 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1574 interconnect-names = "qup-core", "qup-config"; 1575 status = "disabled"; 1576 }; 1577 }; 1578 1579 gpi_dma1: dma-controller@a00000 { 1580 #dma-cells = <3>; 1581 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1582 reg = <0 0x00a00000 0 0x60000>; 1583 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1584 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1585 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1586 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1587 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1588 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1589 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1590 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1591 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1592 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1593 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1595 dma-channels = <12>; 1596 dma-channel-mask = <0x1e>; 1597 iommus = <&apps_smmu 0x56 0x0>; 1598 status = "disabled"; 1599 }; 1600 1601 qupv3_id_1: geniqup@ac0000 { 1602 compatible = "qcom,geni-se-qup"; 1603 reg = <0 0x00ac0000 0 0x2000>; 1604 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1605 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1606 clock-names = "m-ahb", "s-ahb"; 1607 #address-cells = <2>; 1608 #size-cells = <2>; 1609 ranges; 1610 iommus = <&apps_smmu 0x43 0x0>; 1611 status = "disabled"; 1612 1613 i2c8: i2c@a80000 { 1614 compatible = "qcom,geni-i2c"; 1615 reg = <0 0x00a80000 0 0x4000>; 1616 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1617 clock-names = "se"; 1618 pinctrl-names = "default"; 1619 pinctrl-0 = <&qup_i2c8_data_clk>; 1620 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1621 #address-cells = <1>; 1622 #size-cells = <0>; 1623 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1624 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1625 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1626 interconnect-names = "qup-core", "qup-config", 1627 "qup-memory"; 1628 power-domains = <&rpmhpd SC7280_CX>; 1629 required-opps = <&rpmhpd_opp_low_svs>; 1630 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1631 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1632 dma-names = "tx", "rx"; 1633 status = "disabled"; 1634 }; 1635 1636 spi8: spi@a80000 { 1637 compatible = "qcom,geni-spi"; 1638 reg = <0 0x00a80000 0 0x4000>; 1639 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1640 clock-names = "se"; 1641 pinctrl-names = "default"; 1642 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1643 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1644 #address-cells = <1>; 1645 #size-cells = <0>; 1646 power-domains = <&rpmhpd SC7280_CX>; 1647 operating-points-v2 = <&qup_opp_table>; 1648 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1649 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1650 interconnect-names = "qup-core", "qup-config"; 1651 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1652 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1653 dma-names = "tx", "rx"; 1654 status = "disabled"; 1655 }; 1656 1657 uart8: serial@a80000 { 1658 compatible = "qcom,geni-uart"; 1659 reg = <0 0x00a80000 0 0x4000>; 1660 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1661 clock-names = "se"; 1662 pinctrl-names = "default"; 1663 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1664 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1665 power-domains = <&rpmhpd SC7280_CX>; 1666 operating-points-v2 = <&qup_opp_table>; 1667 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1668 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1669 interconnect-names = "qup-core", "qup-config"; 1670 status = "disabled"; 1671 }; 1672 1673 i2c9: i2c@a84000 { 1674 compatible = "qcom,geni-i2c"; 1675 reg = <0 0x00a84000 0 0x4000>; 1676 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1677 clock-names = "se"; 1678 pinctrl-names = "default"; 1679 pinctrl-0 = <&qup_i2c9_data_clk>; 1680 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1681 #address-cells = <1>; 1682 #size-cells = <0>; 1683 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1684 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1685 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1686 interconnect-names = "qup-core", "qup-config", 1687 "qup-memory"; 1688 power-domains = <&rpmhpd SC7280_CX>; 1689 required-opps = <&rpmhpd_opp_low_svs>; 1690 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1691 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1692 dma-names = "tx", "rx"; 1693 status = "disabled"; 1694 }; 1695 1696 spi9: spi@a84000 { 1697 compatible = "qcom,geni-spi"; 1698 reg = <0 0x00a84000 0 0x4000>; 1699 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1700 clock-names = "se"; 1701 pinctrl-names = "default"; 1702 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1703 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1704 #address-cells = <1>; 1705 #size-cells = <0>; 1706 power-domains = <&rpmhpd SC7280_CX>; 1707 operating-points-v2 = <&qup_opp_table>; 1708 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1709 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1710 interconnect-names = "qup-core", "qup-config"; 1711 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1712 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1713 dma-names = "tx", "rx"; 1714 status = "disabled"; 1715 }; 1716 1717 uart9: serial@a84000 { 1718 compatible = "qcom,geni-uart"; 1719 reg = <0 0x00a84000 0 0x4000>; 1720 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1721 clock-names = "se"; 1722 pinctrl-names = "default"; 1723 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1724 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1725 power-domains = <&rpmhpd SC7280_CX>; 1726 operating-points-v2 = <&qup_opp_table>; 1727 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1728 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1729 interconnect-names = "qup-core", "qup-config"; 1730 status = "disabled"; 1731 }; 1732 1733 i2c10: i2c@a88000 { 1734 compatible = "qcom,geni-i2c"; 1735 reg = <0 0x00a88000 0 0x4000>; 1736 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1737 clock-names = "se"; 1738 pinctrl-names = "default"; 1739 pinctrl-0 = <&qup_i2c10_data_clk>; 1740 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1741 #address-cells = <1>; 1742 #size-cells = <0>; 1743 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1744 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1745 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1746 interconnect-names = "qup-core", "qup-config", 1747 "qup-memory"; 1748 power-domains = <&rpmhpd SC7280_CX>; 1749 required-opps = <&rpmhpd_opp_low_svs>; 1750 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1751 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1752 dma-names = "tx", "rx"; 1753 status = "disabled"; 1754 }; 1755 1756 spi10: spi@a88000 { 1757 compatible = "qcom,geni-spi"; 1758 reg = <0 0x00a88000 0 0x4000>; 1759 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1760 clock-names = "se"; 1761 pinctrl-names = "default"; 1762 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1763 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1764 #address-cells = <1>; 1765 #size-cells = <0>; 1766 power-domains = <&rpmhpd SC7280_CX>; 1767 operating-points-v2 = <&qup_opp_table>; 1768 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1769 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1770 interconnect-names = "qup-core", "qup-config"; 1771 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1772 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1773 dma-names = "tx", "rx"; 1774 status = "disabled"; 1775 }; 1776 1777 uart10: serial@a88000 { 1778 compatible = "qcom,geni-uart"; 1779 reg = <0 0x00a88000 0 0x4000>; 1780 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1781 clock-names = "se"; 1782 pinctrl-names = "default"; 1783 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1784 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1785 power-domains = <&rpmhpd SC7280_CX>; 1786 operating-points-v2 = <&qup_opp_table>; 1787 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1788 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1789 interconnect-names = "qup-core", "qup-config"; 1790 status = "disabled"; 1791 }; 1792 1793 i2c11: i2c@a8c000 { 1794 compatible = "qcom,geni-i2c"; 1795 reg = <0 0x00a8c000 0 0x4000>; 1796 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1797 clock-names = "se"; 1798 pinctrl-names = "default"; 1799 pinctrl-0 = <&qup_i2c11_data_clk>; 1800 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1801 #address-cells = <1>; 1802 #size-cells = <0>; 1803 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1804 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1805 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1806 interconnect-names = "qup-core", "qup-config", 1807 "qup-memory"; 1808 power-domains = <&rpmhpd SC7280_CX>; 1809 required-opps = <&rpmhpd_opp_low_svs>; 1810 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1811 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1812 dma-names = "tx", "rx"; 1813 status = "disabled"; 1814 }; 1815 1816 spi11: spi@a8c000 { 1817 compatible = "qcom,geni-spi"; 1818 reg = <0 0x00a8c000 0 0x4000>; 1819 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1820 clock-names = "se"; 1821 pinctrl-names = "default"; 1822 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1823 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1824 #address-cells = <1>; 1825 #size-cells = <0>; 1826 power-domains = <&rpmhpd SC7280_CX>; 1827 operating-points-v2 = <&qup_opp_table>; 1828 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1829 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1830 interconnect-names = "qup-core", "qup-config"; 1831 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1832 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1833 dma-names = "tx", "rx"; 1834 status = "disabled"; 1835 }; 1836 1837 uart11: serial@a8c000 { 1838 compatible = "qcom,geni-uart"; 1839 reg = <0 0x00a8c000 0 0x4000>; 1840 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1841 clock-names = "se"; 1842 pinctrl-names = "default"; 1843 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1844 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1845 power-domains = <&rpmhpd SC7280_CX>; 1846 operating-points-v2 = <&qup_opp_table>; 1847 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1848 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1849 interconnect-names = "qup-core", "qup-config"; 1850 status = "disabled"; 1851 }; 1852 1853 i2c12: i2c@a90000 { 1854 compatible = "qcom,geni-i2c"; 1855 reg = <0 0x00a90000 0 0x4000>; 1856 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1857 clock-names = "se"; 1858 pinctrl-names = "default"; 1859 pinctrl-0 = <&qup_i2c12_data_clk>; 1860 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1861 #address-cells = <1>; 1862 #size-cells = <0>; 1863 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1864 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1865 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1866 interconnect-names = "qup-core", "qup-config", 1867 "qup-memory"; 1868 power-domains = <&rpmhpd SC7280_CX>; 1869 required-opps = <&rpmhpd_opp_low_svs>; 1870 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1871 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1872 dma-names = "tx", "rx"; 1873 status = "disabled"; 1874 }; 1875 1876 spi12: spi@a90000 { 1877 compatible = "qcom,geni-spi"; 1878 reg = <0 0x00a90000 0 0x4000>; 1879 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1880 clock-names = "se"; 1881 pinctrl-names = "default"; 1882 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1883 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1884 #address-cells = <1>; 1885 #size-cells = <0>; 1886 power-domains = <&rpmhpd SC7280_CX>; 1887 operating-points-v2 = <&qup_opp_table>; 1888 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1889 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1890 interconnect-names = "qup-core", "qup-config"; 1891 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1892 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1893 dma-names = "tx", "rx"; 1894 status = "disabled"; 1895 }; 1896 1897 uart12: serial@a90000 { 1898 compatible = "qcom,geni-uart"; 1899 reg = <0 0x00a90000 0 0x4000>; 1900 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1901 clock-names = "se"; 1902 pinctrl-names = "default"; 1903 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1904 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1905 power-domains = <&rpmhpd SC7280_CX>; 1906 operating-points-v2 = <&qup_opp_table>; 1907 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1908 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1909 interconnect-names = "qup-core", "qup-config"; 1910 status = "disabled"; 1911 }; 1912 1913 i2c13: i2c@a94000 { 1914 compatible = "qcom,geni-i2c"; 1915 reg = <0 0x00a94000 0 0x4000>; 1916 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1917 clock-names = "se"; 1918 pinctrl-names = "default"; 1919 pinctrl-0 = <&qup_i2c13_data_clk>; 1920 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1921 #address-cells = <1>; 1922 #size-cells = <0>; 1923 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1924 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1925 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1926 interconnect-names = "qup-core", "qup-config", 1927 "qup-memory"; 1928 power-domains = <&rpmhpd SC7280_CX>; 1929 required-opps = <&rpmhpd_opp_low_svs>; 1930 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1931 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1932 dma-names = "tx", "rx"; 1933 status = "disabled"; 1934 }; 1935 1936 spi13: spi@a94000 { 1937 compatible = "qcom,geni-spi"; 1938 reg = <0 0x00a94000 0 0x4000>; 1939 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1940 clock-names = "se"; 1941 pinctrl-names = "default"; 1942 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1943 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1944 #address-cells = <1>; 1945 #size-cells = <0>; 1946 power-domains = <&rpmhpd SC7280_CX>; 1947 operating-points-v2 = <&qup_opp_table>; 1948 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1949 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1950 interconnect-names = "qup-core", "qup-config"; 1951 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1952 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1953 dma-names = "tx", "rx"; 1954 status = "disabled"; 1955 }; 1956 1957 uart13: serial@a94000 { 1958 compatible = "qcom,geni-uart"; 1959 reg = <0 0x00a94000 0 0x4000>; 1960 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1961 clock-names = "se"; 1962 pinctrl-names = "default"; 1963 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1964 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1965 power-domains = <&rpmhpd SC7280_CX>; 1966 operating-points-v2 = <&qup_opp_table>; 1967 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1968 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1969 interconnect-names = "qup-core", "qup-config"; 1970 status = "disabled"; 1971 }; 1972 1973 i2c14: i2c@a98000 { 1974 compatible = "qcom,geni-i2c"; 1975 reg = <0 0x00a98000 0 0x4000>; 1976 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1977 clock-names = "se"; 1978 pinctrl-names = "default"; 1979 pinctrl-0 = <&qup_i2c14_data_clk>; 1980 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1981 #address-cells = <1>; 1982 #size-cells = <0>; 1983 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1984 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1985 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1986 interconnect-names = "qup-core", "qup-config", 1987 "qup-memory"; 1988 power-domains = <&rpmhpd SC7280_CX>; 1989 required-opps = <&rpmhpd_opp_low_svs>; 1990 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1991 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1992 dma-names = "tx", "rx"; 1993 status = "disabled"; 1994 }; 1995 1996 spi14: spi@a98000 { 1997 compatible = "qcom,geni-spi"; 1998 reg = <0 0x00a98000 0 0x4000>; 1999 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2000 clock-names = "se"; 2001 pinctrl-names = "default"; 2002 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 2003 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 2004 #address-cells = <1>; 2005 #size-cells = <0>; 2006 power-domains = <&rpmhpd SC7280_CX>; 2007 operating-points-v2 = <&qup_opp_table>; 2008 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2009 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2010 interconnect-names = "qup-core", "qup-config"; 2011 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2012 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2013 dma-names = "tx", "rx"; 2014 status = "disabled"; 2015 }; 2016 2017 uart14: serial@a98000 { 2018 compatible = "qcom,geni-uart"; 2019 reg = <0 0x00a98000 0 0x4000>; 2020 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2021 clock-names = "se"; 2022 pinctrl-names = "default"; 2023 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 2024 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 2025 power-domains = <&rpmhpd SC7280_CX>; 2026 operating-points-v2 = <&qup_opp_table>; 2027 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2028 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2029 interconnect-names = "qup-core", "qup-config"; 2030 status = "disabled"; 2031 }; 2032 2033 i2c15: i2c@a9c000 { 2034 compatible = "qcom,geni-i2c"; 2035 reg = <0 0x00a9c000 0 0x4000>; 2036 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2037 clock-names = "se"; 2038 pinctrl-names = "default"; 2039 pinctrl-0 = <&qup_i2c15_data_clk>; 2040 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2041 #address-cells = <1>; 2042 #size-cells = <0>; 2043 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2044 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 2045 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2046 interconnect-names = "qup-core", "qup-config", 2047 "qup-memory"; 2048 power-domains = <&rpmhpd SC7280_CX>; 2049 required-opps = <&rpmhpd_opp_low_svs>; 2050 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2051 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2052 dma-names = "tx", "rx"; 2053 status = "disabled"; 2054 }; 2055 2056 spi15: spi@a9c000 { 2057 compatible = "qcom,geni-spi"; 2058 reg = <0 0x00a9c000 0 0x4000>; 2059 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2060 clock-names = "se"; 2061 pinctrl-names = "default"; 2062 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 2063 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2064 #address-cells = <1>; 2065 #size-cells = <0>; 2066 power-domains = <&rpmhpd SC7280_CX>; 2067 operating-points-v2 = <&qup_opp_table>; 2068 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2069 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2070 interconnect-names = "qup-core", "qup-config"; 2071 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2072 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2073 dma-names = "tx", "rx"; 2074 status = "disabled"; 2075 }; 2076 2077 uart15: serial@a9c000 { 2078 compatible = "qcom,geni-uart"; 2079 reg = <0 0x00a9c000 0 0x4000>; 2080 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2081 clock-names = "se"; 2082 pinctrl-names = "default"; 2083 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 2084 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2085 power-domains = <&rpmhpd SC7280_CX>; 2086 operating-points-v2 = <&qup_opp_table>; 2087 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2088 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2089 interconnect-names = "qup-core", "qup-config"; 2090 status = "disabled"; 2091 }; 2092 }; 2093 2094 rng: rng@10d3000 { 2095 compatible = "qcom,sc7280-trng", "qcom,trng"; 2096 reg = <0 0x010d3000 0 0x1000>; 2097 }; 2098 2099 cnoc2: interconnect@1500000 { 2100 reg = <0 0x01500000 0 0x1000>; 2101 compatible = "qcom,sc7280-cnoc2"; 2102 #interconnect-cells = <2>; 2103 qcom,bcm-voters = <&apps_bcm_voter>; 2104 }; 2105 2106 cnoc3: interconnect@1502000 { 2107 reg = <0 0x01502000 0 0x1000>; 2108 compatible = "qcom,sc7280-cnoc3"; 2109 #interconnect-cells = <2>; 2110 qcom,bcm-voters = <&apps_bcm_voter>; 2111 }; 2112 2113 mc_virt: interconnect@1580000 { 2114 reg = <0 0x01580000 0 0x4>; 2115 compatible = "qcom,sc7280-mc-virt"; 2116 #interconnect-cells = <2>; 2117 qcom,bcm-voters = <&apps_bcm_voter>; 2118 }; 2119 2120 system_noc: interconnect@1680000 { 2121 reg = <0 0x01680000 0 0x15480>; 2122 compatible = "qcom,sc7280-system-noc"; 2123 #interconnect-cells = <2>; 2124 qcom,bcm-voters = <&apps_bcm_voter>; 2125 }; 2126 2127 aggre1_noc: interconnect@16e0000 { 2128 compatible = "qcom,sc7280-aggre1-noc"; 2129 reg = <0 0x016e0000 0 0x1c080>; 2130 #interconnect-cells = <2>; 2131 qcom,bcm-voters = <&apps_bcm_voter>; 2132 }; 2133 2134 aggre2_noc: interconnect@1700000 { 2135 reg = <0 0x01700000 0 0x2b080>; 2136 compatible = "qcom,sc7280-aggre2-noc"; 2137 #interconnect-cells = <2>; 2138 qcom,bcm-voters = <&apps_bcm_voter>; 2139 }; 2140 2141 mmss_noc: interconnect@1740000 { 2142 reg = <0 0x01740000 0 0x1e080>; 2143 compatible = "qcom,sc7280-mmss-noc"; 2144 #interconnect-cells = <2>; 2145 qcom,bcm-voters = <&apps_bcm_voter>; 2146 }; 2147 2148 wifi: wifi@17a10040 { 2149 compatible = "qcom,wcn6750-wifi"; 2150 reg = <0 0x17a10040 0 0x0>; 2151 iommus = <&apps_smmu 0x1c00 0x1>; 2152 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 2153 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 2154 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 2155 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 2156 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 2157 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 2158 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 2159 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 2160 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 2161 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 2162 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 2163 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 2164 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 2165 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 2166 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 2167 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 2168 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 2169 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 2170 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 2171 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 2172 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 2173 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 2174 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 2175 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 2176 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 2177 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 2178 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 2179 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 2180 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2181 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2182 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2183 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2184 qcom,rproc = <&remoteproc_wpss>; 2185 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2186 status = "disabled"; 2187 qcom,smem-states = <&wlan_smp2p_out 0>; 2188 qcom,smem-state-names = "wlan-smp2p-out"; 2189 }; 2190 2191 pcie1: pcie@1c08000 { 2192 compatible = "qcom,pcie-sc7280"; 2193 reg = <0 0x01c08000 0 0x3000>, 2194 <0 0x40000000 0 0xf1d>, 2195 <0 0x40000f20 0 0xa8>, 2196 <0 0x40001000 0 0x1000>, 2197 <0 0x40100000 0 0x100000>; 2198 2199 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2200 device_type = "pci"; 2201 linux,pci-domain = <1>; 2202 bus-range = <0x00 0xff>; 2203 num-lanes = <2>; 2204 2205 #address-cells = <3>; 2206 #size-cells = <2>; 2207 2208 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2209 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2210 2211 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2212 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2213 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2214 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2215 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2216 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2217 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2218 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 2219 interrupt-names = "msi0", "msi1", "msi2", "msi3", 2220 "msi4", "msi5", "msi6", "msi7"; 2221 #interrupt-cells = <1>; 2222 interrupt-map-mask = <0 0 0 0x7>; 2223 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, 2224 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, 2225 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, 2226 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; 2227 2228 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2229 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2230 <&pcie1_phy>, 2231 <&rpmhcc RPMH_CXO_CLK>, 2232 <&gcc GCC_PCIE_1_AUX_CLK>, 2233 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2234 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2235 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2236 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2237 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2238 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2239 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2240 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2241 2242 clock-names = "pipe", 2243 "pipe_mux", 2244 "phy_pipe", 2245 "ref", 2246 "aux", 2247 "cfg", 2248 "bus_master", 2249 "bus_slave", 2250 "slave_q2a", 2251 "tbu", 2252 "ddrss_sf_tbu", 2253 "aggre0", 2254 "aggre1"; 2255 2256 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2257 assigned-clock-rates = <19200000>; 2258 2259 resets = <&gcc GCC_PCIE_1_BCR>; 2260 reset-names = "pci"; 2261 2262 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2263 2264 phys = <&pcie1_phy>; 2265 phy-names = "pciephy"; 2266 2267 pinctrl-names = "default"; 2268 pinctrl-0 = <&pcie1_clkreq_n>; 2269 2270 dma-coherent; 2271 2272 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2273 <0x100 &apps_smmu 0x1c81 0x1>; 2274 2275 status = "disabled"; 2276 2277 pcie@0 { 2278 device_type = "pci"; 2279 reg = <0x0 0x0 0x0 0x0 0x0>; 2280 bus-range = <0x01 0xff>; 2281 2282 #address-cells = <3>; 2283 #size-cells = <2>; 2284 ranges; 2285 }; 2286 }; 2287 2288 pcie1_phy: phy@1c0e000 { 2289 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2290 reg = <0 0x01c0e000 0 0x1000>; 2291 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2292 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2293 <&gcc GCC_PCIE_CLKREF_EN>, 2294 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, 2295 <&gcc GCC_PCIE_1_PIPE_CLK>; 2296 clock-names = "aux", 2297 "cfg_ahb", 2298 "ref", 2299 "refgen", 2300 "pipe"; 2301 2302 clock-output-names = "pcie_1_pipe_clk"; 2303 #clock-cells = <0>; 2304 2305 #phy-cells = <0>; 2306 2307 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2308 reset-names = "phy"; 2309 2310 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2311 assigned-clock-rates = <100000000>; 2312 2313 status = "disabled"; 2314 }; 2315 2316 ufs_mem_hc: ufs@1d84000 { 2317 compatible = "qcom,sc7280-ufshc", "qcom,ufshc", 2318 "jedec,ufs-2.0"; 2319 reg = <0x0 0x01d84000 0x0 0x3000>; 2320 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2321 phys = <&ufs_mem_phy>; 2322 phy-names = "ufsphy"; 2323 lanes-per-direction = <2>; 2324 #reset-cells = <1>; 2325 resets = <&gcc GCC_UFS_PHY_BCR>; 2326 reset-names = "rst"; 2327 2328 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 2329 required-opps = <&rpmhpd_opp_nom>; 2330 2331 iommus = <&apps_smmu 0x80 0x0>; 2332 dma-coherent; 2333 2334 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2335 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2336 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2337 &cnoc2 SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 2338 interconnect-names = "ufs-ddr", "cpu-ufs"; 2339 2340 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2341 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2342 <&gcc GCC_UFS_PHY_AHB_CLK>, 2343 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2344 <&rpmhcc RPMH_CXO_CLK>, 2345 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2346 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2347 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2348 clock-names = "core_clk", 2349 "bus_aggr_clk", 2350 "iface_clk", 2351 "core_clk_unipro", 2352 "ref_clk", 2353 "tx_lane0_sync_clk", 2354 "rx_lane0_sync_clk", 2355 "rx_lane1_sync_clk"; 2356 freq-table-hz = 2357 <75000000 300000000>, 2358 <0 0>, 2359 <0 0>, 2360 <75000000 300000000>, 2361 <0 0>, 2362 <0 0>, 2363 <0 0>, 2364 <0 0>; 2365 qcom,ice = <&ice>; 2366 2367 status = "disabled"; 2368 }; 2369 2370 ufs_mem_phy: phy@1d87000 { 2371 compatible = "qcom,sc7280-qmp-ufs-phy"; 2372 reg = <0x0 0x01d87000 0x0 0xe00>; 2373 clocks = <&rpmhcc RPMH_CXO_CLK>, 2374 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2375 <&gcc GCC_UFS_1_CLKREF_EN>; 2376 clock-names = "ref", "ref_aux", "qref"; 2377 2378 power-domains = <&rpmhpd SC7280_MX>; 2379 2380 resets = <&ufs_mem_hc 0>; 2381 reset-names = "ufsphy"; 2382 2383 #clock-cells = <1>; 2384 #phy-cells = <0>; 2385 2386 status = "disabled"; 2387 }; 2388 2389 ice: crypto@1d88000 { 2390 compatible = "qcom,sc7280-inline-crypto-engine", 2391 "qcom,inline-crypto-engine"; 2392 reg = <0 0x01d88000 0 0x8000>; 2393 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2394 }; 2395 2396 cryptobam: dma-controller@1dc4000 { 2397 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2398 reg = <0x0 0x01dc4000 0x0 0x28000>; 2399 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2400 #dma-cells = <1>; 2401 iommus = <&apps_smmu 0x4e4 0x0011>, 2402 <&apps_smmu 0x4e6 0x0011>; 2403 qcom,ee = <0>; 2404 qcom,controlled-remotely; 2405 num-channels = <16>; 2406 qcom,num-ees = <4>; 2407 }; 2408 2409 crypto: crypto@1dfa000 { 2410 compatible = "qcom,sc7280-qce", "qcom,sm8150-qce", "qcom,qce"; 2411 reg = <0x0 0x01dfa000 0x0 0x6000>; 2412 dmas = <&cryptobam 4>, <&cryptobam 5>; 2413 dma-names = "rx", "tx"; 2414 iommus = <&apps_smmu 0x4e4 0x0011>, 2415 <&apps_smmu 0x4e4 0x0011>; 2416 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 2417 interconnect-names = "memory"; 2418 }; 2419 2420 ipa: ipa@1e40000 { 2421 compatible = "qcom,sc7280-ipa"; 2422 2423 iommus = <&apps_smmu 0x480 0x0>, 2424 <&apps_smmu 0x482 0x0>; 2425 reg = <0 0x01e40000 0 0x8000>, 2426 <0 0x01e50000 0 0x4ad0>, 2427 <0 0x01e04000 0 0x23000>; 2428 reg-names = "ipa-reg", 2429 "ipa-shared", 2430 "gsi"; 2431 2432 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2433 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2434 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2435 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2436 interrupt-names = "ipa", 2437 "gsi", 2438 "ipa-clock-query", 2439 "ipa-setup-ready"; 2440 2441 clocks = <&rpmhcc RPMH_IPA_CLK>; 2442 clock-names = "core"; 2443 2444 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2445 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2446 interconnect-names = "memory", 2447 "config"; 2448 2449 qcom,qmp = <&aoss_qmp>; 2450 2451 qcom,smem-states = <&ipa_smp2p_out 0>, 2452 <&ipa_smp2p_out 1>; 2453 qcom,smem-state-names = "ipa-clock-enabled-valid", 2454 "ipa-clock-enabled"; 2455 2456 status = "disabled"; 2457 }; 2458 2459 tcsr_mutex: hwlock@1f40000 { 2460 compatible = "qcom,tcsr-mutex"; 2461 reg = <0 0x01f40000 0 0x20000>; 2462 #hwlock-cells = <1>; 2463 }; 2464 2465 tcsr_1: syscon@1f60000 { 2466 compatible = "qcom,sc7280-tcsr", "syscon"; 2467 reg = <0 0x01f60000 0 0x20000>; 2468 }; 2469 2470 tcsr_2: syscon@1fc0000 { 2471 compatible = "qcom,sc7280-tcsr", "syscon"; 2472 reg = <0 0x01fc0000 0 0x30000>; 2473 }; 2474 2475 lpasscc: lpasscc@3000000 { 2476 compatible = "qcom,sc7280-lpasscc"; 2477 reg = <0 0x03000000 0 0x40>, 2478 <0 0x03c04000 0 0x4>; 2479 reg-names = "qdsp6ss", "top_cc"; 2480 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2481 clock-names = "iface"; 2482 #clock-cells = <1>; 2483 status = "reserved"; /* Owned by ADSP firmware */ 2484 }; 2485 2486 lpass_rx_macro: codec@3200000 { 2487 compatible = "qcom,sc7280-lpass-rx-macro"; 2488 reg = <0 0x03200000 0 0x1000>; 2489 2490 pinctrl-names = "default"; 2491 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2492 2493 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2494 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2495 <&lpass_va_macro>; 2496 clock-names = "mclk", "npl", "fsgen"; 2497 2498 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2499 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2500 power-domain-names = "macro", "dcodec"; 2501 2502 #clock-cells = <0>; 2503 #sound-dai-cells = <1>; 2504 2505 status = "disabled"; 2506 }; 2507 2508 swr0: soundwire@3210000 { 2509 compatible = "qcom,soundwire-v1.6.0"; 2510 reg = <0 0x03210000 0 0x2000>; 2511 2512 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2513 clocks = <&lpass_rx_macro>; 2514 clock-names = "iface"; 2515 2516 qcom,din-ports = <0>; 2517 qcom,dout-ports = <5>; 2518 2519 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2520 reset-names = "swr_audio_cgcr"; 2521 2522 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2523 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2524 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2525 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2526 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2527 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2528 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2529 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2530 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2531 2532 #sound-dai-cells = <1>; 2533 #address-cells = <2>; 2534 #size-cells = <0>; 2535 2536 status = "disabled"; 2537 }; 2538 2539 lpass_tx_macro: codec@3220000 { 2540 compatible = "qcom,sc7280-lpass-tx-macro"; 2541 reg = <0 0x03220000 0 0x1000>; 2542 2543 pinctrl-names = "default"; 2544 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2545 2546 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2547 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2548 <&lpass_va_macro>; 2549 clock-names = "mclk", "npl", "fsgen"; 2550 2551 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2552 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2553 power-domain-names = "macro", "dcodec"; 2554 2555 #clock-cells = <0>; 2556 #sound-dai-cells = <1>; 2557 2558 status = "disabled"; 2559 }; 2560 2561 swr1: soundwire@3230000 { 2562 compatible = "qcom,soundwire-v1.6.0"; 2563 reg = <0 0x03230000 0 0x2000>; 2564 2565 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2566 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2567 clocks = <&lpass_tx_macro>; 2568 clock-names = "iface"; 2569 2570 qcom,din-ports = <3>; 2571 qcom,dout-ports = <0>; 2572 2573 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2574 reset-names = "swr_audio_cgcr"; 2575 2576 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2577 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2578 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2579 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2580 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2581 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2582 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2583 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2584 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2585 2586 #sound-dai-cells = <1>; 2587 #address-cells = <2>; 2588 #size-cells = <0>; 2589 2590 status = "disabled"; 2591 }; 2592 2593 lpass_audiocc: clock-controller@3300000 { 2594 compatible = "qcom,sc7280-lpassaudiocc"; 2595 reg = <0 0x03300000 0 0x30000>, 2596 <0 0x032a9000 0 0x1000>; 2597 clocks = <&rpmhcc RPMH_CXO_CLK>, 2598 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2599 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2600 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2601 #clock-cells = <1>; 2602 #power-domain-cells = <1>; 2603 #reset-cells = <1>; 2604 }; 2605 2606 lpass_va_macro: codec@3370000 { 2607 compatible = "qcom,sc7280-lpass-va-macro"; 2608 reg = <0 0x03370000 0 0x1000>; 2609 2610 pinctrl-names = "default"; 2611 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>; 2612 2613 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2614 clock-names = "mclk"; 2615 2616 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2617 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2618 power-domain-names = "macro", "dcodec"; 2619 2620 #clock-cells = <0>; 2621 #sound-dai-cells = <1>; 2622 2623 status = "disabled"; 2624 }; 2625 2626 lpass_aon: clock-controller@3380000 { 2627 compatible = "qcom,sc7280-lpassaoncc"; 2628 reg = <0 0x03380000 0 0x30000>; 2629 clocks = <&rpmhcc RPMH_CXO_CLK>, 2630 <&rpmhcc RPMH_CXO_CLK_A>, 2631 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2632 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2633 #clock-cells = <1>; 2634 #power-domain-cells = <1>; 2635 status = "reserved"; /* Owned by ADSP firmware */ 2636 }; 2637 2638 lpass_core: clock-controller@3900000 { 2639 compatible = "qcom,sc7280-lpasscorecc"; 2640 reg = <0 0x03900000 0 0x50000>; 2641 clocks = <&rpmhcc RPMH_CXO_CLK>; 2642 clock-names = "bi_tcxo"; 2643 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2644 #clock-cells = <1>; 2645 #power-domain-cells = <1>; 2646 status = "reserved"; /* Owned by ADSP firmware */ 2647 }; 2648 2649 lpass_cpu: audio@3987000 { 2650 compatible = "qcom,sc7280-lpass-cpu"; 2651 2652 reg = <0 0x03987000 0 0x68000>, 2653 <0 0x03b00000 0 0x29000>, 2654 <0 0x03260000 0 0xc000>, 2655 <0 0x03280000 0 0x29000>, 2656 <0 0x03340000 0 0x29000>, 2657 <0 0x0336c000 0 0x3000>; 2658 reg-names = "lpass-hdmiif", 2659 "lpass-lpaif", 2660 "lpass-rxtx-cdc-dma-lpm", 2661 "lpass-rxtx-lpaif", 2662 "lpass-va-lpaif", 2663 "lpass-va-cdc-dma-lpm"; 2664 2665 iommus = <&apps_smmu 0x1820 0>, 2666 <&apps_smmu 0x1821 0>, 2667 <&apps_smmu 0x1832 0>; 2668 2669 power-domains = <&rpmhpd SC7280_LCX>; 2670 power-domain-names = "lcx"; 2671 required-opps = <&rpmhpd_opp_nom>; 2672 2673 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2674 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2675 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2676 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2677 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2678 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2679 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2680 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2681 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2682 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2683 clock-names = "aon_cc_audio_hm_h", 2684 "audio_cc_ext_mclk0", 2685 "core_cc_sysnoc_mport_core", 2686 "core_cc_ext_if0_ibit", 2687 "core_cc_ext_if1_ibit", 2688 "audio_cc_codec_mem", 2689 "audio_cc_codec_mem0", 2690 "audio_cc_codec_mem1", 2691 "audio_cc_codec_mem2", 2692 "aon_cc_va_mem0"; 2693 2694 #sound-dai-cells = <1>; 2695 #address-cells = <1>; 2696 #size-cells = <0>; 2697 2698 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2699 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2700 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2701 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2702 interrupt-names = "lpass-irq-lpaif", 2703 "lpass-irq-hdmi", 2704 "lpass-irq-vaif", 2705 "lpass-irq-rxtxif"; 2706 2707 status = "disabled"; 2708 }; 2709 2710 slimbam: dma-controller@3a84000 { 2711 compatible = "qcom,bam-v1.7.0"; 2712 reg = <0 0x03a84000 0 0x20000>; 2713 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 2714 #dma-cells = <1>; 2715 qcom,controlled-remotely; 2716 num-channels = <31>; 2717 qcom,ee = <1>; 2718 qcom,num-ees = <2>; 2719 iommus = <&apps_smmu 0x1826 0x0>; 2720 status = "disabled"; 2721 }; 2722 2723 slim: slim-ngd@3ac0000 { 2724 compatible = "qcom,slim-ngd-v1.5.0"; 2725 reg = <0 0x03ac0000 0 0x2c000>; 2726 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 2727 dmas = <&slimbam 3>, <&slimbam 4>; 2728 dma-names = "rx", "tx"; 2729 iommus = <&apps_smmu 0x1826 0x0>; 2730 #address-cells = <1>; 2731 #size-cells = <0>; 2732 status = "disabled"; 2733 }; 2734 2735 lpass_hm: clock-controller@3c00000 { 2736 compatible = "qcom,sc7280-lpasshm"; 2737 reg = <0 0x03c00000 0 0x28>; 2738 clocks = <&rpmhcc RPMH_CXO_CLK>; 2739 clock-names = "bi_tcxo"; 2740 #clock-cells = <1>; 2741 #power-domain-cells = <1>; 2742 status = "reserved"; /* Owned by ADSP firmware */ 2743 }; 2744 2745 lpass_ag_noc: interconnect@3c40000 { 2746 reg = <0 0x03c40000 0 0xf080>; 2747 compatible = "qcom,sc7280-lpass-ag-noc"; 2748 #interconnect-cells = <2>; 2749 qcom,bcm-voters = <&apps_bcm_voter>; 2750 }; 2751 2752 lpass_tlmm: pinctrl@33c0000 { 2753 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 2754 reg = <0 0x033c0000 0x0 0x20000>, 2755 <0 0x03550000 0x0 0x10000>; 2756 gpio-controller; 2757 #gpio-cells = <2>; 2758 gpio-ranges = <&lpass_tlmm 0 0 15>; 2759 2760 lpass_dmic01_clk: dmic01-clk-state { 2761 pins = "gpio6"; 2762 function = "dmic1_clk"; 2763 }; 2764 2765 lpass_dmic01_data: dmic01-data-state { 2766 pins = "gpio7"; 2767 function = "dmic1_data"; 2768 }; 2769 2770 lpass_dmic23_clk: dmic23-clk-state { 2771 pins = "gpio8"; 2772 function = "dmic2_clk"; 2773 }; 2774 2775 lpass_dmic23_data: dmic23-data-state { 2776 pins = "gpio9"; 2777 function = "dmic2_data"; 2778 }; 2779 2780 lpass_rx_swr_clk: rx-swr-clk-state { 2781 pins = "gpio3"; 2782 function = "swr_rx_clk"; 2783 }; 2784 2785 lpass_rx_swr_data: rx-swr-data-state { 2786 pins = "gpio4", "gpio5"; 2787 function = "swr_rx_data"; 2788 }; 2789 2790 lpass_tx_swr_clk: tx-swr-clk-state { 2791 pins = "gpio0"; 2792 function = "swr_tx_clk"; 2793 }; 2794 2795 lpass_tx_swr_data: tx-swr-data-state { 2796 pins = "gpio1", "gpio2", "gpio14"; 2797 function = "swr_tx_data"; 2798 }; 2799 }; 2800 2801 gpu: gpu@3d00000 { 2802 compatible = "qcom,adreno-635.0", "qcom,adreno"; 2803 reg = <0 0x03d00000 0 0x40000>, 2804 <0 0x03d9e000 0 0x1000>, 2805 <0 0x03d61000 0 0x800>; 2806 reg-names = "kgsl_3d0_reg_memory", 2807 "cx_mem", 2808 "cx_dbgc"; 2809 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2810 iommus = <&adreno_smmu 0 0x400>, 2811 <&adreno_smmu 1 0x400>; 2812 operating-points-v2 = <&gpu_opp_table>; 2813 qcom,gmu = <&gmu>; 2814 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2815 interconnect-names = "gfx-mem"; 2816 #cooling-cells = <2>; 2817 2818 nvmem-cells = <&gpu_speed_bin>; 2819 nvmem-cell-names = "speed_bin"; 2820 2821 gpu_zap_shader: zap-shader { 2822 memory-region = <&gpu_zap_mem>; 2823 }; 2824 2825 gpu_opp_table: opp-table { 2826 compatible = "operating-points-v2"; 2827 2828 opp-315000000 { 2829 opp-hz = /bits/ 64 <315000000>; 2830 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2831 opp-peak-kBps = <1804000>; 2832 opp-supported-hw = <0x07>; 2833 }; 2834 2835 opp-450000000 { 2836 opp-hz = /bits/ 64 <450000000>; 2837 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2838 opp-peak-kBps = <4068000>; 2839 opp-supported-hw = <0x07>; 2840 }; 2841 2842 /* Only applicable for SKUs which has 550Mhz as Fmax */ 2843 opp-550000000-0 { 2844 opp-hz = /bits/ 64 <550000000>; 2845 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2846 opp-peak-kBps = <8368000>; 2847 opp-supported-hw = <0x01>; 2848 }; 2849 2850 opp-550000000-1 { 2851 opp-hz = /bits/ 64 <550000000>; 2852 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2853 opp-peak-kBps = <6832000>; 2854 opp-supported-hw = <0x06>; 2855 }; 2856 2857 opp-608000000 { 2858 opp-hz = /bits/ 64 <608000000>; 2859 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2860 opp-peak-kBps = <8368000>; 2861 opp-supported-hw = <0x06>; 2862 }; 2863 2864 opp-700000000 { 2865 opp-hz = /bits/ 64 <700000000>; 2866 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2867 opp-peak-kBps = <8532000>; 2868 opp-supported-hw = <0x06>; 2869 }; 2870 2871 opp-812000000 { 2872 opp-hz = /bits/ 64 <812000000>; 2873 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2874 opp-peak-kBps = <8532000>; 2875 opp-supported-hw = <0x06>; 2876 }; 2877 2878 opp-840000000 { 2879 opp-hz = /bits/ 64 <840000000>; 2880 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2881 opp-peak-kBps = <8532000>; 2882 opp-supported-hw = <0x02>; 2883 }; 2884 2885 opp-900000000 { 2886 opp-hz = /bits/ 64 <900000000>; 2887 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2888 opp-peak-kBps = <8532000>; 2889 opp-supported-hw = <0x02>; 2890 }; 2891 }; 2892 }; 2893 2894 gmu: gmu@3d6a000 { 2895 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 2896 reg = <0 0x03d6a000 0 0x34000>, 2897 <0 0x3de0000 0 0x10000>, 2898 <0 0x0b290000 0 0x10000>; 2899 reg-names = "gmu", "rscc", "gmu_pdc"; 2900 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2901 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2902 interrupt-names = "hfi", "gmu"; 2903 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2904 <&gpucc GPU_CC_CXO_CLK>, 2905 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2906 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2907 <&gpucc GPU_CC_AHB_CLK>, 2908 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2909 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2910 clock-names = "gmu", 2911 "cxo", 2912 "axi", 2913 "memnoc", 2914 "ahb", 2915 "hub", 2916 "smmu_vote"; 2917 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2918 <&gpucc GPU_CC_GX_GDSC>; 2919 power-domain-names = "cx", 2920 "gx"; 2921 iommus = <&adreno_smmu 5 0x400>; 2922 operating-points-v2 = <&gmu_opp_table>; 2923 2924 gmu_opp_table: opp-table { 2925 compatible = "operating-points-v2"; 2926 2927 opp-200000000 { 2928 opp-hz = /bits/ 64 <200000000>; 2929 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2930 }; 2931 }; 2932 }; 2933 2934 gpucc: clock-controller@3d90000 { 2935 compatible = "qcom,sc7280-gpucc"; 2936 reg = <0 0x03d90000 0 0x9000>; 2937 clocks = <&rpmhcc RPMH_CXO_CLK>, 2938 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2939 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2940 clock-names = "bi_tcxo", 2941 "gcc_gpu_gpll0_clk_src", 2942 "gcc_gpu_gpll0_div_clk_src"; 2943 #clock-cells = <1>; 2944 #reset-cells = <1>; 2945 #power-domain-cells = <1>; 2946 }; 2947 2948 dma@117f000 { 2949 compatible = "qcom,sc7280-dcc", "qcom,dcc"; 2950 reg = <0x0 0x0117f000 0x0 0x1000>, 2951 <0x0 0x01112000 0x0 0x6000>; 2952 }; 2953 2954 adreno_smmu: iommu@3da0000 { 2955 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", 2956 "qcom,smmu-500", "arm,mmu-500"; 2957 reg = <0 0x03da0000 0 0x20000>; 2958 #iommu-cells = <2>; 2959 #global-interrupts = <2>; 2960 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2961 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 2962 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2963 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2964 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2965 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2966 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2967 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2968 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2969 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2970 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2971 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2972 2973 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2974 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2975 <&gpucc GPU_CC_AHB_CLK>, 2976 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2977 <&gpucc GPU_CC_CX_GMU_CLK>, 2978 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2979 <&gpucc GPU_CC_HUB_AON_CLK>; 2980 clock-names = "gcc_gpu_memnoc_gfx_clk", 2981 "gcc_gpu_snoc_dvm_gfx_clk", 2982 "gpu_cc_ahb_clk", 2983 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2984 "gpu_cc_cx_gmu_clk", 2985 "gpu_cc_hub_cx_int_clk", 2986 "gpu_cc_hub_aon_clk"; 2987 2988 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2989 dma-coherent; 2990 }; 2991 2992 remoteproc_mpss: remoteproc@4080000 { 2993 compatible = "qcom,sc7280-mpss-pas"; 2994 reg = <0 0x04080000 0 0x10000>; 2995 2996 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2997 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2998 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2999 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3000 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3001 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3002 interrupt-names = "wdog", "fatal", "ready", "handover", 3003 "stop-ack", "shutdown-ack"; 3004 3005 clocks = <&rpmhcc RPMH_CXO_CLK>; 3006 clock-names = "xo"; 3007 3008 power-domains = <&rpmhpd SC7280_CX>, 3009 <&rpmhpd SC7280_MSS>; 3010 power-domain-names = "cx", "mss"; 3011 3012 memory-region = <&mpss_mem>; 3013 3014 qcom,qmp = <&aoss_qmp>; 3015 3016 qcom,smem-states = <&modem_smp2p_out 0>; 3017 qcom,smem-state-names = "stop"; 3018 3019 status = "disabled"; 3020 3021 glink-edge { 3022 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 3023 IPCC_MPROC_SIGNAL_GLINK_QMP 3024 IRQ_TYPE_EDGE_RISING>; 3025 mboxes = <&ipcc IPCC_CLIENT_MPSS 3026 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3027 label = "modem"; 3028 qcom,remote-pid = <1>; 3029 }; 3030 }; 3031 3032 stm@6002000 { 3033 compatible = "arm,coresight-stm", "arm,primecell"; 3034 reg = <0 0x06002000 0 0x1000>, 3035 <0 0x16280000 0 0x180000>; 3036 reg-names = "stm-base", "stm-stimulus-base"; 3037 3038 clocks = <&aoss_qmp>; 3039 clock-names = "apb_pclk"; 3040 3041 out-ports { 3042 port { 3043 stm_out: endpoint { 3044 remote-endpoint = <&funnel0_in7>; 3045 }; 3046 }; 3047 }; 3048 }; 3049 3050 funnel@6041000 { 3051 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3052 reg = <0 0x06041000 0 0x1000>; 3053 3054 clocks = <&aoss_qmp>; 3055 clock-names = "apb_pclk"; 3056 3057 out-ports { 3058 port { 3059 funnel0_out: endpoint { 3060 remote-endpoint = <&merge_funnel_in0>; 3061 }; 3062 }; 3063 }; 3064 3065 in-ports { 3066 #address-cells = <1>; 3067 #size-cells = <0>; 3068 3069 port@7 { 3070 reg = <7>; 3071 funnel0_in7: endpoint { 3072 remote-endpoint = <&stm_out>; 3073 }; 3074 }; 3075 }; 3076 }; 3077 3078 funnel@6042000 { 3079 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3080 reg = <0 0x06042000 0 0x1000>; 3081 3082 clocks = <&aoss_qmp>; 3083 clock-names = "apb_pclk"; 3084 3085 out-ports { 3086 port { 3087 funnel1_out: endpoint { 3088 remote-endpoint = <&merge_funnel_in1>; 3089 }; 3090 }; 3091 }; 3092 3093 in-ports { 3094 #address-cells = <1>; 3095 #size-cells = <0>; 3096 3097 port@4 { 3098 reg = <4>; 3099 funnel1_in4: endpoint { 3100 remote-endpoint = <&apss_merge_funnel_out>; 3101 }; 3102 }; 3103 }; 3104 }; 3105 3106 funnel@6045000 { 3107 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3108 reg = <0 0x06045000 0 0x1000>; 3109 3110 clocks = <&aoss_qmp>; 3111 clock-names = "apb_pclk"; 3112 3113 out-ports { 3114 port { 3115 merge_funnel_out: endpoint { 3116 remote-endpoint = <&swao_funnel_in>; 3117 }; 3118 }; 3119 }; 3120 3121 in-ports { 3122 #address-cells = <1>; 3123 #size-cells = <0>; 3124 3125 port@0 { 3126 reg = <0>; 3127 merge_funnel_in0: endpoint { 3128 remote-endpoint = <&funnel0_out>; 3129 }; 3130 }; 3131 3132 port@1 { 3133 reg = <1>; 3134 merge_funnel_in1: endpoint { 3135 remote-endpoint = <&funnel1_out>; 3136 }; 3137 }; 3138 }; 3139 }; 3140 3141 replicator@6046000 { 3142 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3143 reg = <0 0x06046000 0 0x1000>; 3144 3145 clocks = <&aoss_qmp>; 3146 clock-names = "apb_pclk"; 3147 3148 out-ports { 3149 port { 3150 replicator_out: endpoint { 3151 remote-endpoint = <&etr_in>; 3152 }; 3153 }; 3154 }; 3155 3156 in-ports { 3157 port { 3158 replicator_in: endpoint { 3159 remote-endpoint = <&swao_replicator_out>; 3160 }; 3161 }; 3162 }; 3163 }; 3164 3165 etr@6048000 { 3166 compatible = "arm,coresight-tmc", "arm,primecell"; 3167 reg = <0 0x06048000 0 0x1000>; 3168 iommus = <&apps_smmu 0x04c0 0>; 3169 3170 clocks = <&aoss_qmp>; 3171 clock-names = "apb_pclk"; 3172 arm,scatter-gather; 3173 3174 in-ports { 3175 port { 3176 etr_in: endpoint { 3177 remote-endpoint = <&replicator_out>; 3178 }; 3179 }; 3180 }; 3181 }; 3182 3183 funnel@6b04000 { 3184 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3185 reg = <0 0x06b04000 0 0x1000>; 3186 3187 clocks = <&aoss_qmp>; 3188 clock-names = "apb_pclk"; 3189 3190 out-ports { 3191 port { 3192 swao_funnel_out: endpoint { 3193 remote-endpoint = <&etf_in>; 3194 }; 3195 }; 3196 }; 3197 3198 in-ports { 3199 #address-cells = <1>; 3200 #size-cells = <0>; 3201 3202 port@7 { 3203 reg = <7>; 3204 swao_funnel_in: endpoint { 3205 remote-endpoint = <&merge_funnel_out>; 3206 }; 3207 }; 3208 }; 3209 }; 3210 3211 etf@6b05000 { 3212 compatible = "arm,coresight-tmc", "arm,primecell"; 3213 reg = <0 0x06b05000 0 0x1000>; 3214 3215 clocks = <&aoss_qmp>; 3216 clock-names = "apb_pclk"; 3217 3218 out-ports { 3219 port { 3220 etf_out: endpoint { 3221 remote-endpoint = <&swao_replicator_in>; 3222 }; 3223 }; 3224 }; 3225 3226 in-ports { 3227 port { 3228 etf_in: endpoint { 3229 remote-endpoint = <&swao_funnel_out>; 3230 }; 3231 }; 3232 }; 3233 }; 3234 3235 replicator@6b06000 { 3236 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3237 reg = <0 0x06b06000 0 0x1000>; 3238 3239 clocks = <&aoss_qmp>; 3240 clock-names = "apb_pclk"; 3241 qcom,replicator-loses-context; 3242 3243 out-ports { 3244 port { 3245 swao_replicator_out: endpoint { 3246 remote-endpoint = <&replicator_in>; 3247 }; 3248 }; 3249 }; 3250 3251 in-ports { 3252 port { 3253 swao_replicator_in: endpoint { 3254 remote-endpoint = <&etf_out>; 3255 }; 3256 }; 3257 }; 3258 }; 3259 3260 etm@7040000 { 3261 compatible = "arm,coresight-etm4x", "arm,primecell"; 3262 reg = <0 0x07040000 0 0x1000>; 3263 3264 cpu = <&CPU0>; 3265 3266 clocks = <&aoss_qmp>; 3267 clock-names = "apb_pclk"; 3268 arm,coresight-loses-context-with-cpu; 3269 qcom,skip-power-up; 3270 3271 out-ports { 3272 port { 3273 etm0_out: endpoint { 3274 remote-endpoint = <&apss_funnel_in0>; 3275 }; 3276 }; 3277 }; 3278 }; 3279 3280 etm@7140000 { 3281 compatible = "arm,coresight-etm4x", "arm,primecell"; 3282 reg = <0 0x07140000 0 0x1000>; 3283 3284 cpu = <&CPU1>; 3285 3286 clocks = <&aoss_qmp>; 3287 clock-names = "apb_pclk"; 3288 arm,coresight-loses-context-with-cpu; 3289 qcom,skip-power-up; 3290 3291 out-ports { 3292 port { 3293 etm1_out: endpoint { 3294 remote-endpoint = <&apss_funnel_in1>; 3295 }; 3296 }; 3297 }; 3298 }; 3299 3300 etm@7240000 { 3301 compatible = "arm,coresight-etm4x", "arm,primecell"; 3302 reg = <0 0x07240000 0 0x1000>; 3303 3304 cpu = <&CPU2>; 3305 3306 clocks = <&aoss_qmp>; 3307 clock-names = "apb_pclk"; 3308 arm,coresight-loses-context-with-cpu; 3309 qcom,skip-power-up; 3310 3311 out-ports { 3312 port { 3313 etm2_out: endpoint { 3314 remote-endpoint = <&apss_funnel_in2>; 3315 }; 3316 }; 3317 }; 3318 }; 3319 3320 etm@7340000 { 3321 compatible = "arm,coresight-etm4x", "arm,primecell"; 3322 reg = <0 0x07340000 0 0x1000>; 3323 3324 cpu = <&CPU3>; 3325 3326 clocks = <&aoss_qmp>; 3327 clock-names = "apb_pclk"; 3328 arm,coresight-loses-context-with-cpu; 3329 qcom,skip-power-up; 3330 3331 out-ports { 3332 port { 3333 etm3_out: endpoint { 3334 remote-endpoint = <&apss_funnel_in3>; 3335 }; 3336 }; 3337 }; 3338 }; 3339 3340 etm@7440000 { 3341 compatible = "arm,coresight-etm4x", "arm,primecell"; 3342 reg = <0 0x07440000 0 0x1000>; 3343 3344 cpu = <&CPU4>; 3345 3346 clocks = <&aoss_qmp>; 3347 clock-names = "apb_pclk"; 3348 arm,coresight-loses-context-with-cpu; 3349 qcom,skip-power-up; 3350 3351 out-ports { 3352 port { 3353 etm4_out: endpoint { 3354 remote-endpoint = <&apss_funnel_in4>; 3355 }; 3356 }; 3357 }; 3358 }; 3359 3360 etm@7540000 { 3361 compatible = "arm,coresight-etm4x", "arm,primecell"; 3362 reg = <0 0x07540000 0 0x1000>; 3363 3364 cpu = <&CPU5>; 3365 3366 clocks = <&aoss_qmp>; 3367 clock-names = "apb_pclk"; 3368 arm,coresight-loses-context-with-cpu; 3369 qcom,skip-power-up; 3370 3371 out-ports { 3372 port { 3373 etm5_out: endpoint { 3374 remote-endpoint = <&apss_funnel_in5>; 3375 }; 3376 }; 3377 }; 3378 }; 3379 3380 etm@7640000 { 3381 compatible = "arm,coresight-etm4x", "arm,primecell"; 3382 reg = <0 0x07640000 0 0x1000>; 3383 3384 cpu = <&CPU6>; 3385 3386 clocks = <&aoss_qmp>; 3387 clock-names = "apb_pclk"; 3388 arm,coresight-loses-context-with-cpu; 3389 qcom,skip-power-up; 3390 3391 out-ports { 3392 port { 3393 etm6_out: endpoint { 3394 remote-endpoint = <&apss_funnel_in6>; 3395 }; 3396 }; 3397 }; 3398 }; 3399 3400 etm@7740000 { 3401 compatible = "arm,coresight-etm4x", "arm,primecell"; 3402 reg = <0 0x07740000 0 0x1000>; 3403 3404 cpu = <&CPU7>; 3405 3406 clocks = <&aoss_qmp>; 3407 clock-names = "apb_pclk"; 3408 arm,coresight-loses-context-with-cpu; 3409 qcom,skip-power-up; 3410 3411 out-ports { 3412 port { 3413 etm7_out: endpoint { 3414 remote-endpoint = <&apss_funnel_in7>; 3415 }; 3416 }; 3417 }; 3418 }; 3419 3420 funnel@7800000 { /* APSS Funnel */ 3421 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3422 reg = <0 0x07800000 0 0x1000>; 3423 3424 clocks = <&aoss_qmp>; 3425 clock-names = "apb_pclk"; 3426 3427 out-ports { 3428 port { 3429 apss_funnel_out: endpoint { 3430 remote-endpoint = <&apss_merge_funnel_in>; 3431 }; 3432 }; 3433 }; 3434 3435 in-ports { 3436 #address-cells = <1>; 3437 #size-cells = <0>; 3438 3439 port@0 { 3440 reg = <0>; 3441 apss_funnel_in0: endpoint { 3442 remote-endpoint = <&etm0_out>; 3443 }; 3444 }; 3445 3446 port@1 { 3447 reg = <1>; 3448 apss_funnel_in1: endpoint { 3449 remote-endpoint = <&etm1_out>; 3450 }; 3451 }; 3452 3453 port@2 { 3454 reg = <2>; 3455 apss_funnel_in2: endpoint { 3456 remote-endpoint = <&etm2_out>; 3457 }; 3458 }; 3459 3460 port@3 { 3461 reg = <3>; 3462 apss_funnel_in3: endpoint { 3463 remote-endpoint = <&etm3_out>; 3464 }; 3465 }; 3466 3467 port@4 { 3468 reg = <4>; 3469 apss_funnel_in4: endpoint { 3470 remote-endpoint = <&etm4_out>; 3471 }; 3472 }; 3473 3474 port@5 { 3475 reg = <5>; 3476 apss_funnel_in5: endpoint { 3477 remote-endpoint = <&etm5_out>; 3478 }; 3479 }; 3480 3481 port@6 { 3482 reg = <6>; 3483 apss_funnel_in6: endpoint { 3484 remote-endpoint = <&etm6_out>; 3485 }; 3486 }; 3487 3488 port@7 { 3489 reg = <7>; 3490 apss_funnel_in7: endpoint { 3491 remote-endpoint = <&etm7_out>; 3492 }; 3493 }; 3494 }; 3495 }; 3496 3497 funnel@7810000 { 3498 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3499 reg = <0 0x07810000 0 0x1000>; 3500 3501 clocks = <&aoss_qmp>; 3502 clock-names = "apb_pclk"; 3503 3504 out-ports { 3505 port { 3506 apss_merge_funnel_out: endpoint { 3507 remote-endpoint = <&funnel1_in4>; 3508 }; 3509 }; 3510 }; 3511 3512 in-ports { 3513 port { 3514 apss_merge_funnel_in: endpoint { 3515 remote-endpoint = <&apss_funnel_out>; 3516 }; 3517 }; 3518 }; 3519 }; 3520 3521 sdhc_2: mmc@8804000 { 3522 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 3523 pinctrl-names = "default", "sleep"; 3524 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 3525 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 3526 status = "disabled"; 3527 3528 reg = <0 0x08804000 0 0x1000>; 3529 3530 iommus = <&apps_smmu 0x100 0x0>; 3531 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3532 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3533 interrupt-names = "hc_irq", "pwr_irq"; 3534 3535 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3536 <&gcc GCC_SDCC2_APPS_CLK>, 3537 <&rpmhcc RPMH_CXO_CLK>; 3538 clock-names = "iface", "core", "xo"; 3539 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3540 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 3541 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3542 power-domains = <&rpmhpd SC7280_CX>; 3543 operating-points-v2 = <&sdhc2_opp_table>; 3544 3545 bus-width = <4>; 3546 dma-coherent; 3547 3548 qcom,dll-config = <0x0007642c>; 3549 3550 resets = <&gcc GCC_SDCC2_BCR>; 3551 3552 sdhc2_opp_table: opp-table { 3553 compatible = "operating-points-v2"; 3554 3555 opp-100000000 { 3556 opp-hz = /bits/ 64 <100000000>; 3557 required-opps = <&rpmhpd_opp_low_svs>; 3558 opp-peak-kBps = <1800000 400000>; 3559 opp-avg-kBps = <100000 0>; 3560 }; 3561 3562 opp-202000000 { 3563 opp-hz = /bits/ 64 <202000000>; 3564 required-opps = <&rpmhpd_opp_nom>; 3565 opp-peak-kBps = <5400000 1600000>; 3566 opp-avg-kBps = <200000 0>; 3567 }; 3568 }; 3569 }; 3570 3571 usb_1_hsphy: phy@88e3000 { 3572 compatible = "qcom,sc7280-usb-hs-phy", 3573 "qcom,usb-snps-hs-7nm-phy"; 3574 reg = <0 0x088e3000 0 0x400>; 3575 status = "disabled"; 3576 #phy-cells = <0>; 3577 3578 clocks = <&rpmhcc RPMH_CXO_CLK>; 3579 clock-names = "ref"; 3580 3581 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3582 }; 3583 3584 usb_2_hsphy: phy@88e4000 { 3585 compatible = "qcom,sc7280-usb-hs-phy", 3586 "qcom,usb-snps-hs-7nm-phy"; 3587 reg = <0 0x088e4000 0 0x400>; 3588 status = "disabled"; 3589 #phy-cells = <0>; 3590 3591 clocks = <&rpmhcc RPMH_CXO_CLK>; 3592 clock-names = "ref"; 3593 3594 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3595 }; 3596 3597 usb_1_qmpphy: phy@88e8000 { 3598 compatible = "qcom,sc7280-qmp-usb3-dp-phy"; 3599 reg = <0 0x088e8000 0 0x3000>; 3600 status = "disabled"; 3601 3602 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3603 <&rpmhcc RPMH_CXO_CLK>, 3604 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3605 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3606 clock-names = "aux", 3607 "ref", 3608 "com_aux", 3609 "usb3_pipe"; 3610 3611 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3612 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3613 reset-names = "phy", "common"; 3614 3615 #clock-cells = <1>; 3616 #phy-cells = <1>; 3617 3618 ports { 3619 #address-cells = <1>; 3620 #size-cells = <0>; 3621 3622 port@0 { 3623 reg = <0>; 3624 3625 usb_dp_qmpphy_out: endpoint { 3626 }; 3627 }; 3628 3629 port@1 { 3630 reg = <1>; 3631 3632 usb_dp_qmpphy_usb_ss_in: endpoint { 3633 }; 3634 }; 3635 3636 port@2 { 3637 reg = <2>; 3638 3639 usb_dp_qmpphy_dp_in: endpoint { 3640 }; 3641 }; 3642 }; 3643 }; 3644 3645 usb_2: usb@8cf8800 { 3646 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 3647 reg = <0 0x08cf8800 0 0x400>; 3648 status = "disabled"; 3649 #address-cells = <2>; 3650 #size-cells = <2>; 3651 ranges; 3652 dma-ranges; 3653 3654 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3655 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3656 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3657 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3658 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 3659 clock-names = "cfg_noc", 3660 "core", 3661 "iface", 3662 "sleep", 3663 "mock_utmi"; 3664 3665 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3666 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3667 assigned-clock-rates = <19200000>, <200000000>; 3668 3669 interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 3670 <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 3671 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 3672 <&pdc 13 IRQ_TYPE_EDGE_BOTH>; 3673 interrupt-names = "pwr_event", 3674 "hs_phy_irq", 3675 "dp_hs_phy_irq", 3676 "dm_hs_phy_irq"; 3677 3678 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3679 required-opps = <&rpmhpd_opp_nom>; 3680 3681 resets = <&gcc GCC_USB30_SEC_BCR>; 3682 3683 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 3684 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 3685 interconnect-names = "usb-ddr", "apps-usb"; 3686 3687 usb_2_dwc3: usb@8c00000 { 3688 compatible = "snps,dwc3"; 3689 reg = <0 0x08c00000 0 0xe000>; 3690 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 3691 iommus = <&apps_smmu 0xa0 0x0>; 3692 snps,dis_u2_susphy_quirk; 3693 snps,dis_enblslpm_quirk; 3694 phys = <&usb_2_hsphy>; 3695 phy-names = "usb2-phy"; 3696 maximum-speed = "high-speed"; 3697 usb-role-switch; 3698 3699 port { 3700 usb2_role_switch: endpoint { 3701 remote-endpoint = <&eud_ep>; 3702 }; 3703 }; 3704 }; 3705 }; 3706 3707 qspi: spi@88dc000 { 3708 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 3709 reg = <0 0x088dc000 0 0x1000>; 3710 iommus = <&apps_smmu 0x20 0x0>; 3711 #address-cells = <1>; 3712 #size-cells = <0>; 3713 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 3714 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 3715 <&gcc GCC_QSPI_CORE_CLK>; 3716 clock-names = "iface", "core"; 3717 interconnects = <&gem_noc MASTER_APPSS_PROC 0 3718 &cnoc2 SLAVE_QSPI_0 0>; 3719 interconnect-names = "qspi-config"; 3720 power-domains = <&rpmhpd SC7280_CX>; 3721 operating-points-v2 = <&qspi_opp_table>; 3722 status = "disabled"; 3723 }; 3724 3725 remoteproc_adsp: remoteproc@3700000 { 3726 compatible = "qcom,sc7280-adsp-pas"; 3727 reg = <0 0x03700000 0 0x100>; 3728 3729 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 3730 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3731 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3732 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3733 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3734 <&adsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3735 interrupt-names = "wdog", "fatal", "ready", "handover", 3736 "stop-ack", "shutdown-ack"; 3737 3738 clocks = <&rpmhcc RPMH_CXO_CLK>; 3739 clock-names = "xo"; 3740 3741 power-domains = <&rpmhpd SC7280_LCX>, 3742 <&rpmhpd SC7280_LMX>; 3743 power-domain-names = "lcx", "lmx"; 3744 3745 memory-region = <&adsp_mem>; 3746 3747 qcom,qmp = <&aoss_qmp>; 3748 3749 qcom,smem-states = <&adsp_smp2p_out 0>; 3750 qcom,smem-state-names = "stop"; 3751 3752 status = "disabled"; 3753 3754 glink-edge { 3755 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 3756 IPCC_MPROC_SIGNAL_GLINK_QMP 3757 IRQ_TYPE_EDGE_RISING>; 3758 3759 mboxes = <&ipcc IPCC_CLIENT_LPASS 3760 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3761 3762 label = "lpass"; 3763 qcom,remote-pid = <2>; 3764 3765 fastrpc { 3766 compatible = "qcom,fastrpc"; 3767 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3768 label = "adsp"; 3769 qcom,non-secure-domain; 3770 #address-cells = <1>; 3771 #size-cells = <0>; 3772 3773 compute-cb@3 { 3774 compatible = "qcom,fastrpc-compute-cb"; 3775 reg = <3>; 3776 iommus = <&apps_smmu 0x1803 0x0>; 3777 }; 3778 3779 compute-cb@4 { 3780 compatible = "qcom,fastrpc-compute-cb"; 3781 reg = <4>; 3782 iommus = <&apps_smmu 0x1804 0x0>; 3783 }; 3784 3785 compute-cb@5 { 3786 compatible = "qcom,fastrpc-compute-cb"; 3787 reg = <5>; 3788 iommus = <&apps_smmu 0x1805 0x0>; 3789 }; 3790 }; 3791 }; 3792 }; 3793 3794 remoteproc_wpss: remoteproc@8a00000 { 3795 compatible = "qcom,sc7280-wpss-pas"; 3796 reg = <0 0x08a00000 0 0x10000>; 3797 3798 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 3799 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3800 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3801 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3802 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3803 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3804 interrupt-names = "wdog", "fatal", "ready", "handover", 3805 "stop-ack", "shutdown-ack"; 3806 3807 clocks = <&rpmhcc RPMH_CXO_CLK>; 3808 clock-names = "xo"; 3809 3810 power-domains = <&rpmhpd SC7280_CX>, 3811 <&rpmhpd SC7280_MX>; 3812 power-domain-names = "cx", "mx"; 3813 3814 memory-region = <&wpss_mem>; 3815 3816 qcom,qmp = <&aoss_qmp>; 3817 3818 qcom,smem-states = <&wpss_smp2p_out 0>; 3819 qcom,smem-state-names = "stop"; 3820 3821 3822 status = "disabled"; 3823 3824 glink-edge { 3825 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 3826 IPCC_MPROC_SIGNAL_GLINK_QMP 3827 IRQ_TYPE_EDGE_RISING>; 3828 mboxes = <&ipcc IPCC_CLIENT_WPSS 3829 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3830 3831 label = "wpss"; 3832 qcom,remote-pid = <13>; 3833 }; 3834 }; 3835 3836 pmu@9091000 { 3837 compatible = "qcom,sc7280-llcc-bwmon"; 3838 reg = <0 0x09091000 0 0x1000>; 3839 3840 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3841 3842 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3843 3844 operating-points-v2 = <&llcc_bwmon_opp_table>; 3845 3846 llcc_bwmon_opp_table: opp-table { 3847 compatible = "operating-points-v2"; 3848 3849 opp-0 { 3850 opp-peak-kBps = <800000>; 3851 }; 3852 opp-1 { 3853 opp-peak-kBps = <1804000>; 3854 }; 3855 opp-2 { 3856 opp-peak-kBps = <2188000>; 3857 }; 3858 opp-3 { 3859 opp-peak-kBps = <3072000>; 3860 }; 3861 opp-4 { 3862 opp-peak-kBps = <4068000>; 3863 }; 3864 opp-5 { 3865 opp-peak-kBps = <6220000>; 3866 }; 3867 opp-6 { 3868 opp-peak-kBps = <6832000>; 3869 }; 3870 opp-7 { 3871 opp-peak-kBps = <8532000>; 3872 }; 3873 }; 3874 }; 3875 3876 pmu@90b6400 { 3877 compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon"; 3878 reg = <0 0x090b6400 0 0x600>; 3879 3880 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3881 3882 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3883 operating-points-v2 = <&cpu_bwmon_opp_table>; 3884 3885 cpu_bwmon_opp_table: opp-table { 3886 compatible = "operating-points-v2"; 3887 3888 opp-0 { 3889 opp-peak-kBps = <2400000>; 3890 }; 3891 opp-1 { 3892 opp-peak-kBps = <4800000>; 3893 }; 3894 opp-2 { 3895 opp-peak-kBps = <7456000>; 3896 }; 3897 opp-3 { 3898 opp-peak-kBps = <9600000>; 3899 }; 3900 opp-4 { 3901 opp-peak-kBps = <12896000>; 3902 }; 3903 opp-5 { 3904 opp-peak-kBps = <14928000>; 3905 }; 3906 opp-6 { 3907 opp-peak-kBps = <17056000>; 3908 }; 3909 }; 3910 }; 3911 3912 dc_noc: interconnect@90e0000 { 3913 reg = <0 0x090e0000 0 0x5080>; 3914 compatible = "qcom,sc7280-dc-noc"; 3915 #interconnect-cells = <2>; 3916 qcom,bcm-voters = <&apps_bcm_voter>; 3917 }; 3918 3919 gem_noc: interconnect@9100000 { 3920 reg = <0 0x09100000 0 0xe2200>; 3921 compatible = "qcom,sc7280-gem-noc"; 3922 #interconnect-cells = <2>; 3923 qcom,bcm-voters = <&apps_bcm_voter>; 3924 }; 3925 3926 system-cache-controller@9200000 { 3927 compatible = "qcom,sc7280-llcc"; 3928 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 3929 <0 0x09600000 0 0x58000>; 3930 reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; 3931 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3932 }; 3933 3934 eud: eud@88e0000 { 3935 compatible = "qcom,sc7280-eud", "qcom,eud"; 3936 reg = <0 0x88e0000 0 0x2000>, 3937 <0 0x88e2000 0 0x1000>; 3938 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 3939 3940 status = "disabled"; 3941 3942 ports { 3943 #address-cells = <1>; 3944 #size-cells = <0>; 3945 3946 port@0 { 3947 reg = <0>; 3948 eud_ep: endpoint { 3949 remote-endpoint = <&usb2_role_switch>; 3950 }; 3951 }; 3952 }; 3953 }; 3954 3955 nsp_noc: interconnect@a0c0000 { 3956 reg = <0 0x0a0c0000 0 0x10000>; 3957 compatible = "qcom,sc7280-nsp-noc"; 3958 #interconnect-cells = <2>; 3959 qcom,bcm-voters = <&apps_bcm_voter>; 3960 }; 3961 3962 remoteproc_cdsp: remoteproc@a300000 { 3963 compatible = "qcom,sc7280-cdsp-pas"; 3964 reg = <0 0x0a300000 0 0x10000>; 3965 3966 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3967 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3968 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3969 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3970 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3971 <&cdsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3972 interrupt-names = "wdog", "fatal", "ready", "handover", 3973 "stop-ack", "shutdown-ack"; 3974 3975 clocks = <&rpmhcc RPMH_CXO_CLK>; 3976 clock-names = "xo"; 3977 3978 power-domains = <&rpmhpd SC7280_CX>, 3979 <&rpmhpd SC7280_MX>; 3980 power-domain-names = "cx", "mx"; 3981 3982 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 3983 3984 memory-region = <&cdsp_mem>; 3985 3986 qcom,qmp = <&aoss_qmp>; 3987 3988 qcom,smem-states = <&cdsp_smp2p_out 0>; 3989 qcom,smem-state-names = "stop"; 3990 3991 status = "disabled"; 3992 3993 glink-edge { 3994 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3995 IPCC_MPROC_SIGNAL_GLINK_QMP 3996 IRQ_TYPE_EDGE_RISING>; 3997 mboxes = <&ipcc IPCC_CLIENT_CDSP 3998 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3999 4000 label = "cdsp"; 4001 qcom,remote-pid = <5>; 4002 4003 fastrpc { 4004 compatible = "qcom,fastrpc"; 4005 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4006 label = "cdsp"; 4007 qcom,non-secure-domain; 4008 #address-cells = <1>; 4009 #size-cells = <0>; 4010 4011 compute-cb@1 { 4012 compatible = "qcom,fastrpc-compute-cb"; 4013 reg = <1>; 4014 iommus = <&apps_smmu 0x11a1 0x0420>, 4015 <&apps_smmu 0x1181 0x0420>; 4016 }; 4017 4018 compute-cb@2 { 4019 compatible = "qcom,fastrpc-compute-cb"; 4020 reg = <2>; 4021 iommus = <&apps_smmu 0x11a2 0x0420>, 4022 <&apps_smmu 0x1182 0x0420>; 4023 }; 4024 4025 compute-cb@3 { 4026 compatible = "qcom,fastrpc-compute-cb"; 4027 reg = <3>; 4028 iommus = <&apps_smmu 0x11a3 0x0420>, 4029 <&apps_smmu 0x1183 0x0420>; 4030 }; 4031 4032 compute-cb@4 { 4033 compatible = "qcom,fastrpc-compute-cb"; 4034 reg = <4>; 4035 iommus = <&apps_smmu 0x11a4 0x0420>, 4036 <&apps_smmu 0x1184 0x0420>; 4037 }; 4038 4039 compute-cb@5 { 4040 compatible = "qcom,fastrpc-compute-cb"; 4041 reg = <5>; 4042 iommus = <&apps_smmu 0x11a5 0x0420>, 4043 <&apps_smmu 0x1185 0x0420>; 4044 }; 4045 4046 compute-cb@6 { 4047 compatible = "qcom,fastrpc-compute-cb"; 4048 reg = <6>; 4049 iommus = <&apps_smmu 0x11a6 0x0420>, 4050 <&apps_smmu 0x1186 0x0420>; 4051 }; 4052 4053 compute-cb@7 { 4054 compatible = "qcom,fastrpc-compute-cb"; 4055 reg = <7>; 4056 iommus = <&apps_smmu 0x11a7 0x0420>, 4057 <&apps_smmu 0x1187 0x0420>; 4058 }; 4059 4060 compute-cb@8 { 4061 compatible = "qcom,fastrpc-compute-cb"; 4062 reg = <8>; 4063 iommus = <&apps_smmu 0x11a8 0x0420>, 4064 <&apps_smmu 0x1188 0x0420>; 4065 }; 4066 4067 /* note: secure cb9 in downstream */ 4068 4069 compute-cb@11 { 4070 compatible = "qcom,fastrpc-compute-cb"; 4071 reg = <11>; 4072 iommus = <&apps_smmu 0x11ab 0x0420>, 4073 <&apps_smmu 0x118b 0x0420>; 4074 }; 4075 4076 compute-cb@12 { 4077 compatible = "qcom,fastrpc-compute-cb"; 4078 reg = <12>; 4079 iommus = <&apps_smmu 0x11ac 0x0420>, 4080 <&apps_smmu 0x118c 0x0420>; 4081 }; 4082 4083 compute-cb@13 { 4084 compatible = "qcom,fastrpc-compute-cb"; 4085 reg = <13>; 4086 iommus = <&apps_smmu 0x11ad 0x0420>, 4087 <&apps_smmu 0x118d 0x0420>; 4088 }; 4089 4090 compute-cb@14 { 4091 compatible = "qcom,fastrpc-compute-cb"; 4092 reg = <14>; 4093 iommus = <&apps_smmu 0x11ae 0x0420>, 4094 <&apps_smmu 0x118e 0x0420>; 4095 }; 4096 }; 4097 }; 4098 }; 4099 4100 usb_1: usb@a6f8800 { 4101 compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; 4102 reg = <0 0x0a6f8800 0 0x400>; 4103 status = "disabled"; 4104 #address-cells = <2>; 4105 #size-cells = <2>; 4106 ranges; 4107 dma-ranges; 4108 4109 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4110 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4111 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4112 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4113 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 4114 clock-names = "cfg_noc", 4115 "core", 4116 "iface", 4117 "sleep", 4118 "mock_utmi"; 4119 4120 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4121 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4122 assigned-clock-rates = <19200000>, <200000000>; 4123 4124 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4125 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4126 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4127 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4128 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 4129 interrupt-names = "pwr_event", 4130 "hs_phy_irq", 4131 "dp_hs_phy_irq", 4132 "dm_hs_phy_irq", 4133 "ss_phy_irq"; 4134 4135 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 4136 required-opps = <&rpmhpd_opp_nom>; 4137 4138 resets = <&gcc GCC_USB30_PRIM_BCR>; 4139 4140 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 4141 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 4142 interconnect-names = "usb-ddr", "apps-usb"; 4143 4144 wakeup-source; 4145 4146 usb_1_dwc3: usb@a600000 { 4147 compatible = "snps,dwc3"; 4148 reg = <0 0x0a600000 0 0xe000>; 4149 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4150 iommus = <&apps_smmu 0xe0 0x0>; 4151 snps,dis_u2_susphy_quirk; 4152 snps,dis_enblslpm_quirk; 4153 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4154 phy-names = "usb2-phy", "usb3-phy"; 4155 maximum-speed = "super-speed"; 4156 4157 ports { 4158 #address-cells = <1>; 4159 #size-cells = <0>; 4160 4161 port@0 { 4162 reg = <0>; 4163 4164 usb_1_dwc3_hs: endpoint { 4165 }; 4166 }; 4167 4168 port@1 { 4169 reg = <1>; 4170 4171 usb_1_dwc3_ss: endpoint { 4172 }; 4173 }; 4174 }; 4175 }; 4176 }; 4177 4178 venus: video-codec@aa00000 { 4179 compatible = "qcom,sc7280-venus"; 4180 reg = <0 0x0aa00000 0 0xd0600>; 4181 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4182 4183 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 4184 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 4185 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 4186 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 4187 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 4188 clock-names = "core", "bus", "iface", 4189 "vcodec_core", "vcodec_bus"; 4190 4191 power-domains = <&videocc MVSC_GDSC>, 4192 <&videocc MVS0_GDSC>, 4193 <&rpmhpd SC7280_CX>; 4194 power-domain-names = "venus", "vcodec0", "cx"; 4195 operating-points-v2 = <&venus_opp_table>; 4196 4197 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 4198 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 4199 interconnect-names = "cpu-cfg", "video-mem"; 4200 4201 iommus = <&apps_smmu 0x2180 0x20>; 4202 memory-region = <&video_mem>; 4203 4204 status = "disabled"; 4205 4206 video-decoder { 4207 compatible = "venus-decoder"; 4208 }; 4209 4210 video-encoder { 4211 compatible = "venus-encoder"; 4212 }; 4213 4214 venus_opp_table: opp-table { 4215 compatible = "operating-points-v2"; 4216 4217 opp-133330000 { 4218 opp-hz = /bits/ 64 <133330000>; 4219 required-opps = <&rpmhpd_opp_low_svs>; 4220 }; 4221 4222 opp-240000000 { 4223 opp-hz = /bits/ 64 <240000000>; 4224 required-opps = <&rpmhpd_opp_svs>; 4225 }; 4226 4227 opp-335000000 { 4228 opp-hz = /bits/ 64 <335000000>; 4229 required-opps = <&rpmhpd_opp_svs_l1>; 4230 }; 4231 4232 opp-424000000 { 4233 opp-hz = /bits/ 64 <424000000>; 4234 required-opps = <&rpmhpd_opp_nom>; 4235 }; 4236 4237 opp-460000048 { 4238 opp-hz = /bits/ 64 <460000048>; 4239 required-opps = <&rpmhpd_opp_turbo>; 4240 }; 4241 }; 4242 }; 4243 4244 videocc: clock-controller@aaf0000 { 4245 compatible = "qcom,sc7280-videocc"; 4246 reg = <0 0x0aaf0000 0 0x10000>; 4247 clocks = <&rpmhcc RPMH_CXO_CLK>, 4248 <&rpmhcc RPMH_CXO_CLK_A>; 4249 clock-names = "bi_tcxo", "bi_tcxo_ao"; 4250 #clock-cells = <1>; 4251 #reset-cells = <1>; 4252 #power-domain-cells = <1>; 4253 }; 4254 4255 cci0: cci@ac4a000 { 4256 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci"; 4257 reg = <0 0x0ac4a000 0 0x1000>; 4258 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4259 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4260 4261 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4262 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4263 <&camcc CAM_CC_CPAS_AHB_CLK>, 4264 <&camcc CAM_CC_CCI_0_CLK>, 4265 <&camcc CAM_CC_CCI_0_CLK_SRC>; 4266 clock-names = "camnoc_axi", 4267 "slow_ahb_src", 4268 "cpas_ahb", 4269 "cci", 4270 "cci_src"; 4271 pinctrl-0 = <&cci0_default &cci1_default>; 4272 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 4273 pinctrl-names = "default", "sleep"; 4274 4275 #address-cells = <1>; 4276 #size-cells = <0>; 4277 4278 status = "disabled"; 4279 4280 cci0_i2c0: i2c-bus@0 { 4281 reg = <0>; 4282 clock-frequency = <1000000>; 4283 #address-cells = <1>; 4284 #size-cells = <0>; 4285 }; 4286 4287 cci0_i2c1: i2c-bus@1 { 4288 reg = <1>; 4289 clock-frequency = <1000000>; 4290 #address-cells = <1>; 4291 #size-cells = <0>; 4292 }; 4293 }; 4294 4295 cci1: cci@ac4b000 { 4296 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci"; 4297 reg = <0 0x0ac4b000 0 0x1000>; 4298 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 4299 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 4300 4301 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4302 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4303 <&camcc CAM_CC_CPAS_AHB_CLK>, 4304 <&camcc CAM_CC_CCI_1_CLK>, 4305 <&camcc CAM_CC_CCI_1_CLK_SRC>; 4306 clock-names = "camnoc_axi", 4307 "slow_ahb_src", 4308 "cpas_ahb", 4309 "cci", 4310 "cci_src"; 4311 pinctrl-0 = <&cci2_default &cci3_default>; 4312 pinctrl-1 = <&cci2_sleep &cci3_sleep>; 4313 pinctrl-names = "default", "sleep"; 4314 4315 #address-cells = <1>; 4316 #size-cells = <0>; 4317 4318 status = "disabled"; 4319 4320 cci1_i2c0: i2c-bus@0 { 4321 reg = <0>; 4322 clock-frequency = <1000000>; 4323 #address-cells = <1>; 4324 #size-cells = <0>; 4325 }; 4326 4327 cci1_i2c1: i2c-bus@1 { 4328 reg = <1>; 4329 clock-frequency = <1000000>; 4330 #address-cells = <1>; 4331 #size-cells = <0>; 4332 }; 4333 }; 4334 4335 camcc: clock-controller@ad00000 { 4336 compatible = "qcom,sc7280-camcc"; 4337 reg = <0 0x0ad00000 0 0x10000>; 4338 clocks = <&rpmhcc RPMH_CXO_CLK>, 4339 <&rpmhcc RPMH_CXO_CLK_A>, 4340 <&sleep_clk>; 4341 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 4342 #clock-cells = <1>; 4343 #reset-cells = <1>; 4344 #power-domain-cells = <1>; 4345 }; 4346 4347 dispcc: clock-controller@af00000 { 4348 compatible = "qcom,sc7280-dispcc"; 4349 reg = <0 0x0af00000 0 0x20000>; 4350 clocks = <&rpmhcc RPMH_CXO_CLK>, 4351 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 4352 <&mdss_dsi_phy 0>, 4353 <&mdss_dsi_phy 1>, 4354 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4355 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4356 <&mdss_edp_phy 0>, 4357 <&mdss_edp_phy 1>; 4358 clock-names = "bi_tcxo", 4359 "gcc_disp_gpll0_clk", 4360 "dsi0_phy_pll_out_byteclk", 4361 "dsi0_phy_pll_out_dsiclk", 4362 "dp_phy_pll_link_clk", 4363 "dp_phy_pll_vco_div_clk", 4364 "edp_phy_pll_link_clk", 4365 "edp_phy_pll_vco_div_clk"; 4366 #clock-cells = <1>; 4367 #reset-cells = <1>; 4368 #power-domain-cells = <1>; 4369 }; 4370 4371 mdss: display-subsystem@ae00000 { 4372 compatible = "qcom,sc7280-mdss"; 4373 reg = <0 0x0ae00000 0 0x1000>; 4374 reg-names = "mdss"; 4375 4376 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 4377 4378 clocks = <&gcc GCC_DISP_AHB_CLK>, 4379 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4380 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4381 clock-names = "iface", 4382 "ahb", 4383 "core"; 4384 4385 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4386 interrupt-controller; 4387 #interrupt-cells = <1>; 4388 4389 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS 4390 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4391 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4392 &cnoc2 SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>; 4393 interconnect-names = "mdp0-mem", 4394 "cpu-cfg"; 4395 4396 iommus = <&apps_smmu 0x900 0x402>; 4397 4398 #address-cells = <2>; 4399 #size-cells = <2>; 4400 ranges; 4401 4402 status = "disabled"; 4403 4404 mdss_mdp: display-controller@ae01000 { 4405 compatible = "qcom,sc7280-dpu"; 4406 reg = <0 0x0ae01000 0 0x8f030>, 4407 <0 0x0aeb0000 0 0x2008>; 4408 reg-names = "mdp", "vbif"; 4409 4410 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4411 <&gcc GCC_DISP_SF_AXI_CLK>, 4412 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4413 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 4414 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4415 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4416 clock-names = "bus", 4417 "nrt_bus", 4418 "iface", 4419 "lut", 4420 "core", 4421 "vsync"; 4422 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 4423 <&dispcc DISP_CC_MDSS_AHB_CLK>; 4424 assigned-clock-rates = <19200000>, 4425 <19200000>; 4426 operating-points-v2 = <&mdp_opp_table>; 4427 power-domains = <&rpmhpd SC7280_CX>; 4428 4429 interrupt-parent = <&mdss>; 4430 interrupts = <0>; 4431 4432 ports { 4433 #address-cells = <1>; 4434 #size-cells = <0>; 4435 4436 port@0 { 4437 reg = <0>; 4438 dpu_intf1_out: endpoint { 4439 remote-endpoint = <&mdss_dsi0_in>; 4440 }; 4441 }; 4442 4443 port@1 { 4444 reg = <1>; 4445 dpu_intf5_out: endpoint { 4446 remote-endpoint = <&edp_in>; 4447 }; 4448 }; 4449 4450 port@2 { 4451 reg = <2>; 4452 dpu_intf0_out: endpoint { 4453 remote-endpoint = <&dp_in>; 4454 }; 4455 }; 4456 }; 4457 4458 mdp_opp_table: opp-table { 4459 compatible = "operating-points-v2"; 4460 4461 opp-200000000 { 4462 opp-hz = /bits/ 64 <200000000>; 4463 required-opps = <&rpmhpd_opp_low_svs>; 4464 }; 4465 4466 opp-300000000 { 4467 opp-hz = /bits/ 64 <300000000>; 4468 required-opps = <&rpmhpd_opp_svs>; 4469 }; 4470 4471 opp-380000000 { 4472 opp-hz = /bits/ 64 <380000000>; 4473 required-opps = <&rpmhpd_opp_svs_l1>; 4474 }; 4475 4476 opp-506666667 { 4477 opp-hz = /bits/ 64 <506666667>; 4478 required-opps = <&rpmhpd_opp_nom>; 4479 }; 4480 4481 opp-608000000 { 4482 opp-hz = /bits/ 64 <608000000>; 4483 required-opps = <&rpmhpd_opp_turbo>; 4484 }; 4485 }; 4486 }; 4487 4488 mdss_dsi: dsi@ae94000 { 4489 compatible = "qcom,sc7280-dsi-ctrl", 4490 "qcom,mdss-dsi-ctrl"; 4491 reg = <0 0x0ae94000 0 0x400>; 4492 reg-names = "dsi_ctrl"; 4493 4494 interrupt-parent = <&mdss>; 4495 interrupts = <4>; 4496 4497 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4498 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4499 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4500 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4501 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4502 <&gcc GCC_DISP_HF_AXI_CLK>; 4503 clock-names = "byte", 4504 "byte_intf", 4505 "pixel", 4506 "core", 4507 "iface", 4508 "bus"; 4509 4510 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4511 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>; 4512 4513 operating-points-v2 = <&dsi_opp_table>; 4514 power-domains = <&rpmhpd SC7280_CX>; 4515 4516 phys = <&mdss_dsi_phy>; 4517 4518 #address-cells = <1>; 4519 #size-cells = <0>; 4520 4521 status = "disabled"; 4522 4523 ports { 4524 #address-cells = <1>; 4525 #size-cells = <0>; 4526 4527 port@0 { 4528 reg = <0>; 4529 mdss_dsi0_in: endpoint { 4530 remote-endpoint = <&dpu_intf1_out>; 4531 }; 4532 }; 4533 4534 port@1 { 4535 reg = <1>; 4536 mdss_dsi0_out: endpoint { 4537 }; 4538 }; 4539 }; 4540 4541 dsi_opp_table: opp-table { 4542 compatible = "operating-points-v2"; 4543 4544 opp-187500000 { 4545 opp-hz = /bits/ 64 <187500000>; 4546 required-opps = <&rpmhpd_opp_low_svs>; 4547 }; 4548 4549 opp-300000000 { 4550 opp-hz = /bits/ 64 <300000000>; 4551 required-opps = <&rpmhpd_opp_svs>; 4552 }; 4553 4554 opp-358000000 { 4555 opp-hz = /bits/ 64 <358000000>; 4556 required-opps = <&rpmhpd_opp_svs_l1>; 4557 }; 4558 }; 4559 }; 4560 4561 mdss_dsi_phy: phy@ae94400 { 4562 compatible = "qcom,sc7280-dsi-phy-7nm"; 4563 reg = <0 0x0ae94400 0 0x200>, 4564 <0 0x0ae94600 0 0x280>, 4565 <0 0x0ae94900 0 0x280>; 4566 reg-names = "dsi_phy", 4567 "dsi_phy_lane", 4568 "dsi_pll"; 4569 4570 #clock-cells = <1>; 4571 #phy-cells = <0>; 4572 4573 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4574 <&rpmhcc RPMH_CXO_CLK>; 4575 clock-names = "iface", "ref"; 4576 4577 status = "disabled"; 4578 }; 4579 4580 mdss_edp: edp@aea0000 { 4581 compatible = "qcom,sc7280-edp"; 4582 pinctrl-names = "default"; 4583 pinctrl-0 = <&edp_hot_plug_det>; 4584 4585 reg = <0 0x0aea0000 0 0x200>, 4586 <0 0x0aea0200 0 0x200>, 4587 <0 0x0aea0400 0 0xc00>, 4588 <0 0x0aea1000 0 0x400>; 4589 4590 interrupt-parent = <&mdss>; 4591 interrupts = <14>; 4592 4593 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4594 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 4595 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 4596 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 4597 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 4598 clock-names = "core_iface", 4599 "core_aux", 4600 "ctrl_link", 4601 "ctrl_link_iface", 4602 "stream_pixel"; 4603 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 4604 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 4605 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 4606 4607 phys = <&mdss_edp_phy>; 4608 phy-names = "dp"; 4609 4610 operating-points-v2 = <&edp_opp_table>; 4611 power-domains = <&rpmhpd SC7280_CX>; 4612 4613 status = "disabled"; 4614 4615 ports { 4616 #address-cells = <1>; 4617 #size-cells = <0>; 4618 4619 port@0 { 4620 reg = <0>; 4621 edp_in: endpoint { 4622 remote-endpoint = <&dpu_intf5_out>; 4623 }; 4624 }; 4625 4626 port@1 { 4627 reg = <1>; 4628 mdss_edp_out: endpoint { }; 4629 }; 4630 }; 4631 4632 edp_opp_table: opp-table { 4633 compatible = "operating-points-v2"; 4634 4635 opp-160000000 { 4636 opp-hz = /bits/ 64 <160000000>; 4637 required-opps = <&rpmhpd_opp_low_svs>; 4638 }; 4639 4640 opp-270000000 { 4641 opp-hz = /bits/ 64 <270000000>; 4642 required-opps = <&rpmhpd_opp_svs>; 4643 }; 4644 4645 opp-540000000 { 4646 opp-hz = /bits/ 64 <540000000>; 4647 required-opps = <&rpmhpd_opp_nom>; 4648 }; 4649 4650 opp-810000000 { 4651 opp-hz = /bits/ 64 <810000000>; 4652 required-opps = <&rpmhpd_opp_nom>; 4653 }; 4654 }; 4655 }; 4656 4657 mdss_edp_phy: phy@aec2a00 { 4658 compatible = "qcom,sc7280-edp-phy"; 4659 4660 reg = <0 0x0aec2a00 0 0x19c>, 4661 <0 0x0aec2200 0 0xa0>, 4662 <0 0x0aec2600 0 0xa0>, 4663 <0 0x0aec2000 0 0x1c0>; 4664 4665 clocks = <&rpmhcc RPMH_CXO_CLK>, 4666 <&gcc GCC_EDP_CLKREF_EN>; 4667 clock-names = "aux", 4668 "cfg_ahb"; 4669 4670 #clock-cells = <1>; 4671 #phy-cells = <0>; 4672 4673 status = "disabled"; 4674 }; 4675 4676 mdss_dp: displayport-controller@ae90000 { 4677 compatible = "qcom,sc7280-dp"; 4678 4679 reg = <0 0x0ae90000 0 0x200>, 4680 <0 0x0ae90200 0 0x200>, 4681 <0 0x0ae90400 0 0xc00>, 4682 <0 0x0ae91000 0 0x400>, 4683 <0 0x0ae91400 0 0x400>; 4684 4685 interrupt-parent = <&mdss>; 4686 interrupts = <12>; 4687 4688 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4689 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4690 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4691 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4692 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4693 clock-names = "core_iface", 4694 "core_aux", 4695 "ctrl_link", 4696 "ctrl_link_iface", 4697 "stream_pixel"; 4698 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4699 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4700 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4701 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4702 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 4703 phy-names = "dp"; 4704 4705 operating-points-v2 = <&dp_opp_table>; 4706 power-domains = <&rpmhpd SC7280_CX>; 4707 4708 #sound-dai-cells = <0>; 4709 4710 status = "disabled"; 4711 4712 ports { 4713 #address-cells = <1>; 4714 #size-cells = <0>; 4715 4716 port@0 { 4717 reg = <0>; 4718 dp_in: endpoint { 4719 remote-endpoint = <&dpu_intf0_out>; 4720 }; 4721 }; 4722 4723 port@1 { 4724 reg = <1>; 4725 mdss_dp_out: endpoint { }; 4726 }; 4727 }; 4728 4729 dp_opp_table: opp-table { 4730 compatible = "operating-points-v2"; 4731 4732 opp-160000000 { 4733 opp-hz = /bits/ 64 <160000000>; 4734 required-opps = <&rpmhpd_opp_low_svs>; 4735 }; 4736 4737 opp-270000000 { 4738 opp-hz = /bits/ 64 <270000000>; 4739 required-opps = <&rpmhpd_opp_svs>; 4740 }; 4741 4742 opp-540000000 { 4743 opp-hz = /bits/ 64 <540000000>; 4744 required-opps = <&rpmhpd_opp_svs_l1>; 4745 }; 4746 4747 opp-810000000 { 4748 opp-hz = /bits/ 64 <810000000>; 4749 required-opps = <&rpmhpd_opp_nom>; 4750 }; 4751 }; 4752 }; 4753 }; 4754 4755 pdc: interrupt-controller@b220000 { 4756 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 4757 reg = <0 0x0b220000 0 0x30000>; 4758 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 4759 <55 306 4>, <59 312 3>, <62 374 2>, 4760 <64 434 2>, <66 438 3>, <69 86 1>, 4761 <70 520 54>, <124 609 31>, <155 63 1>, 4762 <156 716 12>; 4763 #interrupt-cells = <2>; 4764 interrupt-parent = <&intc>; 4765 interrupt-controller; 4766 }; 4767 4768 pdc_reset: reset-controller@b5e0000 { 4769 compatible = "qcom,sc7280-pdc-global"; 4770 reg = <0 0x0b5e0000 0 0x20000>; 4771 #reset-cells = <1>; 4772 status = "reserved"; /* Owned by firmware */ 4773 }; 4774 4775 tsens0: thermal-sensor@c263000 { 4776 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4777 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4778 <0 0x0c222000 0 0x1ff>; /* SROT */ 4779 #qcom,sensors = <15>; 4780 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4781 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4782 interrupt-names = "uplow","critical"; 4783 #thermal-sensor-cells = <1>; 4784 }; 4785 4786 tsens1: thermal-sensor@c265000 { 4787 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 4788 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4789 <0 0x0c223000 0 0x1ff>; /* SROT */ 4790 #qcom,sensors = <12>; 4791 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 4792 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 4793 interrupt-names = "uplow","critical"; 4794 #thermal-sensor-cells = <1>; 4795 }; 4796 4797 aoss_reset: reset-controller@c2a0000 { 4798 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 4799 reg = <0 0x0c2a0000 0 0x31000>; 4800 #reset-cells = <1>; 4801 }; 4802 4803 aoss_qmp: power-management@c300000 { 4804 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 4805 reg = <0 0x0c300000 0 0x400>; 4806 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4807 IPCC_MPROC_SIGNAL_GLINK_QMP 4808 IRQ_TYPE_EDGE_RISING>; 4809 mboxes = <&ipcc IPCC_CLIENT_AOP 4810 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4811 4812 #clock-cells = <0>; 4813 }; 4814 4815 sram@c3f0000 { 4816 compatible = "qcom,rpmh-stats"; 4817 reg = <0 0x0c3f0000 0 0x400>; 4818 }; 4819 4820 spmi_bus: spmi@c440000 { 4821 compatible = "qcom,spmi-pmic-arb"; 4822 reg = <0 0x0c440000 0 0x1100>, 4823 <0 0x0c600000 0 0x2000000>, 4824 <0 0x0e600000 0 0x100000>, 4825 <0 0x0e700000 0 0xa0000>, 4826 <0 0x0c40a000 0 0x26000>; 4827 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4828 interrupt-names = "periph_irq"; 4829 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4830 qcom,ee = <0>; 4831 qcom,channel = <0>; 4832 #address-cells = <2>; 4833 #size-cells = <0>; 4834 interrupt-controller; 4835 #interrupt-cells = <4>; 4836 }; 4837 4838 tlmm: pinctrl@f100000 { 4839 compatible = "qcom,sc7280-pinctrl"; 4840 reg = <0 0x0f100000 0 0x300000>; 4841 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4842 gpio-controller; 4843 #gpio-cells = <2>; 4844 interrupt-controller; 4845 #interrupt-cells = <2>; 4846 gpio-ranges = <&tlmm 0 0 175>; 4847 wakeup-parent = <&pdc>; 4848 4849 cci0_default: cci0-default-state { 4850 pins = "gpio69", "gpio70"; 4851 function = "cci_i2c"; 4852 drive-strength = <2>; 4853 bias-pull-up; 4854 }; 4855 4856 cci0_sleep: cci0-sleep-state { 4857 pins = "gpio69", "gpio70"; 4858 function = "cci_i2c"; 4859 drive-strength = <2>; 4860 bias-pull-down; 4861 }; 4862 4863 cci1_default: cci1-default-state { 4864 pins = "gpio71", "gpio72"; 4865 function = "cci_i2c"; 4866 drive-strength = <2>; 4867 bias-pull-up; 4868 }; 4869 4870 cci1_sleep: cci1-sleep-state { 4871 pins = "gpio71", "gpio72"; 4872 function = "cci_i2c"; 4873 drive-strength = <2>; 4874 bias-pull-down; 4875 }; 4876 4877 cci2_default: cci2-default-state { 4878 pins = "gpio73", "gpio74"; 4879 function = "cci_i2c"; 4880 drive-strength = <2>; 4881 bias-pull-up; 4882 }; 4883 4884 cci2_sleep: cci2-sleep-state { 4885 pins = "gpio73", "gpio74"; 4886 function = "cci_i2c"; 4887 drive-strength = <2>; 4888 bias-pull-down; 4889 }; 4890 4891 cci3_default: cci3-default-state { 4892 pins = "gpio75", "gpio76"; 4893 function = "cci_i2c"; 4894 drive-strength = <2>; 4895 bias-pull-up; 4896 }; 4897 4898 cci3_sleep: cci3-sleep-state { 4899 pins = "gpio75", "gpio76"; 4900 function = "cci_i2c"; 4901 drive-strength = <2>; 4902 bias-pull-down; 4903 }; 4904 4905 dp_hot_plug_det: dp-hot-plug-det-state { 4906 pins = "gpio47"; 4907 function = "dp_hot"; 4908 }; 4909 4910 edp_hot_plug_det: edp-hot-plug-det-state { 4911 pins = "gpio60"; 4912 function = "edp_hot"; 4913 }; 4914 4915 mi2s0_data0: mi2s0-data0-state { 4916 pins = "gpio98"; 4917 function = "mi2s0_data0"; 4918 }; 4919 4920 mi2s0_data1: mi2s0-data1-state { 4921 pins = "gpio99"; 4922 function = "mi2s0_data1"; 4923 }; 4924 4925 mi2s0_mclk: mi2s0-mclk-state { 4926 pins = "gpio96"; 4927 function = "pri_mi2s"; 4928 }; 4929 4930 mi2s0_sclk: mi2s0-sclk-state { 4931 pins = "gpio97"; 4932 function = "mi2s0_sck"; 4933 }; 4934 4935 mi2s0_ws: mi2s0-ws-state { 4936 pins = "gpio100"; 4937 function = "mi2s0_ws"; 4938 }; 4939 4940 mi2s1_data0: mi2s1-data0-state { 4941 pins = "gpio107"; 4942 function = "mi2s1_data0"; 4943 }; 4944 4945 mi2s1_sclk: mi2s1-sclk-state { 4946 pins = "gpio106"; 4947 function = "mi2s1_sck"; 4948 }; 4949 4950 mi2s1_ws: mi2s1-ws-state { 4951 pins = "gpio108"; 4952 function = "mi2s1_ws"; 4953 }; 4954 4955 pcie1_clkreq_n: pcie1-clkreq-n-state { 4956 pins = "gpio79"; 4957 function = "pcie1_clkreqn"; 4958 }; 4959 4960 qspi_clk: qspi-clk-state { 4961 pins = "gpio14"; 4962 function = "qspi_clk"; 4963 }; 4964 4965 qspi_cs0: qspi-cs0-state { 4966 pins = "gpio15"; 4967 function = "qspi_cs"; 4968 }; 4969 4970 qspi_cs1: qspi-cs1-state { 4971 pins = "gpio19"; 4972 function = "qspi_cs"; 4973 }; 4974 4975 qspi_data0: qspi-data0-state { 4976 pins = "gpio12"; 4977 function = "qspi_data"; 4978 }; 4979 4980 qspi_data1: qspi-data1-state { 4981 pins = "gpio13"; 4982 function = "qspi_data"; 4983 }; 4984 4985 qspi_data23: qspi-data23-state { 4986 pins = "gpio16", "gpio17"; 4987 function = "qspi_data"; 4988 }; 4989 4990 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4991 pins = "gpio0", "gpio1"; 4992 function = "qup00"; 4993 }; 4994 4995 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4996 pins = "gpio4", "gpio5"; 4997 function = "qup01"; 4998 }; 4999 5000 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 5001 pins = "gpio8", "gpio9"; 5002 function = "qup02"; 5003 }; 5004 5005 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 5006 pins = "gpio12", "gpio13"; 5007 function = "qup03"; 5008 }; 5009 5010 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 5011 pins = "gpio16", "gpio17"; 5012 function = "qup04"; 5013 }; 5014 5015 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 5016 pins = "gpio20", "gpio21"; 5017 function = "qup05"; 5018 }; 5019 5020 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 5021 pins = "gpio24", "gpio25"; 5022 function = "qup06"; 5023 }; 5024 5025 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 5026 pins = "gpio28", "gpio29"; 5027 function = "qup07"; 5028 }; 5029 5030 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 5031 pins = "gpio32", "gpio33"; 5032 function = "qup10"; 5033 }; 5034 5035 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 5036 pins = "gpio36", "gpio37"; 5037 function = "qup11"; 5038 }; 5039 5040 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 5041 pins = "gpio40", "gpio41"; 5042 function = "qup12"; 5043 }; 5044 5045 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 5046 pins = "gpio44", "gpio45"; 5047 function = "qup13"; 5048 }; 5049 5050 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 5051 pins = "gpio48", "gpio49"; 5052 function = "qup14"; 5053 }; 5054 5055 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 5056 pins = "gpio52", "gpio53"; 5057 function = "qup15"; 5058 }; 5059 5060 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 5061 pins = "gpio56", "gpio57"; 5062 function = "qup16"; 5063 }; 5064 5065 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 5066 pins = "gpio60", "gpio61"; 5067 function = "qup17"; 5068 }; 5069 5070 qup_spi0_data_clk: qup-spi0-data-clk-state { 5071 pins = "gpio0", "gpio1", "gpio2"; 5072 function = "qup00"; 5073 }; 5074 5075 qup_spi0_cs: qup-spi0-cs-state { 5076 pins = "gpio3"; 5077 function = "qup00"; 5078 }; 5079 5080 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 5081 pins = "gpio3"; 5082 function = "gpio"; 5083 }; 5084 5085 qup_spi1_data_clk: qup-spi1-data-clk-state { 5086 pins = "gpio4", "gpio5", "gpio6"; 5087 function = "qup01"; 5088 }; 5089 5090 qup_spi1_cs: qup-spi1-cs-state { 5091 pins = "gpio7"; 5092 function = "qup01"; 5093 }; 5094 5095 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 5096 pins = "gpio7"; 5097 function = "gpio"; 5098 }; 5099 5100 qup_spi2_data_clk: qup-spi2-data-clk-state { 5101 pins = "gpio8", "gpio9", "gpio10"; 5102 function = "qup02"; 5103 }; 5104 5105 qup_spi2_cs: qup-spi2-cs-state { 5106 pins = "gpio11"; 5107 function = "qup02"; 5108 }; 5109 5110 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 5111 pins = "gpio11"; 5112 function = "gpio"; 5113 }; 5114 5115 qup_spi3_data_clk: qup-spi3-data-clk-state { 5116 pins = "gpio12", "gpio13", "gpio14"; 5117 function = "qup03"; 5118 }; 5119 5120 qup_spi3_cs: qup-spi3-cs-state { 5121 pins = "gpio15"; 5122 function = "qup03"; 5123 }; 5124 5125 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 5126 pins = "gpio15"; 5127 function = "gpio"; 5128 }; 5129 5130 qup_spi4_data_clk: qup-spi4-data-clk-state { 5131 pins = "gpio16", "gpio17", "gpio18"; 5132 function = "qup04"; 5133 }; 5134 5135 qup_spi4_cs: qup-spi4-cs-state { 5136 pins = "gpio19"; 5137 function = "qup04"; 5138 }; 5139 5140 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 5141 pins = "gpio19"; 5142 function = "gpio"; 5143 }; 5144 5145 qup_spi5_data_clk: qup-spi5-data-clk-state { 5146 pins = "gpio20", "gpio21", "gpio22"; 5147 function = "qup05"; 5148 }; 5149 5150 qup_spi5_cs: qup-spi5-cs-state { 5151 pins = "gpio23"; 5152 function = "qup05"; 5153 }; 5154 5155 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 5156 pins = "gpio23"; 5157 function = "gpio"; 5158 }; 5159 5160 qup_spi6_data_clk: qup-spi6-data-clk-state { 5161 pins = "gpio24", "gpio25", "gpio26"; 5162 function = "qup06"; 5163 }; 5164 5165 qup_spi6_cs: qup-spi6-cs-state { 5166 pins = "gpio27"; 5167 function = "qup06"; 5168 }; 5169 5170 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 5171 pins = "gpio27"; 5172 function = "gpio"; 5173 }; 5174 5175 qup_spi7_data_clk: qup-spi7-data-clk-state { 5176 pins = "gpio28", "gpio29", "gpio30"; 5177 function = "qup07"; 5178 }; 5179 5180 qup_spi7_cs: qup-spi7-cs-state { 5181 pins = "gpio31"; 5182 function = "qup07"; 5183 }; 5184 5185 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 5186 pins = "gpio31"; 5187 function = "gpio"; 5188 }; 5189 5190 qup_spi8_data_clk: qup-spi8-data-clk-state { 5191 pins = "gpio32", "gpio33", "gpio34"; 5192 function = "qup10"; 5193 }; 5194 5195 qup_spi8_cs: qup-spi8-cs-state { 5196 pins = "gpio35"; 5197 function = "qup10"; 5198 }; 5199 5200 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 5201 pins = "gpio35"; 5202 function = "gpio"; 5203 }; 5204 5205 qup_spi9_data_clk: qup-spi9-data-clk-state { 5206 pins = "gpio36", "gpio37", "gpio38"; 5207 function = "qup11"; 5208 }; 5209 5210 qup_spi9_cs: qup-spi9-cs-state { 5211 pins = "gpio39"; 5212 function = "qup11"; 5213 }; 5214 5215 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 5216 pins = "gpio39"; 5217 function = "gpio"; 5218 }; 5219 5220 qup_spi10_data_clk: qup-spi10-data-clk-state { 5221 pins = "gpio40", "gpio41", "gpio42"; 5222 function = "qup12"; 5223 }; 5224 5225 qup_spi10_cs: qup-spi10-cs-state { 5226 pins = "gpio43"; 5227 function = "qup12"; 5228 }; 5229 5230 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 5231 pins = "gpio43"; 5232 function = "gpio"; 5233 }; 5234 5235 qup_spi11_data_clk: qup-spi11-data-clk-state { 5236 pins = "gpio44", "gpio45", "gpio46"; 5237 function = "qup13"; 5238 }; 5239 5240 qup_spi11_cs: qup-spi11-cs-state { 5241 pins = "gpio47"; 5242 function = "qup13"; 5243 }; 5244 5245 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 5246 pins = "gpio47"; 5247 function = "gpio"; 5248 }; 5249 5250 qup_spi12_data_clk: qup-spi12-data-clk-state { 5251 pins = "gpio48", "gpio49", "gpio50"; 5252 function = "qup14"; 5253 }; 5254 5255 qup_spi12_cs: qup-spi12-cs-state { 5256 pins = "gpio51"; 5257 function = "qup14"; 5258 }; 5259 5260 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 5261 pins = "gpio51"; 5262 function = "gpio"; 5263 }; 5264 5265 qup_spi13_data_clk: qup-spi13-data-clk-state { 5266 pins = "gpio52", "gpio53", "gpio54"; 5267 function = "qup15"; 5268 }; 5269 5270 qup_spi13_cs: qup-spi13-cs-state { 5271 pins = "gpio55"; 5272 function = "qup15"; 5273 }; 5274 5275 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 5276 pins = "gpio55"; 5277 function = "gpio"; 5278 }; 5279 5280 qup_spi14_data_clk: qup-spi14-data-clk-state { 5281 pins = "gpio56", "gpio57", "gpio58"; 5282 function = "qup16"; 5283 }; 5284 5285 qup_spi14_cs: qup-spi14-cs-state { 5286 pins = "gpio59"; 5287 function = "qup16"; 5288 }; 5289 5290 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 5291 pins = "gpio59"; 5292 function = "gpio"; 5293 }; 5294 5295 qup_spi15_data_clk: qup-spi15-data-clk-state { 5296 pins = "gpio60", "gpio61", "gpio62"; 5297 function = "qup17"; 5298 }; 5299 5300 qup_spi15_cs: qup-spi15-cs-state { 5301 pins = "gpio63"; 5302 function = "qup17"; 5303 }; 5304 5305 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 5306 pins = "gpio63"; 5307 function = "gpio"; 5308 }; 5309 5310 qup_uart0_cts: qup-uart0-cts-state { 5311 pins = "gpio0"; 5312 function = "qup00"; 5313 }; 5314 5315 qup_uart0_rts: qup-uart0-rts-state { 5316 pins = "gpio1"; 5317 function = "qup00"; 5318 }; 5319 5320 qup_uart0_tx: qup-uart0-tx-state { 5321 pins = "gpio2"; 5322 function = "qup00"; 5323 }; 5324 5325 qup_uart0_rx: qup-uart0-rx-state { 5326 pins = "gpio3"; 5327 function = "qup00"; 5328 }; 5329 5330 qup_uart1_cts: qup-uart1-cts-state { 5331 pins = "gpio4"; 5332 function = "qup01"; 5333 }; 5334 5335 qup_uart1_rts: qup-uart1-rts-state { 5336 pins = "gpio5"; 5337 function = "qup01"; 5338 }; 5339 5340 qup_uart1_tx: qup-uart1-tx-state { 5341 pins = "gpio6"; 5342 function = "qup01"; 5343 }; 5344 5345 qup_uart1_rx: qup-uart1-rx-state { 5346 pins = "gpio7"; 5347 function = "qup01"; 5348 }; 5349 5350 qup_uart2_cts: qup-uart2-cts-state { 5351 pins = "gpio8"; 5352 function = "qup02"; 5353 }; 5354 5355 qup_uart2_rts: qup-uart2-rts-state { 5356 pins = "gpio9"; 5357 function = "qup02"; 5358 }; 5359 5360 qup_uart2_tx: qup-uart2-tx-state { 5361 pins = "gpio10"; 5362 function = "qup02"; 5363 }; 5364 5365 qup_uart2_rx: qup-uart2-rx-state { 5366 pins = "gpio11"; 5367 function = "qup02"; 5368 }; 5369 5370 qup_uart3_cts: qup-uart3-cts-state { 5371 pins = "gpio12"; 5372 function = "qup03"; 5373 }; 5374 5375 qup_uart3_rts: qup-uart3-rts-state { 5376 pins = "gpio13"; 5377 function = "qup03"; 5378 }; 5379 5380 qup_uart3_tx: qup-uart3-tx-state { 5381 pins = "gpio14"; 5382 function = "qup03"; 5383 }; 5384 5385 qup_uart3_rx: qup-uart3-rx-state { 5386 pins = "gpio15"; 5387 function = "qup03"; 5388 }; 5389 5390 qup_uart4_cts: qup-uart4-cts-state { 5391 pins = "gpio16"; 5392 function = "qup04"; 5393 }; 5394 5395 qup_uart4_rts: qup-uart4-rts-state { 5396 pins = "gpio17"; 5397 function = "qup04"; 5398 }; 5399 5400 qup_uart4_tx: qup-uart4-tx-state { 5401 pins = "gpio18"; 5402 function = "qup04"; 5403 }; 5404 5405 qup_uart4_rx: qup-uart4-rx-state { 5406 pins = "gpio19"; 5407 function = "qup04"; 5408 }; 5409 5410 qup_uart5_cts: qup-uart5-cts-state { 5411 pins = "gpio20"; 5412 function = "qup05"; 5413 }; 5414 5415 qup_uart5_rts: qup-uart5-rts-state { 5416 pins = "gpio21"; 5417 function = "qup05"; 5418 }; 5419 5420 qup_uart5_tx: qup-uart5-tx-state { 5421 pins = "gpio22"; 5422 function = "qup05"; 5423 }; 5424 5425 qup_uart5_rx: qup-uart5-rx-state { 5426 pins = "gpio23"; 5427 function = "qup05"; 5428 }; 5429 5430 qup_uart6_cts: qup-uart6-cts-state { 5431 pins = "gpio24"; 5432 function = "qup06"; 5433 }; 5434 5435 qup_uart6_rts: qup-uart6-rts-state { 5436 pins = "gpio25"; 5437 function = "qup06"; 5438 }; 5439 5440 qup_uart6_tx: qup-uart6-tx-state { 5441 pins = "gpio26"; 5442 function = "qup06"; 5443 }; 5444 5445 qup_uart6_rx: qup-uart6-rx-state { 5446 pins = "gpio27"; 5447 function = "qup06"; 5448 }; 5449 5450 qup_uart7_cts: qup-uart7-cts-state { 5451 pins = "gpio28"; 5452 function = "qup07"; 5453 }; 5454 5455 qup_uart7_rts: qup-uart7-rts-state { 5456 pins = "gpio29"; 5457 function = "qup07"; 5458 }; 5459 5460 qup_uart7_tx: qup-uart7-tx-state { 5461 pins = "gpio30"; 5462 function = "qup07"; 5463 }; 5464 5465 qup_uart7_rx: qup-uart7-rx-state { 5466 pins = "gpio31"; 5467 function = "qup07"; 5468 }; 5469 5470 qup_uart8_cts: qup-uart8-cts-state { 5471 pins = "gpio32"; 5472 function = "qup10"; 5473 }; 5474 5475 qup_uart8_rts: qup-uart8-rts-state { 5476 pins = "gpio33"; 5477 function = "qup10"; 5478 }; 5479 5480 qup_uart8_tx: qup-uart8-tx-state { 5481 pins = "gpio34"; 5482 function = "qup10"; 5483 }; 5484 5485 qup_uart8_rx: qup-uart8-rx-state { 5486 pins = "gpio35"; 5487 function = "qup10"; 5488 }; 5489 5490 qup_uart9_cts: qup-uart9-cts-state { 5491 pins = "gpio36"; 5492 function = "qup11"; 5493 }; 5494 5495 qup_uart9_rts: qup-uart9-rts-state { 5496 pins = "gpio37"; 5497 function = "qup11"; 5498 }; 5499 5500 qup_uart9_tx: qup-uart9-tx-state { 5501 pins = "gpio38"; 5502 function = "qup11"; 5503 }; 5504 5505 qup_uart9_rx: qup-uart9-rx-state { 5506 pins = "gpio39"; 5507 function = "qup11"; 5508 }; 5509 5510 qup_uart10_cts: qup-uart10-cts-state { 5511 pins = "gpio40"; 5512 function = "qup12"; 5513 }; 5514 5515 qup_uart10_rts: qup-uart10-rts-state { 5516 pins = "gpio41"; 5517 function = "qup12"; 5518 }; 5519 5520 qup_uart10_tx: qup-uart10-tx-state { 5521 pins = "gpio42"; 5522 function = "qup12"; 5523 }; 5524 5525 qup_uart10_rx: qup-uart10-rx-state { 5526 pins = "gpio43"; 5527 function = "qup12"; 5528 }; 5529 5530 qup_uart11_cts: qup-uart11-cts-state { 5531 pins = "gpio44"; 5532 function = "qup13"; 5533 }; 5534 5535 qup_uart11_rts: qup-uart11-rts-state { 5536 pins = "gpio45"; 5537 function = "qup13"; 5538 }; 5539 5540 qup_uart11_tx: qup-uart11-tx-state { 5541 pins = "gpio46"; 5542 function = "qup13"; 5543 }; 5544 5545 qup_uart11_rx: qup-uart11-rx-state { 5546 pins = "gpio47"; 5547 function = "qup13"; 5548 }; 5549 5550 qup_uart12_cts: qup-uart12-cts-state { 5551 pins = "gpio48"; 5552 function = "qup14"; 5553 }; 5554 5555 qup_uart12_rts: qup-uart12-rts-state { 5556 pins = "gpio49"; 5557 function = "qup14"; 5558 }; 5559 5560 qup_uart12_tx: qup-uart12-tx-state { 5561 pins = "gpio50"; 5562 function = "qup14"; 5563 }; 5564 5565 qup_uart12_rx: qup-uart12-rx-state { 5566 pins = "gpio51"; 5567 function = "qup14"; 5568 }; 5569 5570 qup_uart13_cts: qup-uart13-cts-state { 5571 pins = "gpio52"; 5572 function = "qup15"; 5573 }; 5574 5575 qup_uart13_rts: qup-uart13-rts-state { 5576 pins = "gpio53"; 5577 function = "qup15"; 5578 }; 5579 5580 qup_uart13_tx: qup-uart13-tx-state { 5581 pins = "gpio54"; 5582 function = "qup15"; 5583 }; 5584 5585 qup_uart13_rx: qup-uart13-rx-state { 5586 pins = "gpio55"; 5587 function = "qup15"; 5588 }; 5589 5590 qup_uart14_cts: qup-uart14-cts-state { 5591 pins = "gpio56"; 5592 function = "qup16"; 5593 }; 5594 5595 qup_uart14_rts: qup-uart14-rts-state { 5596 pins = "gpio57"; 5597 function = "qup16"; 5598 }; 5599 5600 qup_uart14_tx: qup-uart14-tx-state { 5601 pins = "gpio58"; 5602 function = "qup16"; 5603 }; 5604 5605 qup_uart14_rx: qup-uart14-rx-state { 5606 pins = "gpio59"; 5607 function = "qup16"; 5608 }; 5609 5610 qup_uart15_cts: qup-uart15-cts-state { 5611 pins = "gpio60"; 5612 function = "qup17"; 5613 }; 5614 5615 qup_uart15_rts: qup-uart15-rts-state { 5616 pins = "gpio61"; 5617 function = "qup17"; 5618 }; 5619 5620 qup_uart15_tx: qup-uart15-tx-state { 5621 pins = "gpio62"; 5622 function = "qup17"; 5623 }; 5624 5625 qup_uart15_rx: qup-uart15-rx-state { 5626 pins = "gpio63"; 5627 function = "qup17"; 5628 }; 5629 5630 sdc1_clk: sdc1-clk-state { 5631 pins = "sdc1_clk"; 5632 }; 5633 5634 sdc1_cmd: sdc1-cmd-state { 5635 pins = "sdc1_cmd"; 5636 }; 5637 5638 sdc1_data: sdc1-data-state { 5639 pins = "sdc1_data"; 5640 }; 5641 5642 sdc1_rclk: sdc1-rclk-state { 5643 pins = "sdc1_rclk"; 5644 }; 5645 5646 sdc1_clk_sleep: sdc1-clk-sleep-state { 5647 pins = "sdc1_clk"; 5648 drive-strength = <2>; 5649 bias-bus-hold; 5650 }; 5651 5652 sdc1_cmd_sleep: sdc1-cmd-sleep-state { 5653 pins = "sdc1_cmd"; 5654 drive-strength = <2>; 5655 bias-bus-hold; 5656 }; 5657 5658 sdc1_data_sleep: sdc1-data-sleep-state { 5659 pins = "sdc1_data"; 5660 drive-strength = <2>; 5661 bias-bus-hold; 5662 }; 5663 5664 sdc1_rclk_sleep: sdc1-rclk-sleep-state { 5665 pins = "sdc1_rclk"; 5666 drive-strength = <2>; 5667 bias-bus-hold; 5668 }; 5669 5670 sdc2_clk: sdc2-clk-state { 5671 pins = "sdc2_clk"; 5672 }; 5673 5674 sdc2_cmd: sdc2-cmd-state { 5675 pins = "sdc2_cmd"; 5676 }; 5677 5678 sdc2_data: sdc2-data-state { 5679 pins = "sdc2_data"; 5680 }; 5681 5682 sdc2_clk_sleep: sdc2-clk-sleep-state { 5683 pins = "sdc2_clk"; 5684 drive-strength = <2>; 5685 bias-bus-hold; 5686 }; 5687 5688 sdc2_cmd_sleep: sdc2-cmd-sleep-state { 5689 pins = "sdc2_cmd"; 5690 drive-strength = <2>; 5691 bias-bus-hold; 5692 }; 5693 5694 sdc2_data_sleep: sdc2-data-sleep-state { 5695 pins = "sdc2_data"; 5696 drive-strength = <2>; 5697 bias-bus-hold; 5698 }; 5699 }; 5700 5701 sram@146a5000 { 5702 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 5703 reg = <0 0x146a5000 0 0x6000>; 5704 5705 #address-cells = <1>; 5706 #size-cells = <1>; 5707 5708 ranges = <0 0 0x146a5000 0x6000>; 5709 5710 pil-reloc@594c { 5711 compatible = "qcom,pil-reloc-info"; 5712 reg = <0x594c 0xc8>; 5713 }; 5714 }; 5715 5716 apps_smmu: iommu@15000000 { 5717 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 5718 reg = <0 0x15000000 0 0x100000>; 5719 #iommu-cells = <2>; 5720 #global-interrupts = <1>; 5721 dma-coherent; 5722 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5723 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 5724 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5725 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5726 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5727 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5728 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5729 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5730 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5731 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5732 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5733 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5734 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5735 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5736 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5737 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5738 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5739 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5740 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5741 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5742 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5743 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5744 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5745 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5746 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5747 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5748 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5749 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5750 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5751 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5752 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5753 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5754 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5755 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5756 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5757 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5758 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5759 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5760 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5761 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5762 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5763 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5764 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5765 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5766 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5767 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5768 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5769 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5770 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5771 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5772 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5773 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5774 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5775 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5776 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5777 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5778 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5779 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5780 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5781 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5782 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5783 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5784 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5785 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5786 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5787 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5788 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5789 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5790 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5791 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5792 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5793 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5794 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5795 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5796 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5797 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5798 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5799 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5800 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5801 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5802 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 5803 }; 5804 5805 intc: interrupt-controller@17a00000 { 5806 compatible = "arm,gic-v3"; 5807 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 5808 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 5809 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 5810 #interrupt-cells = <3>; 5811 interrupt-controller; 5812 #address-cells = <2>; 5813 #size-cells = <2>; 5814 ranges; 5815 5816 msi-controller@17a40000 { 5817 compatible = "arm,gic-v3-its"; 5818 reg = <0 0x17a40000 0 0x20000>; 5819 msi-controller; 5820 #msi-cells = <1>; 5821 status = "disabled"; 5822 }; 5823 }; 5824 5825 watchdog: watchdog@17c10000 { 5826 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 5827 reg = <0 0x17c10000 0 0x1000>; 5828 clocks = <&sleep_clk>; 5829 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 5830 status = "reserved"; /* Owned by Gunyah hyp */ 5831 }; 5832 5833 timer@17c20000 { 5834 #address-cells = <1>; 5835 #size-cells = <1>; 5836 ranges = <0 0 0 0x20000000>; 5837 compatible = "arm,armv7-timer-mem"; 5838 reg = <0 0x17c20000 0 0x1000>; 5839 5840 frame@17c21000 { 5841 frame-number = <0>; 5842 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5843 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5844 reg = <0x17c21000 0x1000>, 5845 <0x17c22000 0x1000>; 5846 }; 5847 5848 frame@17c23000 { 5849 frame-number = <1>; 5850 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5851 reg = <0x17c23000 0x1000>; 5852 status = "disabled"; 5853 }; 5854 5855 frame@17c25000 { 5856 frame-number = <2>; 5857 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5858 reg = <0x17c25000 0x1000>; 5859 status = "disabled"; 5860 }; 5861 5862 frame@17c27000 { 5863 frame-number = <3>; 5864 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5865 reg = <0x17c27000 0x1000>; 5866 status = "disabled"; 5867 }; 5868 5869 frame@17c29000 { 5870 frame-number = <4>; 5871 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5872 reg = <0x17c29000 0x1000>; 5873 status = "disabled"; 5874 }; 5875 5876 frame@17c2b000 { 5877 frame-number = <5>; 5878 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5879 reg = <0x17c2b000 0x1000>; 5880 status = "disabled"; 5881 }; 5882 5883 frame@17c2d000 { 5884 frame-number = <6>; 5885 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5886 reg = <0x17c2d000 0x1000>; 5887 status = "disabled"; 5888 }; 5889 }; 5890 5891 apps_rsc: rsc@18200000 { 5892 compatible = "qcom,rpmh-rsc"; 5893 reg = <0 0x18200000 0 0x10000>, 5894 <0 0x18210000 0 0x10000>, 5895 <0 0x18220000 0 0x10000>; 5896 reg-names = "drv-0", "drv-1", "drv-2"; 5897 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5898 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5899 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5900 qcom,tcs-offset = <0xd00>; 5901 qcom,drv-id = <2>; 5902 qcom,tcs-config = <ACTIVE_TCS 2>, 5903 <SLEEP_TCS 3>, 5904 <WAKE_TCS 3>, 5905 <CONTROL_TCS 1>; 5906 power-domains = <&CLUSTER_PD>; 5907 5908 apps_bcm_voter: bcm-voter { 5909 compatible = "qcom,bcm-voter"; 5910 }; 5911 5912 rpmhpd: power-controller { 5913 compatible = "qcom,sc7280-rpmhpd"; 5914 #power-domain-cells = <1>; 5915 operating-points-v2 = <&rpmhpd_opp_table>; 5916 5917 rpmhpd_opp_table: opp-table { 5918 compatible = "operating-points-v2"; 5919 5920 rpmhpd_opp_ret: opp1 { 5921 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5922 }; 5923 5924 rpmhpd_opp_low_svs: opp2 { 5925 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5926 }; 5927 5928 rpmhpd_opp_svs: opp3 { 5929 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5930 }; 5931 5932 rpmhpd_opp_svs_l1: opp4 { 5933 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5934 }; 5935 5936 rpmhpd_opp_svs_l2: opp5 { 5937 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5938 }; 5939 5940 rpmhpd_opp_nom: opp6 { 5941 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5942 }; 5943 5944 rpmhpd_opp_nom_l1: opp7 { 5945 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5946 }; 5947 5948 rpmhpd_opp_turbo: opp8 { 5949 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5950 }; 5951 5952 rpmhpd_opp_turbo_l1: opp9 { 5953 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5954 }; 5955 }; 5956 }; 5957 5958 rpmhcc: clock-controller { 5959 compatible = "qcom,sc7280-rpmh-clk"; 5960 clocks = <&xo_board>; 5961 clock-names = "xo"; 5962 #clock-cells = <1>; 5963 }; 5964 }; 5965 5966 epss_l3: interconnect@18590000 { 5967 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3"; 5968 reg = <0 0x18590000 0 0x1000>; 5969 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5970 clock-names = "xo", "alternate"; 5971 #interconnect-cells = <1>; 5972 }; 5973 5974 cpufreq_hw: cpufreq@18591000 { 5975 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss"; 5976 reg = <0 0x18591000 0 0x1000>, 5977 <0 0x18592000 0 0x1000>, 5978 <0 0x18593000 0 0x1000>; 5979 5980 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 5981 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5982 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 5983 interrupt-names = "dcvsh-irq-0", 5984 "dcvsh-irq-1", 5985 "dcvsh-irq-2"; 5986 5987 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5988 clock-names = "xo", "alternate"; 5989 #freq-domain-cells = <1>; 5990 #clock-cells = <1>; 5991 }; 5992 }; 5993 5994 thermal_zones: thermal-zones { 5995 cpu0-thermal { 5996 polling-delay-passive = <250>; 5997 polling-delay = <0>; 5998 5999 thermal-sensors = <&tsens0 1>; 6000 6001 trips { 6002 cpu0_alert0: trip-point0 { 6003 temperature = <90000>; 6004 hysteresis = <2000>; 6005 type = "passive"; 6006 }; 6007 6008 cpu0_alert1: trip-point1 { 6009 temperature = <95000>; 6010 hysteresis = <2000>; 6011 type = "passive"; 6012 }; 6013 6014 cpu0_crit: cpu-crit { 6015 temperature = <110000>; 6016 hysteresis = <0>; 6017 type = "critical"; 6018 }; 6019 }; 6020 6021 cooling-maps { 6022 map0 { 6023 trip = <&cpu0_alert0>; 6024 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6025 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6026 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6027 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6028 }; 6029 map1 { 6030 trip = <&cpu0_alert1>; 6031 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6032 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6033 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6034 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6035 }; 6036 }; 6037 }; 6038 6039 cpu1-thermal { 6040 polling-delay-passive = <250>; 6041 polling-delay = <0>; 6042 6043 thermal-sensors = <&tsens0 2>; 6044 6045 trips { 6046 cpu1_alert0: trip-point0 { 6047 temperature = <90000>; 6048 hysteresis = <2000>; 6049 type = "passive"; 6050 }; 6051 6052 cpu1_alert1: trip-point1 { 6053 temperature = <95000>; 6054 hysteresis = <2000>; 6055 type = "passive"; 6056 }; 6057 6058 cpu1_crit: cpu-crit { 6059 temperature = <110000>; 6060 hysteresis = <0>; 6061 type = "critical"; 6062 }; 6063 }; 6064 6065 cooling-maps { 6066 map0 { 6067 trip = <&cpu1_alert0>; 6068 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6069 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6070 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6071 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6072 }; 6073 map1 { 6074 trip = <&cpu1_alert1>; 6075 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6076 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6077 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6078 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6079 }; 6080 }; 6081 }; 6082 6083 cpu2-thermal { 6084 polling-delay-passive = <250>; 6085 polling-delay = <0>; 6086 6087 thermal-sensors = <&tsens0 3>; 6088 6089 trips { 6090 cpu2_alert0: trip-point0 { 6091 temperature = <90000>; 6092 hysteresis = <2000>; 6093 type = "passive"; 6094 }; 6095 6096 cpu2_alert1: trip-point1 { 6097 temperature = <95000>; 6098 hysteresis = <2000>; 6099 type = "passive"; 6100 }; 6101 6102 cpu2_crit: cpu-crit { 6103 temperature = <110000>; 6104 hysteresis = <0>; 6105 type = "critical"; 6106 }; 6107 }; 6108 6109 cooling-maps { 6110 map0 { 6111 trip = <&cpu2_alert0>; 6112 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6113 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6114 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6115 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6116 }; 6117 map1 { 6118 trip = <&cpu2_alert1>; 6119 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6120 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6121 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6122 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6123 }; 6124 }; 6125 }; 6126 6127 cpu3-thermal { 6128 polling-delay-passive = <250>; 6129 polling-delay = <0>; 6130 6131 thermal-sensors = <&tsens0 4>; 6132 6133 trips { 6134 cpu3_alert0: trip-point0 { 6135 temperature = <90000>; 6136 hysteresis = <2000>; 6137 type = "passive"; 6138 }; 6139 6140 cpu3_alert1: trip-point1 { 6141 temperature = <95000>; 6142 hysteresis = <2000>; 6143 type = "passive"; 6144 }; 6145 6146 cpu3_crit: cpu-crit { 6147 temperature = <110000>; 6148 hysteresis = <0>; 6149 type = "critical"; 6150 }; 6151 }; 6152 6153 cooling-maps { 6154 map0 { 6155 trip = <&cpu3_alert0>; 6156 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6157 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6158 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6159 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6160 }; 6161 map1 { 6162 trip = <&cpu3_alert1>; 6163 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6164 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6165 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6166 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6167 }; 6168 }; 6169 }; 6170 6171 cpu4-thermal { 6172 polling-delay-passive = <250>; 6173 polling-delay = <0>; 6174 6175 thermal-sensors = <&tsens0 7>; 6176 6177 trips { 6178 cpu4_alert0: trip-point0 { 6179 temperature = <90000>; 6180 hysteresis = <2000>; 6181 type = "passive"; 6182 }; 6183 6184 cpu4_alert1: trip-point1 { 6185 temperature = <95000>; 6186 hysteresis = <2000>; 6187 type = "passive"; 6188 }; 6189 6190 cpu4_crit: cpu-crit { 6191 temperature = <110000>; 6192 hysteresis = <0>; 6193 type = "critical"; 6194 }; 6195 }; 6196 6197 cooling-maps { 6198 map0 { 6199 trip = <&cpu4_alert0>; 6200 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6201 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6202 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6203 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6204 }; 6205 map1 { 6206 trip = <&cpu4_alert1>; 6207 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6208 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6209 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6210 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6211 }; 6212 }; 6213 }; 6214 6215 cpu5-thermal { 6216 polling-delay-passive = <250>; 6217 polling-delay = <0>; 6218 6219 thermal-sensors = <&tsens0 8>; 6220 6221 trips { 6222 cpu5_alert0: trip-point0 { 6223 temperature = <90000>; 6224 hysteresis = <2000>; 6225 type = "passive"; 6226 }; 6227 6228 cpu5_alert1: trip-point1 { 6229 temperature = <95000>; 6230 hysteresis = <2000>; 6231 type = "passive"; 6232 }; 6233 6234 cpu5_crit: cpu-crit { 6235 temperature = <110000>; 6236 hysteresis = <0>; 6237 type = "critical"; 6238 }; 6239 }; 6240 6241 cooling-maps { 6242 map0 { 6243 trip = <&cpu5_alert0>; 6244 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6245 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6246 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6247 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6248 }; 6249 map1 { 6250 trip = <&cpu5_alert1>; 6251 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6252 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6253 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6254 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6255 }; 6256 }; 6257 }; 6258 6259 cpu6-thermal { 6260 polling-delay-passive = <250>; 6261 polling-delay = <0>; 6262 6263 thermal-sensors = <&tsens0 9>; 6264 6265 trips { 6266 cpu6_alert0: trip-point0 { 6267 temperature = <90000>; 6268 hysteresis = <2000>; 6269 type = "passive"; 6270 }; 6271 6272 cpu6_alert1: trip-point1 { 6273 temperature = <95000>; 6274 hysteresis = <2000>; 6275 type = "passive"; 6276 }; 6277 6278 cpu6_crit: cpu-crit { 6279 temperature = <110000>; 6280 hysteresis = <0>; 6281 type = "critical"; 6282 }; 6283 }; 6284 6285 cooling-maps { 6286 map0 { 6287 trip = <&cpu6_alert0>; 6288 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6289 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6290 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6291 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6292 }; 6293 map1 { 6294 trip = <&cpu6_alert1>; 6295 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6296 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6297 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6298 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6299 }; 6300 }; 6301 }; 6302 6303 cpu7-thermal { 6304 polling-delay-passive = <250>; 6305 polling-delay = <0>; 6306 6307 thermal-sensors = <&tsens0 10>; 6308 6309 trips { 6310 cpu7_alert0: trip-point0 { 6311 temperature = <90000>; 6312 hysteresis = <2000>; 6313 type = "passive"; 6314 }; 6315 6316 cpu7_alert1: trip-point1 { 6317 temperature = <95000>; 6318 hysteresis = <2000>; 6319 type = "passive"; 6320 }; 6321 6322 cpu7_crit: cpu-crit { 6323 temperature = <110000>; 6324 hysteresis = <0>; 6325 type = "critical"; 6326 }; 6327 }; 6328 6329 cooling-maps { 6330 map0 { 6331 trip = <&cpu7_alert0>; 6332 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6333 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6334 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6335 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6336 }; 6337 map1 { 6338 trip = <&cpu7_alert1>; 6339 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6340 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6341 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6342 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6343 }; 6344 }; 6345 }; 6346 6347 cpu8-thermal { 6348 polling-delay-passive = <250>; 6349 polling-delay = <0>; 6350 6351 thermal-sensors = <&tsens0 11>; 6352 6353 trips { 6354 cpu8_alert0: trip-point0 { 6355 temperature = <90000>; 6356 hysteresis = <2000>; 6357 type = "passive"; 6358 }; 6359 6360 cpu8_alert1: trip-point1 { 6361 temperature = <95000>; 6362 hysteresis = <2000>; 6363 type = "passive"; 6364 }; 6365 6366 cpu8_crit: cpu-crit { 6367 temperature = <110000>; 6368 hysteresis = <0>; 6369 type = "critical"; 6370 }; 6371 }; 6372 6373 cooling-maps { 6374 map0 { 6375 trip = <&cpu8_alert0>; 6376 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6377 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6378 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6379 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6380 }; 6381 map1 { 6382 trip = <&cpu8_alert1>; 6383 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6384 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6385 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6386 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6387 }; 6388 }; 6389 }; 6390 6391 cpu9-thermal { 6392 polling-delay-passive = <250>; 6393 polling-delay = <0>; 6394 6395 thermal-sensors = <&tsens0 12>; 6396 6397 trips { 6398 cpu9_alert0: trip-point0 { 6399 temperature = <90000>; 6400 hysteresis = <2000>; 6401 type = "passive"; 6402 }; 6403 6404 cpu9_alert1: trip-point1 { 6405 temperature = <95000>; 6406 hysteresis = <2000>; 6407 type = "passive"; 6408 }; 6409 6410 cpu9_crit: cpu-crit { 6411 temperature = <110000>; 6412 hysteresis = <0>; 6413 type = "critical"; 6414 }; 6415 }; 6416 6417 cooling-maps { 6418 map0 { 6419 trip = <&cpu9_alert0>; 6420 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6421 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6422 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6423 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6424 }; 6425 map1 { 6426 trip = <&cpu9_alert1>; 6427 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6428 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6429 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6430 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6431 }; 6432 }; 6433 }; 6434 6435 cpu10-thermal { 6436 polling-delay-passive = <250>; 6437 polling-delay = <0>; 6438 6439 thermal-sensors = <&tsens0 13>; 6440 6441 trips { 6442 cpu10_alert0: trip-point0 { 6443 temperature = <90000>; 6444 hysteresis = <2000>; 6445 type = "passive"; 6446 }; 6447 6448 cpu10_alert1: trip-point1 { 6449 temperature = <95000>; 6450 hysteresis = <2000>; 6451 type = "passive"; 6452 }; 6453 6454 cpu10_crit: cpu-crit { 6455 temperature = <110000>; 6456 hysteresis = <0>; 6457 type = "critical"; 6458 }; 6459 }; 6460 6461 cooling-maps { 6462 map0 { 6463 trip = <&cpu10_alert0>; 6464 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6465 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6466 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6467 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6468 }; 6469 map1 { 6470 trip = <&cpu10_alert1>; 6471 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6472 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6473 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6474 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6475 }; 6476 }; 6477 }; 6478 6479 cpu11-thermal { 6480 polling-delay-passive = <250>; 6481 polling-delay = <0>; 6482 6483 thermal-sensors = <&tsens0 14>; 6484 6485 trips { 6486 cpu11_alert0: trip-point0 { 6487 temperature = <90000>; 6488 hysteresis = <2000>; 6489 type = "passive"; 6490 }; 6491 6492 cpu11_alert1: trip-point1 { 6493 temperature = <95000>; 6494 hysteresis = <2000>; 6495 type = "passive"; 6496 }; 6497 6498 cpu11_crit: cpu-crit { 6499 temperature = <110000>; 6500 hysteresis = <0>; 6501 type = "critical"; 6502 }; 6503 }; 6504 6505 cooling-maps { 6506 map0 { 6507 trip = <&cpu11_alert0>; 6508 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6509 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6510 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6511 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6512 }; 6513 map1 { 6514 trip = <&cpu11_alert1>; 6515 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6516 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6517 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6518 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6519 }; 6520 }; 6521 }; 6522 6523 aoss0-thermal { 6524 polling-delay-passive = <0>; 6525 polling-delay = <0>; 6526 6527 thermal-sensors = <&tsens0 0>; 6528 6529 trips { 6530 aoss0_alert0: trip-point0 { 6531 temperature = <90000>; 6532 hysteresis = <2000>; 6533 type = "hot"; 6534 }; 6535 6536 aoss0_crit: aoss0-crit { 6537 temperature = <110000>; 6538 hysteresis = <0>; 6539 type = "critical"; 6540 }; 6541 }; 6542 }; 6543 6544 aoss1-thermal { 6545 polling-delay-passive = <0>; 6546 polling-delay = <0>; 6547 6548 thermal-sensors = <&tsens1 0>; 6549 6550 trips { 6551 aoss1_alert0: trip-point0 { 6552 temperature = <90000>; 6553 hysteresis = <2000>; 6554 type = "hot"; 6555 }; 6556 6557 aoss1_crit: aoss1-crit { 6558 temperature = <110000>; 6559 hysteresis = <0>; 6560 type = "critical"; 6561 }; 6562 }; 6563 }; 6564 6565 cpuss0-thermal { 6566 polling-delay-passive = <0>; 6567 polling-delay = <0>; 6568 6569 thermal-sensors = <&tsens0 5>; 6570 6571 trips { 6572 cpuss0_alert0: trip-point0 { 6573 temperature = <90000>; 6574 hysteresis = <2000>; 6575 type = "hot"; 6576 }; 6577 cpuss0_crit: cluster0-crit { 6578 temperature = <110000>; 6579 hysteresis = <0>; 6580 type = "critical"; 6581 }; 6582 }; 6583 }; 6584 6585 cpuss1-thermal { 6586 polling-delay-passive = <0>; 6587 polling-delay = <0>; 6588 6589 thermal-sensors = <&tsens0 6>; 6590 6591 trips { 6592 cpuss1_alert0: trip-point0 { 6593 temperature = <90000>; 6594 hysteresis = <2000>; 6595 type = "hot"; 6596 }; 6597 cpuss1_crit: cluster0-crit { 6598 temperature = <110000>; 6599 hysteresis = <0>; 6600 type = "critical"; 6601 }; 6602 }; 6603 }; 6604 6605 gpuss0-thermal { 6606 polling-delay-passive = <100>; 6607 polling-delay = <0>; 6608 6609 thermal-sensors = <&tsens1 1>; 6610 6611 trips { 6612 gpuss0_alert0: trip-point0 { 6613 temperature = <95000>; 6614 hysteresis = <2000>; 6615 type = "passive"; 6616 }; 6617 6618 gpuss0_crit: gpuss0-crit { 6619 temperature = <110000>; 6620 hysteresis = <0>; 6621 type = "critical"; 6622 }; 6623 }; 6624 6625 cooling-maps { 6626 map0 { 6627 trip = <&gpuss0_alert0>; 6628 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6629 }; 6630 }; 6631 }; 6632 6633 gpuss1-thermal { 6634 polling-delay-passive = <100>; 6635 polling-delay = <0>; 6636 6637 thermal-sensors = <&tsens1 2>; 6638 6639 trips { 6640 gpuss1_alert0: trip-point0 { 6641 temperature = <95000>; 6642 hysteresis = <2000>; 6643 type = "passive"; 6644 }; 6645 6646 gpuss1_crit: gpuss1-crit { 6647 temperature = <110000>; 6648 hysteresis = <0>; 6649 type = "critical"; 6650 }; 6651 }; 6652 6653 cooling-maps { 6654 map0 { 6655 trip = <&gpuss1_alert0>; 6656 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6657 }; 6658 }; 6659 }; 6660 6661 nspss0-thermal { 6662 polling-delay-passive = <0>; 6663 polling-delay = <0>; 6664 6665 thermal-sensors = <&tsens1 3>; 6666 6667 trips { 6668 nspss0_alert0: trip-point0 { 6669 temperature = <90000>; 6670 hysteresis = <2000>; 6671 type = "hot"; 6672 }; 6673 6674 nspss0_crit: nspss0-crit { 6675 temperature = <110000>; 6676 hysteresis = <0>; 6677 type = "critical"; 6678 }; 6679 }; 6680 }; 6681 6682 nspss1-thermal { 6683 polling-delay-passive = <0>; 6684 polling-delay = <0>; 6685 6686 thermal-sensors = <&tsens1 4>; 6687 6688 trips { 6689 nspss1_alert0: trip-point0 { 6690 temperature = <90000>; 6691 hysteresis = <2000>; 6692 type = "hot"; 6693 }; 6694 6695 nspss1_crit: nspss1-crit { 6696 temperature = <110000>; 6697 hysteresis = <0>; 6698 type = "critical"; 6699 }; 6700 }; 6701 }; 6702 6703 video-thermal { 6704 polling-delay-passive = <0>; 6705 polling-delay = <0>; 6706 6707 thermal-sensors = <&tsens1 5>; 6708 6709 trips { 6710 video_alert0: trip-point0 { 6711 temperature = <90000>; 6712 hysteresis = <2000>; 6713 type = "hot"; 6714 }; 6715 6716 video_crit: video-crit { 6717 temperature = <110000>; 6718 hysteresis = <0>; 6719 type = "critical"; 6720 }; 6721 }; 6722 }; 6723 6724 ddr-thermal { 6725 polling-delay-passive = <0>; 6726 polling-delay = <0>; 6727 6728 thermal-sensors = <&tsens1 6>; 6729 6730 trips { 6731 ddr_alert0: trip-point0 { 6732 temperature = <90000>; 6733 hysteresis = <2000>; 6734 type = "hot"; 6735 }; 6736 6737 ddr_crit: ddr-crit { 6738 temperature = <110000>; 6739 hysteresis = <0>; 6740 type = "critical"; 6741 }; 6742 }; 6743 }; 6744 6745 mdmss0-thermal { 6746 polling-delay-passive = <0>; 6747 polling-delay = <0>; 6748 6749 thermal-sensors = <&tsens1 7>; 6750 6751 trips { 6752 mdmss0_alert0: trip-point0 { 6753 temperature = <90000>; 6754 hysteresis = <2000>; 6755 type = "hot"; 6756 }; 6757 6758 mdmss0_crit: mdmss0-crit { 6759 temperature = <110000>; 6760 hysteresis = <0>; 6761 type = "critical"; 6762 }; 6763 }; 6764 }; 6765 6766 mdmss1-thermal { 6767 polling-delay-passive = <0>; 6768 polling-delay = <0>; 6769 6770 thermal-sensors = <&tsens1 8>; 6771 6772 trips { 6773 mdmss1_alert0: trip-point0 { 6774 temperature = <90000>; 6775 hysteresis = <2000>; 6776 type = "hot"; 6777 }; 6778 6779 mdmss1_crit: mdmss1-crit { 6780 temperature = <110000>; 6781 hysteresis = <0>; 6782 type = "critical"; 6783 }; 6784 }; 6785 }; 6786 6787 mdmss2-thermal { 6788 polling-delay-passive = <0>; 6789 polling-delay = <0>; 6790 6791 thermal-sensors = <&tsens1 9>; 6792 6793 trips { 6794 mdmss2_alert0: trip-point0 { 6795 temperature = <90000>; 6796 hysteresis = <2000>; 6797 type = "hot"; 6798 }; 6799 6800 mdmss2_crit: mdmss2-crit { 6801 temperature = <110000>; 6802 hysteresis = <0>; 6803 type = "critical"; 6804 }; 6805 }; 6806 }; 6807 6808 mdmss3-thermal { 6809 polling-delay-passive = <0>; 6810 polling-delay = <0>; 6811 6812 thermal-sensors = <&tsens1 10>; 6813 6814 trips { 6815 mdmss3_alert0: trip-point0 { 6816 temperature = <90000>; 6817 hysteresis = <2000>; 6818 type = "hot"; 6819 }; 6820 6821 mdmss3_crit: mdmss3-crit { 6822 temperature = <110000>; 6823 hysteresis = <0>; 6824 type = "critical"; 6825 }; 6826 }; 6827 }; 6828 6829 camera0-thermal { 6830 polling-delay-passive = <0>; 6831 polling-delay = <0>; 6832 6833 thermal-sensors = <&tsens1 11>; 6834 6835 trips { 6836 camera0_alert0: trip-point0 { 6837 temperature = <90000>; 6838 hysteresis = <2000>; 6839 type = "hot"; 6840 }; 6841 6842 camera0_crit: camera0-crit { 6843 temperature = <110000>; 6844 hysteresis = <0>; 6845 type = "critical"; 6846 }; 6847 }; 6848 }; 6849 }; 6850 6851 timer { 6852 compatible = "arm,armv8-timer"; 6853 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6854 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6855 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6856 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6857 }; 6858}; 6859