1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sc7280 fragment for devices with Chrome bootloader 4 * 5 * This file mainly tries to abstract out the memory protections put into 6 * place by the Chrome bootloader which are different than what's put into 7 * place by Qualcomm's typical bootloader. It also has a smattering of other 8 * things that will hold true for any conceivable Chrome design 9 * 10 * Copyright 2022 Google LLC. 11 */ 12 13/* 14 * Reserved memory changes 15 * 16 * Delete all unused memory nodes and define the peripheral memory regions 17 * required by the setup for Chrome boards. 18 */ 19 20/delete-node/ &cdsp_mem; 21/delete-node/ &domain_idle_states; 22/delete-node/ &gpu_zap_mem; 23/delete-node/ &gpu_zap_shader; 24/delete-node/ &hyp_mem; 25/delete-node/ &xbl_mem; 26/delete-node/ &reserved_xbl_uefi_log; 27/delete-node/ &sec_apps_mem; 28 29/ { 30 cpus { 31 domain_idle_states: domain-idle-states { 32 cluster_sleep_0: cluster-sleep-0 { 33 compatible = "domain-idle-state"; 34 arm,psci-suspend-param = <0x40003444>; 35 entry-latency-us = <2752>; 36 exit-latency-us = <6562>; 37 min-residency-us = <9926>; 38 }; 39 }; 40 }; 41 42 reserved-memory { 43 camera_mem: memory@8ad00000 { 44 reg = <0x0 0x8ad00000 0x0 0x500000>; 45 no-map; 46 }; 47 48 venus_mem: memory@8b200000 { 49 reg = <0x0 0x8b200000 0x0 0x500000>; 50 no-map; 51 }; 52 }; 53}; 54 55&cluster_pd { 56 domain-idle-states = <&cluster_sleep_0>; 57}; 58 59&gpu { 60 status = "okay"; 61}; 62 63&lpass_aon { 64 status = "okay"; 65}; 66 67&lpass_core { 68 status = "okay"; 69}; 70 71&lpass_hm { 72 status = "okay"; 73}; 74 75&lpasscc { 76 status = "okay"; 77}; 78 79&pdc_reset { 80 status = "okay"; 81}; 82 83/* The PMIC PON code isn't compatible w/ how Chrome EC/BIOS handle things. */ 84&pmk8350_pon { 85 status = "disabled"; 86}; 87 88/* 89 * Chrome designs always boot from SPI flash hooked up to the qspi. 90 * 91 * It's expected that all boards will support "dual SPI" at 37.5 MHz. 92 * If some boards need a different speed or have a package that allows 93 * Quad SPI together with WP then those boards can easily override. 94 */ 95&qspi { 96 status = "okay"; 97 pinctrl-names = "default", "sleep"; 98 pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, <&qspi_data1>; 99 pinctrl-1 = <&qspi_sleep>; 100 101 spi_flash: flash@0 { 102 compatible = "jedec,spi-nor"; 103 reg = <0>; 104 105 spi-max-frequency = <37500000>; 106 spi-tx-bus-width = <2>; 107 spi-rx-bus-width = <2>; 108 }; 109}; 110 111/* Currently not used */ 112&remoteproc_cdsp { 113 /delete-property/ memory-region; 114}; 115 116&remoteproc_wpss { 117 compatible = "qcom,sc7280-wpss-pil"; 118 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, 119 <&gcc GCC_WPSS_AHB_CLK>, 120 <&gcc GCC_WPSS_RSCP_CLK>, 121 <&rpmhcc RPMH_CXO_CLK>; 122 clock-names = "ahb_bdg", 123 "ahb", 124 "rscp", 125 "xo"; 126 127 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, 128 <&pdc_reset PDC_WPSS_SYNC_RESET>; 129 reset-names = "restart", "pdc_sync"; 130 131 qcom,halt-regs = <&tcsr_1 0x17000>; 132 133 firmware-name = "ath11k/WCN6750/hw1.0/wpss.mdt"; 134 135 status = "okay"; 136}; 137 138&scm { 139 /* TF-A firmware maps memory cached so mark dma-coherent to match. */ 140 dma-coherent; 141}; 142 143&venus { 144 iommus = <&apps_smmu 0x2180 0x20>, 145 <&apps_smmu 0x2184 0x20>; 146 147 status = "okay"; 148 149 video-firmware { 150 iommus = <&apps_smmu 0x21a2 0x0>; 151 }; 152}; 153 154&watchdog { 155 status = "okay"; 156}; 157 158&wifi { 159 status = "okay"; 160 161 wifi-firmware { 162 iommus = <&apps_smmu 0x1c02 0x1>; 163 }; 164}; 165 166/* PINCTRL - chrome-common pinctrl */ 167 168&tlmm { 169 qspi_sleep: qspi-sleep-state { 170 pins = "gpio12", "gpio13", "gpio14", "gpio15"; 171 172 /* 173 * When we're not actively transferring we want pins as GPIOs 174 * with output disabled so that the quad SPI IP block stops 175 * driving them. We rely on the normal pulls configured in 176 * the active state and don't redefine them here. Also note 177 * that we don't need the reverse (output-enable) in the 178 * normal mode since the "output-enable" only matters for 179 * GPIO function. 180 */ 181 function = "gpio"; 182 output-disable; 183 }; 184}; 185